XTR110 SBOS141C – JANUARY 1984 – REVISED SEPTEMBER 2009 PRECISION VOLTAGE-TO-CURRENT CONVERTER/TRANSMITTER FEATURES APPLICATIONS (cid:1) 4mA TO 20mA TRANSMITTER (cid:1) INDUSTRIAL PROCESS CONTROL (cid:1) SELECTABLE INPUT/OUTPUT RANGES: (cid:1) PRESSURE/TEMPERATURE TRANSMITTERS 0V to +5V, 0V to +10V Inputs (cid:1) CURRENT-MODE BRIDGE EXCITATION 0mA to 20mA, 5mA to 25mA Outputs (cid:1) GROUNDED TRANSDUCER CIRCUITS Other Ranges (cid:1) CURRENT SOURCE REFERENCE FOR DATA (cid:1) 0.005% MAX NONLINEARITY, 14 BIT ACQUISITION (cid:1) PRECISION +10V REFERENCE OUTPUT (cid:1) PROGRAMMABLE CURRENT SOURCE FOR (cid:1) SINGLE-SUPPLY OPERATION TEST EQUIPMENT (cid:1) WIDE SUPPLY RANGE: 13.5V to 40V (cid:1) POWER PLANT/ENERGY SYSTEM MONITORING DESCRIPTION The XTR110 is a precision voltage-to-current converter designed for analog signal transmission. It accepts inputs V Force 15 16 +V of 0 to 5V or 0 to 10V and can be connected for outputs of REF CC R 9 4mA to 20mA, 0mA to 20mA, 5mA to 25mA, and many other VREF Sense 12 Re+fe1r0eVnce R8 1 SRoeusirscteo r commonly used ranges. V Adjust 11 13 Source REF Sense A precision on-chip metal film resistor network provides input scaling and current offsetting. An internal 10V voltage refer- VIN1 (10V) 4 A2 14 GDraivtee ence can be used to drive external circuitry. VREF In 3 R1 7 Offset R (zero) The XTR110 is available in 16-pin plastic DIP, ceramic DIP R5 3 6 Adjust and SOL-16 surface-mount packages. Commercial and in- R4 A1 dustrial temperature range models are available. R 2 Span 8 Adjust R 7 V (5V) 5 10 4mA IN2 Span R Common 2 6 9 16mA Span Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 1984-2009, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Power Supply, +V ............................................................................40V DISCHARGE SENSITIVITY CC Input Voltage, V , V , V .......................................................+V IN1 IN2 REF IN CC See text regarding safe negative input voltage range. Storage Temperature Range:A, B................................–55°C to +125°C This integrated circuit can be damaged by ESD. Texas Instruments K, U..................................–40°C to +85°C recommends that all integrated circuits be handled with appropriate Output Short-Circuit Duration, Gate Drive precautions. Failure to observe proper handling and installation proce- and V Force................................Continuous to common and +V dures can cause damage. REF CC Output Current Using Internal 50Ω Resistor...................................40mA ESD damage can range from subtle performance degradation to NOTE: (1) Stresses above these ratings may cause permanent damage. complete device failure. Precision integrated circuits may be more Exposure to absolute maximum conditions for extended periods may degrade susceptible to damage because very small parametric changes could device reliability. cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PACKAGE TEMPERATURE PRODUCT PACKAGE-LEAD DESIGNATOR RANGE XTR110AG DIP-16 Ceramic JD –40°C to +85°C XTR110BG DIP-16 Ceramic JD –40°C to +85°C XTR110KP DIP-16 Plastic N 0°C to +70°C XTR110KU SOL-16 Surface-Mount DW 0°C to +70°C NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN CONFIGURATION TOP VIEW Source Resistor 1 16 +V CC Common 2 15 V Force REF V In 3 14 Gate Drive REF V (10V) 4 13 Source Sense IN1 V (5V) 5 12 V Sense IN2 REF Zero Adjust 6 11 V Adjust REF Zero Adjust 7 10 4mA Span Span Adjust 8 9 16mA Span XTR110 2 www.ti.com SBOS141C

ELECTRICAL CHARACTERISTICS At T = +25°C and V = +24V and R = 250Ω**, unless otherwise specified. A CC L XTR110AG, KP, KU XTR110BG PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS TRANSMITTER Transfer Function I = 10 [(V In/16) + (V /4) + (V /2)] /R O REF IN1 IN2 SPAN Input Range: V (5) Specified Performance 0 +10 * * V IN1 V Specified Performance 0 +5 * * V IN2 Current, I Specified Performance(1) 4 20 * * mA O Derated Performance(1) 0 40 * * mA Nonlinearity 16mA/20mA Span(2) 0.01 0.025 0.002 0.005 % of Span Offset Current, I I = 4mA(1) OS O Initial (1) 0.2 0.4 0.02 0.1 % of Span vs Temperature (1) 0.0003 0.005 * 0.003 % of Span/°C vs Supply, V (1) 0.0005 0.005 * * % of Span/V CC Span Error I = 20mA O Initial (1) 0.3 0.6 0.05 0.2 % of Span vs Temperature (1) 0.0025 0.005 0.0009 0.003 % of Span/°C vs Supply, V (1) 0.003 0.005 * * % of Span/V CC Output Resistance From Drain of FET (Q )(3) 10 x 109 * Ω EXT Input Resistance V 27 * kΩ IN1 V 22 * kΩ IN2 V In 19 * kΩ REF Dynamic Response Settling Time To 0.1% of Span 15 * µs To 0.01% of Span 20 * µs Slew Rate 1.3 * mA/µs VOLTAGE REFERENCE Output Voltage +9.95 +10 +10.05 +9.98 * +10.02 V vs Temperature 35 50 15 30 ppm/°C vs Supply, V Line Regulation 0.0002 0.005 * * %/V CC vs Output Current Load Regulation 0.0005 0.01 * * %/mA vs Time 100 * ppm/1k hrs Trim Range –0.100 +0.25 * * V Output Current Specified Performance 10 * mA POWER SUPPLY Input Voltage, V +13.5 +40 * * V CC Quiescent Current Excluding I 3 4.5 * * mA O TEMPERATURE RANGE Specification:AG, BG –40 +85 * * °C KP, KU 0 +70 °C Operating:AG, BG –55 +125 * * °C KP, KU –25 +85 °C * Specifications same as AG/KP grades. ** Specifications apply to the range of R shown in Typical Performance Curves. L NOTES: (1) Including internal reference. (2) Span is the change in output current resulting from a full-scale change in input voltage. (3) Within compliance range limited by (+V – 2V) +V required for linear operation of the FET. (4) For V adjustment circuit see Figure 3. (5) For extended I drive circuit see Figure 4. (5) Unit may CC DS REF REF be damaged. See Input Voltage Range section. XTR110 3 SBOS141C www.ti.com

TYPICAL PERFORMANCE CURVES T = +25°C, V = 24VDC, R = 250Ω, unless otherwise noted. A CC L VREF LINE REGULATION vs FREQUENCY IO POWER SUPPLY REGULATION vs FREQUENCY 10 10 V) 1 n/V) 1 %/ pa ∆/ V (REFCC 0.1 V (% of sCC 0.1 ∆ V 0.01 ∆∆ I/ O 0.01 0.001 0.001 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k Ripple Frequency (Hz) Ripple Frequency (Hz) JUNCTION TEMPERATURE RISE vs V OUTPUT CURRENT TOTAL OUTPUT ERROR vs TEMPERATURE REF 100 2 Max. Temp. Rise for +85°C Ambient mperature Rise°mbient (C) 8600 MθJaA x=. T70J °=C +/W175°C VCC = +40V % of span) 10 BAGG nction TeAbove A 40 VCC = +24V Error ( –1 AG Ju 20 VCC = +15V 0 –2 0 2 4 6 8 10 –40 –20 0 20 40 60 80 V Output Current (mA) Temperature (°C) REF (I has minimal effect on T) OUT J ICC vs TEMPERATURE MAXIMUM RL vs VCC 5 2500 I = 20mA O 4 2000 )O g I I = 20mA n O MAX udi 3 1500 A) (excl 2 IO = 4mA ΩR()L 1000 m I = 40mA (C O MAX C I 1 500 0 0 –40 –20 0 20 40 60 80 15 20 25 30 35 40 Temperature (°C) +V (V) CC XTR110 4 www.ti.com SBOS141C

TYPICAL PERFORMANCE CURVES (Continued) At T = +25°C, V = 24VDC, R = 250Ω, unless otherwise noted. A CC L SETTLING TIME WITH NEG V STEP PULSE RESPONSE IN V V IN IN 0V 0V 0V I Error I O O (0.01% of into Span/Box) 500Ω 0V SETTLING TIME WITH POS V STEP IN V IN 0V 0V I Error O (0.01% of Span/Box) XTR110 5 SBOS141C www.ti.com

APPLICATIONS INFORMATION have a voltage rating equal or greater than the maximum power supply voltage. Various recommended types are shown Figure 1 shows the basic connections required for 0V to 10V in Table I. input and 4ma to 20mA output. Other input voltage and output current ranges require changes in connections of pins MANUFACTURER PART NO. BV (1) BV (1) PACKAGE DSS GS 3, 4, 5, 9 and 10 as shown in the table of Figure 1. Ferranti ZVP1304A 40V 20V TO-92 The complete transfer function of the XTR110 is: ZVP1304B 40V 20V TO-39 ZVP1306A 60V 20V TO-92 (V ) (V ) (V ) ZVP1306B 60V 20V TO-39 REF IN IN1 IN2 10 + + International 16 4 2 Rectifier IRF9513 60V 20V TO-220 I = (1) O R Motorola MTP8P08 80V 20V TO-220 SPAN RCA RFL1P08 80V 20V TO-39 R is the total impedance seen at the emitter of the RFT2P08 80V 20V TO-220 SPAN internal NPN transistor. This impedance varies depending Siliconix VP0300B 30V 40V TO-39 (preferred) VP0300L 30V 40V TO-92 on how pins 8, 9 and 10 are configured. Typical operating VP0300M 30V 40V TO-237 region configurations are shown in Figure 1. An external VP0808B 80V 40V TO-39 R can be connected for different output current ranges VP0808L 80V 40V TO-92 SPAN VP0808M 80V 40V TO-237 as described later. Supertex VP1304N2 40V 20V TO-220 VP1304N3 40V 20V TO-92 EXTERNAL TRANSISTOR VP1306N2 60V 20V TO-220 VP1306N3 60V 20V TO-92 An external pass transistor, Q , is required as shown in EXT NOTE: (1) BV —Drain-source breakdown voltage. BV —Gate-source DSS GS Figure 1. This transistor conducts the output signal current. breakdown voltage. A P-channel MOSFET transistor is recommended. It must TABLE I. Available P-Channel MOSFETs. +VCC +1µF +V CC Force15 16 13.5 to 40V R 50Ω Sense12 +10V R8 9 1 IO Reference 500Ω Short VREF 11 13 Connection Adj. (see text) 4 14 Q EXT VIN IO/10 P-Channel 0 to 10V 3 15kΩ 7 MOSFET R Zero (see text) R1 R5 203kΩ 6 Adjust 16.25kΩ I O R 4 to 20mA R2 5kΩ 104kΩ R(2L50Ω typ) 8 Span Adjust R 6250Ω 5 IO/10 7 10 4mA Span 2 9 16mA Span R 1562.5Ω 6 INPUT OUTPUT RANGE (V) RANGE (mA) PIN 3 PIN 4 PIN 5 PIN 9 PIN 10 0-10 0-20 Com Input Com Com Com 2-10 4-20 Com Input Com Com Com 0-10 4-20 +10V Ref Input Com Com Open 0-10 5-25 +10V Ref Input Com Com Com 0-5 0-20 Com Com Input Com Com 1-5 4-20 Com Com Input Com Com 0-5 4-20 +10V Ref Com Input Com Open 0-5 5-25 +10V Ref Com Input Com Com FIGURE 1. Basic Circuit Connection. XTR110 6 www.ti.com SBOS141C

If the supply voltage, +V , exceeds the gate-to-source CC breakdown voltage of Q , and the output connection +VCC EXT (drain of Q ) is broken, Q could fail. If the gate-to- EXT EXT 16 source breakdown voltage is lower than +VCC, QEXT can be 1 47nF protected with a 12V zener diode connected from gate to source. XTR110 13 TIP30B etc. 14 Two PNP discrete transistors (Darlington-connected) can be 0.047µF used for QEXT—see Figure 2. Note that an additional capaci- 2 tor is required for stability. Integrated Darlington transistors 2N2907 I are not recommended because their internal base-emitter etc. OUT resistors cause excessive error. R L Common TRANSISTOR DISSIPATION Maximum power dissipation of Q depends on the power EXT FIGURE 2. Q Using PNP Transistors. supply voltage and full-scale output current. Assuming that EXT the load resistance is low, the power dissipated by Q is: EXT P = (+V ) I (2) MAX CC FS +V CC The transistor type and heat sinking must be chosen accord- VREF Force 15 ing to the maximum power dissipation to prevent overheat- 16 ing. See Table II for general recommendations. VREF Sense 12 V Adjust REF VREF 11 XTR110 PACKAGE TYPE ALLOWABLE POWER DISSIPATION 20RkΩ RS(1) TO-92 Lowest: Use minimum supply and at +25°C. Adjust Range 2 Common TO-237 Acceptable: Trade-off supply and temperature. ±5% Optimum TO-39 Good: Adequate for majority of designs. TO-220 Excellent: For prolonged maximum stress. TO-3 Use if hermetic package is required. NOTE: (1) R gives higher resolution with reduced TABLE II. External Transistor Package Type and range, set RS = 0Ω for larger range. S Dissipation. FIGURE 3. Optional Adjustment of Reference Voltage. INPUT VOLTAGE RANGE The internal op amp A can be damaged if its non-inverting 1 input (an internal node) is pulled more than 0.5V below common (0V). This could occur if input pins 3, 4 or 5 were driven with an op amp whose output could swing negative Q Force 15 REF under abnormal conditions. The voltage at the input of A1 is: Sense 12 16 +VCC (V ) (V ) (V ) +10VREF XTR110 REF IN IN1 IN2 V = + + (3) A1 16 4 2 2 This voltage should not be allowed to go more negative than –0.5V. If necessary, a clamp diode can be connected from For 100mA with V up to the negative-going input to common to clamp the input CC 40V use 2N3055 for Q . REF voltage. FIGURE 4. Increasing Reference Current Drive. COMMON (Ground) Careful attention should be directed toward proper con- 3 should be connected to this point. The circuit in Figure 3 nection of the common (grounds). All commons should shows adjustment of the voltage reference. be joined at one point as close to pin 2 of the XTR110 as The current drive capability of the XTR110’s internal refer- possible. The exception is the I return. It can be OUT ence is 10mA. This can be extended if desired by adding an returned to any point where it will not modulate the external NPN transistor shown in Figure 4. common at pin 2. OFFSET (ZERO) ADJUSTMENT VOLTAGE REFERENCE The offset current can be adjusted by using the potentiom- The reference voltage is accurately regulated at pin 12 eter, R , shown in Figure 5. Set the input voltage to zero and (V ). To preserve accuracy, any load including pin 1 REFSENSE then adjust R to give 4mA at the output. For spans starting 1 XTR110 7 SBOS141C www.ti.com

15 1µF Tantalum 20 RR12 == 110000kkΩΩ 12 16 1 2T4hVird W+ire (mA)O 15 RR34 == 4391..96ΩkΩ 13 S – nt, I Span Adjust ±0.45% 3 e 16mA Span XTR110 urr as shown C 4 14 G put 10 ut O 0V 5 7 8 9 2 D 5 Zero Adjust ±1.8% of Span to 6 4mA to +10V R 4 20mA Out 1V 4mA Offset to R1 R3 25R0LΩ +O5uVt −2.5 0 2 4 6 8 10 Input Voltage, V (V) IN1 R 2 Offset FIGURE 6. Zero and Span of 0V to +10V Input, 4mA to Adjust Span Adjust 20mA Output Configuration (see Figure 5). FIGURE 5. Offset and Span Adjustment Circuit for 0V to +10V Input, 4mA to 20mA Output. 20 See values in Figure 6. at 0mA, the following special procedure is recommended: mA) In addition, connect stheet tphreo pinepr uotu ttop uat scmurarlel nnto. nWzehreon vthaleu ien panudt itsh zeenr oad tjhues to Rut1p tuot ent, I (O 15 pins 9 and 10 together. will be zero. Figures 6 and 7 show graphically how offset is Curr 20mA Span Span Adjust adjusted. put 10 ut O SPAN ADJUSTMENT 5 The span is adjusted at the full-scale output current using the Zero Adjust potentiometer, R , shown in Figure 5. This adjustment is 2 0mA Offset interactive with the offset adjustment, and a few iterations may be necessary. For the circuit shown, set the input 0 2 4 6 8 10 voltage to +10V full scale and adjust R to give 20mA full- Input Voltage, VIN1 (V) 2 scale output. Figures 6 and 7 show graphically how span is adjusted. FIGURE 7. Zero and Span of 0V to +10V , 0mA to 20mA IN Output Configuration (see Figure 5). The values of R , R , and R for adjusting the span are 2 3 4 determined as follows: choose R in series to slightly de- 4 crease the span; then choose R and R to increase the span 2 3 to be adjustable about the center value. EXTENDED SPAN For spans beyond 40mA, the internal 50Ω resistor (R ) may LOW TEMPERATURE COEFFICIENT OPERATION 9 be replaced by an external resistor connected between pins Although the precision resistors in the XTR110 track within 13 and 16. 1ppm/°C, the output current depends upon the absolute Its value can be calculated as follows: temperature coefficient (TC) of any one of the resistors, R , 6 R , R , and R . Since the absolute TC of the output current R = R (Span /Span ) 7 8 9 EXT 9 OLD NEW can have 20ppm/°C, maximum, the TC of the output current Since the internal thin-film resistors have a 20% absolute can have 20ppm/°C drift. For low TC operation, zero TC value tolerance, measure R before determining the final 9 resistors can be substituted for either the span resistors (R6 value of REXT. Self-heating of REXT can cause nonlinearity. or R7) or for the source resistor (R9) but not both. Therefore, choose one with a low TC and adequate power rating. See Figure 10 for application. XTR110 8 www.ti.com SBOS141C

TYPICAL APPLICATIONS The XTR110 is ideal for a variety of applications requiring and low price of the XTR110 allow versatility with a high noise immunity current-mode signal transmission. The minimum of external components and design engineering precision +10V reference can be used to excite bridges and expense. transducers. Selectable ranges make it very useful as a Figures 8 through 10 show typical applications of the precision programmable current source. The compact design XTR110. +15V 15 16 12 1 R +10V 1 2Ω Reference 11 13 V IN 4 14 A T 4 1 3 7 R 6 9 15kΩ R 1k1Ω0 8 Offset R Adjust 5 10 4.775kΩ A 3 R 2 9 R8 200Ω 203kΩ Fine Trim Span 2MRΩ5 R RH 50kΩ Adjust 6 Coarse Trim 402Ω T3 A2 IO A T 1 2 R 4 2kΩ R 2 4.99Ω –15V 200 IO (mA) R1, R2: Low TC resistors to dissipate 0.32W continuous power. For other current ranges, scale both resistors proportionately. R, R , R : 10-turn trimpots for greatest sensitivity. 8 10 11 R, R: Low TC resistors. 6 7 V (V) A - A: 1/4 LM324 (powered by ±15V). 0 IN 1 4 T: International Rectifier IR9513(1). 5 10 T1: International Rectifier IR513(1). 2 T: International Rectifier IRFF9113(1). 3 –200 NOTE: (1) Or other adequate power rating MOS transistor. FIGURE 8. ±200mA Current Pump. XTR110 9 SBOS141C www.ti.com

Isolation Barrier +15V Isolated Power Supply (722) 1µF –15V+15V –15V+15V 15 16 12 1 3 XTR110 13 S 15 ISO122 7 4 14 G 4mA to 20mA Out 0 to –10V16 8 5 9 2 D R L V L FIGURE 9. Isolated 4mA to 20mA Channel. +24V 15 R 16 EXT 0.1Ω 12 13 4 XTR110 0A to 0V to +10V S 3 14 G 10A Out 5 9 2 D See extended span section. FIGURE 10. 0A to 10A Output Voltage-to-Current Converter. XTR110 10 www.ti.com SBOS141C

Revision History DATE REVISION PAGE SECTION DESCRIPTION Front Page Changed front page to standard format. 9/09 C 6 Applications Information Changed text in third paragraph. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. XTR110 11 SBOS141C www.ti.com

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) XTR110AG NRND CDIP SB JD 16 1 Green (RoHS AU N / A for Pkg Type -40 to 85 XTR110AG & no Sb/Br) XTR110BG NRND CDIP SB JD 16 1 Green (RoHS AU N / A for Pkg Type -40 to 85 XTR110BG & no Sb/Br) XTR110KP ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 XTR110KP & no Sb/Br) XTR110KPG4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 XTR110KP & no Sb/Br) XTR110KU ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 XTR110KU & no Sb/Br) XTR110KU/1K ACTIVE SOIC DW 16 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 XTR110KU & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) XTR110KU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) XTR110KU/1K SOIC DW 16 1000 367.0 367.0 38.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated