XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm October 2012 Rev. 1.0.1 GENERAL DESCRIPTION APPLICATIONS The XRP7724 is a quad channel Digital Pulse  Servers Width Modulated (DPWM) Step down (buck)  Base Stations  Switches/Routers controller. A wide 4.75V to 5.5V and 5.5V to  Broadcast Equipment 25V input voltage dual range allows for single supply operation from standard power rails.  Industrial Control Systems  Automatic Test Equipment With integrated FET gate drivers, two LDOs for  Video Surveillance Systems standby power and a 105kHz to 1.23MHz FEATURES independent channel to channel programmable constant operating frequency, the XRP7724  Quad Channel Step-down Controller reduces overall component count and solution  Digital PWM 105kHz-1.23MHz Operations footprint and optimizes conversion efficiencies.  Individual Channel Frequency Selection A selectable digital Pulse Frequency Mode (DPFM) capable of better than 80% efficiency  Patented digital PFM with Ultrasonic mode at light current load and low operating current  Patented Over Sampling Feedback allow for portable and Energy Star compliant  Integrated MOSFET Drivers applications. Each XRP7724 output channel is individually programmable as low as 0.6V with  Programmable 5 coefficient PID control a resolution as fine as 2.5mV, and  4.75V to 25V Input Voltage configurable for precise soft start and soft stop  4.75V-5.5 and 5.5V-25V Input Ranges sequencing, including delay and ramp control.  0.6V to 5.5V Output voltage The XRP7724 operations are fully controlled  SMBus Compliant - I2C Interface via a SMBus-compliant I2C interface allowing for advanced local and/or remote  Full Power Monitoring and Reporting reconfiguration, full performance monitoring  3 x 15V Capable PSIO + 2 x GPIOs and reporting as well as fault handling.  Full Start/Stop Sequencing Support Built-in independent output over voltage, over  Built-in Thermal, Over-Current, UVLO temperature, over-current and under voltage and Output Over-Voltage Protections lockout protections insure safe operation under abnormal operating conditions.  On Board 5V and 3.3V Standby LDOs  On Board Non-volatile Memory The XRP7724 is offered in a RoHS compliant, “green”/halogen free 44-pin TQFN package.  Supported by PowerArchitect™ TYPICAL APPLICATION DIAGRAM Fig. 1: XRP7724 Application Diagram Exar Corporation www.exar.com 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 – Fax. +1 510 668-7001

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS These are stress ratings only and functional operation of Input Voltage Range V ............................... 5.5V to 25V CC the device at these ratings or any other above those Input Voltage Range V = LDO5 ................ 4.75V to 5.5V CC indicated in the operation sections of the specifications VOUT1, 2, 3, 4 ...................................................... 5.5V below is not implied. Exposure to absolute maximum Junction Temperature Range ....................-40°C to 125°C rating conditions for extended periods of time may affect reliability. JEDEC Thermal Resistance θJA ..........................30.2°C/W VCCD, LDO5, LDO3_3, GLx, VOUTx ............. -0.3V to 7.0V ENABLE, 5V_EXT ....................................... -0.3V to 7.0V GPIO0/1, SCL, SDA................................................ 6.0V PSIOs Inputs, BFB .................................................. 18V DVDD, AVDD ........................................................ 2.0V VCC ...................................................................... 28V LX# ............................................................. -1V to 28V BSTx, GHx .................................................... VLXx + 6V Storage Temperature .............................. -65°C to 150°C Power Dissipation ................................ Internally Limited Lead Temperature (Soldering, 10 sec).................... 300°C ESD Rating (HBM - Human Body Model) .................... 2kV ELECTRICAL SPECIFICATIONS Specifications with standard type are for an Operating Junction Temperature of T = 25°C only; limits applying over the full J Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T = 25°C, and are provided for J reference purposes only. Unless otherwise indicated, V = 5.5V to 25V, 5V EXT open. Note that in cases where there is a CC discrepancy in values shown in this section and other sections of the datasheet, the values in the Electrical Specification section shall be deemed correct and supersede the other values. QUIESCENT CURRENT Parameter Min. Typ. Max. Units Conditions VCC Supply Current in SHUTDOWN 10 20 µA EN = 0V, VCC = 12V ENABLE Turn On Threshold 0.82 0.95 V VCC = 12V Enable Rising 10 uA EN=5V ENABLE Pin Leakage Current -10 EN=0V LDO3_3 disabled, all channels disabled VCC Supply Current in STANDBY 440 600 µA GPIOs programmed as inputs VCC=12V,EN = 5V 2 channels on set at 5V, VOUT forced to VCC Supply Current 2ch PFM 3.1 mA 5.1V, no load, non-switching, Ultra-sonic off, VCC=12 V, No I2C activity. 4 channels on set at 5V, VOUT forced to VCC Supply Current 4ch PFM 4.0 mA 5.1V, no load, non-switching, Ultra-sonic off, VCC=12V, No I2C activity. All channels enabled, Fsw=600kHz, gate VCC Supply Current ON 18 mA drivers unloaded, No I2C activity. © 2012 Exar Corporation 2/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm INPUT VOLTAGE RANGE AND UNDERVOLTAGE LOCKOUT Parameter Min. Typ. Max. Units Conditions 5.5 25 V • VCC Range 4.75 5.5 V • With VCC connected to LDO5 VOLTAGE FEEDBACK ACCURACY AND OUTPUT VOLTAGE SET POINT RESOLUTION Parameter Min. Typ. Max. Units Conditions VOUT Regulation Accuracy -5 5 mV 0.6 ≤ VOUT ≤ 1.6V Low Output Range -20 20 mV • 0.6V to 1.6V -7.5 7.5 mV 0.6 ≤ VOUT ≤ 1.6V PWM Operation -22.5 22.5 mV • VCC=LDO5 VOUT Regulation Accuracy -15 15 mV 0.6 ≤ VOUT ≤ 3.2V Mid Output Range -45 45 mV • 0.6V to 3.2V -20 20 mV 0.6 ≤ VOUT ≤ 3.2V PWM Operation -50 50 mV • VCC=LDO5 VOUT Regulation Accuracy -30 30 mV 0.6 ≤ VOUT ≤ 5.5V High Output Range -90 90 mV • 0.6V to 5.5V -40 40 mV 0.6 ≤ VOUT ≤ 4.2V PWM Operation -100 100 mV • VCC=LDO5 VOUT Regulation Range 0.6 5.5 V • Without external divider network 12.5 Low Range VOUT Native Set Point 25 mV Mid Range Resolution 50 High Range 2.5 Low Range VOUT Fine Set Point Resolution1 5 mV Mid Range 10 High Range 120 Low Range VOUT Input Resistance 90 kΩ Mid Range 75 High Range 10 Low Range VOUT Input Resistance in PFM 1 MΩ Mid Range Operation 0.67 High Range -155 157.5 Low Range Power Good and OVP Set Point -310 315 mV Mid Range Range (from set point) -620 630 High Range -5 5 Low Range Power Good and OVP Set Point -10 10 mV Mid Range Accuracy -20 20 High Range BFB Set Point Range 9 16 V BFB Set Point Resolution 1 V BFB Accuracy -0.5 0.5 V Note 1: Fine Set Point Resolution not available in PFM © 2012 Exar Corporation 3/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm CURRENT AND AUX ADC (MONITORING ADCS) Parameter Min. Typ. Max. Units Conditions -3.75 ±1.25 3.75 mV Low Range (≤120mV) Note 2 -10 10 mV • -60mV applied Current Sense Accuracy -5 ±2.5 5 mV High Range (≤280mV) -12.5 +12.5 mV • -150mV Current Sense ADC INL +/-0.4 LSB DNL 0.27 Current Limit Set Point 1.25 mV Low Range (≤120mV) Resolution and Current 2.5 mV High Range (≤280mV) Sense ADC Resolution -120 20 mV Low Range (≤120mV) Current Sense ADC Range -280 40 High Range (≤280mV) 15 Low Range VOUT ADC Resolution 30 mV Mid Range 60 High Range VOUT ADC Accuracy -1 1 LSB VCC ADC Range 4.6 25 V Note 3 UVLO WARN SET 4.4 4.72 V UVLO WARN set point 4.6V, VCC=LDO5 UVLO WARN CLEAR 4.4 4.72 V UVLO WARN set point 4.6V, VCC=LDO5 UVLO FAULT SET (Note 4) 4.2 4.55 V UVLO FAULT set point 4.4V, VCC=LDO5 VCC ADC Resolution 200 mV VCC ADC Accuracy -1 1 LSB Vin <= 20V Die Temp ADC Resolution 5 °C Die Temp ADC Range -44 156 °C Output value is in Kelvin Note 2: Final test limits are ±2.5mV or ±2 LSB Note 3: Although Range of VCC ADC is technically 0V to 25V, below 4.55 the LDO5 hardware UVLO may have tripped. Note 4: This test ensures an UVLO FAULT flag will be given before the LDO5 hardware UVLO trips. LINEAR REGULATORS Parameter Min. Typ. Max. Units Conditions 5.5V ≤ VCC ≤ 25V LDO5 Output Voltage 4.85 5.0 5.15 V • 0mA < I < 130mA, LDO3_3 Off LDO5OUT LDO5 Current Limit 135 155 180 mA • LDO5 Fault Set LDO5 UVLO 4.74 V • VCC Rising LDO5 PGOOD Hysteresis 375 mV VCC Falling LDO5 Bypass Switch Resistance 1.1 1.5 Ω Bypass Switch Activation 2.5 2.5 % • V5EXT Rising, % of threshold setting Threshold Bypass Switch Activation 150 mV V5EXT Falling Hysteresis 4.6V ≤ LDO5 ≤ 5.5V LDO3_3 Output Voltage 3.15 3.3 3.45 V • 0mA < I < 50mA LDO3_3OUT LDO3_3 Current Limit 53 85 mA • LDO3_3 Fault Set ENABLE transition from logic low to Maximum total LDO loading 30 mA high. Once LDO5 in regulation above during ENABLE start-up limits apply. © 2012 Exar Corporation 4/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm PWM GENERATORS AND OSCILLATOR Parameter Min. Typ. Max. Units Conditions Switching Frequency (fsw) 105 1230 kHz Steps defined in table Range fsw Accuracy –5 5 % CLOCK IN When synchronizing to an external clock 20 25.7 31 MHz Synchronization Frequency (Range 1) CLOCK IN When synchronizing to an external clock 10 12.8 15.5 MHz Synchronization Frequency (Range 2) GPIOS5 Parameter Min. Typ. Max. Units Conditions Input Pin Low Level 0.8 V Input Pin High Level 2.0 V Input Pin Leakage Current 1 µA Output Pin Low Level 0.4 V ISINK = 1mA Output Pin High Level 2.4 V ISOURCE = 1mA Output Pin High Level 3.3 3.6 V ISOURCE = 0mA Output Pin High-Z leakage 10 µA Current (GPIO pins only) Maximum Sink Current 1 mA Open Drain Mode I/O Frequency 30 MHz Note 5: 3.3V CMOS logic compatible, 5V tolerant. PSIOS6 Parameter Min. Typ. Max. Units Conditions Input Pin Low Level 0.8 V Input Pin High Level 2.0 V Input Pin Leakage Current 1 µA Output Pin Low Level 0.4 V ISINK = 3mA Open Drain. External pull-up resistor to Output Pin High Level 15 V user supply Output Pin High-Z leakage 10 µA Current (PSIO pins only) I/O Frequency 5 MHz Note 6: 3.3V/5.0V CMOS logic compatible, maximum rating of 15.0V © 2012 Exar Corporation 5/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm SMBUS (I2C) INTERFACE Parameter Min. Typ. Max. Units Conditions Input Pin Low Level, VIL 0.3 VIO V VIO = 3.3 V ±10% Input Pin High Level, VIH 0.7 VIO V VIO = 3.3 V±10% Hysteresis of Schmitt Trigger 0.05 VIO V VIO = 3.3 V±10% inputs, V hys Output Pin Low Level (open drain or collector), V 0.4 V ISINK = 3mA OL Input leakage current -10 10 µA Input is between 0.1 VIO and 0.9 VIO Output fall time from VIHmin to 20 + 0.1 250 ns With a bus capacitance (Cb)from 10 pF to VILmax Cb 400 pF Internal Pin Capacitance 1 pF GATE DRIVERS Parameter Min. Typ. Max. Units Conditions GH, GL Rise Time 17 ns At 10-90% of full scale, 1nF C GH, GL Fall Time 11 ns load GH, GL Pull-Up On-State Output 4 5 Ω Resistance GH, GL Pull-Down On-State 2 2.5 Ω Output Resistance GH, GL Pull-Down Resistance in 50 kΩ VCC = VCCD = 0V. Off-Mode Bootstrap diode forward 9 Ω @ 10mA resistance Minimum On Time 50 ns 1nF of gate capacitance. Minimum Off Time 125 ns 1nF of gate capacitance Minimum Programmable Dead 20 ns Does not include dead time variation from Time driver output stage Maximum Programmable Dead Tsw Tsw=switching period Time Programmable Dead Time 607 ps Adjustment Step © 2012 Exar Corporation 6/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm BLOCK DIAGRAM BST1 Channel 1 GH1 LX1 Feedback Digital Hybrid VOUT1 PreScaler ADC PID DPWM DGriavteer GL1 1/2/4 VCC DTiemade GL_ RTN1 VREF DAC SS & PD Current ADC VCCD1-2 VOUT3 Channel 2 VOUT3 Channel 3 VCCD3-4 VOUT4 Channel 4 Vout1 4uA ENABLE Vout2 Internal Vout3 POR Vout4 GPIO 0-1 MUX GPIO NVM Sequencing Vtj (FLASH) Fault BFB PSIO 0-2 Handling VCC PSIO CoRnefiggiustreartsion GPWooRd UOVTLPO OCP SDA,SCL OVP 5V LDO LDO5 I2C LOGIC CLOCK LDO3_3 3.3V LDO Fig. 2: XRP7724 Block Diagram LDO BLOCK DIAGRAM VCCD3-4 VCCD1-2 LDO5 AVDD DVDD 1.8V Gate Drivers Regulator 5V Blocks 1.8V Analog PSIO 3.3V Regulator VCC 5V LDO 3.3V GPIO 1.8V Digital LDO3_3 3.3V LDO + 4.75V – 4.9V - V5EXT Fig. 3: XRP7724 LDO Block Diagram © 2012 Exar Corporation 7/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm PIN ASSIGNMENT LDO5 V5EXT BFB VCC ENABLE GL_RTN1 GL1 LX1 GH1 BST1 VCCD1-2 4 4 4 4 4 3 3 3 3 3 3 4 3 2 1 0 9 8 7 6 5 4 LDO3_3 1 33 GL_RTN2 AGND 2 32 GL2 CPLL 3 31 LX2 AVDD 4 30 GH2 VOUT1 5 XRP7724 29 BST2 TQFN VOUT2 6 7mm X 7mm 28 GL_RTN3 VOUT3 7 27 GL3 VOUT4 8 26 LX3 GPIO0 9 25 GH3 Exposed Pad: AGND GPIO1 10 24 BST3 SDA 11 23 VCCD3-4 1 1 1 1 1 1 1 1 2 2 2 2 3 4 5 6 7 8 9 0 1 2 S P P P D D B G L G G CL SIO0 SIO1 SIO2 VDD GND ST4 H4 X4 L4 L_RT N 4 Fig. 4: XRP7724 Pin Assignment PIN DESCRIPTION Name Pin Number Description Input voltage. Place a decoupling capacitor close to the controller IC. This input is used VCC 41 in UVLO fault generation. 1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling DVDD 16 capacitor close to the controller IC. Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be connected to the LDO5 pin to enable two power rails initially. It is recommended that VCCD1-2 23,34 the other VCCD pin be connected to the output of a 5V switching rail(for improved VCCD3-4 efficiency or for driving larger external FETs), if available, otherwise this pin may also be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch. AGND 2 Analog ground pin. This is the small signal ground connection. Ground connection for the low side gate driver. This should be routed as a signal trace GL_RTN1-4 39,33, 28,22 with GL. Connect to the source of the low side MOSFET. Output pin of the low side gate driver. Connect directly to the gate of an external N- GL1-GL4 38,32, 27,21 channel MOSFET. Output pin of the high side gate driver. Connect directly to the gate of an external N- GH1-GH4 36,30, 25,19 channel MOSFET. © 2012 Exar Corporation 8/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm Name Pin Number Description Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFETs and the inductor. These LX1-LX4 37,31, 26,20 pins are also used to measure voltage drop across bottom MOSFETs in order to provide output current information to the control engine. High side driver supply pin(s). Connect BST to the external capacitor as shown in the Typical Application Circuit on page 2. The high side driver is connected between the BST1-BST4 35,29, 24,18 BST pin and LX pin and delivers the BST pin voltage to the high side FET gate each cycle. These pins can be configured as inputs or outputs to implement custom flags, power GPI0-GPIO1 9,10 good signals, enable/disable controls and synchronization to an external clock. Open drain, these pins can be used to control external power MOSFETs to switch loads on and off, shedding the load for fine grained power management. They can also be PSIO0-PSIO2 13,14,15 configures as standard logic outputs or inputs just as any of the GPIOs can be configured, but as open drains require an external pull-up when configured as outputs. SDA, SCL 11,12 SMBus/I2C serial interface communication pins. Connect to the output of the corresponding power stage. The output is sampled at least VOUT1-VOUT4 5,6,7,8 once every switching cycle Output of a 5V LDO. This is a micro power LDO that can remain active while the rest of LDO5 44 the IC is in shutdown. This LDO is also used to power the internal Analog Blocks. Output of the 3.3V standby LDO. This is a micro power LDO that can remain active LDO3_3 1 while the rest of the IC is in shutdown. If ENABLE is pulled high or allowed to float high, the chip is powered up (logic is reset, ENABLE 40 registers configuration loaded, etc.). The pin must be held low for the XRP7724 to be placed into shutdown. Input from the 15V output created by the external boost supply. When this pin goes BFB 42 below a pre-defined threshold, a pulse is created on the low side drive to charge this output back to the original level. If not used, this pin should be connected to GND. Digital ground pin. This is the logic ground connection, and should be connected to the DGND 17 ground plane close to the PAD. CPLL 3 Connect to a 2.2nF capacitor to GND. External 5V that can be provided. If one of the output channels is configured for 5V, V5EXT 43 then this voltage can be fed back to this pin for reduced operating current of the chip and improved efficiency. Output of the internal 1.8V LDO. A decoupling capacitor should be placed between AVDD 4 AVDD and AGND close to the chip. This is the die attach paddle, which is exposed on the bottom of the part. Connect PAD 45 externally to the ground plane. ORDERING INFORMATION Temperature Packing I2C Default Part Number Marking Package Note 1 Range Quantity Address XRP7724ILB-F -40°C≤TJ≤+125°C XRP7724ILB 44-pin TQFN Bulk Halogen Free 0x28 (7Bit) XRP7724ILBTR-F -40°C≤T≤+125°C YYWW X 2.5K/Tape & Reel Halogen Free J Evaluation kit includes XRP7724EVB-DEMO-1 Evaluation Board with Power XRP7724EVB-DEMO-2P-KIT Architect software and XRP77XXEVB-XCM (USB to I2C Exar Configuration Module) “YY” = Year – “WW” = Work Week – “X” = Lot Number; when applicable. © 2012 Exar Corporation 9/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm TYPICAL PERFORMANCE CHARACTERISTICS All data taken at VCC = 12V, T = T = 25°C, unless otherwise specified - Schematic and BOM from XRP7724EVB. See J A XRP7724EVB-DEMO-1 Manual. Fig. 5: PFM to PWM Transition Fig. 6 PWM to PFM Transition Fig. 7 0-6A Transient 300kHz PWM only Fig. 8 10-6A Transient 300kHz with OVS ±5.5% Fig. 9 Sequential Start-up Fig. 10 Sequential Shut Down © 2012 Exar Corporation 10/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm Example Fig. 11: Simultaneous Start-up Fig. 12 Simultaneous Shut Down Fig. 13: PFM Zero Current Accuracy Fig. 14: LDO5 Brown Out Recovery, No Load 1.00 0.95 0.90 Vin=25V 0.85 Rising 0.80 Vin=25V Falling 0.75 Vin=4.75 0.70 V Rising 0.65 Vin=4.75 V Falling 0.60 -40°C 25°C 85°C 125°C Fig. 15: Enable Threshold Over Temp © 2012 Exar Corporation 11/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm FEATURES AND BENEFITS System Integration Capabilities  Single supply operation Programmable Power Benefits  I2C interface allows:  Fully Configurable  Communication with a System Controller  Output set point or other Power Management devices for  Feedback compensation optimized system function  Frequency set point  Access to modify or read internal  Under voltage lock out registers that control or monitor:  Input voltage measurement  Output Current  Gate drive dead time  Input and Output Voltage  Soft-Start/Soft-Stop Time  Reduced Development Time  ‘Power Good’  Configurable and re-configurable for different Vout, Iout, Cout, and Inductor  Part Temperature values  Enable/Disable Outputs  No need to change external passives for a  Over Current new output specification.  Over Voltage  Higher integration and Reliability  Temperature Faults  Many external circuits used in the past  Adjusting fault limits and can be eliminated significantly improving disabling/enabling faults reliability.  Packet Error Checking (PEC) on I2C communication PowerArchitect™ 5.0 Design and Configuration Software  5 GPIO pins with a wide range of configurability  Wizard quickly generates a base design  Fault reporting (including UVLO  Calculates all configuration registers Warn/Fault, OCP Warn/Fault, OVP,  Projects can be saved and/or recalled Temperature, Soft-Start in progress,  GPIOs can be configured easily and Power Good, System Reset) intuitively  Allows a Logic Level interface with other  “Dashboard” Interface can be used for non-digital IC’s or as logic inputs to other real-time monitoring and debug devices  Frequency and Synchronization System Benefits Capability  Reliability is enhanced via communication  Selectable switching frequency between with the system controller which can obtain 105kHz and 1.2MHz real time data on an output voltage, input  Main oscillator clock and DPWM clock can voltage and current. be synchronized to external sources  System processors can communicate with  ‘Master’, ‘Slave’ and ‘Stand-alone’ the XRP7724 directly to obtain data or Configurations are possible make adjustments to react to circuit conditions  Internal MOSFET Drivers  Internal FET drivers (4Ω/2Ω) per channel  A system process or could also be configured to log and analyze operating  Built-In Automatic Dead-time adjustment history, perform diagnostics and if required,  30ns Rise and Fall times take the supply off-line after making other  4 Independent SMPS channels and 2 system adjustments. LDOs in a 7x7mm TQFN © 2012 Exar Corporation 12/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm FUNCTIONAL OVERVIEW external circuitry. The 3.3V LDO is solely for customer use and is not used by the chip. The XRP7724 is a quad-output digital pulse There is also a 1.8V linear which is for internal width modulation (DPWM) controller with use only and should not be used externally. integrated gate drivers for use with synchronous buck switching regulators. Each A key feature of the XRP7724 is its powerful output voltage can be programmed from 0.6V power management capabilities. All four to 5.5V without the need of an external outputs are independently programmable and voltage divider. The wide range of the gives the user not only full control of the programmable DPWM switching frequency delay, ramp, and sequence during power up (from 105 kHz to 1.2 MHz) enables the user to and power down. One can also control of how optimize for efficiency or component sizes. the outputs interact and power down in the Since the digital regulation loop requires no event of a fault. This includes active ramp external passive components, loop down of the output voltages to remove an performance is not compromised due to output voltage as quickly as possible. Another external component variation or operating nice feature is that the outputs can be defined condition. and controlled as groups. The XRP7724 provides a number of critical The XRP7724 has two main types of safety features, such as Over-Current programmable memory. The first types are Protection (OCP), Over-Voltage Protection runtime registers that contain configuration, (OVP), Over Temperature Protection (OTP) control and monitoring information for the plus input Under Voltage Lockout (UVLO). In chip. The second type is rewritable Non- addition, a number of key health monitoring Volatile Flash Memory (NVFM) that is used for features such as warning level flags for the permanent storage of the configuration data safety functions, Power Goods (PGOOD), etc., along with various chip internal functions. plus full monitoring of system voltages and During power up the run time registers are currents. The above are all programmable loaded from the NVFM allowing for standalone and/or readable from the SMBus and many operation. are steerable to the GPIOs for hardware The XRP7724 brings an extremely high level of monitoring. functionality and performance to a For hardware communication, the XRP7724 programmable power system. Ever has two logic level General Purpose Input- decreasing product budgets require the Output (GPIO) pins and three, 15V, open designer to quickly make good drain, Power System Input-Output (PSIO) cost/performance tradeoffs to be truly pins. Two pins are dedicated to the SMBus successful. By incorporating 4 switching data (SDA) and clock (SCL). Additional pins channels, two user LDOs, a charge pump include Chip Enable (Enable), Aux Boost boost controller, along with internal gate Feedback (BFB) and External PLL Capacitor drivers, all in a single package, the XRP7724 (CPLL). allows for extremely cost effective power system designs. Another key cost factor to In addition to providing four switching outputs, put into the cost tradeoffs, which is often the XRP7724 also provides control for an Aux overlooked, is the unanticipated Engineering boost supply, and two stand-by linear Change Order (ECO). The programmable regulators that produce 5V and 3.3V for a total versatility of the XRP7724, along with the lack of 7 customer usable supplies in a single of hard wired, on board configuration device. components, allows for minor and major The 5V LDO is used for internal power and is changes to be made, in circuit, on the board also available for customer use to power by simple reprogramming. © 2012 Exar Corporation 13/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm THEORY OF OPERATION CHIP ARCHITECTURE REGULATION LOOPS Vin Vdrive (VCC) (VCCD)x AFE Vref Fine Vin Feed DAC Adjust Forward GHx VFB Scalar Error AFE Error Gate PID DPWM GLx (VOUTx) ÷1,2,4 Amp ADC Register Driver LXx Window Current OVS Comp. ADC PFM/ Ultrasonic PWM- PFM Sel Fig 16 XRP7724 Regulation Loops Figure 16 shows a functional block diagram of up to 1.6V (low range) the scalar has a gain of the regulation loops for an output channel. 1. For output voltages from 1.6V to 3.2V (mid There are four separate parallel control loops; range) the scalar gain is 1/2 and for voltages Pulse Width Modulation (PWM), Pulse greater than 3.2V (high range) the gain is 1/4. Frequency Modulation (PFM), Ultrasonic, and This results in the low range having a Over Sampling (OVS). Each of these loops is reference voltage resolution of 12.5mV, mid fed by the Analog Front End (AFE) as shown at range of 25mV and the high range having a the left of the diagram. The AFE consist of an resolution of 50mV. The error amp has a gain input voltage scalar, a programmable Voltage of 4 and compares the output voltage of the Reference (Vref) DAC, Error Amplifier, and a scalar to Vref to create an error voltage on its window comparator. (Please note that the output. This is converted to a digital error block diagram shown is simplified for ease of term by the AFE ADC which is stored in the understanding. Some of the function blocks error register. The error register has a fine are common and shared by each channel by adjust function that can be used to improve means of a multiplexer.) the output voltage set point resolution by a factor of 5 resulting in a low range resolution PWM Loop of 2.5mV, mid range resolution of 5mV and a high range resolution of 10mV. The output of The PWM loop operates in Voltage Control the error resister is then used by the Mode (VCM) with optional Vin feed forward Proportional Integral Derivative (PID) based on the voltage at the VCC pin. The controller to manage the loop dynamics. reference voltage (Vref) for the error amp is created by a 0.15V to 1.6V DAC that has a The XRP7724 PID is a 17-bit five coefficient 12.5mV resolution. In order to get a full 0.6V control engine that calculates the correct duty to 5.5V output voltage range an input scalar is cycle under the various operating conditions used to reduce feedback voltages for higher and feeds it to the Digital Pulse Width output voltages to bring them within the 0.15V Modulator (DPWM). Besides the normal to 1.6V control range. So for output voltages © 2012 Exar Corporation 14/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm coefficients the PID also uses the Vin voltage The PFM loop works in conjunction with the to provide a feed forward function. PWM loop and is entered when the output current falls below a programmed threshold The XRP7724 DPWM includes a special delay level for a programmed number of cycles. timing loop that gives a timing resolution that When PFM mode is entered, the PWM loop is is 16 times the master oscillator frequency disabled and instead, the scaled output (103MHz) for a timing resolution of 607ns for voltage is compared to Vref with a window both the driver pulse width and dead time comparator. The window comparator has three delays. The DWPM creates and outputs the thresholds; normal (Vref), high (Vref + Gate High (GH) and Gate Low (GL) signals to %high) and low (Vref - %low). The %high and the driver. The maximum and minimum on %low values are programmable and track times and dead time delays are programmable Vref. by configuration resisters. In PFM mode, the normal comparator is used To provide current information, the output to regulate the output voltage. If the output inductor current is measured by a differential voltage falls below the Vref level, the amplifier that reads the voltage drop across comparator is activated and triggers the the RDS of lower FET during its on time. There DPWM to start a switching cycle. When the are two selectable ranges, a low range with a high side FET is turned on, the inductor gain of 8 for a +20mV to -120 mV range and a current ramps up which charges up the output high range with a gain of 4 for +40mV to - capacitors and increasing their voltage. After 280mV range. The optimum range to use will the completion of the high side and low side depend on the maximum output current and on-times, the lower FET is turned off to inhibit the RDS of the lower FET. The measured any inductor reverse current flow. The load voltage is then converted to a digital value by current then discharges the output capacitors the current ADC block. The resulting current until the output voltage falls below Vref and value is stored in a readable register and also the normal comparator is activated this then used to determine when PWM to PFM triggers the DPWM to start the next switching transitions should occur. cycle. The time from the end of the switching cycle to the next trigger is referred to as the PFM mode loop dead zone. This PFM methodology ensures The XRP7724 has a PFM loop that can be output voltage ripple does not increase from enabled to improve efficiency at light loads. PWM to PFM. By reducing switching frequency and operating When PFM mode is initially entered the in the discontinuous conduction mode (DCM), switching duty cycle is the same that it was in both switching and I2R losses are minimized. PWM mode. The cause the inductor ripple Figure 17 shows a functional diagram of the current to be the same level that it was in PFM logic. PWM mode. During operation the PFM duty cycle is calculated based on the ratio of the # Cycles Reg output voltage to VCC. Default = 20 A If the output voltage ever goes outside the PFM Current CHx Fsw Clk COUNTER A<B Threshold Reg A Clear high/low windows, PFM mode is exited and the B A<B PWM loop is reactivated. IADC B Although the PFM mode does a good job in PWM MODE VOUT S Q improving efficiency at light load, at very light R Q + PFM MODE loads the dead zone time can increase to the VREF HIGH - PFM EXIT point where the switching frequency can enter - TRIGGER PULSE the audio hearing range. When this happens VREF + some components, like the output inductor - and ceramic capacitors, can emit audible VREF LOW + noise. The amplitude of the noise depends Fig 17: PFM Enter/Exit Functional Diagram © 2012 Exar Corporation 15/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm mostly on the board design and on the delay of up to one switching cycle before the manufacturer and construction details of the control loop can respond. With OVS enabled if components. Proper selection of components output voltage drops below the lower level, an can reduce the sound to very low levels. In immediate GH pulse will be generated and general Ultrasonic Mode is not used unless sent to the driver to increase the output required as it reduces light load efficiency. inductor current toward the new load level without having to wait for the next cycle to Ultrasonic Mode begin. If the output voltage is still below the lower limit at the beginning of the next cycle, Ultrasonic mode is an extension of PFM to OVS will work in conjunction with the PID to ensure that the switching frequency never insert additional GH pulses to quickly return enters the audible range. When this mode is the output voltage back within its regulation entered, the switching frequency is set to band. The result of this system is transient 30kHz and the duty cycle of the upper and response capabilities on par or exceeding lower FETs, which are fixed in PFM mode, are those of a constant on-time control loop. decreased as required to keep the output voltage in regulation while maintaining the Over Voltage OVS: When there is a step load 30kHz switching frequency. current decrease, the output voltage will increase (bump up) as the excess inductor Under extremely light or zero load currents, current that is no longer used by the load, the GH on time pulse width can decrease to its flows into the output capacitors causing the minimum width. When this happens, the lower output voltage to rise. The voltage will FET on time is increased slightly to allow a continue to rise until the inductor current small amount of reverse inductor to flow back decreases to the new load current. With OVS into Vin to keep the output voltage in enabled, if the output voltage exceeds the regulation while maintaining the switching high limit of the window comparator, a frequency above the audio range. blanking pulse is generated to truncate the GH signal. This causes inductor current to Oversampling OVS Mode immediately begin decreasing to the new load Oversampling (OVS) mode is a feature added level. The GH will continue to be blanked until to the XRP7724 to improve transient the output voltage falls below the high limit. responses. This mode can only be enabled Again, since the output voltage is sampled at when the channel switching frequency is four times the switching frequency, over shoot operating in 1x frequency mode. In OVS mode will be decreased and the time required to get the output voltage is sampled 4 times per back into the regulation band is also switching cycle and is monitored by the AFE decreased. window comparator. If the voltage goes OVS can be used in conjunction with both the outside the set high or low limits, the OVS PWM and PFM operating modes. When it is control electronics can immediately modify the activated it can noticeably decrease output pulse width of the GH or GL drivers to respond voltage excursions when transitioning between accordingly, without having to wait for the PWM and PFM modes. next cycle to start. OVS has two types of response depending on whether the high limit INTERNAL DRIVERS is exceeded during an unloading transient (Over Voltage), or the low limit is exceeded The internal high and low gate drivers use during a loading transient (Under Voltage). totem pole FETs for high drive capability. They are powered by two external 5V power pins Under Voltage OVS: If there is an increasing (VCCD1-2) and (VCCD3-4), VCCD1-2 powers current load step, the output voltage will drop the drivers for channels 1 and 2 and VCCD3-4 until the regulator loop adapts to the new powers channels 3 and 4. The drivers can be conditions to return the voltage to the correct powered by the internal 5V LDO by connecting level. Depending on where in the switching their power pins to the LDO5 output through cycle the load step happens there can be a © 2012 Exar Corporation 16/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm an RC filter to avoid conducted noise back into (VCC) supply. The output of LDO5 should be the analog circuitry. bypassed by a good quality capacitor connected between the pin and ground close To minimize power dissipation in the 5V LDO it to the device. The 5V output is used by the is recommended to power the drivers from an XRP7724 as a standby power supply and is external 5V power source either directly or by also used to power the 3.3V and 1.8V linear using the V5EXT input. Good quality 1uF to regulators inside the chip and can also supply 4.7uF capacitors should be connected directly power to the 5V gate drivers. The total output between the power pins to ground to optimize current that the 5V LDO can provide is 130mA. driver performance and minimize noise The XRP7724 consumes approximately 20mA coupling to the 5V LDO supply. and the rest is shared between LDO3_3 and The driver outputs should be connected the gate drive currents. During initial power directly to their corresponding output up, the maximum external load should be switching FETs, with the Lx output connected limited to 30mA. to the drain of the lower FET for the best The 3.3V LDO output available on the LDO3_3 current monitoring accuracy. pin is solely for customer use and is not used See ANP-32 “Practical Layout Guidelines for internally. This supply may be turned on or off PowerXR Designs” by the configuration registers. Again a good bypass capacitor should be used. LDOS The AVVD pin is the 1.8V regulator output and The XRP7724 has two internal Low Drop Out needs to be connected externally to the DVVD (LDO) linear regulators that generate 5.0V pin on the device. A good quality capacitor (LDO5) and 3.3V (LDO3_3) for both internal should be connected between this pin and and external use. Additionally it also has a ground close to the package. 1.8V regulator that supplies power for the For operation with a VCC of 4.75V to 5.5V, the XRP7724 internal circuits. Figure 3 shows a LDO5 output needs to be connected directly to block diagram of the linear power supplies. VCC on the board. LDO5 is the main power input to the device and is supplied by an external 5.5V to 25V CLOCKS AND TIMING Ext Clock Output GPIO1 ¸4/¸8 Clock Reg Divider Freg Mult Reg PLL DPWM Ext Clock Input System Clock SEL GPIO0 Base Frequency 2x x4/x8 Frequency CH1 Timing 4x Reg Set Reg Sequencer To Channels 2®4 Fig 18 XRP7724 Timing Block Diagram © 2012 Exar Corporation 17/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm Figure 18 shows a simplified block diagram of Base Available 2x Available 4x the XRP7724 timings. Again, please note that Frequency Frequencies Frequencies the function blocks and signal names used are kHz kHz kHz chosen for ease of understanding and do not 105.5 211.1 422.1 necessarily reflect the actual design. 107.3 214.6 429.2 109.1 218.2 436.4 The system timings are generated by a 111.0 222.0 444.0 103MHz internal system clock (Sys_Clk). 112.9 225.9 451.8 There are two ways that the 103 MHz system 115.0 229.9 459.8 117.0 234.1 468.2 clock can be generated. These include an 119.2 238.4 476.9 internal oscillator and a Phase Locked Loop 121.5 242.9 485.8 (PLL) that is synchronized to an external clock 123.8 247.6 495.2 input. The basic timing architecture is to 126.2 252.5 504.9 divide the Sys_Clk down to create a 128.8 257.5 515.0 fundamental switching frequency (Fsw_Fund) 131.4 262.8 525.5 for all the output channels that is settable 134.1 268.2 536.5 from 105kHz to 306kHz. The switching 137.0 273.9 547.9 139.9 279.9 559.8 frequency for a channel (Fsw_CHx) can then 143.1 286.1 572.2 be selected as 1 times, 2 times or 4 times the 146.3 292.6 585.2 fundamental switching frequency. 149.7 299.4 598.8 To set the base frequency for the output 153.3 306.5 613.1 157.0 314.0 628.0 channels a “Fsw_Set” value representing the 160.9 321.9 643.8 base frequency shown in Table 1, is entered 165.1 330.1 660.3 into the switching frequency configuration 169.4 338.8 677.6 register (Fsw_Set is basically equal to the 174.0 348.0 695.9 base frequency times 256). The system 178.8 357.6 715.3 timings are then created by dividing down 183.9 367.9 735.7 Sys_Clk to produce a base frequency clock, 189.3 378.7 757.4 2X and 4X times the base frequency clocks, 195.1 390.2 780.3 201.2 402.3 804.7 and sequencing timing to position the output 207.7 415.3 830.6 channels relative to each other. Each output 214.6 429.2 858.3 channel then has its own frequency multiplier 222.0 444.0 887.9 register that is used to select its final output 229.9 459.8 919.6 switching frequency. 238.4 476.9 953.7 247.6 495.2 990.4 Table 1 shows the available channel switching 257.5 515.0 1030.0 frequencies for the XRP7724 device. In 268.2 536.5 1072.9 practice the PowerArchitect™ 5.0 design tool 279.9 559.8 1119.6 handles all the details and the user only has 292.6 585.2 1170.5 to enter the fundamental switching frequency 306.5 613.1 1226.2 and the 1x, 2x, 4x frequency multiplier for Table 1 each channel. If an external clock is used, the frequencies in this table will shift accordingly. © 2012 Exar Corporation 18/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm SUPERVISORY AND CONTROL  General Output – set with an I2C command Power system design with XRP7724 is  General Input – triggers an interrupt; accomplished using PowerArchitect™ design state read with an I2C command tool version 5 (PA5). All figures referenced in the following sections are taken from PA5.  Power Group Enable – controls Furthermore, the following sections reference enabling and disabling of Group 1 and I2C commands. For more on these commands Group 2 please refer to ANP-38.  Power Channel Enable – controls enabling and disabling of a individual DIGITAL I/O channel including LDO3.3 XRP7724 has two General Purpose Input  I2C Address Bit – controls an I2C Output (GPIO) and three Power System Input address bit Output (PSIO) user configurable pins.  Power OK – indicates that selected channels have reached their target levels and have not faulted. Multiple channel selection is available in which case the resulting signal is the AND logic function of all channels selected  ResetOut – is delayed Power OK. Delay is programmable in 1msec increments with the range of 0 to 255 msecs  Low Vcc – indicates when Vcc has fallen below the UVLO fault threshold and when the UVLO condition clears (Vcc  GPIOs are 3.3V CMOS logic compatible voltage rises above the UVLO warning and 5V tolerant. level)  PSIO configured as outputs are open  Interrupt – the controller generated drain and require external pull-up interrupt selection and clearing is done resistor. These I/Os are 3.3V and 5V through I2C commands CMOS logic compatible, and up to 15V capable. Interrupt, Low Vcc, Power OK and ResetOut signals can only be forwarded to a single The polarity of the GPIO/PSIO pins is set in GPIO/PSIO. PA5 or with an I2C command. In addition, the following are functions that are unique to GPIO0 and GPIO1. Configuring GPIO/PSIOs The following functions can be controlled from or forwarded to any GPIO/PSIO: © 2012 Exar Corporation 19/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm HW Flags – these are hardware monitoring functions forwarded to GPIO0 only. The functions include Under-Voltage Warning, Over- Temperature Warning, Over-Voltage Fault, Over-Current Fault and Over -Current Warning for every channel. Multiple selection  “PGood Max” is the upper window and is available in which case the resulting signal “PGood Min” is the lower window. The is the OR logic function minimum and maximum for each of these values can be calculated by the following equation:  External Clock-in – enables the  Where N =1 to 63 for the PGOOD Max controller to lock to an external clock value and N=1 to 62 for the PGOOD Min including one from another XRP7724 value. For example, with the target applied to the GPIO0 pin. There are two voltage of 1.5V and set point resolution of ranges of clock frequencies the controller 2.5mV (LSB), the Power Good min and accepts, selectable by a user max values can range from 0.17% to 10.3% and 0.17% to 10.5% respectively. A user can effectively double the values by changing to the next higher output voltage range setting, but at the expense of reduced set point resolution.  External Clock-out – clock sent out through GPIO1 for synchronizing with another XRP7724 (see the clock out section for more information). FAULT HANDLING There are seven different types of fault handling:  HW Power Good – the Power Good hardware monitoring function. It can only  Under Voltage Lockout (UVLO) be forwarded to GPIO1. It is an output monitors voltage supplied to the Vcc pin voltage monitoring function that is a and will cause the controller to shutdown hardware comparison of channel output all channels if the supply drops to critical voltage against its user defined Power levels. Good threshold limits (Power Good  Over Temperature Protection (OTP) minimum and maximum levels). . It has monitors temperature of the chip and will no hysteresis. Multiple channel selection is cause the controller to shutdown all available in which case the resulting signal channels if temperature rises to critical is the AND logic function of all channels levels. selected.  Over Voltage Protection (OVP) monitors regulated voltage of a channel and will cause the controller to react in a user specified way if the regulated voltage surpasses threshold level.  The Power Good minimum and maximum  Over Current Protection (OCP) levels are expressed as percentages of the monitors current of a channel and will target voltage. cause the controller to react in a user © 2012 Exar Corporation 20/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm specified way if the current level level at 4.6V may result in the outputs not re- surpasses threshold level. enable until a full 5.0V is reached on Vcc.  Start-up Time-out Fault monitors if a Setting the warning level to 4.6v and the fault channel gets into regulation in a user level at 4.4V would likely make UVLO handing defined time period as desired, however, below 4.6V the device  LDO5 Over Current Protection (LDO5 has a hardware UVLO on LDO5 to ensure OCP) monitor current drawn from the proper shutdown of the internal circuitry of regulator and will cause the controller to the controller. This means the 4.4V UVLO be reset if the current exceeds LDO5 limit fault level will never occur. A special test has (155mA typical) been added to ensure that if UVLO FAULT will  LDO3.3 Over Current Protection (LDO3.3 OCP) monitors current drawn OTP from the regulator and will cause the User defined OTP warning, fault and restart controller to shut down the regulator if the levels are set at 5°C increments in PA5. current exceeds LDO3.3 current limit (65mA typical) UVLO Both UVLO warning and fault levels are user When the warning level is reached the programmable and set at 200mV increments controller will generate the in PA5. TEMP_WARNING_EVENT interrupt. In addition, the host can be informed about the event through HW Flags on GPIO0 (see the Digital I/O section). When the warning level is reached the controller will generate the When an OTP fault condition occurs, the UVLO_WARNING_EVENT interrupt. In XRP7724 outputs are shutdown and the addition, the host can be informed about the TEMP_OVER_EVENT interrupt is generated. event through HW Flags on GPIO0 (see the Once temperature reaches a user defined OTP Digital I/O section). Restart Threshold level, the When an under voltage fault condition occurs, TEMP_UNDER_EVENT interrupt will be the XRP7724 outputs are shutdown and the generated and the controller will reset. UVLO_FAULT_ACTIVE_EVENT interrupt is generated. In addition, the host can be OVP informed by forwarding the Low Vcc signal to A user defined OVP fault level is set in PA5 any GPIO/PSIO (see the Digital I/O section). and is expressed in percentages of a This signal transitions when the UVLO fault regulated target voltage. occurs. When coming out of the fault, rising Vcc crossing the UVLO fault level will trigger the UVLO_FAULT_INACTIVE_EVENT interrupt. Once UVLO condition clears (Vcc voltage rises Resolution is the same as for the target Above or TO the user defined UVLO warning voltage (expressed in percentages). The OVP level), the Low Vcc signal will transition and minimum and maximum values are calculated the controller will be reset. by the following equation where the range for N is 1 to 63: A special attention needs to be paid in the case when Vcc = LDO5 = 4.75V to 5.5V. Since the input voltage ADC resolution is 200mV, the UVLO warning and fault set points are coarse for a 5V input. Therefore, When the OVP level is reached and the fault is setting the warning level at 4.8V and the fault generated, the host will be notified by the © 2012 Exar Corporation 21/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm SUPPLY_FAULT_EVENT interrupt generated by as defined in the electrical characteristics. the controller. The host then can use anI2C The maximum value the user can program is command to check which channel is at fault. limited by Rdson of the synchronous Power FET and current monitoring ADC range. For In addition, OVP fault can be monitored example, using a synchronous FET with Rdson through GPIO0. of 30mΩ, using the wider ADC range, the A user can choose one of three options on maximum current limit programmed would how to react to an OVP event: to shutdown be: the faulting channel, to shut down faulting channel and to perform auto-restart of the channel, or to restart the chip. The current is sampled approximately 30ns before the low side MOSFET turns off, so the actual measured DC output current in this example would be 9.33A plus approximately half the inductor ripple. An OCP Fault is considered to have occurred only if the fault threshold has been tripped in In the case of shutting down the faulting 4 consecutive switching cycles. When the channel and auto-restarting, the user has an switching frequency is using the 4x multiplier, option to specify startup timeout (the time in the current is sampled only every other cycle. which the fault is validated) and hiccup As a result it can take as many as 8 switching timeout (the period after which the controller cycles for an over current event to be will try to restart the channel) periods in 1 detected. When operating in 4x mode msec increments with a maximum value of inductors with a soft saturation characteristic 255 msec. are recommended. When the OCP level is reached and the fault is generated, the host will be notified by the SUPPLY_FAULT_EVENT interrupt generated by the controller. The host then can use an I2C command to check which channel is at fault. In addition, OCP fault can be monitored through HW Flags on GPIO0. The host can also monitor OCP warning flag through HW Flags on GPIO0. The OCP warning level is calculated by PowerArchitect™ as 85% of the OCP fault level. Note: a channel will share a response to an A user can choose one of three options on OVP or OCP event. how to react to an OCP event: to shutdown the faulting channel, to shut down faulting OCP channel and to perform auto-restart of the A user defined OCP fault level is set with 1mA channel, or to restart the chip. increments in PA5. PA5 uses calculations to The output current reported by the XRP7724 give the user the approximate DC output is processed through a 7 sample median filter current entered in the current limit field. in order to reduce noise. The OCP limit is However the actual current limit trip value compared against unfiltered ADC output. programmed into the part is limited to 280mV © 2012 Exar Corporation 22/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm V5EXT SWITCHOVER The V5EXT gives a user an opportunity to supply an external 5 Volt rail to the controller in order to reduce the controller’s power dissipation. The 5 Volt rail can be an independent power rail present in a system or any of 7724 channels regulated to 5 Volts (in the PFM mode in particular) and routed back to the V5EXT pin. It is important to mention In the case of shutting down the faulting that voltage to Vcc must be applied all the channel and auto-restarting, the user has an time even after the switchover in which case option to specify startup timeout (the time in the current drawn from Vcc supply will be which the fault is validated) and hiccup minimal. timeout (the period after which the controller If the function not used, we recommend the will try to restart the channel) periods in 1 pin to be either grounded or left floating in msec increments with a maximum value of conjunction with making sure the function 255 msec. gets disabled through register settings. Note: a channel will share a response to an OCP or OVP event. V5EXT switchover control The function is enabled in PA5. The Start-up Time-out Fault switchover thresholds are programmable in A channel will be at Start-up Time-out Fault if 50mV steps with a total range of 200mV. it does not come-up in a time period specified Hysteresis to go in-out is 150mV. LDO5 in the “Startup Timeout” box. In addition, a automatically turns off when the external channel is at Start-up Timeout Fault if in pre- voltage is switched in and turns on when the bias configuration voltage is a defined value external voltage drops below the lower too close to the target. threshold. When the fault is generated, the host will be notified by the SUPPLY_FAULT_EVENT interrupt generated by the controller. The host then can use an I2C command to check which channel is at fault. LDO5 OCP When current is drawn from LDO5 exceeds When the controller switches over to the LDO5 current limit the controller gets reset. V5EXT rail, the V5EXT_RISE interrupt is generated to inform the host. Similarly, when LDO3.3 OCP the controller switches out, the V5EXT_FALL When current drawn from LDO3.3 exceeds interrupt gets generated. LDO3.3 current limit the regulator gets shut down, a fault is generated, and the host will EXTERNAL CLOCK SYNCHRONIZATION be notified by the SUPPLY_FAULT_EVENT XRP7724 can be run off an external clock interrupt generated by the controller. The available in the system or another XRP7724. host then can through an I2C command The external clock must be in the ranges of check which channel/regulator is at fault. 10.9MHz to 14.7MHz or 21.8MHz to 29.6MHz. Once the fault condition is removed, the host Locking to the external clock is done through needs to turn the regulator on again. an internal Phase Lock Loop (PLL) which requires an external loop capacitor of 2.2nF to © 2012 Exar Corporation 23/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm be connected between the CPLL pin and Channels including LDO3.3 can be controlled AGND. independently by any GPIO/PSIO or I2C command. Channels will start-up or shut- In applications where this functionality is not down following transitions of signals applied desired, the CPLL capacitor is not necessary to GPIO/PSIOs set to control the channels. and can be omitted, and the pin shall be left The control can always be overridden with an floating. In addition, the user needs to make I2C command. sure the function gets disabled through register settings. Regardless whether the channels are controlled independently or are in a group, The external clock must be routed to GPIO0. the ramp rates specified are followed (see the The GPIO0 setting must reflect the range of Power Sequencing section). the external clock applied to it: Sys_Clock/8 corresponds to the range of 10.9MHz to Regulated voltages and voltage drops across 14.7MHz while Sys_Clock/4 setting synchronous FET on each switching channel corresponds to the range of 21.8Mhz to can be read back using x I2C commands y. 29.6MHz. The regulated voltage read back resolution is 15mV, 30mV and 60mV per LSB depending The functionality is enabled in on the target voltage range. The voltage drop PowerArchitect™ 5.0 by selecting External across synchronous FET read back resolution Clock-in function under GPIO0. is 1.25mV and 2.5mV per LSB depending on the range. Through an I2C command the host can check the status of the channels; whether they are For more on details how to monitor PLL lock in regulation or at fault. in-out, please contact Exar or your local Exar representative. Regulated voltages can be dynamically changed on switching channels using I2C CLOCK OUT commands with resolution of 2.5mV, 5mV and 10mV depending on the target voltage XRP7724 can supply clock out to be used by range (in PWM mode only). another XRP7724 controller. The clock gets routed out through GPIO1 and can be set to For more information on I2C commands system clock divided by 8 (Sys_Clock/8) or please contact Exar or your local Exar system clock divided by 4 (Sys_Clock/4) representative. frequencies. POWER SEQUENCING The functionality is enabled in PA5 by selecting External Clock-Out function under All four channels and LDO3.3 can be grouped GPIO1. together and as such start-up and shut-down in a user defined sequence. Selecting none means channel(s) will not be assigned to any group and as such will be CHANNEL CONTROL controlled independently. Group Selection There are three groups: © 2012 Exar Corporation 24/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm  Group 0 – is controlled by the chip milliseconds with a range of 0msec to ENABLE or I2C command. Channels 255msec. assigned to this group will come up with the ENABLE signal being high, and will go Shut-down down with the ENABLE signal being low. The control can always be overridden with an I2C command.  Since it is recommended to leave the ENABLE pin floating in the applications when Vcc = LDO5 = 4.75V to 5.5V, please contact Exar for how to configure the For each channel within a group a user can channels to come up at the power up in specify the following shut-down this scenario. characteristics:  Group 1 – can be controlled by any GPIO/PSIO or I2C command. Channels  Ramp Rate – expressed in milliseconds assigned to this group will start-up or per Volt. It does not apply to LDO3.3. shut-down following transitions of a signal  Order – order position of a channel to applied to the GPIO/PSIO set to control come-down within the group the group. The control can always be  Wait Stop Thresh? – selecting this overridden with an I2C command. option for a channel means the next  Group 2 – can be controlled by any channel in the order cannot start ramping- GPIO/PSIO or I2C command. Channels down until this channel reaches the Stop assigned to this group will start-up or Threshold level. The stop threshold level is shut-down following transitions of a signal fixed at 600mV. applied to the GPIO/PSIO set to control  Delay – additional time delay a user can the group. The control can always be specify to postpone a channel shut-down overridden with an I2C command. with respect to the previous channel in the order. The delay is expressed in Start-up milliseconds with a range of 0msec to 255msec. MONITORING VCC AND TEMPERATURE Through I2C commands, the host can read back voltage applied to the Vcc pin and the die temperature respectively. The Vcc read For each channel within a group a user can back resolution is 200mV per LSB; the die specify the following start-up characteristics: temperature read back resolution is 5C° per LSB. For more on I2C commands please refer  Ramp Rate – expressed in milliseconds to ANP-38 “XRP7724 Command Set and per Volt. It does not apply to LDO3.3. Programming Guide”.  Order – order position of a channel to come-up within the group PROGRAMMING XRP7724  Wait PGOOD? – selecting this option for a channel means the next channel in the XRP7724 is a FLASH based device which order cannot start ramping-up until this means its configuration can be programmed channel reaches the target level and its into FLASH NVM and re-programmed a Power Good flag gets asserted. number of times.  Delay – an additional time delay a user Programming of FLASH NVM is done through can specify to postpone a channel start-up PA5. with respect to the previous channel in the order. The delay is expressed in © 2012 Exar Corporation 25/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm By clicking on the Flash button, user will start programming sequence of the design configuration into the Flash NVM. After the programming sequence completes, the chip ENABLING XRP7724 will reset (if automatically reset After Flashing XRP7724 has a weak internal pull-up ensuring box is checked), and boot the design it gets enabled as soon as internal voltage configuration from the Flash. supplies have ramped up and are in regulation. Driving the Enable pin low externally will keep the controller in the shut-down mode. A simple open drain pull down is the recommended way to shut XRP7724 down. If the Enable pin is driven high externally to control XRP7724 coming out of the shut-down For users that wish to create their own mode, care must be taken in such a scenario programming procedure so they can re- to ensure the Enable pin is driven high after program Flash in-circuit using their system Vcc gets supplied to the controller. software, please contact Exar for a list of I2C Flash Commands needed. In the configuration when Vcc = LDO5 = 4.75V to 5.5V, disabling the device by During a design process a user might want to grounding the Enable pin is not repeatedly download a design configuration recommended. At this time we recommend onto run time registers without saving it in leaving the Enable pin floating and placing the Flash. This is done through PA5 as well. controller in the “Standby Mode” instead in this scenario. The standby mode is defined as the state when all switching channels and LDO3.3 are disabled, all GPIO/PSIOs are programmed as inputs, and system clock is disabled. In this state chip consumes 440uA typical. © 2012 Exar Corporation 26/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm Short duration Enable pin toggled low Short duration shutdown pulses to the ENABLE pin of the XRP7724 which does not provide sufficient time for the LDO5 voltage to fall below 3.5V can result in significant delay in re-enabling of the device. Some examples below show LDO5 and ENABLE pins: Adding a 200 ohm load on LDO5 pulls voltage below 3.5V and restart is short. Note that as V increases, the restart time CC falls as well. 5.5V input is shown as the worst case. Since the ENABLE pin has an internal current source, a simple open drain pull down is the recommended way to shut down the XRP7724. A diode in series with a resistor between the LDO5 and ENABLE pins may No load on LDO5, blue trace. Recovery time offer a way to more quickly pull down the after ENABLE logic high is approximately LDO5 output when the ENABLE pin is pulled 40ms. low. APPLICATION INFORMATION available in the system and connected to the 5V EXT pin. If there is no 5V available in the THERMAL DESIGN system, then the power loss will increase significantly and proper thermal design As a 4 channel controller with internal becomes critical. For lower power levels MOSFET drivers and 5V gate drive supply all using properly sized MOSFETs, the use of the in one 7x7mm 44pin TQFN package, there is internal 5V regulator as a gate drive supply is the potential for the power dissipation to considered appropriate. exceed the package thermal limitations. The XRP7724 has an internal LDO which supplies 5V to the internal circuitry and MOSFET LAYOUT GUIDELINES drivers during startup. It is generally Refer to application note ANP-32 “Practical expected that either one of the switching Layout Guidelines for PowerXR Designs”. regulator outputs is 5V or another 5V rail is © 2012 Exar Corporation 27/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm PACKAGE SPECIFICATION 44-PIN 7X7MM TQFN © 2012 Exar Corporation 28/29 Rev. 1.0.1

XXRRPP77772244 QQuuaadd CChhaannnneell DDiiggiittaall PPWWMM//PPFFMM PPrrooggrraammmmaabbllee PPoowweerr MMaannaaggeemmeenntt SSyysstteemm REVISION HISTORY Revision Date Description 1.0.0 10/04/2012 Initial Release of Data Sheet 1.0.1 10/04/2012 Eliminated “Native GH, GL Rise and Fall Time” typical specification. FOR FURTHER ASSISTANCE Email: customersupport@exar.com powertechsupport@exar.com Exar Technical Documentation: http://www.exar.com/TechDoc/default.aspx? EXAR CORPORATION HEADQUARTERS AND SALES OFFICES 48720 Kato Road Fremont, CA 94538 – USA Tel.: +1 (510) 668-7000 Fax: +1 (510) 668-7030 www.exar.com NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. © 2012 Exar Corporation 29/29 Rev. 1.0.1

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