XE8805/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs r o f d e d n s e n XE8805/05A – SX8805R Sensing m g Machine – Data Am cquisitiosni with 16+10 bit ZoomingADC™ and buffered eDACs o D c General Description Key product Features The XE8805A is a data acquiesition ultra low- w • Low-power, high resolution ZoomingADC power low-voltage system on a chip (SoC) with a • 0.5 to 1000 gain with offset cancellation high efficiency microcontroRller unit embedded • up to 16 bits analog to digital converter (MCU), allowing for 1 MIPS at 300uA and 2.e4 V, • up to 13 inputs multiplexer and multiplying in one c lock cycle. • Low-voltage low-power controller operation t N • 2 MIPS with 2.4 V to 5.5 V operation The XE8805A oincludes a high resolution • 300 µA at 1 MIPS over voltage range acquisition path with the 16+10 bits ZoomingADC • 22 kByte (8 kInstruction) MTP and two buffeNred DACs. • 520 Byte RAM data memory • RC and crystal oscillators The XE8805A is available with on chip ROM (the • 5 reset, 22 interrupt, 8 event sources SX8805) or Multiple-Time-Programmable (MTP) • 8 bit and 16 bit buffered DACs program memory. • 100 years MTP Flash retention at 55°C Applications Ordering Information • Portable, battery operated instruments Product Temperature range Memory type Package • Current loop powered instruments XE8805MI028* -40°C to 85 °C MTP LQFP64 • Wheatstone bridge interfaces XE8805AMI000 -40°C to 85 °C MTP die • Pressure and chemical sensors XE8805AMI028LF -40°C to 85 °C MTP LQFP64 • HVAC control • Metering SX8805Rxxx -40°C to 85 °C** ROM *Not for new designs • Sports watches, wrist instruments **Extended temperature range on request Rev 1 January 2006 www.semtech.com

XE8805/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs TABLE OF CONTENTS Chapter 1 XE8805/05A Overview Chapter 2 XE8805/05A Performance Chapter 3 XE8805/05A CPU Chapter 4 XE8805/05A Memory Chapter 5 System Block Chapter 6 Reset generator r Chapter 7 Clock generation o Chapter 8 Interrupt handler Chapter 9 Event handler f Chapter 10 Low power RAM Chapter 11 Port A d Chapter 12 Port B Chapter 13 Port C e Chapter 14 Universal Asynchronous Receiver/Transmitter (UART) d Chapter 15 Universal Synchronous Receiver/Transmitter (USRT) Chapter 16 Acquisition Chain (ZoomingADC™) n s Chapter 17 Voltage multiplier Chapter 18 Signal D/A (DAS) e n Chapter 19 Bias D/A (DAB) Chapter 20 Counters/Timers/PWM m g Chapter 21 The Voltage Level Detector Chapter 22 XE8805/05A Dimensions i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com

XE8805/05A 1. General Overview CONTENTS r 1.1 Top schematic o 1-2 1.1.1 General description 1-2 1.1.2 XE8805 vs XE8805A f 1-4 d 1.2 Pin map 1-4 1.2.1 Bare die 1-4 e 1.2.2 LQFP-64 1-5 d 1.3 Pin assignment 1-6 n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 1-1

XE8805/05A 1.1 Top schematic 1.1.1 General description The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the Coolrisc816® CPU core. This core includes an 8x8 multiplier and 16 internal registers. The bus controller generates all control signals for access to all data registers other tharn the CPU internal registers. o The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained f in its control registers. Possible reset sources are the power-on-reset (POR), the external pin RESET, the watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low d power modes are implemented. e The clock generation and power management block sets up the clock signals and generates internal supplies for different blocks. The clock can be generated from the RC oscillator d(this is the start-up condition), the crystal oscillator (XTAL) or an external clock source (given on the OSCIN pin). n s The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8 low power data registers. If power consumption is importanet for the applicationn, the variables that need to be accessed very often should be stored in these registers rather than in the RAM. m g The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows i masking of the interrupt sources and it flags whichm interrupt source is sactive. Events are generally used to restart the processor after a HALT eperiod without jumping to a specified address, i.e. the program execution resumes with the ionstruction following the HALT instruction. The EVN handler routes the event signals of the different peripherals to the EVN inputDs of the CPU core. It allows masking of the interrupt sources and it flags which interrupt socurce is active. e The Port B is an 8 bit parallel IO port with analog cawpabilities. The URST, UART, and PWM block also make use of this port. R e The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. Flash and ROM versions have both 8k instruction memoryN. The data memory of this product is 512 byte SRAM. t o The Acquisition Chain is a high resolution acquisition path with the 16+10 bit fully differential ZoomingADC™. The VMULT (voltage multiplier) powers a part of the Acquisition Chain. N The signal D/A (DAS) is a 16 bit D/A based on sigma-delta modulation. It includes a stand-alone amplifier that can be used for analog output filtering. The bias D/A (DAB) is an 8 bit low frequency D/A. It includes a stand-alone amplifier that is used to drive large currents. It can be used to bias a sensor. The Port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input external clocks for the timer/counter/PWM block. The Port C is a general purpose 8 bit parallel I/O port. The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to simplify the software implementation of a synchronous serial link. © Semtech 2006 www.semtech.com 1-2

XE8805/05A INSTRUCTION MEMORY DATA MEMORY VPP/TEST CPU B address PORT A COOLRISC816 US control C P A(7:0) O VBAT N datain r T o VSS R O PORT C f L dataout L PC(7:0) 8X8 MULTIPLIER ER d 16 CPU REGISTERS e RESET RESET BLOCK rceosnettr o l dACQCUHIASIITNI ON AC_R(3:0) WD POR n s ZoomingADCTM e n CLOCK AC_A(7:0) OSCIN RC GENERPAOTWIOENR/ clockms g OSCOUT XTAL MANAGEMENT VREG VREG m test siVMULT VMULT control TEST CONTROLLER e DAS_OUT DAS 8 DATA REGISTERS o Signal D/A DAS_AI_P D DAS_AI_M IRQ HANDLINcG irq D AS_AO DAB DAB_R_P e w Bias D/A DAB_R_M DAB_OUT EVNR HANDLING evn DAB_AI_P e DAB_AI_M DAB_AO_P PORT B N DAB_AO_M PB(7:0) ot USRT B(5:4) P N 6) UART B(7: P VLD COUNTERS 0) TIMERS 3: PWM PA( 0) 1: B( P Figure 1-1. Block schematic of the XE8805/05A circuit. The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the asynchronous serial link. The counters/timers/PWM can take their clocks from internal or external sources (on Port A) and can generate interrupts or events. The PWM is output on Port B. © Semtech 2006 www.semtech.com 1-3

XE8805/05A The VLD (voltage level detector) detects the battery end of life with respect to a programmable threshold. 1.1.2 XE8805 vs XE8805A The XE8805A has a new RESET pin function. The action of the RESET pin of the XE8805A resets the clock registers too and creates an additional short delay. See the RESET chapter for more information. 1.2 Pin map r o 1.2.1 Bare die f SS ( 428.5, 4453.4) SCIN ( 593.5, 4453.4) SS ( 758.5, 4453.4) SCOUT ( 923.5, 4453.4) ESET (1088.5, 4453.4) MULT (1252.9, 4453.4) REG (1418.5, 4453.4) SS_REG (1588.5, 4453.4) SS (1753.5, 4453.4) BAT (1923.5, 4453.4) AS_AO (3114.6, 4453.4) AS_AI_M (3293.5, 4453.4) AS_AI_P (3458.5, 4453.4) dAS_OUT (3628.5, 4453.4) e d V O VO RVVVV V Dn D D D s (52.6,4123.5) PA(0) AC_R(0) (3958.4, 4118.5) (52.6, 3908.5) PA(1) e AC_Rn(1) (3958.4, 3858.5) (52.6,3693.5) PA(2) (52.6, 3478.5) PA(3) m gV SS (3958.4, 3603.5) AC_A(0) (3958.4, 3343.5) (52.6, 3263.5) VBAT (52.6, 3048.5) PA(4) i AC_A(1) (3958.4, 3088.5) (52.6, 2833.5) PA(5) m s AC_A(2) (3958.4, 2828.5) (52.6, 2618.5) PA(6) AC_A(3) (3958.4, 2573.5) (52.6, 2403.5) PA(7) e AC_A(4) (3958.4, 2313.5) (52.6, 2188.5) PC(0) o VBAT (3958.4, 2058.5) (52.6, 1973.5) PC(1) D (52.6, 1758.5) PC(2) c AC_A(5) (3958.4,1798.5) (52.6, 1543.5) PC(3) AC_A(6) (3958.4, 1543.5) (52.6, 1328.5) VSS e AC_A(7) (3958.4, 1283.5) ((5522..66,, 1819183.5.5)) R PPCC((54)) w 4600 A C_R(2) (3958.4, 1028.5) AC_R(3) (3958.4, 768.5) (52.6, 683.5) PC(6) (52.6, 468.5) PC(7) e VPP/TEST (3958.4, 508.5) 4100 N t N o ( 398.5, 47.6) PB(0) ( 533.5, 47.6) PB(1) ( 668.5, 47.6) PB(2) ( 798.5, 47.6) PB(3) ( 933.5, 47.6) PB(4) (1063.5, 47.6) VBAT (1198.5, 47.6) PB(5) (1328.5, 47.6) PB(6) (1463.5, 47.6) PB(7) (1593.5, 47.6) DAB_R_P (1728.5, 47.6) DAB_R_M (1858.5, 47.6) DAB_OUT (2042.4, 47.6) DAB_AO_P (2683.3, 47.6) DAB_AO_M (3363.5,47.6) VSS (3498.5, 47.6) DAB_AI_P (3628.4, 47.6) DAB_AI_M Figure 1-2. Die dimensions and pin coordinates (in µm) © Semtech 2006 www.semtech.com 1-4

XE8805/05A 1.2.2 LQFP-64 The XE8805/05A is delivered in a LQFP-64 package. The pin map is given below. AI_M AI_P AO_M AO_P OUT R_M R_P C AB_ AB_ AB_ AB_ AB_ AB_ AB_ B(7) B(6) B(5) B(4) B(3) B(2) B(1) B(0) N D D D D D D D P P P P P P P P r VPP/TEST 30 25 20 PC(7) o NC 15 PC(6) AC_R(3) 35 PC(f5) AC_R(2) PC(4) d AC_A(7) PC(3) AC_A(6) PC(2) AC_A(5) e 10 PC(1) AC_A(4) 40 d PC(0) AC_A(3) PA(7) AC_A(2) n PA(s6) AC_A(1) PA(5) AC_A(0) e 5 nPA(4) AC_R(1) 45 PA(3) AC_A(0) m g PA(2) NC PA(1) NC 50 m 55 60 si 1 PA(0) NC cNC DAS_OUT oDAS_AI_P DAS_AI_M DAS_AO VBAT VSS VSS_REG DVREG NC eVMULT RESET OSCOUT OSCIN NC Figure 1-3. LQFP-64 pin map e w R e Package pin name Package pin name 1 PA(0) N 33 VPP/TEST t 2 PA(1) 34 NC o 3 PA(2) 35 AC_R(3) 4 N PA(3) 36 AC_R(2) 5 PA(4) 37 AC_A(7) 6 PA(5) 38 AC_A(6) 7 PA(6) 39 AC_A(5) 8 PA(7) 40 AC_A(4) 9 PC(0) 41 AC_A(3) 10 PC(1) 42 AC_A(2) 11 PC(2) 43 AC_A(1) 12 PC(3) 44 AC_A(0) 13 PC(4) 45 AC_R(1) 14 PC(5) 46 AC_R(0) 15 PC(6) 47 NC 16 PC(7) 48 NC 17 PB(0) 49 NC 18 PB(1) 50 NC 19 PB(2) 51 DAS_OUT 20 PB(3) 52 DAS_AI_P © Semtech 2006 www.semtech.com 1-5

XE8805/05A Package pin name Package pin name 21 PB(4) 53 DAS_AI_M 22 PB(5) 54 DAS_AO 23 PB(6) 55 VBAT 24 PB(7) 56 VSS 25 DAB_R_P 57 VSS_REG 26 DAB_R_M 58 VREG 27 DAB_OUT 59 NC 28 DAB_AO_P 60 VMULT 29 DAB_AO_M 61 RESET r 30 DAB_AI_P 62 OSCOUT o 31 DAB_AI_M 63 OSCIN 32 NC 64 NC f d Table 1-1. Bonding plan of the LQFP-64 package (LQFP 64L 10x10mm thick 1.6 mm) e d 1.3 Pin assignment n s The table below gives a short description of the different pin assignments. e n Pin Assignment m g VBAT Positive power supply VSS VSS_REG Negative power supply i VREG Connection for the mandatorym external capacitor of sthe voltage regulator VPP/TEST High voltage supply for flash memory programming (NC in ROM versions) RESET Resets the circuit when the voltage is high e OSCIN/OSCOUT Quartz crystal connecotions, also used for flash memory programming PA(7:0) Parallel input port A pins D PB(7:0) Parallel I/O port cB pins PC(7:0) Parallel I/O port C pins AC_A(7:0) Acquisitione chain input pins w AC_R(3:0) Acquisition chain reference pins VMULT ConneRction for the external capacitor if VBAT is below 3V DAB_OUT Bias D/A output e DAB_R_x Bias D/A reference (x=P: plus, x=M: minus) DAB_Ax_y tBias D/A amplifier ION (x=I: input, x=O: output ; y=P: plus, y=M: minus) DAS_OUT Signal D/A output o DAS_AI_x Signal D/A amplifier inputs (x=P: plus, x=M: minus) DAS_AO Signal D/A amplifier output N Table 1-2. Pin assignment Table 1-3 gives a more detailed pin map for the different pins. It also indicates the possible I/O configuration of these pins. The indications in blue bold are the configuration at start-up. The pins CNTx pins are possible counter inputs, PWMx are possible PWM outputs. © Semtech 2006 www.semtech.com 1-6

XE8805/05A pin function I/O configuration lqfp-64 first second third AI AO DI DO OD PU POWER 1 PA(0) CNTA X X 2 PA(1) CNTB X X 3 PA(2) CNTC X X r 4 PA(3) CNTD X X o 5 PA(4) X X 6 PA(5) X X f 7 PA(6) X X 8 PA(7) X X d 9 PC(0) X X 10 PC(1) X X e 11 PC(2) X X d 12 PC(3) X X 13 PC(4) X X n s 14 PC(5) X X 15 PC(6) Xe X n 16 PC(7) X X 17 PB(0) PWM0 X X m X X X X g 18 PB(1) PWM1 X X X X X X 19 PB(2) X X X X Xi X m s 20 PB(3) X X X X X X 21 PB(4) USRT_S0 X X X eX X X 22 PB(5) USRT_S1 o X X X X X X 23 PB(6) UART_Tx X X DX X X X 24 PB(7) UART_Rx c X X X X X X 25 DAB_R_P X e 26 DAB_R_M Xw 27 DAB_OUT R X 28 DAB_AO_P e X 29 DAB_AO_M X 30 DAB_AI_P t N X 31 DAB_AI_Mo X 33 VPP TEST X 35 AC_RN(3) X 36 AC_R(2) X 37 AC_A(7) X 38 AC_A(6) X 39 AC_A(5) X 40 AC_A(4) X 41 AC_A(3) X 42 AC_A(2) X 43 AC_A(1) X 44 AC_A(0) X 45 AC_R(1) X 46 AC_R(0) X 51 DAS_OUT X 52 DAS_AI_P X 53 DAS_AI_M X 54 DAS_AO X 55 VBAT X © Semtech 2006 www.semtech.com 1-7

XE8805/05A pin function I/O configuration lqfp-64 first second third AI AO DI DO OD PU POWER 56 VSS X 57 VSS_REG X 58 VREG X 60 VMULT X r 61 RESET X o 62 OSCOUT X 63 OSCIN X f Pin map table legend: d blue bold: configuration at start up e AI: analog input AO: analog output d DI: digital input DO: digital output OD: nMOS open drain output n s PU: pull-up resistor POWER: power supply e n Table 1-3. Pin description table m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 1-8

XE8805/05A 2 XE8805/05A Performance 2.1 Absolute maximum ratings 2-2 r 2.2 Operating range o 2-2 2.3 Supply configurations f 2-3 2.3.1 Flash circuit 2-3 2.3.2 ROM circuit d 2-3 2.4 Current consumption e 2-5 d 2.5 Operating speed 2-6 2.5.1 Flash version 2-6 n s 2.5.2 ROM circuit version 2-6 e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 2-1

XE8805/05A 2.1 Absolute maximum ratings Table 2-1. Absolute maximum ratings Min. Max. Note Voltage applied to VBAT with respect to VSS -0.3 6.0 V Voltage applied to VPP with respect to VSS VBAT-0.3 12 V Voltage applied to all pins except VPP and VBAT VSS-0.3 VBAT+0.3 V r Storage temperature (ROM device or unprogrammed -55 150 °C o flash device) Storage temperature (programmed flash device) -40 85 °Cf d Stresses beyond the absolute maximal ratings may cause permanent damage to the device. Functional operation at the absolute maximal ratings is not implied. Exposure to conditions beyond the absolute maximal ratings may e affect the reliability of the device. d 2.2 Operating range n s e n Table 2-2. Operating range for the flash device m g Min. Max. Note Voltage applied to VBAT with respect to VSS 2.4 i5.5 V Voltage applied to VBAT with respect to VSS durming 3.3 s5.5 V 1 the flash programming e Voltage applied to VPP with respect to VSS VBAT 11.5 V o Voltage applied to all pins except VPP and VBAT VSS VBAT V D Operating temperature range -40 85 °C c Capacitor on VREG (flash version) 0.8 1.2 µF 2 Capacitor on VMULT e 1.0 3.0 nF 3 w R 1. During the programming of the device, the supply voltage should at least be equal to the supply voltage e used during normal operation. 2. The capacitor on VREG is mandatory. N 3. The capacittor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The multipliero has to be enabled if VBAT<3.0V. N Table 2-3. Operating range for the ROM device Min. Max. Note Voltage applied to VBAT with respect to VSS 2.4 5.5 V Voltage applied to all pins except VPP and VBAT VSS VBAT V Operating temperature range -40 125 °C Capacitor on VREG 0.1 1.2 µF 1 Capacitor on VMULT 1.0 3.0 nF 2 1. The capacitor may be omitted when VREG is connected to VBAT. 2. The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The multiplier has to be enabled if VBAT<3.0V. All specifications in this document are valid for the complete operating range unless otherwise specified. © Semtech 2006 www.semtech.com 2-2

XE8805/05A Table 2-4. Operating range of the Flash memory Min. Max. Note Retention time at 85°C 10 years 1 Retention time at 55°C 100 years 1 Number of programming cycles 10 2 1. Valid only if programmed using a programming tool that is qualified 2. Circuits can be programmed more than 10 times but after that, the retention time is no longer guaranteed. All qualification tests have been done after 10 cycles. r o 2.3 Supply configurations f d 2.3.1 Flash circuit e The flash version of the circuit can be run from a supply between 2.4V and 5.5V (Figure 2-1). The capacitor on VREG has to be connected at all times (value in Table 2-2) to guaradntee proper operation of the device. The capacitor on VMULT is only required if the circuit is to be operated below 3V. n s VBAT e n m g VREG 2.4V – 5.5V i m s e VMULT o C vreg D c C vmult e w VSS R e Figure 2-1. Supply configuration for the flaNsh circuit. t o 2.3.2 ROM circuit N For the ROM version, two possible operating modes exist: with and without voltage regulator. Using the voltage regulator, low power consumption will be obtained even with supply voltages above 2.4V. Without the voltage regulator (i.e. VREG short-circuited to VBAT), a higher speed can be obtained. 2.3.2.1 Low power operation In this case, the internal voltage regulator is used in order to maintain low power consumption independent from the supply voltage. The capacitor on VREG has to be connected at all times (value in Table 2-3) to guarantee proper operation of the device. The capacitor on VMULT has to be connected only when VBAT<3V. © Semtech 2006 www.semtech.com 2-3

XE8805/05A VBAT VREG 2.4V – 5.5V VMULT Cvreg r C vmult o VSS f d Figure 2-2. Supply voltage connections for low power operation of the ROM version. e 2.3.2.2 High speed operation d In this case, the internal voltage regulator is not used. The operantion speed of the csircuit can be increased with increasing supply voltage but the supply current will also increase. The capacitor on VMULT has to be connected e n only when VBAT<3V. In this case, the supply voltage can decrease down to 2.15V. Beware however that the zoomingADCTM will not run below 2.4V (see Figure 2-4). In this configuration, the circuit can not be used above m g 3.3V. i VBAT m s e o D VREG 2.15V – 3.3V c e w VMULT R e CvmuNlt t o VSS N Figure 2-3. Supply voltage connections for high speed operation of the ROM version. © Semtech 2006 www.semtech.com 2-4

XE8805/05A acquisition chain voltage multiplier DAB CPU parallel and serial ports RC and crystal oscillator VLD Counters and PWM DAS (without amplifier) r o 0 2.15 2.4 3.3 VBAT (V) f Figure 2-4. Operation range of the different circuit blocks d e 2.4 Current consumption d The tables below give the current consumption for the circuit in different configurations. The figures are indicative only and may change as a function of the actual software implemennted in the circuit. s Table 2-5 gives the current consumption for the flash versioen of the circuit. Thne peripherals are disabled. The parallel ports A and B are configured in input with pull up, the parallel port C is configured as an output. Their pins m g are not connected externally. The pin RESET is connected to VSS and the pin VPP/TEST is connected to VBAT. The inputs of the acquisition chain are connected to VSS. i m s Table 2-5. Typical current consumption of the XE8805 version (8k instructions flash memory) e Operation mode CPU RC oXtal Consumption comments Note D High speed CPU 1 MIPS 1 MHz Off 310 µA 2.4V<>5.5V, 27°C c Low power CPU 32 kIPS Off 32 kHz 10 µA 2.4V <>5.5V, 27°C Low power time HALT eOff 32 kHz w 1.0 µA 2.4V <>5.5V, 27°C keeping R Fast wake-up HALT Ready 32kHz 1.7 µA 2.4V <>5.5V, 27°C e time keeping Immediate wake- H ALT 100 kHz Off 1.4 µA 2.4V <>5.5V, 27°C N up time keeping t VLD static currento 15 µA 2.4V <>5.5V, 27°C 16 bit resolution HALT 2 MHz Off 190 µA 3.0V, 27°C 1 N data acquisition 12 bit , gain 100, HALT 2 MHz Off 460 µA 3.0V, 27°C 2 data acquisition 1. PGA disabled, ADC enabled, 16 bit resolution 2. PGA 1 disabled, PGA 2 and 3 enabled, ADC enabled, 12 bit resolution For more information concerning the current consumption of the zoomingADCTM, see the chapter power consumption in the acquisition chain documentation which shows the current consumption of this block as a function of temperature and voltage and for different configurations of the PGA and ADC. The power consumption of the ROM version of the circuit is identical if it is configured as shown in Figure 2-2. In the high speed configuration, the current consumption will increase proportional with VBAT. © Semtech 2006 www.semtech.com 2-5

XE8805/05A 2.5 Operating speed 2.5.1 Flash version The speed of the devices is not highly dependent upon the supply voltage. However, by limiting the temperature range, the speed can be increased. The minimal guaranteed speed as a function of the supply voltage and maximal temperature operating temperature is given in Figure 2-5. r o 4 S) 3 f P MI d ( 2 d e e 1 p 85°C 45°C e s 0 d 2 2.5 3 3.5 4 4.5 5 5.5 supply voltage VBAT (V) n s e n Figure 2-5. Guaranteed speed as a function of the supply voltage and maximal temperature. m g 2.5.2 ROM circuit version i m s 2.5.2.1 Low power supply configuration e o D In the low power supply configuration as shown in Figure 2-2, the operating speed does not depend highly on the c supply voltage as shown in Figure 2-6. e w 85°C 45°C 125°C R 3.5 e 3 S) P 2.5 t N MI 2 d ( 1.5 o e e 1 p N s 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 supply voltage VBAT (V) Figure 2-6. Guaranteed speed as a function of supply voltage and for different maximal temperatures using the voltage regulator. 2.5.2.2 High speed supply configuration In the high speed supply configuration of Figure 2-3, the guaranteed speed of the circuit is shown in Figure 2-7. © Semtech 2006 www.semtech.com 2-6

XE8805/05A 85°C 45°C 125°C 4 ) S 3 P MI ( 2 d e pe 1 s r 0 o 2 2.2 2.4 2.6 2.8 3 3.2 3.4 f supply voltage VBAT (V) d Figure 2-7. Guaranteed speed as a function of supply voltage and for three temperature ranges when VREG=VBAT. e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 2-7

XE8805/05A 3. CPU CONTENTS r 3.1 CPU description o 3-2 f 3.2 CPU internal registers 3-2 d 3.3 CPU instruction short reference 3-4 e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 3-1

XE8805/05A 3.1 CPU description The CPU of the XE8000 series is a low power RISC core. It has 16 internal registers for efficient implementation of the C compiler. Its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. The circuit therefore runs on 1 MIPS on a 1MHz clock. The CPU hardware and software description is given in the document “Coolrisc816 Hardware and Software r Reference Manual”. A short summary is given in the following paragraphs. o The good code efficiency of the CPU core makes it possible to compute a polynomial like f Z =(A0 + A1⋅Y)⋅X +B0 +B1⋅Y in less than 300 clock cycles (software code generated by the XEMICS C- compiler, all numbers are signed integers on 16 bits). d e 3.2 CPU internal registers d As shown in Figure 3-1, the CPU has 16 internal 8-bit registers. Sonme of these registesrs can be concatenated to a 16-bit word for use in some instructions. The function of these registers is defined in Table 3-1. The status register stat (Table 3-2) is used to manage the different interrupt ande event levels. An innterrupt or an event can both be used to wake up after a HALT instruction. The difference is that an interrupt jumps to a special interrupt function whereas an event continues the software execution with tmhe instruction followging the HALT instruction. The program counter (PC) is a 16 bit register that indicates the addressi of the instruction that has to be executed. m s The stack (ST ) is used to memorise the return address when executing subroutines or interrupt routines. n e o program counter stack D c C T1 T2 T3 T4 e P S S Sw S R s u e b CPU on t cti Nr0 Instruction u o r st r1 memory n i Data memory N r2 s u 22bit sters ir03h i0l data b gi e r i1h i1l al n r i2h i2l e nt U i i3h i3l P C iph ipl stat a Figure 3-1. CPU internal registers © Semtech 2006 www.semtech.com 3-2

XE8805/05A Register name Register function r0 general purpose r1 general purpose r2 general purpose r3 data memory offset i0h MSB of the data memory index i0 i0l LBS of the data memory index i0 i1h MSB of the data memory index i1 i1l LBS of the data memory index i1 i2h MSB of the data memory index i2 r i2l LBS of the data memory index i2 o i3h MSB of the data memory index i3 i3l LBS of the data memory index i3 f iph MSB of the program memory index ip ipl LBS of the program memory index ip d stat status register a accumulator e Table 3-1. CPU internal register definition d n s bit name function 7 IE2 enables (when 1) the interrupt request of level 2 e n 6 IE1 enables (when 1) the interrupt request of level 1 5 GIE enables (when 1) all interrupt request levelsm g 4 IN2 interrupt request of level 2. The interrupts labelled “low” in the interrupt handler are routed to this interrupt level. This bit has to be cleared whien the interrupt is served. 3 IN1 interrupt request of level 1. The intmerrupts labelled “msid” in the interrupt handler are routed to this interrupt level. This bit has to be cleared when the interrupt is served. e 2 IN0 interrupt request of level 0. The interrupts labelled “hig” in the interrupt handler are o routed to this interrupt level. This bit has to beD cleared when the interrupt is served. 1 EV1 event request of level 1c. The events labelled “low” in the event handler are routed to this event level. This bit has to be cleared when the event is served. 0 EV0 event request of leevel 1. The events labelled “hig” in the event handler are routed to w this event level. This bit has to be cleared when the event is served. R Table 3-2. Status register description e N The CPU also has a tnumber of flags that can be used for conditional jumps. These flags are defined in Table 3-3. o N symbol name function Z zero Z=1 when the accumulator a content is zero C carry This flag is used in shift or arithmetic operations. For a shift operation, it has the value of the bit that was shifted out (LSB for shift right, MSB for shift left). For an arithmetic operation with unsigned numbers: it is 1 at occurrence of an overflow during an addition (or equivalent). it is 0 at occurrence of an underflow during a subtraction (or equivalent). V overflow This flag is used in shift or arithmetic operations. For arithmetic or shift operations with signed numbers, it is 1 if an overflow or underflow occurs. Table 3-3. Flag description © Semtech 2006 www.semtech.com 3-3

XE8805/05A 3.3 CPU instruction short reference Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The notation cc in the conditional jump instruction refers to the condition description as given in Table 3-6. The notation reg, reg1, reg2, reg3 refers to one of the CPU internal registers of Table 3-1. The notation eaddr and DM(eaddr) refer to one of the extended address modes as defined in Table 3-5. The notation DM(xxx) refers to the data memory location with address xxx. Instruction Modification Operation r o Jump addr[15:0] -,-,-, - PC := addr[15:0] Jump ip -,-,-, - PC := ip Jcc addr[15:0] -,-,-, - if cc is true then PC := addr[15:0] f Jcc ip -,-,-, - if cc is true then PC := ip Call addr[15:0] -,-,-, - STn+1 := STn (n>1); ST1 := PC+1; PC := addr[15:0] d Call ip -,-,-, - ST := ST (n>1); ST := PC+1; PC := ip n+1 n 1 Calls addr[15:0] -,-,-, - ip := PC+1; PC := addr[15:0] e Calls ip -,-,-, - ip := PC+1; PC := ip Ret -,-,-, - PC := ST; ST := ST (n>1) d 1 n n+1 Rets -,-,-, - PC := ip Reti -,-,-, - PC := ST1; STn := STn+1 (n>1); GIEn :=1 s Push -,-,-, - PC := PC+1; ST := ST (n>1); ST := ip n+1 n 1 Pop -,-,-, - PC := PC+1; ip := ST; ST := ST (n>1) 1 ne n+1 n Move reg,#data[7:0] -,-, Z, a a := data[7:0]; reg := data[7:0] Move reg1, reg2 -,-, Z, a a := reg2; reg1 := reg2m g Move reg, eaddr -,-, Z, a a := DM(eaddr); reg := DM(eaddr) Move eaddr, reg -,-,-, - DM(eaddr) := reg i Move addr[7:0],#data[7:0] -,-,-, - DM(addr[7:0]m) := data[7:0] s Cmvd reg1, reg2 -,-, Z, a a := reg2; if C=0 then reg1 := a; e Cmvd reg, eaddr -,-, Z, a a := DM(eaddr); if C=0 then reg := a o Cmvs reg1, reg2 -,-, Z, a a := reg2; if C=1 then reg1 := a; D Cmvs reg, eaddr -,-, Z, a a := DM(eaddr); if C=1 then reg := a c Shl reg1, reg2 C, V, Z, a a := reg2<<1; a[0] := 0; C := reg2[7]; reg1 := a Shl reg C, V, Z, a e a := reg<<1; a[0] := 0; C := reg[7]; reg := a w Shl reg, eaddr C, V, Z, a a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]; reg := a Shlc reg1, reg2 C, V, ZR, a a := reg2<<1; a[0] := C; C := reg2[7]; reg1 := a Shlc reg C, V, Z, a a := rege<<1; a[0] := C; C := reg[7]; reg := a Shlc reg, eaddr C, V, Z, a a := DM(eaddr)<<1; a[0] := C; C := DM(eaddr)[7]; reg := a Shr reg1, reg2 C, V, Z, a a := reg2>>1; a[7] := 0; C := reg2[0]; reg1 :=a N Shr reg tC, V, Z, a a := reg>>1; a[7] := 0; C := reg[0]; reg := a Shr reg, eaddr o C, V, Z, a a := DM(eaddr)>>1; a[7] := 0; C := DM(eaddr)[0]; reg := a Shrc reg1, reg2 C, V, Z, a a := reg2>>1; a[7] := C; C := reg2[0]; reg1 := a Shrc reg C, V, Z, a a := reg>>1; a[7] := C; C := reg[0]; reg := a N Shrc reg, eaddr C, V, Z, a a := DM(eaddr)>>1; a[7] := C; C := DM(eaddr)[0]; reg := a Shra reg1, reg2 C, V, Z, a a := reg2>>1; a[7] := reg2[7]; C := reg2[0]; reg1 := a Shra reg C, V, Z, a a := reg>>1; a[7] := reg[7]; C := reg[0]; reg := a Shra reg, eaddr C, V, Z, a a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0]; reg := a Cpl1 reg1, reg2 -,-, Z, a a := NOT(reg2); reg1 := a Cpl1 reg -,-, Z, a a := NOT(reg); reg := a Cpl1 reg, eaddr -,-, Z, a a := NOT(DM(eaddr)); reg := a Cpl2 reg1, reg2 C, V, Z, a a := NOT(reg2)+1; if a=0 then C:=1 else C := 0; reg1 := a Cpl2 reg C, V, Z, a a := NOT(reg)+1; if a=0 then C:=1 else C := 0; reg := a Cpl2 reg, eaddr C, V, Z, a a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0; reg := a Cpl2c reg1, reg2 C, V, Z, a a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0; reg1 := a Cpl2c reg C, V, Z, a a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0; reg := a Cpl2c reg, eaddr C, V, Z, a a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0; reg := a Inc reg1, reg2 C, V, Z, a a := reg2+1; if a=0 then C := 1 else C := 0; reg1 := a Inc reg C, V, Z, a a := reg+1; if a=0 then C := 1 else C := 0; reg := a Inc reg, eaddr C, V, Z, a a := DM(eaadr)+1; if a=0 then C := 1 else C := 0; reg := a Incc reg1, reg2 C, V, Z, a a := reg2+C; if a=0 and C=1 then C := 1 else C := 0; reg1 := a Incc reg C, V, Z, a a := reg+C; if a=0 and C=1 then C := 1 else C := 0; reg := a Incc reg, eaddr C, V, Z, a a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0; reg := a Dec reg1, reg2 C, V, Z, a a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a © Semtech 2006 www.semtech.com 3-4

XE8805/05A Dec reg C, V, Z, a a := reg-1; if a=hFF then C := 0 else C := 1; reg := a Dec reg, eaddr C, V, Z, a a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1; reg := a Decc reg1, reg2 C, V, Z, a a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg1 := a Decc reg C, V, Z, a a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a Decc reg, eaddr C, V, Z, a a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a And reg,#data[7:0] -,-, Z, a a := reg and data[7:0]; reg := a And reg1, reg2, reg3 -,-, Z, a a := reg2 and reg3; reg1 := a And reg1, reg2 -,-, Z, a a := reg1 and reg2; reg1 := a And reg, eaddr -,-, Z, a a := reg and DM(eaddr); reg := a Or reg,#data[7:0] -,-, Z, a a := reg or data[7:0]; reg := a Or reg1, reg2, reg3 -,-, Z, a a := reg2 or reg3; reg1 := a Or reg1, reg2 -,-, Z, a a := reg1 or reg2; reg1 := a r Or reg, eaddr -,-, Z, a a := reg or DM(eaddr); reg := a o Xor reg,#data[7:0] -,-, Z, a a := reg xor data[7:0]; reg := a Xor reg1, reg2, reg3 -,-, Z, a a := reg2 xor reg3; reg1 := a f Xor reg1, reg2 -,-, Z, a a := reg1 xor reg2; reg1 := a Xor reg, eaddr -,-, Z, a a := reg or DM(eaddr); reg := a d Add reg,#data[7:0] C, V, Z, a a := reg+data[7:0]; if overflow then C:=1 else C := 0; reg := a Add reg1, reg2, reg3 C, V, Z, a a := reg2+reg3; if overflow then C:=1 else C :=e 0; reg1 := a Add reg1, reg2 C, V, Z, a a := reg1+reg2; if overflow then C:=1 else C := 0; reg1 := a Add reg, eaddr C, V, Z, a a := reg+DM(eaddr); if overflow then C:=d1 else C := 0; reg := a Addc reg,#data[7:0] C, V, Z, a a := reg+data[7:0]+C; if overflow then C:=1 else C := 0; reg := a Addc reg1, reg2, reg3 C, V, Z, a a := reg2+reg3+C; if overflow then C:=1 else C := 0; reg1 := a Addc reg1, reg2 C, V, Z, a a := reg1+reg2+C; if overflow thenn C:=1 else C := 0; reg1 s:= a Addc reg, eaddr C, V, Z, a a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0; reg := a Subd reg,#data[7:0] C, V, Z, a a := data[7:0]-reg; if underfloew then C := 0 else C := n1; reg := a Subd reg1, reg2, reg3 C, V, Z, a a := reg2-reg3; if underflow then C := 0 else C := 1; reg1 := a Subd reg1, reg2 C, V, Z, a a := reg2-reg1; if undemrflow then C := 0 else Cg := 1; reg1 := a Subd reg, eaddr C, V, Z, a a := DM(eaddr)-reg; if underflow then C := 0 else C := 1; reg := a Subdc reg,#data[7:0] C, V, Z, a a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1; reg := a Subdc reg1, reg2, reg3 C, V, Z, a a := reg2-reg3-(1-C); if underflow then Ci := 0 else C := 1; reg1 := a Subdc reg1, reg2 C, V, Z, a a := reg2-regm1-(1-C); if underflow thesn C := 0 else C := 1; reg1 := a Subdc reg, eaddr C, V, Z, a a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1; reg := a Subs reg,#data[7:0] C, V, Z, a a := reg-data[7:0]; if underflow tehen C := 0 else C := 1; reg := a Subs reg1, reg2, reg3 C, V, Z, a a :=o reg3-reg2; if underflow then C := 0 else C := 1; reg1 := a Subs reg1, reg2 C, V, Z, a a := reg1-reg2; if underfloDw then C := 0 else C := 1; reg1 := a Subs reg, eaddr C, V, Z, a ca := reg-DM(eaddr); if underflow then C := 0 else C := 1; reg := a Subsc reg,#data[7:0] C, V, Z, a a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1; reg := a Subsc reg1, reg2, reg3 C, V, Z, a a := reg3-reg2-(1-C ); if underflow then C := 0 else C := 1; reg1 := a e Subsc reg1, reg2 C, V, Z, a a := reg1-reg2-w(1-C); if underflow then C := 0 else C := 1; reg1 := a Subsc reg, eaddr C, V, Z, a a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1; reg := a R Mul reg,#data[7:0] u, u, u, a a := (daeta[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8] Mul reg1, reg2, reg3 u, u, u, a a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8] Mul reg1, reg2 u, u, u, a a N:= (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8] t Mul reg, eaddr u, u, u, a a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8] o Mula reg,#data[7:0] u, u, u, a a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8] Mula reg1, reg2, reg3 u, u, u, a a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8] Mula reg1, reg2 N u, u, u, a a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8] Mula reg, eaddr u, u, u, a a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8] Mshl reg,#shift[2:0] u, u, u, a a := (reg*2shift)[7:0]; reg := (reg*2shift)[15:8] Mshr reg,#shift[2:0] u, u, u, a a := (reg*2(8-shift)[7:0]; reg := (reg*2(8-shift)[15:8] Mshra reg,#shift[2:0] u, u, u, a* a := (reg*2(8-shift)[7:0]; reg := (reg*2(8-shift)[15:8] Cmp reg,#data[7:0] C, V, Z, a a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z) Cmp reg1, reg2 C, V, Z, a a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z) Cmp reg, eaddr C, V, Z, a a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z) Cmpa reg,#data[7:0] C, V, Z, a a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z) Cmpa reg1, reg2 C, V, Z, a a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z) Cmpa reg, eaddr C, V, Z, a a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z) Tstb reg,#bit[2:0] -, -, Z, a a[bit] := reg[bit]; other bits in a are 0 Setb reg,#bit[2:0] -, -, Z, a reg[bit] := 1; other bits unchanged; a := reg Clrb reg,#bit[2:0] -, -, Z, a reg[bit] := 0; other bits unchanged; a := reg Invb reg,#bit[2:0] -, -, Z, a reg[bit] := not reg[bit]; other bits unchanged; a := reg © Semtech 2006 www.semtech.com 3-5

XE8805/05A Sflag -,-,-, a a[7] := C; a[6] := C xor V; a[5] := ST full; a[4] := ST empty Rflag reg C, V, Z, a a := reg << 1; ; a[0] := 0; C := reg[7] Rflag eaddr C, V, Z, a a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7] Freq divn -,-,-, - reduces the CPU frequency (divn=nodiv, div2, div4, div8, div16) Halt -,-,-, - halts the CPU Nop -,-,-, - no operation r - = unchanged, u = undefined, *MSHR reg,# 1 doesn’t shift by 1 o Table 3-4. Instruction short reference f The Coolrisc816 has 8 different addressing modes. These modes are described in Table 3-5. In this table, the notation ix refers to one of the data memory index registers i0, i1, i2 or i3. Using edaddr in an instruction of Table 3-4 will access the data memory at the address DM(eaddr) and will simultaneously execute the index operation. e extended address accessed data memory index d eaddr location operation DM(eaddr) addr[7:0] DM(h00&addr[7:0]) - direct addressing n s (ix) DM(ix) - indexed addressing (ix, offset[7:0]) DM(ix+offset) - indexed adedressing with immediate noffset (ix,r3) DM(ix+r3) - indexed addressing with register offset (ix)+ DM(ix) ix := ix+1 indexmed addressing with indexg post-increment (ix,offset[7:0])+ DM(ix+offset) ix := ix+offset indexed addressing with index post-increment by the offset -(ix) DM(ix-1) ix := ix-1 indexed addressing withi index pre-decrement -(ix,offset[7:0]) DM(ix-offset) ix := ix -offsetm indexed addressing swith index pre-decrement by the offset Table 3-5. Extended address mode description e o D Eleven different jump conditions are implemented as shown in Table 3-6. The contents of the column CC in this c table should replace the CC notation in the instruction description of Table 3-4. e w CC condition R CS C=1 CC C=0 e ZS Z=1 ZC Z=0 t N VS V=1o VC V=0 EV (EVN1 or EV0)=1 After CMP op1,op2 EQ op1=op2 NE op1≠op2 GT op1>op2 GE op1≥op2 LT op1<op2 LE op1≤op2 Table 3-6. Jump condition description © Semtech 2006 www.semtech.com 3-6

XE8805/05A 4 Memory Mapping 4.1 Memory organisation 4-2 r 4.2 Quick reference data memory register map 4-2 4.2.1 Low power data registers (h0000-h0007) o 4-3 4.2.2 System, clock configuration and reset configuration (h0010-h001F) 4-4 4.2.3 Port A (h0020-h0027) f 4-4 4.2.4 Port B (h0028-h002F) 4-4 d 4.2.5 Port C (h0030-h0033) 4-5 4.2.6 Flash programming (h0038-003B) 4-5 e 4.2.7 Event handler (h003C-h003F) 4-5 4.2.8 Interrupt handler (h0040-h0047) d 4-6 4.2.9 USRT (h0048-h004F) 4-7 4.2.10 UART (h0050-h0057) n s 4-7 4.2.11 Counter/Timer/PWM registers (h0058-h005F) 4-7 4.2.12 Acquisition chain registers (h0060-h0067) e n 4-8 4.2.13 Signal D/A registers (h0074-h0077) 4-8 4.2.14 Bias D/A registers (h0078-h0079) m g 4-8 4.2.15 Voltage multiplier (h007C) 4-8 4.2.16 Voltage Level Detector registers (h007E-h007F) i 4-9 4.2.17 RAM (h0080-h027F) m s 4-9 e o D c e w R e N t o N © Semtech 2006 www.semtech.com 4-1

XE8805/05A 4.1 Memory organisation The XE8805 CPU is built with a Harvard architecture. The Harvard architecture uses separate instruction and data memories. The instruction bus and data bus are also separated. The advantage of such a structure is that the CPU can get a new instruction and read/write data simultaneously. The circuit configuration is shown in Figure 4-1. The CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit instructions. The data memory space has 8 low power registers, the peripheral register space and 512 bytes of RAM. r o µF µF 0h1FFF 0h027F f CPU RAM d capacity: bus e 512 bytes ction r0 d Instruction u str r1 n s ry memory n o i m r2 e n s e 8cka pxa 2ci2tbyi:t gisters ir03h i0l m data buig 0h0080 Data m e nal r i1h m i1l s 0h007F U inter oii32hh ii32ll D e Preergipishteerrsa l P Cc iph ipl 0h0008 stat Low power e w RAM a 0h0000 R 0h0000 e N t Figure 4-1. Memory mapping o The CPU inteNrnal registers are described in the CPU chapter. A short reference of the low power registers and peripheral registers is given in 4.2. 4.2 Quick reference data memory register map The data register map is given in the tables below. A more detailed description of the different registers is given in the detailed description of the different peripherals. The tables give the following information: 1. The register name and register address 2. The different bits in the register 3. The access mode of the different bits (see Table 4-1 for code description) 4. The reset source and reset value of the different bits The reset source coding is given in Table 4-2. To get a full description of the reset sources, please refer to the reset block chapter. © Semtech 2006 www.semtech.com 4-2

XE8805/05A code access mode r bit can be read w bit can be written r0 bit always reads 0 r1 bit always reads 1 c bit is cleared by writing any value c1 bit is cleared by writing a 1 ca bit is cleared after reading s special function, verify the detailed description in the respective peripherals r Table 4-1. Access mode codes used in the register definitions o code reset source f sys resetsystem cold resetcold d pconf resetpconf sleep resetsleep e Table 4-2. Reset source coding used in the register definitions d n s 4.2.1 Low power data registers (h0000-h0007) e n Name Address 7 6 5 4 m 3 2 g 1 0 Reg00 Reg00[7:0] h0000 rw, xxxxxxxx,- Reg01 Reg01[7:0] i h0001 m rw,xxxxxxxx,- s Reg02 Reg02[7:0] h0002 rw,xxxxxxxx,- e Reg03 o Reg03[7:0] h0003 rw,xxxxxxxDx,- Reg04 c Reg04[7:0] h0004 rw,xxxxxxxx,- Reg05 Re g05[7:0] e h0005 wrw,xxxxxxxx,- Reg06 Reg06[7:0] R h0006 rw,xxxxxxxx,- Reg07 e Reg07[/:0] h0007 rw,xxxxxxxx,- N t Table 4-3. Low power data registers o N © Semtech 2006 www.semtech.com 4-3

XE8805/05A 4.2.2 System, clock configuration and reset configuration (h0010-h001F) Name Address 7 6 5 4 3 2 1 0 RegSysCtrl SleepEn EnResPConf EnBusError EnResWD h0010 rw,0,cold rw,0,cold rw,0,cold rw,0,cold r0 r0 r0 r0 RegSysReset Sleep ResetBusError ResetWD ResetfromportA ResPad ResPadSleep h0011 rw,0,sys rc, 0, cold rc, 0, cold rc, 0, cold rc,0,cold rc,0,cold r0 RegSysClock CpuSel ExtClk EnExtClock BiasRC ColdXtal ColdRC EnableXtal EnableR C h0012 rw,0,sleep r,0,cold rw,0,cold rw,1,cold r,1,sleep r,1,sleep rw,0,sleep rw,1,rsleep RegSysMisc RCOnPA0 DebFast OutputCkXtal OoutputCpuCk h0013 r0 r0 r0 r0 rw,0,sleep rw,0,sleep rw,0,sleep rw,0,sleep RegSysWd WatchDog[3:0] f h0014 r0 r0 r0 r0 s,0000,cold RegSysPre0 ResPre h0015 r0 r0 r0 r0 r0 r0 dr0 c1r0,0,- RegSysRcTrim1 Reserved RcFreqRange RcFreqCoarse[3:0] h001B r0 r0 rw,0,cold rw,0,cold rw,e0000,cold RegSysRcTrim2 RcFreqFine[5:0] h001C r0 r0 rw,10000,cold d Table 4-4. Reset block and clock block registers n s 4.2.3 Port A (h0020-h0027) e n Name m g Address 7 6 5 4 3 2 1 0 RegPAIn PAIn[7:0] i h0020 m r s RegPADebounce PADebounce[7:0] h0021 rw,00000000,pconf e RegPAEdge PAEdge[7:0] o h0022 rw,00000000,sys RegPAPullup PAPullupD[7:0] h0023 c rw,00000000,pconf RegPARes0 PARes0[7:0] h0024 e rw, 00000000, sys w RegPARes1 PARes1[7:0] h0025 R rw,00000000,sys Table 4-5. Port A registers e N t 4.2.4 Port B (h0028-h002F) o NamNe Address 7 6 5 4 3 2 1 0 RegPBOut PBOut[7:0] h0028 rw,00000000,pconf RegPBIn PBIn[7:0] h0029 r RegPBDir PBDir[7:0] h002A rw,00000000,pconf RegPBOpen PBOpen[7:0] h002B rw,00000000,pconf RegPBPullup PBPullup[7:0] h002C rw,00000000,pconf RegPBAna PBAna[3:0] h002D r0 r0 r0 r0 rw,0000,pconf Table 4-6. Port B registers © Semtech 2006 www.semtech.com 4-4

XE8805/05A 4.2.5 Port C (h0030-h0033) Name Address 7 6 5 4 3 2 1 0 RegPCOut PCOut[7:0] h0030 rw,00000000,pconf RegPCIn PCIn[7:0] h0031 r,-,- RegPCDir PD1Dir[7:0] h0032 rw,00000000,pconf r o Table 4-7. Port C registers f 4.2.6 Flash programming (h0038-003B) d These four registers are used during flash programming only. Refer to the flash programming algorithm documentation for more details. e d 4.2.7 Event handler (h003C-h003F) n s Name e n Address 7 6 5 4 3 2 1 0 RegEvn CntIrqA CntIrqC 128Hz PAEvn[1] CntIrqB CntIrqD 1Hz PAEvn[0] m g h003C rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys RegEvnEn EvnEn[7:0] h003D rw,00000000,sys i RegEvnPriority m EvnPriority[7:0] s h003E r,11111111,sys RegEvnEvn e EvnHigh EvnLow h003F r0 r0 r0o r0 r0 r0 r,0,sys r,0,sys D Table 4-8. Event handler registers c The origin of the different events ies summarised in the table below. w R Event Event source e CntIrqA Counter/Timer A (counter block) CntIrqB Count er/Timer B (counter block) N t CntIrqC Counter/Timer C (counter block) o CntIrqD Counter/Timer D (counter block) 128Hz Low prescaler (clock block) N 1Hz Low prescaler (clock block) PAEvn[1:0] Port A Table 4-9. Event source description © Semtech 2006 www.semtech.com 4-5

XE8805/05A 4.2.8 Interrupt handler (h0040-h0047) Name Address 7 6 5 4 3 2 1 0 RegIrqHig IrqAC 128Hz CntIrqA CntIrqC UartIrqTx UartIrqRx h0040 rc1,0,sys rc1,0,sys r0 rc1,0,sys rc1,0,sys r0 rc1,0,sys rc1,0,sys RegIrqMid UsrtCond1 UrstCond2 PAIrq[5] PAIrq[4] 1Hz VldIrq PAIrq[1] PAIrq[0] h0041 rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys RegIrqLow PAIrq[7] PAIrq[6] CntIrqB CntIrqD PAIrq[3] PAIrq[2] h0042 rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys rc1,0,sys r0 rr0 RegIrqEnHig IrqEnHig[7:0] o h0043 rw,0000000,sys RegIrqEnMid IrqEnMid[7:0] f h0044 rw,0000000,sys RegIrqEnLow IrqEnLow[7:0] h0045 rw,0000000,sys d RegIrqPriority IrqPriority[7:0] h0046 r,11111111,sys e RegIrqIrq IrqHig IrqMid IrqLow h0047 r0 r0 r0 r0 r0 r,0,sys r,0,sys r,0,sys d Table 4-10. Interrupt handler registers n s The origin of the different interrupts is summarised in the tablee below. n Event Event source m g CntIrqA Counter/Timer A (counter block) CntIrqB Counter/Timer B (counter block) i CntIrqC Counter/Timer C (counter block) m s CntIrqD Counter/Timer D (counter block) e 128Hz Low prescaler (clock block) o 1Hz Low prescaler (clock block) D PAIrq[7:0] Port A c UartIrqRx UART reception UartIrqTx UART transmisseion w UrstCond1 USRT condition 1 R UsrtCond2 USRT condition 2 e VldIrq Voltage level detector IrqAC Acquisition chain end ofN conversion interrupt t Table 4-11. Interruopt source description N © Semtech 2006 www.semtech.com 4-6

XE8805/05A 4.2.9 USRT (h0048-h004F) Name Address 7 6 5 4 3 2 1 0 RegUsrtS1 UsrtS1 h0048 r0 r0 r0 r0 r0 r0 r0 s,1,sys RegUsrtS0 UsrtS0 h0049 r0 r0 r0 r0 r0 r0 r0 s,1,sys RegUsrtCond1 UsrtCon d1 h004A r0 r0 r0 r0 r0 r0 r0 rc,0r,sys RegUsrtCond2 UosrtCond2 h004B r0 r0 r0 r0 r0 r0 r0 rc,0,sys RegUsrtCtrl UsrtWaitS0 UsrtEnWaitCond1 UsrtEnWaitS0 UsrtEnable h004C r0 r0 r0 r0 r,0,sys rw,0,sys rw,0,syfs rw,0,sys RegUsrtBufferS1 UsrtBufferS1 h004D r0 r0 r0 r0 r0 r0 dr0 r,0,sys RegUsrtEdgeS0 UsrtEdgeS0 h004E r0 r0 r0 r0 r0 r0 e r0 r,0,sys Table 4-12. USRT register description d 4.2.10 UART (h0050-h0057) n s Name e n Address 7 6 5 4 3 2 1 0 RegUartCtrl UartEcho UartEnRx1 UartEnTx UartXRx m UartXTx gUartBR[2:0] h0050 rw,0,sys rw,0,sys rw,0,sys rw,0,sys rw,0,sys rw,101,sys RegUartCmd SelXtal UartEnRx2 UartRcSel[2:0] UartPM UartPE UartWL i h0051 rw,0,sys rw,0,sys rwm,000,sys srw,0,sys rw,0,sys rw,1,sys RegUartTx UartTx[7:0] h0052 rw,0000000,sys e RegUartTxSta UartTxBusy UartTxFull o h0053 r0 r0 r0 r0 r0 r0 r,0,sys r,0,sys RegUartRx UartRx[7D:0] h0054 c r,00000000,sys RegUartRxSta UartRxSErr UartRxPErr UartRxFErr UartRxOerr UartRxBusy UartRxFull h0055 r0 r0 e r,0,sys r,0,sys r,0,sys rc,0,sys r,0,sys r,0,sys w Table 4-13. UART register description R e N 4.2.11 Counter/Ttimer/PWM registers (h0058-h005F) o Name Address N 7 6 5 4 3 2 1 0 RegCntA CounterA[7:0] h0058 s,xxxxxxxx,- RegCntB CounterB[7:0] h0059 s,xxxxxxxx,- RegCntC CounterC[7:0] h005A s,xxxxxxxx,- RegCntD CounterD[7:0] h005B s,xxxxxxxx,- RegCntCtrlCk CntDCkSel[1:0] CntCCkSel[1:0] CntBCkSel[1:0] CntACkSel[1:0] h005C rw,xx,- rw,xx,- rw,xx,- rw,xx,- RegCntConfig1 CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0 h005D rw,x,- rw,x,- rw,x,- rw,x,- rw,x,- rw,x,- rw,0,sys rw,0,sys RegCntConfig2 CapSel[1:0] CapFunc[1:0] Pwm1Size[1:0] Pwm0Size[1:0] h005E rw,00,sys rw,00,sys rw,xx,- rw,xx,- RegCntOn CntDEnable CntCEnable CntBEnable CntAEnable h005F r0 r0 r0 r0 rw,0,sys rw,0,sys rw,0,sys rw,0,sys Table 4-14. Counter/timer/PWM register description. © Semtech 2006 www.semtech.com 4-7

XE8805/05A 4.2.12 Acquisition chain registers (h0060-h0067) Name Address 7 6 5 4 3 2 1 0 RegAcOutLsb OUT[7:0] h0060 r,0,sys RegAcOutMsb OUT[15:8] h0061 r,0,sys RegAcCfg0 START SET_NELCONV[1:0] SET_OSR[2:0] CONT h0062 w r0,0,sys rw,01,sys rw,010,sys rw,0,sys r0 RegAcCfg1 IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] h0063 rw,11,sys rw,11,sys rw,0000,sys r RegAcCfg2 FIN PGA2_GAIN[1:0] PGA2_OFFSET[3:0] h0064 rw,00,sys rw,00,sys rw,0000,sys o RegAcCfg3 PGA1_GAIN PGA3_GAIN[6:0] h0065 Rw,0,sys rw,0000000,sys f RegAcCfg4 PGA3_OFFSET h0066 r0 rw,0000000,sys d RegAcCfg5 BUSY DEF AMUX[4:0] VMUX h0067 r,0,sys w r0 rw,00000,sys rw,0,sys e Table 4-15. Acquisition chain register description. d 4.2.13 Signal D/A registers (h0074-h0077) n s Name e n Address 7 6 5 4 3 2 1 0 RegDasInLsb DasInLmsb(7:0) g h0074 rw,00000000,sys RegDasInMsb DasInMsb(7:0) h0075 rw,00000000,sys i RegDasCfg0 NsOrder(1:0) CodemLmax(2:0) s Enable(1:0) Fin h0076 rw,00,sys rw,000,sys rw,00,sys rw,0,sys RegDasCfg1 e BW Inv h0077 r0 r0 r0o r0 r0 r0 rw,0,sys rw,0,sys D Table 4-16. Signal D/A register description c 4.2.14 Bias D/A registers (h0e078-h0079) w R Name Address 7 6 5 e 4 3 2 1 0 RegDabIn DabIn(7:0) h0078 t N rw,00000000,sys RegDabCfg Enable(1:0) o h0079 r0 r0 r0 r0 r0 r0 rw,00,sys Table 4-17. BNias D/A register description 4.2.15 Voltage multiplier (h007C) Name Address 7 6 5 4 3 2 1 0 RegVmultCfg0 Enable Fin[1:0] h007C r0 r0 r0 r0 r0 rw,0,sys rw,00,sys Table 4-18. VMULT register. © Semtech 2006 www.semtech.com 4-8

XE8805/05A 4.2.16 Voltage Level Detector registers (h007E-h007F) Name Address 7 6 5 4 3 2 1 0 RegVldCtrl VldRange VldTune[2:0] h007E r0 r0 r0 r0 rw,0,sys rw,000,sys RegVldStat VldResult VldValid VldEn h007F r0 r0 r0 r0 r0 r,0,sys r,0,sys rw,0,sys Table 4-19. Voltage level detector register description r o 4.2.17 RAM (h0080-h027F) f The 512 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables stored in the RAM should be initialised before use since they can have any value at circuit start up. d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 4-9

XE8805/05A 5 System Block 5.1 Overview r 5-2 o 5.2 Operating mode 5-2 f d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 5-1

XE8805/05A 5.1 Overview The XE8000 chips have three operating modes. There is the normal, the low current and the very low current modes (see Figure 5-1). The different modes are controlled by the reset and clock blocks (see the documentation of the respective blocks). 5.2 Operating mode Start-up r All bits are reset in the design when a POR (power-on-reset) is active. o RC is enabled, Xtal is disabled and the CPU is reset (pmaddr = 0000). If Port A is used to return from the sleep mode, all bits with resetcold don’t change (sefe sleep mode). Reset d All bits with resetsystem and resetpconf (if enabled) are reset. Clock configuration doesn’t change except cpuck. The CPU is reset. e d Active mode This is the mode where the CPU and all peripherals can work and execute the embedded software. n s Standby mode e n Executing a HALT instruction moves the XE8805 into the Standby mode. The CPU is stopped, but the clocks remain active. Therefore, the enabled peripherals remainm active e.g. for timeg keeping. A reset or an interrupt/event request (if enabled) cancels the standby mode. i Sleep mode m s This is a very low-power mode because all circuit clocks and all peripherals are stopped. Only some service blocks remain active. No time-keeping is possible. Two instructions aree necessary to move into sleep mode. First, the o SleepEn (sleep enable) bit in RegSysCtrl has to be set to 1. The sleep mode can then be activated by setting the D Sleep bit in RegSysReset to 1. c There are three possibe ways to wake-up from the slee p mode: e w 1. The por (power-on-reset caused by a power-down followed by power-on). The RAM information is lost. 2. The padreset R 3. The Port A reset combination (if ethe Port A is present in the product). See Port A documentation for more details. t N Note: If the Porto A is used to return from the sleep mode, all bits with resetcold don’t change (RegSysCtrl, RegSysReset (except bit sleep), EnExtClock and BiasRc in RegSysClock, RegSysRcTrim1 and RegSNysRcTrim2). The SleepFlag bit in RegSysReset, reads back a 1 if the circuit was in sleep mode since the flag was last cleared (see reset block for more details). Note: For a lower power consumption, disable the BiasRc bit in RegSysClock before to going to sleep mode. The start-up time of the oscillator will then be longer however. Note: It is recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode because this instruction can be executed when the sleep mode is left using the resetfromportA. © Semtech 2006 www.semtech.com 5-2

XE8805/05A START-UP r without por o condition f d por RESET e podr por padreset padreset portA reset portA reset watchdog reset n s without padreset condition portA reset e n watchdog reset buserror reset m g i Halt instruction m s ACTIVE STAND-BY SLEEP Interrupt/event e o D c set bit slee p e w R normal mode low current very low current e Figure 5-1. XE8805 otperating modes. N o N © Semtech 2006 www.semtech.com 5-3

XE8805/05A 6 Reset Block 6.1 Features r 6-2 o 6.2 Overview 6-2 f 6.3 Register map 6-2 d 6.4 Reset handling capabilities 6-3 e 6.5 Reset source description d 6-4 6.5.1 Power On Reset 6-4 6.5.2 RESET pin n s 6-4 6.5.3 Programmable Port A input combination 6-4 6.5.4 Watchdog reset e n 6-4 6.5.5 BusError reset 6-4 6.5.6 Sleep mode m g 6-4 6.6 Control register description and operation i 6-4 m s 6.7 Watchdog 6-5 e o 6.8 Start-up and watchdog specifications D 6-5 c e w R e N t o N © Semtech 2006 www.semtech.com 6-1

XE8805/05A 6.1 Features • Power On Reset (POR) • External reset from the RESET pin • Programmable Watchdog timer reset • Programmable BusError reset • Sleep mode management • Programmable Port A input combination reset r 6.2 Overview o The reset block is the reset manager. It handles the different reset sources and dfistributes them through the system. It also controls the sleep mode of the circuit. d 6.3 Register map e d Pos. RegSysCtrl Rw Reset Function 7 SleepEn r w 0 resetcold enables Sleep mode n s 0: sleep mode is disabled 1: sleep mode eis enabled n 6 EnResPConf r w 0 resetcold enables the resetpconf signal when the resetglobalm is active g 0: resetpconf is disabled 1: resetpconf is enabled i 5 EnBusError r w 0 resetcold enambles reset from BusEsrror 0: BusError reset source is disabled 1: BusError reset esource is enabled 4 EnResWD r w 0 resetcold o enables reset from Watchdog 0: WatchdogD reset source is disabled c 1: Watchdog reset source is enabled this bit can not be set to 0 by SW 3 – 0 - r 00e00 unuswed Table 6-1. RegSysCtrl registRer. e N t Pos. RegSysReset Rw Reset Function o 7 Sleep rw 0 resetsystem Sleep mode control (reads always 0) 6 - r 0 unused N 5 ResetBusError r c 0 resetcold reset source was BusError 4 ResetWD r c 0 resetcold reset source was Watchdog 3 ResetfromportA r c 0 resetcold reset source was Port A combination 2 ResPad r c 0 resetcold reset source was reset pad 1 ResPadSleep r c 0 resetcold reset source was reset pad in sleep mode 0 - r 0 unused Table 6-2. RegSysReset register © Semtech 2006 www.semtech.com 6-2

XE8805/05A Pos. RegSysWD Rw Reset Function 7 – 4 - r 0000 unused WDKey[3] w Watchdog Key bit 3 3 0 resetcold WDCounter[3] r Watchdog counter bit 3 WDKey[2] w Watchdog Key bit 2 2 0 resetcold WDCounter[2] r Watchdog counter bit 2 WDKey[1] w Watchdog Key bit 1 1 0 resetcold WDCounter[1] r Watchdog counter bit 1 WDKey[0] w Watchdog Key bit 0 r 0 0 resetcold WDCounter[0] r Watchdog counter bit 0 o Table 6-3. RegSysWD register f 6.4 Reset handling capabilities d e There are 5 reset sources: • Power On Reset (POR) d • External reset from the RESET pin • Programmable Port A input combination n s • Programmable watchdog timer reset • Programmable BusError reset on processor access oeutside the allocatedn memory map Another reset source is the bit Sleep in the RegSysResemt register. This sougrce is fully controlled by software and is only used during the sleep mode. i Four internal reset signals are generated from thesme sources and distsributed through the system: • resetcold: is asserted on POR e • resetsystem: is asserted when resetcold or any other enabled reset source is active o • resetpconf: is asserted when resetsystem is actiDve and if the EnResPConf bit in the RegSysCtrl register is set. This recset is generally used in the different ports. It allows to maintain the port configuration unchanged while the rest of the circuit is reset. • resetsleep: is asserteed when the circuit is in sleep mode w R For the circuits XE8801A and XE8805A (2) For the circuits XE8801 and XE8805 e Table 6-4 shows a sum mary of the dependency of the internal reset signals on the various reset sources. In all the N tables describing thet different registers, the reset source is indicated. o Internal reset signals N Asserted resetpconf reset source resetsystem when when resetsleep resetcold EnResPConf=0 EnResPConf=1 POR Asserted Asserted Asserted Asserted Asserted RESET pin (1) Asserted Asserted Asserted Asserted Asserted RESET pin (2) Asserted - Asserted - - PortA input Asserted - Asserted - - Watchdog Asserted - Asserted - - BusError Asserted - Asserted - - Sleep - - - Asserted - (1) For the circuits XE8801A and XE8805A (2) For the circuits XE8801 and XE8805 Table 6-4. Internal reset assertion as a function of the reset source. © Semtech 2006 www.semtech.com 6-3

XE8805/05A 6.5 Reset source description 6.5.1 Power On Reset The power on reset (POR) monitors the external supply voltage. It activates a reset on a rising edge of this supply voltage. The reset is inactivated only if the internal voltage regulator has started up. No precise voltage level detection is performed by the POR block. 6.5.2 RESET pin r o The reset can be activated by applying a high input state on the RESET pin. f 6.5.3 Programmable Port A input combination d A reset signal can be generated by Port A. See the description of the Port A for further information. e 6.5.4 Watchdog reset d The Watchdog will generate a reset if the EnResetWD bit in the RegSysCtrl register has been set and if the watchdog is not cleared in time by the processor. See chapter 6.7 dnescribing the watchsdog for further information. e n 6.5.5 BusError reset m g The address space is assigned as shown in the register map of the product. If the EnBusError bit in the RegSysCtrl register is set and a non-existant address is accessed by thie software, a reset is generated. m s 6.5.6 Sleep mode e o Entering the sleep mode will reset a part of the circuit. The reset is used to configure the circuit for correct wake-up D after the sleep mode. If the SleepEn bit in the RegSysCtrl register has been set, the sleep mode can be entered c by setting the bit Sleep in RegSysReset. During the sleep mode, the resetsleep signal is active. For detailed information on the sleep mode, seee the system documentation. w 6.6 Control register dRescription and operation e Two registers are ded icated for reset status and control, RegSysReset and RegSysCtrl. The bits Sleep, and N t SleepEn are also located in those registers and are described in the chapter dedicated to the different operating modes of the circuoit (system block). N The RegSysReset register gives information on the source which generated the last reset. It can be read at the beginning of the application program to detect if the circuit is recovering from an error or exception condition, or if the circuit is starting up normally. • when ResBusError is 1, a forbidden address access generated the reset. • when ResWD is 1, the watchdog generated the reset. • when ResPortA is 1, a PortA combination generated the reset. • when ResPad is 1, a reset pin generated the reset. • when ResPadSleep is 1, a reset pin in sleep mode generated the reset. Note: If no bit is set to 1, the reset source was the internal POR. Note: Several bits might be set or not, if the register was not cleared in between 2 reset occurrences. Write any value in RegSysReset to clear it. Note: When a reset pin wakes up the chip from the sleep mode, ResPad and ResPadSleep bits are equal at 1. The last bit concerns the sleep mode control (see system documentation for the sleep mode description). © Semtech 2006 www.semtech.com 6-4

XE8805/05A • when Sleep is set to 1, and SleepEn is 1, the sleep mode is entered. The bit always reads back a 0. The RegSysCtrl register enables the different available reset sources and the sleep mode. • EnResWD enables the reset due to the watchdog (can not be disabled once enabled). • EnBusError enables the reset due to a bus error condition. • EnResPConf enables the reset of the port configurations when reset by Port A, a Bus Error or the watchdog. • SleepEn unlocks the Sleep bit. As long as SleepEn is 0, the Sleep bit has no effect. r o 6.7 Watchdog f The watchdog is a timer which has to be cleared at least every 2 seconds by thed software to prevent a reset being generated by the timeout condition. e The watchdog can be enabled by software by setting the EnResWD bit in the RegSysCtrl register to 1. It can then only be disabled by a power on reset. d The watchdog timer can be cleared by writing consecutively the valnues Hx0A and Hx0s3 to the RegSysWD register. The sequence must strictly be respected to clear the watchdog. e n In assembler code, the sequence to clear the watchdog is: m g move AddrRegSysWD, #0x0A i move AddrRegSysWD, #0x03 m s Only writing Hx0A followed by Hx03 resets the WD. If some oether write instruction is done to the RegSysWD between the writing of the Hx0A and Hx03 voalues, the watchdog timer will not be cleared. D It is possible to read the status of the cwatchdog in the RegSysWD register. The watchdog is a 4 bit counter with a count range between 0 and 7. The system reset is gen erated when the counter is reaching the value 8. e w R 6.8 Start-up and watchdog specificeations At start-up of the cirtcuit, the POR (poweNr-on-reset) block generates a reset signal during tPOR. The circuit starts software executiono after this period (see system chapter). The POR is intended to force the circuit in a correct state at start-up. For precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used. N © Semtech 2006 www.semtech.com 6-5

XE8805/05A Symbol Parameter Min Typ Max Unit Comments TPOR POR reset duration 5 20 ms T RESET pin reset duration 20 200 µs 3 RESET T RESET pin reset duration 5 20 ms 4 RESET r Vbat_sl_M Supply ramp up of MTP version 20 V/ms 1 o Vbat_sl_R Supply ramp up of ROM version 0.25 V/ms f 1 d WDtime Watchdog timeout period 2 s 2 e Table 6-5. Electrical and timing specifications d Note: 1) The Vbat_sl defines the minimum slope required on VBAT. Correct start-up of the circuit is not guaranteed n s if this slope is too slow. In such a case, a delay has to be built using the RESET pin. e n Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. The watchdog takes its clock from the low prescaler. In case an externaml clock source is usged, the RC oscillator must be enabled also (EnRC=1 in RegSysClock). Otherwise, the watchdog is stopped (see the clock block documentation). i Note: 3) For the circuit versions XE8801 and XE88m05. Gives the times the reset is active after the falling edge of the RESET pin. e o Note: 4) For the circuit versions XE8801A and XE8805A. Gives the time the reset is active after the falling edge of D the RESET pin. c e w R e N t o N © Semtech 2006 www.semtech.com 6-6

XE8805/05A 7 Clock Generator 7.1 Features r 7-2 o 7.2 Overview 7-2 f 7.3 Register map 7-2 d 7.4 Interrupts and events map 7-3 e 7.5 Clock sources d 7-4 7.5.1 RC oscillator 7-4 7.5.2 Xtal oscillator n s 7-6 7.5.3 External clock 7-7 e n 7.6 Clock source selection 7-8 m g 7.7 RegSysMisc Description 7-8 i 7.8 Prescalers m s 7-9 e 7.9 32 kHz frequency selector o 7-9 D c e w R e N t o N © Semtech 2006 www.semtech.com 7-1

XE8805/05A 7.1 Features • 3 available clock sources (RC oscillator, quartz oscillator and external clock). • 2 divider chains: high-prescaler (8 bits) and low-prescaler (15 bits). • CPU clock disabling in halt mode. 7.2 Overview The XE8805 chips can work on different clock sources (RC oscillator, quartz oscillator and rexternal clock). The clock generator block is in charge of distributing the necessary clock frequencies to othe circuit. Figure 7-1 represents the functionality of the clock block. f The internal RC oscillator drives the high prescaler. This prescaler generates freque ncy divisions down to 1/256 of its input frequency. A 32kHz clock is generated by enabling the quartz oscillatodr (if present in the product) or by selecting the appropriate tap on the high prescaler. The low prescaler generates clock signals from 32kHz down to 1Hz. The clock source for the CPU can be selected from the RC oscillator, thee external clock or the 32kHz clock. d 7.3 Register map n s e n pos. RegSysClock rw Reset function 7 CpuSel rw 0 resetsleepm Select speed gfor cpuck, 0=RC, 1=xtal or external clock i 6 Extclk r 0 resetcold External clock detected, 1=available m s 5 EnExtClock rw 0 resetcold Enable for external clock, 1=enabled 4 BiasRc rw 1 resetcold Enaeble Rcbias (reduces start-up time of RC). 3 ColdXtal r o1 resetsleep Xtal in start phase D 2 ColdRC r 1 resetsleep RC in start phase c 1 EnableXtal rw 0 resetsleep Enable Xtal oscillator, 0=disabled, 1=enabled 0 EnableRc rw 1 resetsle ep Enable RC oscillator, 0=disabled, 1=enabled e w Table 7-1: RegSysClock register R e pos. Reg SysMisc rw Reset Function N 7-4 -- t r 0000 Unused 3 RoCOnPA0 rw 0 resetsleep Start RC on PA[0], 0=disabled, 1=enabled 2 DebFast rw 0 resetsleep Debouncer clock speed, 0=256Hz, 1=8kHz N 1 OutputCkXtal rw 0 resetsleep Output Xtal Clock on PB[3], 0=disabled, 1=enabled if EnXtal=1 else PB[3]=0 0 OutputCpuCk rw 0 resetsleep Output CPU clock on PB[2], 0=disabled, 1=enabled Table 7-2: RegSysMisc register pos. RegSysPre0 rw reset Function 7-1 -- r 0000000 Unused 0 ResPre w1 0 Write 1 to reset low prescaler, but always r0 reads 0 Table 7-3: RegSysPre0 register © Semtech 2006 www.semtech.com 7-2

XE8805/05A pos. RegSysRcTrim1 rw reset Function 7-4 -- r 00 Unused 5 Reserved rw 0 resetcold Reserved 4 RcFreqRange rw 0 resetcold Low/high freq. range (low=0) 3 RcFreqCoarse[3] rw 0 resetcold RC coarse trim bit 3 2 RcFreqCoarse[2] rw 0 resetcold RC coarse trim bit 2 1 RcFreqCoarse[1] rw 0 resetcold RC coarse trim bit 1 0 RcFreqCoarse[0] rw 0 resetcold RC coarse trim bit 0 r Table 7-4: RegSysRCTrim1 register o pos. RegSysRcTrim2 Rw reset functiofn 7-6 -- r 00 Unused 5 RcFreqFine[5] rw 1 resetcold RC fine trim bit 5 d 4 RcFreqFine[4] rw 0 resetcold RC fine trim bit 4 e 3 RcFreqFine[3] rw 0 resetcold RC fine trim bit 3 2 RcFreqFine[2] rw 0 resetcold RC fine trimd bit 2 1 RcFreqFine[1] rw 0 resetcold RC fine trim bit 1 0 RcFreqFine[0] rw 0 resetcold RC finne trim bit 0 s Table 7-5: RegSysRCTerim2 register n m g RegSysRcTrim1 i RegSysRcTrim2 m s e CkRc o CkRc RC High prescalerD to CkRc/256 c External 0 Clock e 0 w 1 CkXtal R OSCIN Xtal 1 e CpuSel 0 32kHz N Low prescaler to t 1Hz o 1 EnXtal and not(ExtClk or EnExtClk) N CpuCk Figure 7-1. Clock block structure 7.4 Interrupts and events map Interrupt Interrupt source Mapping in the interrupt manager Mapping in the event manager IrqPre1 Ck128Hz RegIrqHig(6) RegEvn(5) IrqPre2 Ck1Hz RegIrqMid(3) RegEvn(1) Table 7-6: Interrupts and events map © Semtech 2006 www.semtech.com 7-3

XE8805/05A 7.5 Clock sources 7.5.1 RC oscillator 7.5.1.1 Configuration The RC oscillator is always turned on and selected for CPU and system operation at power-on reset and when exiting sleep mode. It can be turned off after the Xtal (quartz oscillator) has been started, arfter selection of the external clock or by entering sleep mode. o The RC oscillator has two frequency ranges: sub-MHz (100 kHz to 1 MHz) and above-MHz (1 MHz to 10 MHz). Inside a range, the frequency can be tuned by software for coarse and fine adjustment. See registers f RegSysRcTrim1 and RegSysRcTrim2. d Bit EnableRC in register RegSysClock controls the propagation of the RC clock signal and the operation of the oscillator. The user can stop the RC oscillator by resetting the bit EnableRCe. Entering the sleep mode disables the RC oscillator. d Note: Before turning off the RC oscillator, the cpusel bit in RegSysClock must be set to one. n s Note: The RC oscillator bias can be maintained while the oscillator is switched off by setting the bit BiasRc in e n RegSysClock. This allows a faster restart of the RC oscillator at the cost of increased power consumption when the oscillator is disabled (see section 7.5.1.3). m g i 7.5.1.2 RC oscillator frequency tuning m s The RC oscillator frequency can be set using the bits in the ReegSysRcTrim1 and RegSysRcTrim2 registers. Figure 7-2 shows the nominal frequency oof the RC oscillator as a function of these bits. The absolute value of the D frequency for a given register content may change by ±50% from chip to chip due to the tolerances on the c integrated capacitors and resistors. However, the modification of the frequency as a function of a modification of the register content is fairly precise for frequencies bel ow 2MHz. This means that the curves in Figure 7-2 can shift e up and down but that the slope remains unchanged.w R The bit RcFreqRange modifies the oscillaetor frequency by a factor of 10. The upper curve in the figure corresponds to RcFreqRange=1. t N The RcFreqCoarsoe modifies the frequency of the oscillator by a factor (RcFreqCoarse+1). The figure represents the frequency for 5 different values of the bits RcFreqCoarse: for each value the frequency is multiplied by 2. N Incrementing the RcFreqFine code increases the frequency by about 1.4%. The frequency of the oscillator is therefor given by: f =f ⋅(1+9⋅RcFreqRange)⋅(1+RcFreqCoarse)⋅(1.014)RcFreqFine RC Rcmin with f the RC oscillator frequency if the registers are all 0. At higher frequencies, the frequency may deviate Rcmin from the value predicted by the equation. © Semtech 2006 www.semtech.com 7-4

XE8805/05A 1E+08 RcFreqRange='1' RcFreqRange='0' Nominal RC oscillator frequency [Hz] 111EEE+++000005670000000000R00c11F00r00e0000qF11i00n00e00(00500:011)1100000000111111111111001100000000110000000000111100000000111111111111001100000000m110000000000e111100000000n11111111111100d110000000011eg00000000001111dn000000 001111s11f11111100110000o00R00c11Fr00r00e00q00 00Fin1111e00(00500:000)111111111111 i m s RcFreqCoarse(3:0) 1E+04 0000 0001 0011 e 0111 1111 o D Figure 7-2. RC oscillator nominal frequency tuning. c 7.5.1.3 RC oscillator specificaetions w R symbol description min typ max unit Comments e f Lowest RC frequency 40 80 120 kHz Note 1 RCmin RcFreqFine fine tuning step N 1.4 2.0 % t RC_su startup time 30 50 us BiasRc=0 o 3 5 us BiasRc=1 PSRR @ DCN Supply voltage TBD %/V Note 2 dependence TBD %/V Note 3 ∆f/∆T Temperature 0.1 %/°C dependence Table 7-7. RC oscillator specifications Note 1: this is the frequency tolerance when all trimming codes are 0. Note 2: frequency shift as a function of VBAT with normal regulator function. Note 3: frequency shift as a function of VBAT while the regulator is short-circuited to VBAT. The tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the software DFLL (digital frequency locked loop) which uses the crystal oscillator as a reference frequency. © Semtech 2006 www.semtech.com 7-5

XE8805/05A 7.5.2 Xtal oscillator 7.5.2.1 Xtal configuration The Xtal operates with an external crystal of 32’768 Hz. During Xtal oscillator start-up, the first 32768 cycles are masked. The two bits EnableXtal and ColdXtal in register RegSysClock control the oscillator. r At power-on reset or during sleep mode, EnableXtal is reset and ColdXtal is set (Xtal oscillator is not selected at o start-up). The user can start Xtal oscillator by setting EnableXtal. When the Xtal oscillator starts, bit ColdXtal is reset after 32768 cycles. Before ColdXtal is reset by the system, the Xtal frequency precision is not guaranteed. f The Xtal oscillator can be stopped by the user by resetting bit EnableXtal. d When the user enters into sleep mode, the Xtal is stopped. e When an external clock is detected (ExtClk = 1) or the EnExtClock is set 1, the EnableXtal bit can not be set to 1. d 7.5.2.2 Xtal oscillator specifications n s The crystal oscillator has been designed for a crystal with the specifications given in Table 7-8. The oscillator precision can only be guaranteed for this crystal. e n m g Symbol Description Min Typ Max Unit Comments Fs Resonance frequency 32768 Hz i CL CL for nominal m 8.2 15s pF frequency Rm Motional resistance 40 e100 kΩ o Cm Motional capacitance 1.8 2.5 3.2 fF D C0 Shunt capacitance 0.7 1.1 2.0 pF c Rmp Motional resistance of 4 8 kΩ 6th overtone (parasietic) w Q Quality factor 30k 50k 400k - R Tablee 7-8. Crystal specifications. For safe operation, low power consumptioNn and to meet the specified precision, careful board layout is required: t Keep lines OSCIN and OSCOUT short and insert a VSS line in between them. o Connect the crystal package to VSS. No noisy or digital lines near OSCIN or OSCOUT. N Insert guards where needed. Respect the board specifications of Table 7-9. Symbol Description Min Typ Max Unit Comments Rh_oscin Resistance OSCIN-VSS 10 MΩ Rh_oscout Resistance OSCOUT-VSS 10 MΩ Rh_oscin_oscout Resistance OSCIN-OSCOUT 50 MΩ Cp_oscin Capacitance OSCIN-VSS 0.5 3.0 pF Cp_oscout Capacitance OSCOUT-VSS 0.5 3.0 pF Cp_oscin_oscout Capacitance OSCIN-OSCOUT 0.2 1.0 pF Table 7-9. Board layout specifications. The oscillator characteristics are given in Table 7-10. The characteristics are valid only if the crystal and board layout meet the specifications above. © Semtech 2006 www.semtech.com 7-6

XE8805/05A Symbol Description Min Typ Max Unit Comments f Nominal frequency 32768 Hz Xtal St_xtal Start-up time 1 2 s Fstab Frequency deviation -100 300 ppm Note 1 Table 7-10. Crystal oscillator characteristics. Note 1. This gives the relative frequency deviation from nominal for a crystal with CL=8.2pF and within the temperature range -40°C to 85°C. The crystal tolerance, crystal aging and crystal temperature dr ift are not included in this figure. r o 7.5.3 External clock f 7.5.3.1 External clock configuration d e The user can provide an external clock instead of the internal oscillators. Only the CPU can use the external clock. The external clock input pin is OSCIN. d The system is configured for external clock by bit EnExtClock in register RegSysClock. n s When EnExtClock is set to 1, the external clock is detected eafter 4 pulses on pnin OSCIN. The ExtClk bit shows when the external clock is available. m g Note: when using the external clock, the Xtal is not available. i m s 7.5.3.2 External clock specification e o The external clock has to satisfy the specifications in the tDable below. Correct behavior of the circuit can not be guaranteed if the external clock signal does not respect the specifications below. c Symbol Description e Min w Typ Max Unit Comments F External clock 2 MHz EXT R frequency e PW_1 Pulse 1 width 0.2 µs PW_0 Pulse 0 width N0.2 µs t o Table 7-11. External clock specifications. N © Semtech 2006 www.semtech.com 7-7

XE8805/05A 7.6 Clock source selection There are three possible clock sources available for the CPU clock. The RC clock is always selected after power- up or after Sleep mode. The CPU clock selection is done with the bit CpuSel in RegSysClock (0= RC clock, 1= 32 kHz from Xtal if EnableXtal =1, ExtClk = 0 and EnExtClk = 0 else external clock). Switching from one clock source to another is glitch free. The next table summarizes the different clock configurations of the circuit: r o Clock Sources Clock targets Mode Cpuck Note 1 f name k c al H igh Low EnExtCl EnableR EnableXt CpuSel=0 CpuSel=1 ePdrCeinslpocucaktl e r PrCeinslopccuaktl e r d Sleep 0 0 0 Off Off Off Off Xtal 0 0 1 Off nXtal Offs Xtal RC 0 1 0 RC RC RC High presc. e n RC + Xtal 0 1 1 RC Xtal RC Xtal m g External 1 0 X Off External Off Off RC + 1 1 X RC Exterinal RC High presc. External m s Table 7-12: Table of clocking modes. e o Note 1: The CPU clock can be divided by using the freq instruction (see coolrisc instruction set) D c Switching from one clock source to another and stopping the unused clock source must be performed using 3 MOVE instructions to RegSysClock. First select the n ew clock source, secondly change the CpuSel bit and finally e w stop the unused one. R e 7.7 RegSysMisc Description N t The RCOnPA0 biot in RegSysMisc can be used to enable the RC oscillator on an event external to the circuit. If RCOnPA0 is 1, the RC oscillator is enabled (EnableRC bit is set to 1) as soon as the value on port A pin PA[0] is equal to 1. ThNe port A pin can be debounced (see port A documentation). Bit DebFast in the RegSysMisc register allows to chose the debouncer clock between 256Hz and 8kHz (DebFast = 0 and DebFast = 1 respectively). The Debouncer clock is used to debounce PA inputs (see port A documentation). Bit OutputCkXtal allows to show the Xtal clock on PB[3]. The EnableXtal bit must be set to 1 else PB[3] equals 0 (see port B documentation to set up the port B). Bit OutputCpuCk allows to show the CpuClock on PB[2] (see port B documentation). © Semtech 2006 www.semtech.com 7-8

XE8805/05A 7.8 Prescalers The clock generator block embeds two divider chains: the high prescaler and the low prescaler. The high prescaler is made of an 8 stage dividing chain and the low prescaler of a 15 stage dividing chain. Features: • High prescaler can only be driven with RC clock (bit EnableRc have to be set, see Table 7-12). • Low prescaler can be driven from the high prescaler or directly with the Xtal clock when bit EnableXtal is set to 1, bit EnExtClock is set to 0 and ExtClk is equal at 0. r • Bit ResPre in the RegSysPre0 register allows to reset synchronously the low prescaler, the low prescaler is o also automatically cleared when bit EnableXtal is set. Both dividing chains are reset asynchronously by the resetsleep signal. f • Bit ColdXtal=1 indicates the Xtal is in its start up phase. It is active for 3 7268 Xtal cycles after setting EnableXtal. d 7.9 32 kHz frequency selector e d A decoder is used to select from the high prescaler the frequency tap that is the closest to 32 kHz to operate the low prescaler when the Xtal is not running. In this case, the RC osncillator frequency sof ±50% will also be valid for the low prescaler frequency outputs. e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 7-9

XE8805/05A 8 IRQ - Interrupt handler 8.1 Features r 8-2 o 8.2 Overview 8-2 f 8.3 Register map 8-2 d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 8-1

XE8805/05A 8.1 Features The XE8000 chips support 24 interrupt sources, divided into 3 levels of priority. 8.2 Overview A CPU interruption is generated and memorized when an interrupt becomes active. The 24 interrupt sources are divided into 3 levels of priority: High (8 interrupt sources), Mid (8 interrupt sources), and Low (8 interrupt sources). Those 3 levels of priority are directly mapped to those supported by the CoolRisc® (IN0r, IN1 and IN2; see CoolRisc® documentation for more information). o RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the infterrupt sources. Those flags are set when the interrupt is enabled (i.e. if the corresponding bit in the registers R egIrqEnHig, RegIrqEnMid or RegIrqEnLow is set) and a rising edge is detected on the corresponding interruptd source. Once memorized, an interrupt flag can be cleared by writing a ‘1’ in the correesponding bit of RegIrqHig, RegIrqMid or RegIrqLow. Writing a ‘0’ does not modify the flag. To definitively clear the interrupt, one has to clear the d CoolRisc interrupt in the CoolRisc status register. All interrupts are automatically cleared after a reset. n s Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number of the highest priority interrupt set (its value is 0xFF when no interrupt is set). RegIrqIrq indicates the priority level e n of the current interrupts. RegIrqIrq and RegIrqPriority ‘s values are dependent upon the memorized state of the interrupts (as reflected in flags in RegIrqHig, RegIrqMid amnd RegIrqLow). g 8.3 Register map i m s e pos. RegIrqHig rwo reset function 7 RegIrqHig[7] r 0 resetsystemD interrupt #23 (high priority) cc1 clear interrupt #23 when 1 is written 6 RegIrqHig[6] r 0 reset system interrupt #22 (high priority) e c1 w clear interrupt #22 when 1 is written 5 RegIrqHig[5] r 0 resetsystem interrupt #21 (high priority) R c1 clear interrupt #21 when 1 is written e 4 RegIrqHig[4] r 0 resetsystem interrupt #20 (high priority) Nc1 clear interrupt #20 when 1 is written t 3 RegIrqHig[3] r 0 resetsystem interrupt #19 (high priority) o c1 clear interrupt #19 when 1 is written 2 RegIrqHig[2] r 0 resetsystem interrupt #18 (high priority) N c1 clear interrupt #18 when 1 is written 1 RegIrqHig[1] r 0 resetsystem interrupt #17 (high priority) c1 clear interrupt #17 when 1 is written 0 RegIrqHig[0] r 0 resetsystem interrupt #16 (high priority) c1 clear interrupt #16 when 1 is written Table 8-1: RegIrqHig © Semtech 2006 www.semtech.com 8-2

XE8805/05A pos. RegIrqMid rw reset function 7 RegIrqMid[7] r 0 resetsystem interrupt #15 (mid priority) c1 clear interrupt #15 when 1 is written 6 RegIrqMid[6] r 0 resetsystem interrupt #14 (mid priority) c1 clear interrupt #14 when 1 is written 5 RegIrqMid[5] r 0 resetsystem interrupt #13 (mid priority) c1 clear interrupt #13 when 1 is written 4 RegIrqMid[4] r 0 resetsystem interrupt #12 (mid priority) c1 clear interrupt #12 when 1 is rwritten 3 RegIrqMid[3] r 0 resetsystem interrupt #11 (mid priority) o c1 clear interrupt #11 when 1 is written 2 RegIrqMid[2] r 0 resetsystem interrupt #10 (mid prifority) c1 clear interrupt #10 when 1 is written 1 RegIrqMid[1] r 0 resetsystem interrupt #9 (midd priority) c1 clear interrupt #9 when 1 is written 0 RegIrqMid[0] r 0 resetsystem interrupt #8e (mid priority) c1 clear interrupt #8 when 1 is written d Table 8-2: RegIrqMid n s pos. RegIrqLow rw reset e funnction 7 RegIrqLow[7] r 0 resetsystem interrupt #7 (low priority) c1 m clear interrugpt #7 when 1 is written 6 RegIrqLow[6] r 0 resetsystem interrupt #6 (low priority) c1 clear iinterrupt #6 when 1 is written 5 RegIrqLow[5] r 0 rmesetsystem intersrupt #5 (low priority) c1 clear interrupt #5 when 1 is written e 4 RegIrqLow[4] r 0 resetsystem interrupt #4 (low priority) o c1 D clear interrupt #4 when 1 is written 3 RegIrqLow[3] cr 0 resetsystem interrupt #3 (low priority) c1 clear interrupt #3 when 1 is written 2 RegIrqLow[2]e r 0 reswetsystem interrupt #2 (low priority) c1 clear interrupt #2 when 1 is written R 1 RegIrqLow[1] r 0 resetsystem interrupt #1 (low priority) e c1 clear interrupt #1 when 1 is written 0 RegIrqLow[0] Nr 0 resetsystem interrupt #0 (low priority) t c1 clear interrupt #0 when 1 is written o Table 8-3: RegIrqLow N pos. RegIrqEnHig rw reset function 7 RegIrqEnHig[7] rw 0 resetsystem 1= enable interrupt #23 6 RegIrqEnHig[6] rw 0 resetsystem 1= enable interrupt #22 5 RegIrqEnHig[5] rw 0 resetsystem 1= enable interrupt #21 4 RegIrqEnHig[4] rw 0 resetsystem 1= enable interrupt #20 3 RegIrqEnHig[3] rw 0 resetsystem 1= enable interrupt #19 2 RegIrqEnHig[2] rw 0 resetsystem 1= enable interrupt #18 1 RegIrqEnHig[1] rw 0 resetsystem 1= enable interrupt #17 0 RegIrqEnHig[0] rw 0 resetsystem 1= enable interrupt #16 Table 8-4: RegIrqEnHig © Semtech 2006 www.semtech.com 8-3

XE8805/05A pos. RegIrqEnMid rw reset function 7 RegIrqEnMid[7] rw 0 resetsystem 1= enable interrupt #15 6 RegIrqEnMid[6] rw 0 resetsystem 1= enable interrupt #14 5 RegIrqEnMid[5] rw 0 resetsystem 1= enable interrupt #13 4 RegIrqEnMid[4] rw 0 resetsystem 1= enable interrupt #12 3 RegIrqEnMid[3] rw 0 resetsystem 1= enable interrupt #11 2 RegIrqEnMid[2] rw 0 resetsystem 1= enable interrupt #10 1 RegIrqEnMid[1] rw 0 resetsystem 1= enable interrupt #9 0 RegIrqEnMid[0] rw 0 resetsystem 1= enable interrupt #8 r o Table 8-5: RegIrqEnMid f pos. RegIrqEnLow rw reset fudnction 7 RegIrqEnLow[7] rw 0 resetsystem 1= enable interrupt #7 e 6 RegIrqEnLow[6] rw 0 resetsystem 1= enable interrupt #6 5 RegIrqEnLow[5] rw 0 resetsystem 1= enadble interrupt #5 4 RegIrqEnLow[4] rw 0 resetsystem 1= enable interrupt #4 3 RegIrqEnLow[3] rw 0 resetsystem 1=n enable interrupt #s3 2 RegIrqEnLow[2] rw 0 resetsystem 1= enable interrupt #2 1 RegIrqEnLow[1] rw 0 resetsystem e1= enable interrunpt #1 0 RegIrqEnLow[0] rw 0 resetsystem 1= enable interrupt #0 m g Table 8-6: RegIrqEnLow i m s pos. RegIrqPriority rw reset function 7-0 RegIrqPriority r 11111111 ecode of highest priority set o resetsystem D c Table 8-7: RegIrqPriority e w pos. RegIrqIrq rw Reset function 7-3 - R r 00000 unused 2 IrqHig r e0 resetsystem one or more high priority interrupt is set N 1 ItrqMid r 0 resetsystem one or more mid priority interrupt is o set 0 IrqLow r 0 resetsystem one or more low priority interrupt is N set Table 8-8: RegIrqIrq © Semtech 2006 www.semtech.com 8-4

XE8805/05A 9 Event Handler 9.1 Features r 9-2 o 9.2 Overview 9-2 f 9.3 Register map 9-2 d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 9-1

XE8805/05A 9.1 Features The XE8000 chips support 8 event sources, divided into 2 levels of priority. 9.2 Overview A CPU event is generated and memorized when an event source becomes active. The 8 event s ources are divided into 2 levels of priority: High (4 event sources) and Low (4 event sources). Those 2 levels orf priority are directly mapped to those supported by the CoolRisc (EV0 and EV1; see CoolRisc documentation foor more information). RegEvn is an 8-bit register containing flags for the event sources. Those flags are seft when the event is enabled (i.e. if the corresponding bit in the registers RegEvnEn is set) and a rising edge is detected on the corresponding event source. d Once memorized, writing a ‘1’ in the corresponding bit of RegEvn clearse an event flag. Writing a ‘0’ does not modify the flag. All interrupts are automatically cleared after a reset. d Two registers are provided to facilitate the writing of event service software. RegEvnPriority contains the number n s of the highest priority event set (its value is 0xFF when no event is set). RegEvnEvn indicates the priority level of the current interrupts. RegEvnEvn and RegEvnPriority ‘s values are dependent upon the memorized state of the e n events (as reflected in flags in RegEvn). m g 9.3 Register map i m s e pos. RegEvn rw reset function o 7 RegEvn[7] r 0 resetsysteDm event #7 (high priority) cc1 clear event #7 when written 1 6 RegEvn[6] r 0 resetsystem event #6 (high priority) e c1 w clear event #6 when written 1 5 RegEvn[5] r 0 resetsystem event #5 (high priority) R c1 clear event #5 when written 1 e 4 RegEvn[4] r 0 resetsystem event #4 (high priority) Nc1 clear event #4 when written 1 t 3 RegEvn[3] r 0 resetsystem event #3 (low priority) o c1 clear event #3 when written 1 2 RegEvn[2] r 0 resetsystem event #2 (low priority) N c1 clear event #2 when written 1 1 RegEvn[1] r 0 resetsystem event #1 (low priority) c1 clear event #1 when written 1 0 RegEvn[0] r 0 resetsystem event #0 (low priority) c1 clear event #0 when written 1 Table 9-1: RegEvn © Semtech 2006 www.semtech.com 9-2

XE8805/05A pos. RegEvnEn rw reset function 7 RegEvnEn[7] rw 0 resetsystem 1= enable event #7 6 RegEvnEn[6] rw 0 resetsystem 1= enable event #6 5 RegEvnEn[5] rw 0 resetsystem 1= enable event #5 4 RegEvnEn[4] rw 0 resetsystem 1= enable event #4 3 RegEvnEn[3] rw 0 resetsystem 1= enable event #3 2 RegEvnEn[2] rw 0 resetsystem 1= enable event #2 1 RegEvnEn[1] rw 0 resetsystem 1= enable event #1 0 RegEvnEn[0] rw 0 resetsystem 1= enable event #0 r o Table 9-2: RegEvnEn f pos. RegEvnPriority rw reset func tion 7-0 RegEvnPriority r 11111111 code of highest devent set resetsystem e Table 9-3: RegEvnPriority d pos. RegEvnEvn rw reset n functiosn 7-2 - r 00000 unused 1 EvnHig r 0 resetsysteme one or more highn priority event is set 0 EvnLow r 0 resetsystem one or more low priority event is set m g Table 9-4: RegEvnEvn i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 9-3

XE8805/05A 10 Low Power RAM 10.1 Features r 10-2 o 10.2 Overview 10-2 f 10.3 Register map 10-2 d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 10-1

XE8805/05A 10.1 Features • Low power RAM locations. 10.2 Overview In order to save power consumption, 8 8-bit registers are provided in page 0. These memory locations should be reserved for often-updated variables. Accessing these register locations requires much less pow er than the other general purpose RAM locations. r o 10.3 Register map f pos. Reg00 rw reset funct ion d 7-0 Reg00 rw XXXXXXXX low-power data memory Table 10-1: Reg00 e pos. Reg01 rw reset d function 7-0 Reg01 rw XXXXXXXX low-power data memory n s Table 10-2: Reg01 e n pos. Reg02 rw reset function 7-0 Reg02 rw XXXXXmXXX low-power dgata memory Table 10-3: Reg02 i pos. Reg03 rw m reset s function 7-0 Reg03 rw XXXXXXXX low-power data memory e o Table 10-4: Reg03 D pos. Reg04 c rw reset function 7-0 Reg04 rw XXXXXXXX low-power data memory e w Table 10-5: Reg04 R pos. Reg05 rw reset function e 7-0 Reg05 rw XXXXXXXX low-power data memory N t Table 10-6: Reg05 o pos. Reg06 rw ¨reset function N7-0 Reg06 rw XXXXXXXX low-power data memory Table 10-7: Reg06 pos. Reg07 rw reset function 7-0 Reg07 rw XXXXXXXX low-power data memory Table 10-8: Reg07 © Semtech 2006 www.semtech.com 10-2

XE8805/05A 11 Port A 11.1 Features 11-2 r 11.2 Overview 11-2 o 11.3 Register map 11-3 f 11.4 Interrupts and events map 11-3 d 11.5 Port A (PA) Operation 11-4 e 11.6 Port A electrical specification d 11-5 n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 11-1

XE8805/05A 11.1 Features • Input port, 8 bits wide • Each bit can be set individually for debounced or direct input • Each bit can be set individually for pull-up or not • Each bit is an interrupt request source on the rising or falling edge • A system reset can be generated on an input pattern • PA[0] and PA[1] can generate two events for the CPU, individually maskable • PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM (product dependent) r • PA[0] can be used to enable the RC oscillator o 11.2 Overview f Port A is a general purpose 8 bit wide digital input port, with interrupt capability. Fidgure 11-1 shows its structure. e VBat Port A d n s 8 e n RegPAPullup 8 m RegPADgebounce 8x debounce 0 8 iRegPACtrl 8 m s RegPAIn 1 8 RegPAEdge e 1 0 o RC 1 D8 interrupts c 0 events DebFast e (RegSysMisc(2 )) 8x cntclocks w 256 Hz R 8 kHz e 8 RegPARes1 8 N RegPARes0 t 1 11 o PAReset[x] 10 N 01 resetfromporta 0 00 8x Figure 11-1:structure of Port A © Semtech 2006 www.semtech.com 11-2

XE8805/05A 11.3 Register map There are six registers in the Port A (PA), namely RegPAIn, RegPADebounce, RegPAEdge, RegPAPullup, RegPARes0 and RegPARes1. Table 11-1 to Table 11-6 show the mapping of control bits and functionality. pos. RegPAIn rw reset description 7:0 PAIn[7:0] r pad PA[7] to PA[0] input value Table 11-1: RegPAIn r o pos. RegPADebounce rw reset description PA[7] to PfA[0] 00000000 7:0 PADebounce[7:0] r w 1: deboun ce enabled resetpconf 0: debodunce disabled Table 11-2: RegPADebounce e d pos. RegPAEdge rw reset description PA[7] to PA[0] edge configuration 00000000 n s 7:0 PAEdge[7:0] r w 0: positive edge resetsystem 1: negative edge e n Table 11-3: RegPAEdge m g pos. RegPAPullup rw reset descriptioni m sPA[7] to PA[0] pullup enable 00000000 7:0 PAPullup[7:0] r w 0: pullup disabled resetpconf e 1: pullup enabled o Table 11-4: RegPAPullup D c pos. RegPARes0 rw Reset description e 00000w000 7:0 PARes0[7:0] r w PA[7] to PA[0] reset configuration resetsystem R Teable 11-5: RegPARes0 N t pos. RegPARes1 rw reset Description o 7:0 PARes1[7:0] r w 00000000 PA[7] to PA[0] reset configuration resetsystem N Table 11-6: RegPARes 11.4 Interrupts and events map Interrupt source Default mapping in Default mapping in the the interrupt manager event manager pa_irqbus[5] RegIrqMid[5] pa_irqbus[4] RegIrqMid[4] pa_irqbus[1] RegIrqMid[1] RegEvn[4] pa_irqbus[0] RegIrqMid[0] RegEvn[0] pa_irqbus[7] RegIrqLow[7] pa_irqbus[6] RegIrqLow[6] pa_irqbus[3] RegIrqLow[3] pa_irqbus[2] RegIrqLow[2] © Semtech 2006 www.semtech.com 11-3

XE8805/05A 11.5 Port A (PA) Operation The Port A input status (debounced or not) can be read from RegPAin. Debounce mode: Each bit in Port A can be individually debounced by setting the corresponding bit in RegPADebounce. After reset, the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if the input value is identical at two consecutive sampling on the rising edge of the selected clock. Selection of the clock is done by the bit DebFast in Register RegSysMisc (see clock block documentation for more precision on the frequency). r DebFast Clock filter o 0 256 Hz f 1 8 kHz d Table 11-7: debounce frequency selection e Input d CkDebounce 1 1 2 1 1 2 Debounced n s e n Figure 11-2: digital debouncer Pull-ups: m g When the corresponding bit in RegPAPullup is set to 0, the inputs are floating (pull-up resistors are disconnected). When the corresponding bit in RegPAPullup is set to 1, a pull-up resiistor is connected to the input pin. Port A m s starts up with the pull-up resistors disconnected. e Port A as an interrupt source: o Each Port A input is an interrupt request source and can beD set on rising or falling edge with the corresponding bit in RegPAEdge. After reset, the rising cedge is selected for interrupt generation by default. The interrupt source can be debounced by setting register RegPADebounce. e w Note: care must be taken when modifying RegPAEdge because this register performs an edge selection. The R change of this register may result in a transition which may be interpreted as a valid interruption. e Port A as an event sour ce: N t The interrupt signals of the pins PA[0] and PA[1] are also available as events on the event controller. o Port A as a clock source (product dependent): N Images of the PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the counter/timer/PWM peripheral (see the counter block documentation for more information). Port A as a reset source: Port A can be used to generate a system reset by placing a predetermined word on Port A externally. The reset is built using a logical and of the 8 PARes[x] signals: resetfromportA = PAReset[7] AND PAReset[6] AND PAReset[5] AND ... AND PAReset[0] PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 11-8. © Semtech 2006 www.semtech.com 11-4

XE8805/05A PARes1[x] PARes0[x] PAReset[x] 0 0 0 0 1 PA[x] 1 0 not(PA[x]) 1 1 1 Table 11-8: Selection bits for reset signal A reset from Port A can be inhibited by placing a 0 on both PARes1[x] and PARes0[x] for at least 1 pin. Setting both PARes1[x] and PARes0[x] to 1, makes the reset independent of the value on the corresrponding pin. Setting both registers to hFF, will reset the circuit independent from the Port A input value. This makes it possible to do a o software reset. f Note: depending of the value of PA[0] to PA[7], the change of RegPARes0 and RegPARes1 can cause a reset. Therefore it is safe to have always one (RegPARes0[x], RegPARes1[x]) equal to ‘d00’ during the setting operations. Port A as a RC enable: e PA[0] can be used to enable the RC oscillator. When RCOnPA0 bit in RegSysMisc is set to 1 and the value of PA[0] (debounced or not) is equal to 1, the EnRc bit in RegSysClock is dautomatically set to 1. n s e n 11.6 Port A electrical specification m g Sym description min typ max uniit Comments V Input high voltage 0.7*VBAT m VBAT sV VBAT≥2.4V INH V Input low voltage VSS 0.2*VBAT V VBAT≥2.4V INL e RPU Pull-up resistance 20 o 50 80 kΩ Cin Input capacitance 3.5 D pF Note 1 c Note 1: this value is indicative only since it depends on the package. e w Table 11-9. Port A electrical sRpecification. e N t o N © Semtech 2006 www.semtech.com 11-5

XE8805/05A 12 Port B 12.1 Features r 12-2 o 12.2 Overview 12-2 f 12.3 Register map 12-2 d 12.4 Port B capabilities 12-3 e 12.5 Port B analog capability d 12-3 12.5.1 Port B analog configuration 12-3 12.5.2 Port B analog function specification n s 12-4 12.6 Port B function capability e n 12-4 12.7 Port B digital capabilities m g 12-5 12.7.1 Port B digital configuration 12-5 12.7.2 Port B digital function specification i 12-6 m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 12-1

XE8805/05A 12.1 Features • Input / output / analog port, 8 bits wide • Each bit can be set individually for input or output • Each bit can be set individually for open-drain or push-pull • Each bit can be set individually for pull-up or not (for input or open-drain mode) • In open-drain mode, pull-up is not active when corresponding pad is set to zero • The 8 pads can be connected by pairs to four internal analog lines (4 line analog bus) • Two internal freq. (cpuck and 32 kHz) can be output on PB[2] and PB[3] r o Product dependant: • Two PWM signal can be output on pads PB[0] and PB[1] f • The synchronous serial interface (USRT) uses pads PB[5], PB[4] • The UART interface uses pads PB[6] and PB[7] for Tx and Rx d 12.2 Overview e d Port B is a multi-purpose 8 bit Input/output port. In addition to digital functions, all pins can be used for analog signals. All port terminals can be selected by pairs as digital input or output or as analog to share one of four possible analog lines. n s e n 12.3 Register map m g Pos. RegPBOut rw reset description in digital mode description in analog mode 7 – 0 PBOut[7-0] r w 0 resetpconf Pad PB[7-0] output value i Analog bus selection for pad PB[7-0] m s Table 12-1: RegPBOut e o Pos. RegPBIn rw reset descriptionD in digital mode description in analog mode 7 – 0 PBIn[7-0] r w c Pad PB[7-0] input status Unused Table 1 2-2: RegPBIn e w R Pos. RegPBDir rw reset description in digital mode description in analog mode e 7 – 0 PBDir [7-0] r w 0 resetpconf Pad PB[7-0] direction (0=input) Analog bus selection for pad PB[7-0] N Table 12-3: RegPBDir t o Pos. RegPBOpen rw reset description in digital mode description in analog mode N 7 – 0 PBOpen[7-0] r w 0 resetpconf Pad PB[7-0] open drain (1 = open Unused drain) Table 12-4: RegPBOpen Pos. RegPBPullup rw reset description in digital mode description in analog mode 7 –0 PBPullup[7] r w 0 resetpconf Pull-up for pad PB[7-0] (1=active) Connect pad PB[7-0] on selected ana bus Table 12-5: RegPBPullup Pos. RegPBAna rw reset description in digital mode description in analog mode 7 – 4 -- r 0000 Unused Unused 3 PBAna [3] r w 0 resetpconf Set PB[7:6] in analog mode Set PB[7:6] in analog mode 2 PBAna [2] r w 0 resetpconf Set PB[5:4] in analog mode Set PB[5:4] in analog mode 1 PBAna [1] r w 0 resetpconf Set PB[3:2] in analog mode Set PB[3:2] in analog mode 0 PBAna [0] r w 0 resetpconf Set PB[1:0] in analog mode Set PB[1:0] in analog mode Table 12-6: RegPBAna © Semtech 2006 www.semtech.com 12-2

XE8805/05A Note: Depending on the status of the EnResPConf bit in RegSysCtrl, the reset conditions of the registers are different. See the reset block documentation for more details on the resetpconf signal. 12.4 Port B capabilities Port B usage (priority) analog functions digital name (high) (medium) (low) (default) r PB[7] uart Rx I/O analog o PB[6] uart Tx I/O PB[5] usrt S1 I/Of analog PB[4] usrt S0 I/O PB[3] 32 kHz dI/O analog PB[2] clock CPU I/O PB[1] PWM1 Counter C (C+D) e I/O analog PB[0] PWM0 Counter A (A+B) I/O d Table 12-7: Different Port B functionality n s Table 12-7 shows the different usage that can be made of the port B with the order of priority. If a pair of pins is e n selected to be analog, it overwrites the function and digital set-up. If the pin is not selected as analog, but a function is enabled, it overwrites the digital set-up. If neithmer the analog nor fugnction are selected for a pin, it is used as an ordinary digital I/O. This is the default configuration at start-up. i m s 12.5 Port B analog capability e o D 12.5.1 Port B analog configuraticon Port B terminals can be attacheed to a 4 line analwog bus by setting the PBAna[x] bits to 1 in the RegPBAna register. R e The other registers then define the connection of these 4 analog lines to the different pads of Port B. This can be used to implement a s imple LCD driver or A/D converter. Analog switching is available only when the circuit is N t powered with sufficient voltage (see specification below). Below the specified supply voltage, only voltages that are o close to VSS or VBAT can be switched. N When PBAna[x] is set to 1, a pair of Port B terminals is switched from digital I/O mode to analog mode. The usage of the registers RegPBPullup, RegPBOut and RegPBDir define the analog configuration (see Table 12-8). When PBAna[x] = 1, then PBPullup[x] connects the pin to the analog bus. PBDir[x] and PBPOut[x] select which of the 4 analog lines is used. For odd values of x, the selection bits are in the register RegPBOut (see Table 12-8). For even values of x, the selection bits are in the register RegPBDir (see Table 12-9). if x is odd, PBOut[x, x-1] PBPullup[x] PB[x] selection on 00 1 analog line 0 01 1 analog line 1 10 1 analog line 2 11 1 analog line 3 XX 0 High impedance Table 12-8: Selection of the analog lines for PB[x] when x is odd and PBAna[x] = 1 © Semtech 2006 www.semtech.com 12-3

XE8805/05A if x is even, PBDir[x+1, x] PBPullup[x] PB[x] selection on 00 1 analog line 0 01 1 analog line 1 10 1 analog line 2 11 1 analog line 3 XX 0 High impedance Table 12-9: Selection of the analog lines for PB[x] when x is even and PBAna[x] = 1 Example: r Set the pads PB[2] and PB[3] on the analog line 3. (the values X depend on the configuration of others pads) o - apply high impedance in the analog mode (move RegPBPullup,#0bXXXX00XX) f - go to analog mode (move RegPBAna,#0bXXXXXX1X) - select the analog line3 (move RegPBDir,#0bXXXX11XX and move RegPBOut,#0bXXXX11XX) d - connect the analog line to the pins (move RegPBPullup,#0bXXXX11XX) e 12.5.2 Port B analog function specification d The table below defines the on-resistance of the switches between the pin and the analog bus for different conditions. The series resistance between 2 pins of Port B connnected to the sasme analog line is twice the resistance given in the table. e n sym description min typ max unit Comments m g Ron switch resistance 11 kΩ Note 1 Ron switch resistance 15 kΩ Note 2 i Cin input capacitance (off) m 3.5 s pF Note 3 Cin input capacitance (on) 4.5 pF Note 4 e Table 12-10. Analog input specifications. o D Note 1: This is the series resistance between the pad and the analog line in 2 cases c 1. VBAT ≥ 2.4V and the VMULT peripheral is present on the circuit and enabled. 2. VBAT ≥ 3.0V aend the VMULT peripheral is not present on the circuit. w Note 2: This is the series resistance in case VBAT ≥ 2.8V and the peripheral VMULT is not present on the circuit. Note 3: This is the input capaRcitance seen on the pin when the pin is not connected to an analog line. This value is indicative only since it is product and packagee dependent. Note 4: This is the inpu t capacitance seen on the pin when the pin is connected to an analog line and no other pin N is connected to the stame analog line. This value is indicative only since it is product and package dependent. o N 12.6 Port B function capability The Port B can be used for different functions implemented by other peripherals. The description below is applicable only in so far the circuit contains these peripherals. When the counters are used to implement a PWM function (see the documentation of the counters), the PB[0] and PB[1] terminals are used as outputs (PB[0] is used if CntPWM0 in RegCntConfig1 is set to 1, PB[1] is used if CntPWM1 in RegCntConfig1 is set to 1) and the PWM generated values overwrite the values written in RegPBout. However, PBDir(0) and PBDir(1) are not automatically overwritten and have to be set to 1. If OutputCkXtal is set in RegSysMisc, the Xtal clock is output on PB[3] (EnableXtal in RegSysClock must be set to 1). This overrides the value contained in PBOut(3). However, PBDir(3) must be set to 1. The duty cycle of the clock signal is about 50%. Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value contained in PBOut(2). However, PBDir(2) must be set to 1. © Semtech 2006 www.semtech.com 12-4

XE8805/05A The frequency of the CPU clock depends on the selection of the CpuSel bit in the RegSysClock register (see clock_gen_ff). Pins PB[5] and PB[4] can be used for S1 and S0 of the USRT (see USRT documentation) when the UsrtEnable bit is set in RegUsrtCtrl. The PB[5] and PB[4] then become open-drain. This overrides the values contained in PBOpen(5:4), PBOut(5:4) and PBDir(5:4). If there is no external pull-up resistor on these pins, internal pull-ups should be selected by setting PBPullup(5:4). When S0 is an output, the pin PB[4] takes the value of UsrtS0 in RegUrstS0. When S1 is an output, the pin PB[5] takes the value of UsrtS1 in RegUrstS1. Pins PB[6] and PB[7] can be used by the UART (see UART documentation). When UartEnTx in RegUartCtrl is set r to 1, PB[6] is used as output signal Tx. When UartEnRx in RegUartCtrl is set to 1, PB[7] is used as input signal o Rx. This overrides the values contained in PBOut(7:6) and PBDir(7:6). f d 12.7 Port B digital capabilities e 12.7.1 Port B digital configuration d The direction of each bit within Port B (input only or input/outpunt) can be individuaslly set using the RegPBDir register. If PBDir[x] = 1, both the input and output buffer are active on the corresponding Port B. If PBDir[x] = 0, e n the corresponding Port B pin is an input only and the output buffer is in high impedance. After reset (resetpconf) Port B is in input only mode (PBDir[x] are reset to 0). m g The input values of Port B are available in RegPBIn (read only). Reading is always direct - there is no debounce i function in Port B. In case of possible noise on minput signals, a sosftware debouncer with polling or an external hardware filter have to be realized. The input buffer is also active when the port is defined as output and allows to read back the effective value on the pin. e o D Data stored in RegPBOut are output at Port B if PBDir[x] is 1. The default value after reset is low (0). c When a pin is in output mode (PBDir[x] is set to 1), t he output can be a conventional CMOS (Push-Pull) or a N- e channel Open-drain, driving the output only low. By dwefault, after reset (resetpconf) the PBOpen[x] in RegPBOpen is cleared to 0 (push-pull). If PRBOpen[x] in RegPBOpen is set to 1 then the internal P transistor in the output buffer is electrically removed and the output can onely be driven low (PBOut[x]=0). When PBOut[x]=1, the pin is high Impedance. The internal pull-up or an external pull-up resistor can be used to drive the pin high. Note: Because the Pt transistor actually eNxists (this is not a real Open-drain output) the pull-up range is limited to VDD + 0.2Vo (avoid forward bias the P transistor / diode). Each bit canN be set individually for pull-up or not using register RegPBPullup. Input is pulled up when its corresponding bit in this register is set to 1. Default status after (resetpconf) is 0, which means without pull up. To limit power consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an N- channel open-drain output with the pad set to 1. In the other cases (push-pull output or open-drain output driven low), the pull up resistors are disabled independent of the value in RegPBPullup. After power-on reset, the Port B is configured as an input port without pull-up. The input buffer is always active, except in analog mode. This means that the Port B input should be a valid digital value at all times unless the pin is set in analog mode. Violating this rule may lead to higher power consumption. © Semtech 2006 www.semtech.com 12-5

XE8805/05A 12.7.2 Port B digital function specification Sym description min typ max unit Comments V Input high voltage 0.7*VBAT VBAT V VBAT≥2.4V INH V Input low voltage VSS 0.2*VBAT V VBAT≥2.4V INL VOH Output high voltage VBAT-0.4 VBAT V VBAT=1.2V, IOH =0.3m A VBAT=2.4V, IOH =5.r0mA VBAT=4.5V, I =8.0mA OHo V Output low voltage VSS VSS+0.4 V VBAT=1.2V, I =0.3mA OL OL VBAT=f2.4V, IOL = 12.0mA VBdAT=4.5V, I OL =15.0mA R Pull-up resistance 20 50 80 kΩ e PU Cin Input capacitance 3.5 pF Note 1 d Note 1: this value is indicative only since it depends on the package. n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 12-6

XE8805/05A 13 Port C 13.1 Features r 13-2 o 13.2 Overview 13-2 f 13.3 Port C (PC) Operation 13-2 d 13.4 Register map 13-2 e 13.5 Port C electrical specification d 13-3 n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 13-1

XE8805/05A 13.1 Features • Input / output port, 8 bits wide • Each bit can be set individually for input or output 13.2 Overview Port C (PC) is a general purpose 8 bit input/output digital port. r Figure 13-1 shows its structure. o f Port C d e 8 RegPCOut d 8 nRegPCDir s e n 8 RegPCIn m g i m s Figure 13-1: structure of Port C e o D c 13.3 Port C (PC) Operation e w The direction of each bit within Port C (input or output) can be individually set by using the RegPCDir register. If R PCDir[x] = 1, the corresponding Port C pin becomes an output. After reset, Port C is in input mode (PCDir[x] are reset to 0). e N Output mode: t Data is stored in RoegPCOut prior to output at Port C. Input mode: N The status of Port C is available in RegPCIn (read only). Reading is always direct - there is no digital debounce function associated with Port C. In case of possible noise on input signals, a software debouncer or an external filter must be realized. By default after reset, Port C is configured as an input port. 13.4 Register map There are three registers in the Port C (PC), namely RegPCIn, RegPCOut and RegPCDir. Table 13-1 to Table 13-3 show the mapping of control bits and functionality of these registers. Pos. RegPCIn Rw Reset Description 7-0 PCIn r - pad PC input value Table 13-1. RegPCIn © Semtech 2006 www.semtech.com 13-2

XE8805/05A Pos. RegPCOut Rw Reset Description 7-0 PCOut r w 0 resetpconf pad PC output value Table 13-2. RegPCOut Pos. RegPCDir Rw Reset Description 7-0 PCDir r w 0 resetpconf pad PC direction (0=input) Table 13-3. RegPCDir r o f 13.5 Port C electrical specification d e Sym description min typ max unit Comments d V Input high voltage 0.7*VBAT VBAT V VBAT≥2.4V INH V Input low voltage VSS 0.2*VBAT V VBAT≥2.4V INL n s V Output high voltage VBAT-0.4 VBAT V VBAT=1.2V, I =0.3mA OH OH e VBAT=n2.4V, IOH =5.0mA VBAT=4.5V, I =8.0mA OH V Output low voltage VSS VmSS+0.4 V VgBAT=1.2V, I =0.3mA OL OL VBAT=2.4V, I OL i =12.0mA m s VBAT=4.5V, I OL =15.0mA e Cin Input capacitance 3.0 pF Note 1 o D Note 1: this value is indicative only sincce it depends on the package. e Table 13-4. Port C electrical specification w R e N t o N © Semtech 2006 www.semtech.com 13-3

XE8805/05A 14 UART 14.1 Features r 14-2 o 14.2 Overview 14-2 f 14.3 Registers map 14-2 d 14.4 Interrupts map 14-3 e 14.5 Uart baud rate selection d 14-3 14.5.1 Uart on the RC oscillator 14-3 14.5.2 Uart on the crystal oscillator n s 14-4 14.6 Function description e n 14-4 14.6.1 Configuration bits 14-4 14.6.2 Transmission m g 14-5 14.6.3 Reception 14-5 i 14.7 Interrupt or polling m s 14-6 e 14.8 Software hints o 14-7 D c e w R e N t o N © Semtech 2006 www.semtech.com 14-1

XE8805/05A 14.1 Features • Full duplex operation with buffered receiver and transmitter. • Internal baud rate generator with 12 programmable baud rates (300 - 115200). • 7 or 8 bits word length. • Even, odd, or no-parity bit generation and detection • 1 stop bit • Error receive detection: Start, Parity, Frame and Overrun r • Receiver echo mode o • 2 interrupts (receive full and transmit empty) • Enable receive and/or transmit f • Invert pad Rx and/or Tx d 14.2 Overview e The UART pins are PB[7], which is used as Rx - receive and PB[6] as Tx - transmit. d 14.3 Registers map n s e n pos. RegUartCmd rw Reset Description 7 SelXtal rw 0 resetsystem m Select ingput clock: 0 = RC, 1 = xtal 6 UartEnRx2 rw 0 resetsystem Enable Uart Reception i 5-3 UartRcSel(2:0) rw 000 resetsystem RC prescaler selection m s 2 UartPM rw 0 resetsystem Select parity mode: 0 = odd, 1 = even 1 UartPE rw 0 resetsystem Eenable parity: 1 = with parity, 0 = no parity 0 UartWL rw o1 resetsystem Select word length: 1 = 8 bits, 0 = 7 bits D c Table 14-1: RegUartCmd e Pos. RegUartCtrl rw resewt Description 7 UartEcho R rw 0 resetsystem Enable echo mode: e 1 = echo Rx->Tx, 0 = no echo 6 UartE nRx1 rw 0 resetsystem Enable uart reception 5 UatrtEnTx rw N0 resetsystem Enable uart transmission 4 oUartXRx rw 0 resetsystem Invert pad Rx 3 UartXTx rw 0 resetsystem Invert pad Tx 2-0 N UartBR(2:0) rw 101 resetsystem Select baud rate Table 14-2: RegUartCtrl pos. RegUartTx rw reset Description 7-0 UartTx rw 00000000 Data to be sent resetsystem Table 14-3: RegUartTx © Semtech 2006 www.semtech.com 14-2

XE8805/05A pos. RegUartTxSta rw reset description 7-2 - r 000000 Unused 1 UartTxBusy r 0 resetsystem Uart busy transmitting 0 UartTxFull r 0 resetsystem RegUartTx full Set by writing to RegUartTx Cleared when transferring RegUartTx into internal shift register Table 14-4: RegUartTxSta r o pos. RegUartRx rw reset description 7-0 UartRx r 00000000 Receivefd data resetsystem d Table 14-5: RegUartRx e pos. RegUartRxSta rw Reset description d 7-6 - r 00 Unused 5 UartRxSErr r 0 resetsystem n Start esrror 4 UartRxPErr r 0 resetsystem Parity error 3 UartRxFErr r 0 resetsystem e Frname error 2 UartRxOErr rc 0 resetsystem Overrun error m Clearedg by writing RegUartRxSta 1 UartRxBusy r 0 resetsystem Uart busy receiving i 0 UartRxFull r 0 resetmsystem s RegUartRx full Cleared by reading RegUartRx e Table 14-6: RegUartRxSta o D 14.4 Interrupts map c e interrupt source defaulwt mapping in the interrupt manager Irq_uRart_Tx IrqHig(1) Irq_uart_Rx IerqHig(0) NTable 14-7: Interrupts map t o 14.5 Uart baud rate selection N In order to have correct baud rates, the Uart interface has to be fed with a stable and trimmed clock source. The clock source can be the RC oscillator or the crystal oscillator. The precision of the baud rate will depend on the precision of the selected clock source. 14.5.1 Uart on the RC oscillator To select the RC oscillator for the Uart, the bit SelXtal in RegUartCmd has to be 0. In order to obtain a correct baud rate, the RC oscillator frequency has to be set to one of the frequencies given in the table on the next page. The precision of the obtained baud rate is directly proportional to the frequency deviation with respect to the values in the table. © Semtech 2006 www.semtech.com 14-3

XE8805/05A Frequency selection for correct Uart baud rate with RC oscillator (Hz) 2’457’600 1’843’200 1’228’800 614’400 For each of these frequencies, the baud rate can be selected with the bits UartBR(2:0) in RegUartCtrl and r UartRcSel(2:0) in RegUartCmd as shown in Table 14-8 o RC frequency (Hz) 2’457’600 1’228’800 614’400 1’843’200 f UartRcSel 010 001 000 000 111 38400 d 115200 110 19200 57600 UartBR 101 9600 e 28800 100 Not possible 4800 14400 d Table 14-8: Uart baud rate with RC clock n s Note: The precision of the baud rate is directly proportional to the frequency deviation of the used clock from the e n ideal frequency given in the table. In order to increase the precision and stability of the RC oscillator, the DFLL (digital frequency locked loop) can be used with the crystaml oscillator as a refegrence. i 14.5.2 Uart on the crystal oscillator m s e In order to use the crystal oscillator as the clock source for the Uart, the bit SelXtal in RegUartCmd has to be set. o The crystal oscillator has to be enabled by setting the EnableXtal bit in RegSysClock. The baud rate selection is D done using the UartBR and UartRcSel bits as shown in Table 14-9. c Xtal freq. (Hz) eUartRcSel UartBR Baud rate w 011 2400 R 010 1200 32768 001 e 001 600 000 300 N t Table 14-9: Uart baud rate with Xtal clock o Due to the odd ratio between the crystal oscillator frequency and the baud rate, the generated baud rate has a N systematic error of –2.48%. 14.6 Function description 14.6.1 Configuration bits The configuration bits of the Uart serial interface can be found in the registers RegUartCmd and RegUartCtrl. The bit SelXtal is used to select the clock source (see chapter 14.5). The bits UartSelRc and UartBR select the baud rate (see chapter 14.5). The bits UartEnTx is used to enable or disable the transmission. The bits UartEnRx1 and UartEnRx2 are used to enable or disable the reception. When one is set to 1, the reception is enabled. © Semtech 2006 www.semtech.com 14-4

XE8805/05A The word length (7 or 8 data bits) can be chosen with UartWL. A parity bit is added during transmission or checked during reception if UartPE is set. The parity mode (odd or even) can be chosen with UartPM. Setting the bits UartXRx and UartXTx inverts the Rx respectively Tx signals. The bit UartEcho is used to send the received data automatically back. The transmission function becomes then: Tx = Rx XOR UartXTx. 14.6.2 Transmission r o In order to send data, the transmitter has to be enabled by setting the bit UartEnTx. Data to be sent has to be written to the register RegUartTx. The bit UartTxFull in RegUartTxSta then goes to 1, indicating to the transmitter f that a new word is available. As soon as the transmitter has finished sending the previous word, it then loads the contents of the register RegUartTx to an internal shift register and clears the UartTxFull bit. An interrupt is d generated on Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows that the transmitter is busy transmitting a word. e A timing diagram is shown in Figure 14-1. Data are first sent LSB. d New data should be written to the register RegUartTx only while UanrtTxFull is 0, othesrwise data will be lost. Asynchronous Transmission e n write to RegUartTx m g RegUartTx word 1 i reguarttx_shift word 1 m s shift clock e Tx starot b0 b1 b6/7 parity stop D UartTxBusy c UartTxFull e w Irq_uart_Tx R e Asynchronous Transmission (back to back) N t word 1 word 2 write to RegUartTxo RegUartTx word 1 word 2 N reguarttx_shift word 1 word 2 shift clock Tx start b0 b6/7 stop start UartTxBusy UartTxFull Irq_uart_Tx Figure 14-1. Uart transmission timing diagram. 14.6.3 Reception On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set © Semtech 2006 www.semtech.com 14-5

XE8805/05A and an interrupt is generated on Irq_uart_Rx. This indicates that new data is available in RegUartRx. The timing diagram is shown in Figure 14-2. The UartRxFull bit is cleared when RegUartRx is read. If the register was not read before the receiver transfers a new word to it, the bit UartRxOErr (overflow error) is set and the previous contents of the register is lost. UartRxOErr is cleared by writing any data to RegUartRxSta. The bit UartRxSErr is set if a start error has been detected. The bit is updated at data transfer to RegUartRx. The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the r calculated parity of the received data. The bit is updated at data transfer to RegUartRx. o The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. No stop bit has been detected. f Asynchronous Reception d read of RegUartRx (software) e reguartrx_shift d word 1 RegUartRx n wsord 1 shift clock e n Rx start b0 m b6/7 parity gstop UartRxBusy i m s UartRxFull e o Irq_uart_Rx D c e w Figure 14-2. Uart reception timing diagram. R e 14.7 Interrupt or polling N t The transmission and reception software can be driven by interruption or by polling the status bits. o Interrupt driven reception: each time an Irq_uart_Rx interrupt is generated, a new word is available in RegUartRx. N The register has to be read before a new word is received. Interrupt driven transmission: each time the contents of RegUartTx is transferred to the transmission shift register, an Irq_uart_Tx interrupt is generated. A new word can then be written to RegUartTx. Reception driven by polling: the UartRxFull bit is to be read and checked. When it is 1, the RegUartRx register contains new data and has to be read before a new word is received. Transmission driven by polling: the UartTxFull bit is to read and checked. When it is 0, the RegUartTx register is empty and a new word can be written to it. © Semtech 2006 www.semtech.com 14-6

XE8805/05A 14.8 Software hints Example of program for a transmission with polling: 1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable Uart transmission). 2. Write a byte to RegUartTx. 3. Wait until the UartTxFull bit in RegUartTxSta register equals 0. 4. Jump to 2 to write the next byte if the message is not finished. r 5. End of transmission. o Example of program for a transmission with interrupt: f 1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd d parity, 9600 baud, enable Uart transmission). 2. Write a byte to RegUartTx. e 3. After an interrupt and if the message is not finished, jump to 2 4. End of transmission. d Example of program for a reception with polling: n s 1. The RegUartCmd register and the RegUartCtrl registere are initialized (for nexample: 8 bit word length, odd parity, 9600 baud, enable Uart reception). 2. Wait until the UartRxFull bit in the RegUartRxSta regmister equals 1. g 3. Read the RegUartRxSta and check if there is no error. i 4. Read data in RegUartRx. m s 5. If data is not equal to End-Of-Line, then jump to 2. 6. End of reception. e o Example of program for a reception with interrupt: D c 1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable Uaret reception). w 2. When there is an interrupt, jump to 3 R 3. Read RegUartRxSta and check if there is no error. e 4. Read data in RegUartRx. 5. If data is not equal to End-Of-Line, then jump to 2. N t 6. End of reception. o N © Semtech 2006 www.semtech.com 14-7

XE8805/05A 15 USRT 15.1 Features r 15-2 o 15.2 Overview 15-2 f 15.3 Register map 15-2 d 15.4 Interrupts map 15-4 e 15.5 Conditional edge detection 1 d 15-4 15.6 Conditional edge detection 2 n s 15-4 15.7 Interrupts or polling e n 15-5 15.8 Function description m g 15-5 i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 15-1

XE8805/05A 15.1 Features The USRT implements a hardware support for software implemented serial protocols: • Control of two external lines S0 and S1 (read/write). • Conditional edge detection generates interrupts. • S0 rising edge detection. • S1 value is stored on S0 rising edge. • S0 signal can be forced to 0 after a falling edge on S0 for clock stretching in the low state. • S0 signal can be stretched in the low state after a falling edge on S0 and after a S1 conditiornal detection. o 15.2 Overview f The USRT block supports software universal synchronous receiver and transmitter m ode interfaces. d External lines S0 and S1 respectively correspond to clock line and data line. S0 is mapped to PB[4] and S1 to e PB[5] when the USRT block is enabled. It is independent from RegPBdir (Port B can be input or output). When USRT is enabled, the configurations in port B for PB[4] and PB[5] are overwritten by the USRT configuration. d Internal pull-ups can be used by setting the PBPullup[5:4] bits. n s Conditional edge detections are provided. e n RegUsrtS1 can be used to read the S1 data line from PB[5] in receive mode or to drive the output S1 line PB[5] by writing it when in transmit mode. It is advised to read S1m data when in recegive mode from the RegUsrtBufferS1 register, which is the S1 value sampled on a rising edge of S0. i m s 15.3 Register map e o Block configuration registers: D c e pos. RegUsrtS1 rw resewt function 7-1 - R r 0000000 Unused 0 UsrtS1 rw 1 reesetsystem Write: data S1 written to pad PB[5]), Read: value on PB[5] (not UsrtS1 value). N t Table 15-1: RegUsrtS1 o N pos. RegUsrtS0 rw Reset function 7-1 - r 0000000 Unused 0 UsrtS0 rw 1 resetsystem Write: clock S0 written to pad PB[4], Read: value on PB[4] (not UsrtS0 value). Table 15-2: RegUsrtS0 The values that are read in the registers RegUsrtS1 and RegUsrtS0 are not necessarily the same as the values that were written in the register. The read value is read back on the circuit pins, not in the registers. Since the outputs are open drain, a value different from the register value may be forced by an external circuit on the circuit pins. © Semtech 2006 www.semtech.com 15-2

XE8805/05A pos. RegUsrtCtrl rw reset function 7-4 - r “0000” Unused 3 UsrtWaitS0 r 0 resetsystem Clock stretching flag (0=no stretching), cleared by writing RegUsrtBufferS1 2 UsrtEnWaitCond1 rw 0 resetsystem Enable stretching on UsrtCond1 detection (0=disable) 1 UsrtEnWaitS0 rw 0 resetsystem Enable stretching operation (0=disable) 0 UsrtEnable rw 0 resetsystem Enable USRT operation (0=disable) r Table 15-3: RegUsrtCtrl o pos. RegUsrtCond1 rw reset functiofn 7-1 - r 0000000 Unused d 0 UsrtCond1 r/c 0 resetsystem State of condition 1 detection (1 =detected), cleared when written. e Table 15-4: RegUsrtCond1 d pos. RegUsrtCond2 rw reset n functiosn 7-1 - r 0000000 Unused 0 UsrtCond2 r/c 0 resetsystem Steate of condition 2 ndetection (1 =detected), cleared when written. m g Table 15-5: RegUsrtCond2 i m s pos. RegUsrtBufferS1 rw reset function 7-1 - r 0000000 Unuseed o r Value on S1 at last S0 rising edge. D Clear RegUsrtEdgeS0 bit in RegUsrtEdgeS0 0 UsrtBufferS1 c x w Clear UsrtWaitS0 bit in RegUsrtCtrl with any e value w Table 15-6: RegUsrtBufferS1 R e N t o N © Semtech 2006 www.semtech.com 15-3

XE8805/05A pos. RegUsrtEdgeS0 rw reset function 7-1 - r 0000000 Unused 0 UsrtEdgeS0 r 0 resetsystem State of rising edge detection on S0 (1=detected). Cleared by reading RegUsrtBufferS1 Table 15-7: RegUsrtEdgeS0 15.4 Interrupts map r o interrupt default mapping in the interrupt manager source f Irq_cond1 RegIrqMid(7) d Irq_cond2 RegIrqMid(6) e Table 15-8: Interrupts map d 15.5 Conditional edge detection 1 n s e n m g S1 i m s S0 e o D c e Figure 15-1: Condition 1 w R Condition 1 is satisfied when S0=1 at the falling edge of S1. The bit UsrtCond1 in RegUsrtCond1 is set when the e condition 1 is detected and the USRT interface is enabled (UsrtEnable=1). Condition 1 is asserted for both modes (receiver and transmitter). The UsrtCondN1 bit is read only and is cleared by all reset conditions and by writing any t data to its address. o Condition 1 occurrence also generates an interrupt on Irq_cond1. N 15.6 Conditional edge detection 2 S1 S0 Figure 15-2: Condition 2 © Semtech 2006 www.semtech.com 15-4

XE8805/05A Condition 2 is satisfied when S0=1 at the rising edge of S1. The bit UsrtCond2 in RegUsrtCond2 is set when the condition 2 is detected and the USRT interface is enabled. Condition 2 is asserted for both modes (receiver and transmitter). The UsrtCond2 bit is read only and is cleared by all reset conditions and by writing any data to its address. Condition 2 occurrence also generates an interrupt on Irq_cond2. 15.7 Interrupts or polling In receive mode, there are two possibilities for detecting condition 1 or 2: the detection of the condition can r generate an interrupt or the registers can be polled (reading and checking the RegUsrtCond1 and RegUsrtCond2 o registers for the status of USRT communication). f 15.8 Function description d The bit UsrtEnable in RegUsrtCtrl is used to enable the USRT interface aend controls the PB[4] and PB[5] pins. This bit puts these two port B lines in the open drain configuration requested to use the USRT interface. d If no external pull-ups are added on PB[4] and PB[5], the user can activate internal pull-ups by setting PBPullup[4] n s and PBPullup[5] in RegPBPullup. e n The bits UsrtEnWaitS0, UsrtEnWaitCond1, UsrtWaitS0 in RegUsrtCtrl are used for transmitter/receiver control of USRT interface. m g Figure 15-3 shows the unconditional clock stretching function which is einabled by setting UsrtEnWaitS0. m s e o D S0 c e w UsrtWaitS0 R e N write RegUsrtBtufferS1 o N Figure 15-3: S0 Stretching (UsrtEnWaitS0=1) When UsrtEnWaitS0 is 1, the S0 line will be maintained at 0 after its falling edge (clock stretching). UsrtWaitS0 is then set to 1, indicating that the S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1 register. The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4 shows the conditional clock stretching function which is enabled by setting UsrtEnWaitCond1. © Semtech 2006 www.semtech.com 15-5

XE8805/05A S1 S0 UsrtWaitS0 r o f write RegUsrtBufferS1 d e Figure 15-4: Conditional stretching (UsrtEndWaitCond1=1) n s When UsrtEnWaitCond1 is 1, the S0 signal will be stretched in its low state after its falling edge if the condition 1 has been detected before (UsrtCond1=1). UsrtWaitS0 is then set to 1, indicating that the S0 line is forced low. e n One can release S0 by writing to the RegUsrtBufferS1 register. m g Figure 15-5 shows the sampling function implemented by the UsrtBufferS1 bit. The bit UsrtBufferS1 in RegUsrtBufferS1 is the value of S1 sampled on PB[4] at the last riising edge of S0. The bit UsrtEdgeS0 in RegUsrtEdgeS0 is set to one on the same mS0 rising edge asnd is cleared by a read operation of the RegUsrtBufferS1 register. The bit therefore indicates that a new value is present in the RegUsrtBufferS1 which e has not yet been read. o D c S1 e w R e S0 N t o UsrtBufferS1 N read RegUsrtBufferS1 UsrtEdgeS0 Figure 15-5: S1 sampling © Semtech 2006 www.semtech.com 15-6

XE8805/05A 16. Acquisition Chain 16.1 ZoomingADC™ Features.......................................................................................................16-2 16.2 Overview.................................................................................................................................16-2 16.3 Register map..........................................................................................................................16-2 16.4 ZoomingADC™ Description...................................................................................................16-4 r 16.4.1 Acquisition Chain.....................................................................................................................16-4 o 16.4.2 Peripheral Registers.................................................................................................................16-6 16.4.3 Continuous-Time vs. On-Request............................................................................................16-8 f 16.5 Input Multiplexers..................................................................................................................16-9 d 16.6 Programmable Gain Amplifiers..................................................e.........................................16-10 16.6.1 PGA & ADC Enabling.............................................................................................................16-12 16.6.2 PGA1.....................................................................................d................................................16-12 16.6.3 PGA2.....................................................................................................................................16-12 16.6.4 PGA3.............................................................................n..............................s..........................16-12 16.7 ADC Characteristics.............................................e..............................n.................................16-13 16.7.1 Conversion Sequence............................................................................................................16-13 16.7.2 Sampling Frequency.......................................m..............................g.........................................16-14 16.7.3 Over-Sampling Ratio..............................................................................................................16-14 i 16.7.4 Elementary Conversions........................................................................................................16-14 m s 16.7.5 Resolution..............................................................................................................................16-15 16.7.6 Conversion Time & Throughput.............................................................................................16-16 e 16.7.7 Output Code Format.................o.............................................................................................16-16 16.7.8 Power Saving Modes...........................................D..................................................................16-18 c 16.8 Specifications and Measured Curves.................................................................................16-18 16.8.1 Default Settings..........e.............................w...............................................................................16-19 16.8.2 Specifications.........................................................................................................................16-20 R 16.8.3 Linearity.................................................................................................................................16-21 e 16.8.3.1 Integral non-linearity...............................................................................................................16-21 16.8.3.2 Differential n on-linearity.........................................................................................................16-25 N t 16.8.4 Noise......................................................................................................................................16-26 o 16.8.5 Gain Error and Offset Error....................................................................................................16-27 16.8.6 Power Consumption...............................................................................................................16-28 N 16.8.7 Power Supply Rejection Ratio................................................................................................16-30 16.9 Application Hints..................................................................................................................16-31 16.9.1 Input Impedance....................................................................................................................16-31 16.9.2 PGA Settling or Input Channel Modifications..........................................................................16-31 16.9.3 PGA Gain & Offset, Linearity and Noise.................................................................................16-31 16.9.4 Frequency Response.............................................................................................................16-32 16.9.5 Power Reduction....................................................................................................................16-33 © Semtech 2006 www.semtech.com 16-1

XE8805/05A 16.1 ZoomingADC™ Features The ZoomingADC™ is a complete and versatile low-power analog front-end interface typically intended for sensing applications. The key features of the ZoomingADC™ are: Programmable 6 to 16-bit dynamic range oversampled ADC • Flexible gain programming between 0.5 and 1000 • Flexible and large range offset compensation r • 4-channel differential or 8-channel single-ended input multiplexer o • 2-channel differential reference inputs • Power saving modes f • Direct interfacing to CoolRisc™ microcontroller d e 16.2 Overview d f f S S 0 n s PGA1 PGA2 PGA3 1 Analog 23 X VIN VD1 e VD2 nVIN,ADC 16 Inputs 4 U GD1 GD2m GD3g ADC M 5 6 i 7 m s OFF2 e OFF3 Input o Selection D 0 c Reference 1 X VREF Ue Inputs 2 M w 3 R Offset2 Offset3 e Reference Gain1 Gain2 Gain3 t Selection N o ZOOM N Figure 16-1. ZoomingADC™ general functional block diagram The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an oversampled A/D converter. The reference voltage can be selected on two different channels. Two offset compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset allow one to zoom in on a small portion of the reference voltage defined input range. 16.3 Register map There are eight registers in the acquisition chain (AC), namely RegAcOutLsb, RegAcOutMsb, RegAcCfg0, RegAcCfg1, RegAcCfg2, RegAcCfg3, RegAcCfg4 and RegAcCfg5. Table 16-2 to Table 16-9 show the mapping of control bits and functionality of these registers while Table 16-1 gives an overview of these eight. The register map only gives a short description of the different configuration bits. More detailed information is found in subsequent sections. © Semtech 2006 www.semtech.com 16-2

XE8805/05A register name RegAcOutLsb RegAcOutMsb RegAcCfg0 RegAcCfg1 RegAcCfg2 RegAcCfg3 RegAcCfg4 RegAcCfg5 r o Table 16-1: AC registers f pos. RegAcOutLsb rw reset description 00000000 d 7:0 Out[7:0] r LSB of the output code resetsystem e Table 16-2: RegAcOutLsb d pos. RegAcOutMsb rw reset description 00000000 n s 7:0 Out[15:8] r MSB of the output code resetsystem e n Table 16-3: RegAcOutMsb m g pos. RegAcCfg0 rw reset description i 7 Start w r0 0 resetmsystem s starts a conversion 6:5 SET_NELCONV[1:0] r w 01 resetsystem sets the number of elementary conversions esets the oversampling rate of an elementary 4:2 SET_OSR[2:0] r w 010 resetsystem o conversion 1 CONT r w 0 resetsystem D continuous conversion mode 0 reserved rc w 0 resetsystem Table 16-4: RegAcCfg0 e w R pos. RegAcCfg1 rw reset description e 7:6 IB_AMP_ADC[1:0] r w 11 resetsystem Bias current selection of the ADC converter 5:4 IB_AMP _PGA[1:0] r w 11 resetsystem Bias current selection of the PGA stages N t 0000 3:0 ENABLE[3:0] r w Enables the different PGA stages and the ADC o resetsystem Table 16-5: RegAcCfg1 N pos. RegAcCfg2 rw reset description 7:6 FIN[1:0] r w 00 resetsystem Sampling frequency selection 5:4 PGA2_GAIN[1:0] r w 00 resetsystem PGA2 stage gain selection 0000 3:0 PGA2_OFFSET[3:0] r w PGA2 stage offset selection resetsystem Table 16-6: RegAcCfg2 © Semtech 2006 www.semtech.com 16-3

XE8805/05A pos. RegAcCfg3 rw reset description 7 PGA1_GAIN r w 0 resetsystem PGA1 stage gain selection 6:0 PGA3_GAIN[6:0] r w 0000000 PGA3 stage gain selection resetsystem Table 16-7: RegAcCfg3 pos. RegAcCfg4 rw reset description 7 reserved r 0 Unused r 6:0 PGA3_OFFSET[6:0] r w 0000000 PGA3 stage offset seolection resetsystem f Table 16-8: RegAcCfg4 d pos. RegAcCfg5 rw reset description 7 BUSY r 0 resetsystem eActivity flag 6 DEF w r0 0 Selects default configuration d 5:1 AMUX[4:0] r w 00000 Input channel configuration selector resetsystem 0 VMUX r w 0 resetsystem n Reference chansnel selector Table 16-9: ReegAcCfg5 n m g i 16.4 ZoomingADC™ Description m s e Figure 16-2 gives a more detailed description of the acquisition chain. o D c 16.4.1 Acquisition Chain e w Figure 16-1 shows the general block diagram of the acquisition chain (AC). A control block (not shown in Figure 16-1) manages all communicRations with the CoolRisc™ microcontroller. e Analog inputs can be selected among eight input channels, while reference input is selected between two N differential channels.t o The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of a combination Nof input and reference signals V and V , the input voltage is modulated and amplified through IN REF stages 1 to 3. Fine gain programming up to 1'000V/V is possible. In addition, the last two stages provide programmable offset. Each amplifier can be bypassed if needed. The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal V into digital. IN,ADC Like most ADCs intended for instrumentation or sensing applications, the ZoomingADC™ is an over-sampled converter (See Note1). The ADC is a so-called incremental converter, with bipolar operation (the ADC accepts both positive and negative input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers the quantity: 1 Note: Over-sampled converters are operated with a sampling frequency f much higher than the input signal's Nyquist rate (typically f is 20- S S 1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications. © Semtech 2006 www.semtech.com 16-4

XE8805/05A OUT V ADC ≅ IN,ADC (Eq. 1) FS/2 V /2 REF in two's complement (see Sections 16.4 and 16.7 for details). The output code OUT is -FS/2 to +FS/2 for V ADC IN,ADC ≅ -V /2 to +V /2 respectively. As will be shown in section 16.6, V is related to input voltage V by the REF REF IN,ADC IN relationship: V =GD ⋅V −GDoff ⋅V (V) (Eq. 2) IN,ADC TOT IN TOT REF r where GD is the total PGA gain, and GDoff is the total PGA offset. o TOT TOT f d Inputs f f S S 0 1 PGA1 PGA2 PGA3 eV 2 V IN,ADC IN 3 X d AC_A U GD1 GD2 GD3 ADC 4 M 5 6 n s 7 e n OFF2 OFF3 m g 0 AC_R 1 UX VREF i 2 M m s 3 e o D c5 2 4 7 7 Acquisition Chain Register Bank e w RegACCfg5 R RegACCfg4 e 8 RegACCfg3 RegACOutLSB N 8 tRegACCfg2 RegACOutMSB o RegACCfg1 Power Saving Modes PGA Enabling ADC Busy Flag N RegACCfg0 Default Settings Conversion Start Nbr of Elementary Cycles Sampling Frequency fS Over-Sampling Ratio Continuous vs. On-Request Figure 16-2. ZoomingADC™ detailed functional block diagram © Semtech 2006 www.semtech.com 16-5

XE8805/05A 16.4.2 Peripheral Registers Figure 16-2 shows a detailed functional diagram of the ZoomingADC™. In table 16-10 the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain (RegAcCfg0 to 5), and two registers are used to store the output code of the analog-to-digital conversion (RegAcOutMsb & Lsb). The register coding of the ADC parameters and performance characteristics are detailed in Section 16.7. r o Table 16-10. Peripheral registers to configure the acquisition chain (AC) f and to store the analog-to-digital conversion (ADC) result d Register Bit Position Name e 7 6 5 4 3 2 1 0 RegAcOutLsb OUT[7:0] d RegAcOutMsb OUT[15:8] n s RegAcCfg0 START SET_NELC[1:0] SET_OSR[2:0] CONT TEST Default values: 0 01 e010 n0 0 RegAcCfg1 IB_AMP_ADC[1:0] IB_AMP_PGA[1:0] ENABLE[3:0] Default values: 11 11 m g0001 RegAcCfg2 FIN[1:0] PGA2_GAIN[1:0] PGA2_OFFSET[3:0] Default values: 00 00 i 0000 RegAcCfg3 PGA1_G m PGA3_GAIN[s6:0] Default values: 0 0000000 RegAcCfg4 PGA3_OFFeSET[6:0] Default values: 0 o 0000000 D RegAcCfg5 BUSY DEF AMUX[4:0] VMUX Default values: 0 0 c 00000 0 e With: w • OUT: (r) digital output code oRf the analog-to-digital converter. (MSB = OUT[15]) • START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0. e • SET_NELC: (rw) sets the number of elementary conversions to 2SET_NELC[1:0] . To compensate for offsets, the input signal is chopped between elementary conversioNns (1,2,4,8). t • SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]) . OSR = 8, 16, 32, ..., o 512, 1024. • CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1. N • TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten. • IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. • IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation. • ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are disabled are bypassed. • FIN: (rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the sampling frequency is given as: 00 (cid:198) 1/4 f , 01 (cid:198) 1/8 f , 10 (cid:198) 1/32 f , 11(cid:198) ~8kHz. RC RC RC • PGA1_GAIN: (rw) sets the gain of the first stage: 0 (cid:198) 1, 1 (cid:198) 10. • PGA2_GAIN: (rw) sets the gain of the second stage: 00 (cid:198) 1, 01 (cid:198) 2, 10 (cid:198) 5, 11 (cid:198) 10. • PGA3_GAIN: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]⋅1/12. • PGA2_OFFSET: (rw) sets the offset of the second stage between –1 and +1, with increments of 0.2. The MSB gives the sign (0 → positive, 1 → negative); amplitude is coded with the bits PGA2_OFFSET[5:0]. • PGA3_OFFSET: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 → positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0]. © Semtech 2006 www.semtech.com 16-6

XE8805/05A • BUSY: (r) set to 1 if a conversion is running. Note that the flag is set at the effective start of the conversion. Since the ADC is generally synchronized on a lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC sampling frequency) between the writing of the START or CONT bits and the appearance of BUSY flag. • DEF: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one. • AMUX(4:0): (rw) AMUX[4] sets the mode (0 (cid:198) 4 differential inputs, 1 (cid:198) 7 inputs with A(0) = common reference) AMUX(3) sets the sign (0 (cid:198) straight, 1(cid:198) cross) AMUX[2:0] sets the channel. • VMUX: (rw) sets the differential reference channel (0 (cid:198) R(1) and R(0), 1 (cid:198) R(3) and R(2)). (r = read; w = write; rw = read & write) r o f d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 16-7

XE8805/05A 16.4.3 Continuous-Time vs. On-Request The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit CONT). In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new one is automatically initiated. The new value is then written in the result register, and the corresponding internal trigger pulse is generated. This operation is sketched in Figure 16-3. The conversion time in this case is defined as r T . CONV o T CONV f Internal Trig d Ouput Code RegACOut[15:0] e BUSY IRQ d n s Figure 16-3. ADC "continuous-time" operation e n T CONV m g Internal Trig Request i START m s Ouput Code RegACOut[15:0] e BUoSY D IRQ c e w Figure 16-4. ADC "on-request" operation R e In the "on-request" mode, the internal behaviour of the converter is the same as in the "continuous-time" mode, but the conversion is initiated on user requeNst (with the START bit). As shown in Figure 16-4, the conversion time is t also T . Note that the flag is set at the effective start of the conversion. Since the ADC is generally synchronized CONV o on a lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC sampling frequency) between the writing of the START or CONT bits and the appearance of BUSY flag. N © Semtech 2006 www.semtech.com 16-8

XE8805/05A 16.5 Input Multiplexers The ZoomingADC™ has eight analog inputs AC_A(0) to AC_A(7) and four reference inputs AC_R(0) to AC_R(3). Let us first define the differential input voltage V and reference voltage V respectively as: IN REF V =V −V (V) (Eq. 3) IN INP INN and: r o V =V −V (V) (Eq. 4) REF REFP REFN f As shown in Table 16-11 the inputs can be configured in two ways: either as 4 differential channels (V = IN1 AC_A(1) - AC_A(0),..., V = AC_A(7) - AC_A(6)), or AC_A(0) can be used ads a common reference, providing IN4 7 signal paths all referred to AC_A(0). The control word for the analog input selection is AMUX[4:0]. Notice that e the bit AMUX[3] controls the sign of the input voltage. d AMUX[4:0] V V AMUX[4:n0] V sV (RegAcCfg5[5:1]) INP INN (RegAcCfg5[5:1]) INP INN 00x00 AC_A(1) AC_A(0) 0e1x00 AC_An(0) AC_A(1) 00x01 AC_A(3) AC_A(2) 01x01 AC_A(2) AC_A(3) 00x10 AC_A(5) AC_A(4) m 01x10 gAC_A(4) AC_A(5) 00x11 AC_A(7) AC_A(6) 01x11 AC_A(6) AC_A(7) 10000 AC_A(0) 11000 i AC_A(0) 10001 AC_A(1) m 11001 s AC_A(1) 10010 AC_A(2) 11010 AC_A(2) e 10011 AC_A(3) 11011 AC_A(3) ACo_A(0) AC_A(0) 10100 AC_A(4) 11100 AC_A(4) D 10101 AC_A(5) 11101 AC_A(5) 10110 AC_A(6) c 11110 AC_A(6) 10111 AC_A(7) 11111 AC_A(7) e w R Table 16-11. Analog input selection e Similarly, the reference voltage is chosenN among two differential channels (V = AC_R(1)-AC_R(0) or V = t REF1 REF2 AC_R(3)-AC_R(2)) as shown in Table 16-12. The selection bit is VMUX. The reference inputs V and V o REFP REFN (common-mode) can be up to the power supply range. N © Semtech 2006 www.semtech.com 16-9

XE8805/05A VMUX V V (RegAcCfg5[0]) REFP REFN 0 AC_R(1) AC_R(0) 1 AC_R(3) AC_R(2) Table 16-12. Analog Reference input selection r o 16.6 Programmable Gain Amplifiers f As seen in Figure 16-1, the zooming function is implemented with three programmable gain amplifiers (PGA). d These are: • PGA1: coarse gain tuning e • PGA2: medium gain and offset tuning • PGA3: fine gain and offset tuning d All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and gain, as well as the offset of stages 2 and 3. These functions arne examined hereafster. e n ENABLE[3:0] m Block g xxx0 ADC disabled xxx1 ADC enabiled m s xx0x PGA1 disabled xx1x PGA1 enabled e ox0xx PGA2 disabled x1xx DPGA2 enabled c 0xxx PGA3 disabled 1xxx PGA3 enabled e Table 16-w13. ADC & PGA enabling R e PGA1 Gain PGA1_GAIN GD1 (V/V) N t 0 1 o 1 10 Table 16-14. PGA1 Gain Settings N PGA2 Gain PGA2_GAIN[1:0] GD (V/V) 2 00 1 01 2 10 5 11 10 Table 16-15. PGA2 gain settings © Semtech 2006 www.semtech.com 16-10

XE8805/05A PGA2 Offset PGA2_OFFSET[3:0] GDoff (V/V) 2 0000 0 0001 +0.2 0010 +0.4 0011 +0.6 0100 +0.8 0101 +1 1001 -0.2 1010 -0.4 r 1011 -0.6 o 1100 -0.8 1101 -1 f Table 16-16. PGA2 offset settings d PGA3_GAIN[6:0] PGA3 Gain e GD (V/V) 3 0000000 0 d 0000001 1/12(=0.083) ... n... s 0000110 6/12 ... e ... n 0001100 12/12 0010000 m 16/12 g ... 0100000 32/12i ... m s 1000000 64/12 ... e 1o111111 127/12(=10.58) D c Table 16-17. PGA3 gain settings e w PGA3 Offset PGA3_OFFSET[6:0] GDoff (V/V) R 3 0000000 0 e 0000001 +1/12(=+0.083) N0000010 +2/12 t ... ... o 0010000 +16/12 ... ... N 0100000 +32/12 ... ... 0111111 +63/12(=+5.25) 1000000 0 1000001 -1/12(=-0.083) 1000010 -2/12 ... ... 1010000 -16/12 ... ... 1100000 -32/12 ... ... 1111111 -63/12(=-5.25) Table 16-18. PGA3 offset settings © Semtech 2006 www.semtech.com 16-11

XE8805/05A 16.6.1 PGA & ADC Enabling Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the word ENABLE and the coding given in Table 16-13. To reduce power dissipation, the ADC can also be inactivated while idle. 16.6.2 PGA1 The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 16-14). The voltage V at r D1 the output of PGA1 is: o V =GD ⋅V (V) (Eq. 5) D1 1 IN f where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN. d e 16.6.3 PGA2 d The second PGA has a finer gain and offset tuning capability, as shown in Table 16-15 and Table 16-16. The voltage V at the output of PGA2 is given by: n s D2 e n V =GD ⋅V −GDoff ⋅V (V) (Eq. 6) D2 2 D1 2 REF m g where GD and GDoff are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words 2 2 PGA2_GAIN[1:0] and PGA2_OFFSET[3:0]. i m s As shown in equation 6, the offset correction is directly proportional to the reference voltage. All drifts and perturbations on the reference voltage will affect the precision of ethe offset compensation. o D c 16.6.4 PGA3 e w The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table 16-17 and Table 16-18. The Routput of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the voltage entering the ADC is given by: e V =GDt⋅V −GDoff ⋅V N (V) (Eq. 7) IN,ADC 3 D2 3 REF o where GD and GDoff are respectively the gain and offset of PGA3 (in V/V). The control words are 3 3 PGA3_GAIN[N6:0] and PGA3_OFFSET[6:0] . To remain within the signal compliance of the PGA stages, the condition: V ,V <V (V) (Eq. 8) D1 D2 DD must be verified. As shown in equation 7, the offset correction is directly proportional to the reference voltage. All drifts and perturbations on the reference voltage will affect the precision of the offset compensation. © Semtech 2006 www.semtech.com 16-12

XE8805/05A Finally, combining equations Eq. 5 to Eq. 7 for the three PGA stages, the input voltage V of the ADC is related IN,ADC to V by: IN V =GD ⋅V −GDoff ⋅V (V) (Eq. 9) IN,ADC TOT IN TOT REF where the total PGA gain is defined as: GD =GD ⋅GD ⋅GD (V/V) (Eq. 10) TOT 3 2 1 r and the total PGA offset is: o GDoff =GDoff +GD ⋅GDoff (V/V) (Eq. 11) f TOT 3 3 2 d e 16.7 ADC Characteristics d The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three programmable parameters: n s • sampling frequency f , e n S • over-sampling ratio OSR, and m g • number of elementary conversions N . ELCONV i The setting of these parameters and the resulting pmerformances are dsescribed hereafter. e 16.7.1 Conversion Sequence o D A conversion is started each time thce bit START or the bit DEF is set. As depicted in Figure 16-5, a complete analog-to-digital conversion sequence is made of a se t of N elementary incremental conversions and a final e ELCONV quantization step. Each elementary conversion is mawde of (OSR+1) sampling periods T =1/f , i.e.: S S R T =(OSR+1)/f (s) e (Eq. 12) ELCONV S N The result is the mtean of the elementary conversion results. An important feature is that the elementary conversions are aloternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the output code. Thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.Ne. if N ≥ 2). A few additional clock cycles are also required to initiate and end the conversion ELCONV properly. T = (OSR+1)/f ELCONV S Elementary Elementary Elementary Elementary Conversion Init End Conversion Conversion Conversion Conversion Result Conversion index 1 2 N - 1 N ELCONV ELCONV Offset + - + - T CONV Figure 16-5. Analog-to-digital conversion sequence © Semtech 2006 www.semtech.com 16-13

XE8805/05A 16.7.2 Sampling Frequency The word FIN[1:0] is used to select the sampling frequency f (Table 16-19). Three sub-multiples of the internal S RC-based frequency f can be chosen. For FIN = "11", sampling frequency is about 8kHz. Additional RCEXT information on oscillators and their control can be found in the clock block documentation. Sampling Frequency f (Hz) FIN[1:0] S 01/05 02 00 1/4⋅f 1/8⋅f RC RCEXT r 01 1/8⋅f 1/16⋅f RC RCEXT 10 1/32⋅f 1/64⋅f o RC RCEXT 11 ∼8kHz ∼4kHz f Table 16-19. Sampling frequency settings (fRC= RC-badsed frequency) e 16.7.3 Over-Sampling Ratio d The over-sampling ratio (OSR) defines the number of integration cyncles per elementasry conversion. Its value is set with the word SET_OSR[2:0] in power of 2 steps (see Table 16-20) given by: e n 3+SET_OSR[2:0] OSR=2 (-) m (Eq. g13) i SET_OSR[2:0] m Over-Samplings Ratio (RegAcCfg0[4:2]) OSR (-) 000 8e 001o 16 010 D 32 c011 64 100 128 e 101 w 256 110 512 R 111 1024 e TaNble 16-20. Over-sampling ratio settings t o 16.7.4 Elementary Conversions N As mentioned previously, the whole conversion sequence is made of a set of N elementary incremental ELCONV conversions. This number is set with the word SET_NELC[1:0] in power of 2 steps (see Table 16-21) given by: SET_NELC[1:0] N =2 (-) (Eq. 14) ELCONV © Semtech 2006 www.semtech.com 16-14

XE8805/05A # of Elementary SET_NELC[1:0] Conversions (RegAcCfg0[6:5]) N (-) ELCONV 00 1 01 2 10 4 11 8 Table 16-21. Number of elementary conversion settings r As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier ooffsets. f 16.7.5 Resolution d The theoretical resolution of the ADC, without considering thermal noise, is given by: e n=2⋅log (OSR)+log (N ) (Bits) (Eq. 15) 2 2 ELCONV d 17 n s 15 s] SET_NELC= 11 e n Bit13 10 on - n [11 0010 m g oluti 9 i es m s R 7 e 5 o 000 001 010 011 100 101 110 111 D SET_OSR c Figure 16-6. Resolution vs . SET_OSR[2:0] and SET_NELC[2:0] e w RSET_OSR SET_NELC [2:0] 00 e 01 10 11 000 6 7 8 9 N t 001 8 9 10 11 o 010 10 11 12 13 011 12 13 14 15 N 100 14 15 16 16 101 16 16 16 16 110 16 16 16 16 111 16 16 16 16 (shaded area: resolution truncated to 16 bits due to output register size RegAcOut[15:0]) Table 16-22. Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] settings Using look-up Table 16-22 or the graph plotted in Figure 16-6, resolution can be set between 6 and 16 bits. Notice that, because of 16-bit register use for the ADC output, practical resolution is limited to 16 bits, i.e. n ≤ 16. Even if the resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and N to ELCONV higher values in order to reduce the influence of the thermal noise in the PGA (see section 16.8.4). © Semtech 2006 www.semtech.com 16-15

XE8805/05A 16.7.6 Conversion Time & Throughput As explained using Figure 16-5, conversion time is given by: T =(N ⋅(OSR+1)+1)/ f (s) (Eq. 16) CONV ELCONV S and throughput is then simply 1/T . For example, consider an over-sampling ratio of 256, 2 elementary CONV conversions, and a sampling frequency of 500kHz (SET_OSR = "101", SET_NELC = "01", f = 2MHz, and FIN = RC "00"). In this case, using Table 16-23, the conversion time is 515 sampling periods, or 1.03ms. This corresponds to a throughput of 971Hz in continuous-time mode. The plot of Figure 16-7 illustrates the classic trade-off between r resolution and conversion time. o SET_OSR SET_NELC[1:0] [2:0] 00 01 10 11 f 000 10 19 37 73 d 001 18 35 69 137 010 34 67 133 265 e 011 66 131 261 521 100 130 259 517 1033 d 101 258 515 1029 2057 110 514 1027 2053 4105 n s 111 1026 2051 4101 8201 e n Table 16-23. Normalized conversion time (T ⋅f ) vs. SET_OSR[2:0] and SET_NELC[1:0](normamlized to sCaOmNVplinSgg period 1/f ) S i m s 16.0 e s] o Bit 14.0 D n - n [c12.0 eolutio 108..00 w1 1 SET_NELC s 10 e R R 6.0 01 00 e 4.0 10.0 100.0 1000.0 10000.0 N t Normalized Conversion Time - TCONV*fS [-] o Figure 16-7. Resolution vs. normalized conversion time for different SET_NELC[1:0] N 16.7.7 Output Code Format The ADC output code is a 16-bit word in two's complement format (see Table 16-24). For input voltages outside the range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller than 16 bits, the non-significant bits are forced to the values shown in Table 16-25. The output code, expressed in LSBs, corresponds to: V OSR+1 OUT =216⋅ IN,ADC ⋅ (LSB) (Eq.17) ADC V OSR REF Recalling equation Eq. 9, this can be rewritten as: © Semtech 2006 www.semtech.com 16-16

XE8805/05A V ⎛ V ⎞ OSR+1 OUT =216⋅ IN ⋅⎜GD −GDoff ⋅ REF ⎟ ⋅ (LSB) (Eq. 18) ADC VREF ⎜⎝ TOT TOT VIN ⎟⎠ OSR where, from Eq. 10 and Eq. 11, the total PGA gain and offset are respectively: GD =GD ⋅GD ⋅GD (V/V) TOT 3 2 1 and: r GDoff =GDoff +GD ⋅GDoff (V/V) TOT 3 3 2 o f % of ADC Input Output Full Output in Voltage Code d Scale LSBs V in Hex IN,ADC (FS) e +215-1 +2.49505V +0.5⋅FS 7FFF =+32'767 d +215-2 +2.49497V ... 7FFE =+32'766 n s ... ... ... ... +76.145µV ... +1 e 0001 n 0V 0 0 0000 -76.145µV ... m-1 FFFF g ... ... ... ... -215-1 -2.49505V ... 800i1 m =-32'767 s -215 -2.49513V -0.5⋅FS 8000 =-32'768 e o D Table 16-24. Basic ADC Relationships (example for: V = 5V, OSR = 512, n = 16 bits) c REF e w SET_OSR SET_NERLC = 00 SET_NELC = 01 SET_NELC = 10 SET_NELC = 11 [2:0] e 000 1000000000 100000000 10000000 1000000 001 10000000 N 1000000 100000 10000 t 010 100000 10000 1000 100 o 011 1000 100 10 1 100 10 1 - - N 101 - - - - 110 - - - - 111 - - - - Table 16-25. Last forced LSBs in conversion output registers for resolution settings smaller than 16 bits (n < 16) (RegAcOutMsb[7:0] & RegAcOutLsb[7:0]) © Semtech 2006 www.semtech.com 16-17

XE8805/05A The equivalent LSB size at the input of the PGA chain is: 1 V OSR LSB= ⋅ REF ⋅ (V) (Eq. 19) 2n GD OSR+1 TOT Notice that the input voltage V of the ADC must satisfy the condition: IN,ADC V ≤ 1⋅(V −V )⋅ OSR (V) (Eq. 20) IN,ADC 2 REFP REFN OSR+1 r o to remain within the ADC input range. f d 16.7.8 Power Saving Modes e During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the d control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0] (see Table 16-26). If the system is idle, the PGAs and ADC can even be disabled, thus, reducing power consumption to its minimum. This can considerably improve n s battery lifetime. e n IB_[A1M: P0_]A DC IB_[A1M:P0_]P GA ABDiaCsm PBGiaAs M[kaHx.z gf]S Current Current i 00 m 1/4⋅IADC s62.5 01 1/2⋅I 125 x ADC x 10 3/4⋅IADC e 250 11 o I 500 ADC 00 D1/4⋅IPGA 62.5 c 01 1/2⋅I 125 x x PGA 10 3/4⋅IPGA 250 e 11 w IPGA 500 R Table 16-26. ADC & PGA peower saving modes and maximum sampling frequency N t o 16.8 Specifications and Measured Curves N This section presents measurement results for the acquisition chain. A summary table with circuit specifications and measured curves are given. © Semtech 2006 www.semtech.com 16-18

XE8805/05A 16.8.1 Default Settings Unless otherwise specified, the measurement conditions are the following: • Temperature T = +25°C A • V = +5V, GND = 0V, V = +5V, V = 0V DD REF IN • RC frequency f = 2MHz, sampling frequency f = 500kHz RC S • Offsets GDOff = GDOff = 0 2 3 r • Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '11') o • Resolution: for n = 12 bits: OSR = 32 and N = 4 ELCONV for n = 16 bits: OSR = 512 and N = 2 ELCONV f d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 16-19

XE8805/05A 16.8.2 Specifications Unless otherwise specified: Temperature T = +25°C, V = +5V, GND = 0V, V = +5V, V = 0V, RC frequency f = 2MHz, sampling A DD REF IN RC frequency f = 500kHz, Overall PGA gain GD = 1, offsets GDOff = GDOff = 0. Power operation: normal (IB_AMP_ADC[1:0] = S TOT 2 3 IB_AMP_PGA[1:0] = '11'). For resolution n = 12 bits: OSR = 32 and N = 4. For resolution n = 16 bits: OSR = 512 and N = 2. ELCONV ELCONV VALUE PARAMETER UNITS COMMENTS/CONDITIONS MIN TYP MAX ANALOG INPUT CHARACTERISTICS Differential Input Voltage Ranges -2.42 +2.42 V Gain = 1, OSR = 32 (Note 1) V = (V - V ) -24.2 +24.2 mV Gain = 100, OSR = 32 r IN INP INN -2.42 +2.42 mV Gain = 1000, OSR = 32 o Reference Voltage Range V = (V – V ) V V f REF REFP REFN DD PROGRAMMABLE GAIN AMPLIFIERS (PGA) d Total PGA Gain, GD 0.5 1000 V/V TOT PGA1 Gain, GD 1 10 V/V See Table 16-14 1 e PGA2 Gain, GD 1 10 V/V See Table 16-15 2 PGA3 Gain, GD 0 127/12 V/V Step=1/12 V/V, See Table Gain Setting Precision (ea3ch stage) -3 ±0.5 +3 % d16-17 Gain Temperature Dependence ±5 ppm/°C Offset n s PGA2 Offset, GDoff2 -1 +1 V/V PGA3 Offset, GDoff3 -127/12 +127/12e V/V Step=0.n2 V/V, See Table 16-16 Offset Setting Precision (PGA2 or 3) -3 ±0.5 +3 % Step=1/12 V/V, See Table Offset Temperature Dependence ±5 ppm/°C 16-18 Input Impedance m (Ngote 2) PGA1 1500 kΩ 150 kΩ i PGA2, PGA3 150 m kΩs PGA1 Gain = 1 (Note 3) Output RMS Noise PGA1 Gain = 10 (Note 3) PGA1 205 eµV Maximal gain (Note 3) PGA2 340 µV o PGA3 365 µV (Note 4) D (Note 5) c (Note 6) ADC STATIC PERFORMANCE Resolution, n e 6 16 Bits (Note 7) w No Missing Codes (Note 8) Gain Error R ±0.15 % of FS (Note 9) Offset Error ±1 LSB n = 16 bits (Note 10) e Integral Non-Linearity, INL Resolution n =t 16 Bits N ±1.0 LSB (Note 11) Differential Non-Lineaority, DNL Resolution n = 16 Bits ±0.5 LSB (Note 12) Power Supply Rejection Ratio, PSRR 78 dB VDD = 5V ± 0.3V (Note 13) N 72 dB VDD = 3V ± 0.3V (Note 13) DYNAMIC PERFORMANCE Sampling Frequency, f 3 kHz S Conversion Time, T 133 cycles/f n = 12 bits (Note 14) CONV S 1027 cycles/f n = 16 bits (Note 14) S Throughput Rate (Continuous Mode), 3.76 kSps n = 12 bits, f = 500kHz S 1/T 0.49 kSps n = 16 bits, f = 500kHz CONV S Nbr of Initialization Cycles, N 0 2 cycles INIT Nbr of End Conversion Cycles, N 0 5 cycles END PGA Stabilization Delay OSR cycles (Note 15) DIGITAL OUTPUT ADC Output Data Coding Binary Two’s Complement See Table 16-24 and Table 16-25 © Semtech 2006 www.semtech.com 16-20

XE8805/05A Specifications (Cont’d) VALUE PARAMETER UNITS COMMENTS/CONDITIONS MIN TYP MAX POWER SUPPLY Voltage Supply Range, V +2.4 +5 +5.5 V DD Analog Quiescent Current Only Acquisition Chain Consumption, Total (IQ) 720/620 µA VDD = 5V/3V ADC Only 250/190 µA VDD = 5V/3V PGA1 165/150 µA VDD = 5V/3V PGA2 130/120 µA VDD = 5V/3V PGA3 175/160 µA VDD = 5V/3V r Analog Power Dissipation All PGAs & ADC Active Normal Power Mode 3.6/1.9 mW VDD = 5V/3V (Note 1o6) 3/4 Power Reduction Mode 2.7/1.4 mW VDD = 5V/3V (Note 17) 1/2 Power Reduction Mode 1.8/0.9 mW VDD = 5V/3V (fNote 18) 1/4 Power Reduction Mode 0.9/0.5 mW VDD = 5V/3 V (Note 19) TEMPERATURE d Specified Range -40 +85 °C Operating Range -40 +125 °C e d Notes: (1) Gain defined as overall PGA gain GD = GD⋅GnD⋅GD. Maximum sinput voltage is given by: TOT 1 2 3 V = ±(V /2)⋅(OSR/OSR+1). IN,MAX REF (2) Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinesic offset, use only ADCn and PGA1. (3) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is f = S 512kHz. This figure must be multiplied by 2 for fS = 256kHz, m4 for fS = 128kHz. Input gimpedance is proportional to 1/fS. (4) Figure independent from PGA1 gain and sampling frequency f . See model of Figure 16-18(a). S See equation Eq. 21 to calculate equivalent input noise. (5) Figure independent on PGA2 gain and sampling frequency f . See model iof Figure 16-18(a). See equation Eq. 21 to calculate S equivalent input noise. m s (6) Figure independent on PGA3 gain and sampling frequency f . See model of Figure 16-18(a) and equation Eq. 21 to calculate S equivalent input noise. e (7) Resolution is given by n = 2⋅log2(OSR) + olog2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8. D (8) If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data. c (9) Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function (with the offset error removed). (See Figure 16-19) (10) Offset error is defined as the oeutput code error for a zwero volt input (ideally, output code = 0). For ± 1 LSB offset, NELCONV must be ≥2. (11) INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over the full scale. R (12) DNL is defined as the difference (in LSB) betweeen the ideal (1 LSB) and measured code transitions for successive codes. (13) Figures for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage changes. N (14) Conversion timte is given by: T = (N ⋅ (OSR + 1) + 1) / f . OSR can be set between 8 and 1024, in powers of 2. N can CONV ELCONV S ELCONV be set to 1,o 2, 4 or 8. (15) PGAs are reset after each writing operation to registers RegAcCfg1-5. The ADC must be started after a PGA or inputs common- mode stabilisation delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching. N Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without the PGAs. (16) Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = ‘11’ and IB_AMP_ADC[1:0] = ‘11’. (17) Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘10’, IB_AMP_ADC[1:0] = ‘10’. (18) Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘01’, IB_AMP_ADC[1:0] = ‘01’. (19) Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘00’, IB_AMP_ADC[1:0] = ‘00’. 16.8.3 Linearity 16.8.3.1 Integral non-linearity The integral non-linearity depends on the selected gain configuration. First of all, the non-linearity of the ADC (all PGA stages bypassed) is shown in Figure 16-8. © Semtech 2006 www.semtech.com 16-21

XE8805/05A r o f d Figure 16-8. Integral non-linearity of the ADC (PGA disableed, reference voltage of 4.8V) d The different PGA stages have been designed to find the best compromise between the noise performance, the integral non-linearity and the power consumption. To obtain this, thne first stage has thes best noise performance and the third stage the best linearity performance. For large input signals (small PGA gains, i.e. up to about 50), the noise added by the PGA is very small with respect to the inpeut signal and the sencond and third stage of the PGA should be used to get the best linearity. For small input signals (large gains, i.e. above 50), the noise level in the PGA is important and the first stage of the PGA should bem used. g The following figures give the non-linearity for different gain settings of ithe PGA, selecting the appropriate stage to get the best noise and linearity performance. Figurme 16-9 shows the nson-linearity when the third stage is used with a gain of 1. It is of course not very useful to use the PGA with a gain of 1 unless it is used to compensate offset. By e increasing the gain, the integral non-linearity becomes even smaller since the signal in the amplifiers reduces. o D Figure 16-10 shows the non-linearity for a gain of 2. Figure 16-11 shows the non-linearity for a gain of 5. Figure c 16-12 shows the non-linearity for a gain of 10. By comparing these figures to Figure 16-8, it can be seen that the third stage of the PGA does not aedd significant integral non-linearity. w Figure 16-13 shows the non-Rlinearity for a gain of 20 and Figure 16-14 shows the non-linearity for a gain of 50. In both cases the PGA2 is used at a gain of 10 eand the remaining gain is realized by the third stage. It can be seen again that the second s tage of the PGA does not add significant non-linearity. N t For gains above 5o0, the first stage PGA1 should be selected in stead of PGA2. Although the non-linearity in the first stage of the PGA is larger than in stage 2 and 3, the gain in stage 3 is now sufficiently high so that the non-linearity of the first staNge does become negligible as is shown in Figure 16-15 for a gain of 100. Therefor, the first stage is preferred over the second stage since it has less noise. Increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the first two stages. The signal is full scale at the output of stage 3 and as shown in Figure 16-9 to Figure 16-12, this stage has very good linearity. © Semtech 2006 www.semtech.com 16-22

XE8805/05A r o f d e Figure 16-9. Integral non-linearity of the ADC and with gain of 1 (PGA1 and PGA2 disabled, PGA3=1, reference voltage of 5Vd) n s e n m g i m s e o D c e w R Figure 16-10. Integral non-linearitye of the ADC and gain of 2 (PGA1 and PGA2 disabled, PGA3=2 reference voltage of 5V) N t o N Figure 16-11. Integral non-linearity of the ADC and gain of 5 (PGA1 and PGA2 disabled, PGA3=5, reference voltage of 5V) © Semtech 2006 www.semtech.com 16-23

XE8805/05A r o f d e Figure 16-12. Integral non-linearity of the ADC and gain of 10 (PGA1 and PGA2 disabled, PGA3=10, d reference voltage of 5V) n s e n m g i m s e o D c e w R e N t Figureo 16-13. Integral non-linearity of the ADC and gain of 20 (PGA1 and PGA2=10, PGA3=2, reference voltage of 5V) N © Semtech 2006 www.semtech.com 16-24

XE8805/05A r o f d e d Figure 16-14. Integral non-linearity of the ADC and gain of 50 (PGA1 disabled, PGA2=10, PGA3=5, reference voltage nof 5V) s e n m g i m s e o D c e w R e N t o Figure 16-15. Integral non-linearity of the ADC and gain of 100 (PGA1=10 and PGA3=10, PGA2 N disabled, reference voltage of 5V) 16.8.3.2 Differential non-linearity The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure 16-16 shows the differential non-linearity. © Semtech 2006 www.semtech.com 16-25

XE8805/05A r o f d e d Figure 16-16. Differential non-linearity of the ADC converter. n s 16.8.4 Noise e n Ideally, a constant input voltage V should result in a conmstant output code. gHowever, because of circuit noise, the IN output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions for a constant input voltage was performed to derive the equivalent noiise levels of PGA1, PGA2, and PGA3. The m s extracted rms output noise of PGA1, 2, and 3 are given in Table 16-27: standard output deviation and output rms noise voltage. Figure 16-17 shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed). Quantization e noise is dominant in this case, and, thus, the ADC thermal noise is below 16 bits. o D The simple noise model of Figure 16-c18(a) is used to estimate the equivalent input referred rms noise VN,IN of the acquisition chain in the model of Figure 16-18(b). This is given by the relationship: e w V 2 =(VN1/GD1)2 +R(VN2 /(GD1⋅GD2))2 +(VN3 /(GD1⋅GD2⋅GD3))2 (V2rms) (Eq. 21) N,IN (OSR⋅N ) eELCONV where VN1, VN2, and tVN3 are the output rmNs noise figures of Table 16-27, GD1, GD2, and GD3 are the PGA gains of stages 1 to 3 resopectively. As shown in this equation, noise can be reduced by increasing OSR and NELCONV (increases the ADC averaging effect, but reduces noise). N Parameter PGA1 PGA2 PGA3 Standard deviation at 0.85 1.4 1.5 ADC output (LSB) 1 Output rms noise (µV) 205 (VN1) 340 (VN2) 365 (VN3) Note: see noise model of Figure 16-18 and equation Eq. 21. Table 16-27. PGA noise measurements (n = 16 bits, OSR = 512, N = 2, V = 5V) ELCONV REF © Semtech 2006 www.semtech.com 16-26

XE8805/05A 80 es] 60 es mpl Occurenc% of total sa 2400 [ 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 Output Code Deviation From Mean Value [LSB] r Figure 16-17. ADC noise (PGA1, 2 & 3 bypassed, OSR=512,N =2) ELCoONV f f S d PGA1 PGA2 PGA3 e V V V N1 N2 N3 GD1 GD2 GD3 dADC n s (a) e n f S m g PGA1 PGA2 PGA3 V N,IN i GD1 mGD2 GD3 s ADC e o (b) D c Figure 16-18. (a) Simple noise model for PGAs and ADC e and (b) totawl input referred noise R As an example, consider the system where: GD = 10 (GD = 1; PGA3 bypassed), OSR = 512, N = 2, V = e2 1 ELCONV REF 5V. In this case, the noise contribution V of PGA1 is dominant over that of PGA2. Using equation Eq. 21, we get: N1 V = 6.4µV (rms) at the input of the Nacquisition chain, or, equivalently, 0.85 LSB at the output of the ADC. N,IN t Considering a 0.2V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB. o Noise can also be reduced by implementing a software filter. By making an average on a number of subsequent N measurements, the apparent noise is reduced the square root of the number of measurement used to make the average. 16.8.5 Gain Error and Offset Error Gain error is defined as the amount of deviation between the ideal transfer function (theoretical equation Eq. 18) and the measured transfer function (with the offset error removed). The actual gain of the different stages can vary depending on the fabrication tolerances of the different elements. Although these tolerances are specified to a maximum of ±3%, they will be most of the time around ±0.5%. Moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error in the same direction in all stages is very low. Finally, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance. Figure 16-19 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of Full- Scale Range (FSR) normalized to 25°C. © Semtech 2006 www.semtech.com 16-27

XE8805/05A Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC and the PGA1 stage are completely suppressed if N > 1. ELCONV The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 16-20. The output offset error, expressed in LSB for 16-bit setting, is normalized to 25°C. Notice that if the ADC is used alone, the output offset error is below ±1 LSB and has no drift. NORMALIZED TO 25°C 0.2 r R] 0.1 S o F of 0.0 % f r [ -0.1 o r d Er -0.2 1 n 5 Gai -0.3 20e 100 d -0.4 -50 -25 0 25 50 75 100 n s Temperature [°C] e n Figure 16-19. Gain error vs. temperature for different PGA gains m g NORMALIZED TO 25°C i 100 m s B] 1 S 80 5 L e r [ 60 o 20 o 100 rr D E 40 et c s 20 eOff ut 0 w R utp -20 O e -40 N-50 -25 0 25 50 75 100 t Temperature [°C] o Figure 16-20. Offset error vs. temperature for different PGA gains N 16.8.6 Power Consumption Figure 16-21 plots the variation of quiescent current consumption with supply voltage V , as well as the DD distribution between the 3 PGA stages and the ADC (see Table 16-28). As shown in Figure 16-22, if lower sampling frequency is used, the quiescent current consumption can be lowered by reducing the bias currents of the PGAs and the ADC with registers IB_AMP_PGA [1:0] and IB_AMP_ADC [1:0]. (In Figure 16-22, IB_AMP_PGA/ADC[1:0] = '11', '10', '00' for f = 500, 250, 62.5kHz respectively.) S Quiescent current consumption vs. temperature is depicted in Figure 16-23, showing a relative increase of nearly 40% between -45 and +85°C. Figure 16-24 shows the variation of quiescent current consumption for different frequency settings of the internal RC oscillator. It can be seen that the quiescent current varies by about 20% between 100kHz and 2MHz. © Semtech 2006 www.semtech.com 16-28

XE8805/05A 800 700 A] µ PGA1, 2 & 3 + ADC urrent - I [Q 560000 PGA1 & 2 + ADC nt C 400 uiesce 300 PGA1 + ADC Q 200 No PGAs, ADC only r 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 o Supply Voltage - VDDA [V] f Figure 16-21. Quiescent current consumption vs. supply voltage d 800 Sampling Frequency fS: 500kHz e 700 A] µ d urrent - I [Q 560000 250nkHz s uiescent C 340000 e n Q 200 m 62.5kHz g 100 i 2.5 3.0m 3.5 4.0 4.5 s5.0 5.5 Supply Voltage - VDDA [V] e Figure 16-22. Quiescent current consumption vs. supply voltage for different sampling frequencies o D 900 c 20 e 850 ng 15 A] e wha Quiescent Current - I [µQ 566778505050000000 N ot R N e Relative Quiescent Current CI / I [%] QQ,25°C ---2111-0505005 500 -25 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature [°C] Temperature [°C] (a) (b) Figure 16-23. (a) Absolute and (b) relative change inquiescent current consumption vs. temperature © Semtech 2006 www.semtech.com 16-29

XE8805/05A Supply ADC PGA1 PGA2 PGA3 TOTAL Unit VDD = 5V 250 165 130 175 720 µA VDD = 3V 190 150 120 160 620 µA Table 16-28. Typical quiescent current distributions in acquisition chain (n = 16 bits, f = 500kHz) S e 15 850 r g han 10 A] 800 o C µ ative Quiescent Current / I [%] I∆QQ,2MHz --11-55005 Quiescent Current - I [Q 566775050500000 e d f el d R -20 500 0 500 1000 1500 2000 2500 3000 3500 0 500 n1000 1500 2000 2500s3000 3500 Frequency - fRC [kHz] Frequency - fRC [kHz] e n (a) (b) m g Figure 16-24. (a) Absolute and (b) relative change in quiescent curent consumption vs. RC oscillator frequency (all PGAs active, V = 5V) iDD m s e 16.8.7 Power Supply Rejection Ratio o D Figure 16-25 shows power supply rejecction ratio (PSRR) at 3V and 5V supply voltage, and for various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the change in the converter output (in V). PSRR depends on both PGA gaine and supply voltage V . w DD R 105 VDeD=3V 100 VDD=5V 95N t o B] 90 R [d 85 R 80 N S P 75 70 65 60 1 5 10 20 100 PGA Gain [V/V] Figure 16-25. Power supply rejection ratio (PSRR) © Semtech 2006 www.semtech.com 16-30

XE8805/05A Supply GAIN = 1 GAIN =5 GAIN = 10 GAIN = 20 GAIN =100 Unit V = 5V 79 78 100 99 97 dB DD V = 3V 72 79 90 90 86 dB DD Table 16-29. PSRR (n = 16 bits, V = V = 2.5V, f = 500kHz) IN REF S 16.9 Application Hints r o 16.9.1 Input Impedance f The PGAs of the acquisition chain employ switched-capacitor techniques. For this reason, while a conversion is done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency d f and to stage gain as given in equation 22. S e 768⋅109ΩHz Z ≥ (Eq. 22) d in f ⋅gain s The input impedance observed is the input impedance of the nfirst PGA stage tshat is enabled or the input impedance of the ADC if all three stages are disabled. e n PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input m g impedance of 150kΩ at f = 512kHz (see Specification Table). Larger input impedance can be obtained by S reducing the gain and/or by reducing the sampling frequency. Therefor, with a gain of 1 and a sampling frequency i of 100kHz, Zin > 7.6MΩ. m s The input impedance on channels that are not selected is very higeh (>100MΩ). o D c 16.9.2 PGA Settling or Input Channel Modifications e PGAs are reset after each writing operation to registwers RegAcCfg1-5. Similarly, input channels are switched after modifications of AMUX[4:0]R or VMUX. To ensure precise conversion, the ADC must be started after a PGA or inputs common-mode stabilization delay. Theis is done by writing bit START several cycles after PGA settings modification or channel switching. Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (btetween 8 and 1024)N number of cycles. This delay does not apply to conversions made without the PGAs. o If the ADC isN not settled within the specified period, there is most probably an input impedance problem (see previous section). 16.9.3 PGA Gain & Offset, Linearity and Noise Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC™: 1) Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but degrades noise performance. 2) Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset. Bypass unnecessary PGAs. 3) For high gains (>50), use PGA stage 1. For low gains (<50) use stages 2 and 3. 4) For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For example, in an application where a gain of 20 is needed, set the gain of PGA2 to 10, set the gain of PGA3 to 2. © Semtech 2006 www.semtech.com 16-31

XE8805/05A 4) For highest linearity and lowest noise performance, bypass all PGAs and use the ADC alone (applications where no "zooming" is needed); i.e. set ENABLE[3:0] = '0001'. 5) For low-noise applications where power consumption is not a primary concern, maintain the largest bias currents in the PGAs and in the ADC; i.e. set IB_AMP_PGA[1:0] = IB_AMP_ADC[1:0] = '11'. 6) For lowest output offset error at the output of the ADC, bypass PGA2 and PGA3. Indeed, PGA2 and PGA3 typically introduce an offset of about 5 to 10 LSB (16 bit) at their output. Note, however, that the ADC output offset is easily calibrated out by software. 16.9.4 Frequency Response r The incremental ADC is an over-sampled converter with two main blocks: an analog moodulator and a low-pass digital filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator. f As shown in Figure 16-26, this filter determines the frequency response of the transfer function between the output of the ADC and the analog input V . Notice that the frequency axes are normalized to one elementary conversion IN d period OSR/f . The plots of Figure 16-26 also show that the frequency response changes with the number of S elementary conversions N performed. In particular, notches appear for N ≥ 2. These notches occur at: ELCONV eELCONV f (i)= i⋅ fS (Hz) for i=1,2,...,(N −1)d (Eq. 23) NOTCH OSR⋅N ELCONV ELCONV n s and are repeated every f /OSR. S e n Information on the location of these notches is particularlym useful when specgific frequencies must be filtered out by the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection is needed. Using the above equation and the plots below, we set the 4th notch for N = 4 to 50Hz, i.e. i ELCONV 1.25⋅fS/OSR = 50Hz. The sampling frequency is thmen calculated as fsS = 20.48kHz for OSR = 512. Notice that this choice yields also good attenuation of 50Hz harmonics. e o Magnitude [-] 001...6821 eNELCcONV = 1 w Magnitude [-] 001...1682 D NELCONV = 2 d d alize 0.4 R alize 0.4 m 0.2 e m 0.2 or or N 0 N 0 0 1 t 2 3 N 4 0 1 2 3 4 Normoalized Frequency - f *(OSR/fS) [-] Normalized Frequency - f *(OSR/fS) [-] N ude [-] 1.12 NELCONV = 4 ude [-] 1.12 NELCONV = 8 nit 0.8 nit 0.8 g g a a M 0.6 M 0.6 d d alize 0.4 alize 0.4 m 0.2 m 0.2 or or N 0 N 0 0 1 2 3 4 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-] Normalized Frequency - f *(OSR/fS) [-] Figure 16-26. Frequency response: normalized magnitude vs. frequency for different N ELCONV © Semtech 2006 www.semtech.com 16-32

XE8805/05A 16.9.5 Power Reduction The ZoominADC™ is particularly well suited for low-power applications. When very low power consumption is of primary concern, such as in battery operated systems, several parameters can be used to reduce power consumption as follows: 1) Operate the acquisition chain with a reduced supply voltage V . DD 2) Disable the PGAs which are not used during analog-to-digital conversion with ENABLE[3:0]. 3) Disable all PGAs and the ADC when the system is idle and no conversion is performed. 4) Use lower bias currents in the PGAs and the ADC using the control words IB_AM P_PGA[1:0] and r IB_AMP_ADC[1:0]. (This reduces the maximum sampling frequency according to Table 16-26.) 5) Reduce internal RC oscillator frequency and/or sampling frequency. o f Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed. d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 16-33

XE8805/05A 17. Vmult (Voltage Multiplier) 17.1 Features r 17-2 o 17.2 Overview 17-2 f 17.3 Control register 17-2 d 17.4 External component 17-2 e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 17-1

XE8805/05A 17.1 Features • Generates a voltage that is higher or equal to the supply voltage. • Can be easily enabled or disabled 17.2 Overview The Vmult block generates a voltage (called “Vmult”) that is higher or equal to the supply vo ltage. This output voltage is used in the acquisition chain. r o The voltage multiplier should be on (bit ENABLE in RegVmultCfg0) when using the acquisition chain or analog properties of the Port B while VBAT is below 3V. If the multiplier is enabled, the efxternal capacitor on the pin VMULT is mandatory. d The source clock of Vmult is selected by FIN[1:0] in RegVmultCfg0. It is strongly recommended to use the same settings as in the ADC. e d 17.3 Control register n s There is only one register in the Vmult. Table 177-1 describes the bits in the register. e n Pos. RegVmultCfg0 rw Reset Functimon g 2 Enable rw 0 enable of the vmult resetsystem ‘1’ : enabled i m s ‘0’ : disabled 1-0 Fin rw 0 system clock division factor e resetsysotem ‘00’ : 1/2, ‘01’ : 1/4, D c ‘10’ : 1/16, ‘11’ : 1/64 e w Table 177-1. RegVmultCfg0 R e 17.4 External component N t When the multiplieor is enabled, a capacitor has to be connected to the VMULT pin. If the multiplier is disabled, the pin may remain floating. N Min. Max. Note Capacitor on VMULT 1.0 3.0 nF © Semtech 2006 www.semtech.com 17-2

XE8805/05A 18. Signal D/A (DAS) 18.1 Features r 18-2 o 18.2 Overview of Signal DAC - The generic DAC 18-2 f 18.3 Registers Map 18-3 d 18.4 The D/A description 18-4 e 18.4.1 What is a noise shaper ? 18-4 18.4.2 Advantages/disadvantages 18-4 d 18.4.3 D/A setup and resolution 18-5 n s 18.5 Amplifier 18-7 e n 18.6 Low pass filter 18-8 18.6.1 First order low pass filter m g 18-8 18.6.2 Second order low pass filter 18-9 i 18.7 4-20mA loop m s 18-10 18.7.1 2-wire loop with first order filtering 18-10 e 18.7.2 2-wire loop with second order filteoring 18-12 D c e w R e N t o N © Semtech 2006 www.semtech.com 18-1

XE8805/05A 18.1 Features • 16-bits maximum input word width • Synchronization mechanism to guarantee data integrity when writing LSB and MSB 8-bits data • Programmable noise shaper order: second, first or order zero • Programmable PWM modulation between 4 and 11-bits • Programmable clock input frequency: fin or fin/2 • Programmable output polarity: active high or low • On chip amplifier for analog filtering, voltage output or 4-20 mA loop r o 18.2 Overview of Signal DAC - The generic DAC f The generic DAC block consists of two major parts: the noise shaper (sigma-d elta modulator) and the PWM d modulator as shown in Figure 18-1. e d control Sigma-delta PWM modulator modulantor DAS Osut 16 CPU 4-11 bus m e n m g amp i m s e Figure 18-1. General block diagram o D A D/A converter that is built with a cdigital PWM modulator needs a high clock frequency for a small signal bandwidth. For a 10 bit digital PWM modulator for ins tance, a 10 bit counter is needed in order to create a pulse e with a resolution of 1024. This means that, in cawse an infinitely sharp analog output filter is used, the clock frequency has to be at least 1024 times the output bandwidth. In practice however, in order to be able to build the R analog filter, the clock frequency needs to be much higher. e In order to reduce this frequency requireNment, the input digital word is broken down into n words with a smaller t width m by a noise shaper so that the “average” (average for first order noise shaper, more complicated for higher o order noise shapers) value of the n m-bit words represents the full width input code. Instead of 1 pulse with the full resolution, the PWM modulator now generates n pulses with a smaller resolution m. This increases the output N pulse repetition frequency with a factor n for identical clock frequency. Therefore, the analog output filtering is easier to implement. Higher order noise shapers (order >1) allow to decrease the clock frequency for identical signal bandwidth. Another advantage is that the signal distortion is less dependent on the signal value. A disadvantage is however, that the output signal after filtering is more dependent on the rise and fall times of the PWM output since there are many more pulses. The maximum word width at the input is 16-bit. If the word is narrower, 0’s have to be added after the LSB. In order to maintain maximum flexibility, the order of the noise shaper and the resolution of the PWM modulation are programmable by writing the codes CodeLmax and NsOrder to the configuration register. The possible noise shaper order is 0 (which means no noise shaping), 1 or 2. The possible PWM modulation resolution m can be set between 4 and 11. © Semtech 2006 www.semtech.com 18-2

XE8805/05A 18.3 Registers Map All registers are reset with the system reset. The contents of the registers RegDasInLsb and RegDasInMsb are transferred to the D/A converter when after data have been written into RegDasInMsb. Therefore, in order to maintain the synchronisation between the LSB and MSB, the LSB should always be written before the MSB. Pos. RegDasInLsb rw reset function r 7-0 DasInLsb(7:0) rw 0 Data to convert LSB o resetsystem f Table 18-1. RegDasInLsb d Pos. RegDasInMsb rw reset function 7-0 DasInMsb(7:0) rw 0 Data to convert MSeB resetsystem d Table 18-2. RegDasInMsb n s e n Pos. RegDasCfg0 rw reset function 7:6 NsOrder(1:0) rw 00 Nmoise Shaper orderg resetsystem 00 : order 0 01 : order 1 i m 1x : order 2 s 5:3 CodeLmax(2:0) rw 000 PWM pulse resolution : e resetsystem 000 : 4 bits o 001D : 5 bits c 010 : 6 bits 011 : 7 bits e 100 : 8 bits w 101 : 9 bits R 110 : 10 bits e 111 : 11 bits 2:1 Enable(1:0) rw 00 Bit 0 : enables the D/A N t resetsystem Bit 1 : enables the amplifier 0 Fin o rw 0 Input frequency of modulator as a fraction of resetsystem oscillator frequency N 0 : 1.f , 1 : ½.f RC RC Table 18-3. RegDasCfg0 Pos. RegDasCfg1 rw reset function 7:2 - rw 000000 Unused 1 BW rw 0 Amplifier bandwidth resetsystem 0 : small bandwidth 1 : large bandwidth 0 INV rw 0 Inverts the PWM output resetsystem 0 : normal, active high 1 : inverted, active low Table 18-4. RegDasCfg1 © Semtech 2006 www.semtech.com 18-3

XE8805/05A 18.4 The D/A description The D/A converter consists of 2 parts: a classic PWM modulator which is preceded by a noise shaper (Figure 18-1). The PWM signal has then to be low pass filtered using the amplifier and external components to obtain the analog signal. 18.4.1 What is a noise shaper? The major disadvantage of using a PWM modulator to generate a high resolution analog signal is that it requires a high ratio between the PWM switching frequency and the useful bandwidth of the output analog signal after low r pass filtering. o Example: assuming the switching frequency of the PWM modulator is 1MHz and one wants to resolve 16 bit, i.e. f 216=65536 steps. In this case, the PWM has to code each step in increments of 1µs=1/1MHz and needs therefore 65536µs per pulse. This means that the PWM pulse repetition rate is 1/65536µs=15.25Hz. So, even with a higher d order low pass filter, more than 1 frequency decade will be required to filter the PWM signal down to a 16 bit accurate analog signal. This leaves a useful bandwidth below 1Hz. e The goal of the noise shaper is to reduce the ratio between the PdWM switching frequency and the useful bandwidth. The noise shaper will not reduce the “truncation noise” and “PWM modulation noise” but move it to higher frequencies. It “shapes” the frequency spectrum (“noise”) ofn the generated PWsM signal, hence its name. In practice, the noise shaper allows the generation of a signal with a given resolution using a PWM modulator that has a lower resolution. The noise shaper then generates a seeries of different subnsequent low resolution codes for the PWM so that the average value corresponds to the high resolution code. m g The first order noise shaper interpolates between two adjacent PWM codes to obtain a higher resolution. The i second order noise shaper can use non-adjacent PWM codes. m s Example for first order noise shaper: assuming again the resoelution of 16 bits using a 1MHz PWM switching frequency using the noise shaper with ordoer 1. If a PWM modulator with 4 bits, i.e. 16 steps is used, the PWM repetition frequency becomes then 1MHz/16=62.5kHz. TheD PWM modulator can convert only the 4 MSB’s of the 16 bit input such as h0000, h1000 unctil hF000. In order to convert the code h5800, which is between h5000 and h6000? In this case, the first order noise shaper will i nterpolate by presenting alternatively the code h5 and h6 to the PWM so that after filtering a esignal is obtained whalfway between the normal PWM steps. To convert the code h5400, it will present h5 3 times and h6 once to the PWM and so on. It is clear from this that the PWM repetition R frequency is much higher than for the simple PWM and can be filtered out more easily. The quantization noise e frequency will depend on the code to be converted: for this example for instance we need two PWM pulses to implement the code h58 00, but we need four to implement h5400 etc. N t o Example for second order noise shaper: if we use the same conditions as for the example above, we will obtain the same PWM repetition frequency. However, to implement the code h5400, the noise shaper now can present the N following sequence to the PWM modulator: h6, h5, h6, h4. This increases the frequency components at the PWM pulse repetition frequency and ½ of the PWM pulse repetition frequency but at the same time reduces energy at ¼ of the PWM pulse repetition frequency with respect to the first order noise shaper. The low pass cut-off frequency can therefore be higher than for a first order noise shaper. A disadvantage of the second order noise shaper is however that the resolution will drop when the code is very close to h0000 or hFFFF. Example: if we assume the same conditions as above, but we want to convert the code h0400. It is now impossible to use a similar sequence as above (which would be h1, h0, h1, h(-1) ) due to saturation of the code. There is no choice left but the sequence h1 h0 h0 h0 which is the same sequence as in the first order noise shaper. 18.4.2 Advantages/disadvantages Advantages: Using a high order noise shaper together with a PWM modulator with low resolution reduces the ratio between the low pass cut off frequency and the PWM switching frequency for the same total resolution. This can be used to © Semtech 2006 www.semtech.com 18-4

XE8805/05A increase the output signal bandwidth or to reduce the PWM switching frequency and therefore the power consumption of the D/A. Signal distortion is less dependent on the signal value. Disadvantages: Using a high order noise shaper together with a PWM modulator with low resolution will use lots of short pulses in stead of 1 long pulse. The D/A is therefore more sensitive to rise and fall times of the PWM resulting in a slightly higher non-linearity and temperature dependence. The second order noise shaper also has a reduced resolution for codes very close to zero or full scale. r 18.4.3 D/A setup and resolution o In this section, the resolution that can be obtained with the D/A as a function of settings is calculated. These f calculations are based on the quantization and PWM modulation noise. Noise on the reference, i.e. the supply voltage is not taken into account. High frequency noise on the supply voltage can be filtered by the output low pass d filter, but in band noise on the reference will show up in the output signal with amplitude that will depend on the signal value. Therefore, when using the D/A, one should take care to minimize the switching activity on the digital e ports and/or to limit the load on these ports. d 18.4.3.1 Noise shaper of order 0 n s Setting the noise shaper to order 0 (NsOrder=00), reduces the D/A to a regular PWM. Two parameters are setting the resolution of the D/A: the resolution of the modulator itself eand the amount of lonw pass filtering at the output. The modulation width m of the PWM modulator is given bmy: g i m=4+CodeLmax m s The cut-off frequency f of the low pass filter required to geet the resolution is calculated below. The PWM c o modulator repetition frequency f can be calculated asD a function of the selected modulation width m, the PWM c frequency of the RC oscillator of the circuit f and the selected frequency division set by Fin : RC e w ⎛ 1 ⎞ f ⋅⎜ R ⎟ RC ⎝1+Fin⎠ e f = PWM 2m N t o To obtain an analog signal with the required solution, the PWM signal has to be low pass filtered. The resolution that can be oNbtained depends on the filter order and the ratio between the PWM modulation frequency fPWM and the filter cut-off frequency f . For a low pass filter of LpOrder, we obtain: c ⎛ f ⎞ resolution = LpOrder⋅log ⎜ PWM ⎟ PWM 2⎜ f ⎟ ⎝ ⎠ c The total resolution of the D/A is then the minimal value of both criteria: resolution =min(m,resolution ) PWM In Table 18-5 the required cut-off frequency of the low pass filter is shown for a noise shaper of order 0 as a function of the desired resolution for both a first and second order low pass filter. The PWM modulation factor m should be chosen equal to the desired resolution. © Semtech 2006 www.semtech.com 18-5

XE8805/05A resolution (bit) m f for LpOrder=1 (Hz) f for LpOrder=2 (Hz) c c 4 4 7812 31250 5 5 1953 11048 6 6 488 3906 7 7 122 1381 8 8 30 488 9 9 7.6 172 10 10 1.9 61 11 11 0.48 22 r Table 18-5. Signal bandwidth as a function of the required resolution for the PWM without noise shaper (Fin=0, NsOrder=00, f =2MHz). o RC f 18.4.3.2 Noise shaper of order 1 or 2 d The calculation on the required low pass cut-off frequency given in 18.4.3.1 remains valid in this case. However, the noise shaper allows using smaller PWM modulation for the same eresolution. This increases the PWM modulation frequency and as a consequence increases the output bandwidth. d An additional criterion however shows up: the filtering of the quantization noise. As can be seen from the examples in 18.4.1, the interpolation between PWM codes generated bny the noise shapser introduce sequences at frequencies below the PWM modulation frequency. Assuming a low pass filter that has at least the same order as e n the noise shaper, the resolution is given by (NsOrder≥1) : m g ⎛ f ⎞ resolution =0.359+m+NsOrder⋅⎜log ( PWM )−2.65⎟ quant m⎜⎝ 2 fc si⎟⎠ e The total resolution of the D/A is then the minimal of both criteria: o D resolution =min(resolutioncquant,resolutionPWM) e Table 18-6 and Table 18-7 show the signal bandwidwth that can be obtained as a function of required resolution and PWM modulation for first and second order noise shapers. It can be seen that these options are useful to obtain R high resolution using low PWM modulation m. For high PWM modulation m, the resolution is limited by the PWM e modulator and adding a noise shaper does not change anything. N t NsOrder=1, f =2MHz, Fin=0, LpOrder=2 RC o Resolution PWM modulation m (bit) N 4 5 6 7 8 9 10 11 8 1596.4 1596.4 1596.4 976.6 488.3 244.1 122.1 61.0 9 798.2 798.2 798.2 690.5 345.3 172.6 86.3 43.2 10 399.1 399.1 399.1 399.1 244.1 122.1 61.0 30.5 11 199.5 199.5 199.5 199.5 172.6 86.3 43.2 21.6 12 99.8 99.8 99.8 99.8 99.8 61.0 30.5 15.3 13 49.9 49.9 49.9 49.9 49.9 43.2 21.6 10.8 14 24.9 24.9 24.9 24.9 24.9 24.9 15.3 7.6 15 12.5 12.5 12.5 12.5 12.5 12.5 10.8 5.4 16 6.2 6.2 6.2 6.2 6.2 6.2 6.2 3.8 Table 18-6. Low pass cut-off frequency as a function of the selected PMW modulation and required resolution for a first order noise shaper. © Semtech 2006 www.semtech.com 18-6

XE8805/05A NsOrder=2, f =2MHz, Fin=0, LpOrder=2 RC Resolution PWM modulation m (bit) 4 5 6 7 8 9 10 11 8 5638.4 3906.3 1953.1 976.6 488.3 244.1 122.1 61.0 9 3986.9 2762.1 1381.1 690.5 345.3 172.6 86.3 43.2 10 2819.2 1953.1 976.6 488.3 244.1 122.1 61.0 30.5 11 1993.5 1381.1 690.5 345.3 172.6 86.3 43.2 21.6 12 1409.6 976.6 488.3 244.1 122.1 61.0 30.5 15.3 13 996.7 690.5 345.3 172.6 86.3 43.2 21.6 10.8 r 14 704.8 488.3 244.1 122.1 61.0 30.5 15.3 7.6 15 498.4 345.3 172.6 86.3 43.2 21.6 o10.8 5.4 16 352.4 244.1 122.1 61.0 30.5 15.3 7.6 3.8 f Table 18-7. Low pass cut-off frequency as a function of the selected MPW modulatio n and required resolution for a second order noise shaper. d e The output range of the D/A is for code 0h0000 is VSS and for code 0hFFFF is (VBAT-VSS)(2m-1)/2m. d 18.5 Amplifier n s The amplifier can be used to implement the low pass filter and/or a 4-20mA loop. The amplifier is enabled using the e n bit Enable(1)=1. The amplifier has two different modes selected by the bit BW: a low frequency mode (BW=0) that allows driving a high capacitive load and a high frequency mode (BW=1). m g The first mode is particularly adapted when a voltage output is used. The second mode is more adapted for a 4- i 20mA loop since loads are small and higher banmdwidth is required sto reject current consumption changes in the loop. e Table 18-8 shows the specification of the aomplifier. D Note that the amplifier can not be usecd to generate signals that are larger than the supply voltages VBAT and VSS since the amplifier inputs and outputs are clamped to these voltages. The amplifier inputs and outputs should stay e within the input and output ranges specified below. w R e N t o N © Semtech 2006 www.semtech.com 18-7

XE8805/05A sym description min typ max unit Comment gain gain at DC 80 100 dB 1 GBW gain bandwidth product 25 70 kHz 6 0 C capacitive load 5 nF 6 L0 GBW gain bandwidth product 250 450 kHz 7 1 C capacitive load 200 pF 7 L1 φ phase margin 55 65 ° 8 m RL resistive load 5 kΩ 5 SR slew rate 10 30 kV/s 9r CMR common mode input range VSS-0.2 VBAT-1.2 V o2 OR output range VSS+0.2 VBAT-0.2 V V offset ±5 mV f off CMRR common mode rejection 60 dB 3 d noise integrated input noise 50 100 uVrms PSRR power supply rejection 20 60 dB 4 e ratio I quiescent bias current 150 d uA quie I off current 1 uA off n s 1. For the minimal resistive load and the maximal capacitive load 2. The amplifier common mode is VSS in the 4-20mA loop. e n 3. At DC 4. At DC. Only a low rejection ratio is needed since the D/A outmput refers directly to theg power supplies. 5. Short circuit protection at >3mA. 6. GBW when the maximal load is cl0 and with the bit BW=0 i 7. GBW when the maximal load is cl1 and with the bit BW=1 8. In both cases BW=0 and BW=1 for the maximal campacitive load and the minsimal resistive load. 9. For maximal load C , BW=0 and maximal resistive load R L0 L e Table o18-8. Specification of the amplifier. D c 18.6 Low pass filter e w Several low pass filters are pRroposed here as examples. Other filter types are possible depending on the features or constraints of the application. e N If the filter is invertingt the signal, the bit INV can be used to invert the D/A output. This inversion does not need to be done by calculaotion. A first or secoNnd order low pas filter can be built with the amplifier. If higher order filters are needed, additional first or second order sections can be added using external amplifiers. 18.6.1 First order low pass filter Figure 18-2 shows a possible implementation of a first order low pass filter. Ideally, the analog ground should be halfway between VBAT and VSS. The gain G and cut-off frequency f of such a filter are given by: c R G = 2 R 1 1 f = c 2πR C 2 As an example, to obtain a 1kHz filter with unity gain, we can choose C=1nF and R1=R2=150kΩ. © Semtech 2006 www.semtech.com 18-8

XE8805/05A XE88xx c D o DAS_OUT n t A r R1 o r l o DAS_AI_M f C d R 2 amp e DAS_AO d n analog grounds DAS_AI_P e n m g Figure 18-2. First order low pass filter. i m s 18.6.2 Second order low pass filter e o D c Figure 18-3 shows an example of a second order low pass filter using the multi-feedback architecture. The gain G, cut-off frequency f and the damping factor ξ (or quali ty factor Q) as a function of the factors k and m (see Figure c e 18-3) are given by: w R G =−k e 1 (n+1) km N ξ= = t 2Q o 2 n 1 f =N c 2πRC kmn For a second order Butterworth filter, ξ= 2 2. For smaller damping factors, the filter is under damped resulting in overshoots on the step response. For higher damping factors, the filter is over damped resulting in a smooth but slower step response. An example of a 1dB ripple Chebychev filter with a cut-off frequency of about 1.5kHz and a DC gain of 1 is given by choosing m=0.22, k=1, n=0.5, R=330kΩ and C=1nF. The resistor nR can be rounded to 180kΩ. A 60Hz unity gain low pass Butterworth filter can be built choosing R=180kΩ, C=12nF, k=1, m=0.183, n=8.33. Note that parasitic capacitors between the DAS_OUT node and the filter output DAS_AO will adversely affect the high frequency behavior of the filter. Care should be taken when routing these signals. © Semtech 2006 www.semtech.com 18-9

XE8805/05A XE88xx c D o DAS_OUT n t A r R C o l r o nR f DAS_AI_M d e mC kR DAS_AO d amp n s DAS_AI_P e analog grounnd m g i m s Figure 18-3. Second order low pass filter. e o D 18.7 4-20mA loop c e w 18.7.1 2-wire loop with Rfirst order filtering e The amplifier can be used to build a 4-20mA loop externally. Figure 18-4 shows the principle of such a 2-wire loop using a first order low pass filter. N t o In a 2-wire loop, the current consumption of the sensor and read-out electronics is drawn on the same wires as the signal current. The current consumption of the sensor and read-out electronics should therefore remain below N 4mA. The signal current is then added by the bipolar transistor. The resistors R and R are added to protect lim1 lim2 the bipolar transistor against high transient currents during power-up. R is generally set to a few kΩ. The value lim1 of R is chosen as a function of the external loop voltage V and the transistor saturation voltage V . lim2 EXT CEsat R =(V −V −R ⋅20mA) 20mA lim2 EXT CEsat sense If V is larger than 5.5V, a voltage regulator has to be inserted. Since the quiescent current of the regulator adds EXT up to the 4mA budget, a component with sufficiently low quiescent current has to be selected. The resistor R measures the total current in the loop (if R <<R ). The resistors R and R are used to set sense sense f2 f1 f2 the gain and R and C to set the bandwidth of the filter. The resistor R adds an offset to the filter voltage so f2 f offset that the code 0 of the D/A corresponds to 4mA. The amplifier will force a current through the bipolar transistor so that the voltage on the filter V and VSS on R is equal. This transforms the filter voltage into a loop current f sense I =(VSS-V -)/R . loop EXT sense © Semtech 2006 www.semtech.com 18-10

XE8805/05A The resistor value R is generally chosen between 50Ω and 150Ω resulting in a 1V to 3V voltage drop at sense maximal loop current. The resistor R is then chosen much larger depending on the current error requirement. f2 Allowing for an error of 0.1% gives R =R /0.001. f2 sense The resistor R may be omitted but it will reduce the useful code range of the D/A. offset Using the large bandwidth of the amplifier is recommended since this increases the rejection of supply current variations of the other components in the loop. A bypass capacitor between VBAT and VSS will also reduce the high frequency current variations. Values will depend on the voltage regulator used. The software in the XE8805 should keep the current supply of the circuit as stable as possible. This means that the clock frequency should kept constant, peripherals should not be switched on and off, the current in the sensor is kept const ant, the processor r should not use the halt or sleep modes, etc. o f 4-20mA VBAT Volt age redgulator V + EXT XE88xx VBAT e c D d o DAS_OUT Roffset n n s t A r e R n Rlim2 o f1 l m g DAS_AI_P i m sVf R DAS_AO lim1 amp e Sensor o D c DAS_AI_M VSS e w VSS R e N t Cf Rf2 Rsense o V - EXT N 4-20mA Figure 18-4. 2-wire 4-20mA loop with first order filter The resistor R can then be calculated to set the full scale D/A code range (depends on the PWM modulation m, f1 see section 18.4.3.2) equal to the full scale signal current of 16mA: (VBAT −VSS)⋅(2m −1)⋅R R ≤ f2 f1 2m ⋅R ⋅16mA sense The resistor R can be calculated in order to obtain a 4mA current while the D/A code is 0: offset (VBAT −VSS)⋅R R ≤ f2 offset R ⋅4mA sense © Semtech 2006 www.semtech.com 18-11

XE8805/05A The capacitor C can be calculated from the first order filter cut-off frequency f : f c R +R C = f1 f2 f 2πf R R c f1 f2 As an example, for VBAT-VSS=5V, m=4, R =50Ω, V =30V and a 1kHz low pass filter, we can use: sense EXT R =1kΩ, R =1kΩ, R =560kΩ, R =100kΩ, R =2.4MΩ, C=1.8nF. lim1 lim2 f1 f2 offset f r o 18.7.2 2-wire loop with second order filtering f A second order filter function can be implemented by replacing the resistor R in Figure 18-4 by another first order f1 filter section as shown in Figure 18-5. The value of R +R has to be chosen the same way as R in the first order f1a f2a d f1 schematic. e VBAT Voltage 4-20mA d regulator V + EXT XE88xx VBAT n s R offset c D e n o DAS_OUT Rf1a Rf1b n m g t A r Cf1 Rlim2 o i l m s DAS_AI_P Vf e o DAS_AO D Rlim1 camp Sensor e w DAS_AI_M R VSS e VSS N t o Cf2 Rsense N R V - f2 EXT 4-20mA Figure 18-5. 2-wire 4-20mA loop with second order filtering. Another possibility is shown in Figure 18-6. The advantage this solution is that it is easier to stabilize depending on the component parasitics and board layout. But since it limits the bandwidth of the current regulation loop, it reduces the rejection of the supply current variations. For this schematic, all the equations of the first order schematic remain valid. The values of R and C can be fs fs calculated from the cut-off frequency: 1 R C = fs fs 2πf c For the 1kHz example, we can chose R =150kΩ and C =1nF (set BW=0 in this case). fs fs © Semtech 2006 www.semtech.com 18-12

XE8805/05A VBAT Voltage 4-20mA regulator V + EXT XE88xx VBAT R offset c D o DAS_OUT Rf1 n t r A Rlim2 r o l o DAS_AI_P Vf f R DAS_AO lim1 d amp Sensor C fs e DAS_AI_M d VSS Rfs n VSS s e n m Cf g Rf2 Rsense V - EXT i m s 4-20mA Figure 18-6. 2-wire 4-20mA with second order filter and increasede stability o D c e w R e N t o N © Semtech 2006 www.semtech.com 18-13

XE8805/05A 19. Bias D/A (DAB) 19.1 Features 19-2 r 19.2 General description o 19-2 19.3 Register map f 19-2 19.4 D/A specification d 19-3 19.5 Amplifier specification e 19-3 d 19.6 Application examples 19-4 19.6.1 Voltage controlled sensor bias 19-4 n s 19.6.2 Current controlled sensor bias 19-4 e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 19-1

XE8805/05A 19.1 Features • 8 bit low frequency A/D • On-chip amplifier with 2 terminals MOS output • Current and voltage controlled applications can be implemented 19.2 General description r o XE8805A – Bias D/A block f DAB R P d DAB OUT e DAB AIP d V DAB AOP BATT n s D/A amp e MOS n control registers m g DabIn VSS i DAB AOM Enable m s DAB AIM e o DAB R M D c As the amplifier is attacking a MOS, effective polarity of the feedback loop depends on load and network. e w R Figure 19-1. General block diagram e Figure 19-1 shows the general block diagNram of the D/A peripheral. It consists of a control block that manages all t communication with the CPU and sets the configuration of the peripheral. The D/A converts the digital data in an o analog output signal. An amplifier is added that can be used to drive the large sensor currents. N 19.3 Register map The bias D/A has two registers. Pos. RegDabIn rw reset function 7-0 DabIn(7:0) rw 0 Data to convert resetsystem Table 19-1. RegDabIn Pos. RegDabCfg rw reset function 7-2 r 0 Unused 1-0 Enable(1:0) rw 00 bit 1: enables the amplifier when 1 resetsystem bit 0: enables the D/A when 1 Table 19-2. RegDabCfg © Semtech 2006 www.semtech.com 19-2

XE8805/05A 19.4 D/A specification The D/A generates a voltage on node DAB_OUT that is proportional to the code RegDabIn in between the positive reference voltage DAB_R_P and the negative reference voltage DAB_R_M. The voltage on DAB_R_P always has to be larger than the voltage on DAB_R_M. The DAB is intended for very low frequency use. The specification is given in Table 19-3. The DAB is based on a resistive ladder. Capacitors larger than 100pF are allowed on the node DAB_OUT, but the r step response will increase proportionally. o sym description min typ max unit note f wda number of input bits 8 bits tstep step response 0.25 1 dms 1 OR D/A output range DAB_R_M DAB_R_P refp DAB_R_P range VSS+2.3 VBATe V refn DAB_R_M range VSS VBAT-2.3 V d Rdab impedance between 1.6 Mohm DAB_R_P and DAB_R_M n s 1. Time to reach the final value within 5%, C on DAB_OUT smaller than 100pF. L e n Table 19-3. D/A specification. m g i 19.5 Amplifier specification m s e The amplifier output stage is a single transistor follower that is able to drive large currents. This transistor is not o connected internally so that different circuit configurations are possible (see next section). In order to guarantee D correct functionality, the voltage on the output pins has to respect the specifications VR and VR as indicated c AOP AOM in Table 19-4. e w sym description R min typ max unit Note gain gain at DC e60 90 dB 1 GBW gain bandwid th product 100 4500 Hz 1 N t φ phase margin 60 80 ° 1 m o R resistive load 300 100000 Ω L C capacitive load 1 nF L N CMR common mode input range VSS VBAT V VR DAB_AOM voltage range VSS+0.2 DAB_AOP-0.2 V 1 AOM VR DAB_AOP voltage range VSS+2.3 VBAT V 1 AOP V offset ±10 mV off noise integrated input noise 60 100 µVrm s I max source current 10 40 mA source PSRR power supply rejection ratio 80 dB 2 I quiescent bias current 5 10 µA bias I off current 0.1 1 µA off 1. For all possible combinations of resistive load and capacitive load. 2. At DC. Table 19-4. Amplifier specification. © Semtech 2006 www.semtech.com 19-3

XE8805/05A 19.6 Application examples 19.6.1 Voltage controlled sensor bias Figure 19-2 shows the basic connectivity to have a voltage controlled sensor bias. The D/A will generate a voltage between vrep and vrefn proportional to the input code. The amplifier will copy the D/A voltage to the sensor. The D/A code can be used to do a software temperature calibration of the sensor for instance. Filter capacitors can be added in parallel with the sensor reference and signal, on V , V and DAB_OUT. refp refn r o The voltages V and V can be filtered before being connected to the D/A reference inputs. The reference refp refn voltages can be connected directly to VBAT and VSS for simplicity. They can also be connected to VBAT and VSS f through a low pass filter that rejects the high frequency supply noise. Finally, in most cases, the voltage range of interest for the voltage V on the sensor is only a fraction of the supply voltage. By generating V and V sensor d refp refn equal to the limits of the voltage range of interest, the resolution of the D/A can be increased. Example: if a supply of 5V is used and the reference voltage is equal to the supply, the D/A can geenerate a sensor voltage between 0V and 5V in steps of about 5V/255≈20mV. If the sensor voltage is always to be between 3V and 4V, and by connecting V =3V and V =4V, the sensor voltage is adjustable dbetween 3V and 4V with steps of about refn refp 1V/255≈4mV. n s e n XE8805A – DAB block m g V refp VBAT or a Reference voltage source DAB_R_P V i D/A DmAB_R_M refn s VSS (cid:42) High impedance node, e impedance depends on D/A code o DAB_OUT DAB_AIP D c DAB_AOP VBAT (cid:42) Needs a 300 Ω – 100 kΩ load e (cid:42) Max capacitive load is 1 nF w amp V R sensor eDAB_AOM N DAB_AIM t reference input o of the ZoomingADC N (cid:42) In this configuration the bridge current and DAB_AOM increase when DAB_OUT increases. signal input of the ZoomingADC VSS Figure 19-2. Voltage controlled bridge bias principle. Note that the voltage on the sensor can not be higher than VBAT-0.2V in the example of Figure 19-2 (specification VR in Table 19-4). AOM 19.6.2 Current controlled sensor bias Figure 19-3 shows the principle of a current controlled sensor bias schematic. In this case, the amplifier forces the voltage V to be equal to the D/A output voltage V . The current I through the sensor is given by: R D/A sensor © Semtech 2006 www.semtech.com 19-4

XE8805/05A V −V V −V (V −V )⋅(1−code 255) I = refp R = refp D/A = refp refn sensor R R R sense sense sense The voltage V can be calculated as a function of the current I and the sensor impedance. sensor sensor Note that the voltage V >VSS+2.3V and V -V >0.2V (VR and VR specifications in Table 19-4) to R R sensor AOP AOM guarantee correct functionality of this schematic. r Choosing the V equal to the supply voltage or close to the supply voltage in order to have the highest possible refp voltage on the sensor is recommended. From the equation, it can be seen that the sensor courrent step per LSB can be made smaller by reducing the voltage between V and V or by increasing the sense resistor value. refp refn f As for the voltage controlled sensor bias, capacitors can be added on several nodes to filter out the noise. d XE8805A e (cid:42) Voltage must remain above VSS + 2.3 V DAB_R_P Vrefp d D DAB_R_M Vrefnn (cid:42)s Voltage must remain below VBAT - 2.3 V VSS e n DAB_OUT VD/A DABm_AIM gRsense A (cid:42) Voltage must remain above VSS + 2.3 V DAB_AOP i m s VR amp (cid:42) Needs a 300 Ω – 100 kΩ load e (cid:42) Max capacitive load is 1 nF o DAB_AOM V D sensor c DAB_AIP reference e w (cid:42) In this configurationR, the bridge current and DAB_AOM decrease when DAB_OeUT increases. N t signal o VSS N Figure 19-3. Current controlled bridge bias In Figure 19-4, the sense resistor is inserted between the negative reference voltage and the sensor. This schematic has the same principle as above, but it is easier to respect the limits on VR when VBAT is low. The AOP sensor current is now: V −V V −V (V −V )⋅(code 255) I = R refn = D/A refn = refp refn sensor R R R sense sense sense In this case, it is recommended to choose V equal to VSS or close to VSS in order to have the highest possible refn voltage on the sensor. The only limit is now V <VBAT-0.2V. sensor © Semtech 2006 www.semtech.com 19-5

XE8805/05A XE8805A D DAB_R_P Vrefp VBAT or another reference voltage DAB_R_M Vrefn (cid:42) Vrefp must remain above VSS + 2.3 V VSS DAB_OUT VD/A DAB_AIP A VBAT DAB_AOP r amp (cid:42) Needs a 300 Ωo – 100 kΩ kohm load Vsensor (cid:42) Max capacitive load is 1 nF DAB_AOM f DAB_AIM d reference input of ZoomingADC e (cid:42) In this configuration, the bridge current and DAB_AOM increase when DAB_OUT increases d signal input of ZoomingADC n s e VR n Rsense m gVSS i Figure 19-4. Current controlled sensor bias. m s . e o D c e w R e N t o N © Semtech 2006 www.semtech.com 19-6

XE8805/05A 20. Counters/Timers/PWM 20.1 Features r 20-2 o 20.2 Overview 20-2 f 20.3 Register map 20-2 d 20.4 Interrupts and events map 20-3 e 20.5 Block schematic d 20-4 20.6 General counter registers operation n s 20-4 20.7 Clock selection e n 20-5 20.8 Counter mode selection m g 20-5 20.9 Counter / Timer mode i 20-6 m s 20.10 PWM mode e 20-8 o 20.11 Capture function D 20-9 c e w R e N t o N © Semtech 2006 www.semtech.com 20-1

XE8805/05A 20.1 Features • 4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules • Each with 4 possible clock sources • Up/down counter modes • Interrupt and event generation • Capture function (internal or external source) • Rising, falling or both edge of capture signal • PA[3:0] can be used as clock inputs (debounced or direct) r • 2 x 8 bits PWM or 2 x 16 bits PWM o • PWM resolution of 8, 10, 12, 14 or 16 bits • Complex mode combinations are possible between counter, capture and PWMf modes d 20.2 Overview e CounterA and CounterB are 8-bit counters and can be combined to form a 16-bit counter. CounterC and CounterD exhibit the same features. d The counters can also be used to generate two PWM outputs on PBn[0] and PB[1]. In PsWM mode one can generate PWM functions with 8, 10, 12, 14 or 16 bit wide counters. e n The counters A and B can be captured by events on an internal or an external signal. The capture can be performed on both 8-bit counters running individually on tmwo different clock sgources or on both counters chained to form a 16-bit counter. In any case, the same capture signal is used for both counters. i m s When the counters A and B are not chained, they can be used in several configurations: A and B as counters, A and B as captured counters, A as PWM and B as counter, A as PWM and B as captured counter. e o When the counters C and D are not chained, they can be uDsed either both as counters or counter C as PWM and counter D as counter. c e 20.3 Register map w R e Bit RegCntA rw reset function 7-0 CtounterA r N xxxxxxxx 8-bits counter value 7-0 oCounterA w xxxxxxxx 8-bits comparison value Table 20-1. RegCntA N bit RegCntB rw reset function 7-0 CounterB r xxxxxxxx 8-bits counter value 7-0 CounterB w xxxxxxxx 8-bits comparison value Table 20-2. RegCntB Note: When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading these locations, the processor reads back either the actual counter value or the last captured value if the capture mode is active. bit RegCntC rw reset function 7-0 CounterC r xxxxxxxx 8-bits counter value 7-0 CounterC w xxxxxxxx 8-bits comparison value Table 20-3. RegCntC © Semtech 2006 www.semtech.com 20-2

XE8805/05A bit RegCntD rw reset function 7-0 CounterD r xxxxxxxx 8-bits counter value 7-0 CounterD w xxxxxxxx 8-bits comparison value Table 20-4. RegCntD Note: When writing RegCntC or RegCntD, the processor writes the counter comparison values. When reading these locations, the processor reads back the actual counter value. bit RegCntCtrlCk rw reset funcrtion 7-6 CntDCkSel(1:0) rw xx Counter d clock selection o 5-4 CntCCkSel(1:0) rw xx Counter c clock selection 3-2 CntBCkSel(1:0) rw xx Counfter b clock selection 1-0 CntACkSel(1:0) rw xx Co unter a clock selection d Table 20-5. RegCntCtrlCk e bit RegCntConfig1 rw Reset function d 7 CntDDownUp rw x Counter d up or down counting (0=down) 6 CntCDownUp rw x Conunter c up or downs counting (0=down) 5 CntBDownUp rw x Counter b up or down counting (0=down) 4 CntADownUp rw x eCounter a up or ndown counting (0=down) 3 CascadeCD rw x Cascade counter c & d (1=cascade) m g 2 CascadeAB rw x Cascade counter a & b (1=cascade) 1 CntPWM1 rw 0 resetsystem Activate pwm1 on counter c or c+d (PB(1)) i 0 CntPWM0 rw 0 resmetsystem Activaste pwm0 on counter a or a+b (PB(0)) Table 20-6. RegCntConfig1 e o D bit RegCntConfig2 rw Reset function c 7-6 CapSel(1:0) rw 00 resetsystem Capture source selection 5-4 CapFunc(1:0) e rw 00 resetsystem Capture function w 3-2 Pwm1Size(1:0) rw xx Pwm1 size selection 1-0 Pwm0Size(1R:0) rw xx Pwm0 size selection e Table 20-7. RegCntConfig2 N t bit oRegCntOn rw Reset Function 7-4 -- r 0000 Reserved N 3 CntDEnable rw 0 resetsystem Enable counter d 2 CntCEnable rw 0 resetsystem Enable counter c 1 CntBEnable rw 0 resetsystem Enable counter b 0 CntAEnable rw 0 resetsystem Enable counter a Table 20-8. RegCntOn 20.4 Interrupts and events map Interrupt source Mapping in the Mapping in the event interrupt manager manager IrqA RegIrqHigh(4) RegEvn(7) IrqB RegIrqLow(5) RegEvn(3) IrqC RegIrqHigh(3) RegEvn(6) IrqD RegIrqLow(4) RegEvn(2) Table 20-9. Interrupt and event mapping. © Semtech 2006 www.semtech.com 20-3

XE8805/05A 20.5 Block schematic ck1k ck32k ck128 RegCntA (write) ckrcext/4 RegCntA (read) r Counter A ckrcext o PA(0) Capture f RegCntB (write) d RegCntB (read) Counter B e PA(1) d RegCntC (write) ck1k RegCntC (read) Counter C n s ck32k PA(2) e n m g RegCntD (write) Counter D i RegCntD (read) m s PA(3) PB(0) e o PWM D PB(1) c e w R e Figure 20-1: Counters/timers block schematic N t 20.6 Generalo counter registers operation Counters areN enabled by CntAEnable, CntBEnable, CntCEnable, and CntDEnable in RegCntOn. To stop the counter X, CntXEnable must be reset. To start the counter X, CntXEnable must be set. When counters are cascaded, CntAEnable and CntCEnable also control respectively the counters B and D. In the control registers, all registers must be written in this order: RegCntCtrlCk, RegCntConfig1, RegCntConfig2 and all RegCntX because several bits have no default values at reset. All counters have a corresponding 8-bit read/write register: RegCntA, RegCntB, RegCntC, and RegCntD. When read, these registers contain the counter value (or the captured counter value). When written, they modify the counter comparison values. For a correct acquisition of the counter value, use one of the three following methods: 1) Stop the concerned counter, perform the read operation and restart the counter. While stopped, the counter content is frozen and the counter does not take into account the clock edges delivered on the external pin. © Semtech 2006 www.semtech.com 20-4

XE8805/05A 2) For slow operating counters (typically at least 8 times slower than the CPU clock), oversample the counter content and perform a majority operation on the consecutive read results to select the correct actual content of the counter. 3) Use the capture mechanism. When a value is written into the counter register while the counter is in counter mode, both the comparison value is updated and the counter value is modified. In upcount mode, the register value is reset to zero. In downcount mode, the comparison value is loaded into the counter. Due to the synchronization mechanism between the processor clock domain and the external clock source domain, this modification of the coun ter value can be r postponed until the counter is enabled and it receives it’s first valid clock edge. o In the PWM mode, the counter value is not modified by the write operation in the counter register. Changing the counter mode, does not update the counter value (no load in downcount mode). f d 20.7 Clock selection e The clock source for each counter can be individually selected by writing the appropriate value in the register RegCntCtrlCk. d Table 20-10 gives the correspondence between the binary codes nused for the configsuration bits CntACkSel(1:0), CntBCkSel(1:0), CntCCkSel(1:0) or CntDCkSel(1:0) and the clock source selected respectively for the counters A, B, C or D. e n mClock source forg CntXCkSel(1:0) CounterA CounterB CoiunterC CounterD m s 11 Ck128 10 CkRc/4 e Ck1k 01 o CkRc Ck32k D 00 PA(0) PA(1) PA(2) PA(3) c Table 20-10: Clock sources for counters A, B, C and D e w The CkRc clock is the RC osRcillator. The clocks below 32kHz can be derived from the RC oscillator or the crystal oscillator (see the documentation of the clocke block). A separate external clock source can be delivered on Port A for each individual counter. t N The external clock sources can be debounced or not by setting the Port A configuration registers. o The clock source can be changed only when the counter is stopped. N 20.8 Counter mode selection Each counter can work in one of the following modes: 1) Counter, downcount & upcount 2) Captured counter, downcount & upcount (only counters A&B) 3) PWM, downcount The counters A and B or C and D can be cascaded or not. In cascaded mode, A and C are the LSB counters while B and D are the MSB counters. Table 20-11 shows the different operation modes of the counters A and B as a function of the mode control bits. For all counter modes, the source of the down or upcount selection is given (either the bit CntADownUp or the bit CntBDownUp). Also, the mapping of the interrupt sources IrqA and IrqB and the PWM output on PB(0) in these different modes is shown. © Semtech 2006 www.semtech.com 20-5

XE8805/05A CascadeAB Counter A Counter B IrqA IrqB PB(0) CountPWM0 mode mode source source function CapFunc(1:0) Counter 8b Counter 8b Counter Counter 0 0 00 PB(0) Downup: A Downup: B A B Counter 16b AB Counter 1 0 00 - PB(0) Downup: A AB PWM 8b Counter 8b Counter 0 1 00 - PWM A Down Down B PWM 10 – 16b AB r 1 1 00 - - PWM AB Down o 1x Captured Captured Capture Capture 0 0 or counter 8b counter 8b f PB(0) A B x1 Downup: A Downup: B 1x d Captured counter 16b AB Capture Capture 1 0 or PB(0) Downup: A AB AB x1 e 1x Captured PWM 8b Mdust not Capture 0 1 or counter 8b PWM A Down be used B x1 Downup: B n s Table 20-11: Operating modes of the counters A and B e n Table 20-12 shows the different operation modes of the counters C and D as a function of the mode control bits. m g For all counter modes, the source of the down or upcount selection is given (either the bit CntCDownUp or the bit CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these i different modes is also shown. m s The switching between different modes must be done while the concerned counters are stopped. While switching e capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode o change. D c e Counterw C Counter D IrqC IrqD PB(1) CascadeCD CountPWM1 R mode mode Source source function e Counter 8b Counter 8b Counter Counter PB(1) 0 0 NDownup: C Downup: D C D t Counter 16b CD Counter - PB(1) 1o 0 Downup: C CD PWM 8b Counter 8b - Counter PWM C N 0 1 Down Down D PWM 10 – 16b CD - - PWM CD 1 1 Down Table 20-12: Operating modes of the counters C and D 20.9 Counter / Timer mode The counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock periods applied on the counter clock input. Each counter can be set individually either in upcount mode by setting CntXDownUp in the register RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave as a 16 bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the up/down count modes set for the counters A and C. © Semtech 2006 www.semtech.com 20-6

XE8805/05A When in upcount mode, the counter will start incrementing from zero up to the target value which has been written in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is generated at the next falling edge of counter clock. Then the counter is loaded again with the zero value at the next rising edge of counter clock (Figure 20-2). When in downcount mode, the counter will start decrementing from the initial load value which has been written in the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an interrupt is generated at the next falling edge of counter clock. Then the counter is loaded again with the load value at the next rising edge of counter clock (Figure 20-2). r Be careful to select the counter mode (no capture, not PWM, specify cascaded or not anod up or down counting mode) before writing any target or load value to the RegCntX register(s). This ensures that the counter will start f from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that both cascaded counters will start from the correct initial values. d The stopping and consecutive starting of a counter in counter mode without a target or load value write operation in e between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it’s target value (upcount). This interrupt is additional to the interrupt which has dalready been generated when the counter reached the zero or the target value. n s down counting e n clock counter X m g RegcntX_r XX 3 2 1 0 3 2 1 0 3 2 1 0 i m s RegCntX_w XX 3 e write RegCntX o D CntXDownUp c IrqX e w CntXEnable R up counting e clock counter X N t o RegCntX_r XX 0 1 2 3 0 1 2 3 0 1 2 3 RegCNntX_w XX 3 write RegCntX CntXDownUp IrqX CntXEnable Figure 20-2. Up and down count interrupt generation. © Semtech 2006 www.semtech.com 20-7

XE8805/05A 20.10 PWM mode The counters can generate PWM signals (Pulse Width Modulation) on the Port B outputs PB(0) and PB(1). The PWM mode is selected by setting CntPWM1 and CntPWM0 in the RegCntConfig1 register. See Table 20-11 and Table 20-12 for an exact description of how the setting of CntPWM1 and CntPWM0 affects the operating mode of the counters A, B, C and D according to the other configuration settings. When CntPWM0 is enabled, the PWMA or PWMAB output value overrides the value set in bit 0 of RegPBOut in the Port B peripheral. When CntPWM1 is enabled, the PWMC or PWMCD output value overrides the value set in r bit 1 of RegPBOut. The corresponding ports (0 and/or 1) of Port B must be set in digital mode and as output and o either open drain or not and pull up or not through a proper setting of the control registers of the Port B. f Counters in PWM mode always count down, the CntXDownUp bit setting must be reset. No interrupts and events are generated by the counters which are in PWM mode. Counters do count circularly: they restart at the maximal d value (either 0xFF when not cascaded or 0xFFFF when cascaded) when respectively an underflow condition occurs in the counting. e The internal PWM signals are low as long as the counter contents are hdigher than the PWM code values written in the RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values. n s The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded. PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 eregister are used tno set the PWM resolution for the counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in m g cascaded mode are shown in Table 20-13. Choosing a 16 bit PWM code higher than the maximum value that can be represented by the number of bits chosen for the resolution, results in a PWM output which is always tied to 1. i m s PwmXsize(1:0) Resolution 11 e16 bits 10 o 14 bits D 01 12 bits c 00 10 bits e Table 20-13: Resolution wselection in cascaded PWM mode R e N Smaltl PWM code o Tlsmall Thsmall N Large PWM code Tllarge Thlarge Tper Figure 20-3: PWM modulation examples The period of the PWM signal is given by the formula: 2resolution Tper = f ckcnt © Semtech 2006 www.semtech.com 20-8

XE8805/05A The duty cycle ratio DCR of the PWM signal is defined as: Th DCR = Tper 2resolution −1 DCR can be selected between 0 % and *100 %. 2resolution DCR in % in function of the RegCntX content(s) is given by the relation: 100*RegCntX DCR = r 2resolution o 20.11 Capture function f The 16-bit capture register is provided to facilitate frequency measurements. It prdovides a safe reading mechanism for the counters A and B when they are running. When the capture function is active, the processor does not read anymore the counters A and B directly, but instead reads shadow registeers located in the capture block. An interrupt is generated after a capture condition has been met when the shadow register content is updated. The d capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or from the external PA(2) or PA(3) ports. Both counters use the same capture condition. n s When the capture function is active, the A and B counters must be written with the value 0xFF and can either e n upcount or downcount. They do count circularly: they restart at zero or at the maximal value (either 0xFF when not cascaded or 0xFFFF when cascaded) when respectivemly an overflow or gan underflow condition occurs in the counting. i CapFunc(1:0) in register RegCntConfig2 determmines if the captures function is enabled or not and selects which edges of the capture signal source are valid for the capture operation. The source of the capture signal can be selected by setting CapSel(1:0) in the RegCntConfig2 regiseter. For all sources, rising, falling or both edge o sensitivity can be selected. Table 20-14 shows the capture condition as a function of the setting of these D configuration bits. c CapSel(1:0) Selected ceapture signal Ca pFunc Selected condition Capture condition w 00 Capture disabled - R 01 Rising edge 1 K rising edge 11 1 K e 10 Falling edge 1 K falling edge 11 Both edges 1 K both edges N t 00 Capture disabled - o 01 Rising edge 32 K rising edge 10 32 K 10 Falling edge 32 K falling edge N 11 Both edges 32 K both edges 00 Capture disabled - 01 Rising edge PA3 rising edge 01 PA3 10 Falling edge PA3 falling edge 11 Both edges PA3 both edges 00 Capture disabled - 01 Rising edge PA2 rising edge 00 PA2 10 Falling edge PA2 falling edge 11 Both edges PA2 both edges Table 20-14: Capture condition selection CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be corrupted during one counter clock cycle. Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the © Semtech 2006 www.semtech.com 20-9

XE8805/05A same clock, the interruptions on IrqA and IrqB which inform that the capture condition was met, may appear at different moments. In this case, the processor should read the shadow register associated to a counter only if the interruption related to this counter has been detected. It must be noted that when counters A and B are cascaded, the capture might happen at different cycles for the A and B registers. This is due to the asynchronous relationship between counter and capture clock and to the fact that the capture condition detection is independent for A and B counters. r o f d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 20-10

XE8805/05A 21 VLD (Voltage Level Detector) 21.1 Features r 21-2 o 21.2 Overview 21-2 f 21.3 Register map 21-2 d 21.4 Interrupt map 21-2 e 21.5 VLD operation d 21-2 n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 21-1

XE8805/05A 21.1 Features • Can be switched off, on or simultaneously with CPU activities • Generates an interrupt if power supply is below a pre-determined level 21.2 Overview The Voltage Level Detector monitors the state of the system battery. It returns a logical high vralue (an interrupt) in the status register if the supplied voltage drops below the user defined level (Vsb). o 21.3 Register map f d There are two registers in the VLD, namely RegVldCtrl and RegVldStat. Table 221-1 shows the mapping of control bits and functionality of RegVldCtrl while Table 221-2 describes that efor RegVldStat. d pos. RegVldCtrl rw reset function n s 7-4 -- r 0000 reserved 3 VldRange r w 0 resetsystem VLD edetection voltage rannge for VldTune = “011”: 0 : 1.3V m g 1 : 2.55V 2-0 VldTune[2:0] r w 000 VLD tuning: i resetsystemm 000 : +19 s% 111 : -18 % e Table 221-1: RegVldCtrl o D c pos. RegVldStat rw reset function 7-3 -- r 00000 reserved e w 2 VldResult r 0 resetsystem is 1 when battery voltage is below the detection R voltage 1 VldValid r 0 resetseystem Indicates when VldResult can be read 0 VldEn r w 0 resetsystem VLD enable N t Table 221-2: RegVldStat o 21.4 InterrNupt map interrupt source mapping in the interrupt manager IrqVld RegIrqMid(2) Table 221-3: Interrupt map 21.5 VLD operation The VLD is controlled by VldRange, VldTune and VldEn. VldRange selects the voltage range to be detected, while VldTune is used to fine-tune this voltage level in 8 steps. VldEn is used to enable (disable) the VLD with a 1(0) value respectively. Disabled, the block will dissipate no power. © Semtech 2006 www.semtech.com 21-2

XE8805/05A symbol description min typ max unit comments trimming values: Note 1 VldRange VldTune 1.53 0 000 1.44 0 001 1.36 0 010 1.29 0 011 1.22 0 100 r 1.16 0 101 1.11 0 o 110 Vth Threshold voltage V 1.06 0 111 f 3.06 1 000 2.88 d 1 001 2.72 1 010 2.57 e 1 011 2.44 1 100 d 2.33 1 101 2.22 n s1 110 2.13 1 111 duration of e n T 2.0 2.5 ms Note 2 EOM measurement Minimum pulse width m g T 875 1350 us Note 2 PW detected i Table 221-4: Voltage level detector operation m s e Note 1: absolute precision of the threshold voltage is ±10%. o D Note 2: this timing is respected in case the internal RC or crystal oscillators are enabled c To start the voltage level detectione, the user sets bit VldEn. The measurement is started. w After 2ms, the bit VldValid isR set to indicate that the measurement results are valid. From that time on, as long as the VLD is enabled, a maskable interrupt requeest is sent if the voltage level falls below the threshold. One can also poll the VLD and mon itor the actual measurement result by reading the VldResult bit of the RegVldStat. This N result is only valid ast long as the VldValid bit is ‘1’. o An interrupt is generated on each rising edge of VldResult. N © Semtech 2006 www.semtech.com 21-3

XE8805/05A 22 Physical Dimensions r o 22.1 QFP type package 22-2 f d e d n s e n m g i m s e o D c e w R e N t o N © Semtech 2006 www.semtech.com 22-1

XE8805/05A 22.1 QFP type package The QFP package dimensions are given in Figure 22-1 and Table 22-1. The dimensions conform to JEDEC MS- 026 Rev. C. r o f d e d n s e n Figure 22-1. QFP type package m g i package A B C D mE F sG e o mm mm mm mm mm mm mm D 10.0 12.0 1.4 0.10 0.22 0.5 LQFP-64 c e Table 22-1. QFP package dimensions w R e N t o N © Semtech 2006 www.semtech.com 22-2

XE8805/05A r o f d e d n s e n m g © Semtech 2005 All rights reserved. Reproduction in whole or in part is prohibited without thei prior written consent of the copyright owner. The information presented in this document does not form mpart of anyquotations or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other inedustrial or intellectual property rights. Semtech. assumes o no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper D installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to c parameters beyond the specified maximum ratings or operation outside the specified range. e SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDwED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIRONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE e CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold SemtechN and its officers, employees, subsidiaries, affiliates, and distributors harmless t against all claims, costs damages and attorney fees which could arise. o Contact InformNation Taiwan Tel: 886-2-2748-3380 Switzerland Tel: 41-32-729-4000 Fax: 886-2-2748-3390 Fax: 41-32-729-4001 Korea Tel: 82-2-527-4377 United Kingdom Tel: 44-1794-527-600 Fax: 82-2-527-4376 Fax: 44-1794-527-601 Shanghai Tel: 86-21-6391-0830 France Tel: 33-(0)169-28-22-00 Fax: 86-21-6391-0831 Fax: 33-(0)169-28-12-98 Japan Tel: 81-3-6408-0950 Germany Tel: 49-(0)8161-140-123 Fax: 81-3-6408-0951 Fax: 49-(0)8161-140-124 Semtech International AG is a wholly-owned subsidiary of Semtech Corporation, which has its headquarters in the U.S.A © Semtech 2006 www.semtech.com 22-3