0 R XCR3064XL 64 Macrocell CPLD DS017 (v2.4) September 15, 2008 Product Specification 0 14 Features Description (cid:129) Low power 3.3V 64 macrocell CPLD The CoolRunner™ XPLA3 XCR3064XL device is a 3.3V, (cid:129) 5.5 ns pin-to-pin logic delays 64-macrocell CPLD targeted at power sensitive designs (cid:129) System frequencies up to 192 MHz that require leading edge programmable logic solutions. A (cid:129) 64 macrocells with 1,500 usable gates total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are as fast as 5.5 ns with a (cid:129) Available in small footprint packages maximum system frequency of 192 MHz. - 44-pin VQFP (36 user I/O pins) - 48-ball CS BGA (40 user I/O pins) TotalCMOS Design Technique for Fast - 56-ball CP BGA (48 user I/O pins) Zero Power - 100-pin VQFP (68 user I/O pins) CoolRunner XPLA3 CPLDs offer a TotalCMOS solution, (cid:129) Optimized for 3.3V systems both in process technology and design technique. Xilinx - Ultra-low power operation employs a cascade of CMOS gates to implement its sum of - Typical Standby Current of 17 μA at 25°C products instead of the traditional sense amp approach. - 5V tolerant I/O pins with 3.3V core supply This CMOS gate implementation allows Xilinx to offer - Advanced 0.35 micron five layer metal EEPROM CPLDs that are both high performance and low power, process breaking the paradigm that to have low power, you must have low performance. Refer to Figure1 and Table1 show- - Fast Zero Power CMOS design technology ing the I vs. Frequency of our XCR3064XL TotalCMOS - 3.3V PCI electrical specification compatible CC CPLD (data taken with four resetable up/down, 16-bit outputs (no internal clamp diode on any input or counters at 3.3V, 25°C). I/O, no minimum clock input capacitance) (cid:129) Advanced system features 45 - In-system programming 40 - Input registers - Predictable timing model 35 - Up to 23 available clocks per function block A) 30 - Excellent pin retention during design changes m ( 25 - Full IEEE Standard 1149.1 boundary-scan (JTAG) C C - Four global clocks al I 20 c - Eight product term control terms per function block pi y 15 (cid:129) Fast ISP programming times T 10 (cid:129) Port Enable pin for dual function of JTAG ISP pins (cid:129) 2.7V to 3.6V supply voltage at industrial temperature 5 range 0 (cid:129) Programmable slew rate control per macrocell 0 20 40 60 80 100 120 140 160 180 (cid:129) Security bit prevents unauthorized access Frequency (MHz) (cid:129) Refer to XPLA3 family data sheet (DS012) for architecture description DS017_01_062502 Figure 1: I vs. Frequency at V = 3.3V, 25°C CC CC Table 1: I vs. Frequency (V = 3.3V, 25°C) CC CC Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140 160 180 Typical I (mA) 0.017 0.24 1.09 2.15 4.28 8.50 12.85 16.80 20.80 25.72 29.89 33.53 36.27 CC © 2000–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS017 (v2.4) September 15, 2008 www.xilinx.com 1 Product Specification

XCR3064XL 64 Macrocell CPLD R DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter(1) Test Conditions Typical Min. Max. Unit V (2) Output High voltage V = 3.0V to 3.6V, I = –8 mA - 2.4 - V OH CC OH V = 2.7V to 3.0V, I = –8 mA - 2.0 - V CC OH I = –500 μA - 90% - V OH V (3) CC V Output Low voltage for 3.3V outputs I = 8 mA - - 0.4 V OL OL I (4) Input leakage current V = GND or V to 5.5V - –10 10 μA IL IN CC I (4) I/O High-Z leakage current V = GND or V to 5.5V - –10 10 μA IH IN CC I (8) Standby current V = 3.6V 24.5 - 100 μA CCSB CC I Dynamic current(5,6) f = 1 MHz - - 0.75 mA CC f = 50 MHz - - 15 mA C Input pin capacitance(7) f = 1 MHz - - 8 pF IN C Clock input capacitance(7) f = 1 MHz - - 12 pF CLK C I/O pin capacitance(7) f = 1 MHz - - 10 pF I/O Notes: 1. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. Typical leakage current is less than 1 μA. 5. See Table1, and Figure1 for typical values. 6. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to V or ground. This parameter guaranteed by design and characterization, not testing. CC 7. Typical values, not tested. 8. Typical value at 70°C. 100 90 IOL(3.3V) 80 70 60 A 50 m IOH(3.3V) 40 30 IOH(2.7V) 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Volts DS012_10_031802 Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25°C 2 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification

R XCR3064XL 64 Macrocell CPLD AC Electrical Characteristics Over Recommended Operating Conditions -6 -7 -10 Symbol Parameter(1,2) Min. Max. Min. Max. Min. Max. Unit T Propagation delay time (single p-term) - 5.5 - 7.0 - 9.1 ns PD1 T Propagation delay time (OR array)(3) - 6.0 - 7.5 - 10.0 ns PD2 T Clock to output (global synchronous pin clock) - 4.0 - 5.0 - 6.5 ns CO T Setup time (fast input register) 2.5 - 2.5 - 3.0 - ns SUF T (4) Setup time (single p-term) 3.5 - 4.3 - 5.4 - ns SU1 T Setup time (OR array) 4.0 - 4.8 - 6.3 - ns SU2 T (4) Hold time 0 - 0 - 0 - ns H T (4) Global Clock pulse width (High or Low) 2.5 - 3.0 - 4.0 - ns WLH T (4) P-term clock pulse width 4.0 - 5.0 - 6.0 - ns PLH T Asynchronous preset/reset pulse width (High or Low) 4.0 - 5.0 - 6.0 - ns APRPW T (4) Input rise time - 20 - 20 - 20 ns R T (4) Input fall time - 20 - 20 - 20 ns L f (4) Maximum system frequency - 192 - 119 - 95 MHz SYSTEM T (4) Configuration time(5) - 60 - 60 - 60 μs CONFIG T (4) ISP initialization time - 60 - 60 - 60 μs INIT T (4) P-term OE to output enabled - 7.5 - 9.3 - 11.2 ns POE T (4) P-term OE to output disabled(6) - 7.5 - 9.3 - 11.2 ns POD T (4) P-term clock to output - 7.0 - 8.3 - 10.7 ns PCO T (4) P-term set/reset to output valid - 8.0 - 9.3 - 11.2 ns PAO Notes: 1. Specifications measured with one output switching. 2. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 6 mA at 3.6V. 6. Output C = 5 pF. L DS017 (v2.4) September 15, 2008 www.xilinx.com 3 Product Specification

XCR3064XL 64 Macrocell CPLD R Internal Timing Parameters -6 -7 -10 Symbol Parameter(1, 2) Min. Max. Min. Max. Min. Max. Unit Buffer Delays T Input buffer delay - 1.3 - 1.6 - 2.2 ns IN T Fast Input buffer delay - 2.3 - 3.0 - 3.1 ns FIN T Global Clock buffer delay - 0.8 - 1.0 - 1.3 ns GCK T Output buffer delay - 2.2 - 2.7 - 3.6 ns OUT T Output buffer enable/disable delay - 4.2 - 5.0 - 5.7 ns EN Internal Register and Combinatorial Delays T Latch transparent delay - 1.3 - 1.6 - 2.0 LDI T Register setup time 1.0 - 1.0 - 1.2 - ns SUI T Register hold time 0.3 - 0.5 - 0.7 - ns HI T Register clock enable setup time 2.0 - 2.5 - 3.0 - ns ECSU T Register clock enable hold time 3.0 - 4.5 - 5.5 - ns ECHO T Register clock to output delay - 1.0 - 1.3 - 1.6 ns COI T Register async. S/R to output delay - 2.5 - 2.3 - 2.1 ns AOI T Register async. recovery - 4.0 - 5.0 - 6.0 ns RAI T Product term clock delay - 2.5 - 2.7 - 3.3 ns PTCK T Internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns LOGI1 T Internal logic delay (PLA OR term) - 2.5 - 3.2 - 4.2 ns LOGI2 Feedback Delays T ZIA delay - 0.7 - 2.9 - 3.5 ns F Time Adders T Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns LOGI3 T Universal delay - 1.5 - 2.0 - 2.5 ns UDA T Slew rate limited delay - 4.0 - 5.0 - 6.0 ns SLEW Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See the CoolRunner XPLA3 family data sheet (DS012) for timing model. 4 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification

R XCR3064XL 64 Macrocell CPLD Switching Characteristics VCC S1 Component Values R1 390Ω R2 390Ω R1 C1 35 pF V IN V OUT Measurement S1 S2 R2 C1 TPOE (High) Open Closed TPOE (Low) Closed Open TP Closed Closed Note: For TPOD, C1 = 5 pF. Delay measured at S2 output level of VOL + 300 mV, VOH – 300 mV. DS017_03_102401 Figure 3: AC Load Circuit 5.6 +3.0V 90% 5.5 5.4 5.3 10% 0V 5.2 ) s n 5.1 ( T T R L 5.0 1.5 ns 1.5 ns 4.9 4.8 Measurements: 4.7 All circuit delays are measured at the +1.5V level of 4.6 inputs and outputs, unless otherwise specified. 1 2 4 8 16 Number of Adjacent Outputs Switching DS017_05_042800 3.3V, 25°C Figure 5: Voltage Waveform DS017_04_062502 Figure 4: Derating Curve for T , 3.3V, 25°C PD2 DS017 (v2.4) September 15, 2008 www.xilinx.com 5 Product Specification

XCR3064XL 64 Macrocell CPLD R Pin Descriptions Table 3: XCR3064XL I/O Pins Function Macro- Block cell PC44(1) VQ44 CS48 CP56 VQ100 Table 2: XCR3064XL User I/O Pins 2 14 11 5 D3 E3 12 PC44(1) VQ44 CS48 CP56 VQ100 2 15 12 6 D1 F1 13 Total User I/O 36 36 40 48 68 Pins 2 16 - - - - 14 1. This is an obsolete package type. It remains here for legacy 3 1 32(2) 26(2) E5(2) F10(2) 62(2) support only 3 2 31 25 E7 G8 61 3 3 - - - - 60 Table 3: XCR3064XL I/O Pins 3 4 29 23 F7 H10 58 Function Macro- Block cell PC44(1) VQ44 CS48 CP56 VQ100 3 5 - - - - 57 1 1 41 35 C5 C8 85 3 6 - - - - 56 1 2 40 34 A6 A8 84 3 7 - - F6 K8 54 1 3 - - - - 83 3 8 - - - K10 52 1 4 - - - A9 81 3 9 28 22 G7 K9 48 1 5 - - - A5 80 3 10 27 21 G6 J10 47 1 6 - - A7 A10 79 3 11 26 20 F5 H8 46 1 7 - - - - 76 3 12 25 19 G5 H7 45 1 8 39 33 B6 B10 75 3 13 24 18 F4 H6 44 1 9 38(2) 32(2) B7(2) C10(2) 73(2) 3 14 - - - - 42 1 10 37 31 D4 D8 71 3 15 - - - K7 41 1 11 36 30 C6 E8 69 3 16 - - - - 40 1 12 - - - - 68 4 1 13(2) 7(2) D2(2) G1(2) 15(2) 1 13 - - - - 67 4 2 14 8 E1 F3 16 1 14 34 28 D6 F8 65 4 3 - - - - 17 1 15 33 27 D7 E10 64 4 4 16 10 F1 G3 19 1 16 - - - - 63 4 5 17 11 G1 J1 20 2 1 4 42 A2 C4 92 4 6 - - - - 21 2 2 5 43 A1 C3 93 4 7 - - - - 23 2 3 6 44 C4 A1 94 4 8 - - - K1 25 2 4 - - - - 96 4 9 18 12 E4 K4 29 2 5 - - - B1 97 4 10 19 13 F2 K2 30 2 6 - - - - 98 4 11 20 14 G2 K3 31 2 7 - - - A2 99 4 12 21 15 F3 H3 32 2 8 - - B2 A3 100 4 13 - - G3 H4 33 2 9 7(2) 1(2) B1(2) C1(2) 4(2) 4 14 - - - - 35 2 10 8 2 C2 D1 6 4 15 - - - K5 36 2 11 9 3 C1 D3 8 4 16 - - - - 37 2 12 - - - - 9 Notes: 1. This is an obsolete package type. It remains here for legacy 2 13 - - - - 10 support only. 2. JTAG pins. 6 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification

R XCR3064XL 64 Macrocell CPLD Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type PC44(1) VQ44 CS48 CP56 VQ100 IN0 / CLK0 2 40 A3 C5 90 IN1 / CLK1 1 39 B4 C6 89 IN2 / CLK2 44 38 A4 C7 88 IN3 / CLK3 43 37 B5 A6 87 TCK 32 26 E5 F10 62 TDI 7 1 B1 C1 4 TDO 38 32 B7 C10 73 TMS 13 7 D2 G1 15 PORT_EN 10(2) 4(2) C3(2) E1(2) 11(2) V 3, 15, 23, 35 9, 17, 29, 41 B3, C7, E2, G4 A4, D10, H1, H5 3, 18, 34, 39, 51, CC 66, 82, 91 GND 22, 30, 42 16, 24, 36 A5, E3, E6 A7, G10, K6 26, 38, 43, 59, 74, 86, 95 No Connects - - - - 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 Notes: 1. This is an obsolete package type. It remains here for legacy support only. 2. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for more information. Device Part Marking R Device Type XCRxxxxXL Package TQ144 This line not Speed 7C related to device part number Operating Range 1 Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: · Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 3064XL. · Line 2 = Not related to device part number. · Line 3 = Not related to device part number. · Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C1 = CS48, C2 = CSG48, C3 = CP56, C4 = CPG56. DS017 (v2.4) September 15, 2008 www.xilinx.com 7 Product Specification

XCR3064XL 64 Macrocell CPLD R Ordering Combination Information Speed No. Device Ordering and (pin-to-pin Pkg. of Operating Part Marking Number delay) Symbol Pins Package Type Range(1) XCR3064XL-6VQ44C 6 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3064XL-6VQG44C 6 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3064XL-6CS48C 6 ns CS48 48 Chip Scale Package (CSP) C XCR3064XL-6CSG48C 6 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3064XL-6CP56C 6 ns CP56 56 Chip Scale Package (CSP) C XCR3064XL-6CPG56C 6 ns CPG56 56 Chip Scale Package (CSP); Pb-Free C XCR3064XL-6VQ100C 6 ns VQ100 100 Very Thin Quad Flat Package (VQFP) C XCR3064XL-6VQG100C 6 ns VQG100 100 Very Thin Quad Flat Package (VQFP); C Pb-Free XCR3064XL-7VQ44C 7.5 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3064XL-7VQG44C 7.5 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3064XL-7CS48C 7.5 ns CS48 48 Chip Scale Package (CSP) C XCR3064XL-7CSG48C 7.5 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3064XL-7CP56C 7.5 ns CP56 56 Chip Scale Package (CSP) C XCR3064XL-7CPG56C 7.5 ns CPG56 56 Chip Scale Package (CSP); Pb-Free C XCR3064XL-7VQ100C 7.5 ns VQ100 100 Very Thin Quad Flat Package (VQFP) C XCR3064XL-7VQG100C 7.5 ns VQG100 100 Very Thin Quad Flat Package (VQFP); C Pb-Free XCR3064XL-7VQ44I 7.5 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) I XCR3064XL-7VQG44I 7.5 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free I XCR3064XL-7CS48I 7.5 ns CS48 48 Chip Scale Package (CSP) I XCR3064XL-7CSG48I 7.5 ns CSG48 48 Chip Scale Package (CSP); Pb-Free I XCR3064XL-7CP56I 7.5 ns CP56 56 Chip Scale Package (CSP) I XCR3064XL-7CPG56I 7.5 ns CPG56 56 Chip Scale Package (CSP); Pb-Free I XCR3064XL-7VQ100I 7.5 ns VQ100 100 Very Thin Quad Flat Package (VQFP) I XCR3064XL-7VQG100I 7.5 ns VQG100 100 Very Thin Quad Flat Package (VQFP); I Pb-Free XCR3064XL-10VQ44C 10 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) C XCR3064XL-10VQG44C 10 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free C XCR3064XL-10CS48C 10 ns CS48 48 Chip Scale Package (CSP) C XCR3064XL-10CSG48C 10 ns CSG48 48 Chip Scale Package (CSP); Pb-Free C XCR3064XL-10CP56C 10 ns CP56 56 Chip Scale Package (CSP) C XCR3064XL-10CPG56C 10 ns CPG56 56 Chip Scale Package (CSP); Pb-Free C XCR3064XL-10VQ100C 10 ns VQ100 100 Very Thin Quad Flat Package (VQFP) C XCR3064XL-10VQG100C 10 ns VQG100 100 Very Thin Quad Flat Package (VQFP); C Pb-Free XCR3064XL-10VQ44I 10 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) I XCR3064XL-10VQG44I 10 ns VQG44 44 Very Thin Quad Flat Pack (VQFP); Pb-Free I XCR3064XL-10CS48I 10 ns CS48 48 Chip Scale Package (CSP) I XCR3064XL-10CSG48I 10 ns CSG48 48 Chip Scale Package (CSP); Pb-Free I XCR3064XL-10CP56I 10 ns CP56 56 Chip Scale Package (CSP) I 8 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification

R XCR3064XL 64 Macrocell CPLD Ordering Combination Information (Continued) Speed No. Device Ordering and (pin-to-pin Pkg. of Operating Part Marking Number delay) Symbol Pins Package Type Range(1) XCR3064XL-10CPG56I 10 ns CPG56 56 Chip Scale Package (CSP); Pb-Free I XCR3064XL-10VQ100I 10 ns VQ100 100 Very Thin Quad Flat Package (VQFP) I XCR3064XL-10VQG100I 10 ns VQG100 100 Very Thin Quad Flat Package (VQFP); I Pb-Free Notes: 1. C = Commercial: T = 0° to +70°C; I = Industrial: T = –40° to +85°C A A DS017 (v2.4) September 15, 2008 www.xilinx.com 9 Product Specification

XCR3064XL 64 Macrocell CPLD R Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Additional Information CoolRunner XPLA3 CPLD Data Sheets and Application Device Packages Notes Device Package User Guide Revision History The following table shows the revision history for this document. Date Version Revision 06/01/00 1.0 Initial Xilinx release. 08/30/00 1.1 Added 48-ball CS BGA package. 11/18/00 1.2 Updated to full production data sheet; corrected note in Table4 to read: "port enable pin is brought High". 12/08/00 1.3 Added PC44 package. 04/11/01 1.4 Added Typical I/V curve, Figure2; added Table2: Total User I/O; changed V spec. OH 04/19/01 1.5 Updated Typical I/V curve, Figure2: added voltage levels. 01/08/02 1.6 Moved I vs. Freq Figure1 and Table1 to page 1. Added single p-term setup time (T ) CC SU1 to AC Table, renamed T to T for setup time through the OR array. Updated T and SU SU2 SUF T spec to match software timing. Added T spec. Updated T spec. Updated T FIN INIT CONFIG HI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for T delay measurement. Updated note 5 in AC Characteristics POD table lowering typical current draw during configuration. 04/02/02 1.7 Updated the following specs based on characterization of product after move to UMC fabrication: V , F , T (added T parameter), T , and T . Added typical OH SYSTEM PCO PTCK F LOGI3 leakage current note to DC table. Also updated Typical I vs. Frequency and Derating CC Curve for T (improved to 5.4 ns for 16 outputs switching) per new characterization data. PD2 01/27/03 1.8 Corrected typical I vs. Frequency (Figure1) and Derating Curve for T (Figure4). CC PD2 Updated F for -6 speed, I @ f=1 MHz based on characterization of product after move MAX CC to UMC fabrication. Updated Ordering Information format. 07/15/03 1.9 Updated Device Part Marking. Updated test conditions for I and I . IL IH 08/21/03 2.0 Updated Package Device Marking Pin 1 orientation. 02/13/04 2.1 Add soldering temperature. Add links to application notes and data sheets and packages. 04/08/05 2.2 Added I Typical and T specifications. Removed T specification. CCSB APRPW SOL 03/31/06 2.3 Added Warranty Disclaimer. Added Pb-Free information to ordering table. 09/15/08 2.4 Added notes to Table2, Table3 and Table4 to indicate the PC44 package is obsolete. Removed part number references to the obsolete PC44C and PCG44C packages in the Ordering Combination Information. See Product Discontinuation Notice xcn07022.pdf. 10 www.xilinx.com DS017 (v2.4) September 15, 2008 Product Specification