0 XC95288XL High Performance R CPLD DS055 (v2.1 April 3, 2007 Product Specification 0 5 Features cations and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with • 6 ns pin-to-pin logic delays • System frequency up to 208 MHz propagation delays of 6ns. See Figure2 for architecture • 288 macrocells with 6,400 usable gates overview. • Available in small footprint packages Power Estimation - 144-pin TQFP (117 user I/O pins) Power dissipation in CPLDs can vary substantially depend- - 208-pin PQFP (168 user I/O pins) ing on the system frequency, design application and output - 256-pin BGA (192 user I/O pins) loading. To help reduce power dissipation, each macrocell - 256-pin FBGA (192 user I/O pins) in a XC9500XL device may be configured for low-power - 280-pin CSP (192 user I/O pins) mode (from the default high-performance mode). In addi- - Pb-free available for all packages tion, unused product-terms and macrocells are automati- • Optimized for high-performance 3.3V systems cally deactivated by the software to further conserve power. - Low power operation For a general estimate of I , the following equation may be CC - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V used: signals I (mA) = MC (0.175*PT + 0.345) + MC (0.052*PT CC HS HS LP LP - 3.3V or 2.5V output capability + 0.272) + 0.04 * MC (MC +MC )* f TOG HS LP - Advanced 0.35 micron feature size CMOS where: FastFLASH™ technology MC = # macrocells in high-speed configuration HS • Advanced system features PT = average number of high-speed product terms HS - In-system programmable per macrocell - Superior pin-locking and routability with MC = # macrocells in low power configuration LP FastCONNECT™ II switch matrix PT = average number of low power product terms per LP - Extra wide 54-input Function Blocks macrocell - Up to 90 product-terms per macrocell with f = maximum clock frequency individual product-term allocation MCTOG = average % of flip-flops toggling per clock - Local clock inversion with three global and one (~12%) product-term clocks This calculation was derived from laboratory measurements - Individual output enable per output pin with local of an XC9500XL part filled with 16-bit counters and allowing inversion a single output (the LSB) to be enabled. The actual ICC - Input hysteresis on all user and boundary-scan pin value varies with the design application and should be veri- fied during normal system operation. Figure1 shows the inputs above estimation in a graphical form. For a more detailed - Bus-hold circuitry on all user pin inputs discussion of power consumption in this device, see Xilinx - Full IEEE Standard 1149.1 boundary-scan (JTAG) • Fast concurrent programming • Slew rate control on individual outputs • Enhanced data security features • Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V • Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP package WARNING: Programming temperature range of T = 0° C to +70° C A Description The XC95288XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- © 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS055 (v2.1 April 3, 2007 www.xilinx.com 1 Product Specification 1-800-255-7778

XC95288XL High Performance CPLD R application note XAPP114, “Understanding XC9500XL CPLD Power.” 550 208 MHz 500 A) 440500 High Performance m 350 (C C 300 Typical I 220500 Low P ower 94 MHz 150 100 50 0 50 100 150 200 250 Clock Frequency (MHz) DS055_01_121501 Figure 1: Typical I vs. Frequency for XC95288XL CC 2 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification

R XC95288XL High Performance CPLD 3 JTAG JTAG Port 1 In-System Programming Controller Controller 54 Function I/O 18 Block 1 Macrocells I/O 1 to 18 I/O I/O atrix 54 Function M 18 Block 2 h c Macrocells I/O wit 1 to 18 S Blocks T II I/O C E 54 N Function I/O N O 18 Block 3 C I/O st Macrocells a 1 to 18 F I/O 3 I/O/GCK 54 Function 1 I/O/GSR 18 Block 4 4 Macrocells I/O/GTS 1 to 18 54 Function 18 Block 16 Macrocells 1 to 18 DS055_02_101300 Figure 2: XC95288XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. DS055 (v2.1 April 3, 2007 www.xilinx.com 3 Product Specification 1-800-255-7778

XC95288XL High Performance CPLD R Absolute Maximum Ratings(2) Symbol Description Value Units V Supply voltage relative to GND –0.5 to 4.0 V CC V Input voltage relative to GND(1) –0.5 to 5.5 V IN V Voltage applied to 3-state output(1) –0.5 to 5.5 V TS T Storage temperature (ambient)(3) –65 to +150 oC STG T Junction temperature +150 oC J Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. External I/O voltage may not exceed V by 4.0V. CCINT 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427. Recommended Operation Conditions Symbol Parameter Min Max Units V Supply voltage for internal logic Commercial T = 0oC to 70oC 3.0 3.6 V CCINT A and input buffers Industrial T = –40oC to +85oC 3.0 3.6 V A V Supply voltage for output drivers for 3.3V operation 3.0 3.6 V CCIO Supply voltage for output drivers for 2.5V operation 2.3 2.7 V V Low-level input voltage 0 0.80 V IL V High-level input voltage 2.0 5.5 V IH V Output voltage 0 V V O CCIO Quality and Reliability Characteristics Symbol Parameter Min Max Units T Data Retention 20 - Years DR N Program/Erase Cycles (Endurance) 10,000 - Cycles PE V Electrostatic Discharge (ESD) 2,000 - Volts ESD DC Characteristic Over Recommended Operating Conditions Symbol Parameter Test Conditions Min Max Units V Output high voltage for 3.3V outputs I = –4.0 mA 2.4 - V OH OH Output high voltage for 2.5V outputs I = –500 μA 90% V - V OH CCIO V Output low voltage for 3.3V outputs I = 8.0 mA - 0.4 V OL OL Output low voltage for 2.5V outputs I = 500 μA - 0.4 V OL I Input leakage current V = Max; V = GND or V - ±10 μA IL CC IN CC I I/O high-Z leakage current V = Max; V = GND or V - ±10 μA IH CC IN CC I I/O high-Z leakage current V = Max; V = Max; - ±10 μA IH CC CCIO V = GND or 3.6V IN V Min < V < 5.5V - ±50 μA CC IN C I/O capacitance V = GND; f = 1.0 MHz - 10 pF IN IN I Operating supply current V = GND, No load; f = 1.0 MHz 85 (Typical) mA CC IN (low power mode, active) 4 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification

R XC95288XL High Performance CPLD AC Characteristics XC95288XL-6 XC95288XL-7 XC95288XL-10 Symbol Parameter Min Max Min Max Min Max Units T I/O to output valid - 6.0 - 7.5 - 10.0 ns PD T I/O setup time before GCK 4.0 - 4.8 - 6.5 - ns SU T I/O hold time after GCK 0 - 0 - 0 - ns H T GCK to output valid - 3.8 - 4.5 - 5.8 ns CO f Multiple FB internal operating frequency - 208.3 - 125.0 - 100.0 MHz SYSTEM T I/O setup time before p-term clock input 1.0 - 1.6 - 2.1 - ns PSU T I/O hold time after p-term clock input 2.6 - 3.2 - 4.4 - ns PH T P-term clock output valid - 6.8 - 7.7 - 10.2 ns PCO T GTS to output valid - 4.5 - 5.0 - 7.0 ns OE T GTS to output disable - 4.5 - 5.0 - 7.0 ns OD T Product term OE to output enabled - 8.4 - 9.5 - 11.0 ns POE T Product term OE to output disabled - 8.4 - 9.5 - 11.0 ns POD T GSR to output valid - 10.8 - 12.0 - 14.5 ns AO T P-term S/R to output valid - 11.8 - 12.6 - 15.3 ns PAO T GCK pulse width (High or Low) 2.4 - 4.0 - 4.5 - ns WLH T Asynchronous preset/reset pulse width 6.0 - 6.5 - 7.0 - ns APRPW (High or Low) T P-term clock pulse width (High or Low) 6.0 - 6.5 - 7.0 - ns PLH VTEST R1 Output Type VCCIO VTEST R1 R2 CL Device Output 3.3V 3.3V 320 Ω 360 Ω 35 pF 2.5V 2.5V 250 Ω 660 Ω 35 pF R2 CL DS058_03_081500 Figure 3: AC Load Circuit DS055 (v2.1 April 3, 2007 www.xilinx.com 5 Product Specification 1-800-255-7778

XC95288XL High Performance CPLD R Internal Timing Parameters XC95288XL-6 XC95288XL-7 XC95288XL-10 Symbol Parameter Min Max Min Max Min Max Units Buffer Delays T Input buffer delay - 2.2 - 2.3 - 3.5 ns IN T GCK buffer delay - 1.2 - 1.5 - 1.8 ns GCK T GSR buffer delay - 2.2 - 3.1 - 4.5 ns GSR T GTS buffer delay - 4.5 - 5.0 - 7.0 ns GTS T Output buffer delay - 2.4 - 2.5 - 3.0 ns OUT T Output buffer enable/disable - 0 - 0 - 0 ns EN delay Product Term Control Delays T Product term clock delay - 2.0 - 2.4 - 2.7 ns PTCK T Product term set/reset delay - 1.0 - 1.4 - 1.8 ns PTSR T Product term 3-state delay - 6.2 - 7.2 - 7.5 ns PTTS Internal Register and Combinatorial Delays T Combinatorial logic propagation delay - 0.4 - 1.3 - 1.7 ns PDI T Register setup time 2.0 - 2.6 - 3.0 - ns SUI T Register hold time 1.6 - 2.2 - 3.5 - ns HI T Register clock enable setup time 2.0 - 2.6 - 3.0 - ns ECSU T Register clock enable hold time 1.6 - 2.2 - 3.5 - ns ECHO T Register clock to output valid time - 0.2 - 0.5 - 1.0 ns COI T Register async. S/R to output delay - 6.2 - 6.4 - 7.0 ns AOI T Register async. S/R recover before clock 6.0 7.5 10.0 ns RAI T Internal logic delay - 1.0 - 1.4 - 1.8 ns LOGI T Internal low power logic delay - 5.5 - 6.4 - 7.3 ns LOGILP Feedback Delays T Fast CONNECT II feedback delay - 1.6 - 3.5 - 4.2 ns F Time Adders T Incremental product term allocator delay - 0.8 - 0.8 - 1.0 ns PTA (first incremental delay) T Incremental product term allocator delay - 0.3 - 0.3 - 0.4 ns PTA2 (subsequent incremental delay) T Slew-rate limited delay - 3.5 - 4.0 - 4.5 ns SLEW 6 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification

R XC95288XL High Performance CPLD XC95288XL I/O Pins (2) Func- Func- tion Macro BScan tion Macro BScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Block cell TQ144 PQ208 BG256 FG256 CS280 Order 1 1 – – – – – 861 3 1 – – – – – 753 1 2 – 28 L1 H1 K2 858 3 2 28 38 P1 L2 N2 750 1 3 – 29 L2 H5 K3 855 3 3 – 39 R1 L5 P1 747 1 4 – – – – – 852 3 4 – – – – – 744 1 5 20 30 L3 J1 K4 849 3 5 – 40 P3 M1 P2 741 1 6 21 31 L4 J5 L1 846 3 6 – 41 R2 L4 P3 738 1 7 – – – – – 843 3 7 – – – – – 735 1 8 22 32 M1 J2 L2 840 3 8 – 43 P4 N1 P4 732 1 9 – – M2 J3 L3 837 3 9 – – R3 L3 R1 729 1 10 23 33 M3 K1 L4 834 3 10 30(1) 44(1) T2(1) M2(1) R3(1) 726 1 11 – – M4 J4 M1 831 3 11 – – U1 M4 R2 723 1 12 24 34 N1 K2 M2 828 3 12 31 45 T3 P1 R4 720 1 13 – – – – – 825 3 13 – – – – – 717 1 14 25 35 N2 K5 M3 822 3 14 32(1) 46(1) U2(1) M3(1) T1(1) 714 1 15 26 36 N3 L1 M4 819 3 15 33 47 V1 N2 T2 711 1 16 – – – – – 816 3 16 – – – – – 708 1 17 27 37 N4 K3 N1 813 3 17 – 48 T4 N4 T3 705 1 18 – – – – – 810 3 18 – – – – – 702 2 1 – – – – – 807 4 1 – – – – – 699 2 2 9 15 G2 D1 G3 804 4 2 2(1) 3(1) C2(1) D3(1) C2(1) 696 2 3 10 16 G1 G4 G2 801 4 3 – 4 D2 D2 B1 693 2 4 – – – – – 798 4 4 – – – – – 690 2 5 11 17 H4 E1 G1 795 4 5 3(1) 5(1) D3(1) E3(1) C1(1) 687 2 6 12 18 H3 G3 G4 792 4 6 4 6 E4 C2 D4 684 2 7 – – – – – 789 4 7 – – – – – 681 2 8 13 19 H2 G2 H1 786 4 8 5(1) 7(1) C1(1) D4(1) D3(1) 678 2 9 – – H1 F5 H3 783 4 9 – – D1 B1 D2 675 2 10 14 20 J4 F1 H2 780 4 10 – 8 E3 E4 D1 672 2 11 – – J3 G5 H4 777 4 11 – – E2 C1 E3 669 2 12 15 21 J2 H2 J1 774 4 12 6(1) 9(1) E1(1) E5(1) E2(1) 666 2 13 – – – – – 771 4 13 – – – – – 663 2 14 16 22 J1 H4 J2 768 4 14 7 10 F3 E2 E4 660 2 15 17 23 K2 G1 J3 765 4 15 – 12 F2 F2 F3 657 2 16 – – – – – 762 4 16 – – – – – 654 2 17 19 25 K1 H3 J4 759 4 17 – 14 G3 E6 F4 651 2 18 – – – – – 756 4 18 – – – – – 648 Notes: 1. Global control pin. 2. The pin-outs are the same for Pb-free versions of packages. DS055 (v2.1 April 3, 2007 www.xilinx.com 7 Product Specification 1-800-255-7778

XC95288XL High Performance CPLD R XC95288XL I/O Pins (Continued)(2) Func- Func- tion Macro BScan tion Macro BScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Block cell TQ144 PQ208 BG256 FG256 CS280 Order 5 1 – – – – – 645 7 1 – – – – – 537 5 2 34 49 U3 R1 U1 642 7 2 – 62 W6 R3 W5 534 5 3 – 50 V2 N3 V1 639 7 3 45 63 Y6 M6 U6 531 5 4 – – – – – 636 7 4 – – – – – 528 5 5 35 51 V3 P2 U2 633 7 5 46 64 V7 T3 V6 525 5 6 – 54 Y2 P4 V3 630 7 6 – 66 U8 T4 W6 522 5 7 – – – – – 627 7 7 – – – – – 519 5 8 38(1) 55(1) W4(1) P5(1) W2(1) 624 7 8 – 67 W7 P7 U7 516 5 9 – – V4 T2 W3 621 7 9 – – Y7 T5 V7 513 5 10 39 56 U5 N5 T4 618 7 10 – 69 V8 N7 W7 510 5 11 – – Y3 R4 U4 615 7 11 – – W8 R7 T7 507 5 12 40 57 Y4 M5 V4 612 7 12 48 70 Y8 M7 W8 504 5 13 – – – – – 609 7 13 – – – – – 501 5 14 41 58 V5 R5 W4 606 7 14 – 71 U9 T6 U8 498 5 15 43 60 V6 R6 V5 603 7 15 49 72 V9 N8 V8 495 5 16 – – – – – 600 7 16 – – – – – 492 5 17 44 61 U7 N6 T5 597 7 17 – 73 W9 T7 T8 489 5 18 – – – – – 594 7 18 – – – – – 486 6 1 – – – – – 591 8 1 - – – – – 483 6 2 135 197 D7 A5 D7 588 8 2 130 186 A9 E11 B10 480 6 3 136 198 C6 D6 A6 585 8 3 131 187 B9 A8 C10 477 6 4 – – – – – 582 8 4 – – – – – 474 6 5 137 199 B5 B5 B6 579 8 5 132 188 C9 C8 D10 471 6 6 138 200 A4 C6 C6 576 8 6 – 189 D9 B8 A9 468 6 7 – – – – – 573 8 7 – – – – – 465 6 8 139 201 C5 A4 D6 570 8 8 133 191 A8 D8 B9 462 6 9 – – B4 E7 A5 567 8 9 – – B8 A7 C9 459 6 10 140 202 A3 A3 C5 564 8 10 134 192 C8 E9 D9 456 6 11 – – D5 C5 B5 561 8 11 – – D8 B7 A8 453 6 12 – 203 C4 A2 D5 558 8 12 – 193 A7 D7 B8 450 6 13 – – – – – 555 8 13 – – – – – 447 6 14 142 205 B2 B4 B4 552 8 14 – 194 B7 A6 C8 444 6 15 143(1) 206(1) A2(1) C4(1) C4(1) 549 8 15 – 195 B6 B6 B7 441 6 16 – – – – – 546 8 16 – – – – – 438 6 17 – 208 C3 B3 A3 543 8 17 – 196 A5 E8 C7 435 6 18 – – – – – 540 8 18 – – – – – 432 Notes: 1. Global control pin. 2. The pin-outs are the same for Pb-free versions of packages. 8 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification

R XC95288XL High Performance CPLD XC95288XL I/O Pins (Continued)(2) Func- Func- tion Macro BScan tion Macro BScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Block cell TQ144 PQ208 BG256 FG256 CS280 Order 9 1 – – – – – 429 11 1 – – – – – 321 9 2 50 74 Y11 R8 U9 426 11 2 – 87 Y15 P10 W13 318 9 3 51 75 W11 P8 T9 423 11 3 60 88 V14 T12 V13 315 9 4 – – – – – 420 11 4 – – – – – 312 9 5 52 76 V11 T8 W10 417 11 5 61 89 W15 N10 U13 309 9 6 53 77 U11 M8 V10 414 11 6 – 90 Y16 T13 T13 306 9 7 – – – – – 411 11 7 – – – – – 303 9 8 54 78 Y12 T9 U10 408 11 8 – 91 U14 M11 W14 300 9 9 – – W12 P9 W11 405 11 9 – – Y17 N11 T14 297 9 10 – 80 V12 R9 V11 402 11 10 64 95 V16 T14 W15 294 9 11 56 82 U12 M9 U11 399 11 11 66 97 Y18 R12 V15 291 9 12 57 83 Y13 T10 T11 396 11 12 68 99 V17 T15 W16 288 9 13 – – – – – 393 11 13 – – – – – 285 9 14 58 84 W13 M10 W12 390 11 14 69 100 Y19 R14 U16 282 9 15 – 85 V13 R10 V12 387 11 15 – 101 V18 N13 W17 279 9 16 – – – – – 384 11 16 – – – – – 276 9 17 59 86 W14 T11 T12 381 11 17 70 102 W19 R13 W18 273 9 18 – – – – – 378 11 18 – – – – – 270 10 1 – – – – – 375 12 1 – – – – – 267 10 2 117 170 A14 B11 C14 372 12 2 110 158 B18 B13 B19 264 10 3 118 171 C13 D11 B14 369 12 3 111 159 C17 B14 B18 261 10 4 – – – – – 366 12 4 – – – – – 258 10 5 119 173 B13 A11 A14 363 12 5 112 160 D16 C13 B17 255 10 6 120 174 A13 D10 C13 360 12 6 – 161 A18 A15 A18 252 10 7 – – – – – 357 12 7 – – – – – 249 10 8 121 175 D12 B10 B13 354 12 8 113 162 A17 C12 A17 246 10 9 – – C12 E12 A13 351 12 9 – – C16 B12 D16 243 10 10 124 178 A12 F12 A12 348 12 10 115 164 A16 D13 C16 240 10 11 125 179 B11 B9 C12 345 12 11 – 165 C15 A14 B16 237 10 12 126 180 C11 C9 B12 342 12 12 116 166 D14 E13 A16 234 10 13 – – – – – 339 12 13 – – – – – 231 10 14 128 182 B10 A9 B11 336 12 14 – 167 B15 A13 C15 228 10 15 – 183 C10 D9 C11 333 12 15 – 168 A15 C11 B15 225 10 16 – – – – – 330 12 16 – – – – – 222 10 17 129 185 D10 E10 A10 327 12 17 – 169 C14 A12 D15 219 10 18 – – – – – 324 12 18 – – – – – 216 Notes: 1. Global control pin. 2. The pin-outs are the same for Pb-free versions of packages. DS055 (v2.1 April 3, 2007 www.xilinx.com 9 Product Specification 1-800-255-7778

XC95288XL High Performance CPLD R XC95288XL I/O Pins (Continued)(2) Func- Func- tion Macro BScan tion Macro BScan Block cell TQ144 PQ208 BG256 FG256 CS280 Order Block cell TQ144 PQ208 BG256 FG256 CS280 Order 13 1 – – – – – 213 15 1 – – – – – 105 13 2 71 103 Y20 P13 V17 210 15 2 79 117 P19 M12 P16 102 13 3 – 106 V19 P15 U18 207 15 3 80 118 P20 M16 P19 99 13 4 – – – – – 204 15 4 – – – – – 96 13 5 – 107 U19 N14 V19 201 15 5 – 119 N17 K14 N17 93 13 6 – 109 T17 R16 U19 198 15 6 – 120 N18 L16 N18 90 13 7 – – – – – 195 15 7 – – – – – 87 13 8 74 110 V20 N15 T16 192 15 8 81 121 N19 K13 N19 84 13 9 – – U20 M15 T17 189 15 9 – – N20 K15 N16 81 13 10 – 111 T18 M13 T18 186 15 10 82 122 M17 L12 M19 78 13 11 75 112 T19 P16 T19 183 15 11 83 123 M18 K16 M17 75 13 12 – 113 R18 N16 R18 180 15 12 85 125 M20 J14 M16 72 13 13 – – – – – 177 15 13 – – – – – 69 13 14 76 114 P17 M14 R16 174 15 14 86 126 L19 J15 L19 66 13 15 77 115 R20 L15 R19 171 15 15 87 127 L18 J13 L18 63 13 16 – – – – – 168 15 16 – – – – – 60 13 17 78 116 P18 L13 P17 165 15 17 88 128 L20 J16 L17 57 13 18 – – – – – 162 15 18 – – – – – 54 14 1 – – – – – 159 16 1 – – – – – 51 14 2 – 144 G19 F15 G19 156 16 2 91 131 K19 K12 L16 48 14 3 100 145 F19 E15 G16 153 16 3 92 133 K18 J12 K18 45 14 4 – – – – – 150 16 4 – – – – – 42 14 5 101 146 E20 F13 F19 147 16 5 93 134 K17 H15 K17 39 14 6 102 147 G17 D16 F18 144 16 6 94 135 J20 H14 K16 36 14 7 – – – – – 141 16 7 – – – – – 33 14 8 103 148 F18 F14 F17 138 16 8 95 136 J19 G16 J19 30 14 9 – – E19 C16 F16 135 16 9 – – J18 H13 J18 27 14 10 104 149 D20 E14 E19 132 16 10 96 137 J17 G15 J17 24 14 11 105 150 E18 D15 E17 129 16 11 97 138 H20 H16 J16 21 14 12 – 151 D19 G12 E18 126 16 12 98 139 H19 F16 H19 18 14 13 – – – – – 123 16 13 – – – – – 15 14 14 106 152 C20 C15 E16 120 16 14 – 140 H18 H12 H18 12 14 15 107 154 D18 D14 D18 117 16 15 – 142 H17 E16 H17 9 14 16 – – – – – 114 16 16 – – – – – 6 14 17 – 155 C18 B16 D17 111 16 17 – 143 G20 G14 H16 3 14 18 – – – – – 108 16 18 – – – – – 0 Notes: 1. Global control pin. 2. The pin-outs are the same for Pb-free versions of packages. 10 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification

R XC95288XL High Performance CPLD XC95288XL Global, JTAG and Power Pins(1) Pin Type TQ144 PQ208 BG256 FG256 CS280 I/O/GCK1 30 44 T2 M2 R3 I/O/GCK2 32 46 U2 M3 T1 I/O/GCK3 38 55 W4 P5 W2 I/O/GTS1 5 7 C1 D4 D3 I/O/GTS2 6 9 E1 E5 E2 I/O/GTS3 2 3 C2 D3 C2 I/O/GTS4 3 5 D3 E3 C1 I/O/GSR 143 206 A2 C4 C4 TCK 67 98 U16 P12 T15 TDI 63 94 W16 R11 U14 TDO 122 176 B12 A10 D13 TMS 65 96 W17 N12 U15 V 3.3V 8, 42, 84, 141 11, 59, 124, 153, F1, P2, W5, Y9, F4, F7, G6, H6, J6, E1, F2, N3, U5, W9, CCINT 204 V10, U13, W18, K6, L7, F8, L8, F9, V9, U12, V16, R17, T20, M19, F20, E17, L9, F10, L10, G11, M18, G18, D19, B17, B14, A10, C7, H11, J11, K11 C18, A15, A11, D8, B3, G4 A4 V 2.5V/3.3 V 1, 37, 55, 73, 109, 1, 26, 53, 65, 79, D4, D6, D11, D15, F3, K4, D5, F6, L6, C3, F1, K1, N4, V2 CCIO 127 92, 105, 132, 157, D17, F4, F17, K4, P6, C7, N9, C10, T6, T10, V14, V18, 172, 181, 184 L17, R4, R17, U4, F11, L11, P11, D12, P18, K19, G17, U6, U10, U15, U17 G13, L14 C19, D14, D12, D11, A7 GND 18, 29, 36, 47, 62, 2, 13, 24, 27, 42, B1, K3, T1, Y5, A1, A16, C14, T1, E5, F5, G5, H5, J5, 72, 89, 90, 99, 52, 68, 81, 93, W10, Y10, Y14, B2, B15, R2, C3, K5, L5, M5, N5, R5, 108, 114, 123, 104,1 08, 129, V15, U18, R19, K20, P3, G7, H7, J7, K7, R6, R7, R8, R9 R10, 144 130, 141, 156, G18, B16, D13, A11, G8, H8, J8, K8, G9, R11, R12, R13, R14, 163, 177, 190, A6, J9, J10, J11, H9, J9, K9, G10, R15, P15, N15, 207 J12, K9, K10, K11, H10, J10, K10, P14, M15, L15, K15, J15, K12, L9, L10, L11, R15, T16 H15, G15, F15, E15, L12, M9, M10, M11, E14, E13, E12, E11, M12 E10, E9, E8, E7, E6, P5 No Connects – – A1, A19, A20, B19, - A1, B2, W1, U3, B20, C19, W1, W2, W19, U17, A19, W3, W20, Y1 C17, A2, B3 Notes: 1. The pin-outs are the same for Pb-free versions of packages. DS055 (v2.1 April 3, 2007 www.xilinx.com 11 Product Specification 1-800-255-7778

XC95288XL High Performance CPLD R Device Part Marking and Ordering Combination Information R Device Type XC95xxxXL Package TQ144 This line not Speed 7C related to device part number Operating Range 1 Sample package with part marking. Speed Device Ordering and (pin-to-pin Pkg. No. of Operating Part Marking Number delay) Symbol Pins Package Type Range(1) XC95288XL-6TQ144C 6 ns TQ144 144-pin Thin Quad Flat Pack C XC95288XL-6PQ208C 6 ns PQ208 208-pin Plastic Quad Flat Package C XC95288XL-6BG256C 6 ns BG256 256-ball Plastic Ball Grid Array C XC95288XL-6FG256C 6 ns FG256 256-ball Plastic Fineline Ball Grid Array C XC95288XL-6CS280C 6 ns CS280 280-ball Chipscale Package C XC95288XL-7TQ144C 7.5 ns TQ144 144-pin Thin Quad Flat Pack C XC95288XL-7PQ208C 7.5 ns PQ208 208-pin Plastic Quad Flat Package C XC95288XL-7BG256C 7.5 ns BG256 256-ball Plastic Ball Grid Array C XC95288XL-7FG256C 7.5 ns FG256 256-ball Plastic Fineline Ball Grid Array C XC95288XL-7CS280C 7.5 ns CS280 280-pin Chipscale Package C XC95288XL-7TQ144I 7.5 ns TQ144 144-pin Thin Quad Flat Pack I XC95288XL-7PQ208I 7.5 ns PQ208 208-pin Plastic Quad Flat Package I XC95288XL-7BG256I 7.5 ns BG256 256-ball Plastic Ball Grid Array I XC95288XL-7FG256I 7.5 ns FG256 256-ball Plastic Fineline Ball Grid Array I XC95288XL-7CS280I 7.5 ns CS280 280-pin Chipscale Package I XC95288XL-10TQ144C 10 ns TQ144 144-pin Thin Quad Flat Pack C XC95288XL-10PQ208C 10 ns PQ208 208-pin Plastic Quad Flat Package C XC95288XL-10BG256C 10 ns BG256 256-ball Plastic Ball Grid Array C XC95288XL-10FG256C 10 ns FG256 256-ball Plastic Fineline Ball Grid Array C XC95288XL-10CS280C 10 ns CS280 280-ball Chipscale Package C XC95288XL-10TQ144I 10 ns TQ144 144-pin Thin Quad Flat Pack I XC95288XL-10PQ208I 10 ns PQ208 208-pin Plastic Quad Flat Package I XC95288XL-10BG256I 10 ns BG256 256-ball Plastic Ball Grid Array I XC95288XL-10FG256I 10 ns FG256 256-ball Plastic Fineline Ball Grid Array I XC95288XL-10CS280I 10 ns CS280 280-ball Chipscale Package I XC95288XL-6TQG144C 6 ns TQG144 144-pin Thin Quad Flat Pack; Pb-free C 12 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification

R XC95288XL High Performance CPLD Speed Device Ordering and (pin-to-pin Pkg. No. of Operating Part Marking Number delay) Symbol Pins Package Type Range(1) XC95288XL-6PQG208C 6 ns PQG208 208-pin Plastic Quad Flat Package; Pb-free C XC95288XL-6BGG256C 6 ns BGG256 256-ball Plastic Ball Grid Array; Pb-free C XC95288XL-6FGG256C 6 ns FGG256 256-ball Plastic Fineline Ball Grid Array; Pb-free C XC95288XL-6CSG280C 6 ns CSG280 280-ball Chipscale Package; Pb-free C XC95288XL-7TQG144C 7.5 ns TQG144 144-pin Thin Quad Flat Pack; Pb-free C XC95288XL-7PQG208C 7.5 ns PQG208 208-pin Plastic Quad Flat Package; Pb-free C XC95288XL-7BGG256C 7.5 ns BGG256 256-ball Plastic Ball Grid Array; Pb-free C XC95288XL-7FGG256C 7.5 ns FGG256 256-ball Plastic Fineline Ball Grid Array; Pb-free C XC95288XL-7CSG280C 7.5 ns CSG280 280-pin Chipscale Package; Pb-free C XC95288XL-7TQG144I 7.5 ns TQG144 144-pin Thin Quad Flat Pack; Pb-free I XC95288XL-7PQG208I 7.5 ns PQG208 208-pin Plastic Quad Flat Package; Pb-free I XC95288XL-7BGG256I 7.5 ns BGG256 256-ball Plastic Ball Grid Array; Pb-free I XC95288XL-7FGG256I 7.5 ns FGG256 256-ball Plastic Fineline Ball Grid Array; Pb-free I XC95288XL-7CSG280I 7.5 ns CSG280 280-pin Chipscale Package; Pb-free I XC95288XL-10TQG144C 10 ns TQG144 144-pin Thin Quad Flat Pack; Pb-free C XC95288XL-10PQG208C 10 ns PQG208 208-pin Plastic Quad Flat Package; Pb-free C XC95288XL-10BGG256C 10 ns BGG256 256-ball Plastic Ball Grid Array; Pb-free C XC95288XL-10FGG256C 10 ns FGG256 256-ball Plastic Fineline Ball Grid Array; Pb-free C XC95288XL-10CSG280C 10 ns CSG280 280-ball Chipscale Package; Pb-free C XC95288XL-10TQG144I 10 ns TQG144 144-pin Thin Quad Flat Pack; Pb-free I XC95288XL-10PQG208I 10 ns PQG208 208-pin Plastic Quad Flat Package; Pb-free I XC95288XL-10BGG256I 10 ns BGG256 256-ball Plastic Ball Grid Array; Pb-free I XC95288XL-10FGG256I 10 ns FGG256 256-ball Plastic Fineline Ball Grid Array; Pb-free I XC95288XL-10CSG280I 10 ns CSG280 280-ball Chipscale Package; Pb-free I Notes: 1. C = Commercial: T = 0° to +70°C; I = Industrial: T = –40° to +85°C A A Standard Example: X C 9 5 2 88XL -4 TQ 144 C Pb-Free Example: X C 9 5 2 8 8XL -4 TQ G 144 C Device Device Speed Grade Speed Grade Package Type Package Type Number of Pins Pb-Free Temperature Range Number of Pins Temperature Range DS055 (v2.1 April 3, 2007 www.xilinx.com 13 Product Specification 1-800-255-7778

XC95288XL High Performance CPLD R Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Further Reading The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down. Data Sheets, Application Notes, and White Papers. Packaging Revision History The following table shows the revision history for this document. Date Version Revision 09/28/98 1.0 Initial Xilinx release. 02/05/99 1.1 Updated pinouts to reflect BG256 (replaces BG352). 06/07/99 1.2 Added -7 speed and CS280 package. 02/08/01 1.3 Updated -6 AC and timing parameters, added FG256 package. 03/19/01 1.4 Pinout corrections. 06/20/02 1.5 Updated I equation, page 1. Updated Component Availability Chart: added -7 Industrial. CC Added additional I test conditions and measurements to DC Characteristics table. IH 05/27/03 1.6 Updated T from 260 to 220oC. Added Part Marking and Updated Ordering Information. SOL 08/21/03 1.7 Updated Package Device Marking Pin 1 orientation. 07/15/04 1.8 Added Pb-free documentation 09/15/04 1.9 Added T specification to AC Characteristics. APRPW 03/22/06 2.0 Add Warranty Disclaimer. 04/03/07 2.1 Add programming temperature range warning on page 1. 14 www.xilinx.com DS055 (v2.1 April 3, 2007 1-800-255-7778 Product Specification