Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16.1) August 7, 2018 Product Specification Introduction Kintex®-7 FPGAs are available in -3, -2, -1, -1L, and -2L unless otherwise noted, all the DC and AC electrical speed grades, with -3 having the highest performance. The parameters are the same for a particular speed grade (that -2L devices are screened for lower maximum static power is, the timing characteristics of a -1 speed grade military and can operate at lower core voltages for lower dynamic temperature device are the same as for a -1 speed grade power than the -2 devices. The -2L industrial (I) temperature commercial temperature device). However, only selected devices operate only at V =0.95V. The -2L extended (E) speed grades and/or devices are available in each CCINT temperature devices can operate at either V =0.9V or temperature range. CCINT 1.0V. The -2LE devices when operated at V =1.0V, and CCINT All supply voltage and junction temperature specifications the -2LI devices when operated at V =0.95V, have the CCINT are representative of worst-case conditions. The parameters same speed specifications as the -2 speed grade, except included are common to popular designs and typical where noted. When the -2LE devices are operated at applications. V =0.9V, the speed specifications, static power, and CCINT dynamic power are reduced. The -1L military (M) Available device and package combinations can be found in: temperature devices have the same speed specifications as • 7Series FPGAs Overview (DS180) the -1 military temperature devices and are screened for lower maximum static power. • Defense-Grade 7Series FPGAs Overview (DS185) Kintex-7 FPGA DC and AC characteristics are specified in This Kintex-7 FPGA data sheet, part of an overall set of commercial, extended, industrial, and military temperature documentation on the 7series FPGAs, is available on the ranges. Except for the operating temperature range or Xilinx website at www.xilinx.com/documentation. DC Characteristics Table 1: Absolute Maximum Ratings(1) Symbol Description Min Max Units FPGA Logic V Internal supply voltage –0.5 1.1 V CCINT V Auxiliary supply voltage –0.5 2.0 V CCAUX V Supply voltage for the block RAM memories –0.5 1.1 V CCBRAM Output drivers supply voltage for HR I/O banks –0.5 3.6 V V CCO Output drivers supply voltage for HP I/O banks –0.5 2.0 V V Auxiliary supply voltage –0.5 2.06 V CCAUX_IO V Input reference voltage –0.5 2.0 V REF I/O input voltage for HR I/O banks –0.40 V +0.55 V CCO I/O input voltage for HP I/O banks –0.55 V +0.55 V V (2)(3)(4) CCO IN I/O input voltage (when V =3.3V) for V and differential I/O standards except –0.40 2.625 V CCO REF TMDS_33(5) V Key memory battery backup supply –0.5 2.0 V CCBATT © 2011–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 1

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units GTX Transceiver V Analog supply voltage for the GTX transmitter and receiver circuits –0.5 1.1 V MGTAVCC V Analog supply voltage for the GTX transmitter and receiver termination circuits –0.5 1.32 V MGTAVTT V Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers –0.5 1.935 V MGTVCCAUX V GTX transceiver reference clock absolute input voltage –0.5 1.32 V MGTREFCLK Analog supply voltage for the resistor calibration circuit of the GTX transceiver –0.5 1.32 V V MGTAVTTRCAL column V Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V IN I DC input current for receiver input pins DC coupled RX termination=floating – 14 mA DCIN-FLOAT I DC input current for receiver input pins DC coupled RX termination=V – 12 mA DCIN-MGTAVTT MGTAVTT I DC input current for receiver input pins DC coupled RX termination=GND – 6.5 mA DCIN-GND I DC output current for transmitter pins DC coupled RX termination=floating – 14 mA DCOUT-FLOAT I DC output current for transmitter pins DC coupled RX termination=V – 12 mA DCOUT-MGTAVTT MGTAVTT XADC V XADC supply relative to GNDADC –0.5 2.0 V CCADC V XADC reference input relative to GNDADC –0.5 2.0 V REFP Temperature T Storage temperature (ambient) –65 150 °C STG Maximum soldering temperature for Pb/Sn component bodies (6) – +220 °C T SOL Maximum soldering temperature for Pb-free component bodies (6) – +260 °C T Maximum junction temperature(6) – +125 °C j Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. The lower absolute voltage specification always applies. 3. For I/O operation, refer to the 7Series FPGAs SelectIO Resources User Guide (UG471). 4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table4 and Table5. 5. See Table10 for TMDS_33 specifications. 6. For soldering guidelines and thermal considerations, see the 7Series FPGA Packaging and Pinout Specification (UG475). Table 2: Recommended Operating Conditions(1)(2) Symbol Description Min Typ Max Units FPGA Logic For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: internal supply voltage 0.97 1.00 1.03 V V (3) For -2LE (0.9V) devices: internal supply voltage 0.87 0.90 0.93 V CCINT For -2LI (0.95V) devices: internal supply voltage 0.93 0.95 0.97 V For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: block RAM supply voltage 0.97 1.00 1.03 V V (3) For -2LE (0.9V) devices: block RAM supply voltage 0.87 0.90 1.03 V CCBRAM For -2LI (0.95V) devices: block RAM supply voltage 0.93 0.95 0.97 V V Auxiliary supply voltage 1.71 1.80 1.89 V CCAUX Supply voltage for HR I/O banks 1.14 – 3.465 V V (4)(5) CCO Supply voltage for HP I/O banks 1.14 – 1.89 V DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 2

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 2: Recommended Operating Conditions(1)(2) (Cont’d) Symbol Description Min Typ Max Units Auxiliary supply voltage when set to 1.8V 1.71 1.80 1.89 V V (6) CCAUX_IO Auxiliary supply voltage when set to 2.0V 1.94 2.00 2.06 V I/O input voltage –0.20 – V +0.2 V CCO VIN(7) I/O input voltage (when VCCO=3.3V) for VREF and differential I/O –0.20 – 2.625 V standards except TMDS_33(8) Maximum current through any pin in a powered or unpowered bank when – – 10 mA I (9) IN forward biasing the clamp diode. V (10) Battery voltage 1.0 – 1.89 V CCBATT GTX Transceiver Analog supply voltage for the GTX transceiver QPLL frequency range 0.97 1.0 1.08 V ≤10.3125GHz(12)(13) V (11) MGTAVCC Analog supply voltage for the GTX transceiver QPLL frequency range 1.02 1.05 1.08 V >10.3125GHz Analog supply voltage for the GTX transmitter and receiver termination V (11) 1.17 1.2 1.23 V MGTAVTT circuits V (11) Auxiliary analog QPLL voltage supply for the transceivers 1.75 1.80 1.85 V MGTVCCAUX Analog supply voltage for the resistor calibration circuit of the GTX V (11) 1.17 1.2 1.23 V MGTAVTTRCAL transceiver column XADC V XADC supply relative to GNDADC 1.71 1.80 1.89 V CCADC V Externally supplied reference voltage 1.20 1.25 1.30 V REFP Temperature Junction temperature operating range for commercial (C) temperature 0 – 85 °C devices Junction temperature operating range for extended (E) temperature 0 – 100 °C Tj devices Junction temperature operating range for industrial (I) temperature devices –40 – 100 °C Junction temperature operating range for military (M) temperature devices –55 – 125 °C Notes: 1. All voltages are relative to ground. 2. For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide (UG483). 3. V and V should be connected to the same supply. CCINT CCBRAM 4. Configuration data is retained even if V drops to 0V. CCO 5. Includes V of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), and 3.3V (HR I/O only) at ±5%. CCO 6. For more information, refer to the V section of 7Series FPGAs SelectIO Resources User Guide (UG471). CCAUX_IO 7. The lower absolute voltage specification always applies. 8. See Table10 for TMDS_33 specifications. 9. A total of 200mA per bank should not be exceeded. 10. V is required only when using bitstream encryption. If battery is not used, connect V to either ground or V . CCBATT CCBATT CCAUX 11. Each voltage listed requires the filter circuit described in the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476). 12. For data rates ≤10.3125Gb/s, V should be 1.0V ±3% for lower power consumption. MGTAVCC 13. For lower power consumption, V should be 1.0V ±3% over the entire CPLL frequency range. MGTAVCC DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 3

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units V Data retention V voltage (below which configuration data might be lost) 0.75 – – V DRINT CCINT V Data retention V voltage (below which configuration data might be lost) 1.5 – – V DRI CCAUX I V leakage current per pin – – 15 µA REF REF I Input or output leakage current per pin (sample-tested) – – 15 µA L C (2) Die input capacitance at the pad – – 8 pF IN Pad pull-up (when selected) @ V =0V, V =3.3V 90 – 330 µA IN CCO Pad pull-up (when selected) @ V =0V, V =2.5V 68 – 250 µA IN CCO I Pad pull-up (when selected) @ V =0V, V =1.8V 34 – 220 µA RPU IN CCO Pad pull-up (when selected) @ V =0V, V =1.5V 23 – 150 µA IN CCO Pad pull-up (when selected) @ V =0V, V =1.2V 12 – 120 µA IN CCO Pad pull-down (when selected) @ V =3.3V 68 – 330 µA IN I RPD Pad pull-down (when selected) @ V =1.8V 45 – 180 µA IN I Analog supply current, analog circuits in powered up state – – 25 mA CCADC I (3) Battery supply current – – 150 nA BATT Thevenin equivalent resistance of programmable input termination to V /2 28 40 55 Ω CCO (UNTUNED_SPLIT_40) Thevenin equivalent resistance of programmable input termination to V /2 35 50 65 Ω R (4) CCO IN_TERM (UNTUNED_SPLIT_50) Thevenin equivalent resistance of programmable input termination to V /2 44 60 83 Ω CCO (UNTUNED_SPLIT_60) n Temperature diode ideality factor – 1.010 – – r Temperature diode series resistance – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. This measurement represents the die capacitance at the pad, not including the package. 3. Maximum value specified for worst case process at 25°C. 4. Termination resistance to a V /2 level. CCO Table 4: V Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) IN AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C –0.40 100 –0.45 61.7 V +0.55 100 CCO –0.50 25.8 –0.55 11.0 V +0.60 46.6 –0.60 4.77 CCO V +0.65 21.2 –0.65 2.10 CCO V +0.70 9.75 –0.70 0.94 CCO V +0.75 4.55 –0.75 0.43 CCO V +0.80 2.15 –0.80 0.20 CCO V +0.85 1.02 –0.85 0.09 CCO V +0.90 0.49 –0.90 0.04 CCO DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 4

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 4: V Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) (Cont’d) IN AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C V +0.95 0.24 –0.95 0.02 CCO Notes: 1. A total of 200mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above V +0.20V or below GND–0.20V, must not exceed the values CCO in this table. Table 5: V Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2) IN AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C V +0.55 100 –0.55 100 CCO V +0.60 50.0(3) –0.60 50.0(3) CCO V +0.65 50.0(3) –0.65 50.0(3) CCO V +0.70 47.0 –0.70 50.0(3) CCO V +0.75 21.2 –0.75 50.0(3) CCO V +0.80 9.71 –0.80 50.0(3) CCO V +0.85 4.51 –0.85 28.4 CCO V +0.90 2.12 –0.90 12.7 CCO V +0.95 1.01 –0.95 5.79 CCO Notes: 1. A total of 200mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above V +0.20V or below GND–0.20V, must not exceed the values CCO in this table. 3. For UI lasting less than 20µs. Table 6: Typical Quiescent Supply Current Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1LM -1M -2LI -2LE I Quiescent V supply XC7K70T 241 241 241 N/A N/A N/A 187 mA CCINTQ CCINT current XC7K160T 474 474 474 N/A N/A 271 368 mA XC7K325T 810 810 810 N/A N/A 463 629 mA XC7K355T 993 993 993 N/A N/A 568 771 mA XC7K410T 1080 1080 1080 N/A N/A 618 838 mA XC7K420T 1313 1313 1313 N/A N/A 751 1019 mA XC7K480T 1313 1313 1313 N/A N/A 751 1019 mA XQ7K325T N/A 810 810 810 810 463 629 mA XQ7K410T N/A 1080 1080 N/A 1080 618 838 mA DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 5

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 6: Typical Quiescent Supply Current (Cont’d) Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1LM -1M -2LI -2LE I Quiescent V supply XC7K70T 1 1 1 N/A N/A N/A 1 mA CCOQ CCO current XC7K160T 1 1 1 N/A N/A 1 1 mA XC7K325T 1 1 1 N/A N/A 1 1 mA XC7K355T 1 1 1 N/A N/A 1 1 mA XC7K410T 1 1 1 N/A N/A 1 1 mA XC7K420T 1 1 1 N/A N/A 1 1 mA XC7K480T 1 1 1 N/A N/A 1 1 mA XQ7K325T N/A 1 1 1 1 1 1 mA XQ7K410T N/A 1 1 N/A 1 1 1 mA I Quiescent V supply XC7K70T 21 21 21 N/A N/A N/A 21 mA CCAUXQ CCAUX current XC7K160T 40 40 40 N/A N/A 36 40 mA XC7K325T 68 68 68 N/A N/A 61 68 mA XC7K355T 75 75 75 N/A N/A 67 75 mA XC7K410T 85 85 85 N/A N/A 76 85 mA XC7K420T 99 99 99 N/A N/A 89 99 mA XC7K480T 99 99 99 N/A N/A 89 99 mA XQ7K325T N/A 68 68 68 68 68 68 mA XQ7K410T N/A 85 85 N/A 85 85 85 mA I Quiescent V supply XC7K70T N/A N/A N/A N/A N/A N/A N/A mA CCAUX_IOQ CCAUX_IO current XC7K160T 2 2 2 N/A N/A 1 2 mA XC7K325T 2 2 2 N/A N/A 1 2 mA XC7K355T N/A N/A N/A N/A N/A N/A N/A mA XC7K410T 2 2 2 N/A N/A 1 2 mA XC7K420T N/A N/A N/A N/A N/A N/A N/A mA XC7K480T N/A N/A N/A N/A N/A N/A N/A mA XQ7K325T N/A 2 2 2 2 2 2 mA XQ7K410T N/A 2 2 N/A 2 2 2 mA DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 6

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 6: Typical Quiescent Supply Current (Cont’d) Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1LM -1M -2LI -2LE I Quiescent V supply XC7K70T 6 6 6 N/A N/A N/A 6 mA CCBRAMQ CCBRAM current XC7K160T 14 14 14 N/A N/A 8 14 mA XC7K325T 19 19 19 N/A N/A 10 19 mA XC7K355T 31 31 31 N/A N/A 17 31 mA XC7K410T 34 34 34 N/A N/A 19 34 mA XC7K420T 41 41 41 N/A N/A 23 41 mA XC7K480T 41 41 41 N/A N/A 23 41 mA XQ7K325T N/A 19 19 19 19 19 19 mA XQ7K410T N/A 34 34 N/A 34 34 34 mA Notes: 1. Typical values are specified at nominal voltage, 85°C junction temperatures (T) with single-ended SelectIO resources. j 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions other than those specified. Power-On/Off Power Supply Sequencing The recommended power-on sequence is V , V , V , V , and V to achieve minimum current draw CCINT CCBRAM CCAUX CCAUX_IO CCO and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If V and V have the same recommended voltage levels then both can be powered by the same supply CCINT CCBRAM and ramped simultaneously. If V , V , and V have the same recommended voltage levels then they can be CCAUX CCAUX_IO CCO powered by the same supply and ramped simultaneously. For V voltages of 3.3V in HR I/O banks and configuration bank 0: CCO • The voltage difference between V and V must not exceed 2.625V for longer than T for each CCO CCAUX VCCO2VCCAUX power-on/off cycle to maintain device reliability levels. • The T time can be allocated in any percentage between the power-on and power-off ramps. VCCO2VCCAUX The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is V , V , CCINT MGTAVCC V OR V , V , V . There is no recommended sequencing for V . Both V and V MGTAVTT MGTAVCC CCINT MGTAVTT MGTVCCAUX MGTAVCC CCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from V can be higher than specifications during power- MGTAVTT up and power-down. • When V is powered before V and V –V >150 mV and V <0.7V, the V MGTAVTT MGTAVCC MGTAVTT MGTAVCC MGTAVCC MGTAVTT current draw can increase by 460mA per transceiver during V ramp up. The duration of the current draw can be MGTAVCC up to 0.3xT (ramp time from GND to 90% of V ). The reverse is true for power-down. MGTAVCC MGTAVCC • When V is powered before V and V –V >150 mV and V <0.7V, the V current MGTAVTT CCINT MGTAVTT CCINT CCINT MGTAVTT draw can increase by 50mA per transceiver during V ramp up. The duration of the current draw can be up to CCINT 0.3xT (ramp time from GND to 90% of V ). The reverse is true for power-down. VCCINT CCINT There is no recommended sequence for supplies not shown. Table7 shows the minimum current, in addition to I , that are required by Kintex-7 devices for proper power-on and CCQ configuration. If the current minimums shown in Table6 and Table7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V is applied. CCINT DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 7

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate current drain on these supplies. Table 7: Power-On Current for Kintex-7 Devices Device I I I I I Units CCINTMIN CCAUXMIN CCOMIN CCAUX_IOMIN CCBRAMMIN XC7K70T I +450 I +40 I +40mA per bank I +40mA per bank I +40 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XC7K160T I +550 I +50 I +40mA per bank I +40mA per bank I +40 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XC7K325T I +600 I +80 I +40mA per bank I +40mA per bank I +40 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XC7K355T I +1450 I +109 I +40mA per bank I +40mA per bank I +81 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XC7K410T I +1500 I +125 I +40mA per bank I +40mA per bank I +90 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XC7K420T I +2200 I +180 I +40mA per bank I +40mA per bank I +108 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XC7K480T I +2200 I +180 I +40mA per bank I +40mA per bank I +108 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XQ7K325T I +600 I +80 I +40mA per bank I +40mA per bank I +40 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ XQ7K410T I +1500 I +125 I +40mA per bank I +40mA per bank I +90 mA CCINTQ CCAUXQ CCOQ CCOAUXIOQ CCBRAMQ Table 8: Power Supply Ramp Time Symbol Description Conditions Min Max Units T Ramp time from GND to 90% of V 0.2 50 ms VCCINT CCINT T Ramp time from GND to 90% of V 0.2 50 ms VCCO CCO T Ramp time from GND to 90% of V 0.2 50 ms VCCAUX CCAUX T Ramp time from GND to 90% of V 0.2 50 ms VCCAUX_IO CCAUX_IO T Ramp time from GND to 90% of V 0.2 50 ms VCCBRAM CCBRAM T = 125°C(1) – 300 J T Allowed time per power cycle for V – V > 2.625V T = 100°C(1) – 500 ms VCCO2VCCAUX CCO CCAUX J T = 85°C(1) – 800 J T Ramp time from GND to 90% of V 0.2 50 ms MGTAVCC MGTAVCC T Ramp time from GND to 90% of V 0.2 50 ms MGTAVTT MGTAVTT T Ramp time from GND to 90% of V 0.2 50 ms MGTVCCAUX MGTVCCAUX Notes: 1. Based on 240,000 power cycles with nominal V of 3.3V or 36,500 power cycles with a worst case V of 3.465V. CCO CCO DC Input and Output Levels Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended IL IH OL OH operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that all OL OH standards meet their specifications. The selected standards are tested at a minimum V with the respective V and V CCO OL OH voltage levels shown. Other standards are sample tested. Table 9: SelectIO DC Input and Output Levels(1)(2) V V V V I I IL IH OL OH OL OH I/O Standard V, Min V, Max V, Min V, Max V, Max V, Min mA mA HSTL_I –0.300 V –0.100 V +0.100 V +0.300 0.400 V –0.400 8 –8 REF REF CCO CCO HSTL_I_12 –0.300 V –0.080 V +0.080 V +0.300 25%V 75%V 6.3 –6.3 REF REF CCO CCO CCO HSTL_I_18 –0.300 V –0.100 V +0.100 V +0.300 0.400 V –0.400 8 –8 REF REF CCO CCO HSTL_II –0.300 V –0.100 V +0.100 V +0.300 0.400 V –0.400 16 –16 REF REF CCO CCO HSTL_II_18 –0.300 V –0.100 V +0.100 V +0.300 0.400 V –0.400 16 –16 REF REF CCO CCO DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 8

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 9: SelectIO DC Input and Output Levels(1)(2) (Cont’d) V V V V I I IL IH OL OH OL OH I/O Standard V, Min V, Max V, Min V, Max V, Max V, Min mA mA HSUL_12 –0.300 V –0.130 V +0.130 V +0.300 20%V 80%V 0.1 –0.1 REF REF CCO CCO CCO LVCMOS12 –0.300 35% V 65% V V +0.300 0.400 V –0.400 Note3 Note3 CCO CCO CCO CCO LVCMOS15, –0.300 35% V 65% V V +0.300 25%V 75%V Note4 Note4 CCO CCO CCO CCO CCO LVDCI_15 LVCMOS18, –0.300 35% V 65% V V +0.300 0.450 V –0.450 Note5 Note5 CCO CCO CCO CCO LVDCI_18 LVCMOS25 –0.300 0.700 1.700 V +0.300 0.400 V –0.400 Note6 Note6 CCO CCO LVCMOS33 –0.300 0.800 2.000 3.450 0.400 V –0.400 Note6 Note6 CCO LVTTL –0.300 0.800 2.000 3.450 0.400 2.400 Note7 Note7 MOBILE_DDR –0.300 20% V 80% V V +0.300 10%V 90%V 0.1 –0.1 CCO CCO CCO CCO CCO PCI33_3 –0.400 30% V 50% V V +0.500 10%V 90%V 1.5 –0.5 CCO CCO CCO CCO CCO SSTL12 –0.300 V –0.100 V +0.100 V +0.300 V /2–0.150 V /2+0.150 14.25 –14.25 REF REF CCO CCO CCO SSTL135 –0.300 V –0.090 V +0.090 V +0.300 V /2–0.150 V /2+0.150 13.0 –13.0 REF REF CCO CCO CCO SSTL135_R –0.300 V –0.090 V +0.090 V +0.300 V /2–0.150 V /2+0.150 8.9 –8.9 REF REF CCO CCO CCO SSTL15 –0.300 V –0.100 V +0.100 V +0.300 V /2–0.175 V /2+0.175 13.0 –13.0 REF REF CCO CCO CCO SSTL15_R –0.300 V –0.100 V +0.100 V +0.300 V /2–0.175 V /2+0.175 8.9 –8.9 REF REF CCO CCO CCO SSTL18_I –0.300 V –0.125 V +0.125 V +0.300 V /2–0.470 V /2+0.470 8 –8 REF REF CCO CCO CCO SSTL18_II –0.300 V –0.125 V +0.125 V +0.300 V /2–0.600 V /2+0.600 13.4 –13.4 REF REF CCO CCO CCO Notes: 1. Tested according to relevant specifications. 2. 3.3V and 2.5V standards are only supported in HR I/O banks. 3. Supported drive strengths of 2, 4, 6, or 8mA in HP I/O banks and 4, 8, or 12mA in HR I/O banks. 4. Supported drive strengths of 2, 4, 6, 8, 12, or 16mA in HP I/O banks and 4, 8, 12, or 16mA in HR I/O banks. 5. Supported drive strengths of 2, 4, 6, 8, 12, or 16mA in HP I/O banks and 4, 8, 12, 16, or 24mA in HR I/O banks. 6. Supported drive strengths of 4, 8, 12, or 16mA 7. Supported drive strengths of 4, 8, 12, 16, or 24mA 8. For detailed interface specific DC voltage levels, see the 7Series FPGAs SelectIO Resources User Guide (UG471). DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 9

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 10: Differential SelectIO DC Input and Output Levels V (1) V (2) V (3) V (4) ICM ID OCM OD I/O Standard V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max BLVDS_25 0.300 1.200 1.425 0.100 – – – 1.250 – Note5 MINI_LVDS_25 0.300 1.200 V 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 CCAUX PPDS_25 0.200 0.900 V 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 CCAUX RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600 TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 V –0.405 V –0.300 V –0.190 0.400 0.600 0.800 CCO CCO CCO Notes: 1. V is the input common mode voltage. ICM 2. V is the input differential voltage (Q–Q). ID 3. V is the output common mode voltage. OCM 4. V is the output differential voltage (Q–Q). OD 5. V for BLVDS will vary significantly depending on topology and loading. OD 6. LVDS_25 is specified in Table12. 7. LVDS is specified in Table13. Table 11: Complementary Differential SelectIO DC Input and Output Levels V (1) V (2) V (3) V (4) I I ICM ID OL OH OL OH I/O Standard V, Min V, Typ V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min DIFF_HSTL_I 0.300 0.750 1.125 0.100 – 0.400 V –0.400 8.00 –8.00 CCO DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 – 0.400 V –0.400 8.00 –8.00 CCO DIFF_HSTL_II 0.300 0.750 1.125 0.100 – 0.400 V –0.400 16.00 –16.00 CCO DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 – 0.400 V –0.400 16.00 –16.00 CCO DIFF_HSUL_12 0.300 0.600 0.850 0.100 – 20% V 80% V 0.100 –0.100 CCO CCO DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 – 10% V 90% V 0.100 –0.100 CCO CCO DIFF_SSTL12 0.300 0.600 0.850 0.100 – (V /2)–0.150 (V /2)+0.150 14.25 –14.25 CCO CCO DIFF_SSTL135 0.300 0.675 1.000 0.100 – (V /2)–0.150 (V /2)+0.150 13.0 –13.0 CCO CCO DIFF_SSTL135_R 0.300 0.675 1.000 0.100 – (V /2)–0.150 (V /2)+0.150 8.9 –8.9 CCO CCO DIFF_SSTL15 0.300 0.750 1.125 0.100 – (V /2)–0.175 (V /2)+0.175 13.0 –13.0 CCO CCO DIFF_SSTL15_R 0.300 0.750 1.125 0.100 – (V /2)–0.175 (V /2)+0.175 8.9 –8.9 CCO CCO DIFF_SSTL18_I 0.300 0.900 1.425 0.100 – (V /2)–0.470 (V /2)+0.470 8.00 –8.00 CCO CCO DIFF_SSTL18_II 0.300 0.900 1.425 0.100 – (V /2)–0.600 (V /2)+0.600 13.4 –13.4 CCO CCO Notes: 1. V is the input common mode voltage. ICM 2. V is the input differential voltage (Q–Q). ID 3. V is the single-ended low-output voltage. OL 4. V is the single-ended high-output voltage. OH DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 10

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics LVDS DC Specifications (LVDS_25) The LVDS_25 standard is available in the HR I/O banks. See the 7Series FPGAs SelectIO Resources User Guide (UG471) for more information. Table 12: LVDS_25 DC Specifications Symbol DC Parameter Conditions Min Typ Max Units V Supply Voltage 2.375 2.500 2.625 V CCO V Output High Voltage for Q and Q R = 100Ω across Q and Q signals – – 1.675 V OH T V Output Low Voltage for Q and Q R = 100Ω across Q and Q signals 0.700 – – V OL T Differential Output Voltage: R = 100Ω across Q and Q signals 247 350 600 mV T V (Q–Q), Q = High ODIFF (Q–Q), Q=High V Output Common-Mode Voltage R = 100Ω across Q and Q signals 1.000 1.250 1.425 V OCM T Differential Input Voltage: 100 350 600 mV V (Q–Q), Q = High IDIFF (Q–Q), Q=High V Input Common-Mode Voltage 0.300 1.200 1.500 V ICM Notes: 1. Differential inputs for LVDS_25 can be placed in banks with V levels that are different from the required level for outputs. Refer to the CCO 7Series FPGAs SelectIO Resources User Guide (UG471) for more information. LVDS DC Specifications (LVDS) The LVDS standard is available in the HP I/O banks. See the 7Series FPGAs SelectIO Resources User Guide (UG471) for more information. Table 13: LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units V Supply Voltage 1.710 1.800 1.890 V CCO V Output High Voltage for Q and Q R = 100Ω across Q and Q signals – – 1.675 V OH T V Output Low Voltage for Q and Q R = 100Ω across Q and Q signals 0.825 – – V OL T Differential Output Voltage: R = 100Ω across Q and Q signals 247 350 600 mV T V (Q–Q), Q = High ODIFF (Q–Q), Q=High V Output Common-Mode Voltage R = 100Ω across Q and Q signals 1.000 1.250 1.425 V OCM T Differential Input Voltage: Common-mode input voltage=1.25V 100 350 600 mV V (Q–Q), Q = High IDIFF (Q–Q), Q=High V Input Common-Mode Voltage Differential input voltage=±350mV 0.300 1.200 1.425 V ICM Notes: 1. Differential inputs for LVDS can be placed in banks with V levels that are different from the required level for outputs. Refer to the 7Series CCO FPGAs SelectIO Resources User Guide (UG471) for more information. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 11

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics AC Switching Characteristics All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite 2015.4 and ISE®software 14.7 as outlined in Table14. Table 14: Kintex-7 FPGA Speed Specification Version By Device Version In: Typical V CCINT Device ISE 14.7 Vivado 2015.4 (Table2) 1.10 1.12 1.0V XC7K70T(1), XC7K160T(1), XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T N/A 1.12 0.95V XC7K160T(1), XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T 1.09 1.09 0.9V XC7K70T, XC7K160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T 1.05 1.09 1.0V XQ7K325T, XQ7K410T 1.05 1.09 0.9V XQ7K325T, XQ7K410T Notes: 1. GTX data rates greater than 6.6Gb/s in the FBG484 package in the -3 and -2 speed grades require Vivado Design Suite 2017.1 or later. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance Product Specification These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary Product Specification These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Product Specification These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex-7 FPGAs. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 12

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Speed Grade Designations Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table15 correlates the current status of each Kintex-7 device on a per speed grade basis. Table 15: Kintex-7 Device Speed Grade Designations Speed Grade Designations Device Advance Preliminary Production XC7K70T -3, -2, -2LE(1.0V), -1, and -2LE (0.9V) XC7K160T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K325T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K355T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K410T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K420T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K480T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XQ7K325T -2I, -2LE(1.0V), -1I, -2LE(0.9V), -2LI (0.95V), -1LM, and -1M XQ7K410T -2I, -2LE(1.0V), -1I, -2LE(0.9V), -2LI (0.95V), and -1M Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table16 lists the production released Kintex-7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 16: Kintex-7 Device Production Software and Speed Specification Release Speed Grade Designations Device 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M -1LM -2LI -2LE XC7K70T Vivado tools 2012.4 v1.08 N/A N/A N/A Vivado tools 2012.4 v1.07 or ISE tools 14.2 v1.06 or ISE tools 14.3 v1.06 XC7K160T Vivado tools 2012.4 v1.08 N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07 or ISE tools 14.2 v1.06 or ISE tools 14.3 v1.06 XC7K325T Vivado tools 2012.4 v1.08 N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07 or ISE tools 14.2 v1.06 or ISE tools 14.3 v1.06 XC7K355T Vivado tools 2012.4 v1.08 N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07 or ISE tools 14.2 v1.06 or ISE tools 14.3 v1.06 XC7K410T Vivado tools 2012.4 v1.08 N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07 or ISE tools 14.2 v1.06 or ISE tools 14.3 v1.06 XC7K420T Vivado tools 2012.4 v1.08 N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07 or ISE tools 14.2 v1.06 or ISE tools 14.3 v1.06 XC7K480T Vivado tools 2012.4 v1.08 N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07 or ISE tools 14.2 v1.06 or ISE tools 14.3 v1.06 XQ7K325T N/A Vivado tools 2013.1 v1.04 Vivado tools Vivado tools 2015.4 v1.07 Vivado tools 2013.1 v1.04 or ISE tools 14.5 v1.04 2015.4 v1.09 or ISE tools 14.5 v1.04 XQ7K410T N/A Vivado tools 2013.1 v1.04 N/A Vivado tools 2015.4 v1.07 Vivado tools 2013.1 v1.04 or ISE tools 14.5 v1.04 or ISE tools 14.5 v1.04 DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 13

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Selecting the Correct Speed Grade and Voltage in the Vivado Tools It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting. To select the 1.0V speed specifications in the Vivado tools, select the Kintex-7 or Defense Grade Kintex-7Q sub-family, and then select the part name that is the device name followed by the package name followed by the speed grade. For example, select the xc7k325tffg900-3 part name for the XC7K325T device in the FFG900 package and -3 (1.0V) speed grade or select the xc7k325tffg900-2L part name for the XC7K325T device in the FFG900 package and -2LE (1.0V) speed grade. To select the -2LI (0.95V) speed specifications in the Vivado tools, select the Kintex-7 sub-family and then select the part name that is the device name followed by an i followed by the package name followed by the speed grade. For example, select the xc7k325tiffg900-2L part name for the XC7K325T device in the FFG900 package and -2LI (0.95V) speed grade. The -2LI (0.95V) speed specifications are not supported in the ISE tools. To select the -2LE (0.9V) speed specifications in the Vivado tools, select the Kintex-7 Low Voltage or Defense Grade Kintex-7Q Low Voltage sub-family, and then select the part name that is the device name followed by an l followed by the package name followed by the speed grade. For example, select the xc7k325tlffg900-2L part name for the XC7K325T device in the FFG900 package and -2LE (0.9V) speed grade. A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See Table16 for the subset of 7 series FPGAs supported in the ISE tools. Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Kintex-7 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page12. In each table, the I/O bank type is either High Performance (HP) or High Range (HR). Table 17: Networking Applications Interface Performances Speed Grade I/O Description Bank 1.0V 0.95V 0.9V Units Type -3 -2/-2LE -1/-1M/-1LM -2LI -2LE SDR LVDS transmitter (using OSERDES; HR 710 710 625 710 625 Mb/s DATA_WIDTH=4 to 8) HP 710 710 625 710 625 Mb/s DDR LVDS transmitter (using OSERDES; HR 1250 1250 950 1250 950 Mb/s DATA_WIDTH=4 to 14) HP 1600 1400 1250 1400 1250 Mb/s SDR LVDS receiver (SFI-4.1)(1) HR 710 710 625 710 625 Mb/s HP 710 710 625 710 625 Mb/s DDR LVDS receiver (SPI-4.2)(1) HR 1250 1250 950 1250 950 Mb/s HP 1600 1400 1250 1400 1250 Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. Table18 and Table19 provide the maximum data rates for applicable memory standards using the Kintex-7 FPGAs memory PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado or ISE Design Suite, following guidelines in the Zynq-7000 SoC and 7Series Devices Memory Interface Solutions User Guide (UG586), electrical analysis, and characterization of the system. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 14

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator (FF and RF Packages)(1)(2) Speed Grade Memory I/O Bank V 1.0V 0.95V 0.9V Units Standard Type CCAUX_IO -3 -2/-2LE -1 -1M/-1LM -2LI -2LE 4:1 Memory Controllers HP 2.0V 1866(3) 1866(3) 1600 1066 1600 1333 Mb/s DDR3 HP 1.8V 1600 1333 1066 800 1333 1066 Mb/s HR N/A 1066 1066 800 800 1066 800 Mb/s HP 2.0V 1600 1600 1333 1066 1600 1066 Mb/s DDR3L HP 1.8V 1333 1066 800 800 1066 800 Mb/s HR N/A 800 800 667 N/A 800 667 Mb/s HP 2.0V 800 800 800 667 800 800 Mb/s DDR2 HP 1.8V 800 800 800 667 800 800 Mb/s HR N/A 800 800 800 533 800 800 Mb/s HP 2.0V 800 667 667 550 667 533 MHz RLDRAM III HP 1.8V 550 500 450 400 500 450 MHz HR N/A N/A 2:1 Memory Controllers HP 2.0V 1066 1066 800 667 1066 800 Mb/s DDR3 HP 1.8V 1066 1066 800 667 1066 800 Mb/s HR N/A 1066 1066 800 667 1066 800 Mb/s HP 2.0V 1066 1066 800 667 1066 800 Mb/s DDR3L HP 1.8V 1066 1066 800 667 1066 800 Mb/s HR N/A 800 800 667 N/A 800 667 Mb/s HP 2.0V 667 DDR2 HP 1.8V 800 800 800 667 800 800 Mb/s HR N/A 533 HP 2.0V 550 500 450 300 500 450 MHz QDR II+(4) HP 1.8V HR N/A 500 450 400 300 450 400 MHz HP 2.0V RLDRAM II HP 1.8V 533 500 450 400 500 450 MHz HR N/A HP 2.0V 667 667 667 533 667 667 Mb/s LPDDR2 HP 1.8V 667 667 667 533 667 667 Mb/s HR N/A 667 667 667 533 667 667 Mb/s Notes: 1. V tracking is required. For more information, see the Zynq-7000 SoC and 7Series Devices Memory Interface Solutions User Guide REF (UG586). 2. When using the internal V , the maximum data rate is 800Mb/s (400MHz). REF 3. For designs using 1866Mb/s components, contact Xilinx Technical Support. 4. The maximum QDRII+ performance specifications are for burst-length 4 (BL=4) implementations. Burst length 2 (BL=2) implementations are limited to 333MHz for all speed grades and I/O bank types. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 15

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 19: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator (FB Packages)(1)(2) Speed Grade Memory I/O Bank V (3) 1.0V 0.95V 0.9V Units Standard Type CCAUX_IO -3 -2/-2LE -1 -1M/-1LM -2LI -2LE 4:1 Memory Controllers HP N/A 1333 1066 800 800 1066 800 Mb/s DDR3 HR N/A 1066 800 800 800 800 800 Mb/s HP N/A 1066 800 667 667 800 667 Mb/s DDR3L HR N/A 800 800 667 N/A 800 667 Mb/s HP N/A 800 800 800 667 800 800 Mb/s DDR2 HR N/A 800 667 667 533 667 667 Mb/s HP N/A 550 500 450 350 500 450 MHz RLDRAM III HR N/A N/A 2:1 Memory Controllers HP N/A 1066 1066 800 667 1066 800 Mb/s DDR3 HR N/A 1066 800 800 667 800 800 Mb/s HP N/A 1066 800 667 667 800 667 Mb/s DDR3L HR N/A 800 800 667 N/A 800 667 Mb/s HP N/A 800 800 800 667 800 800 Mb/s DDR2 HR N/A 800 667 667 533 667 667 Mb/s HP N/A 550 500 450 300 500 450 MHz QDR II+(4) HR N/A 450 400 350 300 400 350 MHz HP N/A RLDRAM II 533 500 450 400 500 450 MHz HR N/A HP N/A 667 667 667 400 667 667 Mb/s LPDDR2 HR N/A 667 667 533 400 667 533 Mb/s Notes: 1. V tracking is required. For more information, see the Zynq-7000 SoC and 7Series Devices Memory Interface Solutions User Guide REF (UG586). 2. When using the internal V , the maximum data rate is 800Mb/s (400MHz). REF 3. FB packages do not have separate V supply pins to adjust the pre-driver voltage of the HP I/O banks. CCAUX_IO 4. The maximum QDRII+ performance specifications are for burst-length 4 (BL=4) implementations. Burst length 2 (BL=2) implementations are limited to 333MHz for all speed grades and I/O bank types. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 16

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics IOB Pad Input/Output/3-State Table20 (high-range IOB (HR)) and Table21 (high-performance IOB (HP)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. • T is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies IOPI depending on the capability of the SelectIO input buffer. • T is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies IOOP depending on the capability of the SelectIO output buffer. • T is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is IOTP disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than T when the DCITERMDISABLE pin is used. In HR I/O banks, the IOTP IN_TERM termination turn-on time is always faster than T when the INTERMDISABLE pin is used. IOTP Table 20: IOB High Range (HR) Switching Characteristics T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM LVTTL_S4 1.31 1.42 1.64 1.64 1.42 1.51 3.77 3.90 4.00 4.00 3.90 4.13 3.52 3.67 3.86 3.86 3.67 3.85 ns LVTTL_S8 1.31 1.42 1.64 1.64 1.42 1.51 3.50 3.64 3.73 3.73 3.64 3.86 3.26 3.40 3.60 3.60 3.40 3.58 ns LVTTL_S12 1.31 1.42 1.64 1.64 1.42 1.51 3.49 3.62 3.72 3.72 3.62 3.84 3.24 3.39 3.58 3.58 3.39 3.56 ns LVTTL_S16 1.31 1.42 1.64 1.64 1.42 1.51 3.03 3.17 3.26 3.26 3.17 3.39 2.79 2.93 3.13 3.13 2.93 3.11 ns LVTTL_S24 1.31 1.42 1.64 1.64 1.42 1.51 3.25 3.39 3.48 3.48 3.39 3.61 3.01 3.15 3.35 3.35 3.15 3.33 ns LVTTL_F4 1.31 1.42 1.64 1.64 1.42 1.51 3.22 3.36 3.45 3.45 3.36 3.58 2.98 3.12 3.32 3.32 3.12 3.30 ns LVTTL_F8 1.31 1.42 1.64 1.64 1.42 1.51 2.71 2.84 2.93 2.93 2.84 3.06 2.46 2.61 2.80 2.80 2.61 2.78 ns LVTTL_F12 1.31 1.42 1.64 1.64 1.42 1.51 2.69 2.82 2.92 2.92 2.82 3.05 2.44 2.59 2.79 2.79 2.59 2.77 ns LVTTL_F16 1.31 1.42 1.64 1.64 1.42 1.51 2.57 2.85 3.15 3.15 2.85 2.88 2.33 2.61 3.02 3.02 2.61 2.60 ns LVTTL_F24 1.31 1.42 1.64 1.64 1.42 1.51 2.41 2.64 2.89 3.04 2.64 2.94 2.16 2.41 2.76 2.91 2.41 2.66 ns LVDS_25 0.64 0.68 0.80 0.87 0.68 0.83 1.36 1.47 1.55 1.55 1.47 1.58 1.11 1.24 1.41 1.41 1.24 1.30 ns MINI_LVDS_25 0.68 0.70 0.79 0.87 0.70 0.83 1.36 1.47 1.55 1.55 1.47 1.59 1.11 1.24 1.41 1.41 1.24 1.31 ns BLVDS_25 0.65 0.69 0.80 0.85 0.69 0.83 1.83 2.02 2.20 2.57 2.02 2.16 1.59 1.79 2.07 2.44 1.79 1.88 ns RSDS_25 0.63 0.68 0.79 0.87 0.68 0.83 1.36 1.48 1.55 1.55 1.48 1.59 1.11 1.24 1.41 1.41 1.24 1.31 ns (point to point) PPDS_25 0.65 0.69 0.80 0.87 0.69 0.83 1.36 1.49 1.58 1.58 1.49 1.59 1.11 1.25 1.45 1.45 1.25 1.31 ns TMDS_33 0.72 0.76 0.86 0.90 0.76 0.83 1.43 1.54 1.60 1.60 1.54 1.70 1.18 1.31 1.47 1.47 1.31 1.42 ns PCI33_3 1.28 1.41 1.65 1.65 1.41 1.50 2.71 3.08 3.52 3.52 3.08 3.42 2.46 2.84 3.39 3.39 2.84 3.14 ns HSUL_12_S 0.63 0.64 0.71 0.85 0.64 0.79 1.77 1.90 2.00 2.00 1.90 2.13 1.52 1.67 1.86 1.86 1.67 1.85 ns HSUL_12_F 0.63 0.64 0.71 0.85 0.64 0.79 1.26 1.40 1.50 1.50 1.40 1.61 1.01 1.16 1.37 1.37 1.16 1.33 ns DIFF_HSUL_ 0.58 0.61 0.70 0.84 0.61 0.81 1.55 1.68 1.78 1.78 1.68 1.92 1.30 1.45 1.65 1.65 1.45 1.64 ns 12_S DIFF_HSUL_ 0.58 0.61 0.70 0.84 0.61 0.81 1.16 1.28 1.35 1.35 1.28 1.50 0.92 1.04 1.21 1.21 1.04 1.22 ns 12_F MOBILE_DDR_S 0.64 0.66 0.74 0.74 0.66 0.89 2.58 2.91 3.31 3.31 2.91 1.95 2.33 2.68 3.17 3.17 2.68 1.67 ns MOBILE_DDR_F 0.64 0.66 0.74 0.74 0.66 0.89 1.91 2.13 2.36 2.36 2.13 1.69 1.66 1.89 2.23 2.23 1.89 1.41 ns DIFF_MOBILE_ 0.63 0.66 0.75 0.75 0.66 0.79 2.51 2.84 3.24 3.24 2.84 1.95 2.26 2.61 3.10 3.10 2.61 1.67 ns DDR_S DIFF_MOBILE_ 0.63 0.66 0.75 0.75 0.66 0.79 1.89 2.11 2.34 2.34 2.11 1.72 1.64 1.88 2.21 2.21 1.88 1.44 ns DDR_F DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 17

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 20: IOB High Range (HR) Switching Characteristics (Cont’d) T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM HSTL_I_S 0.61 0.64 0.73 0.84 0.64 0.79 1.55 1.69 1.80 1.80 1.69 1.91 1.30 1.46 1.67 1.67 1.46 1.63 ns HSTL_II_S 0.61 0.64 0.73 0.84 0.64 0.78 1.21 1.34 1.43 1.61 1.34 1.70 0.96 1.11 1.30 1.47 1.11 1.42 ns HSTL_I_18_S 0.64 0.67 0.76 0.85 0.67 0.79 1.28 1.39 1.45 1.45 1.39 1.58 1.04 1.16 1.31 1.32 1.16 1.30 ns HSTL_II_18_S 0.64 0.67 0.76 0.85 0.67 0.79 1.18 1.31 1.40 1.57 1.31 1.69 0.93 1.08 1.27 1.44 1.08 1.41 ns DIFF_HSTL_I_S 0.63 0.67 0.77 0.84 0.67 0.78 1.42 1.54 1.61 1.78 1.54 1.84 1.17 1.31 1.48 1.65 1.31 1.56 ns DIFF_HSTL_II_S 0.63 0.67 0.77 0.84 0.67 0.79 1.15 1.24 1.27 1.61 1.24 1.78 0.91 1.01 1.14 1.47 1.01 1.50 ns DIFF_HSTL_I_ 0.65 0.69 0.78 0.84 0.69 0.79 1.27 1.38 1.43 1.45 1.38 1.67 1.03 1.14 1.30 1.32 1.14 1.39 ns 18_S DIFF_HSTL_II_ 0.65 0.69 0.78 0.85 0.69 0.81 1.14 1.23 1.26 1.57 1.23 1.72 0.90 1.00 1.13 1.44 1.00 1.44 ns 18_S HSTL_I_F 0.61 0.64 0.73 0.84 0.64 0.79 1.10 1.19 1.23 1.31 1.19 1.41 0.85 0.96 1.10 1.18 0.96 1.13 ns HSTL_II_F 0.61 0.64 0.73 0.84 0.64 0.78 1.05 1.18 1.28 1.31 1.18 1.42 0.80 0.95 1.15 1.18 0.95 1.14 ns HSTL_I_18_F 0.64 0.67 0.76 0.85 0.67 0.79 1.05 1.18 1.28 1.36 1.18 1.44 0.80 0.95 1.15 1.22 0.95 1.16 ns HSTL_II_18_F 0.64 0.67 0.76 0.85 0.67 0.79 1.03 1.14 1.23 1.32 1.14 1.42 0.78 0.90 1.10 1.19 0.90 1.14 ns DIFF_HSTL_I_F 0.63 0.67 0.77 0.84 0.67 0.78 1.09 1.18 1.22 1.31 1.18 1.48 0.84 0.95 1.09 1.18 0.95 1.20 ns DIFF_HSTL_II_F 0.63 0.67 0.77 0.84 0.67 0.79 1.02 1.11 1.14 1.31 1.11 1.48 0.77 0.88 1.01 1.18 0.88 1.20 ns DIFF_HSTL_I_ 0.65 0.69 0.78 0.84 0.69 0.79 1.08 1.17 1.21 1.36 1.17 1.48 0.83 0.94 1.07 1.22 0.94 1.20 ns 18_F DIFF_HSTL_II_ 0.65 0.69 0.78 0.85 0.69 0.81 1.01 1.10 1.13 1.32 1.10 1.48 0.76 0.87 1.00 1.19 0.87 1.20 ns 18_F LVCMOS33_S4 1.31 1.40 1.60 1.60 1.40 1.54 3.77 3.90 4.00 4.00 3.90 4.13 3.52 3.67 3.86 3.86 3.67 3.85 ns LVCMOS33_S8 1.31 1.40 1.60 1.60 1.40 1.54 3.49 3.62 3.72 3.72 3.62 3.84 3.24 3.39 3.58 3.58 3.39 3.56 ns LVCMOS33_S12 1.31 1.40 1.60 1.60 1.40 1.54 3.05 3.18 3.28 3.28 3.18 3.41 2.80 2.95 3.15 3.15 2.95 3.13 ns LVCMOS33_S16 1.31 1.40 1.60 1.60 1.40 1.54 3.06 3.43 3.88 3.88 3.43 3.72 2.81 3.20 3.75 3.75 3.20 3.44 ns LVCMOS33_F4 1.31 1.40 1.60 1.60 1.40 1.54 3.22 3.36 3.45 3.45 3.36 3.58 2.98 3.12 3.32 3.32 3.12 3.30 ns LVCMOS33_F8 1.31 1.40 1.60 1.60 1.40 1.54 2.71 2.84 2.93 2.93 2.84 3.06 2.46 2.61 2.80 2.80 2.61 2.78 ns LVCMOS33_F12 1.31 1.40 1.60 1.60 1.40 1.54 2.57 2.85 3.15 3.15 2.85 2.88 2.33 2.61 3.02 3.02 2.61 2.60 ns LVCMOS33_F16 1.31 1.40 1.60 1.60 1.40 1.54 2.44 2.69 2.96 2.96 2.69 2.88 2.19 2.45 2.82 2.82 2.45 2.60 ns LVCMOS25_S4 1.08 1.16 1.32 1.35 1.16 1.36 3.08 3.22 3.31 3.31 3.22 3.44 2.84 2.98 3.18 3.18 2.98 3.16 ns LVCMOS25_S8 1.08 1.16 1.32 1.35 1.16 1.36 2.85 2.98 3.07 3.08 2.98 3.20 2.60 2.75 2.94 2.94 2.75 2.92 ns LVCMOS25_S12 1.08 1.16 1.32 1.35 1.16 1.36 2.44 2.57 2.67 2.67 2.57 2.80 2.19 2.34 2.54 2.54 2.34 2.52 ns LVCMOS25_S16 1.08 1.16 1.32 1.35 1.16 1.36 2.79 2.92 3.01 3.01 2.92 3.14 2.54 2.68 2.88 2.88 2.68 2.86 ns LVCMOS25_F4 1.08 1.16 1.32 1.35 1.16 1.36 2.71 2.84 2.93 2.93 2.84 3.06 2.46 2.61 2.80 2.80 2.61 2.78 ns LVCMOS25_F8 1.08 1.16 1.32 1.35 1.16 1.36 2.14 2.28 2.37 2.37 2.28 2.50 1.90 2.04 2.24 2.24 2.04 2.22 ns LVCMOS25_F12 1.08 1.16 1.32 1.35 1.16 1.36 2.15 2.29 2.52 2.52 2.29 2.48 1.91 2.05 2.38 2.38 2.05 2.20 ns LVCMOS25_F16 1.08 1.16 1.32 1.35 1.16 1.36 1.92 2.17 2.45 2.45 2.17 2.33 1.67 1.94 2.32 2.32 1.94 2.05 ns LVCMOS18_S4 0.64 0.66 0.74 0.95 0.66 0.87 1.55 1.68 1.78 1.78 1.68 1.91 1.30 1.45 1.65 1.65 1.45 1.63 ns LVCMOS18_S8 0.64 0.66 0.74 0.95 0.66 0.87 2.14 2.28 2.37 2.37 2.28 2.50 1.90 2.04 2.24 2.24 2.04 2.22 ns LVCMOS18_S12 0.64 0.66 0.74 0.95 0.66 0.87 2.14 2.28 2.37 2.37 2.28 2.50 1.90 2.04 2.24 2.24 2.04 2.22 ns LVCMOS18_S16 0.64 0.66 0.74 0.95 0.66 0.87 1.49 1.62 1.72 1.72 1.62 1.84 1.24 1.39 1.58 1.58 1.39 1.56 ns DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 18

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 20: IOB High Range (HR) Switching Characteristics (Cont’d) T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM LVCMOS18_S24 0.64 0.66 0.74 0.95 0.66 0.87 1.74 1.92 2.08 2.22 1.92 1.92 1.50 1.69 1.95 2.08 1.69 1.64 ns LVCMOS18_F4 0.64 0.66 0.74 0.95 0.66 0.87 1.38 1.51 1.61 1.64 1.51 1.77 1.13 1.28 1.47 1.50 1.28 1.49 ns LVCMOS18_F8 0.64 0.66 0.74 0.95 0.66 0.87 1.64 1.78 1.87 1.87 1.78 2.00 1.40 1.54 1.74 1.74 1.54 1.72 ns LVCMOS18_F12 0.64 0.66 0.74 0.95 0.66 0.87 1.64 1.78 1.87 1.87 1.78 2.00 1.40 1.54 1.74 1.74 1.54 1.72 ns LVCMOS18_F16 0.64 0.66 0.74 0.95 0.66 0.87 1.52 1.68 1.81 1.81 1.68 1.72 1.28 1.45 1.68 1.68 1.45 1.44 ns LVCMOS18_F24 0.64 0.66 0.74 0.95 0.66 0.87 1.34 1.46 1.55 2.09 1.46 1.66 1.09 1.23 1.42 1.96 1.23 1.38 ns LVCMOS15_S4 0.66 0.69 0.81 0.93 0.69 0.90 1.86 2.00 2.09 2.09 2.00 2.22 1.62 1.76 1.96 1.96 1.76 1.94 ns LVCMOS15_S8 0.66 0.69 0.81 0.93 0.69 0.90 2.05 2.18 2.28 2.28 2.18 2.41 1.80 1.95 2.14 2.15 1.95 2.13 ns LVCMOS15_S12 0.66 0.69 0.81 0.93 0.69 0.90 1.83 2.03 2.23 2.23 2.03 1.91 1.59 1.80 2.10 2.10 1.80 1.63 ns LVCMOS15_S16 0.66 0.69 0.81 0.93 0.69 0.90 1.76 1.95 2.13 2.13 1.95 1.91 1.52 1.72 1.99 1.99 1.72 1.63 ns LVCMOS15_F4 0.66 0.69 0.81 0.93 0.69 0.90 1.63 1.76 1.86 1.86 1.76 1.98 1.38 1.53 1.72 1.72 1.53 1.70 ns LVCMOS15_F8 0.66 0.69 0.81 0.93 0.69 0.90 1.79 1.99 2.18 2.18 1.99 1.92 1.55 1.76 2.05 2.05 1.76 1.64 ns LVCMOS15_F12 0.66 0.69 0.81 0.93 0.69 0.90 1.40 1.54 1.65 1.65 1.54 1.67 1.15 1.31 1.52 1.52 1.31 1.39 ns LVCMOS15_F16 0.66 0.69 0.81 0.93 0.69 0.90 1.37 1.51 1.61 1.89 1.51 1.66 1.13 1.27 1.48 1.75 1.27 1.38 ns LVCMOS12_S4 0.88 0.91 1.00 1.17 0.91 1.01 2.53 2.67 2.76 2.76 2.67 2.89 2.29 2.43 2.63 2.63 2.43 2.61 ns LVCMOS12_S8 0.88 0.91 1.00 1.17 0.91 1.01 2.05 2.18 2.28 2.28 2.18 2.41 1.80 1.95 2.14 2.15 1.95 2.13 ns LVCMOS12_S12 0.88 0.91 1.00 1.17 0.91 1.01 1.75 1.89 1.98 1.98 1.89 2.11 1.51 1.65 1.85 1.85 1.65 1.83 ns LVCMOS12_F4 0.88 0.91 1.00 1.17 0.91 1.01 1.94 2.07 2.17 2.17 2.07 2.30 1.69 1.84 2.04 2.04 1.84 2.02 ns LVCMOS12_F8 0.88 0.91 1.00 1.17 0.91 1.01 1.50 1.64 1.73 1.73 1.64 1.86 1.26 1.40 1.60 1.60 1.40 1.58 ns LVCMOS12_F12 0.88 0.91 1.00 1.17 0.91 1.01 1.54 1.71 1.87 1.87 1.71 1.69 1.29 1.48 1.74 1.74 1.48 1.41 ns SSTL135_S 0.61 0.64 0.73 0.85 0.64 0.79 1.27 1.40 1.50 1.53 1.40 1.64 1.02 1.17 1.36 1.40 1.17 1.36 ns SSTL15_S 0.61 0.64 0.73 0.73 0.64 0.73 1.24 1.37 1.47 1.53 1.37 1.59 0.99 1.14 1.33 1.40 1.14 1.31 ns SSTL18_I_S 0.64 0.67 0.76 0.84 0.67 0.79 1.59 1.74 1.85 1.85 1.74 1.95 1.34 1.50 1.72 1.72 1.50 1.67 ns SSTL18_II_S 0.64 0.67 0.76 0.85 0.67 0.78 1.27 1.40 1.50 1.50 1.40 1.63 1.02 1.17 1.36 1.36 1.17 1.35 ns DIFF_SSTL135_ 0.59 0.61 0.73 0.85 0.61 0.79 1.27 1.40 1.50 1.53 1.40 1.64 1.02 1.17 1.36 1.40 1.17 1.36 ns S DIFF_SSTL15_S 0.63 0.67 0.77 0.85 0.67 0.79 1.24 1.37 1.47 1.53 1.37 1.59 0.99 1.14 1.33 1.40 1.14 1.31 ns DIFF_SSTL18_ 0.65 0.69 0.78 0.85 0.69 0.79 1.50 1.63 1.72 1.82 1.63 1.95 1.26 1.40 1.59 1.69 1.40 1.67 ns I_S DIFF_SSTL18_ 0.65 0.69 0.78 0.85 0.69 0.79 1.13 1.22 1.25 1.50 1.22 1.66 0.88 0.99 1.12 1.36 0.99 1.38 ns II_S DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 19

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 20: IOB High Range (HR) Switching Characteristics (Cont’d) T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM SSTL135_F 0.61 0.64 0.73 0.85 0.64 0.79 1.04 1.17 1.26 1.31 1.17 1.42 0.79 0.93 1.13 1.18 0.93 1.14 ns SSTL15_F 0.61 0.64 0.73 0.73 0.64 0.73 1.04 1.17 1.26 1.26 1.17 1.39 0.79 0.93 1.13 1.13 0.93 1.11 ns SSTL18_I_F 0.64 0.67 0.76 0.84 0.67 0.79 1.12 1.22 1.26 1.34 1.22 1.44 0.88 0.99 1.13 1.21 0.99 1.16 ns SSTL18_II_F 0.64 0.67 0.76 0.85 0.67 0.78 1.05 1.18 1.28 1.32 1.18 1.42 0.80 0.95 1.15 1.19 0.95 1.14 ns DIFF_SSTL135_ ns 0.59 0.61 0.73 0.85 0.61 0.79 1.04 1.17 1.26 1.31 1.17 1.42 0.79 0.93 1.13 1.18 0.93 1.14 F DIFF_SSTL15_F 0.63 0.67 0.77 0.85 0.67 0.79 1.04 1.17 1.26 1.26 1.17 1.39 0.79 0.93 1.13 1.13 0.93 1.11 ns DIFF_SSTL18_I_ ns 0.65 0.69 0.78 0.85 0.69 0.79 1.10 1.19 1.23 1.34 1.19 1.52 0.85 0.96 1.10 1.21 0.96 1.24 F DIFF_SSTL18_II ns 0.65 0.69 0.78 0.85 0.69 0.79 1.02 1.10 1.14 1.32 1.10 1.50 0.77 0.87 1.00 1.19 0.87 1.22 _F DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 20

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 21: IOB High Performance (HP) Switching Characteristics T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM LVDS 0.75 0.79 0.92 0.96 0.79 0.89 1.05 1.17 1.24 1.26 1.17 1.43 0.88 1.01 1.08 1.10 1.01 1.32 ns HSUL_12_S 0.69 0.72 0.82 0.98 0.72 0.95 1.65 1.84 2.05 2.05 1.84 1.80 1.48 1.68 1.89 1.89 1.68 1.70 ns HSUL_12_F 0.69 0.72 0.82 0.98 0.72 0.95 1.39 1.54 1.68 1.68 1.54 1.49 1.22 1.38 1.52 1.52 1.38 1.39 ns DIFF_HSUL_12_ 0.69 0.72 0.82 0.98 0.72 0.92 1.65 1.84 2.05 2.05 1.84 1.47 1.48 1.68 1.89 1.89 1.68 1.37 ns S DIFF_HSUL_12_F 0.69 0.72 0.82 0.98 0.72 0.92 1.39 1.54 1.68 1.68 1.54 1.35 1.22 1.38 1.52 1.52 1.38 1.24 ns DIFF_HSUL_12_ 0.69 0.72 0.82 0.82 0.72 0.92 1.78 1.91 2.05 2.05 1.91 1.46 1.61 1.76 1.89 1.89 1.76 1.35 ns DCI_S DIFF_HSUL_12_ 0.69 0.72 0.82 0.82 0.72 0.92 1.56 1.67 1.76 1.76 1.67 1.35 1.39 1.51 1.60 1.60 1.51 1.24 ns DCI_F HSTL_I_S 0.68 0.72 0.82 0.90 0.72 0.84 1.15 1.28 1.38 1.38 1.28 1.46 0.98 1.12 1.22 1.22 1.12 1.35 ns HSTL_II_S 0.68 0.72 0.82 0.90 0.72 0.84 1.05 1.17 1.26 1.27 1.17 1.44 0.88 1.01 1.10 1.11 1.01 1.34 ns HSTL_I_18_S 0.70 0.72 0.82 0.95 0.72 0.86 1.12 1.24 1.34 1.34 1.24 1.41 0.95 1.08 1.18 1.18 1.08 1.31 ns HSTL_II_18_S 0.70 0.72 0.82 0.90 0.72 0.86 1.06 1.18 1.26 1.27 1.18 1.44 0.89 1.02 1.10 1.11 1.02 1.34 ns HSTL_I_12_S 0.68 0.72 0.82 0.96 0.72 0.94 1.14 1.27 1.37 1.37 1.27 1.43 0.97 1.11 1.21 1.21 1.11 1.32 ns HSTL_I_DCI_S 0.68 0.72 0.82 0.90 0.72 0.78 1.11 1.23 1.33 1.33 1.23 1.36 0.94 1.07 1.17 1.17 1.07 1.26 ns HSTL_II_DCI_S 0.68 0.72 0.82 0.85 0.72 0.78 1.05 1.17 1.26 1.26 1.17 1.33 0.88 1.01 1.10 1.10 1.01 1.23 ns HSTL_II_T_DCI_ 0.70 0.72 0.82 0.82 0.72 0.76 1.15 1.28 1.38 1.38 1.28 1.40 0.98 1.12 1.22 1.22 1.12 1.29 ns S HSTL_I_DCI_18_ 0.70 0.72 0.82 0.90 0.72 0.76 1.11 1.23 1.33 1.33 1.23 1.36 0.94 1.07 1.17 1.17 1.07 1.26 ns S HSTL_II_DCI_18_ 0.70 0.72 0.82 0.82 0.72 0.76 1.05 1.16 1.24 1.24 1.16 1.32 0.88 1.00 1.08 1.08 1.00 1.21 ns S HSTL_II 0.70 0.72 0.82 0.84 0.72 0.76 1.11 1.23 1.33 1.34 1.23 1.36 0.94 1.07 1.17 1.18 1.07 1.26 ns _T_DCI_18_S DIFF_HSTL_I_S 0.75 0.79 0.92 1.02 0.79 0.89 1.15 1.28 1.38 1.38 1.28 1.47 0.98 1.12 1.22 1.22 1.12 1.37 ns DIFF_HSTL_II_S 0.75 0.79 0.92 1.02 0.79 0.89 1.05 1.17 1.26 1.32 1.17 1.47 0.88 1.01 1.10 1.16 1.01 1.37 ns DIFF_HSTL_I_ 0.75 0.79 0.92 0.92 0.79 0.76 1.15 1.28 1.38 1.38 1.28 1.47 0.98 1.12 1.22 1.22 1.12 1.37 ns DCI_S DIFF_HSTL_II_ 0.75 0.79 0.92 0.92 0.79 0.76 1.05 1.17 1.26 1.26 1.17 1.40 0.88 1.01 1.10 1.10 1.01 1.29 ns DCI_S DIFF_HSTL_I_ 0.75 0.79 0.92 0.98 0.79 0.89 1.12 1.24 1.34 1.34 1.24 1.46 0.95 1.08 1.18 1.18 1.08 1.35 ns 18_S DIFF_HSTL_II_ 0.75 0.79 0.92 0.99 0.79 0.89 1.06 1.18 1.26 1.32 1.18 1.47 0.89 1.02 1.10 1.16 1.02 1.37 ns 18_S DIFF_HSTL_I_ 0.75 0.79 0.92 0.92 0.79 0.75 1.11 1.23 1.33 1.33 1.23 1.46 0.94 1.07 1.17 1.17 1.07 1.35 ns DCI_18_S DIFF_HSTL_II_ 0.75 0.79 0.92 0.93 0.79 0.75 1.05 1.16 1.24 1.26 1.16 1.41 0.88 1.00 1.08 1.10 1.00 1.31 ns DCI_18_S DIFF_HSTL_II 0.75 0.79 0.92 0.92 0.79 0.76 1.11 1.23 1.33 1.33 1.23 1.46 0.94 1.07 1.17 1.17 1.07 1.35 ns _T_DCI_18_S HSTL_I_F 0.68 0.72 0.82 0.90 0.72 0.84 1.02 1.14 1.22 1.22 1.14 1.26 0.85 0.98 1.06 1.06 0.98 1.15 ns HSTL_II_F 0.68 0.72 0.82 0.90 0.72 0.84 0.97 1.08 1.15 1.15 1.08 1.29 0.80 0.92 0.99 0.99 0.92 1.18 ns HSTL_I_18_F 0.70 0.72 0.82 0.95 0.72 0.86 1.04 1.16 1.24 1.24 1.16 1.32 0.87 1.00 1.08 1.08 1.00 1.21 ns DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 21

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM HSTL_II_18_F 0.70 0.72 0.82 0.90 0.72 0.86 0.98 1.09 1.16 1.20 1.09 1.35 0.81 0.94 1.00 1.03 0.94 1.24 ns HSTL_I_12_F 0.68 0.72 0.82 0.96 0.72 0.94 1.02 1.13 1.21 1.21 1.13 1.26 0.85 0.97 1.05 1.05 0.97 1.15 ns HSTL_I_DCI_F 0.68 0.72 0.82 0.90 0.72 0.78 1.04 1.16 1.24 1.24 1.16 1.30 0.87 1.00 1.08 1.08 1.00 1.20 ns HSTL_II_DCI_F 0.68 0.72 0.82 0.85 0.72 0.78 0.97 1.08 1.15 1.15 1.08 1.22 0.80 0.92 0.99 0.99 0.92 1.12 ns HSTL_II_T_DCI_F 0.70 0.72 0.82 0.82 0.72 0.76 1.02 1.14 1.22 1.22 1.14 1.26 0.85 0.98 1.06 1.06 0.98 1.15 ns HSTL_I_DCI_ 0.70 0.72 0.82 0.90 0.72 0.76 1.04 1.16 1.24 1.24 1.16 1.30 0.87 1.00 1.08 1.08 1.00 1.20 ns 18_F HSTL_II_DCI_ 0.70 0.72 0.82 0.82 0.72 0.76 0.98 1.09 1.16 1.16 1.09 1.27 0.81 0.93 1.00 1.00 0.93 1.17 ns 18_F HSTL_II 0.70 0.72 0.82 0.84 0.72 0.76 1.04 1.16 1.24 1.24 1.16 1.30 0.87 1.00 1.08 1.08 1.00 1.20 ns _T_DCI_18_F DIFF_HSTL_I_F 0.75 0.79 0.92 1.02 0.79 0.89 1.02 1.14 1.22 1.22 1.14 1.35 0.85 0.98 1.06 1.06 0.98 1.24 ns DIFF_HSTL_II_F 0.75 0.79 0.92 1.02 0.79 0.89 0.97 1.08 1.15 1.20 1.08 1.35 0.80 0.92 0.99 1.03 0.92 1.24 ns DIFF_HSTL_I_ 0.75 0.79 0.92 0.92 0.79 0.76 1.02 1.14 1.22 1.22 1.14 1.35 0.85 0.98 1.06 1.06 0.98 1.24 ns DCI_F DIFF_HSTL_II_ 0.75 0.79 0.92 0.92 0.79 0.76 0.97 1.08 1.15 1.15 1.08 1.30 0.80 0.92 0.99 0.99 0.92 1.20 ns DCI_F DIFF_HSTL_I_ 0.75 0.79 0.92 0.98 0.79 0.89 1.04 1.16 1.24 1.24 1.16 1.38 0.87 1.00 1.08 1.08 1.00 1.28 ns 18_F DIFF_HSTL_II_ 0.75 0.79 0.92 0.99 0.79 0.89 0.98 1.09 1.16 1.24 1.09 1.40 0.81 0.94 1.00 1.08 0.94 1.29 ns 18_F DIFF_HSTL_I_ 0.75 0.79 0.92 0.92 0.79 0.75 1.04 1.16 1.24 1.24 1.16 1.38 0.87 1.00 1.08 1.08 1.00 1.28 ns DCI_18_F DIFF_HSTL_II_ 0.75 0.79 0.92 0.93 0.79 0.75 0.98 1.09 1.16 1.18 1.09 1.33 0.81 0.93 1.00 1.02 0.93 1.23 ns DCI_18_F DIFF_HSTL_II 0.75 0.79 0.92 0.92 0.79 0.76 1.04 1.16 1.24 1.24 1.16 1.38 0.87 1.00 1.08 1.08 1.00 1.28 ns _T_DCI_18_F LVCMOS18_S2 0.47 0.50 0.60 0.90 0.50 0.87 3.95 4.28 4.85 4.85 4.28 3.40 3.78 4.13 4.69 4.69 4.13 3.29 ns LVCMOS18_S4 0.47 0.50 0.60 0.90 0.50 0.87 2.67 2.98 3.43 3.43 2.98 2.69 2.50 2.82 3.27 3.27 2.82 2.59 ns LVCMOS18_S6 0.47 0.50 0.60 0.90 0.50 0.87 2.14 2.38 2.72 2.72 2.38 2.18 1.97 2.22 2.56 2.56 2.22 2.07 ns LVCMOS18_S8 0.47 0.50 0.60 0.90 0.50 0.87 1.98 2.21 2.52 2.52 2.21 2.02 1.81 2.05 2.36 2.36 2.05 1.92 ns LVCMOS18_S12 0.47 0.50 0.60 0.90 0.50 0.87 1.70 1.91 2.17 2.17 1.91 1.85 1.53 1.75 2.01 2.01 1.75 1.74 ns LVCMOS18_S16 0.47 0.50 0.60 0.90 0.50 0.87 1.57 1.75 1.97 1.97 1.75 1.76 1.40 1.59 1.81 1.81 1.59 1.65 ns LVCMOS18_F2 0.47 0.50 0.60 0.90 0.50 0.87 3.50 3.87 4.48 4.48 3.87 2.85 3.33 3.71 4.32 4.32 3.71 2.74 ns LVCMOS18_F4 0.47 0.50 0.60 0.90 0.50 0.87 2.23 2.50 2.87 2.87 2.50 2.26 2.06 2.34 2.71 2.71 2.34 2.15 ns LVCMOS18_F6 0.47 0.50 0.60 0.90 0.50 0.87 1.80 2.00 2.26 2.26 2.00 1.52 1.63 1.84 2.09 2.09 1.84 1.42 ns LVCMOS18_F8 0.47 0.50 0.60 0.90 0.50 0.87 1.46 1.72 2.04 2.04 1.72 1.51 1.29 1.56 1.88 1.88 1.56 1.40 ns LVCMOS18_F12 0.47 0.50 0.60 0.90 0.50 0.87 1.26 1.40 1.53 1.53 1.40 1.46 1.09 1.24 1.37 1.37 1.24 1.35 ns LVCMOS18_F16 0.47 0.50 0.60 0.90 0.50 0.87 1.19 1.33 1.44 1.66 1.33 1.46 1.02 1.17 1.28 1.50 1.17 1.35 ns LVCMOS15_S2 0.59 0.62 0.73 0.88 0.62 0.86 3.55 3.89 4.45 4.45 3.89 3.11 3.38 3.73 4.29 4.29 3.73 3.01 ns LVCMOS15_S4 0.59 0.62 0.73 0.88 0.62 0.86 2.45 2.70 3.06 3.06 2.70 2.46 2.28 2.54 2.90 2.90 2.54 2.35 ns LVCMOS15_S6 0.59 0.62 0.73 0.88 0.62 0.86 2.24 2.51 2.88 2.88 2.51 2.33 2.07 2.35 2.72 2.72 2.35 2.23 ns DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 22

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM LVCMOS15_S8 0.59 0.62 0.73 0.88 0.62 0.86 1.91 2.16 2.49 2.49 2.16 2.05 1.74 2.00 2.32 2.32 2.00 1.95 ns LVCMOS15_S12 0.59 0.62 0.73 0.88 0.62 0.86 1.77 1.98 2.23 2.23 1.98 1.97 1.60 1.82 2.07 2.07 1.82 1.87 ns LVCMOS15_S16 0.59 0.62 0.73 0.88 0.62 0.86 1.62 1.81 2.02 2.02 1.81 1.85 1.45 1.65 1.86 1.86 1.65 1.74 ns LVCMOS15_F2 0.59 0.62 0.73 0.88 0.62 0.86 3.38 3.69 4.18 4.18 3.69 2.74 3.21 3.53 4.02 4.02 3.53 2.64 ns LVCMOS15_F4 0.59 0.62 0.73 0.88 0.62 0.86 2.04 2.21 2.44 2.44 2.21 1.72 1.87 2.06 2.27 2.27 2.06 1.62 ns LVCMOS15_F6 0.59 0.62 0.73 0.88 0.62 0.86 1.47 1.74 2.09 2.09 1.74 1.49 1.30 1.58 1.93 1.93 1.58 1.39 ns LVCMOS15_F8 0.59 0.62 0.73 0.88 0.62 0.86 1.31 1.46 1.61 1.61 1.46 1.47 1.14 1.30 1.45 1.45 1.30 1.37 ns LVCMOS15_F12 0.59 0.62 0.73 0.88 0.62 0.86 1.21 1.34 1.45 1.45 1.34 1.44 1.04 1.18 1.29 1.29 1.18 1.34 ns LVCMOS15_F16 0.59 0.62 0.73 0.88 0.62 0.86 1.18 1.31 1.41 1.68 1.31 1.41 1.01 1.15 1.25 1.52 1.15 1.31 ns LVCMOS12_S2 0.64 0.67 0.78 1.04 0.67 0.95 3.38 3.80 4.48 4.48 3.80 3.27 3.21 3.64 4.31 4.31 3.64 3.17 ns LVCMOS12_S4 0.64 0.67 0.78 1.04 0.67 0.95 2.62 2.94 3.43 3.43 2.94 2.76 2.45 2.78 3.27 3.27 2.78 2.65 ns LVCMOS12_S6 0.64 0.67 0.78 1.04 0.67 0.95 2.05 2.33 2.72 2.72 2.33 2.24 1.88 2.17 2.56 2.56 2.17 2.14 ns LVCMOS12_S8 0.64 0.67 0.78 1.04 0.67 0.95 1.94 2.18 2.51 2.51 2.18 2.16 1.77 2.02 2.34 2.34 2.02 2.06 ns LVCMOS12_F2 0.64 0.67 0.78 1.04 0.67 0.95 2.84 3.15 3.62 3.62 3.15 2.47 2.67 2.99 3.46 3.46 2.99 2.37 ns LVCMOS12_F4 0.64 0.67 0.78 1.04 0.67 0.95 1.97 2.18 2.44 2.44 2.18 1.69 1.80 2.02 2.28 2.28 2.02 1.59 ns LVCMOS12_F6 0.64 0.67 0.78 1.04 0.67 0.95 1.33 1.51 1.70 1.70 1.51 1.43 1.16 1.35 1.54 1.54 1.35 1.32 ns LVCMOS12_F8 0.64 0.67 0.78 1.04 0.67 0.95 1.27 1.42 1.55 1.55 1.42 1.41 1.10 1.26 1.39 1.39 1.26 1.31 ns LVDCI_18 0.47 0.50 0.60 0.87 0.50 0.86 1.99 2.15 2.35 2.35 2.15 2.44 1.82 1.99 2.19 2.19 1.99 2.34 ns LVDCI_15 0.59 0.62 0.73 0.92 0.62 0.87 1.98 2.23 2.58 2.58 2.23 2.40 1.81 2.07 2.41 2.41 2.07 2.29 ns LVDCI_DV2_18 0.47 0.50 0.60 0.88 0.50 0.87 1.99 2.15 2.34 2.34 2.15 1.86 1.82 1.99 2.18 2.18 1.99 1.76 ns LVDCI_DV2_15 0.59 0.62 0.73 0.88 0.62 0.87 1.98 2.23 2.58 2.58 2.23 1.83 1.81 2.07 2.41 2.41 2.07 1.73 ns HSLVDCI_18 0.68 0.72 0.82 0.90 0.72 0.86 1.99 2.15 2.35 2.35 2.15 2.43 1.82 1.99 2.19 2.19 1.99 2.32 ns HSLVDCI_15 0.68 0.72 0.82 0.93 0.72 0.84 1.98 2.23 2.58 2.58 2.23 2.27 1.81 2.07 2.41 2.41 2.07 2.17 ns SSTL18_I_S 0.68 0.72 0.82 0.95 0.72 0.86 1.02 1.15 1.24 1.24 1.15 1.41 0.85 0.99 1.08 1.08 0.99 1.31 ns SSTL18_II_S 0.68 0.72 0.82 1.01 0.72 0.87 1.17 1.29 1.37 1.38 1.29 1.55 1.00 1.13 1.21 1.22 1.13 1.45 ns SSTL18_I_DCI_S 0.68 0.72 0.82 0.87 0.72 0.76 0.92 1.06 1.17 1.18 1.06 1.32 0.75 0.90 1.01 1.02 0.90 1.21 ns SSTL18_II_DCI_S 0.68 0.72 0.82 0.82 0.72 0.78 0.88 0.98 1.08 1.12 0.98 1.26 0.71 0.83 0.92 0.96 0.83 1.15 ns SSTL18_II_T_ 0.68 0.72 0.82 0.98 0.72 0.78 0.92 1.06 1.17 1.18 1.06 1.32 0.75 0.90 1.01 1.02 0.90 1.21 ns DCI_S SSTL15_S 0.68 0.72 0.82 0.82 0.72 0.81 0.94 1.06 1.15 1.16 1.06 1.32 0.77 0.91 0.99 1.00 0.91 1.21 ns SSTL15_DCI_S 0.68 0.72 0.82 0.90 0.72 0.78 0.94 1.06 1.15 1.16 1.06 1.30 0.77 0.90 0.99 1.00 0.90 1.20 ns SSTL15_T_DCI_S 0.68 0.72 0.82 0.87 0.72 0.80 0.94 1.06 1.15 1.15 1.06 1.30 0.77 0.90 0.99 0.99 0.90 1.20 ns SSTL135_S 0.69 0.72 0.82 0.93 0.72 0.89 0.97 1.10 1.19 1.20 1.10 1.35 0.80 0.94 1.03 1.03 0.94 1.24 ns SSTL135_DCI_S 0.69 0.72 0.82 0.85 0.72 0.84 0.97 1.09 1.19 1.20 1.09 1.33 0.80 0.93 1.03 1.03 0.93 1.23 ns SSTL135_T_ 0.69 0.72 0.82 0.93 0.72 0.84 0.97 1.09 1.19 1.20 1.09 1.33 0.80 0.93 1.03 1.03 0.93 1.23 ns DCI_S SSTL12_S 0.69 0.72 0.82 1.02 0.72 0.95 0.96 1.09 1.18 1.18 1.09 1.33 0.79 0.93 1.02 1.02 0.93 1.23 ns SSTL12_DCI_S 0.69 0.72 0.82 0.90 0.72 0.91 1.03 1.17 1.27 1.27 1.17 1.33 0.86 1.01 1.11 1.11 1.01 1.23 ns SSTL12_T_DCI_S 0.69 0.72 0.82 0.88 0.72 0.91 1.03 1.17 1.27 1.27 1.17 1.33 0.86 1.01 1.11 1.11 1.01 1.23 ns DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 23

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM DIFF_SSTL18_ 0.75 0.79 0.92 0.99 0.79 0.89 1.02 1.15 1.24 1.29 1.15 1.43 0.85 0.99 1.08 1.13 0.99 1.32 ns I_S DIFF_SSTL18_ 0.75 0.79 0.92 0.93 0.79 0.89 1.17 1.29 1.37 1.40 1.29 1.55 1.00 1.13 1.21 1.24 1.13 1.45 ns II_S DIFF_SSTL18_ 0.75 0.79 0.92 0.92 0.79 0.76 0.92 1.06 1.17 1.24 1.06 1.40 0.75 0.90 1.01 1.08 0.90 1.29 ns I_DCI_S DIFF_SSTL18_ 0.75 0.79 0.92 0.96 0.79 0.75 0.88 0.98 1.08 1.18 0.98 1.33 0.71 0.83 0.92 1.02 0.83 1.23 ns II_DCI_S DIFF_SSTL18_ 0.75 0.79 0.92 0.92 0.79 0.76 0.92 1.06 1.17 1.24 1.06 1.40 0.75 0.90 1.01 1.08 0.90 1.29 ns II_T_DCI_S DIFF_SSTL15_S 0.68 0.72 0.82 0.99 0.72 0.89 0.94 1.06 1.15 1.16 1.06 1.32 0.77 0.91 0.99 1.00 0.91 1.21 ns DIFF_SSTL15_ 0.68 0.72 0.82 0.96 0.72 0.75 0.94 1.06 1.15 1.16 1.06 1.30 0.77 0.90 0.99 1.00 0.90 1.20 ns DCI_S DIFF_SSTL15_T_ 0.68 0.72 0.82 0.88 0.72 0.76 0.94 1.06 1.15 1.23 1.06 1.38 0.77 0.90 0.99 1.07 0.90 1.28 ns DCI_S DIFF_SSTL135_S 0.69 0.72 0.82 1.09 0.72 0.91 0.97 1.10 1.19 1.20 1.10 1.35 0.80 0.94 1.03 1.03 0.94 1.24 ns DIFF_SSTL135_D 0.69 0.72 0.82 0.90 0.72 0.76 0.97 1.09 1.19 1.20 1.09 1.33 0.80 0.93 1.03 1.03 0.93 1.23 ns CI_S DIFF_SSTL135_ 0.69 0.72 0.82 0.84 0.72 0.76 0.97 1.09 1.19 1.27 1.09 1.43 0.80 0.93 1.03 1.11 0.93 1.32 ns T_DCI_S DIFF_SSTL12_S 0.69 0.72 0.82 0.96 0.72 0.91 0.96 1.09 1.18 1.18 1.09 1.33 0.79 0.93 1.02 1.02 0.93 1.23 ns DIFF_SSTL12_ 0.69 0.72 0.82 0.87 0.72 0.78 1.03 1.17 1.27 1.27 1.17 1.33 0.86 1.01 1.11 1.11 1.01 1.23 ns DCI_S DIFF_SSTL12_ 0.69 0.72 0.82 0.96 0.72 0.80 1.03 1.17 1.27 1.27 1.17 1.41 0.86 1.01 1.11 1.11 1.01 1.31 ns T_DCI_S SSTL18_I_F 0.68 0.72 0.82 0.95 0.72 0.86 0.94 1.06 1.15 1.15 1.06 1.32 0.77 0.91 0.99 0.99 0.91 1.21 ns SSTL18_II_F 0.68 0.72 0.82 1.01 0.72 0.87 0.97 1.09 1.16 1.21 1.09 1.36 0.80 0.93 1.00 1.05 0.93 1.26 ns SSTL18_I_DCI_F 0.68 0.72 0.82 0.87 0.72 0.76 0.89 1.02 1.10 1.15 1.02 1.30 0.72 0.86 0.94 0.99 0.86 1.20 ns SSTL18_II_DCI_F 0.68 0.72 0.82 0.82 0.72 0.78 0.89 1.02 1.10 1.10 1.02 1.24 0.72 0.86 0.94 0.94 0.86 1.14 ns SSTL18_II_T_ 0.68 0.72 0.82 0.98 0.72 0.78 0.89 1.02 1.10 1.15 1.02 1.27 0.72 0.86 0.94 0.99 0.86 1.17 ns DCI_F SSTL15_F 0.68 0.72 0.82 0.82 0.72 0.81 0.89 1.01 1.09 1.09 1.01 1.24 0.72 0.85 0.93 0.93 0.85 1.14 ns SSTL15_DCI_F 0.68 0.72 0.82 0.90 0.72 0.78 0.89 1.01 1.09 1.12 1.01 1.27 0.72 0.85 0.93 0.96 0.85 1.17 ns SSTL15_T_DCI_F 0.68 0.72 0.82 0.87 0.72 0.80 0.89 1.01 1.09 1.12 1.01 1.27 0.72 0.85 0.93 0.96 0.85 1.17 ns SSTL135_F 0.69 0.72 0.82 0.93 0.72 0.89 0.88 1.00 1.08 1.12 1.00 1.27 0.71 0.85 0.92 0.96 0.85 1.17 ns SSTL135_DCI_F 0.69 0.72 0.82 0.85 0.72 0.84 0.89 1.00 1.08 1.12 1.00 1.27 0.72 0.85 0.92 0.96 0.85 1.17 ns SSTL135_T_ 0.69 0.72 0.82 0.93 0.72 0.84 0.89 1.00 1.08 1.12 1.00 1.27 0.72 0.85 0.92 0.96 0.85 1.17 ns DCI_F SSTL12_F 0.69 0.72 0.82 1.02 0.72 0.95 0.88 1.00 1.08 1.12 1.00 1.26 0.71 0.84 0.92 0.96 0.84 1.15 ns SSTL12_DCI_F 0.69 0.72 0.82 0.90 0.72 0.91 0.91 1.03 1.11 1.11 1.03 1.24 0.74 0.88 0.95 0.95 0.88 1.14 ns SSTL12_T_DCI_F 0.69 0.72 0.82 0.88 0.72 0.91 0.91 1.03 1.11 1.12 1.03 1.26 0.74 0.88 0.95 0.96 0.88 1.15 ns DIFF_SSTL18_ 0.75 0.79 0.92 0.99 0.79 0.89 0.94 1.06 1.15 1.23 1.06 1.38 0.77 0.91 0.99 1.07 0.91 1.28 ns I_F DIFF_SSTL18_ 0.75 0.79 0.92 0.93 0.79 0.89 0.97 1.09 1.16 1.24 1.09 1.40 0.80 0.93 1.00 1.08 0.93 1.29 ns II_F DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 24

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) T T T IOPI IOOP IOTP Speed Grade Speed Grade Speed Grade I/OStandard Units 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V -2/ -1M/ -2/ -1M/ -2/ -1M/ -3 -1 -2LI -2LE -3 -1 -2LI -2LE -3 -1 -2LI -2LE -2LE -1LM -2LE -1LM -2LE -1LM DIFF_SSTL18_I_ 0.75 0.79 0.92 0.92 0.79 0.76 0.89 1.02 1.10 1.23 1.02 1.36 0.72 0.86 0.94 1.07 0.86 1.26 ns DCI_F DIFF_SSTL18_II_ 0.75 0.79 0.92 0.96 0.79 0.75 0.89 1.02 1.10 1.16 1.02 1.32 0.72 0.86 0.94 1.00 0.86 1.21 ns DCI_F DIFF_SSTL18_II_ 0.75 0.79 0.92 0.92 0.79 0.76 0.89 1.02 1.10 1.24 1.02 1.38 0.72 0.86 0.94 1.08 0.86 1.28 ns T_DCI_F DIFF_SSTL15_F 0.68 0.72 0.82 0.99 0.72 0.89 0.89 1.01 1.09 1.09 1.01 1.24 0.72 0.85 0.93 0.93 0.85 1.14 ns DIFF_SSTL15_D 0.68 0.72 0.82 0.96 0.72 0.75 0.89 1.01 1.09 1.12 1.01 1.27 0.72 0.85 0.93 0.96 0.85 1.17 ns CI_F DIFF_SSTL15_T_ 0.68 0.72 0.82 0.88 0.72 0.76 0.89 1.01 1.09 1.20 1.01 1.35 0.72 0.85 0.93 1.03 0.85 1.24 ns DCI_F DIFF_SSTL135_F 0.69 0.72 0.82 1.09 0.72 0.91 0.88 1.00 1.08 1.12 1.00 1.27 0.71 0.85 0.92 0.96 0.85 1.17 ns DIFF_SSTL135_ 0.69 0.72 0.82 0.90 0.72 0.76 0.89 1.00 1.08 1.12 1.00 1.27 0.72 0.85 0.92 0.96 0.85 1.17 ns DCI_F DIFF_SSTL135_ 0.69 0.72 0.82 0.84 0.72 0.76 0.89 1.00 1.08 1.20 1.00 1.35 0.72 0.85 0.92 1.03 0.85 1.24 ns T_DCI_F DIFF_SSTL12_F 0.69 0.72 0.82 0.96 0.72 0.91 0.88 1.00 1.08 1.12 1.00 1.26 0.71 0.84 0.92 0.96 0.84 1.15 ns DIFF_SSTL12_ 0.69 0.72 0.82 0.87 0.72 0.78 0.91 1.03 1.11 1.11 1.03 1.24 0.74 0.88 0.95 0.95 0.88 1.14 ns DCI_F DIFF_SSTL12_T_ 0.69 0.72 0.82 0.96 0.72 0.80 0.91 1.03 1.11 1.18 1.03 1.33 0.74 0.88 0.95 1.02 0.88 1.23 ns DCI_F Table22 specifies the values of T and T . T is described as the delay from the T pin to the IOB pad IOTPHZ IOIBUFDISABLE IOTPHZ through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T is described as IOIBUFDISABLE the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than T when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always IOTPHZ faster than T when the INTERMDISABLE pin is used. IOTPHZ Table 22: IOB 3-state Output Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T T input to pad high-impedance 0.76 0.86 0.99 0.99 0.86 0.62 ns IOTPHZ T IBUF turn-on time from IBUFDISABLE to 1.72 1.89 2.14 2.14 1.89 2.17 ns IOIBUFDISABLE_HR Ooutput for HR I/O banks T IBUF turn-on time from IBUFDISABLE to 1.31 1.46 1.76 1.76 1.46 1.86 ns IOIBUFDISABLE_HP Ooutput for HP I/O banks DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 25

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table23 shows the test setup parameters used for measuring input delay. Table 23: Input Delay Measurement Methodology V V MEAS REF Description I/O Standard Attribute V (1)(2) V (1)(2) L H (1)(4)(6) (1)(3)(5) LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 – LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 – LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 – LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 – LVTTL, 3.3V LVTTL 0.1 3.2 1.65 – MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 – PCI33, 3.3V PCI33_3 0.1 3.2 1.65 – HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 V –0.5 V +0.5 V 0.60 REF REF REF HSTL, Class I & II, 1.5V HSTL_I, HSTL_II V –0.65 V +0.65 V 0.75 REF REF REF HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 V –0.8 V +0.8 V 0.90 REF REF REF HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 V –0.5 V +0.5 V 0.60 REF REF REF SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 V –0.5 V +0.5 V 0.60 REF REF REF SSTL, 1.35V SSTL135, SSTL135_R V –0.575 V +0.575 V 0.675 REF REF REF SSTL, 1.5V SSTL15, SSTL15_R V –0.65 V +0.65 V 0.75 REF REF REF SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V –0.8 V +0.8 V 0.90 REF REF REF DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9–0.125 0.9+0.125 0(6) – DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6–0.125 0.6+0.125 0(6) – DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I, 0.75–0.125 0.75+0.125 0(6) – DIFF_HSTL_II DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, 0.9–0.125 0.9+0.125 0(6) – DIFF_HSTL_II_18 DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6–0.125 0.6+0.125 0(6) – DIFF_SSTL, 1.2V DIFF_SSTL12 0.6–0.125 0.6+0.125 0(6) – DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, 0.675–0.125 0.675+0.125 0(6) – DIFF_SSTL135_R DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, 0.75–0.125 0.75+0.125 0(6) – DIFF_SSTL15_R DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, 0.9–0.125 0.9+0.125 0(6) – DIFF_SSTL18_II LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 0.9–0.125 0.9+0.125 0(6) – LVDS_25, 2.5V LVDS_25 1.2–0.125 1.2+0.125 0(6) – BLVDS_25, 2.5V BLVDS_25 1.25–0.125 1.25+0.125 0(6) – MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25–0.125 1.25+0.125 0(6) – PPDS_25 PPDS_25 1.25–0.125 1.25+0.125 0(6) – RSDS_25 RSDS_25 1.25–0.125 1.25+0.125 0(6) – DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 26

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 23: Input Delay Measurement Methodology (Cont’d) V V MEAS REF Description I/O Standard Attribute V (1)(2) V (1)(2) L H (1)(4)(6) (1)(3)(5) TMDS_33 TMDS_33 3–0.125 3+0.125 0(6) – Notes: 1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. 2. Input waveform switches between V and V . L H 3. Measurements are made at typical, minimum, and maximum V values. Reported delays reflect worst case of these measurements. V REF REF values listed are typical. 4. Input voltage level from which measurement starts. 5. This is an input voltage reference that bears no relation to the V / V parameters found in IBIS models and/or noted in Figure1. REF MEAS 6. The value given is the differential input voltage. Output Delay Measurements Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure1 and Figure2. X-Ref Target - Figure 1 V REF FPGA Output RREF V MEAS (Voltage Level When Taking Delay Measurement) C REF (Probe Capacitance) DS182_04_081114 Figure 1: Single-Ended Test Setup X-Ref Target - Figure 2 FPGA Output + C R V REF REF MEAS – DS182_05_080814 Figure 2: Differential Test Setup Parameters V , R , C , and V fully describe the test conditions for each I/O standard. The most accurate prediction REF REF REF MEAS of propagation delay in any given application can be obtained through IBIS simulation, using this method: 1. Simulate the output driver of choice into the generalized test setup using values from Table24. 2. Record the time to V . MEAS 3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to V . MEAS DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 27

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics 5. Compare the results of step2 and step4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. Table 24: Output Delay Measurement Methodology R C (1) V V Description I/O Standard Attribute REF REF MEAS REF (Ω) (pF) (V) (V) LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 LVCMOS/LVDCI/HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 1M 0 0.75 0 LVCMOS/LVDCI/HSLVDCI, 1.8V LVCMOS18, LVDCI_15, HSLVDCI_18 1M 0 0.9 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0 LVTTL, 3.3V LVTTL 1M 0 1.65 0 PCI33, 3.3V PCI33_3 25 10 1.65 0 HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 V 0.6 REF HSTL, Class I, 1.5V HSTL_I 50 0 V 0.75 REF HSTL, Class II, 1.5V HSTL_II 25 0 V 0.75 REF HSTL, Class I, 1.8V HSTL_I_18 50 0 V 0.9 REF HSTL, Class II, 1.8V HSTL_II_18 25 0 V 0.9 REF HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 V 0.6 REF SSTL12, 1.2V SSTL12 50 0 V 0.6 REF SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 V 0.675 REF SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 V 0.75 REF SSTL (Stub Series Terminated Logic), SSTL18_I, SSTL18_II 50 0 V 0.9 REF Class I & ClassII, 1.8V DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 V 0.9 REF DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 V 0.6 REF DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 V 0.75 REF DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 V 0.9 REF DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 V 0.6 REF DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 V 0.6 REF DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 V 0.675 REF DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 V 0.75 REF DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 V 0.9 REF LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 100 0 0(2) 0 LVDS, 2.5V LVDS_25 100 0 0(2) 0 BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0 Mini LVDS, 2.5V MINI_LVDS_25 100 0 0(2) 0 PPDS_25 PPDS_25 100 0 0(2) 0 RSDS_25 RSDS_25 100 0 0(2) 0 TMDS_33 TMDS_33 50 0 0(2) 3.3 Notes: 1. C is the capacitance of the probe, nominally 0 pF. REF 2. The value given is the differential output voltage. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 28

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Logic Switching Characteristics Table 25: ILOGIC Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold T / CE1 pin Setup/Hold with respect to 0.42/0.00 0.48/0.00 0.67/0.00 0.67/0.00 0.48/0.00 0.56/–0.16 ns ICE1CK T CLK ICKCE1 T /T SR pin Setup/Hold with respect to CLK 0.53/0.01 0.61/0.01 0.99/0.01 0.99/0.01 0.61/0.01 0.88/–0.30 ns ISRCK ICKSR T / D pin Setup/Hold with respect to CLK 0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 0.01/0.29 0.01/0.41 ns IDOCKE2 T without Delay (HP I/O banks only) IOCKDE2 T / DDLY pin Setup/Hold with respect to 0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 0.02/0.29 0.01/0.41 ns IDOCKDE2 T CLK (using IDELAY) (HP I/O banks IOCKDDE2 only) T / D pin Setup/Hold with respect to CLK 0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 0.01/0.29 0.01/0.41 ns IDOCKE3 T without Delay (HR I/O banks only) IOCKDE3 T / DDLY pin Setup/Hold with respect to 0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 0.02/0.29 0.01/0.41 ns IDOCKDE3 T CLK (using IDELAY) (HR I/O banks IOCKDDE3 only) Combinatorial T D pin to O pin propagation delay, no 0.09 0.10 0.12 0.12 0.10 0.14 ns IDIE2 Delay (HP I/O banks only) T DDLY pin to O pin propagation delay 0.10 0.11 0.13 0.13 0.11 0.15 ns IDIDE2 (using IDELAY) (HP I/O banks only) T D pin to O pin propagation delay, no 0.09 0.10 0.12 0.12 0.10 0.14 ns IDIE3 Delay (HR I/O banks only) T DDLY pin to O pin propagation delay 0.10 0.11 0.13 0.13 0.11 0.15 ns IDIDE3 (using IDELAY) (HR I/O banks only) Sequential Delays T D pin to Q1 pin using flip-flop as a latch 0.36 0.39 0.45 0.45 0.39 0.54 ns IDLOE2 without Delay (HP I/O banks only) T DDLY pin to Q1 pin using flip-flop as a 0.36 0.39 0.45 0.45 0.39 0.55 ns IDLODE2 latch (using IDELAY) (HP I/O banks only) T D pin to Q1 pin using flip-flop as a latch 0.36 0.39 0.45 0.45 0.39 0.54 ns IDLOE3 without Delay (HR I/O banks only) T DDLY pin to Q1 pin using flip-flop as a 0.36 0.39 0.45 0.45 0.39 0.55 ns IDLODE3 latch (using IDELAY) (HR I/O banks only) T CLK to Q outputs 0.47 0.50 0.58 0.58 0.50 0.71 ns ICKQ T SR pin to OQ/TQ out (HP I/O banks 0.84 0.94 1.16 1.16 0.94 1.32 ns RQ_ILOGICE2 only) T Global Set/Reset to Q outputs 7.60 7.60 10.51 10.51 7.60 11.39 ns GSRQ_ILOGICE2 (HP I/O banks only) T SR pin to OQ/TQ out 0.84 0.94 1.16 1.16 0.94 1.32 ns RQ_ILOGICE3 (HR I/O banks only) T Global Set/Reset to Q outputs 7.60 7.60 10.51 10.51 7.60 11.39 ns GSRQ_ILOGICE3 (HR I/O banks only) DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 29

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 25: ILOGIC Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Set/Reset T Minimum Pulse Width, SR inputs (HP 0.54 0.63 0.63 0.63 0.63 0.68 ns, RPW_ILOGICE2 I/O banks only) Min T Minimum Pulse Width, SR inputs (HR 0.54 0.63 0.63 0.63 0.63 0.68 ns, RPW_ILOGICE3 I/O banks only) Min Table 26: OLOGIC Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold T /T D1/D2 pins Setup/Hold with 0.45/–0.13 0.50/–0.13 0.58/–0.13 0.58/–0.13 0.50/–0.13 0.79/–0.18 ns ODCK OCKD respect to CLK T / OCE pin Setup/Hold with 0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 0.29/0.03 0.35/–0.10 ns OOCECK T respect to CLK OCKOCE T /T SR pin Setup/Hold with respect 0.32/0.18 0.38/0.18 0.70/0.18 0.70/0.18 0.38/0.18 0.62/–0.04 ns OSRCK OCKSR to CLK T /T T1/T2 pins Setup/Hold with 0.49/–0.16 0.56/–0.16 0.68/–0.16 0.68/–0.13 0.56/–0.16 0.67/–0.18 ns OTCK OCKT respect to CLK T / TCE pin Setup/Hold with 0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.06 0.30/0.01 0.31/–0.10 ns OTCECK T respect to CLK OCKTCE Combinatorial T D1 to OQ out or T1 to TQ out 0.73 0.81 0.97 0.97 0.81 1.18 ns ODQ Sequential Delays T CLK to OQ/TQ out 0.41 0.43 0.49 0.49 0.43 0.63 ns OCKQ T SR pin to OQ/TQ out (HP I/O 0.63 0.70 0.83 0.83 0.70 1.12 ns RQ_OLOGICE2 banks only) T Global Set/Reset to Q outputs 7.60 7.60 10.51 10.51 7.60 11.39 ns GSRQ_OLOGICE2 (HP I/O banks only) T SR pin to OQ/TQ out (HR I/O 0.63 0.70 0.83 0.83 0.70 1.12 ns RQ_OLOGICE3 banks only) T Global Set/Reset to Q outputs 7.60 7.60 10.51 10.51 7.60 11.39 ns GSRQ_OLOGICE3 (HR I/O banks only) Set/Reset T Minimum Pulse Width, SR 0.54 0.54 0.63 0.63 0.54 0.68 ns, RPW_OLOGICE2 inputs (HP I/O banks only) Min T Minimum Pulse Width, SR 0.54 0.54 0.63 0.63 0.54 0.68 ns, RPW_OLOGICE3 inputs (HR I/O banks only) Min DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 30

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 27: ISERDES Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold for Control Lines T / BITSLIP pin Setup/Hold with 0.01/0.12 0.02/0.13 0.02/0.15 0.02/0.15 0.02/0.13 0.02/0.21 ns ISCCK_BITSLIP T respect to CLKDIV ISCKC_BITSLIP T / CE pin Setup/Hold with respect 0.39/–0.02 0.44/–0.02 0.63/–0.02 0.63/–0.02 0.44/–0.02 0.51/–0.22 ns ISCCK_CE T (2) to CLK (for CE1) ISCKC_CE T / CE pin Setup/Hold with respect –0.12/0.29 –0.12/0.31 –0.12/0.35 –0.12/0.35 –0.12/0.31 –0.17/0.40 ns ISCCK_CE2 T (2) to CLKDIV (for CE2) ISCKC_CE2 Setup/Hold for Data Lines T / D pin Setup/Hold with respect –0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.04/0.19 ns ISDCK_D T to CLK ISCKD_D T / DDLY pin Setup/Hold with –0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.03/0.19 ns ISDCK_DDLY T respect to CLK (using ISCKD_DDLY IDELAY)(1) T / D pin Setup/Hold with respect –0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.04/0.19 ns ISDCK_D_DDR T to CLK at DDR mode ISCKD_D_DDR T / D pin Setup/Hold with respect 0.11/0.11 0.12/0.12 0.15/0.15 0.15/0.15 0.12/0.12 0.19/0.19 ns ISDCK_DDLY_DDR T to CLK at DDR mode (using ISCKD_DDLY_DDR IDELAY)(1) Sequential Delays T CLKDIV to out at Q pin 0.46 0.47 0.58 0.58 0.47 0.67 ns ISCKO_Q Propagation Delays T D input to DO output pin 0.09 0.10 0.12 0.12 0.10 0.14 ns ISDO_DO Notes: 1. Recorded at 0 tap value. 2. T and T are reported as T /T in the timing report. ISCCK_CE2 ISCKC_CE2 ISCCK_CE ISCKC_CE DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 31

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Output Serializer/Deserializer Switching Characteristics Table 28: OSERDES Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold T / D input Setup/Hold with respect 0.37/0.02 0.40/0.02 0.55/0.02 0.55/0.02 0.40/0.02 0.44/–0.24 ns OSDCK_D T to CLKDIV OSCKD_D T / T input Setup/Hold with respect 0.49/–0.15 0.56/–0.15 0.68/–0.15 0.68/–0.15 0.56/–0.15 0.67/–0.25 ns OSDCK_T T (1) to CLK OSCKD_T T / T input Setup/Hold with respect 0.27/–0.15 0.30/–0.15 0.34/–0.15 0.34/–0.15 0.30/–0.15 0.46/–0.25 ns OSDCK_T2 T (1) to CLKDIV OSCKD_T2 T / OCE input Setup/Hold with 0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 0.29/0.03 0.35/–0.15 ns OSCCK_OCE T respect to CLK OSCKC_OCE T SR (Reset) input Setup with 0.41 0.46 0.75 0.75 0.46 0.70 ns OSCCK_S respect to CLKDIV T / TCE input Setup/Hold with 0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.01 0.30/0.01 0.31/–0.15 ns OSCCK_TCE T respect to CLK OSCKC_TCE Sequential Delays T Clock to out from CLK to OQ 0.35 0.37 0.42 0.42 0.37 0.54 ns OSCKO_OQ T Clock to out from CLK to TQ 0.41 0.43 0.49 0.49 0.43 0.63 ns OSCKO_TQ Combinatorial T T input to TQ Out 0.73 0.81 0.97 0.97 0.81 1.18 ns OSDO_TTQ Notes: 1. T and T are reported as T /T in the timing report. OSDCK_T2 OSCKD_T2 OSDCK_T OSCKD_T DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 32

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Delay Switching Characteristics Table 29: Input/Output Delay Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE IDELAYCTRL T Reset to Ready for IDELAYCTRL 3.22 3.22 3.22 3.22 3.22 3.22 µs DLYCCO_RDY F Attribute 200.00 200.00 200.00 200.00 200.00 200.00 MHz IDELAYCTRL_REF REFCLK frequency=200.00(1) Attribute 300.00 300.00 N/A N/A 300.00 N/A MHz REFCLK frequency=300.00(1) Attribute 400.00 400.00 N/A N/A 400.00 N/A MHz REFCLK frequency=400.00(1) IDELAYCTRL_REF REFCLK precision ±10 ±10 ±10 ±10 ±10 ±10 MHz _PRECISION T Minimum Reset pulse width 52.00 52.00 52.00 52.00 52.00 52.00 ns IDELAYCTRL_RPW IDELAY/ODELAY T IDELAY/ODELAY chain delay 1/(32x2xF ) µs IDELAYRESOLUTION REF resolution Pattern dependent period jitter in 0 0 0 0 0 0 ps delay chain for clock pattern.(2) per tap Pattern dependent period jitter in ±5 ±5 ±5 ±5 ±5 ±5 ps T and delay chain for random data pattern per tap IDELAYPAT_JIT T (PRBS 23)(3) ODELAYPAT_JIT Pattern dependent period jitter in ±9 ±9 ±9 ±9 ±9 ±9 ps delay chain for random data pattern per tap (PRBS 23)(4) T / Maximum frequency of CLK input to 800.00 800.00 710.00 710.00 800.00 710.00 MHz IDELAY_CLK_MAX T IDELAY/ODELAY ODELAY_CLK_MAX T / CE pin Setup/Hold with respect to C 0.11/0.10 0.14/0.12 0.18/0.14 0.18/0.14 0.14/0.12 0.14/0.16 ns IDCCK_CE T for IDELAY IDCKC_CE T / CE pin Setup/Hold with respect to C 0.14/0.03 0.16/0.04 0.19/0.05 0.19/0.05 0.16/0.04 0.28/0.06 ns ODCCK_CE T for ODELAY ODCKC_CE T / INC pin Setup/Hold with respect to 0.10/0.14 0.12/0.16 0.14/0.20 0.14/0.20 0.12/0.16 0.10/0.23 ns IDCCK_INC T C for IDELAY IDCKC_INC T / INC pin Setup/Hold with respect to 0.10/0.07 0.12/0.08 0.13/0.09 0.13/0.09 0.12/0.08 0.19/0.16 ns ODCCK_INC T C for ODELAY ODCKC_INC T / RST pin Setup/Hold with respect to 0.13/0.08 0.14/0.10 0.16/0.12 0.16/0.12 0.14/0.10 0.22/0.19 ns IDCCK_RST T C for IDELAY IDCKC_RST T / RST pin Setup/Hold with respect to 0.16/0.04 0.19/0.06 0.24/0.08 0.24/0.08 0.19/0.06 0.32/0.11 ns ODCCK_RST T C for ODELAY ODCKC_RST T Propagation delay through IDELAY Note5 Note5 Note5 Note5 Note5 Note5 ps IDDO_IDATAIN T Propagation delay through Note5 Note5 Note5 Note5 Note5 Note5 ps ODDO_ODATAIN ODELAY Notes: 1. Average Tap Delay at 200 MHz=78ps, at 300MHz=52ps, and at 400MHz=39ps. 2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. 3. When HIGH_PERFORMANCE mode is set to TRUE. 4. When HIGH_PERFORMANCE mode is set to FALSE. 5. Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 33

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 30: IO_FIFO Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE IO_FIFO Clock to Out Delays T RDCLK to Q outputs 0.51 0.56 0.63 0.63 0.56 0.81 ns OFFCKO_DO T Clock to IO_FIFO Flags 0.59 0.62 0.81 0.81 0.62 0.77 ns CKO_FLAGS Setup/Hold T / D inputs to WRCLK 0.43/–0.01 0.47/–0.01 0.53/–0.01 0.53/0.09 0.47/–0.01 0.76/–0.05 ns CCK_D T CKC_D T / WREN to WRCLK 0.39/–0.01 0.43/–0.01 0.50/–0.01 0.50/–0.01 0.43/–0.01 0.70/–0.05 ns IFFCCK_WREN T IFFCKC_WREN T / RDEN to RDCLK 0.49/0.01 0.53/0.02 0.61/0.02 0.61/0.02 0.53/0.02 0.79/–0.02 ns OFFCCK_RDEN T OFFCKC_RDEN Minimum Pulse Width T RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.08 0.92 1.29 ns PWH_IO_FIFO T RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.08 0.92 1.29 ns PWL_IO_FIFO Maximum Frequency F RDCLK and WRCLK 533.05 470.37 400.00 400.00 470.37 333.33 MHz MAX DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 34

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Switching Characteristics Table 31: CLB Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Combinatorial Delays T An–Dn LUT address to A 0.05 0.05 0.06 0.06 0.05 0.07 ns, Max ILO T An–Dn LUT address to AMUX/CMUX 0.15 0.16 0.19 0.19 0.16 0.22 ns, Max ILO_2 T An–Dn LUT address to BMUX_A 0.24 0.25 0.30 0.30 0.25 0.37 ns, Max ILO_3 T An–Dn inputs to A–D Q outputs 0.58 0.61 0.74 0.74 0.61 0.91 ns, Max ITO T AX inputs to AMUX output 0.38 0.40 0.49 0.49 0.40 0.62 ns, Max AXA T AX inputs to BMUX output 0.40 0.42 0.52 0.52 0.42 0.66 ns, Max AXB T AX inputs to CMUX output 0.39 0.41 0.50 0.50 0.41 0.62 ns, Max AXC T AX inputs to DMUX output 0.43 0.44 0.52 0.52 0.44 0.67 ns, Max AXD T BX inputs to BMUX output 0.31 0.33 0.40 0.40 0.33 0.51 ns, Max BXB T BX inputs to DMUX output 0.38 0.39 0.47 0.47 0.39 0.62 ns, Max BXD T CX inputs to CMUX output 0.27 0.28 0.34 0.34 0.28 0.43 ns, Max CXC T CX inputs to DMUX output 0.33 0.34 0.41 0.41 0.34 0.54 ns, Max CXD T DX inputs to DMUX output 0.32 0.33 0.40 0.40 0.33 0.52 ns, Max DXD Sequential Delays T Clock to AQ–DQ outputs 0.26 0.27 0.32 0.32 0.27 0.40 ns, Max CKO T Clock to AMUX – DMUX outputs 0.32 0.32 0.39 0.39 0.32 0.46 ns, Max SHCKO Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK T /T A –D input to CLK on 0.01/0.12 0.02/0.13 0.03/0.18 0.03/0.24 0.02/0.13 0.02/0.18 ns, Min AS AH N N A–D flip-flops T /T A –D input to CLK on 0.04/0.14 0.04/0.14 0.05/0.20 0.05/0.26 0.04/0.14 0.05/0.21 ns, Min DICK CKDI X X A–D flip-flops A –D input through MUXs and/or 0.36/0.10 0.37/0.11 0.46/0.16 0.46/0.22 0.37/0.11 0.56/0.15 ns, Min X X carry logic to CLK on A–D flip-flops T / CE input to CLK on A–D flip-flops 0.19/0.05 0.20/0.05 0.25/0.05 0.25/0.11 0.20/0.05 0.24/0.04 ns, Min CECK_CLB T CKCE_CLB T /T SR input to CLK on A–D flip-flops 0.30/0.05 0.31/0.07 0.37/0.09 0.37/0.22 0.31/0.07 0.48/0.05 ns, Min SRCK CKSR Set/Reset T SR input minimum pulse width 0.52 0.78 1.04 1.04 0.78 0.95 ns, Min SRMIN T Delay from SR input to 0.38 0.38 0.46 0.46 0.38 0.59 ns, Max RQ AQ–DQ flip-flops T Delay from CE input to 0.34 0.35 0.43 0.43 0.35 0.54 ns, Max CEO AQ–DQ flip-flops F Toggle frequency (for export control) 1818 1818 1818 1818 1818 1286 MHz TOG DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 35

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 32: CLB Distributed RAM Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Sequential Delays T Clock to A–B outputs 0.68 0.70 0.85 0.85 0.70 1.08 ns, Max SHCKO T Clock to AMUX–BMUX outputs 0.91 0.95 1.15 1.15 0.95 1.44 ns, Max SHCKO_1 Setup and Hold Times Before/After Clock CLK T / A–D inputs to CLK 0.45/0.23 0.45/0.24 0.54/0.27 0.54/0.28 0.45/0.24 0.69/0.33 ns, Min DS_LRAM T DH_LRAM T / Address An inputs to clock 0.13/0.50 0.14/0.50 0.17/0.58 0.17/0.61 0.14/0.50 0.21/0.63 ns, Min AS_LRAM T AH_LRAM Address An inputs through MUXs 0.40/0.16 0.42/0.17 0.52/0.23 0.52/0.29 0.42/0.17 0.63/0.23 ns, Min and/or carry logic to clock T / WE input to clock 0.29/0.09 0.30/0.09 0.36/0.09 0.36/0.11 0.30/0.09 0.46/0.10 ns, Min WS_LRAM T WH_LRAM T / CE input to CLK 0.29/0.09 0.30/0.09 0.37/0.09 0.37/0.11 0.30/0.09 0.47/0.10 ns, Min CECK_LRAM T CKCE_LRAM Clock CLK T Minimum pulse width 0.68 0.77 0.91 0.91 0.77 1.11 ns, Min MPW T Minimum clock period 1.35 1.54 1.82 1.82 1.54 2.22 ns, Min MCP Notes: 1. T also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path. SHCKO CLB Shift Register Switching Characteristics (SLICEM Only) Table 33: CLB Shift Register Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Sequential Delays T Clock to A–D outputs 0.96 0.98 1.20 1.20 0.98 1.35 ns, Max REG T Clock to AMUX–DMUX output 1.19 1.23 1.50 1.50 1.23 1.72 ns, Max REG_MUX T Clock to DMUX output via M31 0.89 0.91 1.10 1.10 0.91 1.25 ns, Max REG_M31 output Setup and Hold Times Before/After Clock CLK T / WE input 0.26/0.09 0.27/0.09 0.33/0.09 0.33/0.11 0.27/0.09 0.41/0.10 ns, Min WS_SHFREG T WH_SHFREG T / CE input to CLK 0.27/0.09 0.28/0.09 0.33/0.09 0.33/0.11 0.28/0.09 0.42/0.10 ns, Min CECK_SHFREG T CKCE_SHFREG T / A–D inputs to CLK 0.28/0.26 0.28/0.26 0.33/0.30 0.33/0.36 0.28/0.26 0.41/0.36 ns, Min DS_SHFREG T DH_SHFREG Clock CLK T Minimum pulse width 0.55 0.65 0.78 0.78 0.65 0.91 ns, Min MPW_SHFREG DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 36

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Block RAM and FIFO Switching Characteristics Table 34: Block RAM and FIFO Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Block RAM and FIFO Clock-to-Out Delays T and Clock CLK to DOUT output 1.57 1.80 2.08 2.08 1.80 2.44 ns, Max RCKO_DO T (1) (without output register)(2)(3) RCKO_DO_REG Clock CLK to DOUT output (with 0.54 0.63 0.75 0.75 0.63 0.86 ns, Max output register)(4)(5) T and Clock CLK to DOUT output with 2.35 2.58 3.26 3.26 2.58 4.49 ns, Max RCKO_DO_ECC T ECC (without output RCKO_DO_ECC_REG register)(2)(3) Clock CLK to DOUT output with 0.62 0.69 0.80 0.80 0.69 0.94 ns, Max ECC (with output register)(4)(5) T and Clock CLK to DOUT output with 2.21 2.45 2.80 2.80 2.45 3.19 ns, Max RCKO_DO_CASCOUT T Cascade (without output RCKO_DO_CASCOUT_REG register)(2) Clock CLK to DOUT output with 0.98 1.08 1.24 1.24 1.08 1.32 ns, Max Cascade (with output register)(4) T Clock CLK to FIFO flags 0.65 0.74 0.89 0.89 0.74 0.97 ns, Max RCKO_FLAGS outputs(6) T Clock CLK to FIFO pointers 0.79 0.87 0.98 0.98 0.87 1.10 ns, Max RCKO_POINTERS outputs(7) T Clock CLK to ECCPARITY in 0.66 0.72 0.80 0.80 0.72 0.93 ns, Max RCKO_PARITY_ECC ECC encode only mode T and Clock CLK to BITERR (without 2.17 2.38 3.01 3.01 2.38 4.15 ns, Max RCKO_SDBIT_ECC T output register) RCKO_SDBIT_ECC_REG Clock CLK to BITERR (with 0.57 0.65 0.76 0.76 0.65 0.89 ns, Max output register) T and Clock CLK to RDADDR output 0.64 0.74 0.90 0.90 0.74 0.98 ns, Max RCKO_RDADDR_ECC T with ECC (without output RCKO_RDADDR_ECC_REG register) Clock CLK to RDADDR output 0.71 0.79 0.92 0.92 0.79 1.10 ns, Max with ECC (with output register) Setup and Hold Times Before/After Clock CLK T / ADDR inputs(8) 0.38/ 0.42/ 0.48/ 0.48/ 0.42/ 0.65/ ns, Min RCCK_ADDRA T 0.27 0.28 0.31 0.38 0.28 0.38 RCKC_ADDRA T / Data input setup/hold time when 0.49/ 0.55/ 0.63/ 0.63/ 0.55/ 0.78/ ns, Min RDCK_DI_WF_NC T blockRAM is configured in 0.51 0.53 0.57 0.57 0.53 0.64 RCKD_DI_WF_NC WRITE_FIRST or NO_CHANGE mode(9) T / Data input setup/hold time when 0.17/ 0.19/ 0.21/ 0.21/ 0.19/ 0.25/ ns, Min RDCK_DI_RF T blockRAM is configured in 0.25 0.29 0.35 0.35 0.29 0.32 RCKD_DI_RF READ_FIRST mode(9) T / DIN inputs with block RAM ECC 0.42/ 0.47/ 0.53/ 0.53/ 0.47/ 0.66/ ns, Min RDCK_DI_ECC T in standard mode(9) 0.37 0.39 0.43 0.58 0.39 0.46 RCKD_DI_ECC T / DIN inputs with block RAM ECC 0.79/ 0.87/ 0.99/ 0.99/ 0.87/ 1.17/ ns, Min RDCK_DI_ECCW T encode only(9) 0.37 0.39 0.43 0.58 0.39 0.41 RCKD_DI_ECCW T / DIN inputs with FIFO ECC in 0.89/ 0.98/ 1.12/ 1.12/ 0.98/ 1.32/ ns, Min RDCK_DI_ECC_FIFO T standard mode(9) 0.47 0.50 0.54 0.69 0.50 0.65 RCKD_DI_ECC_FIFO DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 37

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 34: Block RAM and FIFO Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T / Inject single/double bit error in 0.49/ 0.55/ 0.63/ 0.63/ 0.55/ 0.78/ ns, Min RCCK_INJECTBITERR T ECC mode 0.30 0.31 0.34 0.43 0.31 0.41 RCKC_INJECTBITERR T /T Block RAM Enable (EN) input 0.30/ 0.33/ 0.38/ 0.38/ 0.33/ 0.48/ ns, Min RCCK_EN RCKC_EN 0.17 0.18 0.20 0.32 0.18 0.22 T / CE input of output register 0.21/ 0.25/ 0.31/ 0.31/ 0.25/ 0.34/ ns, Min RCCK_REGCE T 0.13 0.13 0.14 0.19 0.13 0.16 RCKC_REGCE T / Synchronous RSTREG input 0.25/ 0.27/ 0.29/ 0.29/ 0.27/ 0.35/ ns, Min RCCK_RSTREG T 0.06 0.06 0.06 0.14 0.06 0.06 RCKC_RSTREG T / Synchronous RSTRAM input 0.27/ 0.29/ 0.31/ 0.31/ 0.29/ 0.34/ ns, Min RCCK_RSTRAM T 0.35 0.37 0.39 0.39 0.37 0.40 RCKC_RSTRAM T / Write Enable (WE) input (Block 0.38/ 0.41/ 0.46/ 0.46/ 0.41/ 0.54/ ns, Min RCCK_WEA T RAM only) 0.15 0.16 0.17 0.29 0.16 0.19 RCKC_WEA T / WREN FIFO inputs 0.39/ 0.39/ 0.40/ 0.40/ 0.39/ 0.65/ ns, Min RCCK_WREN T 0.25 0.30 0.37 0.49 0.30 0.37 RCKC_WREN T / RDEN FIFO inputs 0.36/ 0.36/ 0.37/ 0.37/ 0.36/ 0.60/ ns, Min RCCK_RDEN T 0.26 0.30 0.37 0.49 0.30 0.38 RCKC_RDEN Reset Delays T Reset RST to FIFO 0.76 0.83 0.93 0.93 0.83 1.06 ns, Max RCO_FLAGS flags/pointers(10) T / FIFO reset recovery and removal 1.59/ 1.76/ 2.01/ 2.01/ 1.76/ 2.07/ ns, Max RREC_RST T timing(11) –0.68 –0.68 –0.68 –0.68 –0.68 –0.60 RREM_RST Maximum Frequency F Block RAM 601.32 543.77 458.09 458.09 543.77 372.44 MHz MAX_BRAM_WF_NC (Write first and No change modes) When not in SDP RF mode F Block RAM 601.32 543.77 458.09 458.09 543.77 372.44 MHz MAX_BRAM_RF (Read first, Performance mode) _PERFORMANCE When in SDP RF mode but no address overlap between port A and port B F Block RAM 528.26 477.33 400.80 400.80 477.33 317.36 MHz MAX_BRAM_RF_ (Read first, Delayed_write mode) DELAYED_WRITE When in SDP RF mode and there is possibility of overlap between port A and port B addresses F Block RAM Cascade 551.27 493.83 408.00 408.00 493.83 322.48 MHz MAX_CAS_WF_NC (Write first, No change mode) When cascade but not in RF mode F Block RAM Cascade 551.27 493.83 408.00 408.00 493.83 322.48 MHz MAX_CAS_RF (Read first, Performance mode) _PERFORMANCE When in cascade with RF mode and no possibility of address overlap/one port is disabled DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 38

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 34: Block RAM and FIFO Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE F When in cascade RF mode and 478.24 427.35 350.88 350.88 427.35 267.38 MHz MAX_CAS_RF_ there is a possibility of address DELAYED_WRITE overlap between port A and port B F FIFO in all modes without ECC 601.32 543.77 458.09 458.09 543.77 372.44 MHz MAX_FIFO F Block RAM and FIFO in ECC 484.26 430.85 351.12 351.12 430.85 254.13 MHz MAX_ECC configuration Notes: 1. The timing report shows all of these parameters as T . RCKO_DO 2. T includes T , T , and T as well as the B port equivalent timing parameters. RCKO_DOR RCKO_DOW RCKO_DOPR RCKO_DOPW 3. These parameters also apply to synchronous FIFO with DO_REG=0. 4. T includes T as well as the B port equivalent timing parameters. RCKO_DO RCKO_DOP 5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG=1. 6. T includes the following parameters: T , T , T , T , T , T RCKO_FLAGS RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR. 7. T includes both T and T RCKO_POINTERS RCKO_RDCOUNT RCKO_WRCOUNT. 8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 9. These parameters include both A and B inputs as well as the parity inputs of A and B. 10. T includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. RCO_FLAGS 11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK). DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 39

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DSP48E1 Switching Characteristics Table 35: DSP48E1 Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup and Hold Times of Data/Control Pins to the Input Register Clock T / A input to Aregister CLK 0.24/ 0.27/ 0.31/ 0.33/ 0.27/ 0.38/ ns DSPDCK_A_AREG T 0.12 0.14 0.16 0.18 0.14 0.12 DSPCKD_A_AREG T / B input to Bregister CLK 0.28/ 0.32/ 0.39/ 0.41/ 0.32/ 0.51/ ns DSPDCK_B_BREG T 0.13 0.14 0.15 0.18 0.14 0.16 DSPCKD_B_BREG T / C input to Cregister CLK 0.15/ 0.17/ 0.20/ 0.20/ 0.17/ 0.31/ ns DSPDCK_C_CREG T 0.15 0.17 0.20 0.22 0.17 0.21 DSPCKD_C_CREG T / D input to Dregister CLK 0.21/ 0.27/ 0.35/ 0.35/ 0.27/ 0.46/ ns DSPDCK_D_DREG T 0.19 0.22 0.26 0.27 0.22 0.20 DSPCKD_D_DREG T / ACIN input to A register CLK 0.21/ 0.24/ 0.27/ 0.30/ 0.24/ 0.31/ ns DSPDCK_ACIN_AREG T 0.12 0.14 0.16 0.16 0.14 0.12 DSPCKD_ACIN_AREG T / BCIN input to B register CLK 0.22/ 0.25/ 0.30/ 0.32/ 0.25/ 0.34/ ns DSPDCK_BCIN_BREG T 0.13 0.14 0.15 0.15 0.14 0.16 DSPCKD_BCIN_BREG Setup and Hold Times of Data Pins to the Pipeline Register Clock T / {A, B} input to Mregister CLK 2.04/ 2.34/ 2.79/ 2.79/ 2.34/ 3.66/ ns DSPDCK_{A, B}_MREG_MULT T using multiplier –0.01 –0.01 –0.01 –0.01 –0.01 –0.06 DSPCKD_{A, B}_MREG_MULT T / {A, D} input to AD register CLK 1.09/ 1.25/ 1.49/ 1.49/ 1.25/ 1.94/ ns DSPDCK_{A, D}_ADREG T –0.02 –0.02 –0.02 –0.02 –0.02 –0.23 DSPCKD_{A, D}_ADREG Setup and Hold Times of Data/Control Pins to the Output Register Clock T / {A, B,} input to Pregister CLK 3.41/ 3.90/ 4.64/ 4.64/ 3.90/ 5.89/ ns DSPDCK_{A, B}_PREG_MULT TDSPCKD_{A, B} _PREG_MULT using multiplier –0.24 –0.24 –0.24 –0.24 –0.24 –0.41 T / D input to P register CLK 3.33/ 3.81/ 4.53/ 4.53/ 3.81/ 5.70/ ns DSPDCK_D_PREG_MULT T using multiplier –0.62 –0.62 –0.62 –0.62 –0.62 –1.42 DSPCKD_D_PREG_MULT T / A or B input to Pregister CLK 1.47/ 1.68/ 2.00/ 2.00/ 1.68/ 2.37/ ns DSPDCK_{A, B} _PREG TDSPCKD_{A, B} _PREG not using multiplier –0.24 –0.24 –0.24 –0.24 –0.24 –0.41 T / C input to Pregister CLK not 1.30/ 1.49/ 1.78/ 1.78/ 1.49/ 2.11/ ns DSPDCK_C_PREG T using multiplier –0.22 –0.22 –0.22 –0.22 –0.22 –0.36 DSPCKD_C_PREG T / PCIN input to Pregister CLK 1.12/ 1.28/ 1.52/ 1.52/ 1.28/ 1.81/ ns DSPDCK_PCIN_PREG T –0.13 –0.13 –0.13 –0.13 –0.13 –0.21 DSPCKD_PCIN_PREG Setup and Hold Times of the CE Pins T / {CEA; CEB} input to {A; B} 0.30/ 0.36/ 0.44/ 0.44/ 0.36/ 0.55/ ns DSPDCK_{CEA;CEB}_{AREG;BREG} TDSPCKD_{CEA;CEB}_{AREG;BREG} register CLK 0.05 0.06 0.09 0.09 0.06 0.09 T / CEC input to Cregister CLK 0.24/ 0.29/ 0.36/ 0.36/ 0.29/ 0.43/ ns DSPDCK_CEC_CREG T 0.08 0.09 0.11 0.11 0.09 0.11 DSPCKD_CEC_CREG T / CED input to Dregister CLK 0.31/ 0.36/ 0.44/ 0.44/ 0.36/ 0.58/ ns DSPDCK_CED_DREG T –0.02 –0.02 –0.02 0.02 –0.02 0.12 DSPCKD_CED_DREG T / CEM input to Mregister CLK 0.26/ 0.29/ 0.33/ 0.33/ 0.29/ 0.39/ ns DSPDCK_CEM_MREG T 0.15 0.17 0.20 0.20 0.17 0.25 DSPCKD_CEM_MREG T / CEP input to Pregister CLK 0.31/ 0.36/ 0.45/ 0.45/ 0.36/ 0.54/ ns DSPDCK_CEP_PREG T 0.01 0.01 0.01 0.01 0.01 0.00 DSPCKD_CEP_PREG DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 40

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 35: DSP48E1 Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup and Hold Times of the RST Pins T / {RSTA, RSTB} input to {A, B} 0.34/ 0.39/ 0.47/ 0.47/ 0.39/ 0.53/ ns DSPDCK_{RSTA; RSTB}_{AREG; BREG} TDSPCKD_{RSTA; RSTB}_{AREG; BREG} register CLK 0.10 0.11 0.13 0.14 0.11 0.34 T / RSTC input to Cregister CLK 0.06/ 0.07/ 0.08/ 0.08/ 0.07/ 0.08/ ns DSPDCK_RSTC_CREG T 0.22 0.24 0.26 0.26 0.24 0.31 DSPCKD_RSTC_CREG T / RSTD input to Dregister CLK 0.37/ 0.42/ 0.50/ 0.50/ 0.42/ 0.57/ ns DSPDCK_RSTD_DREG T 0.06 0.06 0.07 0.07 0.06 0.07 DSPCKD_RSTD_DREG T / RSTM input to Mregister CLK 0.18/ 0.20/ 0.23/ 0.23/ 0.20/ 0.24/ ns DSPDCK_RSTM_MREG T 0.18 0.21 0.24 0.24 0.21 0.29 DSPCKD_RSTM_MREG T / RSTP input to Pregister CLK 0.24/ 0.26/ 0.30/ 0.30/ 0.26/ 0.37/ ns DSPDCK_RSTP_PREG T 0.01 0.01 0.01 0.11 0.01 0.00 DSPCKD_RSTP_PREG Combinatorial Delays from Input Pins to Output Pins T A input to CARRYOUT output 3.21 3.69 4.39 4.39 3.69 5.60 ns DSPDO_A_CARRYOUT_MULT using multiplier T D input to P output using 3.15 3.61 4.30 4.30 3.61 5.44 ns DSPDO_D_P_MULT multiplier T A input to P output not using 1.30 1.48 1.76 1.76 1.48 2.10 ns DSPDO_A_P multiplier T C input to P output 1.13 1.30 1.55 1.55 1.30 1.84 ns DSPDO_C_P Combinatorial Delays from Input Pins to Cascading Output Pins T {A, B} input to {ACOUT, 0.47 0.53 0.63 0.63 0.53 0.75 ns DSPDO_{A; B}_{ACOUT; BCOUT} BCOUT} output T {A, B} input to 3.44 3.94 4.69 4.69 3.94 5.96 ns DSPDO_{A, B}_CARRYCASCOUT_MULT CARRYCASCOUT output using multiplier T D input to CARRYCASCOUT 3.36 3.85 4.58 4.58 3.85 5.77 ns DSPDO_D_CARRYCASCOUT_MULT output using multiplier T {A, B} input to 1.50 1.72 2.04 2.04 1.72 2.44 ns DSPDO_{A, B}_CARRYCASCOUT CARRYCASCOUT output not using multiplier T C input to CARRYCASCOUT 1.34 1.53 1.83 1.83 1.53 2.18 ns DSPDO_C_CARRYCASCOUT output Combinatorial Delays from Cascading Input Pins to All Output Pins T ACIN input to P output using 3.09 3.55 4.24 4.24 3.55 5.42 ns DSPDO_ACIN_P_MULT multiplier T ACIN input to P output not 1.16 1.33 1.59 1.59 1.33 2.07 ns DSPDO_ACIN_P using multiplier T ACIN input to ACOUT output 0.32 0.37 0.45 0.45 0.37 0.53 ns DSPDO_ACIN_ACOUT T ACIN input to 3.30 3.79 4.52 4.52 3.79 5.76 ns DSPDO_ACIN_CARRYCASCOUT_MULT CARRYCASCOUT output using multiplier T ACIN input to 1.37 1.57 1.87 1.87 1.57 2.40 ns DSPDO_ACIN_CARRYCASCOUT CARRYCASCOUT output not using multiplier T PCIN input to P output 0.94 1.08 1.29 1.29 1.08 1.54 ns DSPDO_PCIN_P T PCIN input to 1.15 1.32 1.57 1.57 1.32 1.88 ns DSPDO_PCIN_CARRYCASCOUT CARRYCASCOUT output DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 41

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 35: DSP48E1 Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Clock to Outs from Output Register Clock to Output Pins T CLK PREG to P output 0.33 0.35 0.39 0.39 0.35 0.45 ns DSPCKO_P_PREG T CLK PREG to 0.44 0.50 0.59 0.59 0.50 0.71 ns DSPCKO_CARRYCASCOUT_PREG CARRYCASCOUT output Clock to Outs from Pipeline Register Clock to Output Pins T CLK MREG to P output 1.42 1.64 1.96 1.96 1.64 2.31 ns DSPCKO_P_MREG T CLK MREG to 1.63 1.87 2.24 2.24 1.87 2.65 ns DSPCKO_CARRYCASCOUT_MREG CARRYCASCOUT output T CLK ADREG to P output using 2.30 2.63 3.13 3.13 2.63 3.90 ns DSPCKO_P_ADREG_MULT multiplier T CLK ADREG to 2.51 2.87 3.41 3.41 2.87 4.23 ns DSPCKO_CARRYCASCOUT_ CARRYCASCOUT output ADREG_MULT using multiplier Clock to Outs from Input Register Clock to Output Pins T CLK AREG to P output using 3.34 3.83 4.55 4.55 3.83 5.80 ns DSPCKO_P_AREG_MULT multiplier T CLK BREG to P output not 1.39 1.59 1.88 1.88 1.59 2.24 ns DSPCKO_P_BREG using multiplier T CLK CREG to P output not 1.43 1.64 1.95 1.95 1.64 2.32 ns DSPCKO_P_CREG using multiplier T CLK DREG to P output using 3.32 3.80 4.51 4.51 3.80 5.74 ns DSPCKO_P_DREG_MULT multiplier Clock to Outs from Input Register Clock to Cascading Output Pins T CLK (ACOUT, BCOUT) to 0.55 0.62 0.74 0.74 0.62 0.87 ns DSPCKO_{ACOUT; BCOUT} {A,B} register output _{AREG; BREG} T CLK (AREG, BREG) to 3.55 4.06 4.84 4.84 4.06 6.13 ns DSPCKO_CARRYCASCOUT_ CARRYCASCOUT output {AREG, BREG}_MULT using multiplier T CLK BREG to 1.60 1.82 2.16 2.16 1.82 2.58 ns DSPCKO_CARRYCASCOUT_ BREG CARRYCASCOUT output not using multiplier T CLK DREG to 3.52 4.03 4.79 4.79 4.03 6.07 ns DSPCKO_CARRYCASCOUT CARRYCASCOUT output _ DREG_MULT using multiplier T CLK CREG to 1.64 1.88 2.23 2.23 1.88 2.65 ns DSPCKO_CARRYCASCOUT_ CREG CARRYCASCOUT output Maximum Frequency F With all registers used 741.84 650.20 547.95 547.95 650.20 429.37 MHz MAX F With pattern detector 627.35 549.75 463.61 463.61 549.75 365.90 MHz MAX_PATDET F Two register multiply without 412.20 360.75 303.77 303.77 360.75 248.32 MHz MAX_MULT_NOMREG MREG F Two register multiply without 374.25 327.65 276.01 276.01 327.65 225.73 MHz MAX_MULT_NOMREG_PATDET MREG with pattern detect F Without ADREG 468.82 408.66 342.70 342.70 408.66 263.44 MHz MAX_PREADD_MULT_NOADREG F Without ADREG with pattern 468.82 408.66 342.70 342.70 408.66 263.44 MHz MAX_PREADD_MULT_ detect NOADREG_PATDET DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 42

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 35: DSP48E1 Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE F Without pipeline registers 306.84 267.81 225.02 225.02 267.81 177.15 MHz MAX_NOPIPELINEREG (MREG, ADREG) F Without pipeline registers 285.23 249.13 209.38 209.38 249.13 165.32 MHz MAX_NOPIPELINEREG_PATDET (MREG, ADREG) with pattern detect Clock Buffers and Networks Table 36: Global Clock Switching Characteristics (Including BUFGCTRL) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T / CE pins Setup/Hold 0.12/0.30 0.14/0.38 0.26/0.38 0.26/0.92 0.14/0.38 0.23/0.40 ns BCCCK_CE T (1) BCCKC_CE T / S pins Setup/Hold 0.12/0.30 0.14/0.38 0.26/0.38 0.26/0.92 0.14/0.38 0.23/0.40 ns BCCCK_S T (1) BCCKC_S T (2) BUFGCTRL delay from I0/I1 to O 0.08 0.10 0.12 0.12 0.10 0.10 ns BCCKO_O Maximum Frequency F Global clock tree (BUFG) 741.00 710.00 625.00 625.00 710.00 560.00 MHz MAX_BUFG Notes: 1. T and T must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These BCCCK_CE BCCKC_CE parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 2. T (BUFG delay from I0 to O) values are the same as T values. BGCKO_O BCCKO_O Table 37: Input/Output Clock Switching Characteristics (BUFIO) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T Clock to out delay from I to O 1.04 1.14 1.32 1.32 1.14 1.48 ns BIOCKO_O Maximum Frequency F I/O clock tree (BUFIO) 800.00 800.00 710.00 710.00 800.00 710.00 MHz MAX_BUFIO Table 38: Regional Clock Buffer Switching Characteristics (BUFR) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Clock to out delay from 0.60 0.65 0.77 0.77 0.65 1.06 ns T BRCKO_O I to O Clock to out delay from I to O with 0.30 0.32 0.38 0.38 0.32 0.57 ns T BRCKO_O_BYP Divide Bypass attribute set T Propagation delay from CLR to O 0.71 0.75 0.96 0.96 0.75 0.93 ns BRDO_O DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 43

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 38: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Maximum Frequency F (1) Regional clock tree (BUFR) 600.00 540.00 450.00 450.00 540.00 450.00 MHz MAX_BUFR Notes: 1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F frequency except for the BUFMR in the -2LE at 0.9V, which has MAX a maximum input frequency of 667MHz. Table 39: Horizontal Clock Buffer Switching Characteristics (BUFH) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T BUFH delay from I to O 0.10 0.11 0.13 0.13 0.11 0.12 ns BHCKO_O T / 0.20/0.16 0.23/0.20 0.38/0.21 0.38/0.79 0.23/0.20 0.28/0.09 ns BHCCK_CE CE pin Setup and Hold T BHCKC_CE Maximum Frequency F Horizontal clock buffer (BUFH) 741.00 710.00 625.00 625.00 710.00 560.00 MHz MAX_BUFH Table 40: Duty Cycle Distortion and Clock-Tree Skew Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T Global Clock Tree Duty Cycle All 0.20 0.20 0.20 0.20 All 0.25 ns DCD_CLK Distortion(1) T Global Clock Tree Skew(2) XC7K70T 0.29 0.40 0.40 N/A N/A 0.47 ns CKSKEW XC7K160T 0.42 0.53 0.57 N/A 0.53 0.59 ns XC7K325T 0.59 0.74 0.79 N/A 0.74 0.91 ns XC7K355T 0.45 0.57 0.59 N/A 0.57 0.69 ns XC7K410T 0.60 0.74 0.79 N/A 0.74 0.91 ns XC7K420T 0.60 0.74 0.79 N/A 0.74 0.91 ns XC7K480T 0.60 0.74 0.79 N/A 0.74 0.91 ns XQ7K325T N/A 0.74 0.79 0.79 0.74 0.91 ns XQ7K410T N/A 0.74 0.79 0.79 0.74 0.91 ns T I/O clock tree duty cycle All 0.12 0.12 0.12 0.12 0.12 0.12 ns DCD_BUFIO distortion T I/O clock tree skew across All 0.02 0.02 0.02 0.02 0.02 0.03 ns BUFIOSKEW one clock region T Regional clock tree duty cycle All 0.15 0.15 0.15 0.15 0.15 0.15 ns DCD_BUFR distortion Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The T value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree CKSKEW skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer tools to evaluate clock skew specific to your application. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 44

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics MMCM Switching Characteristics Table 41: MMCM Specification Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE MMCM_F Maximum Input Clock 1066.00 933.00 800.00 800.00 933.00 800.00 MHz INMAX Frequency MMCM_F Minimum Input Clock 10.00 10.00 10.00 10.00 10.00 10.00 MHz INMIN Frequency MMCM_F Maximum Input Clock Period <20% of clock input period or 1ns Max INJITTER Jitter MMCM_F Allowable Input Duty Cycle: 25.00 25.00 25.00 25.00 25.00 25.00 % INDUTY 10–49MHz Allowable Input Duty Cycle: 30.00 30.00 30.00 30.00 30.00 30.00 % 50–199MHz Allowable Input Duty Cycle: 35.00 35.00 35.00 35.00 35.00 35.00 % 200–399MHz Allowable Input Duty Cycle: 40.00 40.00 40.00 40.00 40.00 40.00 % 400–499MHz Allowable Input Duty Cycle: 45.00 45.00 45.00 45.00 45.00 45.00 % >500MHz MMCM_F Minimum Dynamic Phase Shift 0.01 0.01 0.01 0.01 0.01 0.01 MHz MIN_PSCLK Clock Frequency MMCM_F Maximum Dynamic Phase 550.00 500.00 450.00 450.00 500.00 450.00 MHz MAX_PSCLK Shift Clock Frequency MMCM_F Minimum MMCM VCO 600.00 600.00 600.00 600.00 600.00 600.00 MHz VCOMIN Frequency MMCM_F Maximum MMCM VCO 1600.00 1440.00 1200.00 1200.00 1440.00 1200.00 MHz VCOMAX Frequency MMCM_F Low MMCM Bandwidth at 1.00 1.00 1.00 1.00 1.00 1.00 MHz BANDWIDTH Typical(1) High MMCM Bandwidth at 4.00 4.00 4.00 4.00 4.00 4.00 MHz Typical(1) MMCM_T Static Phase Offset of the 0.12 0.12 0.12 0.12 0.12 0.12 ns STATPHAOFFSET MMCM Outputs(2) MMCM_T MMCM Output Jitter Note3 OUTJITTER MMCM_T MMCM Output Clock Duty 0.20 0.20 0.20 0.20 0.20 0.25 ns OUTDUTY Cycle Precision(4) MMCM_T MMCM Maximum Lock Time 100.00 100.00 100.00 100.00 100.00 100.00 µs LOCKMAX MMCM Maximum Output 1066.00 933.00 800.00 800.00 933.00 800.00 MHz MMCM_F OUTMAX Frequency MMCM_F MMCM Minimum Output 4.69 4.69 4.69 4.69 4.69 4.69 MHz OUTMIN Frequency(5)(6) MMCM_T External Clock Feedback <20% of clock input period or 1ns Max EXTFDVAR Variation MMCM_RST Minimum Reset Pulse Width 5.00 5.00 5.00 5.00 5.00 5.00 ns MINPULSE MMCM_F Maximum Frequency at the 550.00 500.00 450.00 450.00 500.00 450.00 MHz PFDMAX Phase Frequency Detector MMCM_F Minimum Frequency at the 10.00 10.00 10.00 10.00 10.00 10.00 MHz PFDMIN Phase Frequency Detector DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 45

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 41: MMCM Specification (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE MMCM_T Maximum Delay in the 3ns Max or one CLKIN cycle FBDELAY Feedback Path MMCM Switching Characteristics Setup and Hold T / Setup and Hold of Phase Shift 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns MMCMDCK_PSEN T Enable MMCMCKD_PSEN T / Setup and Hold of Phase Shift 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns MMCMDCK_PSINCDEC T Increment/Decrement MMCMCKD_PSINCDEC T Phase Shift Clock-to-Out of 0.59 0.68 0.81 0.81 0.68 0.78 ns MMCMCKO_PSDONE PSDONE Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK T / DADDR Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min MMCMDCK_DADDR T MMCMCKD_DADDR T / DI Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min MMCMDCK_DI T MMCMCKD_DI T / DEN Setup/Hold 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 1.97/0.00 2.40/0.00 ns, Min MMCMDCK_DEN T MMCMCKD_DEN T / DWE Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min MMCMDCK_DWE T MMCMCKD_DWE T CLK to out of DRDY 0.65 0.72 0.99 0.99 0.72 0.70 ns, Max MMCMCKO_DRDY F DCLK frequency 200.00 200.00 200.00 200.00 200.00 100.00 MHz, Max DCK Notes: 1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any MMCM outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. See www.xilinx.com/products/intellectual-property/clocking_wizard.htm. 4. Includes global clock buffer. 5. Calculated as F /128 assuming output duty cycle is 50%. VCO 6. When CLKOUT4_CASCADE=TRUE, MMCM_F is 0.036MHz. OUTMIN DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 46

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics PLL Switching Characteristics Table 42: PLL Specification Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE PLL_F Maximum Input Clock Frequency 1066.00 933.00 800.00 800.00 933.00 800.00 MHz INMAX PLL_F Minimum Input Clock Frequency 19.00 19.00 19.00 19.00 19.00 19.00 MHz INMIN PLL_F Maximum Input Clock Period <20% of clock input period or 1ns Max INJITTER Jitter PLL_F Allowable Input Duty Cycle: 25.00 25.00 25.00 25.00 25.00 25.00 % INDUTY 19–49MHz Allowable Input Duty Cycle: 30.00 30.00 30.00 30.00 30.00 30.00 % 50–199MHz Allowable Input Duty Cycle: 35.00 35.00 35.00 35.00 35.00 35.00 % 200–399MHz Allowable Input Duty Cycle: 40.00 40.00 40.00 40.00 40.00 40.00 % 400–499MHz Allowable Input Duty Cycle: 45.00 45.00 45.00 45.00 45.00 45.00 % >500MHz PLL_F Minimum PLL VCO Frequency 800.00 800.00 800.00 800.00 800.00 800.00 MHz VCOMIN PLL_F Maximum PLL VCO Frequency 2133.00 1866.00 1600.00 1600.00 1866.00 1600.00 MHz VCOMAX PLL_F Low PLL Bandwidth at Typical(1) 1.00 1.00 1.00 1.00 1.00 1.00 MHz BANDWIDTH High PLL Bandwidth at Typical(1) 4.00 4.00 4.00 4.00 4.00 4.00 MHz PLL_T Static Phase Offset of the PLL 0.12 0.12 0.12 0.12 0.12 0.12 ns STATPHAOFFSET Outputs(2) PLL_T PLL Output Jitter Note3 OUTJITTER PLL_T PLL Output Clock Duty Cycle 0.20 0.20 0.20 0.20 0.20 0.25 ns OUTDUTY Precision(4) PLL_T PLL Maximum Lock Time 100 100 100 100 100 100 µs LOCKMAX PLL_F PLL Maximum Output Frequency 1066.00 933.00 800.00 800.00 933.00 800.00 MHz OUTMAX PLL_F PLL Minimum Output 6.25 6.25 6.25 6.25 6.25 6.25 MHz OUTMIN Frequency(5) PLL_T External Clock Feedback <20% of clock input period or 1ns Max EXTFDVAR Variation PLL_RST Minimum Reset Pulse Width 5.00 5.00 5.00 5.00 5.00 5.00 ns MINPULSE PLL_F Maximum Frequency at the 550.00 500.00 450.00 450.00 500.00 450.00 MHz PFDMAX Phase Frequency Detector PLL_F Minimum Frequency at the Phase 19.00 19.00 19.00 19.00 19.00 19.00 MHz PFDMIN Frequency Detector PLL_T Maximum Delay in the Feedback 3ns Max or one CLKIN cycle FBDELAY Path Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK T / Setup and hold of D address 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min PLLCCK_DADDR T PLLCKC_DADDR T / Setup and hold of D input 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min PLLCCK_DI T PLLCKC_DI T / Setup and hold of D enable 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 1.97/0.00 2.40/0.00 ns, Min PLLCCK_DEN T PLLCKC_DEN DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 47

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 42: PLL Specification (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T / Setup and hold of D write enable 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min PLLCCK_DWE T PLLCKC_DWE T CLK to out of DRDY 0.65 0.72 0.99 0.99 0.72 0.70 ns, Max PLLCKO_DRDY F DCLK frequency 200.00 200.00 200.00 200.00 200.00 100.00 MHz, Max DCK Notes: 1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any PLL outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. See www.xilinx.com/products/intellectual-property/clocking_wizard.htm. 4. Includes global clock buffer. 5. Calculated as F /128 assuming output duty cycle is 50%. VCO DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 48

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Device Pin-to-Pin Output Parameter Guidelines Table 43: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region) Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. T Clock-capable clock input and XC7K70T 4.98 5.49 6.17 N/A N/A 7.04 ns ICKOF OUTFF at pins/banks closest to XC7K160T 5.23 5.77 6.48 N/A 5.77 7.38 ns the BUFGs without MMCM/PLL (near clock region) XC7K325T 5.72 6.31 7.09 N/A 6.31 8.07 ns XC7K355T 5.34 5.87 6.57 N/A 5.87 7.51 ns XC7K410T 5.84 6.44 7.22 N/A 6.44 8.21 ns XC7K420T 5.50 6.04 6.77 N/A 6.04 7.73 ns XC7K480T 5.50 6.04 6.77 N/A 6.04 7.73 ns XQ7K325T N/A 6.31 7.09 7.09 6.31 8.07 ns XQ7K410T N/A 6.44 7.22 7.22 6.44 8.21 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of the 7Series FPGA Packaging and Pinout Specification (UG475). Table 44: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region) Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. T Clock-capable clock input and XC7K70T 5.29 5.83 6.55 N/A N/A 7.47 ns ICKOFFAR OUTFF at pins/banks farthest XC7K160T 5.84 6.45 7.24 N/A 6.45 8.24 ns from the BUFGs without MMCM/PLL (far clock region) XC7K325T 6.33 6.99 7.84 N/A 6.99 8.92 ns XC7K355T 5.95 6.55 7.32 N/A 6.55 8.36 ns XC7K410T 6.45 7.12 7.97 N/A 7.12 9.07 ns XC7K420T 6.41 7.06 7.90 N/A 7.06 9.01 ns XC7K480T 6.41 7.06 7.90 N/A 7.06 9.01 ns XQ7K325T N/A 6.99 7.84 7.84 6.99 8.92 ns XQ7K410T N/A 7.12 7.97 7.97 7.12 9.07 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of the 7Series FPGA Packaging and Pinout Specification (UG475). DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 49

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 45: Clock-Capable Clock Input to Output Delay With MMCM Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. T Clock-capable clock input and XC7K70T 0.95 0.95 0.95 N/A N/A 1.74 ns ICKOFMMCMCC OUTFF with MMCM XC7K160T 0.96 0.96 0.96 N/A 0.96 1.78 ns XC7K325T 1.00 1.00 1.00 N/A 1.00 1.82 ns XC7K355T 1.00 1.00 1.00 N/A 1.00 1.78 ns XC7K410T 1.00 1.00 1.00 N/A 1.00 1.82 ns XC7K420T 1.07 1.07 1.07 N/A 1.07 1.82 ns XC7K480T 1.07 1.07 1.07 N/A 1.07 1.82 ns XQ7K325T N/A 1.00 1.00 1.00 1.00 1.82 ns XQ7K410T N/A 1.00 1.00 1.00 1.00 1.82 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. MMCM output jitter is already included in the timing calculation. Table 46: Clock-Capable Clock Input to Output Delay With PLL Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. T Clock-capable clock input and XC7K70T 0.84 0.84 0.84 N/A N/A 1.45 ns ICKOFPLLCC OUTFF with PLL XC7K160T 0.89 0.89 0.89 N/A 0.89 1.54 ns XC7K325T 0.89 0.89 0.89 N/A 0.89 1.54 ns XC7K355T 0.89 0.89 0.89 N/A 0.89 1.50 ns XC7K410T 0.89 0.89 0.89 N/A 0.89 1.54 ns XC7K420T 0.96 0.96 0.96 N/A 0.96 1.54 ns XC7K480T 0.96 0.96 0.96 N/A 0.96 1.54 ns XQ7K325T N/A 0.89 0.89 0.89 0.89 1.54 ns XQ7K410T N/A 0.89 0.89 0.89 0.89 1.54 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is already included in the timing calculation. Table 47: Pin-to-Pin, Clock-to-Out using BUFIO Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO. T Clock-to-Out of I/O clock for HR I/O banks 4.93 5.52 6.20 6.20 5.52 6.97 ns ICKOFCS Clock-to-Out of I/O clock for HP I/O banks 4.85 5.44 6.11 6.11 5.44 6.90 ns DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 50

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Device Pin-to-Pin Input Parameter Guidelines Table 48: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) T /T Full Delay (Legacy XC7K70T 2.83/–0.29 2.95/–0.29 3.15/–0.29 N/A N/A 4.96/–0.33 ns PSFD PHFD Delay or Default Delay) XC7K160T 3.17/–0.35 3.29/–0.35 3.55/–0.35 N/A 3.29/–0.35 5.54/–0.49 ns Global Clock Input and IFF(2) without XC7K325T 2.83/–0.06 2.94/–0.06 3.15/–0.06 N/A 2.94/–0.06 5.18/–0.14 ns MMCM/PLL with ZHOLD_DELAY on HR XC7K355T 3.26/–0.32 3.41/–0.32 3.67/–0.32 N/A 3.41/–0.32 5.84/–0.49 ns I/O Banks XC7K410T 3.43/–0.34 3.59/–0.34 3.88/–0.34 N/A 3.59/–0.34 6.21/–0.54 ns XC7K420T 3.37/–0.27 3.48/–0.27 3.76/–0.27 N/A 3.48/–0.27 6.00/–0.52 ns XC7K480T 3.37/–0.27 3.48/–0.27 3.76/–0.27 N/A 3.48/–0.27 6.00/–0.52 ns XQ7K325T N/A 2.94/–0.06 3.15/–0.06 3.15/–0.06 2.94/–0.06 5.18/–0.14 ns XQ7K410T N/A 3.59/–0.34 3.88/–0.34 3.88/–0.34 3.59/–0.34 6.21/–0.54 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch. Table 49: Clock-Capable Clock Input Setup and Hold With MMCM Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) T / No Delay clock- XC7K70T 2.39/–0.22 2.65/–0.22 2.94/–0.22 N/A N/A 2.21/–0.44 ns PSMMCMCC T capable clock input and PHMMCMCC IFF(2) with MMCM XC7K160T 2.49/–0.20 2.77/–0.20 3.07/–0.20 N/A 2.77/–0.20 2.38/–0.47 ns XC7K325T 2.55/–0.16 2.85/–0.16 3.14/–0.16 N/A 2.85/–0.16 2.60/–0.47 ns XC7K355T 2.43/–0.16 2.73/–0.16 3.00/–0.16 N/A 2.73/–0.16 2.47/–0.43 ns XC7K410T 2.55/–0.16 2.84/–0.16 3.14/–0.16 N/A 2.84/–0.16 2.58/–0.47 ns XC7K420T 2.47/–0.09 2.73/–0.09 3.02/–0.09 N/A 2.73/–0.09 2.40/–0.41 ns XC7K480T 2.47/–0.09 2.73/–0.09 3.02/–0.09 N/A 2.73/–0.09 2.40/–0.41 ns XQ7K325T N/A 2.85/–0.16 3.14/–0.16 3.14/–0.16 2.85/–0.16 2.60/–0.47 ns XQ7K410T N/A 2.84/–0.16 3.14/–0.16 3.14/–0.16 2.84/–0.16 2.58/–0.47 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 51

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 50: Clock-Capable Clock Input Setup and Hold With PLL Speed Grade Symbol Description Device 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1) T / No Delay clock-capable XC7K70T 2.75/–0.32 3.04/–0.32 3.33/–0.32 N/A N/A 2.42/–0.54 ns PSPLLCC T clock input and IFF(2) PHPLLCC XC7K160T 2.85/–0.31 3.16/–0.31 3.46/–0.31 N/A 3.16/–0.31 2.59/–0.56 ns with PLL XC7K325T 2.91/–0.27 3.24/–0.27 3.54/–0.27 N/A 3.24/–0.27 2.80/–0.56 ns XC7K355T 2.79/–0.27 3.12/–0.27 3.40/–0.27 N/A 3.12/–0.27 2.67/–0.52 ns XC7K410T 2.91/–0.27 3.24/–0.27 3.53/–0.27 N/A 3.24/–0.27 2.78/–0.56 ns XC7K420T 2.83/–0.20 3.12/–0.20 3.41/–0.20 N/A 3.12/–0.20 2.61/–0.50 ns XC7K480T 2.83/–0.20 3.12/–0.20 3.41/–0.20 N/A 3.12/–0.20 2.61/–0.50 ns XQ7K325T N/A 3.24/–0.27 3.54/–0.27 3.54/–0.27 3.24/–0.27 2.80/–0.56 ns XQ7K410T N/A 3.24/–0.27 3.53/–0.27 3.53/–0.27 3.24/–0.27 2.78/–0.56 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. Table 51: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard. T /T Setup/Hold of I/O clock for HR I/O –0.36/1.36 –0.36/1.50 –0.36/1.70 –0.36/1.70 –0.36/1.50 –0.44/1.87 ns PSCS PHCS banks Setup/Hold of I/O clock for HP I/O –0.34/1.39 –0.34/1.53 –0.34/1.73 –0.34/1.73 –0.34/1.53 –0.44/1.87 ns banks Table 52: Sample Window Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1 -1M/-1LM -2LI -2LE T Sampling Error at Receiver Pins(1) 0.51 0.56 0.61 0.61 0.56 0.56 ns SAMP T Sampling Error at Receiver Pins using 0.30 0.35 0.40 0.40 0.35 0.35 ns SAMP_BUFIO BUFIO(2) Notes: 1. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 52

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for Kintex-7 FPGA clock transmitter and receiver data-valid windows. Table 53: Package Skew Symbol Description Device Package Value Units T Package Skew(1) XC7K70T FBG484 108 ps PKGSKEW FBG676 135 ps XC7K160T FBG484 118 ps FBG676 136 ps FFG676 161 ps XC7K325T FBG676 146 ps FFG676 154 ps FBG900 163 ps FFG900 161 ps XC7K355T FFG901 149 ps XC7K410T FBG676 165 ps FFG676 168 ps FBG900 151 ps FFG900 146 ps XC7K420T FFG901 149 ps FFG1156 145 ps XC7K480T FFG901 149 ps FFG1156 145 ps XQ7K325T RF676 154 ps RF900 161 ps XQ7K410T RF676 168 ps RF900 146 ps Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the package. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 53

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics GTX Transceiver Specifications GTX Transceiver DC Input and Output Levels Table54 summarizes the DC output specifications of the GTX transceivers in Kintex-7 FPGAs. Consult the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further details. Table 54: GTX Transceiver DC Specifications Symbol DC Parameter Conditions Min Typ Max Units Differential peak-to-peak output Transmitter output swing is set to 1000 – – mV DV PPOUT voltage(1) maximum setting DC common mode output Equation based V –DV /4 mV V MGTAVTT PPOUT CMOUTDC voltage. R Differential output resistance – 100 – Ω OUT T Transmitter output pair (TXP and TXN) intra-pair skew – 2 12 ps OSKEW Differential peak-to-peak input >10.3125Gb/s 150 – 1250 mV voltage (external AC coupled) DV 6.6Gb/s to 10.3125Gb/s 150 – 1250 mV PPIN ≤ 6.6Gb/s 150 – 2000 mV V Single-ended input voltage(2) DC coupled V =1.2V –200 – V mV IN MGTAVTT MGTAVTT V Common mode input voltage DC coupled V =1.2V – 2/3 V – mV CMIN MGTAVTT MGTAVTT R Differential input resistance – 100 – Ω IN C Recommended external AC coupling capacitor(3) – 100 – nF EXT Notes: 1. The output swing and preemphasis levels are programmable using the attributes discussed in the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476) and can result in values lower than reported in this table. 2. Voltage measured at the pin referenced to ground. 3. Other values can be used as appropriate to conform to specific protocols and standards. X-Ref Target - Figure 3 +V P Single-Ended Peak-to-Peak N Voltage 0 DS182_01_071014 Figure 3: Single-Ended Peak-to-Peak Voltage X-Ref Target - Figure 4 +V Differential 0 Peak-to-Peak Voltage –V P–N DS182_02_071014 Figure 4: Differential Peak-to-Peak Voltage Note: In Figure4, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 54

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table55 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further details. Table 55: GTX Transceiver Clock DC Input Level Specification Symbol DC Parameter Min Typ Max Units V Differential peak-to-peak input voltage 250 – 2000 mV IDIFF R Differential input resistance – 100 – Ω IN C Required external AC coupling capacitor – 100 – nF EXT GTX Transceiver Switching Characteristics Consult the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further information. Table 56: GTX Transceiver Performance Speed Grade(1) -2 (1.0V) -1 (1.0V)(2) -3 (1.0V) -2LE (1.0V) -1M (1.0V)(2) -2LE (0.9V)(3) -2LI (0.95V) -1LM (1.0V)(2) Output Symbol Description Units Divider Package Type FF FBG676 FBG676 FF FF FF FBG484 RF FB FB FBG900 FBG900 RF RF FBG484 F (4) Maximum GTX transceiver 12.5(5) 10.3125(6) 6.6 10.3125(6) 6.6 8.0 6.6 6.6 6.6 Gb/s GTXMAX data rate F (4) Minimum GTX transceiver 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.500 Gb/s GTXMIN data rate 1 3.2–6.6 Gb/s 2 1.6–3.3 Gb/s F CPLL line rate range 4 0.8–1.65 Gb/s GTXCRANGE 8 0.5–0.825 Gb/s 16 N/A Gb/s 5.93– 5.93– 5.93– 5.93– 5.93– 5.93– 5.93– 5.93–6.6 Gb/s 1 8.0 8.0 6.6 8.0 6.6 8.0 6.6 2 2.965–4.0 2.965–4.0 2.965–4.0 2.965–3.3 Gb/s QPLL line rate F GTXQRANGE1 range1 4 1.4825–2.0 1.4825–2.0 1.4825–2.0 1.4825–1.65 Gb/s 8 0.74125–1.0 0.74125–1.0 0.74125–1.0 0.74125–0.825 Gb/s 16 N/A N/A N/A N/A Gb/s 9.8– 9.8– N/A 9.8– N/A N/A N/A Gb/s 1 12.5 10.3125 10.3125 2 4.9–6.25 4.9–5.15625 N/A N/A Gb/s QPLL line rate F 4 2.45–3.125 2.45–2.578125 N/A N/A Gb/s GTXQRANGE2 range2(7) 8 1.225–1.5625 1.225–1.2890625 N/A N/A Gb/s 0.6125–0.78125 0.6125– N/A N/A Gb/s 16 0.64453125 F GTX transceiver CPLL 1.6–3.3 1.6–3.3 1.6–3.3 1.6–3.3 GHz GCPLLRANGE frequency range F GTX transceiver QPLL 5.93–8.0 5.93–8.0 5.93–8.0 5.93–6.6 GHz GQPLLRANGE1 frequency range 1 DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 55

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 56: GTX Transceiver Performance (Cont’d) Speed Grade(1) -2 (1.0V) -1 (1.0V)(2) -3 (1.0V) -2LE (1.0V) -1M (1.0V)(2) -2LE (0.9V)(3) -2LI (0.95V) -1LM (1.0V)(2) Output Symbol Description Units Divider Package Type FF FBG676 FBG676 FF FF FF FBG484 RF FB FB FBG900 FBG900 RF RF FBG484 F GTX transceiver QPLL 9.8–12.5 9.8–10.3125 N/A N/A GHz GQPLLRANGE2 frequency range 2 Notes: 1. Voltages specified for speed grades are V . CCINT 2. The -1 speed grade requires a 4-byte internal data width for operation above 5.0Gb/s. 3. The -2LE (0.9V) speed grade requires a 4-byte internal data width for operation above 3.8Gb/s. 4. Data rates between 8.0Gb/s and 9.8Gb/s are not available. 5. For line rates greater than 10.3125Gb/s, V is 1.05V nominal (see Table2). MGTAVCC 6. The FBG484 package supports data rates greater than 6.6Gb/s in the -2 and -3 speed grades (requires Vivado Design Suite 2017.1 or later). 7. For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125Gb/s. Table 57: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1/-1M/-1LM -2LI -2LE F GTXDRPCLK maximum frequency 175.01 175.01 156.25 175.01 125.00 MHz GTXDRPCLK Table 58: GTX Transceiver Reference Clock Switching Characteristics All Speed Grades Symbol Description Conditions Units Min Typ Max -3 speed grade 60 – 700 MHz F Reference clock frequency range GCLK All other speed grades 60 – 670 MHz T Reference clock rise time 20%–80% – 200 – ps RCLK T Reference clock fall time 80%–20% – 200 – ps FCLK T Reference clock duty cycle Transceiver PLL only 40 50 60 % DCREF X-Ref Target - Figure 5 T RCLK 80% 20% T FCLK ds182_03_042712 Figure 5: Reference Clock Timing Parameters DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 56

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 59: GTX Transceiver PLL /Lock Time Adaptation All Speed Grades Symbol Description Conditions Units Min Typ Max T Initial PLL lock – – 1 ms LOCK Clock recovery phase acquisition and – 50,000 37x106 UI adaptation time for decision feedback After the PLL is locked to the equalizer (DFE). reference clock, this is the time it T takes to lock the clock data DLOCK Clock recovery phase acquisition and recovery (CDR) to the data – 50,000 2.3x106 UI adaptation time for low-power mode present at the input. (LPM) when the DFE is disabled. Table 60: GTX Transceiver User Clock Switching Characteristics(1)(2) Speed Grade Symbol Description Conditions 1.0V 0.95V 0.9V Units -3(3) -2/-2LE(3) -1/-1M/-1LM(4) -2LI -2LE(5) F TXOUTCLK maximum frequency 412.500 412.500 312.500 412.500 237.500 MHz TXOUT F RXOUTCLK maximum frequency 412.500 412.500 312.500 412.500 237.500 MHz RXOUT 16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz F TXUSRCLK maximum frequency TXIN 32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz 16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz F RXUSRCLK maximum frequency RXIN 32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz 16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz TXUSRCLK2 maximum FTXIN2 frequency 32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz 64-bit data path 195.313 161.133 125.000 161.133 103.125 MHz 16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz RXUSRCLK2 maximum FRXIN2 frequency 32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz 64-bit data path 195.313 161.133 125.000 161.133 103.125 MHz Notes: 1. Clocking must be implemented as described in the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476). 2. These frequencies are not supported for all possible transceiver configurations. 3. For speed grades -3, -2, -2LE (1.0V), -2LI (0.95V), a 16-bit data path can only be used for speeds less than 6.6Gb/s. 4. For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0Gb/s. 5. For speed grade -2LE (0.9V), a 16-bit data path can only be used for speeds less than 3.8Gb/s. Table 61: GTX Transceiver Transmitter Switching Characteristics Symbol Description Condition Min Typ Max Units F Serial data rate range 0.500 – F Gb/s GTXTX GTXMAX T TX Rise time 20%–80% – 40 – ps RTX T TX Fall time 80%–20% – 40 – ps FTX T TX lane-to-lane skew(1) – – 500 ps LLSKEW V Electrical idle amplitude – – 15 mV TXOOBVDPP T Electrical idle transition time – – 140 ns TXOOBTRANSITION TJ Total Jitter(2)(4) – – 0.28 UI 12.5 12.5Gb/s DJ Deterministic Jitter(2)(4) – – 0.17 UI 12.5 TJ Total Jitter(2)(4) – – 0.28 UI 11.18 11.18Gb/s DJ Deterministic Jitter(2)(4) – – 0.17 UI 11.18 DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 57

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 61: GTX Transceiver Transmitter Switching Characteristics (Cont’d) Symbol Description Condition Min Typ Max Units TJ Total Jitter(2)(4) – – 0.28 UI 10.3125 10.3125Gb/s DJ Deterministic Jitter(2)(4) – – 0.17 UI 10.3125 TJ Total Jitter(2)(4) – – 0.28 UI 9.953 9.953Gb/s DJ Deterministic Jitter(2)(4) – – 0.17 UI 9.953 TJ Total Jitter(2)(4) – – 0.28 UI 9.8 9.8Gb/s DJ Deterministic Jitter(2)(4) – – 0.17 UI 9.8 TJ Total Jitter(2)(4) – – 0.30 UI 8.0 8.0Gb/s DJ Deterministic Jitter(2)(4) – – 0.15 UI 8.0 TJ Total Jitter(2)(4) – – 0.28 UI 6.6_QPLL 6.6Gb/s DJ Deterministic Jitter(2)(4) – – 0.17 UI 6.6_QPLL TJ Total Jitter(3)(4) – – 0.30 UI 6.6_CPLL 6.6Gb/s DJ Deterministic Jitter(3)(4) – – 0.15 UI 6.6_CPLL TJ Total Jitter(3)(4) – – 0.30 UI 5.0 5.0Gb/s DJ Deterministic Jitter(3)(4) – – 0.15 UI 5.0 TJ Total Jitter(3)(4) – – 0.30 UI 4.25 4.25Gb/s DJ Deterministic Jitter(3)(4) – – 0.15 UI 4.25 TJ Total Jitter(3)(4) – – 0.30 UI 3.75 3.75Gb/s DJ Deterministic Jitter(3)(4) – – 0.15 UI 3.75 TJ Total Jitter(3)(4) – – 0.2 UI 3.2 3.20Gb/s(5) DJ Deterministic Jitter(3)(4) – – 0.1 UI 3.2 TJ Total Jitter(3)(4) – – 0.32 UI 3.2L 3.20Gb/s(6) DJ Deterministic Jitter(3)(4) – – 0.16 UI 3.2L TJ Total Jitter(3)(4) – – 0.20 UI 2.5 2.5Gb/s(7) DJ Deterministic Jitter(3)(4) – – 0.08 UI 2.5 TJ Total Jitter(3)(4) – – 0.15 UI 1.25 1.25Gb/s(8) DJ Deterministic Jitter(3)(4) – – 0.06 UI 1.25 TJ Total Jitter(3)(4) – – 0.1 UI 500 500Mb/s DJ Deterministic Jitter(3)(4) – – 0.03 UI 500 Notes: 1. Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads). 2. Using QPLL_FBDIV=40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 3. Using CPLL_FBDIV=2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 4. All jitter values are based on a bit-error ratio of 1e-12. 5. CPLL frequency at 3.2GHz and TXOUT_DIV=2. 6. CPLL frequency at 1.6GHz and TXOUT_DIV=1. 7. CPLL frequency at 2.5GHz and TXOUT_DIV=2. 8. CPLL frequency at 2.5GHz and TXOUT_DIV=4. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 58

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 62: GTX Transceiver Receiver Switching Characteristics Symbol Description Min Typ Max Units F Serial data rate 0.500 – F Gb/s GTXRX GTXMAX T Time for RXELECIDLE to respond to loss or restoration of data – 10 – ns RXELECIDLE RX OOB detect threshold peak-to-peak 60 – 150 mV OOBVDPP Receiver spread-spectrum –5000 – 0 ppm RX Modulated @ 33KHz SST tracking(1) RX Run length (CID) – – 512 UI RL Data/REFCLK PPM offset Bit rates≤6.6Gb/s –1250 – 1250 ppm tolerance Bit rates >6.6Gb/s and –700 – 700 ppm RX PPMTOL ≤8.0Gb/s Bit rates>8.0Gb/s –200 – 200 ppm SJ Jitter Tolerance(2) JT_SJ Sinusoidal Jitter (QPLL)(3) 12.5Gb/s 0.3 – – UI 12.5 JT_SJ Sinusoidal Jitter (QPLL)(3) 11.18Gb/s 0.3 – – UI 11.18 JT_SJ Sinusoidal Jitter (QPLL)(3) 10.32Gb/s 0.3 – – UI 10.32 JT_SJ Sinusoidal Jitter (QPLL)(3) 9.95Gb/s 0.3 – – UI 9.95 JT_SJ Sinusoidal Jitter (QPLL)(3) 9.8Gb/s 0.3 – – UI 9.8 JT_SJ Sinusoidal Jitter (QPLL)(3) 8.0Gb/s 0.44 – – UI 8.0 JT_SJ Sinusoidal Jitter (QPLL)(3) 6.6Gb/s 0.48 – – UI 6.6_QPLL JT_SJ Sinusoidal Jitter (CPLL)(3) 6.6Gb/s 0.44 – – UI 6.6_CPLL JT_SJ Sinusoidal Jitter (CPLL)(3) 5.0Gb/s 0.44 – – UI 5.0 JT_SJ Sinusoidal Jitter (CPLL)(3) 4.25Gb/s 0.44 – – UI 4.25 JT_SJ Sinusoidal Jitter (CPLL)(3) 3.75Gb/s 0.44 – – UI 3.75 JT_SJ Sinusoidal Jitter (CPLL)(3) 3.2Gb/s(4) 0.45 – – UI 3.2 JT_SJ Sinusoidal Jitter (CPLL)(3) 3.2Gb/s(5) 0.45 – – UI 3.2L JT_SJ Sinusoidal Jitter (CPLL)(3) 2.5Gb/s(6) 0.5 – – UI 2.5 JT_SJ Sinusoidal Jitter (CPLL)(3) 1.25Gb/s(7) 0.5 – – UI 1.25 JT_SJ Sinusoidal Jitter (CPLL)(3) 500Mb/s 0.4 – – UI 500 SJ Jitter Tolerance with Stressed Eye(2) JT_TJSE 3.2Gb/s 0.70 – – UI 3.2 Total Jitter with Stressed Eye(8) JT_TJSE 6.6Gb/s 0.70 – – UI 6.6 JT_SJSE3.2 Sinusoidal Jitter with Stressed 3.2Gb/s 0.1 – – UI JT_SJSE Eye(8) 6.6Gb/s 0.1 – – UI 6.6 Notes: 1. Using RXOUT_DIV=1, 2, and 4. 2. All jitter values are based on a bit error ratio of 1e–12. 3. The frequency of the injected sinusoidal jitter is 10MHz. 4. CPLL frequency at 3.2GHz and RXOUT_DIV=2. 5. CPLL frequency at 1.6GHz and RXOUT_DIV=1. 6. CPLL frequency at 2.5GHz and RXOUT_DIV=2. 7. CPLL frequency at 2.5GHz and RXOUT_DIV=4. 8. Composite jitter with RX in LPM or DFE mode. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 59

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics GTX Transceiver Protocol Jitter Characteristics For Table63 through Table68, the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476) contains recommended settings for optimal usage of protocol specific characteristics. Table 63: Gigabit Ethernet Protocol Characteristics Description Line Rate (Mb/s) Min Max Units Gigabit Ethernet Transmitter Jitter Generation Total transmitter jitter (T_TJ) 1250 – 0.24 UI Gigabit Ethernet Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 1250 0.749 – UI Table 64: XAUI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units XAUI Transmitter Jitter Generation Total transmitter jitter (T_TJ) 3125 – 0.35 UI XAUI Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 3125 0.65 – UI Table 65: PCI Express Protocol Characteristics(1) Standard Description Line Rate (Mb/s) Min Max Units PCI Express Transmitter Jitter Generation PCI Express Gen 1 Total transmitter jitter 2500 – 0.25 UI PCI Express Gen 2 Total transmitter jitter 5000 – 0.25 UI Total transmitter jitter uncorrelated – 31.25 ps PCI Express Gen 3 8000 Deterministic transmitter jitter uncorrelated – 12 ps PCI Express Receiver High Frequency Jitter Tolerance PCI Express Gen 1 Total receiver jitter tolerance 2500 0.65 – UI Receiver inherent timing error 0.40 – UI PCI Express Gen 2(2) 5000 Receiver inherent deterministic timing error 0.30 – UI 0.03MHz–1.0MHz 1.00 – UI Receiver sinusoidal jitter PCI Express Gen 3 1.0MHz–10MHz 8000 Note3 – UI tolerance 10MHz–100MHz 0.10 – UI Notes: 1. Tested per card electromechanical(CEM)methodology. 2. Using common REFCLK. 3. Between 1MHz and 10MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 60

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 66: CEI-6G and CEI-11G Protocol Characteristics Description Line Rate (Mb/s) Interface Min Max Units CEI-6G Transmitter Jitter Generation CEI-6G-SR – 0.3 UI Total transmitter jitter(1) 4976–6375 CEI-6G-LR – 0.3 UI CEI-6G Receiver High Frequency Jitter Tolerance CEI-6G-SR 0.6 – UI Total receiver jitter tolerance(1) 4976–6375 CEI-6G-LR 0.95 – UI CEI-11G Transmitter Jitter Generation CEI-11G-SR – 0.3 UI Total transmitter jitter(2) 9950–11100 CEI-11G-LR/MR – 0.3 UI CEI-11G Receiver High Frequency Jitter Tolerance CEI-11G-SR 0.65 – UI Total receiver jitter tolerance(2) 9950–11100 CEI-11G-MR 0.65 – UI CEI-11G-LR 0.825 – UI Notes: 1. Tested at most commonly used line rate of 6250Mb/s using 390.625MHz reference clock. 2. Tested at line rate of 9950Mb/s using 155.46875MHz reference clock and 11100Mb/s using 173.4375MHz reference clock. Table 67: SFP+ Protocol Characteristics Description Line Rate (Mb/s) Min Max Units SFP+ Transmitter Jitter Generation 9830.40(1) 9953.00 Total transmitter jitter 10312.50 – 0.28 UI 10518.75 11100.00 SFP+ Receiver Frequency Jitter Tolerance 9830.40(1) 9953.00 Total receiver jitter tolerance 10312.50 0.7 – UI 10518.75 11100.00 Notes: 1. Line rated used for CPRI over SFP+ applications. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 61

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 68: CPRI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units CPRI Transmitter Jitter Generation 614.4 – 0.35 UI 1228.8 – 0.35 UI 2457.6 – 0.35 UI Total transmitter jitter 3072.0 – 0.35 UI 4915.2 – 0.3 UI 6144.0 – 0.3 UI 9830.4 – Note1 UI CPRI Receiver Frequency Jitter Tolerance 614.4 0.65 – UI 1228.8 0.65 – UI 2457.6 0.65 – UI Total receiver jitter tolerance 3072.0 0.65 – UI 4915.2 0.95 – UI 6144.0 0.95 – UI 9830.4 Note1 – UI Notes: 1. Tested per SFP+ specification, see Table67. Integrated Interface Block for PCI Express Designs Switching Characteristics More information and documentation on solutions for PCI Express designs can be found at: www.xilinx.com/products/technology/pci-express.html Table 69: Maximum Performance for PCI Express Designs(1) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1/-1M/-1LM -2LI -2LE F Pipe clock maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz PIPECLK F User clock maximum frequency 500.00(1) 500.00(1) 250.00 500.00(1) 250.00 MHz USERCLK F User clock 2 maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz USERCLK2 F DRP clock maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz DRPCLK Notes: 1. Refer to the 7Series FPGAs Integrated Block for PCIExpress Product Guide (PG054) for specific supported core configurations. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 62

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics XADC Specifications Table 70: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units V =1.8V±5%, V =1.25V, V =0V, ADCCLK=26MHz, T =–40°C to 100°C, Typical values at T=+40°C CCADC REFP REFN j j ADC Accuracy(1) Resolution 12 – – Bits Integral Nonlinearity(2) INL – – ±3 LSBs Differential Nonlinearity DNL No missing codes, guaranteed monotonic – – ±1 LSBs Offset Error Offset calibration enabled – – ±6 LSBs Gain Error Gain calibration disabled – – ±0.5 % Offset Matching Offset calibration enabled – – 4 LSBs Gain Matching Gain calibration disabled – – 0.3 % Sample Rate – – 1 MS/s Signal to Noise Ratio(2) SNR F =500KS/s, F =20KHz 60 – – dB SAMPLE IN RMS Code Noise External 1.25V reference – – 2 LSBs On-chip reference – 3 – LSBs Total Harmonic Distortion(2) THD F =500KS/s, F =20KHz – 70 – dB SAMPLE IN ADC Accuracy at Extended Temperatures Resolution T =–55°C to 125°C 10 – – Bits j Integral Nonlinearity(2) INL T =–55°C to 125°C – – ±1 LSB j (at 10bits) Differential Nonlinearity DNL No missing codes, guaranteed monotonic, – – ±1 T =–55°C to 125°C j Analog Inputs(3) ADC Input Ranges Unipolar operation 0 – 1 V Bipolar operation –0.5 – +0.5 V Unipolar common mode range (FS input) 0 – +0.5 V Bipolar common mode range (FS input) +0.5 – +0.6 V Maximum External Channel Input Ranges Adjacent channels set within these ranges –0.1 – V V CCADC should not corrupt measurements on adjacent channels Auxiliary Channel Full FRBW 250 – – KHz Resolution Bandwidth On-Chip Sensors Temperature Sensor Error T =–40°C to 100°C – – ±4 °C j T =–55°C to +125°C – – ±6 °C j Supply Sensor Error Measurement range of V 1.8V ±5% – – ±1 % CCAUX T =–40°C to +100°C j Measurement range of V 1.8V ±5% – – ±2 % CCAUX T =–55°C to +125°C j Conversion Rate(4) Conversion Time - Continuous t Number of ADCCLK cycles 26 – 32 Cycles CONV Conversion Time - Event t Number of CLK cycles – – 21 Cycles CONV DRP Clock Frequency DCLK DRP clock frequency 8 – 250 MHz ADC Clock Frequency ADCCLK Derived from DCLK 1 – 26 MHz DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 63

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 70: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units DCLK Duty Cycle 40 – 60 % XADC Reference(5) External Reference V Externally supplied reference voltage 1.20 1.25 1.30 V REFP On-Chip Reference Ground V pin to AGND, 1.2375 1.25 1.2625 V REFP T =–40°C to 100°C j Notes: 1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. 2. Only specified for bitstream option XADCEnhancedLinearity=ON. 3. For a detailed description, see the ADC chapter in the 7Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480). 4. For a detailed description, see the Timing chapter in the 7Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480). 5. Any variation in the reference voltage from the nominal V = 1.25V and V = 0V will result in a deviation from the ideal transfer REFP REFN function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. On-chip reference variation is ±1%. Configuration Switching Characteristics Table 71: Configuration Switching Characteristics Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1/-1M/-1LM -2LI -2LE Power-up Timing Characteristics T (1) Program latency 5 5 5 5 5 ms, Max PL T (1) Power-on reset (50ms ramp rate time) 10/50 10/50 10/50 10/50 10/50 ms, Min/Max POR Power-on reset (1ms ramp rate time) 10/35 10/35 10/35 10/35 10/35 ms, Min/Max T Program pulse width 250 250 250 250 250 ns, Min PROGRAM CCLK Output (Master Mode) T Master CCLK output delay 150 150 150 150 150 ns, Min ICCK T Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max MCCKL T Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max MCCKH F Master CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max MCCK Master CCLK frequency for AES encrypted 50.00 50.00 50.00 50.00 35.00 MHz, Max x16 F Master CCLK frequency at start of 3.00 3.00 3.00 3.00 3.00 MHz, Typ MCCK_START configuration F Frequency tolerance, master mode with ±50 ±50 ±50 ±50 ±50 %, Max MCCKTOL respect to nominal CCLK CCLK Input (Slave Modes) T Slave CCLK clock minimum Low time 2.50 2.50 2.50 2.50 2.50 ns, Min SCCKL T Slave CCLK clock minimum High time 2.50 2.50 2.50 2.50 2.50 ns, Min SCCKH F Slave CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max SCCK EMCCLK Input (Master Mode) T External master CCLK Low time 2.50 2.50 2.50 2.50 2.50 ns, Min EMCCKL T External master CCLK High time 2.50 2.50 2.50 2.50 2.50 ns, Min EMCCKH DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 64

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 71: Configuration Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1/-1M/-1LM -2LI -2LE F External master CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max EMCCK Internal Configuration Access Port F Internal configuration access port (ICAPE2) 100.00 100.00 100.00 100.00 70.00 MHz, Max ICAPCK Master/Slave Serial Mode Programming Switching T / DIN Setup/Hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min DCCK T CCKD T DOUT clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max CCO SelectMAP Mode Programming Switching T / D[31:00] Setup/Hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min SMDCCK T SMCCKD T / CSI_B Setup/Hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min SMCSCCK T SMCCKCS T / RDWR_B Setup/Hold 10.00/0.00 10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00 ns, Min SMWCCK T SMCCKW T CSO_B clock to out (330Ω pull-up resistor 7.00 7.00 7.00 7.00 8.00 ns, Max SMCKCSO required) T D[31:00] clock to out in readback 8.00 8.00 8.00 8.00 10.00 ns, Max SMCO F Readback frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max RBCCK Boundary-Scan Port Timing Specifications T / TMS and TDI Setup/Hold 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 ns, Min TAPTCK T TCKTAP T TCK falling edge to TDO output 7.00 7.00 7.00 7.00 8.50 ns, Max TCKTDO F TCK frequency 66.00 66.00 66.00 66.00 50.00 MHz, Max TCK BPI Flash Master Mode Programming Switching T (2) A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, 8.50 8.50 8.50 8.50 10.00 ns, Max BPICCO ADV_B clock to out T / D[15:00] Setup/Hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min BPIDCC T BPICCD SPI Flash Master Mode Programming Switching T / D[03:00] Setup/Hold 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 ns, Min SPIDCC T SPICCD T MOSI clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max SPICCM T FCS_B clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max SPICCFC STARTUPE2 Ports T STARTUPE2 USRCCLKO input to CCLK 0.50/6.00 0.50/6.70 0.50/7.50 0.50/6.70 0.50/7.50 ns, Min/Max USRCCLKO output F STARTUPE2 CFGMCLK output frequency 65.00 65.00 65.00 65.00 65.00 MHz, Typ CFGMCLK F STARTUPE2 CFGMCLK output frequency ±50 ±50 ±50 ±50 ±50 %, Max CFGMCLKTOL tolerance DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 65

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 71: Configuration Switching Characteristics (Cont’d) Speed Grade Symbol Description 1.0V 0.95V 0.9V Units -3 -2/-2LE -1/-1M/-1LM -2LI -2LE Device DNA Access Port F DNA access port (DNA_PORT) 100.00 100.00 100.00 100.00 70.00 MHz, Max DNACK Notes: 1. To support longer delays in configuration, use the design solutions described in the 7Series FPGA Configuration User Guide (UG470). 2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. eFUSE Programming Conditions Table72 lists the programming conditions specifically for eFUSE. For more information, see the 7Series FPGA Configuration User Guide (UG470). Table 72: eFUSE Programming Conditions(1) Symbol Description Min Typ Max Units I V supply current – – 115 mA FS CCAUX t Temperature range 15 – 125 °C j Notes: 1. The FPGA must not be configured during eFUSE programming. Revision History The following table shows the revision history for this document: Date Version Description 03/01/2011 1.0 Initial Xilinx release. 04/01/2011 1.1 Added the XC7K355T, XC7K420T, and XC7K480T devices throughout data sheet. Added the extended temperature range discussion to page1. Updated V in Table2. Edits to clarify CCAUX_IO Power-On/Off Power Supply Sequencing power sequencing discussion. Added I and I CCAUX_IO CCBRAM to Table6 and Table7. Updated MMCM_F and added F , T , T , and INDUTY INJITTER OUTJITTER EXTFDVAR Note3 to Table41. Removed the SBG324 package from Table53. Updated the Notice of Disclaimer. 10/04/2011 1.2 Replaced -1L with -2L throughout this data sheet. Updated Min/Max values and removed Note 5 from Table2. Clarified Power-On/Off Power Supply Sequencing power sequencing discussion including adding T to Table8. Updated V in Table12 and Table13. Added Note 1 to table 12. VCCO2VCCAUX ICM Updated Table72 including adding Note1. Added Absolute Maximum Ratings for GTX Transceivers. Revised the reference clock maximum frequency (F ) in Table58. Added Table60. Added LVTTL GCLK and removed SSTL135_II and SSTL15_II specifications from Table20. Removed HSTL_III from Table21. Removed the I/O Standard Adjustment Measurement Methodology section. Use IBIS for more accurate information and measurements. Updated T in Table29. Added T /T to IDELAYPAT_JIT AS AH Table31. Added T /T and T /T to Table34. RDCK_DI_WF_NC RCKD_DI_WF_NC RDCK_DI_RF RCKD_DI_RF Completely updated Table71. Updated the AC Switching Characteristics in Table20, Table21, Table22, Table25, Table26, Table27, Table29 through Table41, Table43 though Table40, and Table 67. 11/03/2011 1.3 Revised the V specification in Table12. Updated the AC Switching Characteristics based upon the OCM ISE 13.3 v1.02 speed specification throughout document including Table20 and Table21. Added MMCM_T while adding MMCM_ to the symbol names of a few specifications in Table41 and FBDELAY PLL to the symbol names in Table42. In Table43 through Table50, updated the pin-to-pin descriptions with the SSTL15 standard. Updated units in Table52. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 66

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description 02/13/2012 1.4 Updated summary description on page1. In Table2, revised V for the 3.3V HR I/O banks and CCO updated T. Added typical values to Table3. Updated the notes in Table6. Added MGTAVCC, j MGTAVTT, and MGTVCCAUX power supply ramp times to Table8. Rearranged Table9, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12, SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I, DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table10 and Table11. Revised the specifications in Table12 and Table13. Updated the eFUSE Programming Conditions section and removed the endurance table. Added the IO_FIFO Switching Characteristics table. Revised I and updated Note1 in Table70. Revised DDR LVDS CCADC transmitter data width in Table17. Updated the AC Switching Characteristics based upon the ISE 13.4 v1.03 speed specification throughout document. Removed notes from Table31 as they are no longer applicable. Updated specifications in Table71. Updated Note1 in Table40. In the GTX Transceiver DC Input and Output Levels section: Revised V , and added I and I IN DCIN DCOUT to Table54. Added Note7 to Table56. In Table58, revised F , removed T , and added GCLK PHASE T . Revised specifications and added Note2 to Table60. Added Table61 and Table62 along with DLOCK GTX Transceiver Protocol Jitter Characteristics in Table63 through Table68. 05/23/2012 1.5 Reorganized entire data sheet including adding Table47 and Table51. Updated T in Table1. Updated I and added R to Table3. Added values to Table6 and SOL BATT IN_TERM Table7. Updated Power-On/Off Power Supply Sequencing, page7 with regards to GTX transceivers. Updated many parameters in Table9 including SSTL135 and SSTL135_R. Removed V column and OX added DIFF_HSUL_12 to Table11. Updated V in Table12. Updated Table17 and removed notes 2 OL and 3. Updated Table18. Updated the AC Switching Characteristics based upon the ISE 14.1 v1.04 for the -3, -2, -2L (1.0V), -1, and -2L (0.9V) speed specifications throughout the document. In Table34, updated Reset Delays section including Note10 and Note11. Added data for T and LOCK T in Table58. Updated many of the XADC specifications in Table70 and added Note2. Updated DLOCK and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from Table71 to Table41 and Table42. 07/25/2012 1.6 Updated the descriptions, changed V and Note2 and added Note4 in Table1. In Table2, changed IN descriptions and notes, removed Note 7, changed GTX transceiver parameters and values and added Note12. Updated parameters in Table3. Added Table4 and Table5. Changed the typical values for many of the devices in Table7. Updated LVCMOS12 and the SSTLs in Table9. Updated many of the specifications in Table10 and Table11. Updated speed specification to v1.06 (-3, -2, -2L(1.0V), -1) and v1.05 (-2L(0.9V)) with appropriate changes to Table15 and Table16 including production release of the XC7K325T and the XC7K410T in the -2, -2L(1.0V), and -1 speed designations. Added notes and specifications to Table18 and Table19. Updated the IOB Pad Input/Output/3-State discussion and changed Table22 by adding T . IOIBUFDISABLE Removed many of the combinatorial delay specifications and T /T from Table31. CINCK CKCIN Rearranged Table54 including moving some parameters to Table1. Added Table59. Updated Table60. In Table62, updated SJ Jitter Tolerance with Stressed Eye section, page59 and Note8. Added Note1, Note2, and Note2 to Table65. Added Note1 and Note2 to Table66, and line rate ranges. Updated Table67 including adding Note1. Updated Table68 including adding Note1. In Table70 updated Note1 and added Note 4. In Table71, updated T and F . POR EMCCK 09/04/2012 1.7 Updated Table15 and Table16 for production release of the XC7K160T in the -2, -2L(1.0V), and -1 speed designations. 09/26/2012 1.8 In Table2, revised V and V and added Note3. Updated Table15 and Table16 for CCINT CCBRAM production release of the XC7K480T in the -2, -2L(1.0V), and -1 speed designations and the XC7K325T and XC7K410T in the -3 speed designation. 10/10/2012 1.9 Updated the I value for the XC7K355T in Table7. Updated Table15 and Table16 for CCINTMIN production release of the XC7K420T in the -2, -2L(1.0V), and -1 speed designations. 10/25/2012 2.0 Updated the AC Switching Characteristics based upon ISE 14.3 v1.07 for the -3, -2, -2L (1.0V), -1 speed specifications, and ISE 14.3 v1.06 for the -2L (0.9V) speed specifications throughout the document. Updated Table15 and Table16 for production release of the XC7K355T in the -2, -2L(1.0V), and -1 speed designations. Also updated Table15 and Table16 for production release of the XC7K325T and XC7K410T in the -2L (0.9V). Added values for Table17 -2L (0.9V). Added package skew values to Table53. In Table56, increased -1 speed grade (FF package) F value from 6.6Gb/s to 8.0Gb/s. GTXMAX DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 67

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description 10/31/2012 2.1 Updated Table15 and Table16 for production release of the XC7K70T in the -2, -2L(1.0V), and -1 speed designations. 11/26/2012 2.2 Updated Table15 and Table16 for production release of -3 speed designation for XC7K70T, XC7K160T, XC7K355T, XC7K420T, and XC7K480T. Removed Note4 from Table70. 12/05/2012 2.3 Updated Table15 and Table16 for production release of the -2L (0.9V) speed designation for XC7K160T, XC7K420T, and XC7K480T. Updated Note1 in Table53. 12/12/2012 2.4 Updated Table15 and Table16 for production release of the -2L (0.9V) speed designation for XC7K70T and XC7K355T. Added Internal Configuration Access Port section to Table71. 10/04/2013 2.5 In Table1, revised V (I/O input voltage) to match values in Table4 and Table5, and combined Note4 IN with old Note 5 and then added new Note5. Also in Table1, updated I and I sections. DCIN DCOUT Revised V description and added Note3 and Note8 in Table2. Updated first 3 rows in Table4 and IN Table5. Replaced XPower with Xilinx Power Estimator (XPE) in sentence before Table7. Updated V IL minimum for PCI33_3 in Table9. Added Note1 to Table12. Added Note1 to Table13. Added Vivado Design Suite to AC Switching Characteristics. Updated titles of Table18 and Table19, and removed the following note: RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated with memory IP. Updated T and T values in Table20. Replaced “TRACE report” with “timing IOOP IOTP report” in notes for Table28, Table29, Table30, Table32, and Table34. Removed this note: A Zero “0” Hold Time listing indicates no hold time or a negative hold time from Table32, Table33, and Table48. Updated Note1 in Table38. Updated Table60 to more accurately show transceiver user clocks for supported line rates. Updated Note8 and description of F in Table62. Updated Note2, Note3, GTXRX and Note4 in Table70. Added T to Table71. USRCCLKO 11/27/2013 2.6 Added Kintex-7Q defense-grade devices throughout. Added -1M speed grade throughout. Added reference to 7Series FPGAs Overview and Defense-Grade 7Series FPGAs Overview in Introduction. In Table2, added junction temperature operating range for military (M) devices. In Table3, removed commercial (C), industrial (I), and extended (E) from descriptions of R . Updated temperature IN_TERM ranges in Table4 and Table5. Removed Note 1 and Note 2 from Table7. Added T = 125°C to J Conditions column for T in Table8. Added Table14. Updated description of VCCO2VCCAUX MMCM_F in Table41. Updated description of PLL_F in Table42. Added RF package PFDMAX PFDMAX type to Table56. Added F to Table71. DNACK 02/07/2014 2.7 Updated the AC Switching Characteristics based upon ISE 14.7 and Vivado 2013.4. Updated Note5 and added Note6 to Table2. Added Note2 to Table4. Added Note2 and updated Note3 in Table5. Added HSUL_12_F, DIFF_HSUL_12_F, MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S, and DIFF_MOBILE_DDR_F standards to and updated values in Table20. Added HSUL_12_F, DIFF_HSUL_12_F, DIFF_HSUL_12_DCI_S, and DIFF_HSUL_12_DCI_F standards to and updated values in Table21. In Table35, corrected F from 478.27 to 478.24 MHz to MAX_CAS_RF_DELAYED_WRITE match software behavior. Removed introductory paragraph of Device Pin-to-Pin Output Parameter Guidelines and Device Pin-to-Pin Input Parameter Guidelines. Updated display format of “ADC Accuracy at Extended Temperatures” section in Table70. 03/04/2014 2.8 Updated Note2 in Table4 and Note2 in Table5. For XQ7K325T and XQ7K410T in Table15, changed -2 and -1 speed grades to -2I and -1I, respectively, and moved all XQ7K325T speed grades from Preliminary to Production. In Table16, added production software for XQ7K325T -2/2L, -1, -1M, and (0.9V) -2L speed grades. Removed “and FB” from title of Table19. Removed notes from Table20 and Table21. Added Note1 to Table69. 06/20/2014 2.9 In Table4 and Table5, updated Note2 per the customer notice XCN14014: 7 Series FPGA and Zynq-7000 AP SoC I/O Undershoot Voltage Data Sheet Update. In Table15, moved all XQ7K410T speed grades from Preliminary to Production. In Table16, added production software for XQ7K410T -2/-2L, -1, -1M, and (0.9V) -2L speed grades and removed Note 2. Added Note3 to Table18. In Table29, added attribute REFCLK frequency of 400MHz to F and average tap delay IDELAYCTRL_REF at 400MHz to Note1. In Table69, updated Note1 to Gen2 and added reference to 7 Series FPGAs Integrated Block for PCI Express Product Guide (PG054). In Table71, replaced USRCCLK Output with STARTUPE2 Ports and added F and F . CFGMCLK CFGMCLKTOL 09/08/2014 2.10 Updated Note3 in Table6. In Power-On/Off Power Supply Sequencing, added sentence about there being no recommended sequence for supplies not shown. Added I/O Standard Adjustment Measurement Methodology. In Table43, updated description of T and added Note2. In Table44, ICKOF updated description of T and added Note2. In Table54, moved DV value of 1000mV ICKOFFAR PPOUT from Max to Min column, updated V DC parameter description, and added Note2. Added “peak-to- IN peak” to labels in Figure3 and Figure4. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 68

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description 10/06/2014 2.11 Added -2LI (0.95V) speed grade throughout. Removed 3.3V as a descriptor of HR I/O banks and 1.8V as a descriptor of HP I/O banks throughout. Updated Introduction. Added -2LI (0.95V) to description of V and V in Table2. Added Note1 and updated Note2 in Table16. Updated Note3 in CCINT CCBRAM Table18. 11/19/2014 2.12 Replaced -2L speed grade with -2LE throughout. Updated descriptions of V and V in CCINT CCBRAM Table2. Updated the AC Switching Characteristics based upon Vivado 2014.4. In Table14, updated Vivado software version to 1.12 and added a row for V =0.95V. In Table15, moved -2LI (0.95V) CCINT speed grade from Advance to Production. In Table16, added Vivado 2014.4 software version to -2LI (0.95V) speed grade column and removed notes. Added Selecting the Correct Speed Grade and Voltage in the Vivado Tools. Updated speed grade heading row in Table56. Added -2LI (0.95V) speed grade to Note3 in Table60. Removed sentence about PCIExpress x8 Gen2 operation from Note1 in Table69. 02/23/2015 2.13 In Table12, changed maximum V value from 1.425V to 1.500V. Removed minimum sample rate ICM specification from Table70. 09/24/2015 2.14 Updated first two paragraphs in Introduction. Added -1LM speed grade to V and V CCINT CCBRAM descriptions in Table2. In Table6, added -1LM (1.0V) speed grade and assigned quiescent supply currents to -2LI speed grade Kintex-7Q devices. In Table16, changed -2LI speed grade Kintex-7Q device cells from N/A to blank, added -1LM speed grade, and added Note1. Added -1M and -1LM speed grades to Table17. Added introductory paragraph before Table18. Removed Pb-free G suffix from Table18 and Table19 titles and Note3. Updated Note3 in Table18. Added -1LM speed grade in Table18 to Table52, Table57, Table60, Table69, and Table71. Changed -2LI speed grade Kintex-7Q device cells from N/A to blank in Table40, Table43 to Table46, and Table48 to Table50. Added FBV484, FBV676, FFV676, FBV900, FFV900, FFV901, and FFV1156 packages to Table53. Added -1LM (1.0V) speed grade to Table56. Removed note about PCI-SIG 3.0 certification and compliance test boards from Table65. 11/24/2015 2.15 Updated the AC Switching Characteristics based upon Vivado 2015.4. In Table15, added -2LI (0.95V) and -1LM speed grades to Production column for XQ7K325T and XQ7K410T. In Table16, removed table note and added Vivado 2015.4 software version to -1LM and -2LI (0.95V) speed grades for XQ7K325T and -2LI (0.95V) speed grade for XQ7K410T. In Table40, added T for XQ7K325T CKSKEW and XQ7K410T at -2LI (0.95V) speed grade. Updated device pin-to-pin output parameter tables (Table43 to Table46) and input parameter tables (Table48 to Table50) for XQ7K325T and XQ7K410T at -2LI (0.95V) speed grade. 05/08/2017 2.16 Updated Note5 in Table2. Added Note1 to Table14. Updated V for LVCMOS33, LVTTL, and MEAS PCI33_3 I/O standard attributes in Table23. In Table29, changed T units from ps to IDELAYRESOLUTION µs. Updated Note1 in Table38. Removed FBV484, FBV676, FFV676, FBV900, FFV900, FFV901, and FFV1156 packages from Table53 per the customer notice XCN16022: Cross-ship of Lead-free Bump and Substrates in Lead-free (FFG/FBG/SBG) Packages. In Table56, improved GTX performance for FBG484 package in -2 and -3 speed grades (requires Vivado tools 2017.1), and added Note1, Note5, and Note6. 08/07/2018 2.16.1 Editorial updates only. No technical content updates. Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. DS182 (v2.16.1) August 7, 2018 www.xilinx.com Send Feedback Product Specification 70