1 Spartan-3E FPGA Family Data Sheet DS312 December 14, 2018 Product Specification Module 1: Module 3: Introduction and Ordering Information DC and Switching Characteristics DS312 (v4.2) December 14, 2018 DS312 (v4.2) December 14, 2018 (cid:129) Introduction (cid:129) DC Electrical Characteristics (cid:129) Features (cid:129) Absolute Maximum Ratings (cid:129) Architectural Overview (cid:129) Supply Voltage Specifications (cid:129) Package Marking (cid:129) Recommended Operating Conditions (cid:129) Ordering Information (cid:129) DC Characteristics (cid:129) Switching Characteristics Module 2: Functional Description (cid:129) I/O Timing DS312 (v4.2) December 14, 2018 (cid:129) SLICE Timing (cid:129) DCM Timing (cid:129) Input/Output Blocks (IOBs) (cid:129) Block RAM Timing (cid:129) Overview (cid:129) Multiplier Timing (cid:129) SelectIO™ Signal Standards (cid:129) Configuration and JTAG Timing (cid:129) Configurable Logic Block (CLB) (cid:129) Block RAM Module 4: Pinout Descriptions (cid:129) Dedicated Multipliers (cid:129) Digital Clock Manager (DCM) DS312 (v4.2) December 14, 2018 (cid:129) Clock Network (cid:129) Pin Descriptions (cid:129) Configuration (cid:129) Package Overview (cid:129) Powering Spartan®-3E FPGAs (cid:129) Pinout Tables (cid:129) Production Stepping (cid:129) Footprint Diagrams © Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 December 14, 2018 www.xilinx.com Send Feedback Product Specification 1

8 Spartan-3E FPGA Family: Introduction and Ordering Information DS312 (v4.2) December 14, 2018 Product Specification Introduction The Spartan®-3E family of Field-Programmable Gate (cid:129) LVCMOS, LVTTL, HSTL, and SSTL single-ended signal Arrays (FPGAs) is specifically designed to meet the needs standards of high volume, cost-sensitive consumer electronic (cid:129) 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling (cid:129) 622+ Mb/s data transfer rate per I/O applications. The five-member family offers densities (cid:129) True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL ranging from 100,000 to 1.6 million system gates, as shown differential I/O in Table1. (cid:129) Enhanced Double Data Rate (DDR) support The Spartan-3E family builds on the success of the earlier (cid:129) DDR SDRAM support up to 333 Mb/s Spartan-3 family by increasing the amount of logic per I/O, (cid:129) Abundant, flexible logic resources significantly reducing the cost per logic cell. New features (cid:129) Densities up to 33,192 logic cells, including optional shift improve system performance and reduce the cost of register or distributed RAM support (cid:129) Efficient wide multiplexers, wide logic configuration. These Spartan-3E FPGA enhancements, (cid:129) Fast look-ahead carry logic combined with advanced 90 nm process technology, deliver (cid:129) Enhanced 18 x 18 multipliers with optional pipeline more functionality and bandwidth per dollar than was (cid:129) IEEE 1149.1/1532 JTAG programming/debug port previously possible, setting new standards in the (cid:129) Hierarchical SelectRAM™ memory architecture programmable logic industry. (cid:129) Up to 648 Kbits of fast block RAM Because of their exceptionally low cost, Spartan-3E FPGAs (cid:129) Up to 231 Kbits of efficient distributed RAM are ideally suited to a wide range of consumer electronics (cid:129) Up to eight Digital Clock Managers (DCMs) applications, including broadband access, home (cid:129) Clock skew elimination (delay locked loop) networking, display/projection, and digital television (cid:129) Frequency synthesis, multiplication, division equipment. (cid:129) High-resolution phase shifting (cid:129) Wide frequency range (5MHz to over 300MHz) The Spartan-3E family is a superior alternative to mask (cid:129) Eight global clocks plus eight additional clocks per each half programmed ASICs. FPGAs avoid the high initial cost, the of device, plus abundant low-skew routing lengthy development cycles, and the inherent inflexibility of (cid:129) Configuration interface to industry-standard PROMs conventional ASICs. Also, FPGA programmability permits (cid:129) Low-cost, space-saving SPI serial Flash PROM design upgrades in the field with no hardware replacement (cid:129) x8 or x8/x16 parallel NOR Flash PROM necessary, an impossibility with ASICs. (cid:129) Low-cost Xilinx® Platform Flash with JTAG (cid:129) Complete Xilinx ISE® and WebPACK™ software Features (cid:129) MicroBlaze™ and PicoBlaze embedded processor cores (cid:129) Fully compliant 32-/64-bit 33MHz PCI support (66MHz in (cid:129) Very low cost, high-performance logic solution for some devices) high-volume, consumer-oriented applications (cid:129) Low-cost QFP and BGA packaging options (cid:129) Proven advanced 90-nanometer process technology (cid:129) Common footprints support easy density migration (cid:129) Multi-voltage, multi-standard SelectIO™ interface pins (cid:129) Pb-free packaging options (cid:129) Up to 376 I/O pins or 156 differential signal pairs (cid:129) XA Automotive version available Table 1: Summary of Spartan-3E FPGA Attributes CLB Array Block Maximum System Equivalent (One CLB = Four Slices) Distributed Dedicated Maximum Device RAM DCMs Differential Gates Logic Cells Rows Columns Total Total RAM bits(1) bits(1) Multipliers User I/O I/O Pairs CLBs Slices XC3S100E 100K 2,160 22 16 240 960 15K 72K 4 2 108 40 XC3S250E 250K 5,508 34 26 612 2,448 38K 216K 12 4 172 68 XC3S500E 500K 10,476 46 34 1,164 4,656 73K 360K 20 4 232 92 XC3S1200E 1200K 19,512 60 46 2,168 8,672 136K 504K 28 8 304 124 XC3S1600E 1600K 33,192 76 58 3,688 14,752 231K 648K 36 8 376 156 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. © Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 2

Spartan-3E FPGA Family: Introduction and Ordering Information Architectural Overview The Spartan-3E family architecture consists of five (cid:129) Digital Clock Manager (DCM) Blocks provide fundamental programmable functional elements: self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock (cid:129) Configurable Logic Blocks (CLBs) contain flexible signals. Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs These elements are organized as shown in Figure1. A ring perform a wide variety of logical functions as well as of IOBs surrounds a regular array of CLBs. Each device has store data. two columns of block RAM except for the XC3S100E, which has one column. Each RAM column consists of several (cid:129) Input/Output Blocks (IOBs) control the flow of data 18-Kbit RAM blocks. Each block RAM is associated with a between the I/O pins and the internal logic of the dedicated multiplier. The DCMs are positioned in the center device. Each IOB supports bidirectional data flow plus with two at the top and two at the bottom of the device. The 3-state operation. Supports a variety of signal XC3S100E has only one DCM at the top and bottom, while standards, including four high-performance differential the XC3S1200E and XC3S1600E add two DCMs in the standards. Double Data-Rate (DDR) registers are middle of the left and right sides. included. (cid:129) Block RAM provides data storage in the form of The Spartan-3E family features a rich network of traces that 18-Kbit dual-port blocks. interconnect all five functional elements, transmitting signals among them. Each functional element has an (cid:129) Multiplier Blocks accept two 18-bit binary numbers as associated switch matrix that permits multiple connections inputs and calculate the product. to the routing. X-Ref Target - Figure 1 Figure 1: Spartan-3E Family Architecture DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 3

Spartan-3E FPGA Family: Introduction and Ordering Information Configuration I/O Capabilities Spartan-3E FPGAs are programmed by loading The Spartan-3E FPGA SelectIO interface supports many configuration data into robust, reprogrammable, static popular single-ended and differential standards. Table2 CMOS configuration latches (CCLs) that collectively control shows the number of user I/Os as well as the number of all functional elements and routing resources. The FPGA’s differential I/O pairs available for each device/package configuration data is stored externally in a PROM or some combination. other non-volatile medium, either on or off the board. After Spartan-3E FPGAs support the following single-ended applying power, the configuration data is written to the standards: FPGA using any of seven different modes: (cid:129) 3.3V low-voltage TTL (LVTTL) (cid:129) Master Serial from a Xilinx Platform Flash PROM (cid:129) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, (cid:129) Serial Peripheral Interface (SPI) from an 1.5V, or 1.2V industry-standard SPI serial Flash (cid:129) 3V PCI at 33MHz, and in some devices, 66MHz (cid:129) Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16 parallel NOR Flash (cid:129) HSTL I and III at 1.8V, commonly used in memory applications (cid:129) Slave Serial, typically downloaded from a processor (cid:129) SSTL I at 1.8V and 2.5V, commonly used for memory (cid:129) Slave Parallel, typically downloaded from a processor applications (cid:129) Boundary Scan (JTAG), typically downloaded from a Spartan-3E FPGAs support the following differential processor or system tester. standards: Furthermore, Spartan-3E FPGAs support MultiBoot (cid:129) LVDS configuration, allowing two or more FPGA configuration bitstreams to be stored in a single parallel NOR Flash. The (cid:129) Bus LVDS FPGA application controls which configuration to load next (cid:129) mini-LVDS and when to load it. (cid:129) RSDS (cid:129) Differential HSTL (1.8V, Types I and III) (cid:129) Differential SSTL (2.5V and 1.8V, Type I) (cid:129) 2.5V LVPECL inputs Table 2: Available User I/Os and Differential (Diff) I/O Pairs VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484 Package VQG100 CPG132 TQG144 PQG208 FTG256 FGG320 FGG400 FGG484 Footprint 16x16 8x8 22x22 30.5x30.5 17x17 19x19 21x21 23x23 Size (mm) Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff 66(2) 30 83 35 108 40 XC3S100E - - - - - - - - - - 9(7) (2) (11) (2) (28) (4) 66 30 92 41 108 40 158 65 172 68 XC3S250E - - - - - - (7) (2) (7) (2) (28) (4) (32) (5) (40) (8) 66(3) 30 92 41 158 65 190 77 232 92 XC3S500E - - - - - - (7) (2) (7) (2) (32) (5) (41) (8) (56) (12) 190 77 250 99 304 124 XC3S1200E - - - - - - - - - - (40) (8) (56) (12) (72) (20) 250 99 304 124 376 156 XC3S1600E - - - - - - - - - - (56) (12) (72) (20) (82) (21) Notes: 1. All Spartan-3E devices provided in the same package are pin-compatible as further described in Module4, Pinout Descriptions. 2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. 3. The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical and general references to the VQ100 will apply to the XC3S500E. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 4

Spartan-3E FPGA Family: Introduction and Ordering Information Package Marking Figure2 provides a top marking example for Spartan-3E On the QFP and BGA packages, the optional numerical FPGAs in the quad-flat packages. Figure3 shows the top Stepping Code follows the Lot Code. marking for Spartan-3E FPGAs in BGA packages except The “5C” and “4I” part combinations can have a dual mark the 132-ball chip-scale package (CP132 and CPG132). The of “5C/4I”. Devices with a single mark are only guaranteed markings for the BGA packages are nearly identical to those for the marked speed grade and temperature range. All “5C” for the quad-flat packages, except that the marking is and “4I” part combinations use the Stepping 1 production rotated with respect to the ball A1 indicator. Figure4 shows silicon. the top marking for Spartan-3E FPGAs in the CP132 and CPG132 packages. X-Ref Target - Figure 2 Mask Revision Code Fabrication Code R SPARTANR Process Technology Device Type XC3S250ETM Package PQ208AGQ0525 Date Code D1234567A Stepping Code (optional) Speed Grade 4C Lot Code Temperature Range Pin P1 DS312-1_06_102905 Figure 2: Spartan-3E QFP Package Marking Example X-Ref Target - Figure 3 Mask Revision Code BGA Ball A1 R Fabrication Code SPARTANR Process Code Device Type XC3S250ETM Package FT256AGQ0525 Date Code D1234567A Stepping Code (optional) 4C Lot Code Speed Grade Temperature Range DS312-1_02_090105 Figure 3: Spartan-3E BGA Package Marking Example X-Ref Target - Figure 4 Ball A1 3S250E Device Type Lot Code F1234567-0525 Date Code PHILIPPINES Temperature Range Package C5AGQ 4C C5 = CP132 C6 = CPG132 Speed Grade Process Code Mask Revision Code Fabrication Code DS312-1_05_032105 Figure 4: Spartan-3E CP132 and CPG132 Package Marking Example DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 5

Spartan-3E FPGA Family: Introduction and Ordering Information Ordering Information Spartan-3E FPGAs are available in both standard and temperature ranges. Both the standard –4 and faster –5 Pb-free packaging options for all device/package speed grades are available for the Commercial temperature combinations. All devices are available in Pb-free packages, range. However, only the –4 speed grade is available for the which adds a ‘G’ character to the ordering code. All devices Industrial temperature range. See Table2 for valid are available in either Commercial (C) or Industrial (I) device/package combinations. Example: XC3S250E -4 FT 256 C S1(optional code to specify Stepping 1) Device Type Speed Grade Temperature Range Package Type Number of Pins DS312_03_082409 Device Speed Grade Package Type / Number of Pins Temperature Range (T ) J XC3S100E -4 Standard Performance VQ100 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C) VQG100 XC3S250E -5 High Performance(1) CP132 132-ball Chip-Scale Package (CSP) I Industrial (–40°C to 100°C) CPG132 XC3S500E(2) TQ144 144-pin Thin Quad Flat Pack (TQFP) TQG144 XC3S1200E PQ208 208-pin Plastic Quad Flat Pack (PQFP) PQG208 XC3S1600E FT256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) FTG256 FG320 320-ball Fine-Pitch Ball Grid Array (FBGA) FGG320 FG400 400-ball Fine-Pitch Ball Grid Array (FBGA) FGG400 FG484 484-ball Fine-Pitch Ball Grid Array (FBGA) FGG484 Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range. 2. The XC3S500E VQG100 is available only in the -4 Speed Grade. 3. See DS635 for the XA Automotive Spartan-3E FPGAs. Production Stepping The Spartan-3E FPGA family uses production stepping to Table 3: Spartan-3E Optional Stepping Level Ordering indicate improved capabilities or enhanced features. Stepping Suffix Code Status Stepping 1 is, by definition, a functional superset of Number Stepping 0. Furthermore, configuration bitstreams 0 None or S0 Production generated for any stepping are forward compatible. See 1 S1 Production Table72 for additional details. Xilinx has shipped both Stepping 0 and Stepping 1. Designs The stepping level is optionally marked on the device using operating on the Stepping 0 devices perform similarly on a a single number character, as shown in Figure2, Figure3, Stepping 1 device. Stepping 1 devices have been shipping and Figure4. since 2006. The faster speed grade (-5), Industrial (I grade), Automotive devices, and -4C devices with date codes 0901 (2009) and later, are always Stepping 1 devices. Only -4C devices have shipped as Stepping 0 devices. To specify only the later stepping for the -4C, append an S# suffix to the standard ordering code, where # is the stepping number, as indicated in Table3. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 6

Spartan-3E FPGA Family: Introduction and Ordering Information Revision History The following table shows the revision history for this document. Date Version Revision 03/01/2005 1.0 Initial Xilinx release. 03/21/2005 1.1 Added XC3S250E in CP132 package to Table2. Corrected number of differential I/O pairs for CP132 package. Added package markings for QFP packages (Figure2) and CP132/CPG132 packages (Figure4). 11/23/2005 2.0 Added differential HSTL and SSTL I/O standards. Updated Table2 to indicate number of input-only pins. Added Production Stepping information, including example top marking diagrams. 03/22/2006 3.0 Upgraded data sheet status to Preliminary. Added XC3S100E in CP132 package and updated I/O counts for the XC3S1600E in FG320 package (Table2). Added information about dual markings for – 5C and –4I product combinations to Package Marking. 11/09/2006 3.4 Added 66MHz PCI support and links to the Xilinx PCI LogiCORE data sheet. Indicated that Stepping 1 parts are Production status. Promoted Module1 to Production status. Synchronized all modules to v3.4. 04/18/2008 3.7 Added XC3S500E VQG100 package. Added reference to XA Automotive version. Updated links. 08/26/2009 3.8 Added paragraph to Configuration indicating the device supports MultiBoot configuration. Added package sizes to Table2. Described the speed grade and temperature range guarantee for devices having a single mark in paragraph 3 under Package Marking. Deleted Pb-Free Packaging example under Ordering Information. Revised information under Production Stepping. Revised description of Table3. 10/29/2012 4.0 Added Notice of Disclaimer. This product is not recommended for new designs. Updated Table2 footprint size of PQ208. 07/19/2013 4.1 Removed banner. This product IS recommended for new designs. 12/14/2018 4.2 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024). Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 7

Spartan-3E FPGA Family: Introduction and Ordering Information AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 8

114 Spartan-3E FPGA Family: Functional Description DS312 (v4.2) December 14, 2018 Product Specification Design Documentation Available Xilinx Alerts The functionality of the Spartan®-3E FPGA family is now Create a Xilinx user account and sign up to receive described and updated in the following documents. The automatic e-mail notification whenever this data sheet or topics covered in each guide are listed below. the associated user guides are updated. (cid:129) UG331: Spartan-3 Generation FPGA User Guide Sign Up for Alerts on Xilinx.com https://secure.xilinx.com/webreg/register.do (cid:129) Clocking Resources ?group=myprofile&languageID=1 (cid:129) Digital Clock Managers (DCMs) (cid:129) Block RAM Spartan-3E FPGA Starter Kit (cid:129) Configurable Logic Blocks (CLBs) For specific hardware examples, please see the Spartan-3E - Distributed RAM FPGA Starter Kit board web page, which has links to - SRL16 Shift Registers various design examples and the user guide. - Carry and Arithmetic Logic (cid:129) Spartan-3E FPGA Starter Kit Board page (cid:129) I/O Resources http://www.xilinx.com/s3estarter (cid:129) Embedded Multiplier Blocks (cid:129) UG230: Spartan-3E FPGA Starter Kit User Guide (cid:129) Programmable Interconnect (cid:129) ISE® Design Tools (cid:129) IP Cores (cid:129) Embedded Processing and Control Solutions (cid:129) Pin Types and Package Overview (cid:129) Package Drawings (cid:129) Powering FPGAs (cid:129) Power Management (cid:129) UG332: Spartan-3 Generation Configuration User Guide (cid:129) Configuration Overview - Configuration Pins and Behavior - Bitstream Sizes (cid:129) Detailed Descriptions by Mode - Master Serial Mode using Xilinx® Platform Flash PROM - Master SPI Mode using Commodity SPI Serial Flash PROM - Master BPI Mode using Commodity Parallel NOR Flash PROM - Slave Parallel (SelectMAP) using a Processor - Slave Serial using a Processor - JTAG Mode (cid:129) ISE iMPACT Programming Examples (cid:129) MultiBoot Reconfiguration © Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 9

Spartan-3E FPGA Family: Functional Description Introduction pair of storage elements to the IQ1 and IQ2 lines. The IOB outputs I, IQ1, and IQ2 lead to the FPGA’s internal As described in Architectural Overview, the Spartan-3E logic. The delay element can be set to ensure a hold FPGA architecture consists of five fundamental functional time of zero (see Input Delay Functions). elements: (cid:129) The output path, starting with the O1 and O2 lines, (cid:129) Input/Output Blocks (IOBs) carries data from the FPGA’s internal logic through a multiplexer and then a three-state driver to the IOB (cid:129) Configurable Logic Block (CLB) and Slice Resources pad. In addition to this direct path, the multiplexer (cid:129) Block RAM provides the option to insert a pair of storage elements. (cid:129) Dedicated Multipliers (cid:129) The 3-state path determines when the output driver is (cid:129) Digital Clock Managers (DCMs) high impedance. The T1 and T2 lines carry data from the FPGA’s internal logic through a multiplexer to the The following sections provide detailed information on each output driver. In addition to this direct path, the of these functions. In addition, this section also describes multiplexer provides the option to insert a pair of the following functions: storage elements. (cid:129) Clocking Infrastructure (cid:129) All signal paths entering the IOB, including those (cid:129) Interconnect associated with the storage elements, have an inverter option. Any inverter placed on these paths is (cid:129) Configuration automatically absorbed into the IOB. (cid:129) Powering Spartan-3E FPGAs Input/Output Blocks (IOBs) For additional information, refer to the “Using I/O Resources” chapter in UG331. IOB Overview The Input/Output Block (IOB) provides a programmable, unidirectional or bidirectional interface between a package pin and the FPGA’s internal logic. The IOB is similar to that of the Spartan-3 family with the following differences: (cid:129) Input-only blocks are added (cid:129) Programmable input delays are added to all blocks (cid:129) DDR flip-flops can be shared between adjacent IOBs The unidirectional input-only block has a subset of the full IOB capabilities. Thus there are no connections or logic for an output path. The following paragraphs assume that any reference to output functionality does not apply to the input-only blocks. The number of input-only blocks varies with device size, but is never more than 25% of the total IOB count. Figure5 is a simplified diagram of the IOB’s internal structure. There are three main signal paths within the IOB: the output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or latches. For more information, see Storage Element Functions. The three main signal paths are as follows: (cid:129) The input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay element directly to the I line. After the delay element, there are alternate routes through a DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 10

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 5 T TFF1 T1 D Q CE CK SR REV DDR MUX TCE T2 D Q TFF2 CE CK SR REV Three-state Path VCCO OFF1 O1 D Q CE OTCLK1 CK Pull-Up ESD SR REV DDR I/O MUX Pin OCE Program- Pull- O2 D Q mable Down ESD OFF2 Output CE Driver OTCLK2 CK SR REV Keeper Latch Output Path Programmable I Delay LVCMOS, LVTTL, PCI IQ1 Programmable Delay Single-ended Standards IDDRIN1 D Q using VREF IDDRIN2 IFF1 VREF CE Pin ICLK1 CK ICE SR REV Differential Standards I/O Pin from IQ2 Adjacent D Q IOB IFF2 CE ICLK2 CK SR REV SR REV Input Path DS312-2_19_110606 Figure 5: Simplified IOB Diagram DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 11

Spartan-3E FPGA Family: Functional Description Input Delay Functions Each IOB has a programmable delay block that optionally report generated by the implementation tools, and the delays the input signal. In Figure6, the signal path has a resulting effects on input timing are reported using the coarse delay element that can be bypassed. The input Timing Analyzer tool. signal then feeds a 6-tap delay line. The coarse and tap If the design uses a DCM in the clock path, then the delay delays vary; refer to timing reports for specific delay values. element can be safely set to zero because the All six taps are available via a multiplexer for use as an Delay-Locked Loop (DLL) compensation automatically asynchronous input directly into the FPGA fabric. In this ensures that there is still no input hold time requirement. way, the delay is programmable in 12 steps. Three of the six taps are also available via a multiplexer to the D inputs of Both asynchronous and synchronous values can be the synchronous storage elements. The delay inserted in modified, which is useful where extra delay is required on the path to the storage element can be varied in six steps. clock or data inputs, for example, in interfaces to various The first, coarse delay element is common to both types of RAM. asynchronous and synchronous paths, and must be either These delay values are defined through the used or not used for both paths. IBUF_DELAY_VALUE and the IFD_DELAY_VALUE The delay values are set up in the silicon once at parameters. The default IBUF_DELAY_VALUE is 0, configuration time—they are non-modifiable in device bypassing the delay elements for the asynchronous input. operation. The user can set this parameter to 0-12. The default IFD_DELAY_VALUE is AUTO. IBUF_DELAY_VALUE and The primary use for the input delay element is to adjust the IFD_DELAY_VALUE are independent for each input. If the input delay path to ensure that there is no hold time same input pin uses both registered and non-registered requirement when using the input flip-flop(s) with a global input paths, both parameters can be used, but they must clock. The default value is chosen automatically by the both be in the same half of the total delay (both either Xilinx software tools as the value depends on device size bypassing or using the coarse delay element). and the specific device edge where the flip-flop resides. The value set by the Xilinx ISE software is indicated in the Map X-Ref Target - Figure 6 IFD_DELAY_VALUE Synchronous input (IQ1) D Q Synchronous input (IQ2) D Q Coarse Delay PAD Asynchronous input (I) IBUF_DELAY_VALUE UG331_c10_09_011508 Figure 6: Programmable Fixed Input Delay Elements DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 12

Spartan-3E FPGA Family: Functional Description Storage Element Functions There are three pairs of storage elements in each IOB, one synchronized to the clock signal’s rising edge and pair for each of the three paths. It is possible to configure converting it to bits synchronized on both the rising and the each of these storage elements as an edge-triggered falling edge. The combination of two registers and a D-type flip-flop (FD) or a level-sensitive latch (LD). multiplexer is referred to as a Double-Data-Rate D-type flip-flop (ODDR2). The storage-element pair on either the Output path or the Three-State path can be used together with a special Table4 describes the signal paths associated with the multiplexer to produce Double-Data-Rate (DDR) storage element. transmission. This is accomplished by taking data Table 4: Storage Element Signal Description Storage Element Description Function Signal D Data input Data at this input is stored on the active edge of CK and enabled by CE. For latch operation when the input is enabled, data passes directly to the output Q. Q Data output The data on this output reflects the state of the storage element. For operation as a latch in transparent mode, Q mirrors the data at D. CK Clock input Data is loaded into the storage element on this input’s active edge with CE asserted. CE Clock Enable input When asserted, this input enables CK. If not connected, CE defaults to the asserted state. SR Set/Reset input This input forces the storage element into the state specified by the SRHIGH/SRLOW attributes. The SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not. If both SR and REV are active at the same time, the storage element gets a value of 0. REV Reverse input This input is used together with SR. It forces the storage element into the state opposite from what SR does. The SYNC/ASYNC attribute setting determines whether the REV input is synchronized to the clock or not. If both SR and REV are active at the same time, the storage element gets a value of 0. As shown in Figure5, the upper registers in both the output controls the CE inputs for the register pair on the three-state and three-state paths share a common clock. The OTCLK1 path and ICE does the same for the register pair on the clock signal drives the CK clock inputs of the upper registers input path. on the output and three-state paths. Similarly, OTCLK2 The Set/Reset (SR) line entering the IOB controls all six drives the CK inputs for the lower registers on the output registers, as is the Reverse (REV) line. and three-state paths. The upper and lower registers on the input path have independent clock lines: ICLK1 and ICLK2. In addition to the signal polarity controls described in IOB Overview, each storage element additionally supports the The OCE enable line controls the CE inputs of the upper controls described in Table5. and lower registers on the output path. Similarly, TCE Table 5: Storage Element Options Option Switch Function Specificity FF/Latch Chooses between an edge-triggered flip-flop or a Independent for each storage element level-sensitive latch SYNC/ASYNC Determines whether the SR set/reset control is Independent for each storage element synchronous or asynchronous SRHIGH/SRLOW Determines whether SR acts as a Set, which forces Independent for each storage element, except when using the storage element to a logic 1 (SRHIGH) or a ODDR2. In the latter case, the selection for the upper Reset, which forces a logic 0 (SRLOW) element will apply to both elements. INIT1/INIT0 When Global Set/Reset (GSR) is asserted or after Independent for each storage element, except when using configuration this option specifies the initial state of ODDR2, which uses two IOBs. In the ODDR2 case, the storage element, either set (INIT1) or reset selecting INIT0 for one IOBs applies to both elements (INIT0). By default, choosing SRLOW also selects within the IOB, although INIT1 could be selected for the INIT0; choosing SRHIGH also selects INIT1. elements in the other IOB. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 13

Spartan-3E FPGA Family: Functional Description Double-Data-Rate Transmission Double-Data-Rate (DDR) transmission describes the The storage-element pair on the Three-State path (TFF1 technique of synchronizing signals to both the rising and and TFF2) also can be combined with a local multiplexer to falling edges of the clock signal. Spartan-3E devices use form a DDR primitive. This permits synchronizing the output register pairs in all three IOB paths to perform DDR enable to both the rising and falling edges of a clock. This operations. DDR operation is realized in the same way as for the output path. The pair of storage elements on the IOB’s Output path (OFF1 and OFF2), used as registers, combine with a The storage-element pair on the input path (IFF1 and IFF2) special multiplexer to form a DDR D-type flip-flop (ODDR2). allows an I/O to receive a DDR signal. An incoming DDR This primitive permits DDR transmission where output data clock signal triggers one register, and the inverted clock bits are synchronized to both the rising and falling edges of signal triggers the other register. The registers take turns a clock. DDR operation requires two clock signals (usually capturing bits of the incoming DDR data signal. The 50% duty cycle), one the inverted form of the other. These primitive to allow this functionality is called IDDR2. signals trigger the two registers in alternating fashion, as Aside from high bandwidth data transfers, DDR outputs also shown in Figure7. The Digital Clock Manager (DCM) can be used to reproduce, or mirror, a clock signal on the generates the two clock signals by mirroring an incoming output. This approach is used to transmit clock and data signal, and then shifting it 180 degrees. This approach signals together (source synchronously). A similar ensures minimal skew between the two signals. approach is used to reproduce a clock signal at multiple Alternatively, the inverter inside the IOB can be used to outputs. The advantage for both approaches is that skew invert the clock signal, thus only using one clock line and across the outputs is minimal. both rising and falling edges of that clock line as the two clocks for the DDR flip-flops. X-Ref Target - Figure 7 DCM DCM 180˚0˚ 0˚ FDDR FDDR D1 D1 Q1 Q1 CLK1 CLK1 DDR MUX Q DDR MUX Q D2 D2 Q2 Q2 CLK2 CLK2 DS312-2_20_021105 Figure 7: Two Methods for Clocking the DDR Register Register Cascade Feature IDDR2 In the Spartan-3E family, one of the IOBs in a differential As a DDR input pair, the master IOB registers incoming pair can cascade its input storage elements with those in data on the rising edge of ICLK1 (=D1) and the rising edge the other IOB as part of a differential pair. This is intended to of ICLK2 (=D2), which is typically the same as the falling make DDR operation at high speed much simpler to edge of ICLK1. This data is then transferred into the FPGA implement. The new DDR connections that are available fabric. At some point, both signals must be brought into the are shown in Figure5 (dashed lines), and are only available same clock domain, typically ICLK1. This can be difficult at for routing between IOBs and are not accessible to the high frequencies because the available time is only one half FPGA fabric. Note that this feature is only available when of a clock cycle assuming a 50% duty cycle. See Figure8 using the differential I/O standards LVDS, RSDS, and for a graphical illustration of this function. MINI_LVDS. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 14

Spartan-3E FPGA Family: Functional Description and the rising edge of OCLK2 (=D2), which is typically the X-Ref Target - Figure 8 same as the falling edge of OCLK1. These two bits of data D Q D1 are multiplexed by the DDR mux and forwarded to the PAD output pin. The D2 data signal must be re-synchronized To Fabric from the OCLK1 clock domain to the OCLK2 domain using FPGA slice flip-flops. Placement is critical at high D Q D2 frequencies, because the time available is only one half a clock cycle. See Figure10 for a graphical illustration of this function. ICLK2 ICLK1 The C0 or C1 alignment feature of the ODDR2 flip-flop, originally introduced in the Spartan-3E FPGA family, is not recommended or supported in the ISE development ICLK1 software. The ODDR2 flip-flop without the alignment feature ICLK2 remains fully supported. Without the alignment feature, the ODDR2 feature behaves equivalent to the ODDR flip-flop PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8 on previous Xilinx FPGA families. D1 d d+2 d+4 d+6 d+8 X-Ref Target - Figure 10 D2 d-1 d+1 d+3 d+5 d+7 D1 D Q PAD DS312-2_21_021105 From Figure 8: Input DDR (without Cascade Feature) Fabric In the Spartan-3E device, the signal D2 can be cascaded D2 D Q into the storage element of the adjacent slave IOB. There it is re-registered to ICLK1, and only then fed to the FPGA fabric where it is now already in the same time domain as D1. Here, the FPGA fabric uses only the clock ICLK1 to process the received data. See Figure9 for a graphical OCLK1 OCLK2 illustration of this function. X-Ref Target - Figure 9 OCLK1 D Q D1 OCLK2 PAD D1 d d+2 d+4 d+6 d+8 d+10 To Fabric D2 d+1 d+3 d+5 d+7 d+9 IQ2 IDDRIN2 D Q D Q D2 PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8 DS312-2_23_030105 Figure 10: Output DDR ICLK1 SelectIO Signal Standards ICLK2 The Spartan-3E I/Os feature inputs and outputs that ICLK1 support a wide range of I/O signaling standards (Table6 and Table7). The majority of the I/Os also can be used to ICLK2 form differential pairs to support any of the differential PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8 signaling standards (Table7). D1 d d+2 d+4 d+6 d+8 To define the I/O signaling standard in a design, set the IOSTANDARD attribute to the appropriate setting. Xilinx D2 d-1 d+1 d+3 d+5 d+7 provides a variety of different methods for applying the DS312-2_22_030105 IOSTANDARD for maximum flexibility. For a full description Figure 9: Input DDR Using Spartan-3E Cascade Feature of different methods of applying attributes to control IOSTANDARD, refer to the Xilinx Software Manuals and ODDR2 Help. As a DDR output pair, the master IOB registers data coming from the FPGA fabric on the rising edge of OCLK1 (=D1) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 15

Spartan-3E FPGA Family: Functional Description Spartan-3E FPGAs provide additional input flexibility by IOSTANDARDs that can be combined and if the allowing I/O standards to be mixed in different banks. For a IOSTANDARD is supported as an input only or can be used particular V voltage, Table6 and Table7 list all of the for both inputs and outputs. CCO Table 6: Single-Ended IOSTANDARD Bank Compatibility V Supply/Compatibility Input Requirements CCO Single-Ended Board IOSTANDARD 1.2V 1.5V 1.8V 2.5V 3.3V V Termination REF Voltage (V ) TT Input/ LVTTL - - - - N/R(1) N/R Output Input/ LVCMOS33 - - - - N/R N/R Output Input/ LVCMOS25 - - - Input N/R N/R Output Input/ LVCMOS18 - - Input Input N/R N/R Output Input/ LVCMOS15 - Input Input Input N/R N/R Output Input/ LVCMOS12 Input Input Input Input N/R N/R Output Input/ PCI33_3 - - - - N/R N/R Output Input/ PCI66_3 - - - - N/R N/R Output Input/ HSTL_I_18 - - Input Input 0.9 0.9 Output Input/ HSTL_III_18 - - Input Input 1.1 1.8 Output Input/ SSTL18_I - - Input Input 0.9 0.9 Output Input/ SSTL2_I - - - Input 1.25 1.25 Output Notes: 1. N/R - Not required for input operation. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 16

Spartan-3E FPGA Family: Functional Description Table 7: Differential IOSTANDARD Bank Compatibility V Supply Input Differential CCO Differential Bank Requirements: IOSTANDARD 1.8V 2.5V 3.3V Restriction(1) V REF Input, Applies to Outputs LVDS_25 Input On-chip Differential Termination, Input Only Output Input, Applies to Outputs RSDS_25 Input On-chip Differential Termination, Input Only Output Input, Applies to Outputs MINI_LVDS_25 Input On-chip Differential Termination, Input Only Output LVPECL_25 Input Input Input V is not used for REF Input, these I/O standards BLVDS_25 Input Input Output Input, No Differential Bank DIFF_HSTL_I_18 Input Input Output Restriction Input, (other I/O bank DIFF_HSTL_III_18 Input Input Output restrictions might apply) Input, DIFF_SSTL18_I Input Input Output Input, DIFF_SSTL2_I Input Input Output Notes: 1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs. HSTL and SSTL inputs use the Reference Voltage (V ) to On-Chip Differential Termination REF bias the input-switching threshold. Once a configuration data file is loaded into the FPGA that calls for the I/Os of a Spartan-3E devices provide an on-chip ~120Ω differential given bank to use HSTL/SSTL, a few specifically reserved termination across the input differential receiver terminals. I/O pins on the same bank automatically convert to V The on-chip input differential termination in Spartan-3E inputs. For banks that do not contain HSTL or SSTL, RVEF devices potentially eliminates the external 100Ω termination REF pins remain available for user I/Os or input pins. resistor commonly found in differential receiver circuits. Differential termination is used for LVDS, mini-LVDS, and Differential standards employ a pair of signals, one the RSDS as applications permit. opposite polarity of the other. The noise canceling properties (for example, Common-Mode Rejection) of these On-chip Differential Termination is available in banks with standards permit exceptionally high data transfer rates. This VCCO = 2.5V and is not supported on dedicated input pins. subsection introduces the differential signaling capabilities Set the DIFF_TERM attribute to TRUE to enable Differential of Spartan-3E devices. Termination on a differential I/O pin pair. Each device-package combination designates specific I/O The DIFF_TERM attribute uses the following syntax in the pairs specially optimized to support differential standards. A UCF file: unique L-number, part of the pin name, identifies the INST <I/O_BUFFER_INSTANTIATION_NAME> line-pairs associated with each bank (see Module4, Pinout DIFF_TERM = "<TRUE/FALSE>"; Descriptions). For each pair, the letters P and N designate the true and inverted lines, respectively. For example, the pin names IO_L43P_3 and IO_L43N_3 indicate the true and inverted lines comprising the line pair L43 on Bank 3. V provides current to the outputs and additionally CCO powers the On-Chip Differential Termination. V must be CCO 2.5V when using the On-Chip Differential Termination. The V lines are not required for differential operation. REF To further understand how to combine multiple IOSTANDARDs within a bank, refer to IOBs Organized into Banks, page19. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 17

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 11 X-Ref Target - Figure 12 Spartan-3E Z0 = 50Ω Spartan-3E Pull-up Differential Differential Input Output Ω 0 0 1 Output Path Z0 = 50Ω Input Path Spartan-3E Differential Input Keeper Spartan-3E Z0 = 50Ω wDithiff eOrne-nCtihailp Pull-down Differential Terminator Output Ω DS312-2_25_020807 0 2 1 Figure 12: Keeper Circuit ~ Z0 = 50Ω Slew Rate Control and Drive Strength DS312-2_24_082605 Each IOB has a slew-rate control that sets the output Figure 11: Differential Inputs and Outputs switching edge-rate for LVCMOS and LVTTL outputs. The Pull-Up and Pull-Down Resistors SLEW attribute controls the slew rate and can either be set to SLOW (default) or FAST. Pull-up and pull-down resistors inside each IOB optionally Each LVCMOS and LVTTL output additionally supports up force a floating I/O or Input-only pin to a determined state. to six different drive current strengths as shown in Table8. Pull-up and pull-down resistors are commonly applied to To adjust the drive strength for each output, the DRIVE unused I/Os, inputs, and three-state outputs, but can be attribute is set to the desired drive strength: 2, 4, 6, 8, 12, used on any I/O or Input-only pin. The pull-up resistor and 16. Unless otherwise specified in the FPGA application, connects an IOB to V through a resistor. The resistance CCO the software default IOSTANDARD is LVCMOS25, SLOW value depends on the V voltage (see Module3, DC and CCO slew rate, and 12mA output drive. Switching Characteristics for the specifications). The pull-down resistor similarly connects an IOB to ground with Table 8: Programmable Output Drive Current a resistor. The PULLUP and PULLDOWN attributes and Output Drive Current (mA) library primitives turn on these optional resistors. IOSTANDARD 2 4 6 8 12 16 By default, PULLDOWN resistors terminate all unused I/O and Input-only pins. Unused I/O and Input-only pins can LVTTL ✔ ✔ ✔ ✔ ✔ ✔ alternatively be set to PULLUP or FLOAT. To change the LVCMOS33 ✔ ✔ ✔ ✔ ✔ ✔ unused I/O Pad setting, set the Bitstream Generator LVCMOS25 ✔ ✔ ✔ ✔ ✔ - (BitGen) option UnusedPin to PULLUP, PULLDOWN, or FLOAT. The UnusedPin option is accessed through the LVCMOS18 ✔ ✔ ✔ ✔ - - Properties for Generate Programming File in ISE. See LVCMOS15 ✔ ✔ ✔ - - - Bitstream Generator (BitGen) Options. LVCMOS12 ✔ - - - - - During configuration a Low logic level on the HSWAP pin activates pull-up resistors on all I/O and Input-only pins not High output current drive strength and FAST output slew actively used in the selected configuration mode. rates generally result in fastest I/O performance. However, these same settings generally also result in transmission Keeper Circuit line effects on the printed circuit board (PCB) for all but the shortest board traces. Each IOB has independent slew rate Each I/O has an optional keeper circuit (see Figure12) that and drive strength controls. Use the slowest slew rate and keeps bus lines from floating when not being actively driven. lowest output drive current that meets the performance The KEEPER circuit retains the last logic level on a line after requirements for the end application. all drivers have been turned off. Apply the KEEPER Likewise, due to lead inductance, a given package supports attribute or use the KEEPER library primitive to use the a limited number of simultaneous switching outputs (SSOs) KEEPER circuitry. Pull-up and pull-down resistors override when using fast, high-drive outputs. Only use fast, the KEEPER settings. high-drive outputs when required by the application. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 18

Spartan-3E FPGA Family: Functional Description IOBs Organized into Banks 1. All V pins must be connected within a bank. REF 2. All V lines associated with the bank must be set to The Spartan-3E architecture organizes IOBs into four I/O REF the same voltage level. banks as shown in Figure13. Each bank maintains separate VCCO and VREF supplies. The separate supplies 3. The VREF levels used by all standards assigned to the allow each bank to independently set V . Similarly, the Inputs of the bank must agree. The Xilinx development CCO V supplies can be set for each bank. Refer to Table6 software checks for this. Table6 describes how different REF and Table7 for VCCO and VREF requirements. standards use the VREF supply. When working with Spartan-3E devices, most of the If VREF is not required to bias the input switching thresholds, differential I/O standards are compatible and can be all associated VREF pins within the bank can be used as combined within any given bank. Each bank can support user I/Os or input pins. any two of the following differential standards: LVDS_25 outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As Package Footprint Compatibility an example, LVDS_25 outputs, RSDS_25 outputs, and any Sometimes, applications outgrow the logic capacity of a other differential inputs while using on-chip differential specific Spartan-3E FPGA. Fortunately, the Spartan-3E termination are a valid combination. A combination not family is designed so that multiple part types are available in allowed is a single bank with LVDS_25 outputs, RSDS_25 pin-compatible package footprints, as described in outputs, and MINI_LVDS_25 outputs. Module4, Pinout Descriptions. In some cases, there are X-Ref Target - Figure 13 subtle differences between devices available in the same footprint. These differences are outlined for each package, Bank 0 such as pins that are unconnected on one device but connected on another in the same package or pins that are dedicated inputs on one package but full I/O on another. 3 1 When designing the printed circuit board (PCB), plan for k k n n potential future upgrades and package migration. a a B B The Spartan-3E family is not pin-compatible with any previous Xilinx FPGA family. Bank 2 Dedicated Inputs DS312-2_26_021205 Dedicated Inputs are IOBs used only as inputs. Pin names Figure 13: Spartan-3E I/O Banks (top view) designate a Dedicated Input if the name starts with IP, for I/O Banking Rules example, IP or IP_Lxxx_x. Dedicated inputs retain the full functionality of the IOB for input functions with a single When assigning I/Os to banks, these V rules must be exception for differential inputs (IP_Lxxx_x). For the CCO followed: differential Dedicated Inputs, the on-chip differential termination is not available. To replace the on-chip 1. All V pins on the FPGA must be connected even if a CCO differential termination, choose a differential pair that bank is unused. supports outputs (IO_Lxxx_x) or use an external 100Ω 2. All VCCO lines associated within a bank must be set to termination resistor on the board. the same voltage level. 3. The V levels used by all standards assigned to the ESD Protection CCO I/Os of any given bank must agree. The Xilinx Clamp diodes protect all device pads against damage from development software checks for this. Table6 and Electro-Static Discharge (ESD) as well as excessive voltage Table7 describe how different standards use the V CCO transients. Each I/O has two clamp diodes: one diode supply. extends P-to-N from the pad to V and a second diode CCO 4. If a bank does not have any V requirements, CCO extends N-to-P from the pad to GND. During operation, connect V to an available voltage, such as 2.5V or CCO these diodes are normally biased in the off state. These 3.3V. Some configuration modes might place additional clamp diodes are always connected to the pad, regardless V requirements. Refer to Configuration for more CCO of the signal standard selected. The presence of diodes information. limits the ability of Spartan-3E I/Os to tolerate high signal If any of the standards assigned to the Inputs of the bank voltages. The VIN absolute maximum rating in Table73 of use V , then the following additional rules must be Module3, DC and Switching Characteristics specifies the REF observed: voltage range that I/Os can tolerate. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 19

Spartan-3E FPGA Family: Functional Description Supply Voltages for the IOBs beginning of design operation in the User mode. After the GTS net is released, all user I/Os go active while all unused The IOBs are powered by three supplies: I/Os are pulled down (PULLDOWN). The designer can control how the unused I/Os are terminated after GTS is 1. The V supplies, one for each of the FPGA’s I/O CCO released by setting the Bitstream Generator (BitGen) option banks, power the output drivers. The voltage on the UnusedPin to PULLUP, PULLDOWN, or FLOAT. V pins determines the voltage swing of the output CCO signal. One clock cycle later (default), the Global Write Enable 2. V is the main power supply for the FPGA’s internal (GWE) net is released allowing the RAM and registers to CCINT logic. change states. Once in User mode, any pull-up resistors enabled by HSWAP revert to the user settings and HSWAP 3. V is an auxiliary source of power, primarily to CCAUX is available as a general-purpose I/O. For more information optimize the performance of various FPGA functions on PULLUP and PULLDOWN, see Pull-Up and Pull-Down such as I/O switching. Resistors. I/O and Input-Only Pin Behavior During Behavior of Unused I/O Pins After Power-On, Configuration, and User Mode Configuration In this section, all behavior described for I/O pins also By default, the Xilinx ISE development software applies to input-only pins and dual-purpose I/O pins that are automatically configures all unused I/O pins as input pins not actively involved in the currently-selected configuration with individual internal pull-down resistors to GND. mode. This default behavior is controlled by the UnusedPin All I/O pins have ESD clamp diodes to their respective V CCO bitstream generator (BitGen) option, as described in supply and from GND, as shown in Figure5. The V CCINT Table69. (1.2V), V (2.5V), and V supplies can be applied in CCAUX CCO any order. Before the FPGA can start its configuration JTAG Boundary-Scan Capability process, V , V Bank 2, and V must have CCINT CCO CCAUX reached their respective minimum recommended operating All Spartan-3E IOBs support boundary-scan testing levels indicated in Table74. At this time, all output drivers compatible with IEEE 1149.1/1532 standards. During are in a high-impedance state. V Bank 2, V , and CCO CCINT boundary-scan operations such as EXTEST and HIGHZ the V serve as inputs to the internal Power-On Reset CCAUX pull-down resistor is active. See JTAG Mode for more circuit (POR). information on programming via JTAG. A Low level applied to the HSWAP input enables pull-up resistors on user-I/O and input-only pins from power-on throughout configuration. A High level on HSWAP disables the pull-up resistors, allowing the I/Os to float. HSWAP contains an internal pull-up resistor and defaults to High if left floating. As soon as power is applied, the FPGA begins initializing its configuration memory. At the same time, the FPGA internally asserts the Global Set-Reset (GSR), which asynchronously resets all IOB storage elements to a default Low state. Also see Pin Behavior During Configuration. Upon the completion of initialization and the beginning of configuration, INIT_B goes High, sampling the M0, M1, and M2 inputs to determine the configuration mode. Configuration data is then loaded into the FPGA. The I/O drivers remain in a high-impedance state (with or without pull-up resistors, as determined by the HSWAP input) throughout configuration. At the end of configuration, the GSR net is released, placing the IOB registers in a Low state by default, unless the loaded design reverses the polarity of their respective SR inputs. The Global Three State (GTS) net is released during Start-Up, marking the end of configuration and the DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 20

Spartan-3E FPGA Family: Functional Description Configurable Logic Block (CLB) and (SRL16), and additional multiplexers and carry logic simplify wide logic and arithmetic functions. Most general-purpose Slice Resources logic in a design is automatically mapped to the slice For additional information, refer to the “Using Configurable resources in the CLBs. Each CLB is identical, and the Logic Blocks (CLBs)” chapter in UG331. Spartan-3E family CLB structure is identical to that for the Spartan-3 family. CLB Overview CLB Array The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as The CLBs are arranged in a regular array of rows and combinatorial circuits. Each CLB contains four slices, and columns as shown in Figure14. each slice contains two Look-Up Tables (LUTs) to Each density varies by the number of rows and columns of implement logic and two dedicated storage elements that CLBs (see Table9). can be used as flip-flops or latches. The LUTs can be used as a 16x1 memory (RAM16) or as a 16-bit shift register X-Ref Target - Figure 14 X0Y3 X1Y3 X2Y3 X3Y3 X0Y2 X1Y2 X2Y2 X3Y2 X0Y1 X1Y1 X2Y1 X3Y1 Spartan-3E FPGA X0Y0 X1Y0 X2Y0 X3Y0 IOBs Slice CLB DS312-2_31_021205 Figure 14: CLB Locations Table 9: Spartan-3E CLB Resources CLB CLB CLB LUTs / Equivalent RAM16 / Distributed Device Slices Rows Columns Total(1) Flip-Flops Logic Cells SRL16 RAM Bits XC3S100E 22 16 240 960 1,920 2,160 960 15,360 XC3S250E 34 26 612 2,448 4,896 5,508 2,448 39,168 XC3S500E 46 34 1,164 4,656 9,312 10,476 4,656 74,496 XC3S1200E 60 46 2,168 8,672 17,344 19,512 8,672 138,752 XC3S1600E 76 58 3,688 14,752 29,504 33,192 14,752 236,032 Notes: 1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are embedded in the array (see Figure1 in Module1). Slices LUTs support both logic and memory (including both RAM16 and SRL16 shift registers) while half support logic Each CLB comprises four interconnected slices, as shown only, and the two types alternate throughout the array in Figure16. These slices are grouped in pairs. Each pair is columns. The SLICEL reduces the size of the CLB and organized as a column with an independent carry chain. lowers the cost of the device, and can also provide a The left pair supports both logic and memory functions and performance advantage over the SLICEM. its slices are called SLICEM. The right pair supports logic only and its slices are called SLICEL. Therefore half the DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 21

Spartan-3E FPGA Family: Functional Description .X-Ref Target - Figure 15 WS DI DI D WF[4:1] DS312-2_32_042007 Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has an F7MUX. The lower SLICEL and SLICEM both have an F6MUX. Figure 15: Simplified Diagram of the Left-Hand SLICEM DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 22

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 16 Left-Hand SLICEM Right-Hand SLICEL (Logic or Distributed RAM (Logic Only) or Shift Register) COUT CLB SLICE X1Y1 SLICE X1Y0 COUT Switch Interconnect Matrix CIN to Neighbors SLICE X0Y1 SHIFTOUT SHIFTIN SLICE X0Y0 CIN DS099-2_05_082104 Figure 16: Arrangement of Slices within the CLB Slice Location Designations Slice Overview The Xilinx development software designates the location of A slice includes two LUT function generators and two a slice according to its X and Y coordinates, starting in the storage elements, along with additional logic, as shown in bottom left corner, as shown in Figure14. The letter ‘X’ Figure17. followed by a number identifies columns of slices, Both SLICEM and SLICEL have the following elements in incrementing from the left side of the die to the right. The common to provide logic, arithmetic, and ROM functions: letter ‘Y’ followed by a number identifies the position of each slice in a pair as well as indicating the CLB row, (cid:129) Two 4-input LUT function generators, F and G incrementing from the bottom of the die. Figure16 shows (cid:129) Two storage elements the CLB located in the lower left-hand corner of the die. The SLICEM always has an even ‘X’ number, and the SLICEL (cid:129) Two wide-function multiplexers, F5MUX and FiMUX always has an odd ‘X’ number. (cid:129) Carry and arithmetic logic X-Ref Target - Figure 17 FiMUX FiMUX SRL16 RAM16 Carry Carry LUT4 (G) Register LUT4 (G) Register F5MUX F5MUX SRL16 RAM16 Carry Register Carry Register LUT4 (F) LUT4 (F) Arithmetic Logic Arithmetic Logic SLICEM SLICEL DS312-2_13_020905 Figure 17: Resources in a Slice DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 23

Spartan-3E FPGA Family: Functional Description The SLICEM pair supports two additional functions: Enable (CE), Slice Write Enable (SLICEWE1), and Reset/Set (RS) are shared in common between the two (cid:129) Two 16x1 distributed RAM blocks, RAM16 halves. (cid:129) Two 16-bit shift registers, SRL16 The LUTs located in the top and bottom portions of the slice Each of these elements is described in more detail in the are referred to as “G” and “F”, respectively, or the “G-LUT” following sections. and the “F-LUT”. The storage elements in the top and bottom portions of the slice are called FFY and FFX, Logic Cells respectively. The combination of a LUT and a storage element is known Each slice has two multiplexers with F5MUX in the bottom as a “Logic Cell”. The additional features in a slice, such as portion of the slice and FiMUX in the top portion. Depending the wide multiplexers, carry logic, and arithmetic gates, add on the slice, the FiMUX takes on the name F6MUX, to the capacity of a slice, implementing logic that would F7MUX, or F8MUX, according to its position in the otherwise require additional LUTs. Benchmarks have multiplexer chain. The lower SLICEL and SLICEM both shown that the overall slice is equivalent to 2.25 simple logic have an F6MUX. The upper SLICEM has an F7MUX, and cells. This calculation provides the equivalent logic cell the upper SLICEL has an F8MUX. count shown in Table9. The carry chain enters the bottom of the slice as CIN and exits at the top as COUT. Five multiplexers control the chain: Slice Details CYINIT, CY0F, and CYMUXF in the bottom portion and CY0G and CYMUXG in the top portion. The dedicated Figure15 is a detailed diagram of the SLICEM. It represents arithmetic logic includes the exclusive-OR gates XORF and a superset of the elements and connections to be found in XORG (bottom and top portions of the slice, respectively) all slices. The dashed and gray lines (blue when viewed in as well as the AND gates FAND and GAND (bottom and top color) indicate the resources found only in the SLICEM and portions, respectively). not in the SLICEL. See Table10 for a description of all the slice input and Each slice has two halves, which are differentiated as top output signals. and bottom to keep them distinct from the upper and lower slices in a CLB. The control inputs for the clock (CLK), Clock Table 10: Slice Inputs and Outputs Name Location Direction Description F[4:1] SLICEL/M Bottom Input F-LUT and FAND inputs G[4:1] SLICEL/M Top Input G-LUT and GAND inputs or Write Address (SLICEM) BX SLICEL/M Bottom Input Bypass to or output (SLICEM) or storage element, or control input to F5MUX, input to carry logic, or data input to RAM (SLICEM) BY SLICEL/M Top Input Bypass to or output (SLICEM) or storage element, or control input to FiMUX, input to carry logic, or data input to RAM (SLICEM) BXOUT SLICEM Bottom Output BX bypass output BYOUT SLICEM Top Output BY bypass output ALTDIG SLICEM Top Input Alternate data input to RAM DIG SLICEM Top Output ALTDIG or SHIFTIN bypass output SLICEWE1 SLICEM Common Input RAM Write Enable F5 SLICEL/M Bottom Output Output from F5MUX; direct feedback to FiMUX FXINA SLICEL/M Top Input Input to FiMUX; direct feedback from F5MUX or another FiMUX FXINB SLICEL/M Top Input Input to FiMUX; direct feedback from F5MUX or another FiMUX Fi SLICEL/M Top Output Output from FiMUX; direct feedback to another FiMUX CE SLICEL/M Common Input FFX/Y Clock Enable SR SLICEL/M Common Input FFX/Y Set or Reset or RAM Write Enable (SLICEM) CLK SLICEL/M Common Input FFX/Y Clock or RAM Clock (SLICEM) SHIFTIN SLICEM Top Input Data input to G-LUT RAM DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 24

Spartan-3E FPGA Family: Functional Description Table 10: Slice Inputs and Outputs (Cont’d) Name Location Direction Description SHIFTOUT SLICEM Bottom Output Shift data output from F-LUT RAM CIN SLICEL/M Bottom Input Carry chain input COUT SLICEL/M Top Output Carry chain output X SLICEL/M Bottom Output Combinatorial output Y SLICEL/M Top Output Combinatorial output XB SLICEL/M Bottom Output Combinatorial output from carry or F-LUT SRL16 (SLICEM) YB SLICEL/M Top Output Combinatorial output from carry or G-LUT SRL16 (SLICEM) XQ SLICEL/M Bottom Output FFX output YQ SLICEL/M Top Output FFY output Main Logic Paths 2. Bypass the LUT, and then pass through a storage element via the D input before exiting as XQ (or YQ). Central to the operation of each slice are two nearly 3. Control the wide function multiplexer F5MUX (or identical data paths at the top and bottom of the slice. The FiMUX). description that follows uses names associated with the bottom path. (The top path names appear in parentheses.) 4. Via multiplexers, serve as an input to the carry chain. The basic path originates at an interconnect switch matrix 5. Drive the DI input of the LUT. outside the CLB. See Interconnect for more information on 6. BY can control the REV inputs of both the FFY and FFX the switch matrix and the routing connections. storage elements. See Storage Element Functions. Four lines, F1 through F4 (or G1 through G4 on the upper 7. Finally, the DIG_MUX multiplexer can switch BY onto path), enter the slice and connect directly to the LUT. Once the DIG line, which exits the slice. inside the slice, the lower 4-bit path passes through a LUT ‘F’ (or ‘G’) that performs logic operations. The LUT Data The control inputs CLK, CE, SR, BX and BY have output, ‘D’, offers five possible paths: programmable polarity. The LUT inputs do not need programmable polarity because their function can be 1. Exit the slice via line “X” (or “Y”) and return to inverted inside the LUT. interconnect. The sections that follow provide more detail on individual 2. Inside the slice, “X” (or “Y”) serves as an input to the functions of the slice. DXMUX (or DYMUX) which feeds the data input, “D”, of the FFX (or FFY) storage element. The “Q” output of the Look-Up Tables storage element drives the line XQ (or YQ) which exits the slice. The Look-Up Table or LUT is a RAM-based function 3. Control the CYMUXF (or CYMUXG) multiplexer on the generator and is the main resource for implementing logic carry chain. functions. Furthermore, the LUTs in each SLICEM pair can be configured as Distributed RAM or a 16-bit shift register, 4. With the carry chain, serve as an input to the XORF (or as described later. XORG) exclusive-OR gate that performs arithmetic operations, producing a result on “X” (or “Y”). Each of the two LUTs (F and G) in a slice have four logic 5. Drive the multiplexer F5MUX to implement logic inputs (A1-A4) and a single output (D). Any four-variable functions wider than four bits. The “D” outputs of both Boolean logic operation can be implemented in one LUT. the F-LUT and G-LUT serve as data inputs to this Functions with more inputs can be implemented by multiplexer. cascading LUTs or by using the wide function multiplexers that are described later. In addition to the main logic paths described above, there are two bypass paths that enter the slice as BX and BY. The output of the LUT can connect to the wide multiplexer Once inside the FPGA, BX in the bottom half of the slice (or logic, the carry and arithmetic logic, or directly to a CLB BY in the top half) can take any of several possible output or to the CLB storage element. See Figure18. branches: 1. Bypass both the LUT and the storage element, and then exit the slice as BXOUT (or BYOUT) and return to interconnect. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 25

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 18 Wide Multiplexers Y For additional information, refer to the “Using Dedicated 4 Multiplexers” chapter in UG331. G[4:1] A[4:1] D YQ FFY Wide-function multiplexers effectively combine LUTs in G-LUT order to permit more complex logic operations. Each slice has two of these multiplexers with F5MUX in the bottom portion of the slice and FiMUX in the top portion. The X F5MUX multiplexes the two LUTs in a slice. The FiMUX multiplexes two CLB inputs which connect directly to the 4 F[4:1] A[4:1] D XQ F5MUX and FiMUX results from the same slice or from FFX other slices. See Figure19. F-LUT DS312-2_33_111105 Figure 18: LUT Resources in a Slice X-Ref Target - Figure 19 FiMUX FXINA 1 FX (Local Feedback to FXIN) FXINB 0 Y (General Interconnect) BY D Q YQ F5MUX F[4:1] LUT 1 F5 (Local Feedback to FXIN) G[4:1] LUT 0 X (General Interconnect) BX D Q XQ x312-2_34_021205 Figure 19: Dedicated Multiplexers in Spartan-3E CLB Depending on the slice, FiMUX takes on the name F6MUX, F7MUX, or F8MUX. The designation indicates the number of inputs possible without restriction on the function. For example, an F7MUX can generate any function of seven inputs. Figure20 shows the names of the multiplexers in each position in the Spartan-3E CLB. The figure also includes the direct connections within the CLB, along with the F7MUX connection to the CLB below. Each mux can create logic functions of more inputs than indicated by its name. The F5MUX, for example, can generate any function of five inputs, with four inputs duplicated to two LUTs and the fifth input controlling the mux. Because each LUT can implement independent 2:1 muxes, the F5MUX can combine them to create a 4:1 mux, which is a six-input function. If the two LUTs have completely independent sets of inputs, some functions of all nine inputs can be implemented. Table11 shows the connections for each multiplexer and the number of inputs possible for different types of functions. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 26

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 20 FXINB F8 X FXINA F5 F5 FXINB FX F6 FXINA F5 F5 FXINB FX F7 FXINA F5 F5 FXINB F6 FX FXINA F5 F5 DS312-2_38_021305 Figure 20: MUXes and Dedicated Feedback in Spartan-3E CLB Table 11: MUX Capabilities Total Number of Inputs per Function MUX Usage Input Source For Limited For Any Function For MUX Functions F5MUX F5MUX LUTs 5 6 (4:1 MUX) 9 FiMUX F6MUX F5MUX 6 11 (8:1 MUX) 19 F7MUX F6MUX 7 20 (16:1 MUX) 39 F8MUX F7MUX 8 37 (32:1 MUX) 79 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 27

Spartan-3E FPGA Family: Functional Description The wide multiplexers can be used by the automatic tools or instantiated in a design using a component such as the F5MUX. The symbol, signals, and function are described in Figure21, Table12, and Table13. The description is similar for the F6MUX, F7MUX, and F8MUX. Each has versions with a general output, local output, or both. X-Ref Target - Figure 21 I0 0 LO I1 1 O S DS312-2_35_021205 Figure 21: F5MUX with Local and General Outputs Table 12: F5MUX Inputs and Outputs Signal Function I0 Input selected when S is Low I1 Input selected when S is High S Select input LO Local Output that connects to the F5 or FX CLB pins, which use local feedback to the FXIN inputs to the FiMUX for cascading O General Output that connects to the general-purpose combinatorial or registered outputs of the CLB Table 13: F5MUX Function Inputs Outputs S I0 I1 O LO 0 1 X 1 1 0 0 X 0 0 1 X 1 1 1 1 X 0 0 0 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 28

Spartan-3E FPGA Family: Functional Description Carry and Arithmetic Logic The carry chain enters the slice as CIN and exits as COUT, controlled by several multiplexers. The carry chain connects For additional information, refer to the “Using Carry and directly from one CLB to the CLB above. The carry chain Arithmetic Logic” chapter in UG331. can be initialized at any point from the BX (or BY) inputs. The carry chain, together with various dedicated arithmetic The dedicated arithmetic logic includes the exclusive-OR logic gates, support fast and efficient implementations of gates XORF and XORG (upper and lower portions of the math operations. The carry logic is automatically used for slice, respectively) as well as the AND gates GAND and most arithmetic functions in a design. The gates and FAND (upper and lower portions, respectively). These gates multiplexers of the carry and arithmetic logic can also be work in conjunction with the LUTs to implement efficient used for general-purpose logic, including simple wide arithmetic functions, including counters and multipliers, Boolean functions. typically at two bits per slice. See Figure22 and Table14. X-Ref Target - Figure 22 COUT YB 1 CYMUXG Y G[4:1] A[4:1] CYSELG G1 G2 G-LUT D YQ XORG FFY CY0G GAND 1 0 BY XB 1 4 CYMUXF X F[4:1] A[4:1] CYSELF F1 F2 F-LUT D XQ XORF FFX CY0F FAND 1 CYINIT 0 BX CIN DS312-2_14_021305 Figure 22: Carry Logic Table 14: Carry Logic Functions Function Description CYINIT Initializes carry chain for a slice. Fixed selection of: · CIN carry input from the slice below · BX input CY0F Carry generation for bottom half of slice. Fixed selection of: · F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated) · FAND gate for multiplication · BX input for carry initialization · Fixed 1 or 0 input for use as a simple Boolean function DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 29

Spartan-3E FPGA Family: Functional Description Table 14: Carry Logic Functions (Cont’d) Function Description CY0G Carry generation for top half of slice. Fixed selection of: · G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated) · GAND gate for multiplication · BY input for carry initialization · Fixed 1 or 0 input for use as a simple Boolean function CYMUXF Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of: · CYINIT carry propagation (CYSELF = 1) · CY0F carry generation (CYSELF = 0) CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of: · CYMUXF carry propagation (CYSELG = 1) · CY0G carry generation (CYSELG = 0) CYSELF Carry generation or propagation select for bottom half of slice. Fixed selection of: · F-LUT output (typically XOR result) · Fixed 1 to always propagate CYSELG Carry generation or propagation select for top half of slice. Fixed selection of: · G-LUT output (typically XOR result) · Fixed 1 to always propagate XORF Sum generation for bottom half of slice. Inputs from: · F-LUT · CYINIT carry signal from previous stage Result is sent to either the combinatorial or registered output for the top of the slice. XORG Sum generation for top half of slice. Inputs from: · G-LUT · CYMUXF carry signal from previous stage Result is sent to either the combinatorial or registered output for the top of the slice. FAND Multiplier partial product for bottom half of slice. Inputs: · F-LUT F1 input · F-LUT F2 input Result is sent through CY0F to become the carry generate signal into CYMUXF GAND Multiplier partial product for top half of slice. Inputs: · G-LUT G1 input · G-LUT G2 input Result is sent through CY0G to become the carry generate signal into CYMUXG The basic usage of the carry logic is to generate a half-sum X-Ref Target - Figure 23 in the LUT via an XOR function, which generates or LUT COUT B propagates a carry out COUT via the carry mux CYMUXF (or CYMUXG), and then complete the sum with the MUXCY A dedicated XORF (or XORG) gate and the carry input CIN. This structure allows two bits of an arithmetic function in Sum each slice. The CYMUXF (or CYMUXG) can be instantiated XORCY using the MUXCY element, and the XORF (or XORG) can CIN be instantiated using the XORCY element. DS312-2_37_021305 Figure 23: Using the MUXCY and XORCY in the Carry The FAND (or GAND) gate is used for partial product Logic multiplication and can be instantiated using the MULT_AND component. Partial products are generated by two-input The FAND (or GAND) gate is used to duplicate one of the AND gates and then added. The carry logic is efficient for partial products, while the LUT generates both partial the adder, but one of the inputs must be outside the LUT as products and the XOR function, as shown in Figure24. shown in Figure23. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 30

Spartan-3E FPGA Family: Functional Description Storage Elements X-Ref Target - Figure 24 LUT Am COUT The storage element, which is programmable as either a B n+1 D-type flip-flop or a level-sensitive transparent latch, Am+1 provides a means for synchronizing data to a clock signal, Bn among other uses. The storage elements in the top and P bottom portions of the slice are called FFY and FFX, m+1 respectively. FFY has a fixed multiplexer on the D input MULT_AND CIN selecting either the combinatorial output Y or the bypass DS312-2_39_021305 signal BY. FFX selects between the combinatorial output X Figure 24: Using the MULT_AND for Multiplication in or the bypass signal BX. Carry Logic The functionality of a slice storage element is identical to The MULT_AND is useful for small multipliers. Larger that described earlier for the I/O storage elements. All multipliers can be built using the dedicated 18x18 multiplier signals have programmable polarity; the default active-High blocks (see Dedicated Multipliers). function is described. Table 15: Storage Element Signals Signal Description D Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High during the Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate enable (GE) are High and R and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output of the latch remains unchanged as long as G or GE remains Low. Q Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch. C Clock for edge-triggered flip-flops. G Gate for level-sensitive latches. CE Clock Enable for flip-flops. GE Gate Enable for latches. S Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. A latch output is immediately set, output High. R Synchronous Reset (Q = Low); has precedence over Set. PRE Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. A latch output is immediately set, output High. CLR Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low SR CLB input for R, S, CLR, or PRE REV CLB input for opposite of SR. Must be asynchronous or synchronous to match SR. The control inputs R, S, CE, and C are all shared between Table 16: FD Flip-Flop Functionality with Synchronous the two flip-flops in a slice. Reset, Set, and Clock Enable X-Ref Target - Figure 25 Inputs Outputs S R S CE D C Q FDRSE 1 X X X ↑ 0 D Q CE 0 1 X X ↑ 1 C 0 0 0 X X No Change R 0 0 1 1 ↑ 1 DS312-2_40_021305 Figure 25: FD Flip-Flop Component with Synchronous 0 0 1 0 ↑ 0 Reset, Set, and Clock Enable DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 31

Spartan-3E FPGA Family: Functional Description Initialization Distributed RAM The CLB storage elements are initialized at power-up, For additional information, refer to the “Using Look-Up during configuration, by the global GSR signal, and by the Tables as Distributed RAM” chapter in UG331. individual SR or REV inputs to the CLB. The storage The LUTs in the SLICEM can be programmed as distributed elements can also be re-initialized using the GSR input on RAM. This type of memory affords moderate amounts of the STARTUP_SPARTAN3E primitive. See Global Controls data buffering anywhere along a data path. One SLICEM (STARTUP_SPARTAN3E). LUT stores 16 bits (RAM16). The four LUT inputs F[4:1] or Table 17: Slice Storage Element Initialization G[4:1] become the address lines labeled A[4:1] in the device model and A[3:0] in the design components, Signal Description providing a 16x1 configuration in one LUT. Multiple SLICEM SR Set/Reset input. Forces the storage element into the LUTs can be combined in various ways to store larger state specified by the attribute SRHIGH or SRLOW. amounts of data, including 16x4, 32x2, or 64x1 SRHIGH forces a logic 1 when SR is asserted. SRLOW forces a logic 0. For each slice, set and reset configurations in one CLB. The fifth and sixth address lines can be set to be synchronous or asynchronous. required for the 32-deep and 64-deep configurations, REV Reverse of Set/Reset input. A second input (BY) respectively, are implemented using the BX and BY inputs, forces the storage element into the opposite state. which connect to the write enable logic for writing and the The reset condition is predominant over the set F5MUX and F6MUX for reading. condition if both are active. Same synchronous/asynchronous setting as for SR. Writing to distributed RAM is always synchronous to the SLICEM clock (WCLK for distributed RAM) and enabled by GSR Global Set/Reset. GSR defaults to active High but can be inverted by adding an inverter in front of the GSR the SLICEM SR input which functions as the active-High input of the STARTUP_SPARTAN3E element. The Write Enable (WE). The read operation is asynchronous, initial state after configuration or GSR is defined by a and, therefore, during a write, the output initially reflects the separate INIT0 and INIT1 attribute. By default, setting old data at the address being written. the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. The distributed RAM outputs can be captured using the flip-flops within the SLICEM element. The WE write-enable control for the RAM and the CE clock-enable control for the flip-flop are independent, but the WCLK and CLK clock inputs are shared. Because the RAM read operation is asynchronous, the output data always reflects the currently addressed RAM location. A dual-port option combines two LUTs so that memory access is possible from two independent data lines. The same data is written to both 16x1 memories but they have independent read address lines and outputs. The dual-port function is implemented by cascading the G-LUT address lines, which are used for both read and write, to the F-LUT write address lines (WF[4:1] in Figure15), and by cascading the G-LUT data input D1 through the DIF_MUX in Figure15 and to the D1 input on the F-LUT. One CLB provides a 16x1 dual-port memory as shown in Figure26. Any write operation on the D input and any read operation on the SPO output can occur simultaneously with and independently from a read operation on the second read-only port, DPO. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 32

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 26 SLICEM D 16x1 SPO LUT A[3:0] RAM (Read/ Optional Write) Register WE WCLK DPO 16x1 LUT RAM DPRA[3:0] (Read Optional Only) Register DS312-2_41_021305 Figure 26: RAM16X1D Dual-Port Usage X-Ref Target - Figure 27 Table 19: Distributed RAM Signals RAM16X1D WE SPO Signal Description D WCLK The clock is used for synchronous writes. The WCLK DPO data and the address input pins have setup A0 times referenced to the WCLK pin. Active on A1 the positive edge by default with built-in A2 programmable polarity. A3 DPRA0 WE The enable pin affects the write functionality of DPRA1 the port. An inactive Write Enable prevents DPRA2 any writing to memory cells. An active Write DPRA3 Enable causes the clock edge to write the data DS312-2_42_021305 input signal to the memory location pointed to by the address inputs. Active High by default Figure 27: Dual-Port RAM Component with built-in programmable polarity. Table 18: Dual-Port RAM Function A0, A1, A2, A3 The address inputs select the memory cells for (A4, A5) read or write. The width of the port determines Inputs Outputs the required address inputs. WE (mode) WCLK D SPO DPO D The data input provides the new data value to be written into the RAM. 0 (read) X X data_a data_d O, SPO, and The data output O on single-port RAM or the 1 (read) 0 X data_a data_d DPO SPO and DPO outputs on dual-port RAM 1 (read) 1 X data_a data_d reflects the contents of the memory cells referenced by the address inputs. Following an 1 (write) ↑ D D data_d active write clock edge, the data out (O or 1 (read) ↓ X data_a data_d SPO) reflects the newly written data. Notes: The INIT attribute can be used to preload the memory with 1. data_a = word addressed by bits A3-A0. data during FPGA configuration. The default initial contents 2. data_d = word addressed by bits DPRA3-DPRA0. for RAM is all zeros. If the WE is held Low, the element can be considered a ROM. The ROM function is possible even in the SLICEL. The global write enable signal, GWE, is asserted automatically at the end of device configuration to enable all writable elements. The GWE signal guarantees that the DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 33

Spartan-3E FPGA Family: Functional Description initialized distributed RAM contents are not disturbed during X-Ref Target - Figure 29 the configuration process. SRLC16E D Q The distributed RAM is useful for smaller amounts of CE Q15 memory. Larger memory requirements can use the CLK dedicated 18Kbit RAM blocks (see Block RAM). A0 A1 A2 Shift Registers A3 For additional information, refer to the “Using Look-Up DS312-2_43_021305 Tables as Shift Registers (SRL16)” chapter in UG331. Figure 29: SRL16 Shift Register Component with Cascade and Clock Enable It is possible to program each SLICEM LUT as a 16-bit shift register (see Figure28). Used in this way, each LUT can The functionality of the shift register is shown in Table20. delay serial data anywhere from 1 to 16 clock cycles without The SRL16 shifts on the rising edge of the clock input when using any of the dedicated flip-flops. The resulting the Clock Enable control is High. This shift register cannot programmable delays can be used to balance the timing of be initialized either during configuration or during operation data pipelines. except by shifting data into it. The clock enable and clock inputs are shared between the two LUTs in a SLICEM. The The SLICEM LUTs cascade from the G-LUT to the F-LUT clock enable input is automatically kept active if unused. through the DIFMUX (see Figure15). SHIFTIN and SHIFTOUT lines cascade a SLICEM to the SLICEM below Table 20: SRL16 Shift Register Function to form larger shift registers. The four SLICEM LUTs of a Inputs Outputs single CLB can be combined to produce delays up to 64 clock cycles. It is also possible to combine shift registers Am CLK CE D Q Q15 across more than one CLB. Am X 0 X Q[Am] Q[15] X-Ref Target - Figure 28 Am ↑ 1 D Q[Am-1] Q[15] SHIFTIN SRLC16 Notes: 1. m = 0, 1, 2, 3. SHIFT-REG A[3:0] 4 A[3:0] D Output MC15 Registered D Q Output WS DI DI (BY) WSG (optional) CE (SR) WE CLK CK SHIFTOUT or YB X465_03_040203 Figure 28: Logic Cell SRL16 Structure Each shift register provides a shift output MC15 for the last bit in each LUT, in addition to providing addressable access to any bit in the shift register through the normal D output. The address inputs A[3:0] are the same as the distributed RAM address lines, which come from the LUT inputs F[4:1] or G[4:1]. At the end of the shift register, the CLB flip-flop can be used to provide one more shift delay for the addressable bit. The shift register element is known as the SRL16 (Shift Register LUT 16-bit), with a ‘C’ added to signify a cascade ability (Q15 output) and ‘E’ to indicate a Clock Enable. See Figure29 for an example of the SRLC16E component. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 34

Spartan-3E FPGA Family: Functional Description Block RAM and write operations. There are four basic data paths, as shown in Figure30: For additional information, refer to the “Using Block RAM” 1. Write to and read from Port A chapter in UG331. 2. Write to and read from Port B Spartan-3E devices incorporate 4 to 36 dedicated block RAMs, which are organized as dual-port configurable 3. Data transfer from Port A to Port B 18Kbit blocks. Functionally, the block RAM is identical to 4. Data transfer from Port B to Port A the Spartan-3 architecture block RAM. Block RAM X-Ref Target - Figure 30 synchronously stores large amounts of data while distributed RAM, previously described, is better suited for Write Read 3 buffering small amounts of data anywhere along signal paths. This section describes basic block RAM functions. 4 Read Write A Spartan-3E B Einaitciahl bvalolucke sR, AdMef aisu lct osnigfingaulr vaablluee b oyf stehteti nogu ttphuet creognitsetnetr’ss, ort Dual-Port ort P P Block RAM port aspect ratios, and write modes. Block RAM can be used in single-port or dual-port modes. Write Write 1 2 Arrangement of RAM Blocks on Die Read Read The block RAMs are located together with the multipliers on DS312-2_01_020705 the die in one or two columns depending on the size of the Figure 30: Block RAM Data Paths device. The XC3S100E has one column of block RAM. The Spartan-3E devices ranging from the XC3S250E to Number of Ports XC3S1600E have two columns of block RAM. Table21 A choice among primitives determines whether the block shows the number of RAM blocks, the data storage RAM functions as dual- or single-port memory. A name of capacity, and the number of columns for each device. the form RAMB16_S[w ]_S[w ] calls out the dual-port Row(s) of CLBs are located above and below each block A B RAM column. primitive, where the integers wA and wB specify the total data path width at ports A and B, respectively. Thus, a Table 21: Number of RAM Blocks by Device RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A and an 18-bit Port B. A name of the form RAMB16_S[w] Total Total identifies the single-port primitive, where the integer w Addressable Number of Device Number of Locations Columns specifies the total data path width of the lone port A. A RAM Blocks (bits) RAMB16_S18 is a single-port RAM with an 18-bit port. XC3S100E 4 73,728 1 Port Aspect Ratios XC3S250E 12 221,184 2 XC3S500E 20 368,640 2 Each port of the block RAM can be configured independently to select a number of different possible XC3S1200E 28 516,096 2 widths for the data input (DI) and data output (DO) signals XC3S1600E 36 663,552 2 as shown in Table22. Immediately adjacent to each block RAM is an embedded 18x18 hardware multiplier. The upper 16 bits of the block RAM's Port A Data input bus are shared with the upper 16 bits of the A multiplicand input bus of the multiplier. Similarly, the upper 16 bits of Port B's data input bus are shared with the B multiplicand input bus of the multiplier. The Internal Structure of the Block RAM The block RAM has a dual port structure. The two identical data ports called A and B permit independent access to the common block RAM, which has a maximum capacity of 18,432 bits, or 16,384 bits with no parity bits (see parity bits description in Table22). Each port has its own dedicated set of data, control, and clock lines for synchronous read DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 35

Spartan-3E FPGA Family: Functional Description Table 22: Port Aspect Ratios Total Data DI/DO Data DIP/DOP ADDR No. of Block RAM DI/DO DIP/DOP ADDR Path Width Bus Width Parity Bus Bus Width Addressable Capacity [w-p-1:0] [p-1:0] [r-1:0] (w bits) (w-p bits)(1) Width (p bits) (r bits)(2) Locations (n)(3) (w*n bits)(4) 1 1 0 14 [0:0] - [13:0] 16,384 16,384 2 2 0 13 [1:0] - [12:0] 8,192 16,384 4 4 0 12 [3:0] - [11:0] 4,096 16,384 9 8 1 11 [7:0] [0:0] [10:0] 2,048 18,432 18 16 2 10 [15:0] [1:0] [9:0] 1,024 18,432 36 32 4 9 [31:0] [3:0] [8:0] 512 18,432 Notes: 1. The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p). 2. The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as: r = 14 – [log(w–p)/log9(2)]. 3. The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2r. 4. The product of w and n yields the total block RAM capacity. If the data bus width of Port A differs from that of Port B, the block RAM automatically performs a bus-matching function as described in Figure31. When data is written to a port with a narrow bus and then read from a port with a wide bus, the latter port effectively combines “narrow” words to form “wide” words. Similarly, when data is written into a port with a wide bus and then read from a port with a narrow bus, the latter port divides “wide” words to form “narrow” words. Parity bits are not available if the data port width is configured as x4, x2, or x1. For example, if a x36 data word (32 data, 4 parity) is addressed as two x18 halfwords (16 data, 2 parity), the parity bits associated with each data byte are mapped within the block RAM to the appropriate parity bits. The same effect happens when the x36 data word is mapped as four x9 words. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 36

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 31 Parity Data Address 35 34 33 32 31 24 23 16 15 8 7 0 512x36 P3 P2 P1 P0 Byte 3 Byte 2 Byte 1 Byte 0 0 17 16 15 8 7 0 P3 P2 Byte 3 Byte 2 1 1Kx18 P1 P0 Byte 1 Byte 0 0 2K(1bP6iatKsrb iptiytas rO idtypa)ttaio,nal PP823 7 BByyttee 23 0 23 2Kx9 P1 Byte 1 1 P0 Byte 0 0 3 2 1 0 7 6 5 4 7 B y te 3 3 2 1 0 6 4Kx4 7 6 5 4 1 3B2yt1e 00 0 1 0 7 6 F 5 e34 E 3yt2 D B 1 0 C ya) 8Kx2 Parits dat 7 6 3 No 6Kbit 35 Byte024 12 (1 1 0 0 0 7 1F e36 1E yt5 1D B 4 1C 16Kx1 3 3 0 2 2 e yt1 1 B 0 0 DS312-2_02_102105 Figure 31: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 37

Spartan-3E FPGA Family: Functional Description Block RAM Port Signal Definitions Design Note Whenever a block RAM port is enabled (ENA or Representations of the dual-port primitive ENB=High), all address transitions must meet the data RAMB16_S[w ]_S[w ] and the single-port primitive A B sheet setup and hold times with respect to the port clock RAMB16_S[w] with their associated signals are shown in (CLKA or CLKB), as shown in Table103, page139.This Figure32a and Figure32b, respectively. These signals are requirement must be met even if the RAM read output is of defined in Table23. The control signals (WE, EN, CLK, and no interest. SSR) on the block RAM are active High. However, optional inverters on the control signals change the polarity of the active edge to active Low. X-Ref Target - Figure 32 WEA RAMB16_SWA_SWB ENA SSRA DOPA[p –1:0] A CLKA DOA[w –p –1:0] ADDRA[r –1:0] A A A DIA[w –p –1:0] A A DIPA[p –1:0] A WEB WE RAMB16_Sw ENB EN SSRB DOPB[p –1:0] SSR B DOP[p–1:0] CLKB CLK DOB[w –p –1:0] ADDRB[r –1:0] B B ADDR[r–1:0] DO[w–p–1:0] B DIB[w –p –1:0] DI[w–p–1:0] B B DIPB[p –1:0] DIP[p–1:0] B (a) Dual-Port (b) Single-Port DS312-2_03_111105 Notes: 1. w and w are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively. A B 2. p and p are integers that indicate the number of data path lines serving as parity bits. A B 3. r and r are integers representing the address bus width at ports A and B, respectively. A B 4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity. Figure 32: Block RAM Primitives DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 38

Spartan-3E FPGA Family: Functional Description Table 23: Block RAM Port Signals Port A Port B Signal Signal Signal Direction Function Description Name Name Address Bus ADDRA ADDRB Input The Address Bus selects a memory location for read or write operations. The width (w) of the port’s associated data path determines the number of available address lines (r), as per Table22. Whenever a port is enabled (ENA or ENB = High), address transitions must meet the data sheet setup and hold times with respect to the port clock (CLKA or CLKB), as shown in Table103, page139.This requirement must be met even if the RAM read output is of no interest. Data Input Bus DIA DIB Input Data at the DI input bus is written to the RAM location specified by the address input bus (ADDR) during the active edge of the CLK input, when the clock enable (EN) and write enable (WE) inputs are active. It is possible to configure a port’s DI input bus width (w-p) based on Table22. This selection applies to both the DI and DO paths of a given port. Parity Data Input(s) DIPA DIPB Input Parity inputs represent additional bits included in the data input path. Although referred to herein as “parity” bits, the parity inputs and outputs have no special functionality for generating or checking parity and can be used as additional data bits. The number of parity bits ‘p’ included in the DI (same as for the DO bus) depends on a port’s total data path width (w). See Table22. Data Output Bus DOA DOB Output Data is written to the DO output bus from the RAM location specified by the address input bus, ADDR. See the DI signal description for DO port width configurations. Basic data access occurs on the active edge of the CLK when WE is inactive and EN is active. The DO outputs mirror the data stored in the address ADDR memory location. Data access with WE active if the WRITE_MODE attribute is set to the value: WRITE_FIRST, which accesses data after the write takes place. READ_FIRST accesses data before the write occurs. A third attribute, NO_CHANGE, latches the DO outputs upon the assertion of WE. See Block RAM Data Operations for details on the WRITE_MODE attribute. Parity Data DOPA DOPB Output Parity outputs represent additional bits included in the data input path. The Output(s) number of parity bits ‘p’ included in the DI bus (same as for the DO bus) depends on a port’s total data path width (w). See the DIP signal description for configuration details. Write Enable WEA WEB Input When asserted together with EN, this input enables the writing of data to the RAM. When WE is inactive with EN asserted, read operations are still possible. In this case, a latch passes data from the addressed memory location to the DO outputs. Clock Enable ENA ENB Input When asserted, this input enables the CLK signal to perform read and write operations to the block RAM. When inactive, the block RAM does not perform any read or write operations. Set/Reset SSRA SSRB Input When asserted, this pin forces the DO output latch to the value of the SRVAL attribute. It is synchronized to the CLK signal. Clock CLKA CLKB Input This input accepts the clock signal to which read and write operations are synchronized. All associated port inputs are required to meet setup times with respect to the clock signal’s active edge. The data output bus responds after a clock-to-out delay referenced to the clock signal’s active edge. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 39

Spartan-3E FPGA Family: Functional Description Block RAM Attribute Definitions A block RAM has a number of attributes that control its behavior as shown in Table24. Table 24: Block RAM Attributes Function Attribute Possible Values Initial Content for Data Memory, Loaded during INITxx Each initialization string defines 32 hex values of the Configuration (INIT_00 through INIT3F) 16384-bit data memory of the block RAM. Initial Content for Parity Memory, Loaded INITPxx Each initialization string defines 32 hex values of the during Configuration (INITP_00 through INITP0F) 2048-bit parity data memory of the block RAM. Data Output Latch Initialization INIT (single-port) Hex value the width of the chosen port. INITA, INITB (dual-port) Data Output Latch Synchronous Set/Reset SRVAL (single-port) Hex value the width of the chosen port. Value SRVAL_A, SRVAL_B (dual-port) Data Output Latch Behavior during Write (see WRITE_MODE WRITE_FIRST, READ_FIRST, NO_CHANGE Block RAM Data Operations) Block RAM Data Operations The waveforms for the write operation are shown in the top half of Figure33, Figure34, and Figure35. When the WE Writing data to and accessing data from the block RAM are and EN signals enable the active edge of CLK, data at the synchronous operations that take place independently on DI input bus is written to the block RAM location addressed each of the two ports. Table25 describes the data by the ADDR lines. operations of each port as a result of the block RAM control signals in their default active-High edges. Table 25: Block RAM Function Table Input Signals Output Signals RAM Data GSR EN SSR WE CLK ADDR DIP DI DOP DO Parity Data Immediately After Configuration Loaded During Configuration X X INITP_xx INIT_xx Global Set/Reset Immediately After Configuration 1 X X X X X X X INIT INIT No Chg No Chg RAM Disabled 0 0 X X X X X X No Chg No Chg No Chg No Chg Synchronous Set/Reset 0 1 1 0 ↑ X X X SRVAL SRVAL No Chg No Chg Synchronous Set/Reset During Write RAM 0 1 1 1 ↑ addr pdata Data SRVAL SRVAL RAM(addr) RAM(addr) ← pdata ← data Read RAM, no Write Operation 0 1 0 0 ↑ addr X X RAM(pdata) RAM(data) No Chg No Chg Write RAM, Simultaneous Read Operation 0 1 0 1 ↑ addr pdata Data WRITE_MODE = WRITE_FIRST pdata data RAM(addr) RAM(addr) ← pdata ← data WRITE_MODE = READ_FIRST RAM(data) RAM(data) RAM(addr) RAM(addr) ← pdata ← pdata WRITE_MODE = NO_CHANGE No Chg No Chg RAM(addr) RAM(addr) ← pdata ← pdata DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 40

Spartan-3E FPGA Family: Functional Description There are a number of different conditions under which data portions of Figure33, Figure34, and Figure35 during can be accessed at the DO outputs. Basic data access which WE is Low. always occurs when the WE input is inactive. Under this Data also can be accessed on the DO outputs when condition, data stored in the memory location addressed by asserting the WE input based on the value of the the ADDR lines passes through a output latch to the DO WRITE_MODE attribute as described in Table26. outputs. The timing for basic data access is shown in the Table 26: WRITE_MODE Effect on Data Output Latches During Write Operations Effect on Opposite Port Write Mode Effect on Same Port (dual-port only with same address) WRITE_FIRST Data on DI and DIP inputs is written into specified Invalidates data on DO and DOP outputs. Read After Write RAM location and simultaneously appears on DO and DOP outputs. READ_FIRST Data from specified RAM location appears on DO and Data from specified RAM location appears on DO and Read Before Write DOP outputs. DOP outputs. Data on DI and DIP inputs is written into specified location. NO_CHANGE Data on DO and DOP outputs remains unchanged. Invalidates data on DO and DOP outputs. No Read on Write Data on DI and DIP inputs is written into specified location. X-Ref Target - Figure 33 Internal Data_in DI DO Data_out = Data_in Memory CLK WE DI XXXX 1111 2222 XXXX ADDR aa bb cc dd DO 0000 MEM(aa) 1111 2222 MEM(dd) EN DISABLED READ WRITE WRITE READ MEM(bb)=1111 MEM(cc)=2222 DS312-2_05_020905 Figure 33: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected Setting the WRITE_MODE attribute to a value of WRITE_FIRST, data is written to the addressed memory location on an enabled active CLK edge and is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure33 during which WE is High. Setting the WRITE_MODE attribute to a value of READ_FIRST, data already stored in the addressed location passes to the DO outputs before that location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the portion of Figure34 during which WE is High. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 41

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 34 Internal Data_in DI DO Prior stored data Memory CLK WE DI XXXX 1111 2222 XXXX ADDR aa bb cc dd DO 0000 MEM(aa) old MEM(bb) old MEM(cc) MEM(dd) EN DISABLED READ WRITE WRITE READ MEM(bb)=1111 MEM(cc)=2222 DS312-2_06_020905 Figure 34: Waveforms of Block RAM Data Operations with READ_FIRST Selected X-Ref Target - Figure 35 Internal Data_in DI DO No change during write Memory CLK WE DI XXXX 1111 2222 XXXX ADDR aa bb cc dd DO 0000 MEM(aa) MEM(dd) EN DISABLED READ WRITE WRITE READ MEM(bb)=1111 MEM(cc)=2222 DS312-2_07_020905 Figure 35: Waveforms of Block RAM Data Operations with NO_CHANGE Selected Setting the WRITE_MODE attribute to a value of NO_CHANGE, puts the DO outputs in a latched state when asserting WE. Under this condition, the DO outputs retain the data driven just before WE is asserted. NO_CHANGE timing is shown in the portion of Figure35 during which WE is High. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 42

Spartan-3E FPGA Family: Functional Description Dedicated Multipliers product ranging from –17,179,738,112 to 10 +17,179,869,184 . 10 For additional information, refer to the “Using Embedded Implement multipliers with inputs less than 18 bits by Multipliers” chapter in UG331. sign-extending the inputs (i.e., replicating the The Spartan-3E devices provide 4 to 36 dedicated multiplier most-significant bit). Wider multiplication operations are blocks per device. The multipliers are located together with performed by combining the dedicated multipliers and the block RAM in one or two columns depending on device slice-based logic in any viable combination or by density. See Arrangement of RAM Blocks on Die for details time-sharing a single multiplier. Perform unsigned on the location of these blocks and their connectivity. multiplication by restricting the inputs to the positive range. Tie the most-significant bit Low and represent the unsigned Operation value in the remaining 17 lesser-significant bits. The multiplier blocks primarily perform two’s complement Optional Pipeline Registers numerical multiplication but can also perform some less obvious applications, such as simple data storage and As shown in Figure36, each multiplier block has optional barrel shifting. Logic slices also implement efficient small registers on each of the multiplier inputs and the output. The multipliers and thereby supplement the dedicated registers are named AREG, BREG, and PREG and can be multipliers. The Spartan-3E dedicated multiplier blocks used in any combination. The clock input is common to all have additional features beyond those provided in the registers within a block, but each register has an Spartan-3 FPGAs. independent clock enable and synchronous reset controls making them ideal for storing data samples and coefficients. Each multiplier performs the principle operation P=A×B, When used for pipelining, the registers boost the multiplier where ‘A’ and ‘B’ are 18-bit words in two’s complement clock rate, beneficial for higher performance applications. form, and ‘P’ is the full-precision 36-bit product, also in two’s complement form. The 18-bit inputs represent values Figure36 illustrates the principle features of the multiplier ranging from –131,07210 to +131,07110 with a resulting block. X-Ref Target - Figure 36 AREG (Optional) CEA CE A[17:0] D Q PREG (Optional) RST CEP CE RSTA X D Q P[35:0] BREG (Optional) RST CEB CE B[17:0] D Q RSTP RST RSTB CLK DS312-2_27_021205 Figure 36: Principle Ports and Functions of Dedicated Multiplier Blocks Use the MULT18X18SIO primitive shown in Figure37 to associated register, or to 0 to remove it and make the signal instantiate a multiplier within a design. Although high-level path combinatorial. logic synthesis software usually automatically infers a multiplier, adding the pipeline registers might require the MULT18X18SIO primitive. Connect the appropriate signals to the MULT18X18SIO multiplier ports and set the individual AREG, BREG, and PREG attributes to ‘1’ to insert the DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 43

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 37 Cascading Multipliers MULT18X18SIO The MULT18X18SIO primitive has two additional ports A[17:0] P[35:0] called BCIN and BCOUT to cascade or share the B[17:0] multiplier’s ‘B’ input among several multiplier bocks. The CEA 18-bit BCIN “cascade” input port offers an alternate input CEB source from the more typical ‘B’ input. The B_INPUT CEP attribute specifies whether the specific implementation uses CLK the BCIN or ‘B’ input path. Setting B_INPUT to DIRECT RSTA chooses the ‘B’ input. Setting B_INPUT to CASCADE selects the alternate BCIN input. The BREG register then RSTB optionally holds the selected input value, if required. RSTP BCIN[17:0] BCOUT[17:0] BCOUT is an 18-bit output port that always reflects the value that is applied to the multiplier’s second input, which is DS312-2_28_021205 either the ‘B’ input, the cascaded value from the BCIN input, Figure 37: MULT18X18SIO Primitive or the output of the BREG if it is inserted. Figure38 illustrates the four possible configurations using different settings for the B_INPUT attribute and the BREG attribute. X-Ref Target - Figure 38 BCOUT[17:0] BCOUT[17:0] BREG X X CEB CE D Q CLK BREG = 0 RST B_INPUT = CASCADE BREG = 1 RSTB B_INPUT = CASCADE BCIN[17:0] BCIN[17:0] BCOUT[17:0] BCOUT[17:0] BREG X X CEB CE B[17:0] B[17:0] D Q BREG = 0 CLK B_INPUT = DIRECT RST BREG = 1 RSTB B_INPUT = DIRECT DS312-2_29_021505 Figure 38: Four Configurations of the B Input DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 44

Spartan-3E FPGA Family: Functional Description The BCIN and BCOUT ports have associated dedicated routing that connects adjacent multipliers within the same column. Via the cascade connection, the BCOUT port of one multiplier block drives the BCIN port of the multiplier block directly above it. There is no connection to the BCIN port of the bottom-most multiplier block in a column or a connection from the BCOUT port of the top-most block in a column. As an example, Figure39 shows the multiplier cascade capability within the XC3S100E FPGA, which has a single column of multiplier, four blocks tall. For clarity, the figure omits the register control inputs. X-Ref Target - Figure 39 BCOUT A P B B_INPUT = CASCADE BCIN BCOUT A P B B_INPUT = CASCADE BCIN BCOUT A P B B_INPUT = CASCADE BCIN BCOUT A P B B_INPUT = DIRECT BCIN DS312-2_30_021505 Figure 39: Multiplier Cascade Connection When using the BREG register, the cascade connection forms a shift register structure typically used in DSP algorithms such as direct-form FIR filters. When the BREG register is omitted, the cascade structure essentially feeds the same input value to more than one multiplier. This parallel connection serves to create wide-input multipliers, implement transpose FIR filters, and is used in any application that requires that several multipliers have the same input value. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 45

Spartan-3E FPGA Family: Functional Description Multiplier/Block RAM Interaction The upper 16 bits of the ‘A’ multiplicand input are shared with the upper 16 bits of the block RAM’s Port A Data input. Each multiplier is located adjacent to an 18Kbit block RAM Similarly, the upper 16 bits of the ‘B’ multiplicand input are and shares some interconnect resources. Configuring an shared with Port B’s data input. See also Figure48, 18Kbit block RAM for 36-bit wide data (512x36 mode) page63. prevents use of the associated dedicated multiplier. Table27 defines each port of the MULT18X18SIO primitive. Table 27: MULT18X18SIO Embedded Multiplier Primitives Description Signal Name Direction Function A[17:0] Input The primary 18-bit two’s complement value for multiplication. The block multiplies by this value asynchronously if the optional AREG and PREG registers are omitted. When AREG and/or PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject to the appropriate register controls. B[17:0] Input The second 18-bit two’s complement value for multiplication if the B_INPUT attribute is set to DIRECT. The block multiplies by this value asynchronously if the optional BREG and PREG registers are omitted. When BREG and/or PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject to the appropriate register controls. BCIN[17:0] Input The second 18-bit two’s complement value for multiplication if the B_INPUT attribute is set to CASCADE. The block multiplies by this value asynchronously if the optional BREG and PREG registers are omitted. When BREG and/or PREG are used, the value provided on this port is qualified by the rising edge of CLK, subject to the appropriate register controls. P[35:0] Output The 36-bit two’s complement product resulting from the multiplication of the two input values applied to the multiplier. If the optional AREG, BREG and PREG registers are omitted, the output operates asynchronously. Use of PREG causes this output to respond to the rising edge of CLK with the value qualified by CEP and RSTP. If PREG is omitted, but AREG and BREG are used, this output responds to the rising edge of CLK with the value qualified by CEA, RSTA, CEB, and RSTB. If PREG is omitted and only one of AREG or BREG is used, this output responds to both asynchronous and synchronous events. BCOUT[17:0] Output The value being applied to the second input of the multiplier. When the optional BREG register is omitted, this output responds asynchronously in response to changes at the B[17:0] or BCIN[17:0] ports according to the setting of the B_INPUT attribute. If BREG is used, this output responds to the rising edge of CLK with the value qualified by CEB and RSTB. CEA Input Clock enable qualifier for the optional AREG register. The value provided on the A[17:0] port is captured by AREG in response to a rising edge of CLK when this signal is High, provided that RSTA is Low. RSTA Input Synchronous reset for the optional AREG register. AREG content is forced to the value zero in response to a rising edge of CLK when this signal is High. CEB Input Clock enable qualifier for the optional BREG register. The value provided on the B[17:0] or BCIN[17:0] port is captured by BREG in response to a rising edge of CLK when this signal is High, provided that RSTB is Low. RSTB Input Synchronous reset for the optional BREG register. BREG content is forced to the value zero in response to a rising edge of CLK when this signal is High. CEP Input Clock enable qualifier for the optional PREG register. The value provided on the output of the multiplier port is captured by PREG in response to a rising edge of CLK when this signal is High, provided that RSTP is Low. RSTP Input Synchronous reset for the optional PREG register. PREG content is forced to the value zero in response to a rising edge of CLK when this signal is High. Notes: 1. The control signals CLK, CEA, RSTA, CEB, RSTB, CEP, and RSTP have the option of inverted polarity. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 46

Spartan-3E FPGA Family: Functional Description Digital Clock Managers (DCMs) surrounded by CLBs within the logic array and is no longer located at the top and bottom of a column of block RAM as For additional information, refer to the “Using Digital Clock in the Spartan-3 architecture. The Digital Clock Manager is Managers (DCMs)” chapter in UG331. instantiated within a design using a “DCM” primitive. The DCM supports three major functions: Differences from the Spartan-3 Architecture (cid:129) Clock-skew Elimination: Clock skew within a system (cid:129) Spartan-3E FPGAs have two, four, or eight DCMs, occurs due to the different arrival times of a clock signal depending on device size. at different points on the die, typically caused by the (cid:129) The variable phase shifting feature functions differently clock signal distribution network. Clock skew increases on Spartan-3E FPGAs than from Spartan-3 FPGAs. setup and hold time requirements and increases (cid:129) The Spartan-3E DLLs support lower input frequencies, clock-to-out times, all of which are undesirable in high down to 5MHz. Spartan-3 DLLs support down to frequency applications. The DCM eliminates clock 18MHz. skew by phase-aligning the output clock signal that it generates with the incoming clock signal. This Overview mechanism effectively cancels out the clock distribution delays. Spartan-3E FPGA Digital Clock Managers (DCMs) provide (cid:129) Frequency Synthesis: The DCM can generate a wide flexible, complete control over clock frequency, phase shift range of different output clock frequencies derived from and skew. To accomplish this, the DCM employs a the incoming clock signal. This is accomplished by Delay-Locked Loop (DLL), a fully digital control system that either multiplying and/or dividing the frequency of the uses feedback to maintain clock signal characteristics with a input clock signal by any of several different factors. high degree of precision despite normal variations in (cid:129) Phase Shifting: The DCM provides the ability to shift operating temperature and voltage. This section provides a the phase of all its output clock signals with respect to fundamental description of the DCM. the input clock signal. The XC3S100E FPGA has two DCMs, one at the top and Although a single design primitive, the DCM consists of four one at the bottom of the device. The XC3S250E and interrelated functional units: the Delay-Locked Loop (DLL), XC3S500E FPGAs each include four DCMs, two at the top the Digital Frequency Synthesizer (DFS), the Phase Shifter and two at the bottom. The XC3S1200E and XC3S1600E (PS), and the Status Logic. Each component has its FPGAs contain eight DCMs with two on each edge (see associated signals, as shown in Figure40. also Figure45). The DCM in Spartan-3E FPGAs is X-Ref Target - Figure 40 DCM PSINCDEC Phase PSEN Shifter PSDONE PSCLK Clock CLK0 CLKIN Distribution e CLKFB ut Stage ay Steps put Stag CCCCLLLLKKKK9122807X00 Delay Inp Del Out CLK2X180 CLKDV CLKFX DFS DLL CLKFX180 RST Status 8 LOCKED Logic STATUS [7:0] DS099-2_07_101205 Figure 40: DCM Functional Blocks and Associated Signals DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 47

Spartan-3E FPGA Family: Functional Description Delay-Locked Loop (DLL) The most basic function of the DLL component is to The DLL component has two clock inputs, CLKIN and eliminate clock skew. The main signal path of the DLL CLKFB, as well as seven clock outputs, CLK0, CLK90, consists of an input stage, followed by a series of discrete CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as delay elements or steps, which in turn leads to an output described in Table28. The clock outputs drive stage. This path together with logic for phase detection and simultaneously. Signals that initialize and report the state of control forms a system complete with feedback as shown in the DLL are discussed in Status Logic. Figure41. In Spartan-3E FPGAs, the DLL is implemented using a counter-based delay line. X-Ref Target - Figure 41 CLK0 n CLK90 o cti CLK180 e ut S CLK270 p CLK2X Delay Delay Delay Delay ut CLKIN O CLK2X180 1 2 n-1 n CLKDV Control LOCKED Phase CLKFB Detection RST DS099-2_08_041103 Figure 41: Simplified Functional Diagram of DLL Table 28: DLL Signals Signal Direction Description CLKIN Input Receives the incoming clock signal. See Table30, Table31, and Table32 for optimal external inputs to a DCM. CLKFB Input Accepts either CLK0 or CLK2X as the feedback signal. (Set the CLK_FEEDBACK attribute accordingly). CLK0 Output Generates a clock signal with the same frequency and phase as CLKIN. CLK90 Output Generates a clock signal with the same frequency as CLKIN, phase-shifted by 90°. CLK180 Output Generates a clock signal with the same frequency as CLKIN, phase-shifted by 180°. CLK270 Output Generates a clock signal with the same frequency as CLKIN, phase-shifted by 270°. CLK2X Output Generates a clock signal with the same phase as CLKIN, and twice the frequency. CLK2X180 Output Generates a clock signal with twice the frequency of CLKIN, and phase-shifted 180° with respect to CLK2X. CLKDV Output Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal that is phase-aligned to CLKIN. The clock signal supplied to the CLKIN input serves as a internal or external to the FPGA. After passing through the reference waveform. The DLL seeks to align the rising-edge clock distribution network, the clock signal returns to the of feedback signal at the CLKFB input with the rising-edge DLL via a feedback line called CLKFB. The control block of CLKIN input. When eliminating clock skew, the common inside the DLL measures the phase error between CLKFB approach to using the DLL is as follows: The CLK0 signal is and CLKIN. This phase error is a measure of the clock skew passed through the clock distribution network that feeds all that the clock distribution network introduces. The control the registers it synchronizes. These registers are either block activates the appropriate number of delay steps to DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 48

Spartan-3E FPGA Family: Functional Description cancel out the clock skew. When the DLL phase-aligns the DLL Attributes and Related Functions CLK0 signal with the CLKIN signal, it asserts the LOCKED The DLL unit has a variety of associated attributes as output, indicating a lock on to the CLKIN signal. described in Table29. Each attribute is described in detail in the sections that follow. T able 29: DLL Attributes Attribute Description Values CLK_FEEDBACK Chooses either the CLK0 or CLK2X output to drive NONE, 1X, 2X the CLKFB input CLKIN_DIVIDE_BY_2 Halves the frequency of the CLKIN signal just as it FALSE, TRUE enters the DCM CLKDV_DIVIDE Selects the constant used to divide the CLKIN input 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, frequency to generate the CLKDV output frequency 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16 CLKIN_PERIOD Additional information that allows the DLL to Floating-point value representing the operate with the most efficient lock time and the CLKIN period in nanoseconds best jitter tolerance DLL Clock Input Connections For best results, an external clock source enters the FPGA Design Note via a Global Clock Input (GCLK). Each specific DCM has Avoid using global clock input GCLK1 as it is always shared four possible direct, optimal GCLK inputs that feed the with the M2 mode select pin. Global clock inputs GCLK0, DCM’s CLKIN input, as shown in Table30. Table30 also GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and provides the specific pin numbers by package for each GCLK15 have shared functionality in some configuration GCLK input. The two additional DCM’s on the XC3S1200E modes. and XC3S1600E have similar optimal connections from the left-edge LHCLK and the right-edge RHCLK inputs, as described in Table31 and Table32. (cid:129) The DCM supports differential clock inputs (for example, LVDS, LVPECL_25) via a pair of GCLK inputs that feed an internal single-ended signal to the DCM’s CLKIN input. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 49

Spartan-3E FPGA Family: Functional Description Table 30: Direct Clock Input Connections and Optional External Feedback to Associated DCMs Differential Pair Differential Pair Differential Pair Differential Pair Package N P N P N P N P Pin Number for Single-Ended Input Pin Number for Single-Ended Input VQ100 P91 P90 P89 P88 P86 P85 P84 P83 CP132 B7 A7 C8 B8 A9 B9 C9 A10 TQ144 P131 P130 P129 P128 P126 P125 P123 P122 PQ208 P186 P185 P184 P183 P181 P180 P178 P177 FT256 D8 C8 B8 A8 A9 A10 F9 E9 FG320 D9 C9 B9 B8 A10 B10 E10 D10 FG400 A9 A10 G10 H10 E10 E11 G11 F11 FG484 B11 C11 H11 H12 C12 B12 E12 F12     Associated Global Buffers     GCLK11 GCLK10 GCLK9 GCLK8 0 1 0 1 GCLK7 GCLK6 GCLK5 GCLK4 1 1 1 1 Y Y Y Y 1 1 2 2 Top Left DCM X X X X Top Right DCM _ _ _ _ XC3S100: N/A X X X X XC3S100: DCM_X0Y1 U U U U M M M M XC3S250E, XC3S500E: DCM_X0Y1 XC3S250E, XC3S500E: DCM_X1Y1 G G G G XC3S1200E, XC3S1600E: DCM_X1Y3 F F F F XC3S1200E, XC3S1600E: DCM_X2Y3 U U U U B B B B     H G F E Clock Line (see Table41) D C B A     Bottom Left DCM Y0 Y1 Y0 Y1 Bottom Right DCM 1 1 2 2 XC3S100: N/A X X X X XC3S100: DCM_X0Y0 _ _ _ _ XC3S250E, XC3S500E: DCM_X0Y0 X X X X XC3S250E, XC3S500E: DCM_X1Y0 U U U U XC3S1200E, XC3S1600E: DCM_X1Y0 M M M M XC3S1200E, XC3S1600E: DCM_X2Y0 G G G G F F F F GCLK12 GCLK13 GCLK14 GCLK15 U U U U GCLK0 GCLK1 GCLK2 GCLK3 B B B B     Associated Global Buffers     Differential Pair Differential Pair Differential Pair Differential Pair Package P N P N P N P N Pin Number for Single-Ended Input Pin Number for Single-Ended Input VQ100 P32 P33 P35 P36 P38 P39 P40 P41 CP132 M4 N4 M5 N5 M6 N6 P6 P7 TQ144 P50 P51 P53 P54 P56 P57 P58 P59 PQ208 P74 P75 P77 P78 P80 P81 P82 P83 FT256 M8 L8 N8 P8 T9 R9 P9 N9 FG320 N9 M9 U9 V9 U10 T10 R10 P10 FG400 W9 W10 R10 P10 P11 P12 V10 V11 FG484 V11 U11 R11 T11 R12 P12 Y12 W12 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 50

Spartan-3E FPGA Family: Functional Description Table 31: Direct Clock Input and Optional External Feedback to Left-Edge DCMs (XC3S1200E and XC3S1600E) Diff. Single-Ended Pin Number by Package Type Left Edge Clock VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484 LHCLK DCM/BUFGMUX BUFGMUX_X0Y5  D BUFGMUX_X0Y4  C P P9 F3 P14 P22 H5 J5 K3 M5  LHCLK0 Pair N P10 F2 P15 P23 H6 J4 K2 L5  LHCLK1 DCM_X0Y2 Lines P P11 F1 P16 P24 H3 J1 K7 L8  LHCLK2 ck Pair N P12 G1 P17 P25 H4 J2 L7 M8  LHCLK3 Clo BUFGMUX_X0Y3  B BUFGMUX_X0Y2  A BUFGMUX_X0Y9  H BUFGMUX_X0Y8  G P P15 G3 P20 P28 J2 K3 M1 M1  LHCLK4 Pair N P16 H1 P21 P29 J3 K4 L1 N1  LHCLK5 DCM_X0Y1 Lines P P17 H2 P22 P30 J5 K6 M3 M3  LHCLK6 ck Pair N P18 H3 P23 P31 J4 K5 L3 M4  LHCLK7 Clo BUFGMUX_X0Y7  F BUFGMUX_X0Y6  E Table 32: Direct Clock Input and Optional External Feedback to Right-Edge DCMs (XC3S1200E and XC3S1600E) Right Edge Single-Ended Pin Number by Package Type Diff. DCM/BUFGMUX RHCLK VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484 Clock D  BUFGMUX_X3Y5 C  BUFGMUX_X3Y4 RHCLK7  P68 G13 P94 P135 H11 J14 J20 L19 N Lines DCM_X3Y2 RHCLK6  P67 G14 P93 P134 H12 J15 K20 L18 P Pair ck RHCLK5  P66 H12 P92 P133 H14 J16 K14 L21 N Clo RHCLK4  P65 H13 P91 P132 H15 J17 K13 L20 P Pair B  BUFGMUX_X3Y3 A  BUFGMUX_X3Y2 H  BUFGMUX_X3Y9 G  BUFGMUX_X3Y8 RHCLK3  P63 J14 P88 P129 J13 K14 L14 M16 N Lines DCM_X3Y1 RHCLK2  P62 J13 P87 P128 J14 K15 L15 M15 P Pair ck RHCLK1  P61 J12 P86 P127 J16 K12 L16 M22 N Clo RHCLK0  P60 K14 P85 P126 K16 K13 M16 N22 P Pair F  BUFGMUX_X3Y7 E  BUFGMUX_X3Y6 Every FPGA input provides a possible DCM clock input, but connects directly to the CLKIN input. The internal and the path is not temperature and voltage compensated like external connections are shown in Figure42a and the GCLKs. Alternatively, clock signals within the FPGA Figure42c, respectively. optionally provide a DCM clock input via a Global Clock Multiplexer Buffer (BUFGMUX). The global clock net DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 51

Spartan-3E FPGA Family: Functional Description DLL Clock Output and Feedback Connections Two basic cases determine how to connect the DLL clock outputs and feedback connections: on-chip synchronization As many as four of the nine DCM clock outputs can and off-chip synchronization, which are illustrated in simultaneously drive four of the BUFGMUX buffers on the Figure42a through Figure42d. same die edge. All DCM clock outputs can simultaneously drive general routing resources, including interconnect In the on-chip synchronization case in Figure42a and leading to OBUF buffers. Figure42b, it is possible to connect any of the DLL’s seven output clock signals through general routing resources to The feedback loop is essential for DLL operation. Either the the FPGA’s internal registers. Either a Global Clock Buffer CLK0 or CLK2X outputs feed back to the CLKFB input via a (BUFG) or a BUFGMUX affords access to the global clock BUFGMUX global buffer to eliminate the clock distribution network. As shown in Figure42a, the feedback loop is delay. The specific BUFGMUX buffer used to feed back the created by routing CLK0 (or CLK2X) in Figure42b to a CLK0 or CLK2X signal is ideally one of the BUFGMUX global clock net, which in turn drives the CLKFB input. buffers associated with a specific DCM, as shown in Table30, Table31, and Table32. In the off-chip synchronization case in Figure42c and Figure42d, CLK0 (or CLK2X) plus any of the DLL’s other The feedback path also phase-aligns the other seven DLL output clock signals exit the FPGA using output buffers outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X, (OBUF) to drive an external clock network plus registers on or CLK2X180. The CLK_FEEDBACK attribute value must the board. As shown in Figure42c, the feedback loop is agree with the physical feedback connection. Use “1X” for formed by feeding CLK0 (or CLK2X) in Figure42d back into CLK0 feedback and “2X” for CLK2X feedback. If the DFS the FPGA, then to the DCM’s CLKFB input via a Global unit is used stand-alone, without the DLL, then no feedback Buffer Input, specified in Table30. is required and set the CLK_FEEDBACK attribute to “NONE”. X-Ref Target - Figure 42 FPGA FPGA BUFGMUX BUFGMUX BUFG CLK90 BUFG CLK0 CLK180 CLK90 CLKIN CLK270 CLKIN CLK180 CLKDV CLK270 DCM CLK2X NeCt lDoceklay DCM CLKDV NeCt lDoceklay CLK2X180 CLK2X180 CLKFB CLK0 CLKFB CLK2X BUFGMUX BUFGMUX CLK0 CLK2X (a) On-Chip with CLK0 Feedback (b) On-Chip with CLK2X Feedback FPGA FPGA IBUFG CLK90 OBUF IBUFG CLK0 OBUF CLK180 CLK90 CLKIN CLK270 CLKIN CLK180 CLKDV CLK270 DCM CLK2X NeCt lDoceklay DCM CLKDV NeCt lDoceklay CLK2X180 CLK2X180 CLKFB CLK0 CLKFB CLK2X IBUFG OBUF IBUFG OBUF CLK0 CLK2X (c) Off-Chip with CLK0 Feedback (d) Off-Chip with CLK2X Feedback DS099-2_09_082104 Figure 42: Input Clock, Output Clock, and Feedback Connections for the DLL DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 52

Spartan-3E FPGA Family: Functional Description Accommodating Input Frequencies Beyond Spec- multiple (for multiplication) of the incoming clock frequency. ified Maximums The CLK2X output produces an in-phase signal that is twice the frequency of CLKIN. The CLK2X180 output also If the CLKIN input frequency exceeds the maximum doubles the frequency, but is 180° out-of-phase with respect permitted, divide it down to an acceptable value using the to CLKIN. The CLKDIV output generates a clock frequency CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to that is a predetermined fraction of the CLKIN frequency. “TRUE”, the CLKIN frequency is divided by a factor of two The CLKDV_DIVIDE attribute determines the factor used to as it enters the DCM. In addition, the CLKIN_DIVIDE_BY_2 divide the CLKIN frequency. The attribute can be set to option produces a 50% duty-cycle on the input clock, various values as described in Table29. The basic although at half the CLKIN frequency. frequency synthesis outputs are described in Table28. Quadrant and Half-Period Phase Shift Outputs Duty Cycle Correction of DLL Clock Outputs In addition to CLK0 for zero-phase alignment to the CLKIN The DLL output signals exhibit a 50% duty cycle, even if the signal, the DLL also provides the CLK90, CLK180, and incoming CLKIN signal has a different duty cycle. CLK270 outputs for 90°, 180°, and 270° phase-shifted Fifty-percent duty cycle means that the High and Low times signals, respectively. These signals are described in of each clock cycle are equal. Table28, page48 and their relative timing is shown in Figure43. For control in finer increments than 90°, see DLL Performance Differences Between Steppings Phase Shifter (PS). As indicated in Digital Clock Manager (DCM) Timing X-Ref Target - Figure 43 (Module3), the Stepping 1 revision silicon supports higher Phase: 0o 90o 180o 270o 0o 90o 180o 270o 0o maximum input and output frequencies. Stepping 1 devices are backwards compatible with Stepping 0 devices. Input Signal (40%/60% Duty Cycle) Digital Frequency Synthesizer (DFS) t The DFS unit generates clock signals where the output CLKIN frequency is a product of the CLKIN input clock frequency and a ratio of two user-specified integers. The two dedicated outputs from the DFS unit, CLKFX and Output Signal - Duty Cycle Corrected CLKFX180, are defined in Table33. Table 33: DFS Signals CLK0 Signal Direction Description CLK90 CLKFX Output Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLY/ CLK180 CLKFX_DIVIDE) to generate a clock signal with a new target frequency. CLK270 CLKFX180 Output Generates a clock signal with the same frequency as CLKFX, but shifted 180° out-of-phase. CLK2X The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always CLK2X180 exhibit a 50% duty cycle, even when the CLKIN signal does not. The DFS clock outputs are active coincident with the CLKDV seven DLL outputs and their output phase is controlled by DS099-2_10_101105 the Phase Shifter unit (PS). Figure 43: Characteristics of the DLL Clock Outputs The output frequency (f ) of the DFS is a function of the CLKFX Basic Frequency Synthesis Outputs incoming clock frequency (f ) and two integer CLKIN attributes, as follows. The DLL component provides basic options for frequency multiplication and division in addition to the more flexible f = f •C-----L---K----F----X----_---M-----U-----L---T----I-P----L----Y--- Eq1 CLKFX CLKIN  CLKFX_DIVIDE  synthesis capability of the DFS component, described in a later section. These operations result in output clock signals The CLKFX_MULTIPLY attribute is an integer ranging from with frequencies that are either a fraction (for division) or a 2 to 32, inclusive, and forms the numerator in Equation1. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 53

Spartan-3E FPGA Family: Functional Description The CLKFX_DIVIDE is an integer ranging from 1 to 32, periods, which is equivalent in time to five CLKFX output inclusive and forms the denominator in Equation1. For periods. example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values the frequency of the output clock signal is 5/3 that of the result in faster lock times. Therefore, CLKFX_MULTIPLY input clock signal. These attributes and their acceptable and CLKFX_DIVIDE must be factored to reduce their values ranges are described in Table34. wherever possible. For example, given CLKFX_MULTIPLY T able 34: DFS Attributes = 9 and CLKFX_DIVIDE = 6, removing a factor of three yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2. Attribute Description Values While both value-pairs result in the multiplication of clock CLKFX_MULTIPLY Frequency multiplier Integer from 2 frequency by 3/2, the latter value-pair enables the DLL to constant to 32, inclusive lock more quickly. CLKFX_DIVIDE Frequency divisor Integer from 1 constant to 32, inclusive Phase Shifter (PS) Any combination of integer values can be assigned to the The DCM provides two approaches to controlling the phase CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, of a DCM clock output signal relative to the CLKIN signal: provided that two conditions are met: First, eight of the nine DCM clock outputs – CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKFX, and 1. The two values fall within their corresponding ranges, CLKFX180 – provide either quadrant or half-period phase as specified in Table34. shifting of the input clock. 2. The f output frequency calculated in Equation1 CLKFX Second, the PS unit provides additional fine phase shift falls within the DCM’s operating frequency control of all nine DCM outputs. The PS unit accomplishes specifications (see Table107 in Module3). this by introducing a “fine phase shift” delay (T ) between PS DFS With or Without the DLL the CLKFB and CLKIN signals inside the DLL unit. In FIXED phase shift mode, the fine phase shift is specified at design Although the CLKIN input is shared with both units, the DFS time with a resolution down to 1/ th of a CLKIN cycle or unit functions with or separately from the DLL unit. Separate 256 one delay step (DCM_DELAY_STEP), whichever is greater. from the DLL, the DFS generates an output frequency from This fine phase shift value is relative to the coarser quadrant the CLKIN frequency according to the respective or half-period phase shift of the DCM clock output. When CLKFX_MULTIPLY and CLKFX_DIVIDE values. Frequency used, the PS unit shifts the phase of all nine DCM clock synthesis does not require a feedback loop. Furthermore, output signals. without the DLL, the DFS unit supports a broader operating frequency range. Enabling Phase Shifting and Selecting an Operat- ing Mode With the DLL, the DFS unit operates as described above, only with the additional benefit of eliminating the clock The CLKOUT_PHASE_SHIFT attribute controls the PS unit distribution delay. In this case, a feedback loop from the for the specific DCM instantiation. As described in Table35, CLK0 or CLK2X output to the CLKFB input must be present. this attribute has three possible values: NONE, FIXED, and When operating with the DLL unit, the DFS’s CLKFX and VARIABLE. When CLKOUT_PHASE_SHIFT = NONE, the CLKFX180 outputs are phase-aligned with the CLKIN input PS unit is disabled and the DCM output clocks are every CLKFX_DIVIDE cycles of CLKIN and every phase-aligned to the CLKIN input via the CLKFB feedback CLKFX_MULTIPLY cycles of CLKFX. For example, when path. Figure44a shows this case. CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input The PS unit is enabled when the CLKOUT_PHASE_SHIFT and output clock edges coincide every three CLKIN input attribute is set to FIXED or VARIABLE modes. These two modes are described in the sections that follow. Table 35: PS Attributes Attribute Description Values CLKOUT_PHASE_SHIFT Disables the PS component or chooses between Fixed NONE, FIXED, VARIABLE Phase and Variable Phase modes. PHASE_SHIFT Determines size and direction of initial fine phase shift. Integers from –255 to +255 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 54

Spartan-3E FPGA Family: Functional Description FIXED Phase Shift Mode FIXED Phase Shift prior to ISE 8.1i, Service Pack 3: See Equation3. The value corresponds to a phase shift range of The FIXED phase shift mode shifts the DCM outputs by a –180° to +180° degrees, which is different from the fixed amount (T ), controlled by the user-specified PS Spartan-3 DCM design primitive and simulation model. PHASE_SHIFT attribute. The PHASE_SHIFT value (shown Designs created prior to ISE 8.1i, Service Pack 3 must be as P in Figure44) must be an integer ranging from –255 to recompiled using the most recent ISE development +255. PHASE_SHIFT specifies a phase shift delay as a software. fraction of the T The phase shift behavior is different CLKIN. between ISE 8.1, Service Pack 3 and prior software t = P-----H-----A----S----E-----S----H-----I--F----T-- •T Eq3 PS  512  CLKIN versions, as described below. When the PHASE_SHIFT value is zero, CLKFB and CLKIN Design Note are in phase, the same as when the PS unit is disabled. When the PHASE_SHIFT value is positive, the DCM Prior to ISE 8.1i, Service Pack 3, the FIXED phase shift outputs are shifted later in time with respect to CLKIN input. feature operated differently than the Spartan-3 DCM design When the attribute value is negative, the DCM outputs are primitive and simulation model. Designs using software shifted earlier in time with respect to CLKIN. prior to ISE 8.1i, Service Pack 3 require recompilation using the latest ISE software release. The following Answer Figure44b illustrates the relationship between CLKFB and Record contains additional information: CLKIN in the Fixed Phase mode. In the Fixed Phase mode, the PSEN, PSCLK, and PSINCDEC inputs are not used http://www.xilinx.com/support/answers/23153.htm. and must be tied to GND. FIXED Phase Shift using ISE 8.1i, Service Pack 3 and Equation2 or Equation3 applies only to FIXED phase shift later: See Equation2. The value corresponds to a phase mode. The VARIABLE phase shift mode operates shift range of –360° to +360°, which matches behavior of differently. the Spartan-3 DCM design primitive and simulation model. t = P-----H-----A----S----E-----S----H-----I--F----T-- •T Eq2 PS  256  CLKIN X-Ref Target - Figure 44 a. CLKOUT_PHASE_SHIFT = NONE CLKIN CLKFB (via CLK0 or CLK2X feedback) b. CLKOUT_PHASE_SHIFT = FIXED CLKIN Shift Range over all P Values: –255 0 +255 P 256* TCLKIN CLKFB (via CLK0 or CLK2X feedback) DS312-2_61_021606 Figure 44: NONE and FIXED Phase Shifter Waveforms (ISE 8.1i, Service Pack 3 and later) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 55

Spartan-3E FPGA Family: Functional Description VARIABLE Phase Shift Mode In VARIABLE phase shift mode, the FPGA application inputs to the PS unit (PSEN, PSCLK, and PSINCDEC), as dynamically adjusts the fine phase shift value using three defined in Table36 and shown in Figure40. Table 36: Signals for Variable Phase Mode Signal Direction Description PSEN(1) Input Enables the Phase Shift unit for variable phase adjustment. PSCLK(1) Input Clock to synchronize phase shift adjustment. PSINCDEC(1) Input When High, increments the current phase shift value. When Low, decrements the current phase shift value. This signal is synchronized to the PSCLK signal. PSDONE Output Goes High to indicate that the present phase adjustment is complete and PS unit is ready for next phase adjustment request. This signal is synchronized to the PSCLK signal. Notes: 1. This input supports either a true or inverted polarity. The FPGA application uses the three PS inputs on the phase shift range measured in time and not steps, use Phase Shift unit to dynamically and incrementally increase MAX_STEPS derived in Equation6 and Equation7 for or decrease the phase shift amount on all nine DCM clock VALUE in Equation4 and Equation5. outputs. If CLKIN<60MHz: To adjust the current phase shift value, the PSEN enable MAX_STEPS = ±[INTEGER(10•(T –3))] Eq6 signal must be High to enable the PS unit. Coincidently, CLKIN PSINCDEC must be High to increment the current phase If CLKIN≥60MHz: shift amount or Low to decrement the current amount. All MAX_STEPS = ±[INTEGER(15•(T –3))] Eq7 VARIABLE phase shift operations are controlled by the CLKIN PSCLK input, which can be the CLKIN signal or any other The phase adjustment might require as many as 100 CLKIN clock signal. cycles plus 3 PSCLK cycles to take effect, at which point the DCM’s PSDONE output goes High for one PSCLK cycle. Design Note This pulse indicates that the PS unit completed the previous adjustment and is now ready for the next request. The VARIABLE phase shift feature operates differently from the Spartan-3 DCM; use the DCM_SP primitive, not the Asserting the Reset (RST) input returns the phase shift to DCM primitive. zero. DCM_DELAY_STEP DCM_DELAY_STEP is the finest delay resolution available in the PS unit. Its value is provided at the bottom of Table105 in Module3. For each enabled PSCLK cycle that PSINCDEC is High, the PS unit adds one DCM_ DELAY_STEP of phase shift to all nine DCM outputs. Similarly, for each enabled PSCLK cycle that PSINCDEC is Low, the PS unit subtracts one DCM_ DELAY_STEP of phase shift from all nine DCM outputs. Because each DCM_DELAY_STEP has a minimum and maximum value, the actual phase shift delay for the present phase increment/decrement value (VALUE) falls within the minimum and maximum values according to Equation4 and Equation5. T (Max) = VALUE•DCM_DELAY_STEP_MAX Eq4 PS T (Min) = VALUE•DCM_DELAY_STEP_MIN Eq5 PS The maximum variable phase shift steps, MAX_STEPS, is described in Equation6 or Equation7, for a given CLKIN input period, T , in nanoseconds. To convert this to a CLKIN DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 56

Spartan-3E FPGA Family: Functional Description Status Logic The Status Logic indicates the present state of the DCM frequency. The RST signal must be asserted for three or and a means to reset the DCM to its initial known state. The more CLKIN cycles. A DCM reset does not affect attribute Status Logic signals are described in Table37. values (for example, CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST is tied to GND. In general, the Reset (RST) input is only asserted upon configuring the FPGA or when changing the CLKIN The eight bits of the STATUS bus are described in Table38. Table 37: Status Logic Signals Signal Direction Description RST Input A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of zero. Sets the LOCKED output Low. This input is asynchronous. STATUS[7:0] Output The bit values on the STATUS bus provide information regarding the state of DLL and PS operation LOCKED Output Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are out-of-phase when Low. Table 38: DCM Status Bus Bit Name Description 0 Reserved - 1 CLKIN Stopped When High, indicates that the CLKIN input signal is not toggling. When Low, indicates CLKIN is toggling. This bit functions only when the CLKFB input is connected.(1) 2 CLKFX Stopped When High, indicates that the CLKFX output is not toggling. When Low, indicates the CLKFX output is toggling. This bit functions only when the CLKFX or CLKFX180 output are connected. 3-6 Reserved - Notes: 1. When only the DFS clock outputs but none of the DLL clock outputs are used, this bit does not go High when the CLKIN signal stops. Stabilizing DCM Clocks Before User Mode Spread Spectrum The STARTUP_WAIT attribute shown in Table39 optionally DCMs accept typical spread spectrum clocks as long as delays the end of the FPGA’s configuration process until they meet the input requirements. The DLL will track the after the DCM locks to its incoming clock frequency. This frequency changes created by the spread spectrum clock to option ensures that the FPGA remains in the Startup phase drive the global clocks to the FPGA logic. See XAPP469, of configuration until all clock outputs generated by the Spread-Spectrum Clocking Reception for Displays for DCM are stable. When all DCMs that have their details. STARTUP_WAIT attribute set to TRUE assert the LOCKED signal, then the FPGA completes its configuration process and proceeds to user mode. The associated bitstream generator (BitGen) option LCK_cycle specifies one of the six cycles in the Startup phase. The selected cycle defines the point at which configuration stalls until all the LOCKED outputs go High. See Start-Up, page106 for more information. Table 39: STARTUP_WAIT Attribute Attribute Description Values STARTUP_WAIT When TRUE, delays TRUE, FALSE transition from configuration to user mode until DCM locks to the input clock. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 57

Spartan-3E FPGA Family: Functional Description Clocking Infrastructure High or Low time of either input clock. The two clock inputs can be asynchronous with regard to each other, and the S For additional information, refer to the “Using Global Clock input can change at any time, except for a short setup time Resources” chapter in UG331. prior to the rising edge of the presently selected clock (I0 or I1). This setup time is specified as TGSI in Table101, The Spartan-3E clocking infrastructure, shown in Figure45, page137. Violating this setup time requirement possibly provides a series of low-capacitance, low-skew interconnect results in an undefined runt pulse output. lines well-suited to carrying high-frequency signals throughout the FPGA. The infrastructure also includes the Table 40: BUFGMUX Select Mechanism clock inputs and BUFGMUX clock buffers/multiplexers. The S Input O Output Xilinx Place-and-Route (PAR) software automatically routes high-fanout clock signals using these resources. 0 I0 Input 1 I1 Input Clock Inputs The BUFG clock buffer primitive drives a single clock signal Clock pins accept external clock signals and connect onto the clock network and is essentially the same element directly to DCMs and BUFGMUX elements. Each as a BUFGMUX, just without the clock select mechanism. Spartan-3E FPGA has: Similarly, the BUFGCE primitive creates an enabled clock (cid:129) 16 Global Clock inputs (GCLK0 through GCLK15) buffer using the BUFGMUX select mechanism. located along the top and bottom edges of the FPGA The I0 and I1 inputs to an BUFGMUX element originate (cid:129) 8 Right-Half Clock inputs (RHCLK0 through RHCLK7) from clock input pins, DCMs, or Double-Line interconnect, located along the right edge as shown in Figure46. As shown in Figure45, there are 24 BUFGMUX elements distributed around the four edges of (cid:129) 8 Left-Half Clock inputs (LHCLK0 through LHCLK7) the device. Clock signals from the four BUFGMUX elements located along the left edge at the top edge and the four at the bottom edge are truly Clock inputs optionally connect directly to DCMs using global and connect to all clocking quadrants. The eight dedicated connections. Table30, Table31, and Table32 left-edge BUFGMUX elements only connect to the two clock show the clock inputs that best feed a specific DCM within a quadrants in the left half of the device. Similarly, the eight given Spartan-3E part number. Different Spartan-3E FPGA right-edge BUFGMUX elements only connect to the right densities have different numbers of DCMs. The half of the device. XC3S1200E and XC3S1600E are the only two densities BUFGMUX elements are organized in pairs and share I0 with the left- and right-edge DCMs. and I1 connections with adjacent BUFGMUX elements from Each clock input is also optionally a user-I/O pin and a common clock switch matrix as shown in Figure46. For connects to internal interconnect. Some clock pad pins are example, the input on I0 of one BUFGMUX is also a shared input-only pins as indicated in Module4, Pinout input to I1 of the adjacent BUFGMUX. Descriptions. The clock switch matrix for the left- and right-edge Design Note BUFGMUX elements receive signals from any of the three following sources: an LHCLK or RHCLK pin as appropriate, Avoid using global clock input GCLK1 as it is always shared a Double-Line interconnect, or a DCM in the XC3S1200E with the M2 mode select pin. Global clock inputs GCLK0, and XC3S1600E devices. GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and GCLK15 have shared functionality in some configuration modes. Clock Buffers/Multiplexers Clock Buffers/Multiplexers either drive clock input signals directly onto a clock line (BUFG) or optionally provide a multiplexer to switch between two unrelated, possibly asynchronous clock signals (BUFGMUX). Each BUFGMUX element, shown in Figure46, is a 2-to-1 multiplexer. The select line, S, chooses which of the two inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as described in Table40. The switching from one clock to the other is glitch-less, and done in such a way that the output High and Low times are never shorter than the shortest DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 58

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 45 Global Clock Inputs 4 GCLK11 GCLK10 GCLK9 GCLK8 GCLK7 GCLK6 GCLK5 GCLK44 BUFGMUX DCM DCM pair XXCC33SS255000EE ((XX00YY11)) X1Y10X1Y11 X2Y10X2Y11 XXCC33SS120500EE ((XX01YY11)) inC lQocuka dLrinaent BUFGMUX XC3S1200E (X1Y3) 4 4 XC3S500E (X1Y1) LHCLK7 X0Y9 H Top LeXfCt3S1600E (X1Y3) H G F E XXCC33SS11260000EE ((XX22YY33)) Top Right H X3Y9 RHCLK LHCLK6 X0Y8 G Quadrant (TL) (cid:129)8 4 (cid:129)8 Quadrant (TR) G X3Y8 RHCLK3 2 2 ne 2 2 2 DCM 8 p Spi 8 DCM XC3S1200E (X0Y1) 8 (cid:129) To (cid:129) 8 XC3S1200E (X3Y1) XC3S1600E (X0Y1) XC3S1600E (X3Y1) 2 2 2 2 Clock InputsLHCLK5LHCLK4 X0Y6X0Y7 EF Left Spine 8 No(cid:129)te 3 8 Horizontal Spine 8 No(cid:129)te 4 8 Right Spine EF X3Y7X3Y6 RHCLK0RHCLK1Right-Half C Left-Half LHCLK3LHCLK2 X0Y4X0Y5 CD No(cid:129)te 3 No(cid:129)te 4 CD X3Y5X3Y4 RHCLKRHCLK7lock Inputs 2 8 ne 8 2 6 2 pi 2 DCM 8 (cid:129) m S (cid:129) 8 DCM o XC3S1200E (X0Y2) ott XC3S1200E (X3Y2) XC3S1600E (X0Y2) B XC3S1600E (X3Y2) 2 2 2 (cid:129) (cid:129) 2 LHCLK1 X0Y3 B B X3Y3 RHCLK 5 LK0 Y2 Bottom Left 8 4 8 Bottom Right X3 RH HC X0 A Quadrant (BL) Quadrant (BR) A Y2 CL L K 4 DCM 4 D C B A 4 DCM XC3S250E (X0Y0) XC3S100E (X0Y0) XC3S500E (X0Y0) XC3S250E (X1Y0) XC3S1200E (X1Y0) X1Y0 X1Y1 X2Y0 X2Y1 XC3S500E (X1Y0) XC3S1600E (X1Y0) XC3S1200E (X2Y0) 4 XC3S1600E (X2Y0) 4GCLK3 GCLK2 GCLK1 GCLK0 GCLK15 GCLK14 GCLK13 GCLK12 Global Clock Inputs DS312-2_04_041106 Notes: 1. The diagram presents electrical connectivity. The diagram locations do not necessarily match the physical location on the device, although the coordinate locations shown are correct. 2. Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die. 3. See Figure47a, which shows how the eight clock lines are multiplexed on the left-hand side of the device. 4. See Figure47b, which shows how the eight clock lines are multiplexed on the right-hand side of the device. 5. For best direct clock inputs to a particular clock buffer, not a DCM, see Table41. 6. For best direct clock inputs to a particular DCM, not a BUFGMUX, see Table30, Table31, and Table32. Direct pin inputs to a DCM are shown in gray. Figure 45: Spartan-3E Internal Quadrant-Based Clock Network (Electrical Connectivity View) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 59

Spartan-3E FPGA Family: Functional Description By contrast, the clock switch matrixes on the top and bottom The four BUFGMUX elements on the top edge are paired edges receive signals from any of the five following sources: together and share inputs from the eight global clock inputs two GCLK pins, two DCM outputs, or one Double-Line along the top edge. Each BUFGMUX pair connects to four interconnect. of the eight global clock inputs, as shown in Figure45. This optionally allows differential inputs to the global clock inputs Table41 indicates permissible connections between clock without wasting a BUFGMUX element. inputs and BUFGMUX elements. The I0-input provides the best input path to a clock buffer. The I1-input provides the secondary input for the clock multiplexer function. Table 41: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock Quadran Left-Half BUFGMUX Top or Bottom BUFGMUX Right-Half BUFGMUX t Clock Line(1) Location(2) I0 Input I1 Input Location(2) I0 Input I1 Input Location(2) I0 Input I1 Input GCLK7 or GCLK6 or H X0Y9 LHCLK7 LHCLK6 X1Y10 X3Y9 RHCLK3 RHCLK2 GCLK11 GCLK10 GCLK6 or GCLK7 or G X0Y8 LHCLK6 LHCLK7 X1Y11 X3Y8 RHCLK2 RHCLK3 GCLK10 GCLK11 GCLK5 or GCLK4 or F X0Y7 LHCLK5 LHCLK4 X2Y10 X3Y7 RHCLK1 RHCLK0 GCLK9 GCLK8 GCLK4 or GCLK5 or E X0Y6 LHCLK4 LHCLK5 X2Y11 X3Y6 RHCLK0 RHCLK1 GCLK8 GCLK9 GCLK3 or GCLK2 or D X0Y5 LHCLK3 LHCLK2 X1Y0 X3Y5 RHCLK7 RHCLK6 GCLK15 GCLK14 GCLK2 or GCLK3 or C X0Y4 LHCLK2 LHCLK3 X1Y1 X3Y4 RHCLK6 RHCLK7 GCLK14 GCLK15 GCLK1 or GCLK0 or B X0Y3 LHCLK1 LHCLK0 X2Y0 X3Y3 RHCLK5 RHCLK4 GCLK13 GCLK12 GCLK0 or GCLK1 or A X0Y2 LHCLK0 LHCLK1 X2Y1 X3Y2 RHCLK4 RHCLK5 GCLK12 GCLK13 Notes: 1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks. 2. See Figure45 for specific BUFGMUX locations, and Figure47 for information on how BUFGMUX elements drive onto a specific clock line within a quadrant. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 60

Spartan-3E FPGA Family: Functional Description The connections for the bottom-edge BUFGMUX elements On the left and right edges, only two clock inputs feed each are similar to the top-edge connections (see Figure46). pair of BUFGMUX elements. X-Ref Target - Figure 46 Left-/Right-Half BUFGMUX Top/Bottom (Global) BUFGMUX CLK Switch CLK Switch Matrix Matrix BUFGMUX BUFGMUX S S I0 I0 0 O 0 O I1 I1 1 1 I0 I0 0 O 0 O I1 I1 1 1 S S LHCLK or 1st GCLK pin RHCLK input Double Line 1st DCM output Double Line DCM output* *(XC3S1200E and 2nd DCM output XC3S1600E only) 2nd GCLK pin DS312-2_16_110706 Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity Quadrant Clock Routing Table 42: QFP Package Clock Quadrant Locations The clock routing within the FPGA is quadrant-based, as Clock Pins Quadrant shown in Figure45. Each clock quadrant supports eight GCLK[3:0] BR total clock signals, labeled ‘A’ through ‘H’ in Table41 and GCLK[7:4] TR Figure47. The clock source for an individual clock line originates either from a global BUFGMUX element along GCLK[11:8] TL the top and bottom edges or from a BUFGMUX element GCLK[15:12] BL along the associated edge, as shown in Figure47. The RHCLK[3:0] BR clock lines feed the synchronous resource elements (CLBs, IOBs, block RAM, multipliers, and DCMs) within the RHCLK[7:4] TR quadrant. LHCLK[3:0] TL The four quadrants of the device are: LHCLK[7:4] BL (cid:129) Top Right (TR) In a few cases, a dedicated input is physically in one (cid:129) Bottom Right (BR) quadrant of the device but connects to a different clock quadrant: (cid:129) Bottom Left (BL) (cid:129) Top Left (TL) (cid:129) FT256, H16 is in clock quadrant BR (cid:129) FG320, K2 is in clock quadrant BL Note that the quadrant clock notation (TR, BR, BL, TL) is separate from that used for similar IOB placement (cid:129) FG400, L8 is in clock quadrant TL and the I/O at N11 is constraints. in clock quadrant BL To estimate the quadrant location for a particular I/O, see (cid:129) FG484, M2 is in clock quadrant TL and L15 is in clock the footprint diagrams in Module4, Pinout Descriptions. For quadrant BR exact quadrant locations, use the floorplanning tool. In the QFP packages (VQ100, TQ144 and PQ208) the quadrant borders fall in the middle of each side of the package, at a GND pin. The clock inputs fall on the quadrant boundaries, as indicated in Table42. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 61

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 47 BUFGMUX Output Clock Line BUFGMUX Output Clock Line X1Y10 (Global) X1Y10 (Global) H H X0Y9 (Left Half) X3Y9 (Right Half) X1Y11 (Global) X1Y11 (Global) G G X0Y8 (Left Half) X3Y8 (Right Half) X2Y10 (Global) X2Y10 (Global) F F X0Y7 (Left Half) X3Y7 (Right Half) X2Y11 (Global) X2Y11 (Global) E E X0Y6 (Left Half) X3Y6 (Right Half) X1Y0 (Global) X1Y0 (Global) D D X0Y5 (Left Half) X3Y5 (Right Half) X1Y1 (Global) X1Y1 (Global) C C X0Y4 (Left Half) X3Y4 (Right Half) X2Y0 (Global) X2Y0 (Global) B B X0Y3 (Left Half) X3Y3 (Right Half) X2Y1 (Global) X2Y1 (Global) A A X0Y2 (Left Half) X3Y2 (Right Half) a. Left (TL and BL Quadrants) Half of Die b. Right (TR and BR Quadrants) Half of Die DS312-2_17_103105 Figure 47: Clock Sources for the Eight Clock Lines within a Clock Quadrant The outputs of the top or bottom BUFGMUX elements connect to two vertical spines, each comprising four vertical clock lines as shown in Figure45. At the center of the die, these clock signals connect to the eight-line horizontal clock spine. Outputs of the left and right BUFGMUX elements are routed onto the left or right horizontal spines, each comprising eight horizontal clock lines. Each of the eight clock signals in a clock quadrant derives either from a global clock signal or a half clock signal. In other words, there are up to 24 total potential clock inputs to the FPGA, eight of which can connect to clocked elements in a single clock quadrant. Figure47 shows how the clock lines in each quadrant are selected from associated BUFGMUX sources. For example, if quadrant clock ‘A’ in the bottom left (BL) quadrant originates from BUFGMUX_X2Y1, then the clock signal from BUFGMUX_X0Y2 is unavailable in the bottom left quadrant. However, the top left (TL) quadrant clock ‘A’ can still solely use the output from either BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source. To minimize the dynamic power dissipation of the clock network, the Xilinx development software automatically disables all clock segments not in use. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 62

Spartan-3E FPGA Family: Functional Description Interconnect exploits the rich interconnect array to deliver optimal system performance and the fastest compile times. For additional information, refer to the “Using Interconnect” chapter in UG331. Switch Matrix Interconnect is the programmable network of signal The switch matrix connects to the different kinds of pathways between the inputs and outputs of functional interconnects across the device. An interconnect tile, shown elements within the FPGA, such as IOBs, CLBs, DCMs, and in Figure48, is defined as a single switch matrix connected block RAM. to a functional element, such as a CLB, IOB, or DCM. If a functional element spans across multiple switch matrices Overview such as the block RAM or multipliers, then an interconnect Interconnect, also called routing, is segmented for optimal tile is defined by the number of switch matrices connected connectivity. Functionally, interconnect resources are to that functional element. A Spartan-3E device can be identical to that of the Spartan-3 architecture. There are four represented as an array of interconnect tiles where kinds of interconnects: long lines, hex lines, double lines, interconnect resources are for the channel between any two and direct lines. The Xilinx Place and Route (PAR) software adjacent interconnect tile rows or columns as shown in Figure49. X-Ref Target - Figure 48 Switch Switch Matrix CLB Matrix Switch Matrix Switch 18Kb MULT IOB Matrix Block 18 x 18 Switch RAM Matrix Switch Matrix DCM Switch Matrix DS312_08_100110 Figure 48: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier) X-Ref Target - Figure 49 Switch Switch Switch Switch Switch IOB IOB IOB IOB Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB CLB Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB CLB Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB CLB Matrix Matrix Matrix Matrix Matrix Switch Switch Switch Switch Switch IOB CLB CLB CLB Matrix Matrix Matrix Matrix Matrix DS312_09_100110 Figure 49: Array of Interconnect Tiles in Spartan-3E FPGA DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 63

Spartan-3E FPGA Family: Functional Description Horizontal and Vertical X-Ref Target - Figure 50 Long Lines 24 (horizontal channel shown as an example) CLB (cid:129)(cid:129)(cid:129) CLB CLB (cid:129)(cid:129)(cid:129) CLB CLB (cid:129)(cid:129)(cid:129) CLB CLB (cid:129)(cid:129)(cid:129) CLB CLB (cid:129)(cid:129)(cid:129) CLB 6 6 6 6 6 DS312-2_10_022305 Horizontal and Vertical Hex Lines 8 (horizontal channel shown as an example) CLB CLB CLB CLB CLB CLB CLB DS312-2_11_020905 Horizontal and Vertical Double Lines 8 (horizontal channel shown as an example) CLB CLB CLB DS312-2_15_022305 Direct Connections CLB CLB CLB CLB CLB CLB CLB CLB CLB DS312-2_12_020905 Figure 50: Interconnect Types between Two Adjacent Interconnect Tiles The four types of general-purpose interconnect available in Hex Lines each channel, shown in Figure50, are described below. Each set of eight hex lines are connected to one out of Long Lines every three tiles, both horizontally and vertically. Thirty-two hex lines are available between any given interconnect tile. Each set of 24 long line signals spans the die both Hex lines are only driven from one end of the route. horizontally and vertically and connects to one out of every six interconnect tiles. At any tile, four of the long lines drive Double Lines or receive signals from a switch matrix. Because of their low capacitance, these lines are well-suited for carrying Each set of eight double lines are connected to every other high-frequency signals with minimal loading effects (e.g. tile, both horizontally and vertically. in all four directions. skew). If all global clock lines are already committed and Thirty-two double lines available between any given additional clock signals remain to be assigned, long lines interconnect tile. Double lines are more connections and serve as a good alternative. more flexibility, compared to long line and hex lines. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 64

Spartan-3E FPGA Family: Functional Description Direct Connections Direct connect lines route signals to neighboring tiles: vertically, horizontally, and diagonally. These lines most often drive a signal from a “source” tile to a double, hex, or long line and conversely from the longer interconnect back to a direct line accessing a “destination” tile. Global Controls (STARTUP_SPARTAN3E) In addition to the general-purpose interconnect, Spartan-3E FPGAs have two global logic control signals, as described in Table43. These signals are available to the FPGA application via the STARTUP_SPARTAN3E primitive. Table 43: Spartan-3E Global Logic Control Signals Global Control Description Input Global Set/Reset: When High, asynchronously places all registers and flip-flops in their initial state (see Initialization, GSR page32). Asserted automatically during the FPGA configuration process (see Start-Up, page106). Global Three-State: When High, GTS asynchronously forces all I/O pins to a high-impedance state (Hi-Z, three-state). The Global Set/Reset (GSR) signal replaces the global reset signal included in many ASIC-style designs. Use the GSR control instead of a separate global reset signal in the design to free up CLB inputs, resulting in a smaller, more efficient design. Similarly, the GSR signal is asserted automatically during the FPGA configuration process, guaranteeing that the FPGA starts-up in a known state. The STARTUP_SPARTAN3E primitive also includes two other signals used specifically during configuration. The MBT signals are for Dynamically Loading Multiple Configuration Images Using MultiBoot Option, page92. The CLK input is an alternate clock for configuration Start-Up, page106. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 65

Spartan-3E FPGA Family: Functional Description Configuration merely borrowed and returned to the application as general-purpose user I/Os after configuration completes. For additional information on configuration, refer to UG332: Spartan-3E FPGAs offer several configuration options to Spartan-3 Generation Configuration User Guide. minimize the impact of configuration on the overall system design. In some configuration modes, the FPGA generates Differences from Spartan-3 FPGAs a clock and loads itself from an external memory source, In general, Spartan-3E FPGA configuration modes are a either serially or via a byte-wide data path. Alternatively, an superset to those available in Spartan-3 FPGAs. Two new external host such as a microprocessor downloads the modes added in Spartan-3E FPGAs provide a glueless FPGA’s configuration data using a simple synchronous configuration interface to industry-standard parallel NOR serial interface or via a byte-wide peripheral-style interface. Flash and SPI serial Flash memories. Furthermore, multiple-FPGA designs share a single configuration memory source, creating a structure called a Configuration Process daisy chain. Three FPGA pins—M2, M1, and M0—select the desired The function of a Spartan-3E FPGA is defined by loading configuration mode. The mode pin settings appear in application-specific configuration data into the FPGA’s Table44. The mode pin values are sampled during the start internal, reprogrammable CMOS configuration latches of configuration when the FPGA’s INIT_B output goes High. (CCLs), similar to the way a microprocessor’s function is After the FPGA completes configuration, the mode pins are defined by its application program. For FPGAs, this available as user I/Os. configuration process uses a subset of the device pins, some of which are dedicated to configuration; other pins are Table 44: Spartan-3E Configuration Mode Options and Pin Settings Master SPI BPI Slave Parallel Slave Serial JTAG Serial M[2:0] mode pin <0:0:0> <0:0:1> <0:1:0>=Up <1:1:0> <1:1:1> <1:0:1> settings <0:1:1>=Down Data width Serial Serial Byte-wide Byte-wide Serial Serial Configuration memory Xilinx Industry-standard Industry-standard Any source via Any source via Any source via source Platform SPI serial Flash parallel NOR microcontroller, microcontroller, microcontroller, Flash Flash or Xilinx CPU, Xilinx CPU, Xilinx CPU, System parallel Platform parallel Platform Platform Flash, ACE™ CF, etc. Flash Flash, etc. etc. Clock source Internal Internal oscillator Internal oscillator External clock External clock External clock oscillator on CCLK pin on CCLK pin on TCK pin Total I/O pins borrowed 8 13 46 21 8 0 during configuration Configuration mode for Slave Serial Slave Serial Slave Parallel Slave Parallel or Slave Serial JTAG downstream daisy- Memory chained FPGAs Mapped Stand-alone FPGA Possible using Possible using applications (no XCFxxP XCFxxP ✓ ✓ ✓ external download Platform Flash, Platform Flash, host) which optionally which optionally generates CCLK generates CCLK Uses low-cost, ✓ ✓ industry-standard Flash Supports optional MultiBoot, ✓ multi-configuration mode DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 66

Spartan-3E FPGA Family: Functional Description Configuration Bitstream Image Sizes values applied to the M2, M1, and M0 mode select pins and the HSWAP pin. The mode select pins determine which of A specific Spartan-3E part type always requires a constant the I/O pins are borrowed during configuration and how they number of configuration bits, regardless of design function. In JTAG configuration mode, no user-I/O pins are complexity, as shown in Table45. The configuration file size borrowed for configuration. for a multiple-FPGA daisy-chain design roughly equals the All user-I/O pins, input-only pins, and dual-purpose pins that sum of the individual file sizes. are not actively involved in the currently-select configuration Table 45: Number of Bits to Program a Spartan-3E mode are high impedance (floating, three-stated, Hi-Z) FPGA (Uncompressed Bitstreams) during the configuration process. These pins are indicated in Table46 as gray shaded table entries or cells. Number of Spartan-3E FPGA Configuration Bits The HSWAP input controls whether all user-I/O pins, XC3S100E 581,344 input-only pins, and dual-purpose pins have a pull-up resistor to the supply rail or not. When HSWAP is Low, each XC3S250E 1,353,728 pin has an internal pull-up resistor that is active throughout XC3S500E 2,270,208 configuration. After configuration, pull-up and pull-down XC3S1200E 3,841,184 resistors are available in the FPGA application as described in Pull-Up and Pull-Down Resistors. XC3S1600E 5,969,696 The yellow-shaded table entries or cells represent pins Pin Behavior During Configuration where the pull-up resistor is always enabled during configuration, regardless of the HSWAP input. The For additional information, refer to the “Configuration Pins post-configuration behavior of these pins is defined by and Behavior during Configuration” chapter in UG332. Bitstream Generator options as defined in Table69. Table46 shows how various pins behave during the FPGA configuration process. The actual behavior depends on the Table 46: Pin Behavior during Configuration SPI (Serial BPI (Parallel Pin Name Master Serial JTAG Slave Parallel Slave Serial I/O Bank(3) Flash) NOR Flash) IO* (user-I/O) - IP* (input-only) TDI TDI TDI TDI TDI TDI TDI V CCAUX TMS TMS TMS TMS TMS TMS TMS V CCAUX TCK TCK TCK TCK TCK TCK TCK V CCAUX TDO TDO TDO TDO TDO TDO TDO V CCAUX PROG_B PROG_B PROG_B PROG_B PROG_B PROG_B PROG_B V CCAUX DONE DONE DONE DONE DONE DONE DONE V CCAUX HSWAP HSWAP HSWAP HSWAP HSWAP HSWAP HSWAP 0 M2 0 0 0 1 1 1 2 M1 0 0 1 0 1 1 2 M0 0 1 0 = Up 1 0 1 2 1 = Down CCLK CCLK (I/O) CCLK (I/O) CCLK (I/O) CCLK (I) CCLK (I) 2 INIT_B INIT_B INIT_B INIT_B INIT_B INIT_B 2 CSO_B CSO_B CSO_B CSO_B 2 DOUT/BUSY DOUT DOUT BUSY BUSY DOUT 2 MOSI/CSI_B MOSI CSI_B CSI_B 2 D7 D7 D7 2 D6 D6 D6 2 D5 D5 D5 2 D4 D4 D4 2 D3 D3 D3 2 D2 D2 D2 2 D1 D1 D1 2 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 67

Spartan-3E FPGA Family: Functional Description Table 46: Pin Behavior during Configuration (Cont’d) SPI (Serial BPI (Parallel Pin Name Master Serial JTAG Slave Parallel Slave Serial I/O Bank(3) Flash) NOR Flash) D0/DIN DIN DIN D0 D0 DIN 2 RDWR_B RDWR_B RDWR_B 2 A23 A23 2 A22 A22 2 A21 A21 2 A20 A20 2 A19/VS2 VS2 A19 2 A18/VS1 VS1 A18 2 A17/VS0 VS0 A17 2 A16 A16 1 A15 A15 1 A14 A14 1 A13 A13 1 A12 A12 1 A11 A11 1 A10 A10 1 A9 A9 1 A8 A8 1 A7 A7 1 A6 A6 1 A5 A5 1 A4 A4 1 A3 A3 1 A2 A2 1 A1 A1 1 A0 A0 1 LDC0 LDC0 1 LDC1 LDC1 1 LDC2 LDC2 1 HDC HDC 1 Notes: 1. Gray shaded cells represent pins that are in a high-impedance state (Hi-Z, floating) during configuration. These pins have an optional internal pull-up resistor to their respective V supply pin that is active throughout configuration if the HSWAP input is Low. CCO 2. Yellow shaded cells represent pins with an internal pull-up resistor to its respective voltage supply rail that is active during configuration, regardless of the HSWAP pin. 3. Note that dual-purpose outputs are supplied by V , and configuration inputs are supplied by V . CCO CCAUX The HSWAP pin itself has a pull-up resistor enabled during Table47 shows the default I/O standard setting for the configuration. However, the VCCO_0 supply voltage must various configuration pins during the configuration process. be applied before the pull-up resistor becomes active. If the The configuration interface is designed primarily for 2.5V VCCO_0 supply ramps after the VCCO_2 power supply, do operation when the VCCO_2 (and VCCO_1 in BPI mode) not let HSWAP float; tie HSWAP to the desired logic level connects to 2.5V. externally. Table 47: Default I/O Standard Setting During Config- Spartan-3E FPGAs have only six dedicated configuration uration (VCCO_2 = 2.5V) pins, including the DONE and PROG_B pins, and the four Pin(s) I/O Standard Output Drive Slew Rate JTAG boundary-scan pins: TDI, TDO, TMS, and TCK. All other configuration pins are dual-purpose I/O pins and are All, including CCLK LVCMOS25 8mA Slow available to the FPGA application after the DONE pin goes High. See Start-Up for additional information. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 68

Spartan-3E FPGA Family: Functional Description The configuration pins also operate at other voltages by Design Considerations for the HSWAP, setting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V M[2:0], and VS[2:0] Pins or 1.8V. The change on the V supply also changes the CCO I/O characteristics, including the effective IOSTANDARD. For additional information, refer to the “Configuration Pins For example, with V =3.3V, the output characteristics and Behavior during Configuration” chapter in UG332. CCO will be similar to those of LVCMOS33, and the current when Unlike previous Spartan FPGA families, nearly all of the driving High, I , increases to approximately 12 to 16mA, OH Spartan-3E dual-purpose configuration pins are available while the current when driving Low, I , remains 8mA. At OL as full-featured user I/O pins after successful configuration, V =1.8V, the output characteristics will be similar to CCO when the DONE output goes High. those of LVCMOS18, and the current when driving High, I , decreases slightly to approximately 6 to 8mA. Again, The HSWAP pin, the mode select pins (M[2:0]), and the OH the current when driving Low, I , remains 8mA. The variant-select pins (VS[2:0]) must have valid and stable OL output voltages are determined by the V level, logic values at the start of configuration. VS[2:0] are only CCO LVCMOS18 for 1.8V, LVCMOS25 for 2.5V, and LVCMOS33 used in the SPI configuration mode. The levels on the for 3.3V. For more details see UG332. M[2:0] pins and VS[2:0] pins are sampled when the INIT_B pin returns High. See Figure76 for a timing example. CCLK Design Considerations The HSWAP pin defines whether FPGA user I/O pins have For additional information, refer to the “Configuration Pins a pull-up resistor connected to their associated VCCO and Behavior during Configuration” chapter in UG332. supply pin during configuration or not, as shown Table48. HSWAP must be valid at the start of configuration and The FPGA’s configuration process is controlled by the remain constant throughout the configuration process. CCLK configuration clock. Consequently, signal integrity of CCLK is important to guarantee successful configuration. Table 48: HSWAP Behavior Poor CCLK signal integrity caused by ringing or reflections HSWAP might cause double-clocking, causing the configuration Description Value process to fail. 0 Pull-up resistors connect to the associated V CCO Although the CCLK frequency is relatively low, Spartan-3E supply for all user-I/O or dual-purpose I/O pins FPGA output edge rates are fast. Therefore, careful during configuration. Pull-up resistors are active until configuration completes. attention must be paid to the CCLK signal integrity on the printed circuit board. Signal integrity simulation with IBIS is 1 Pull-up resistors disabled during configuration. All recommended. For all configuration modes except JTAG, user-I/O or dual-purpose I/O pins are in a high-impedance state. the signal integrity must be considered at every CCLK trace destination, including the FPGA’s CCLK pin. The Configuration section provides detailed schematics for This analysis is especially important when the FPGA each configuration mode. The schematics indicate the re-uses the CCLK pin as a user-I/O after configuration. In required logic values for HSWAP, M[2:0], and VS[2:0] but do these cases, there might be unrelated devices attached to not specify how the application provides the logic Low or CCLK, which add additional trace length and signal High value. The HSWAP, M[2:0], and VS[2:0] pins can be destinations. either dedicated or reused by the FPGA application. In the Master Serial, SPI, and BPI configuration modes, the Dedicating the HSWAP, M[2:0], and VS[2:0] Pins FPGA drives the CCLK pin and CCLK should be treated as If the HSWAP, M[2:0], and VS[2:0] pins are not required by a full bidirectional I/O pin for signal integrity analysis. In BPI the FPGA design after configuration, simply connect these mode, CCLK is only used in multi-FPGA daisy-chains. pins directly to the V or GND supply rail shown in the CCO The best signal integrity is ensured by following these basic appropriate configuration schematic. PCB guidelines: Reusing HSWAP, M[2:0], and VS[2:0] After Config- (cid:129) Route the CCLK signal as a 50Ω uration controlled-impedance transmission line. To reuse the HSWAP, M[2:0], and VS[2:0] pin after (cid:129) Route the CCLK signal without any branching. Do not configuration, use pull-up or pull-down resistors to define use a “star” topology. the logic values shown in the appropriate configuration (cid:129) Keep stubs, if required, shorter than 10 mm (0.4 schematic. inches). (cid:129) Terminate the end of the CCLK transmission line. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 69

Spartan-3E FPGA Family: Functional Description Table 49: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0] Required Resistor Value to Define Logic Level on I/O Pull-up Resistors HSWAP, M[2:0], or VS[2:0] HSWAP Value during Configuration High Low 0 Enabled Pulled High via an internal pull-up Pulled Low using an appropriately sized resistor to the associated V pull-down resistor to GND. CCO supply. No external pull-up resistor is For a 2.5V or 3.3V interface: R≤560Ω. For a necessary. 1.8V interface: R≤1.1kΩ. 1 Disabled Pulled High using a 3.3 to 4.7kΩ Pulled Low using a 3.3 to 4.7kΩ resistor to resistor to the associated V GND. CCO supply. The logic level on HSWAP dictates how to define the logic levels on M[2:0] and VS[2:0], as shown in Table49. If the application requires HSWAP to be High, the HSWAP pin is pulled High using an external 3.3kΩ to 4.7kΩ resistor to VCCO_0. If the application requires HSWAP to be Low during configuration, then HSWAP is either connected to GND or pulled Low using an appropriately sized external pull-down resistor to GND. When HSWAP is Low, its pin has an internal pull-up resistor to VCCO_0. The external pull-down resistor must be strong enough to define a logic Low on HSWAP for the I/O standard used during configuration. For 2.5V or 3.3V I/O, the pull-down resistor is 560Ω or lower. For 1.8V I/O, the pull-down resistor is 1.1kΩ or lower. Once HSWAP is defined, use Table49 to define the logic values for M[2:0] and VS[2:0]. Use the weakest external pull-up or pull-down resistor value allowed by the application. The resistor must be strong enough to define a logic Low or High during configuration. However, when driving the HSWAP, M[2:0], or VS[2:0] pins after configuration, the output driver must be strong enough to overcome the pull-up or pull-down resistor value and generate the appropriate logic levels. For example, to overcome a 560Ω pull-down resistor, a 3.3V FPGA I/O pin must use a 6mA or stronger driver. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 70

Spartan-3E FPGA Family: Functional Description Master Serial Mode Flash PROM, as illustrated in Figure51. The FPGA supplies the CCLK output clock from its internal oscillator to For additional information, refer to the “Master Serial Mode” the attached Platform Flash PROM. In response, the chapter in UG332. Platform Flash PROM supplies bit-serial data to the FPGA’s DIN input, and the FPGA accepts this data on each rising In Master Serial mode (M[2:0]=<0:0:0>), the Spartan-3E CCLK edge. FPGA configures itself from an attached Xilinx Platform X-Ref Target - Figure 51 +1.2V V XCFxxS = +3.3V VCCINT XCFxxP = +1.8V P HSWAP VCCO_0 VCCO_0 Ω k 7 VCCO_2 V 4. VCCINT Serial Master DIN D0 VCCO V Mode CCLK CLK ‘0’ M2 DOUT ‘0’ M1 INIT_B OE/RESET +2.5V ‘0’ M0 Platform Flash Spartan-3E Ω Ω XCFxx 0 k FPGA 3 7 3 4. CE CEO CF +2.5V JTAG VCCAUX +2.5V VCCJ +2.5V TDI TDI TDO TDI TDO TMS TMS TMS TCK TCK TCK TDO GND PROG_B DONE GND PROG_B Recommend open-drain driver DS312-2_44_082009 Figure 51: Master Serial Mode using Platform Flash PROM All mode select pins, M[2:0], must be Low when sampled, when the FPGA’s INIT_B output goes High. After configuration, when the FPGA’s DONE output goes High, the mode select pins are available as full-featured user-I/O pins. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 71

Spartan-3E FPGA Family: Functional Description P Similarly, the FPGA’s HSWAP pin must be Low to available as full-featured user-I/O pin and is powered by the enable pull-up resistors on all user-I/O pins during VCCO_0 supply. configuration or High to disable the pull-up resistors. The The FPGA's DOUT pin is used in daisy-chain applications, HSWAP control must remain at a constant logic level described later. In a single-FPGA application, the FPGA’s throughout FPGA configuration. After configuration, when DOUT pin is not used but is actively driving during the the FPGA’s DONE output goes High, the HSWAP pin is configuration process. Table 50: Serial Master Mode Connections FPGA Pin Name Description During Configuration After Configuration Direction HSWAP Input User I/O Pull-Up Control. When Low during Drive at valid logic level User I/O configuration, enables pull-up resistors in all throughout configuration. P I/O pins to respective I/O bank V input. CCO 0: Pull-ups during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA configuration M2=0, M1=0, M0=0. Sampled User I/O mode. See Design Considerations for the when INIT_B goes High. HSWAP, M[2:0], and VS[2:0] Pins. DIN Input Serial Data Input. Receives serial data from PROM’s User I/O D0 output. CCLK Output Configuration Clock. Generated by FPGA Drives PROM’s CLK clock input. User I/O internal oscillator. Frequency controlled by ConfigRate bitstream generator option. If CCLK PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. See CCLK Design Considerations. DOUT Output Serial Data Output. Actively drives. Not used in User I/O single-FPGA designs. In a daisy-chain configuration, this pin connects to DIN input of the next FPGA in the chain. INIT_B Open-drain Initialization Indicator. Active Low. Goes Connects to PROM’s OE/RESET User I/O. If unused in bidirectional Low at start of configuration during input. FPGA clears PROM’s the application, drive I/O Initialization memory clearing process. address counter at start of INIT_B High. Released at end of memory clearing, when configuration, enables outputs mode select pins are sampled. Requires during configuration. PROM also external 4.7 kΩ pull-up resistor to VCCO_2. holds FPGA in Initialization state until PROM reaches Power-On Reset (POR) state. If CRC error detected during configuration, FPGA drives INIT_B Low. DONE Open-drain FPGA Configuration Done. Low during Connects to PROM’s chip-enable Pulled High via external bidirectional configuration. Goes High when FPGA (CE) input. Enables PROM during pull-up. When High, I/O successfully completes configuration. configuration. Disables PROM indicates that the FPGA Requires external 330 Ω pull-up resistor to after configuration. successfully 2.5V. configured. PROG_B Input Program FPGA. Active Low. When asserted Must be High during configuration Drive PROG_B Low Low for 500ns or longer, forces the FPGA to to allow configuration to start. and release to restart its configuration process by clearing Connects to PROM’s CF pin, reprogram FPGA. configuration memory and resetting the allowing JTAG PROM DONE and INIT_B pins once PROG_B programming algorithm to returns High. Recommend external 4.7 kΩ reprogram the FPGA. pull-up resistor to 2.5V. Internal pull-up value may be weaker (see Table78). If driving externally with a 3.3V output, use an open-drain or open-collector driver or use a current limiting series resistor. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 72

Spartan-3E FPGA Family: Functional Description Voltage Compatibility Table 52: Maximum ConfigRate Settings for Platform Flash The PROM’s V supply must be either 3.3V for the CCINT serial XCFxxS Platform Flash PROMs or 1.8V for the Maximum Platform Flash I/O Voltage serial/parallel XCFxxP PROMs. Part Number (VCCO_2, V ) ConfigRate CCO Setting V The FPGA’s VCCO_2 supply input and the Platform XCF01S 3.3V or 2.5V 25 Flash PROM’s V supply input must be the same CCO XCF02S voltage, ideally +2.5V. Both devices also support 1.8V and XCF04S 1.8V 12 3.3V interfaces but the FPGA’s PROG_B and DONE pins XCF08P require special attention as they are powered by the FPGA’s XCF16P 3.3V, 2.5V, or 1.8V 25 V supply, nominally 2.5V. See application note XCF32P CCAUX XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for additional information. Supported Platform Flash PROMs Table51 shows the smallest available Platform Flash PROM to program one Spartan-3E FPGA. A multiple-FPGA daisy-chain application requires a Platform Flash PROM large enough to contain the sum of the various FPGA file sizes. Table 51: Number of Bits to Program a Spartan-3E FPGA and Smallest Platform Flash PROM Spartan-3E Number of Smallest Available FPGA Configuration Bits Platform Flash XC3S100E 581,344 XCF01S XC3S250E 1,353,728 XCF02S XC3S500E 2,270,208 XCF04S XC3S1200E 3,841,184 XCF04S XCF08P XC3S1600E 5,969,696 or 2 x XCF04S The XC3S1600E requires an 8Mbit PROM. Two solutions are possible: either a single 8Mbit XCF08P parallel/serial PROM or two 4Mbit XCF04S serial PROMs cascaded. The two XCF04S PROMs use a 3.3V V supply while the CCINT XCF08P requires a 1.8V V supply. If the board does CCINT not already have a 1.8V supply available, the two cascaded XCF04S PROM solution is recommended. CCLK Frequency In Master Serial mode, the FPGA’s internal oscillator generates the configuration clock frequency. The FPGA provides this clock on its CCLK output pin, driving the PROM’s CLK input pin. The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the configuration process if so specified in the configuration bitstream. The maximum frequency is specified using the ConfigRate bitstream generator option. Table52 shows the maximum ConfigRate settings, approximately equal to MHz, for various Platform Flash devices and I/O voltages. For the serial XCFxxS PROMs, the maximum frequency also depends on the interface voltage. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 73

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 52 CCLK +1.2V +1.2V XCFxxS = +3.3V VCCINT XCFxxP = +1.8V VCCINT P HSWAP VCCO_0 VCCO_0 P HSWAP VCCO_0 VCCO_0 VCCO_2 V VCCINT VCCO_2 V Slave Serial Master DIN D0 VCCO V Serial Mode CCLK CLK Mode ‘0’ M2 DOUT ‘1’ M2 DOUT DOUT ‘0’ M1 INIT_B OE/RESET ‘1’ M1 INIT_B ‘0’ M0 ‘1’ M0 Platform Flash Spartan-3E Spartan-3E XCFxx FPGA FPGA CE CEO CCLK +2.5V CF DIN JTAG VCCAUX +2.5V VCCJ +2.5V VCCAUX +2.5V TDI TDI TDO TDI TDO TDI TDO TMS TMS TMS TMS TCK TCK TCK V TCK +2.5V TDO GND PROG_B DONE PROG_B DONE GND Ω330 Ω4.7k Ω4.7k GND PROG_B PROG_B Recommend open-drain TCK driver TMS DONE INIT_B DS312-2_45_082009 Figure 52: Daisy-Chaining from Master Serial Mode Daisy-Chaining In-System Programming Support If the application requires multiple FPGAs with different Both the FPGA and the Platform Flash PROM are in-system configurations, then configure the FPGAs using a daisy programmable via the JTAG chain. Download support is chain, as shown in Figure52. Use Master Serial mode provided by the Xilinx iMPACT programming software and (M[2:0]=<0:0:0>) for the FPGA connected to the Platform the associated Xilinx Parallel Cable IV or Platform Cable Flash PROM and Slave Serial mode (M[2:0]=<1:1:1>) for USB programming cables. all other FPGAs in the daisy-chain. After the master Storing Additional User Data in Platform Flash FPGA—the FPGA on the left in the diagram—finishes loading its configuration data from the Platform Flash, the After configuration, the FPGA application can continue to master device supplies data using its DOUT output pin to use the Master Serial interface pins to communicate with the next device in the daisy-chain, on the falling CCLK edge. the Platform Flash PROM. If desired, use a larger Platform Flash PROM to hold additional non-volatile application data, JTAG Interface such as MicroBlaze processor code, or other user data such Both the Spartan-3E FPGA and the Platform Flash PROM as serial numbers and Ethernet MAC IDs. The FPGA first have a four-wire IEEE 1149.1/1532 JTAG port. Both devices configures from Platform Flash PROM. Then using FPGA share the TCK clock input and the TMS mode select input. logic after configuration, the FPGA copies MicroBlaze code The devices may connect in either order on the JTAG chain from Platform Flash into external DDR SDRAM for code with the TDO output of one device feeding the TDI input of execution. the following device in the chain. The TDO output of the last See XAPP694: Reading User Data from Configuration device in the JTAG chain drives the JTAG connector. PROMs and XAPP482: MicroBlaze Platform Flash/PROM The JTAG interface on Spartan-3E FPGAs is powered by Boot Loader and User Data Storage for specific details on the 2.5V V supply. Consequently, the PROM’s V how to implement such an interface. CCAUX CCJ supply input must also be 2.5V. To create a 3.3V JTAG interface, please refer to application note XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for additional information. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 74

Spartan-3E FPGA Family: Functional Description SPI Serial Flash Mode In SPI Serial Flash mode (M[2:0]=<0:0:1>), the Spartan-3E FPGA configures itself from an attached industry-standard For additional information, refer to the “Master SPI Mode” SPI serial Flash PROM, as illustrated in Figure53 and chapter in UG332. Figure54. The FPGA supplies the CCLK output clock from its internal oscillator to the clock input of the attached SPI Flash PROM. X-Ref Target - Figure 53 +1.2V +3.3V SPI Serial VCCINT Flash P HSWAP VCCO_0 VCCO_0 7k P I 4. VCCO_2 +3.3V VCC MOSI DATA_IN SPI Mode DIN DATA_OUT ‘0’ M2 CSO_B SELECT ‘0’ M1 W WR_PROTECT ‘1’ M0 ‘1’ HOLD Spartan-3E CLOCK Variant Select FPGA GND ‘1’ VS2 +3.3V S VS1 ‘1’ VS0 CCLK k 7 DOUT 4. INIT_B +2.5V +2.5V JTAG VCCAUX +2.5V TDI TDI TDO TMS TMS TCK TCK 30 7k 3 4. TDO PROG_B DONE GND PROG_B Recommend open-drain driver DS312-2_46_082009 Figure 53: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B) Commands S Although SPI is a standard four-wire interface, various Serial Peripheral Interface (SPI) Configuration Timing in available SPI Flash PROMs use different command Module3. protocols. The FPGA’s variant select pins, VS[2:0], define Figure53 shows the general connection diagram for those how the FPGA communicates with the SPI Flash, including SPI Flash PROMs that support the 0x03 READ command which SPI Flash command the FPGA issues to start the or the 0x0B FAST READ commands. read operation and the number of dummy bytes inserted before the FPGA expects to receive valid data from the SPI Figure54 shows the connection diagram for Atmel Flash. Table53 shows the available SPI Flash PROMs DataFlash serial PROMs, which also use an SPI-based expected to operate with Spartan-3E FPGAs. Other protocol. ‘B’-series DataFlash devices are limited to FPGA compatible devices might work but have not been tested for applications operating over the commercial temperature suitability with Spartan-3E FPGAs. All other VS[2:0] values range. Industrial temperature range applications must use are reserved for future use. Consult the data sheet for the ‘C’- or ‘D’-series DataFlash devices, which have a shorter desired SPI Flash device to determine its suitability. The DataFlash select setup time, because of the faster FPGA basic timing requirements and waveforms are provided in CCLK frequency at cold temperatures. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 75

Spartan-3E FPGA Family: Functional Description Figure57, page83 demonstrates how to configure multiple but the same general technique applies for Atmel FPGAs with different configurations, all stored in a single DataFlash. SPI Flash. The diagram uses standard SPI Flash memories X-Ref Target - Figure 54 +1.2V +3.3V Atmel AT45DB VCCINT DataFlash P HSWAP VCCO_0 VCCO_0 7k P I 4. VCCO_2 +3.3V VCC MOSI SI SPI Mode DIN SO P+3o.w3eVr -(oVnC mCoOn_it2o)r sisu popnllyy irse tqhuei rleads ti fsupply ‘0’ M2 CSO_B CS in power-on sequence, after VCCINT and VCCAUX. Must delay FPGA ‘0’ M1 W WP configuration for > 20 ms after SPI ‘1’ M0 ‘1’ RESET DataFlash reaches its minimum VCC. Spartan-3E RDY/BUSY Force FPGA INIT_B input OR PROG_B Variant Select FPGA SCK icnoplluetc Ltoorw d wrivitehr .an open-drain or open- ‘1’ VS2 +3.3V GND ‘1’ VS1 +3.3V ‘0’ VS0 CCLK k 7 DOUT 4. INIT_B Power-On INIT_B +2.5V Monitor +2.5V JTAG VCCAUX +2.5V TDI TDI TDO TMS TMS TTDCOK TCK 330 4.7k or PROG_B DONE +3.3V GND Power-On PROG_B PROG_B Monitor Recommend open-drain driver DS312-2_50a_082009 Figure 54: Atmel SPI-based DataFlash Configuration Interface DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 76

Spartan-3E FPGA Family: Functional Description Table 53: Variant Select Codes for Various SPI Serial Flash PROMs iMPACT Dummy VS2 VS1 VS0 SPI Read Command SPI Serial Flash Vendor SPI Flash Family Programming Bytes Support M25Pxx STMicroelectronics (ST) Yes M25PExx/M45PExx AT45DB ‘D’-Series Data Yes Atmel Flash AT26 / AT25(1) Intel S33 Spansion (AMD, Fujitsu) S25FLxxxA FAST READ (0x0B) Winbond (NexFlash) NX25 / W25 1 1 1 1 (see Figure53) Macronix MX25Lxxxx Silicon Storage Technology SST25LFxxxA (SST) SST25VFxxxA Programmable Microelectronics Corp. Pm25LVxxx (PMC) AMIC Technology A25L Eon Silicon Solution, Inc. EN25 M25Pxx STMicroelectronics (ST) Yes M25PExx/M45PExx Spansion (AMD, Fujitsu) S25FLxxxA Winbond (NexFlash) NX25 / W25 READ (0x03) Macronix MX25Lxxxx 1 0 1 0 (see Figure53) SST25LFxxxA Silicon Storage Technology SST25VFxxxA (SST) SST25VFxxx Programmable Microelectronics Corp. Pm25LVxxx (PMC) AT45DB DataFlash READ ARRAY (0xE8) (use only ‘C’ or ‘D’ 1 1 0 4 Atmel Corporation Yes (see Figure54) Series for Industrial temperature range) Others Reserved Notes: 1. See iMPACT documentation for specific device support. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 77

Spartan-3E FPGA Family: Functional Description W Table54 shows the connections between the SPI Flash controls are not used by the FPGA during configuration. PROM and the FPGA’s SPI configuration interface. Each However, the HOLD pin must be High during the SPI Flash PROM vendor uses slightly different signal configuration process. The PROM’s write protect input must naming. The SPI Flash PROM’s write protect and hold be High in order to write or program the Flash memory. Table 54: Example SPI Flash PROM Connections and Pin Naming Silicon Atmel SPI Flash Pin FPGA Connection STMicro NexFlash Storage DataFlash Technology DATA_IN MOSI D DI SI SI DATA_OUT DIN Q DO SO SO SELECT CSO_B S CS CE# CS CLOCK CCLK C CLK SCK SCK Not required for FPGA configuration. Must be High WR_PROTECT to program SPI Flash. Optional connection to W WP WP# WP W FPGA user I/O after configuration. Not required for FPGA configuration but must be HOLD High during configuration. Optional connection to HOLD HOLD HOLD# N/A (see Figure53) FPGA user I/O after configuration. Not applicable to Atmel DataFlash. Only applicable to Atmel DataFlash. Not required for FPGA configuration but must be High during RESET configuration. Optional connection to FPGA user N/A N/A N/A RESET (see Figure54) I/O after configuration. Do not connect to FPGA’s PROG_B as this will prevent direct programming of the DataFlash. Only applicable to Atmel DataFlash and only available on certain packages. Not required for RDY/BUSY FPGA configuration. Output from DataFlash N/A N/A N/A RDY/BUSY (see Figure54) PROM. Optional connection to FPGA user I/O after configuration. The mode select pins, M[2:0], and the variant select pins, disable the pull-up resistors. The HSWAP control must VS[2:0] are sampled when the FPGA’s INIT_B output goes remain at a constant logic level throughout FPGA High and must be at defined logic levels during this time. configuration. After configuration, when the FPGA’s DONE After configuration, when the FPGA’s DONE output goes output goes High, the HSWAP pin is available as High, these pins are all available as full-featured user-I/O full-featured user-I/O pin and is powered by the VCCO_0 pins. supply. P In a single-FPGA application, the FPGA’s DOUT pin is not Similarly, the FPGA’s HSWAP pin must be Low to used but is actively driving during the configuration process. enable pull-up resistors on all user-I/O pins or High to Table 55: Serial Peripheral Interface (SPI) Connections FPGA Pin Name Description During Configuration After Configuration Direction HSWAP Input User I/O Pull-Up Control. When Low Drive at valid logic level User I/O during configuration, enables pull-up throughout configuration. P resistors in all I/O pins to respective I/O bank V input. CCO 0: Pull-ups during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA M2=0, M1=0, M0=1. User I/O configuration mode. See Design Sampled when INIT_B goes Considerations for the HSWAP, M[2:0], High. and VS[2:0] Pins. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 78

Spartan-3E FPGA Family: Functional Description Table 55: Serial Peripheral Interface (SPI) Connections (Cont’d) FPGA Pin Name Description During Configuration After Configuration Direction VS[2:0] Input Variant Select. Instructs the FPGA how Must be at the logic levels shown User I/O to communicate with the attached SPI in Table53. Sampled when S Flash PROM. See Design Considerations INIT_B goes High. for the HSWAP, M[2:0], and VS[2:0] Pins. MOSI Output Serial Data Output. FPGA sends SPI Flash memory User I/O read commands and starting address to the PROM’s serial data input. DIN Input Serial Data Input. FPGA receives serial data from User I/O PROM’s serial data output. CSO_B Output Chip Select Output. Active Low. Connects to the SPI Flash Drive CSO_B High after PROM’s chip-select input. If configuration to disable the HSWAP=1, connect this signal SPI Flash and reclaim the to a 4.7 kΩ pull-up resistor to MOSI, DIN, and CCLK pins. 3.3V. Optionally, re-use this pin and MOSI, DIN, and CCLK to continue communicating with SPI Flash. CCLK Output Configuration Clock. Generated by Drives PROM’s clock input. User I/O FPGA internal oscillator. Frequency controlled by ConfigRate bitstream generator option. If CCLK PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. See CCLK Design Considerations. DOUT Output Serial Data Output. Actively drives. Not used in User I/O single-FPGA designs. In a daisy-chain configuration, this pin connects to DIN input of the next FPGA in the chain. INIT_B Open-drain Initialization Indicator. Active Low. Active during configuration. If User I/O. If unused in the bidirectional Goes Low at start of configuration during SPI Flash PROM requires application, drive INIT_B I/O Initialization memory clearing process. >2ms to awake after powering High. Released at end of memory clearing, on, hold INIT_B Low until PROM when mode select pins are sampled. In is ready. If CRC error detected daisy-chain applications, this signal during configuration, FPGA requires an external 4.7 kΩ pull-up drives INIT_B Low. resistor to VCCO_2. DONE Open-drain FPGA Configuration Done. Low during Low indicates that the FPGA is Pulled High via external bidirectional configuration. Goes High when FPGA not yet configured. pull-up. When High, I/O successfully completes configuration. indicates that the FPGA Requires external 330 Ω pull-up resistor successfully configured. to 2.5V. PROG_B Input Program FPGA. Active Low. When Must be High to allow Drive PROG_B Low and asserted Low for 500ns or longer, forces configuration to start. release to reprogram FPGA. the FPGA to restart its configuration Hold PROG_B to force process by clearing configuration FPGA I/O pins into Hi-Z, memory and resetting the DONE and allowing direct programming INIT_B pins once PROG_B returns High. access to SPI Flash PROM Recommend external 4.7 kΩ pull-up pins. resistor to 2.5V. Internal pull-up value may be weaker (see Table78). If driving externally with a 3.3V output, use an open-drain or open-collector driver or use a current limiting series resistor. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 79

Spartan-3E FPGA Family: Functional Description Voltage Compatibility for its three power supplies — V , V , and V CCINT CCAUX CCO to I/O Bank 2 (VCCO_2) — to reach their respective Available SPI Flash PROMs use a single 3.3V supply power-on thresholds before beginning the configuration voltage. All of the FPGA’s SPI Flash interface signals are process. within I/O Bank 2. Consequently, the FPGA’s VCCO_2 supply voltage must also be 3.3V to match the SPI Flash The SPI Flash PROM is powered by the same voltage PROM. supply feeding the FPGA's VCCO_2 voltage input, typically 3.3V. SPI Flash PROMs specify that they cannot be Power-On Precautions if 3.3V Supply is Last in accessed until their V supply reaches its minimum data CC Sequence sheet voltage, followed by an additional delay. For some devices, this additional delay is as little as 10µs as shown in Spartan-3E FPGAs have a built-in power-on reset (POR) Table56. For other vendors, this delay is as much as 20ms. circuit, as shown in Figure66, page103. The FPGA waits Table 56: Example Minimum Power-On to Select Times for Various SPI Flash PROMs SPI Flash PROM Data Sheet Minimum Time from VCC min to Select = Low Vendor Part Number Symbol Value Units STMicroelectronics M25Pxx T 10 μs VSL Spansion S25FLxxxA t 10 ms PU NexFlash NX25xx T 10 μs VSL Macronix MX25Lxxxx t 10 μs VSL Silicon Storage Technology SST25LFxx T 10 μs PU-READ Programmable Microelectronics Pm25LVxxx T 50 μs Corporation VCS Atmel Corporation AT45DBxxxD t 30 μs VCSL AT45DBxxxB 20 ms In many systems, the 3.3V supply feeding the FPGA's supply is last in the sequence, a potential race occurs VCCO_2 input is valid before the FPGA's other V and between the FPGA and the SPI Flash PROM, as shown in CCINT V supplies, and consequently, there is no issue. Figure55. CCAUX However, if the 3.3V supply feeding the FPGA's VCCO_2 X-Ref Target - Figure 55 3.3V Supply SPI Flash cannot be selected SPI Flash PROM SPI Flash available for minimum voltage read operations SPI Flash SPI Flash PROM must PROM CS FPGA VCCO_2 minimum delay(t ) be ready for FPGA Power On Reset Voltage VSL access, otherwise delay FPGA configuration (V ) CCO2T (VCCINT, VCCAUX FPGA initializes configuration FPGA accesses already valid) memory (TPOR) SPI Flash PROM Time DS312-2_50b_110206 Figure 55: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence If the FPGA's V and V supplies are already respective Power On Reset (POR) thresholds, the FPGA CCINT CCAUX valid, then the FPGA waits for VCCO_2 to reach its starts the configuration process and begins initializing its minimum threshold voltage before starting configuration. internal configuration memory. Initialization requires This threshold voltage is labeled as V in Table74 of approximately 1ms (T , minimum in Table111 of CCO2T POR Module3 and ranges from approximately 0.4V to 1.0V, Module3, after which the FPGA de-asserts INIT_B, selects substantially lower than the SPI Flash PROM's minimum the SPI Flash PROM, and starts sending the appropriate voltage. Once all three FPGA supplies reach their read command. The SPI Flash PROM must be ready for DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 80

Spartan-3E FPGA Family: Functional Description read operations at this time. Spartan-3E FPGAs issue the such PROMs support up to ConfigRate=25 and beyond read command just once. If the SPI Flash is not ready, then but require careful data sheet analysis. See Serial the FPGA does not properly configure. Peripheral Interface (SPI) Configuration Timing for more detailed timing analysis. If the 3.3V supply is last in the sequence and does not ramp fast enough, or if the SPI Flash PROM cannot be ready Using the SPI Flash Interface after Configuration when required by the FPGA, delay the FPGA configuration process by holding either the FPGA's PROG_B input or After the FPGA successfully completes configuration, all of INIT_B input Low, as highlighted in Figure54. Release the the pins connected to the SPI Flash PROM are available as FPGA when the SPI Flash PROM is ready. For example, a user-I/O pins. simple R-C delay circuit attached to the INIT_B pin forces If not using the SPI Flash PROM after configuration, drive the FPGA to wait for a preselected amount of time. CSO_B High to disable the PROM. The MOSI, DIN, and Alternately, a Power Good signal from the 3.3V supply or a CCLK pins are then available to the FPGA application. system reset signal accomplishes the same purpose. Use an open-drain or open-collector output when driving Because all the interface pins are user I/O after PROG_B or INIT_B. configuration, the FPGA application can continue to use the SPI Flash interface pins to communicate with the SPI Flash SPI Flash PROM Density Requirements PROM, as shown in Figure56. SPI Flash PROMs offer random-accessible, byte-addressable, read/write, Table57 shows the smallest usable SPI Flash PROM to non-volatile storage to the FPGA application. program a single Spartan-3E FPGA. Commercially available SPI Flash PROMs range in density from 1Mbit to SPI Flash PROMs are available in densities ranging from 128Mbits. A multiple-FPGA daisy-chained application 1Mbit up to 128Mbits. However, a single Spartan-3E requires a SPI Flash PROM large enough to contain the FPGA requires less than 6Mbits. If desired, use a larger sum of the FPGA file sizes. An application can also use a SPI Flash PROM to contain additional non-volatile larger-density SPI Flash PROM to hold additional data application data, such as MicroBlaze processor code, or beyond just FPGA configuration data. For example, the SPI other user data such as serial numbers and Ethernet MAC Flash PROM can also store application code for a IDs. In the example shown in Figure56, the FPGA MicroBlaze™ RISC processor core integrated in the configures from SPI Flash PROM. Then using FPGA logic Spartan-3E FPGA. See Using the SPI Flash Interface after after configuration, the FPGA copies MicroBlaze code from Configuration. SPI Flash into external DDR SDRAM for code execution. Similarly, the FPGA application can store non-volatile Table 57: Number of Bits to Program a Spartan-3E application data within the SPI Flash PROM. FPGA and Smallest SPI Flash PROM The FPGA configuration data is stored starting at location 0. Number of Smallest Usable SPI Device Store any additional data beginning in the next available SPI Configuration Bits Flash PROM Flash PROM sector or page. Do not mix configuration data XC3S100E 581,344 1Mbit and user data in the same sector or page. XC3S250E 1,353,728 2Mbit Similarly, the SPI bus can be expanded to additional SPI XC3S500E 2,270,208 4Mbit peripherals. Because SPI is a common industry-standard interface, various SPI-based peripherals are available, such XC3S1200E 3,841,184 4Mbit as analog-to-digital (A/D) converters, digital-to-analog (D/A) XC3S1600E 5,969,696 8Mbit converters, CAN controllers, and temperature sensors. However, if sufficient I/O pins are available in the CCLK Frequency application, Xilinx recommends creating a separate SPI bus In SPI Flash mode, the FPGA’s internal oscillator generates to control peripherals. Creating a second port reduces the the configuration clock frequency. The FPGA provides this loading on the CCLK and DIN pins, which are crucial for clock on its CCLK output pin, driving the PROM’s clock input configuration. pin. The FPGA starts configuration at its lowest frequency The MOSI, DIN, and CCLK pins are common to all SPI and increases its frequency for the remainder of the peripherals. Connect the select input on each additional SPI configuration process if so specified in the configuration peripheral to one of the FPGA user I/O pins. If HSWAP=0 bitstream. The maximum frequency is specified using the during configuration, the FPGA holds the select line High. If ConfigRate bitstream generator option. The maximum HSWAP=1, connect the select line to +3.3V via an external frequency supported by the FPGA configuration logic 4.7 kΩ pull-up resistor to avoid spurious read or write depends on the timing for the SPI Flash device. Without operations. After configuration, drive the select line Low to examining the timing for a specific SPI Flash PROM, use select the desired SPI peripheral. ConfigRate=12 or lower. SPI Flash PROMs that support the FAST READ command support higher data rates. Some DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 81

Spartan-3E FPGA Family: Functional Description During the configuration process, CCLK is controlled by the other clock signals to drive the CCLK pin and can further FPGA and limited to the frequencies generated by the optimize SPI-based communication. FPGA. After configuration, the FPGA application can use Refer to the individual SPI peripheral data sheet for specific interface and communication protocol requirements. X-Ref Target - Figure 56 Spartan-3E FPGA SPI Serial Flash PROM FFFFF User Data M MOSI DATA_IN A e FPGA-based SDR Blaz SPI Master CCDLIKN DCALTOAC_KOUT MicCrooBdleaze R ro CSO_B SELECT FPGA D c Configuration D Mi +3.3V 0 User I/O k SPI Peripherals 7 4. - A/D Converter DATA_IN - D/A Converter - CAN Controller DATA_OUT - Displays CLOCK - Temperature Sensor SELECT - ASSP To other SPI slave peripherals DS312-2_47_082009 Figure 56: Using the SPI Flash Interface After Configuration DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 82

Spartan-3E FPGA Family: Functional Description Daisy-Chaining If the application requires multiple FPGAs with different diagram—finishes loading its configuration data from the configurations, then configure the FPGAs using a daisy SPI Flash PROM, the master device uses its DOUT output chain, as shown in Figure57. Daisy-chaining from a single pin to supply data to the next device in the daisy-chain, on SPI serial Flash PROM is supported in Stepping 1 devices. the falling CCLK edge. It is not supported in Stepping 0 devices. Use SPI Flash mode (M[2:0]=<0:0:1>) for the FPGA connected to the Design Note Platform Flash PROM and Slave Serial mode SPI mode daisy chains are supported only in Stepping 1 (M[2:0]=<1:1:1>) for all other FPGAs in the daisy-chain. silicon versions. After the master FPGA—the FPGA on the left in the X-Ref Target - Figure 57 SPI-based daisy-chaining is ! only supported in Stepping 1. CCLK +1.2V +3.3V +1.2V SPI Serial P HSWAPVCCINTVCCO_0 VCCO_0 7k P Flash P HSWAPVCCINTVCCO_0 VCCO_0 I 4. VCCO_2 +3.3V VCC VCCO_2 +3.3V Slave MOSI DATA_IN Serial SPI Mode DIN DATA_OUT Mode ‘0’ M2 CSO_B SELECT ‘1’ M2 ‘0’ M1 W WR_PROTECT ‘1’ M1 ‘1’ M0 ‘1’ HOLD ‘1’ M0 Spartan-3E CLOCK Spartan-3E Variant Select FPGA GND FPGA ‘1’ VS2 S VS1 ‘1’ VS0 CCLK CCLK DOUT DIN DOUT DOUT INIT_B INIT_B +2.5V JTAG VCCAUX +2.5V VCCAUX +2.5V TDI TDI TDO TDI TDO TMS TMS TMS TCK TCK TCK +2.5V +3.3V TDO PROG_B DONE PROG_B DONE GND GND 330 4.7k 4.7k PROG_B PROG_B Recommend open-drain TCK driver TMS DONE INIT_B DS312-2_48_082009 Figure 57: Daisy-Chaining from SPI Flash Mode (Stepping 1) Programming Support In-system programming support is available from some third-party PROM programmers using a socket adapter with For successful daisy-chaining, the DONE_cycle attached wires. To gain access to the SPI Flash signals, configuration option must be set to cycle 5 or sooner. The drive the FPGA’s PROG_B input Low with an open-drain default cycle is 4. See Table69 and the Start-Up section for driver. This action places all FPGA I/O pins, including those additional information. attached to the SPI Flash, in high-impedance (Hi-Z). If the I In production applications, the SPI Flash PROM is HSWAP input is Low, the I/Os have pull-up resistors to the usually pre-programmed before it is mounted on the printed V input on their respective I/O bank. The external CCO circuit board. The Xilinx ISE development software programming hardware then has direct access to the SPI produces industry-standard programming files that can be Flash pins. The programming access points are highlighted used with third-party gang programmers. Consult your in the gray box in Figure53, Figure54, and Figure57. specific SPI Flash vendor for recommended production Beginning with the Xilinx ISE 8.2i software release, the programming solutions. iMPACT programming utility provides direct, in-system prototype programming support for STMicro M25P-series DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 83

Spartan-3E FPGA Family: Functional Description SPI serial Flash PROMs and the Atmel AT45DB-series Data Flash PROMs using the Platform Cable USB, Xilinx Parallel IV, or other compatible programming cable. Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode For additional information, refer to the “Master BPI Mode” chapter in UG332. In Byte-wide Peripheral Interface (BPI) mode (M[2:0]=<0:1:0> or <0:1:1>), a Spartan-3E FPGA configures itself from an industry-standard parallel NOR Flash PROM, as illustrated in Figure58. The FPGA generates up to a 24-bit address lines to access an attached parallel Flash. Only 20 address lines are generated for Spartan-3E FPGAs in the TQ144 package. Similarly, the XC3S100E FPGA in the CP132 package only has 20 address lines while the XC3S250E and XC3S500E FPGAs in the same package have 24 address lines. When using the VQ100 package, the BPI mode is not available when using parallel NOR Flash, but is supported using parallel Platform Flash (XCFxxP). The BPI configuration interface is primarily designed for standard parallel NOR Flash PROMs and supports both byte-wide (x8) and byte-wide/halfword (x8/x16) PROMs. The interface functions with halfword-only (x16) PROMs, but the upper byte in a portion of the PROM remains unused. For configuration, the BPI interface does not require any specific Flash PROM features, such as boot block or a specific sector size. The BPI interface also functions with Xilinx parallel Platform Flash PROMs (XCFxxP), although the FPGA’s address lines are left unconnected. The BPI interface also works equally wells with other asynchronous memories that use a similar SRAM-style interface such as SRAM, NVRAM, EEPROM, EPROM, or masked ROM. NAND Flash memory is commonly used in memory cards for digital cameras. Spartan-3E FPGAs do not configure directly from NAND Flash memories. The FPGA’s internal oscillator controls the interface timing and the FPGA supplies the clock on the CCLK output pin. However, the CCLK signal is not used in single FPGA applications. Similarly, the FPGA drives three pins Low during configuration (LDC[2:0]) and one pin High during configuration (HDC) to the PROM’s control inputs. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 84

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 58 +1.2V V VCCINT P HSWAP VCCO_0 VCCO_0 I VCCO_1 V VCCO LDC0 CE# x8 or x8/x16 LDC1 OE# Flash HDC WE# PROM LDC2 BYTE# Not available D in VQ100 A[16:0] package DQ[15:7] BPI Mode VCCO_2 V ‘0’ M2 D[7:0] DQ[7:0] ‘1’ M1 A[23:17] A[n:0] A M0 GND V Spartan-3E BUSY FPGA CCLK k 7 ‘0’ CSI_B CSO_B 4. ‘0’ RDWR_B INIT_B +2.5V +2.5V JTAG VCCAUX +2.5V TDI TDI TDO TMS TMS TCK TCK 0 k 3 7 TDO 3 4. PROG_B DONE GND PROG_B Recommend open-drain driver DS312-2_49_082009 Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs A During configuration, the value of the M0 mode pin determines how the FPGA generates addresses, as shown Table58. When M0=0, the FPGA generates addresses starting at 0 and increments the address on every falling CCLK edge. Conversely, when M0=1, the FPGA generates addresses starting at 0xFF_FFFF (all ones) and decrements the address on every falling CCLK edge. Table 58: BPI Addressing Control M2 M1 M0 Start Address Addressing 0 0 Incrementing 0 1 1 0xFF_FFFF Decrementing DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 85

Spartan-3E FPGA Family: Functional Description This addressing flexibility allows the FPGA to share the full-featured user-I/O pin and is powered by the VCCO_0 parallel Flash PROM with an external or embedded supply. processor. Depending on the specific processor The RDWR_B and CSI_B must be Low throughout the architecture, the processor boots either from the top or configuration process. After configuration, these pins also bottom of memory. The FPGA is flexible and boots from the become user I/O. opposite end of memory from the processor. Only the processor or the FPGA can boot at any given time. The In a single-FPGA application, the FPGA’s CSO_B and FPGA can configure first, holding the processor in reset or CCLK pins are not used but are actively driving during the the processor can boot first, asserting the FPGA’s PROG_B configuration process. The BUSY pin is not used but also pin. actively drives during configuration and is available as a user I/O after configuration. The mode select pins, M[2:0], are sampled when the FPGA’s INIT_B output goes High and must be at defined After configuration, all of the interface pins except DONE logic levels during this time. After configuration, when the and PROG_B are available as user I/Os. Furthermore, the FPGA’s DONE output goes High, the mode pins are bidirectional SelectMAP configuration peripheral interface available as full-featured user-I/O pins. (see Slave Parallel Mode) is available after configuration. To P continue using SelectMAP mode, set the Persist bitstream Similarly, the FPGA’s HSWAP pin must be Low to generator option to Yes. An external host can then read and enable pull-up resistors on all user-I/O pins or High to verify configuration data. disable the pull-up resistors. The HSWAP control must remain at a constant logic level throughout FPGA The Persist option will maintain A20-A23 as configuration configuration. After configuration, when the FPGA’s DONE pins although they are not used in SelectMAP mode. output goes High, the HSWAP pin is available as Table 59: Byte-Wide Peripheral Interface (BPI) Connections Pin Name FPGA Direction Description During Configuration After Configuration HSWAP Input User I/O Pull-Up Control. When Drive at valid logic level throughout User I/O P Low during configuration, enables configuration. pull-up resistors in all I/O pins to respective I/O bank V input. CCO 0: Pull-ups during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA M2=0, M1=1. Set M0=0 to start User I/O configuration mode. See Design at address 0, increment A Considerations for the HSWAP, addresses. Set M0=1 to start at M[2:0], and VS[2:0] Pins. address 0xFFFFFF and decrement addresses. Sampled when INIT_B goes High. CSI_B Input Chip Select Input. Active Low. Must be Low throughout User I/O. If bitstream option configuration. Persist=Yes, becomes part of SelectMap parallel peripheral interface. RDWR_B Input Read/Write Control. Active Low Must be Low throughout User I/O. If bitstream option write enable. Read functionality configuration. Persist=Yes, becomes typically only used after part of SelectMap parallel configuration, if bitstream option peripheral interface. Persist=Yes. LDC0 Output PROM Chip Enable Connect to PROM chip-select User I/O. If the FPGA does input (CE#). FPGA drives this not access the PROM after signal Low throughout configuration, drive this pin configuration. High to deselect the PROM. A[23:0], D[7:0], LDC[2:1], and HDC then become available as user I/O. LDC1 Output PROM Output Enable Connect to the PROM User I/O output-enable input (OE#). The FPGA drives this signal Low throughout configuration. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 86

Spartan-3E FPGA Family: Functional Description Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d) Pin Name FPGA Direction Description During Configuration After Configuration HDC Output PROM Write Enable Connect to PROM write-enable User I/O input (WE#). FPGA drives this signal High throughout configuration. LDC2 Output PROM Byte Mode This signal is not used for x8 User I/O. Drive this pin High PROMs. For PROMs with a x8/x16 after configuration to use a D data width control, connect to x8/x16 PROM in x16 mode. PROM byte-mode input (BYTE#). See Precautions Using x8/x16 Flash PROMs. FPGA drives this signal Low throughout configuration. A[23:0] Output Address Connect to PROM address inputs. User I/O High-order address lines may not be available in all packages and not all may be required. Number of address lines required depends on the size of the attached Flash PROM. FPGA address generation controlled by M0 mode pin. Addresses presented on falling CCLK edge. Only 20 address lines are available in TQ144 package. D[7:0] Input Data Input FPGA receives byte-wide data on User I/O. If bitstream option these pins in response the address Persist=Yes, becomes presented on A[23:0]. Data part of SelectMap parallel captured by FPGA on rising edge peripheral interface. of CCLK. CSO_B Output Chip Select Output. Active Low. Not used in single FPGA User I/O applications. In a daisy-chain configuration, this pin connects to the CSI_B pin of the next FPGA in the chain. If HSWAP=1 in a multi-FPGA daisy-chain application, connect this signal to a 4.7 kΩ pull-up resistor to VCCO_2. Actively drives Low when selecting a downstream device in the chain. BUSY Output Busy Indicator. Typically only used Not used during configuration but User I/O. If bitstream option after configuration, if bitstream actively drives. Persist=Yes, becomes option Persist=Yes. part of SelectMap parallel peripheral interface. CCLK Output Configuration Clock. Generated Not used in single FPGA User I/O. If bitstream option by FPGA internal oscillator. applications but actively drives. In Persist=Yes, becomes Frequency controlled by a daisy-chain configuration, drives part of SelectMap parallel ConfigRate bitstream generator the CCLK inputs of all other peripheral interface. option. If CCLK PCB trace is long or FPGAs in the daisy-chain. has multiple connections, terminate this output to maintain signal integrity. See CCLK Design Considerations. INIT_B Open-drain Initialization Indicator. Active Low. Active during configuration. If CRC User I/O. If unused in the bidirectional I/O Goes Low at start of configuration error detected during application, drive INIT_B during the Initialization memory configuration, FPGA drives INIT_B High. clearing process. Released at the Low. end of memory clearing, when the mode select pins are sampled. In daisy-chain applications, this signal requires an external 4.7 kΩ pull-up resistor to VCCO_2. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 87

Spartan-3E FPGA Family: Functional Description Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d) Pin Name FPGA Direction Description During Configuration After Configuration DONE Open-drain FPGA Configuration Done. Low Low indicates that the FPGA is not Pulled High via external bidirectional I/O during configuration. Goes High yet configured. pull-up. When High, when FPGA successfully completes indicates that the FPGA is configuration. Requires external successfully configured. 330 Ω pull-up resistor to 2.5V. PROG_B Input Program FPGA. Active Low. When Must be High to allow configuration Drive PROG_B Low and asserted Low for 500ns or longer, to start. release to reprogram forces the FPGA to restart its FPGA. Hold PROG_B to configuration process by clearing force FPGA I/O pins into configuration memory and resetting Hi-Z, allowing direct the DONE and INIT_B pins once programming access to PROG_B returns High. Flash PROM pins. Recommend external 4.7 kΩ pull-up resistor to 2.5V. Internal pull-up value may be weaker (see Table78). If driving externally with a 3.3V output, use an open-drain or open-collector driver or use a current limiting series resistor. Voltage Compatibility Power-On Precautions if 3.3V Supply is Last in Sequence for a similar description of the issue for SPI Flash PROMs. V The FPGA’s parallel Flash interface signals are within I/O Banks 1 and 2. The majority of parallel Flash PROMs Supported Parallel NOR Flash PROM Densities use a single 3.3V supply voltage. Consequently, in most Table60 indicates the smallest usable parallel Flash PROM cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages to program a single Spartan-3E FPGA. Parallel Flash must also be 3.3V to match the parallel Flash PROM. There density is specified in bits but addressed as bytes. The are some 1.8V parallel Flash PROMs available and the FPGA presents up to 24 address lines during configuration FPGA interfaces with these devices if the VCCO_1 and but not all are required for single FPGA applications. VCCO_2 supplies are also 1.8V. Table60 shows the minimum required number of address Power-On Precautions if PROM Supply is Last in lines between the FPGA and parallel Flash PROM. The Sequence actual number of address line required depends on the density of the attached parallel Flash PROM. Like SPI Flash PROMs, parallel Flash PROMs typically require some amount of internal initialization time when the A multiple-FPGA daisy-chained application requires a supply voltage reaches its minimum value. parallel Flash PROM large enough to contain the sum of the FPGA file sizes. An application can also use a larger-density The PROM supply voltage also connects to the FPGA’s parallel Flash PROM to hold additional data beyond just VCCO_2 supply input. In many systems, the PROM supply FPGA configuration data. For example, the parallel Flash feeding the FPGA’s VCCO_2 input is valid before the PROM can also contain the application code for a MicroBlaze FPGA’s other V and V supplies, and CCINT CCAUX RISC processor core implemented within the Spartan-3E consequently, there is no issue. However, if the PROM FPGA. After configuration, the MicroBlaze processor can supply is last in the sequence, a potential race occurs execute directly from external Flash or can copy the code to between the FPGA and the parallel Flash PROM. See other, faster system memory before executing the code. Table 60: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM Uncompressed Smallest Usable Minimum Required Spartan-3E FPGA File Sizes (bits) Parallel Flash PROM Address Lines XC3S100E 581,344 1Mbit A[16:0] XC3S250E 1,353,728 2Mbit A[17:0] XC3S500E 2,270,208 4Mbit A[18:0] XC3S1200E 3,841,184 4Mbit A[18:0] XC3S1600E 5,969,696 8Mbit A[19:0] DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 88

Spartan-3E FPGA Family: Functional Description Compatible Flash Families Because all the interface pins are user I/Os after configuration, the FPGA application can continue to use the The Spartan-3E BPI configuration interface operates with a interface pins to communicate with the parallel Flash wide variety of x8 or x8/x16 parallel NOR Flash devices. PROM. Parallel Flash PROMs are available in densities Table61 provides a few Flash memory families that operate ranging from 1Mbit up to 128Mbits and beyond. However, with the Spartan-3E BPI interface. Consult the data sheet a single Spartan-3E FPGA requires less than 6Mbits for for the desired parallel NOR Flash to determine its suitability configuration. If desired, use a larger parallel Flash PROM The basic timing requirements and waveforms are provided to contain additional non-volatile application data, such as in Byte Peripheral Interface (BPI) Configuration Timing MicroBlaze processor code, or other user data, such as (Module3). serial numbers and Ethernet MAC IDs. In such an example, the FPGA configures from parallel Flash PROM. Then using Table 61: Compatible Parallel NOR Flash Families FPGA logic after configuration, a MicroBlaze processor Flash Vendor Flash Memory Family embedded within the FPGA can either execute code directly Numonyx M29W, J3D StrataFlash from parallel Flash PROM or copy the code to external DDR SDRAM and execute from DDR SDRAM. Similarly, the Atmel AT29 / AT49 FPGA application can store non-volatile application data Spansion S29 within the parallel Flash PROM. Macronix MX29 The FPGA configuration data is stored starting at either at location 0 or the top of memory (addresses all ones) or at CCLK Frequency both locations for MultiBoot mode. Store any additional data In BPI mode, the FPGA’s internal oscillator generates the beginning in other available parallel Flash PROM sectors. configuration clock frequency that controls all the interface Do not mix configuration data and user data in the same timing. The FPGA starts configuration at its lowest sector. frequency and increases its frequency for the remainder of Similarly, the parallel Flash PROM interface can be the configuration process if so specified in the configuration expanded to additional parallel peripherals. bitstream. The maximum frequency is specified using the ConfigRate bitstream generator option. The address, data, and LDC1 (OE#) and HDC (WE#) control signals are common to all parallel peripherals. Table 62: Maximum ConfigRate Settings for Parallel Connect the chip-select input on each additional peripheral Flash PROMs (Commercial Temperature Range) to one of the FPGA user I/O pins. If HSWAP=0 during Maximum ConfigRate configuration, the FPGA holds the chip-select line High via Flash Read Access Time Setting an internal pull-up resistor. If HSWAP=1, connect the select line to +3.3V via an external 4.7kΩ pull-up resistor to 250ns 3 avoid spurious read or write operations. After configuration, 115ns 6 drive the select line Low to select the desired peripheral. 45ns 12 Refer to the individual peripheral data sheet for specific interface and communication protocol requirements. Table62 shows the maximum ConfigRate settings for various typical PROM read access times over the The FPGA optionally supports a 16-bit peripheral interface Commercial temperature operating range. See Byte by driving the LDC2 (BYTE#) control pin High after Peripheral Interface (BPI) Configuration Timing (Module3) configuration. See Precautions Using x8/x16 Flash PROMs and UG332 for more detailed information. Despite using for additional information. slower ConfigRate settings, BPI mode is equally fast as the The FPGA provides up to 24 address lines during other configuration modes. In BPI mode, data is accessed configuration, addressing up to 128Mbits (16Mbytes). If at the ConfigRate frequency and internally serialized with using a larger parallel PROM, connect the upper address an 8X clock frequency. lines to FPGA user I/O. During configuration, the upper address lines will be pulled High if HSWAP=0. Otherwise, Using the BPI Interface after Configuration use external pull-up or pull-down resistors on these address After the FPGA successfully completes configuration, all lines to define their values during configuration. pins connected to the parallel Flash PROM are available as Precautions Using x8/x16 Flash PROMs user I/Os. D If not using the parallel Flash PROM after configuration, Most low- to mid-density PROMs are byte-wide (x8) drive LDC0 High to disable the PROM’s chip-select input. only. Many higher-density Flash PROMs support both The remainder of the BPI pins then become available to the byte-wide (x8) and halfword-wide (x16) data paths and FPGA application, including all 24 address lines, the eight include a mode input called BYTE# that switches between data lines, and the LDC2, LDC1, and HDC control pins. x8 or x16. During configuration, Spartan-3E FPGAs only DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 89

Spartan-3E FPGA Family: Functional Description support byte-wide data. However, after configuration, the Other vendors (AMD, Atmel, Silicon Storage Technology, FPGA supports either x8 or x16 modes. In x16 mode, up to some STMicroelectronics devices) use a pin-efficient eight additional user I/O pins are required for the upper data interface but change the function of one pin, called bits, D[15:8]. IO15/A-1, depending if the PROM is in x8 or x16 mode. In x8 mode, BYTE#=0, this pin is the least-significant Connecting a Spartan-3E FPGA to a x8/x16 Flash PROM is address line. The A0 address line selects the halfword simple, but does require a precaution. Various Flash PROM location. The A-1 address line selects the byte location. vendors use slightly different interfaces to support both x8 When in x16 mode, BYTE#=1, the IO15/A-1 pin becomes and x16 modes. Some vendors (Intel, Micron, some the most-significant data bit, D15 because byte addressing STMicroelectronics devices) use a straightforward interface is not required in this mode. Check to see if the Flash with pin naming that matches the FPGA connections. PROM has a pin named “IO15/A-1” or “DQ15/A-1”. If so, be However, the PROM’s A0 pin is wasted in x16 applications careful to connect x8/x16 Flash PROMs correctly, as shown and a separate FPGA user-I/O pin is required for the D15 in Table63. Also, remember that the D[14:8] data data line. Fortunately, the FPGA A0 pin is still available as a connections require FPGA user I/O pins but that the D15 user I/O after configuration, even though it connects to the data is already connected for the FPGA’s A0 pin. Flash PROM. Table 63: FPGA Connections to Flash PROM with IO15/A-1 Pin Connection to Flash PROM with x8 Flash PROM Interface After x16 Flash PROM Interface After FPGA Pin IO15/A-1 Pin FPGA Configuration FPGA Configuration LDC2 BYTE# Drive LDC2 Low or leave Drive LCD2 High unconnected and tie PROM BYTE# input to GND LDC1 OE# Active-Low Flash PROM Active-Low Flash PROM output-enable control output-enable control LDC0 CS# Active-Low Flash PROM chip-select Active-Low Flash PROM chip-select control control HDC WE# Flash PROM write-enable control Flash PROM write-enable control A[23:1] A[n:0] A[n:0] A[n:0] A0 IO15/A-1 IO15/A-1 is the least-significant IO15/A-1 is the most-significant data address input line, IO15 D[7:0] IO[7:0] IO[7:0] IO[7:0] User I/O Upper data lines IO[14:8] not required Upper data lines IO[14:8] not IO[14:8] unless used as x16 Flash interface after required configuration Some x8/x16 Flash PROMs have a long setup time chain between the first and last FPGAs must from either the requirement on the BYTE# signal. For the FPGA to Spartan-3E or Virtex®-5 FPGA families. configure correctly, the PROM must be in x8 mode with After the master FPGA—the FPGA on the left in the BYTE#=0 at power-on or when the FPGA’s PROG_B pin is diagram—finishes loading its configuration data from the pulsed Low. If required, extend the BYTE# setup time for a parallel Flash PROM, the master device continues 3.3V PROM using an external 680 Ω pull-down resistor on generating addresses to the Flash PROM and asserts its the FPGA’s LDC2 pin or by delaying assertion of the CSI_B CSO_B output Low, enabling the next FPGA in the select input to the FPGA. daisy-chain. The next FPGA then receives parallel Daisy-Chaining configuration data from the Flash PROM. The master FPGA’s CCLK output synchronizes data capture. If the application requires multiple FPGAs with different If HSWAP = 1, an external 4.7kΩ pull-up resistor must be configurations, then configure the FPGAs using a daisy added on the CSO_B pin. If HSWAP = 0, no external pull-up chain, as shown in Figure59. Use BPI mode is necessary. (M[2:0]=<0:1:0> or <0:1:1>) for the FPGA connected to the parallel NOR Flash PROM and Slave Parallel mode Design Note (M[2:0]=<1:1:0>) for all downstream FPGAs in the daisy-chain. If there are more than two FPGAs in the chain, BPI mode daisy chain software support is available starting then last FPGA in the chain can be from any Xilinx FPGA in ISE 8.2i. family. However, all intermediate FPGAs located in the http://www.xilinx.com/support/answers/23061.htm DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 90

Spartan-3E FPGA Family: Functional Description Also, in a multi-FPGA daisy-chain configuration of more than two devices, all intermediate FPGAs between the first and last devices must be Spartan-3E or Virtex-5 FPGAs. The last FPGA in the chain can be from any Xilinx FPGA family. BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs Some of the BPI mode configuration pins are shared with global clock inputs along the right and bottom edges of the device (Bank 1 and Bank 2, respectively). These pins are not easily reclaimable for clock inputs after configuration, especially if the FPGA application access the parallel NOR Flash after configuration. Table64 summarizes the shared pins. Table 64: Shared BPI Configuration Mode and Global Buffer Input Pins Device Global Buffer BPI Mode Edge Input Pin Configuration Pin GCLK0 RDWR_B GCLK2 D2 GCLK3 D1 Bottom GCLK12 D7 GCLK13 D6 GCLK14 D4 GCLK15 D3 RHCLK0 A10 RHCLK1 A9 RHCLK2 A8 RHCLK3 A7 Right RHCLK4 A6 RHCLK5 A5 RHCLK6 A4 RHCLK7 A3 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 91

Spartan-3E FPGA Family: Functional Description Stepping 0 Limitations when Reprogramming via configuration file, then subsequent reconfigurations using JTAG if FPGA Set for BPI Configuration the JTAG port will fail. Potential workarounds include setting the mode pins for JTAG configuration (M[2:0] = <1:0:1>) or The FPGA can always be reprogrammed via the JTAG port, offsetting the initial memory location in Flash by 0x2000. regardless of the mode pin (M[2:0]) settings. However, Stepping 0 devices have a minor limitation. If a Stepping 0 Stepping 1 devices fully support JTAG configuration even FPGA is set to configure in BPI mode and the FPGA is when the FPGA mode pins are set for BPI mode. attached to a parallel memory containing a valid FPGA X-Ref Target - Figure 59 CCLK D[7:0] +1.2V V +1.2V VCCINT VCCINT P HSWAP VCCO_0 VCCO_0 I 4.7k P HSWAP VCCO_0 VCCO_0 VCCO_1 V VCC VCCO_1 VCCO_1 LDC0 CE# x8 or LDC1 OE# x8/x16 Flash HDC WE# PROM Not available LDC2 BYTE# in VQ100 A[16:0] D package DQ[15:7] Slave Parallel BPI Mode VCCO_2 V Mode VCCO_2 V ‘0’ M2 D[7:0] DQ[7:0] ‘1’ M2 D[7:0] ‘1’ M1 A[23:17] A[n:0] ‘1’ M1 A M0 GND ‘0’ M0 Spartan-3E Spartan-3E FPGA BUSY FPGA BUSY CCLK CCLK ‘0’ CSI_B CSO_B CSI_B CSO_B CSO_B ‘0’ RDWR_B INIT_B ‘0’ RDWR_B INIT_B 2.5V JTAG VCCAUX +2.5V VCCAUX +2.5V TDI TDI TDO TDI TDO TMS TMS TMS TCK TCK V TCK +2.5V TDO PROG_B DONE PROG_B DONE GND GND 330 4.7k 4.7k PROG_B PROG_B Recommend open-drain TCK driver TMS DONE INIT_B DS312-2_50_082009 Figure 59: Daisy-Chaining from BPI Flash Mode In-System Programming Support parallel Flash pins. The programming access points are highlighted in the gray boxes in Figure58 and Figure59. I In a production application, the parallel Flash PROM is usually preprogrammed before it is mounted on the printed The FPGA itself can also be used as a parallel Flash PROM circuit board. In-system programming support is available programmer during development and test phases. Initially, from third-party boundary-scan tool vendors and from some an FPGA-based programmer is downloaded into the FPGA third-party PROM programmers using a socket adapter with via JTAG. Then the FPGA performs the Flash PROM attached wires. To gain access to the parallel Flash signals, programming algorithms and receives programming data drive the FPGA’s PROG_B input Low with an open-drain from the host via the FPGA’s JTAG interface. See the driver. This action places all FPGA I/O pins, including those Embedded System Tools Reference Manual. attached to the parallel Flash, in high-impedance (Hi-Z). If Dynamically Loading Multiple Configuration the HSWAP input is Low, the I/Os have pull-up resistors to Images Using MultiBoot Option the V input on their respective I/O bank. The external CCO programming hardware then has direct access to the For additional information, refer to the “Reconfiguration and MultiBoot” chapter in UG332. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 92

Spartan-3E FPGA Family: Functional Description After the FPGA configures itself using BPI mode from one Figure60 shows an example usage. At power up, the FPGA end of the parallel Flash PROM, then the FPGA can trigger loads itself from the attached parallel Flash PROM. In this a MultiBoot event and reconfigure itself from the opposite example, the M0 mode pin is Low so the FPGA starts at end of the parallel Flash PROM. MultiBoot is only available address 0 and increments through the Flash PROM when using BPI mode and only for applications with a single memory locations. After the FPGA completes configuration, Spartan-3E FPGA. the application initially loaded into the FPGA performs a board-level or system test using FPGA logic. If the test is By default, MultiBoot mode is disabled. To trigger a successful, the FPGA then triggers a MultiBoot event, MultiBoot event, assert a Low pulse lasting at least 300ns causing the FPGA to reconfigure from the opposite end of on the MultiBoot Trigger (MBT) input to the the Flash PROM memory. This second configuration STARTUP_SPARTAN3E library primitive. When the MBT contains the FPGA application for normal operation. signal returns High after the 300ns or longer pulse, the FPGA automatically reconfigures from the opposite end of Similarly, the general FPGA application could trigger the parallel Flash memory. another MultiBoot event at any time to reload the diagnostics design, and so on. X-Ref Target - Figure 60 Parallel Flash PROM Parallel Flash PROM FFFFFF FFFFFF General General FPGA FPGA Application STARTUP_SPARTAN3E Application GSR User Area GTS User Area MBT > 300 ns CLK Diagnostics Diagnostics FPGA Reconfigure FPGA Application Application 0 0 First Configuration Second Configuration DS312-2_51_103105 Figure 60: Use MultiBoot to Load Alternate Configuration Images In another potential application, the initial design loaded into the FPGA image contains a “golden” or “fail-safe” configuration image, which then communicates with the outside world and checks for a newer image. If there is a new configuration revision and the new image verifies as good, the “golden” configuration triggers a MultiBoot event to load the new image. When a MultiBoot event is triggered, the FPGA then again drives its configuration pins as described in Table59. However, the FPGA does not assert the PROG_B pin. The system design must ensure that no other device drives on these same pins during the reconfiguration process. The FPGA’s DONE, LDC[2:0], or HDC pins can temporarily disable any conflicting drivers during reconfiguration. Asserting the PROG_B pin Low overrides the MultiBoot feature and forces the FPGA to reconfigure starting from the end of memory defined by the mode pins, shown in Table58. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 93

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 61 +1.2V VCCINT P HSWAP VCCO_0 VCCO_0 Slave Parallel Mode VCCO_2 V V ‘1’ M2 Intelligent ‘1’ M1 Download Host V ‘0’ M0 Spartan-3E VCC FPGA D[7:0] D[7:0] Configuration 7 Memory BUSY BUSY 4. Source SELECT CSI_B CSO_B READ/WRITE RDWR_B INIT_B - Internal memory CLOCK CCLK - Disk drive PROG_B - Over network DONE VCCAUX +2.5V - Over RF link INIT_B TDI TDO GND TMS TCK +2.5V - Microcontroller PROG_B DONE - Processor - Tester GND - Computer 330 4.7k PROG_B Recommend open-drain +2.5V driver JTAG TDI TMS TCK TDO DS312-2_52_082009 Figure 61: Slave Parallel Configuration Mode Slave Parallel Mode For additional information, refer to the “Slave Parallel The FPGA captures data on the rising CCLK edge. If the (SelectMAP) Mode” chapter in UG332. CCLK frequency exceeds 50MHz, then the host must also monitor the FPGA’s BUSY output. If the FPGA asserts In Slave Parallel mode (M[2:0]=<1:1:0>), an external host, BUSY High, the host must hold the data for an additional such as a microprocessor or microcontroller, writes clock cycle, until BUSY returns Low. If the CCLK frequency byte-wide configuration data into the FPGA, using a typical is 50MHz or below, the BUSY pin may be ignored but peripheral interface as shown in Figure61. actively drives during configuration. The external download host starts the configuration process The configuration process requires more clock cycles than by pulsing PROG_B and monitoring that the INIT_B pin indicated from the configuration file size. Additional clocks goes High, indicating that the FPGA is ready to receive its are required during the FPGA’s start-up sequence, first data. The host asserts the active-Low chip-select signal especially if the FPGA is programmed to wait for selected (CSI_B) and the active-Low Write signal (RDWR_B). The Digital Clock Managers (DCMs) to lock to their respective host then continues supplying data and clock signals until clock inputs (see Start-Up, page106). either the FPGA’s DONE pin goes High, indicating a successful configuration, or until the FPGA’s INIT_B pin If the Slave Parallel interface is only used to configure the goes Low, indicating a configuration error. FPGA, never to read data back, then the RDWR_B signal DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 94

Spartan-3E FPGA Family: Functional Description can also be eliminated from the interface. However, The Persist option will maintain A20-A23 as configuration RDWR_B must remain Low during configuration. pins although they are not used in SelectMAP mode. After configuration, all of the interface pins except DONE The Slave Parallel mode is also used with BPI mode to and PROG_B are available as user I/Os. Alternatively, the create multi-FPGA daisy-chains. The lead FPGA is set for bidirectional SelectMAP configuration interface is available BPI mode configuration; all the downstream daisy-chain after configuration. To continue using SelectMAP mode, set FPGAs are set for Slave Parallel configuration, as the Persist bitstream generator option to Yes. The external highlighted in Figure59. host can then read and verify configuration data. Table 65: Slave Parallel Mode Connections Pin Name FPGA Direction Description During Configuration After Configuration HSWAP Input User I/O Pull-Up Control. When Drive at valid logic level User I/O Low during configuration, enables throughout configuration. pull-up resistors in all I/O pins to respective I/O bank V input. CCO 0: Pull-ups during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA M2=1, M1=1, M0=0 Sampled User I/O configuration mode. See Design when INIT_B goes High. Considerations for the HSWAP, M[2:0], and VS[2:0] Pins. D[7:0] Input Data Input. Byte-wide data provided by host. User I/O. If bitstream FPGA captures data on rising option Persist=Yes, CCLK edge. becomes part of SelectMap parallel peripheral interface. BUSY Output Busy Indicator. If CCLK frequency is < 50MHz, User I/O. If bitstream this pin may be ignored. When option Persist=Yes, High, indicates that the FPGA is becomes part of not ready to receive additional SelectMap parallel configuration data. Host must hold peripheral interface. data an additional clock cycle. CSI_B Input Chip Select Input. Active Low. Must be Low throughout User I/O. If bitstream configuration. option Persist=Yes, becomes part of SelectMap parallel peripheral interface. RDWR_B Input Read/Write Control. Active Low Must be Low throughout User I/O. If bitstream write enable. configuration. option Persist=Yes, becomes part of SelectMap parallel peripheral interface. CCLK Input Configuration Clock. If CCLK PCB External clock. User I/O If bitstream option trace is long or has multiple Persist=Yes, becomes connections, terminate this output to part of SelectMap parallel maintain signal integrity. See CCLK peripheral interface. Design Considerations. CSO_B Output Chip Select Output. Active Low. Not used in single FPGA User I/O applications. In a daisy-chain configuration, this pin connects to the CSI_B pin of the next FPGA in the chain. Actively drives. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 95

Spartan-3E FPGA Family: Functional Description Table 65: Slave Parallel Mode Connections (Cont’d) Pin Name FPGA Direction Description During Configuration After Configuration INIT_B Open-drain Initialization Indicator. Active Low. Active during configuration. If User I/O. If unused in the bidirectional I/O Goes Low at the start of CRC error detected during application, drive INIT_B configuration during the Initialization configuration, FPGA drives High. memory clearing process. Released INIT_B Low. at the end of memory clearing, when mode select pins are sampled. In daisy-chain applications, this signal requires an external 4.7 kΩ pull-up resistor to VCCO_2. DONE Open-drain FPGA Configuration Done. Low Low indicates that the FPGA is not Pulled High via external bidirectional I/O during configuration. Goes High yet configured. pull-up. When High, when FPGA successfully completes indicates that the FPGA configuration. Requires external 330 successfully configured. Ω pull-up resistor to 2.5V. PROG_B Input Program FPGA. Active Low. When Must be High to allow Drive PROG_B Low and asserted Low for 500ns or longer, configuration to start. release to reprogram forces the FPGA to restart its FPGA. configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. Recommend external 4.7 kΩ pull-up resistor to 2.5V. Internal pull-up value may be weaker (see Table78). If driving externally with a 3.3V output, use an open-drain or open-collector driver or use a current limiting series resistor. Voltage Compatibility V Most Slave Parallel interface signals are within the FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input. The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match the requirements of the external host, ideally 2.5V. Using 1.8V or 3.3V requires additional design considerations as the DONE and PROG_B pins are powered by the FPGA’s 2.5V V supply. See XAPP453: The 3.3V CCAUX Configuration of Spartan-3 FPGAs for additional information. Daisy-Chaining If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain. Use Slave Parallel mode (M[2:0]=<1:1:0>) for all FPGAs in the daisy-chain. The schematic in Figure62 is optimized for FPGA downloading and does not support the SelectMAP read interface. The FPGA’s RDWR_B pin must be Low during configuration. After the lead FPGA is filled with its configuration data, the lead FPGA enables the next FPGA in the daisy-chain by asserting is chip-select output, CSO_B. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 96

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 62 D[7:0] CCLK +1.2V +1.2V VCCINT VCCINT P HSWAP VCCO_0 VCCO_0 P HSWAP VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 LDC0 LDC0 LDC1 LDC1 HDC HDC Slave LDC2 Slave LDC2 Parallel Parallel Mode VCCO_2 V Mode VCCO_2 V V ‘1’ M2 ‘1’ M2 Intelligent Download Host ‘1’ M1 ‘1’ M1 V ‘0’ M0 Spartan-3E ‘0’ M0 Spartan-3E VCC FPGA Ω FPGA Configuration DATA[7:0] D[7:0] 7k D[7:0] Memory BUSY BUSY 4. BUSY Source SELECT CSI_B CSO_B CSI_B CSO_B CSO_B READ/WRITE ‘0’ RDWR_B INIT_B ‘0’ RDWR_B INIT_B •• IDnitsekr ndarilv meemory CLOCK CCLK CCLK • PROG_B •Over network Over RF link DONE VCCAUX +2.5V VCCAUX +2.5V INIT_B TDI TDO TDI TDO GND TMS TMS TCK TCK +2.5V ••MPriocrcoecsosnotrroller PROG_B DONE PROG_B DONE •Tester GND Ω Ω GND 0 k 3 7 3 4. PROG_B PROG_B Recommend open-drain 2.5V DONE driver JTAG INIT_B TDI TMS TMS TCK TCK TDO DS312-2_53_082009 Figure 62: Daisy-Chaining using Slave Parallel Mode Slave Serial Mode For additional information, refer to the “Slave Serial Mode” The intelligent host starts the configuration process by chapter in UG332. pulsing PROG_B and monitoring that the INIT_B pin goes High, indicating that the FPGA is ready to receive its first In Slave Serial mode (M[2:0]=<1:1:1>), an external host data. The host then continues supplying data and clock such as a microprocessor or microcontroller writes serial signals until either the DONE pin goes High, indicating a configuration data into the FPGA, using the synchronous successful configuration, or until the INIT_B pin goes Low, serial interface shown in Figure63. The serial configuration indicating a configuration error. The configuration process data is presented on the FPGA’s DIN input pin with requires more clock cycles than indicated from the sufficient setup time before each rising edge of the configuration file size. Additional clocks are required during externally generated CCLK clock input. the FPGA’s start-up sequence, especially if the FPGA is programmed to wait for selected Digital Clock Managers (DCMs) to lock to their respective clock inputs (see Start-Up, page106). DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 97

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 63 +1.2V VCCINT P HSWAP VCCO_0 VCCO_0 VCCO_2 V Slave Serial V Mode ‘1’ M2 Intelligent V ‘1’ M1 Download Host ‘1’ M0 Spartan-3E k 7 FPGA 4. VCC Configuration CLOCK CCLK Memory Source SERIAL_OUT DIN DOUT PROG_B INIT_B •Internal memory DONE • Disk drive VCCAUX +2.5V INIT_B • Over network TDI TDO • Over RF link GND TMS TCK +2.5V •Microcontroller •Processor PROG_B DONE • Tester • Computer GND 0 k 3 7 3 4. PROG_B Recommend open-drain driver +2.5V JTAG TDI TMS TCK TDO DS312-2_54_082009 Figure 63: Slave Serial Configuration The mode select pins, M[2:0], are sampled when the Voltage Compatibility FPGA’s INIT_B output goes High and must be at defined V Most Slave Serial interface signals are within the logic levels during this time. After configuration, when the FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input. FPGA’s DONE output goes High, the mode pins are The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match available as full-featured user-I/O pins. the requirements of the external host, ideally 2.5V. Using P Similarly, the FPGA’s HSWAP pin must be Low to 3.3V or 1.8V requires additional design considerations as enable pull-up resistors on all user-I/O pins or High to the DONE and PROG_B pins are powered by the FPGA’s disable the pull-up resistors. The HSWAP control must 2.5V V supply. See XAPP453: The 3.3V CCAUX remain at a constant logic level throughout FPGA Configuration of Spartan-3 FPGAs for additional configuration. After configuration, when the FPGA’s DONE information. output goes High, the HSWAP pin is available as Daisy-Chaining full-featured user-I/O pin and is powered by the VCCO_0 supply. If the application requires multiple FPGAs with different configurations, then configure the FPGAs using a daisy chain, as shown in Figure64. Use Slave Serial mode (M[2:0]=<1:1:1>) for all FPGAs in the daisy-chain. After the lead FPGA is filled with its configuration data, the lead DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 98

Spartan-3E FPGA Family: Functional Description FPGA passes configuration data via its DOUT output pin to the next FPGA on the falling CCLK edge. Table 66: Slave Serial Mode Connections Pin Name FPGA Direction Description During Configuration After Configuration HSWAP Input User I/O Pull-Up Control. When Drive at valid logic level User I/O Low during configuration, enables throughout configuration. pull-up resistors in all I/O pins to respective I/O bank V input. CCO 0: Pull-up during configuration 1: No pull-ups M[2:0] Input Mode Select. Selects the FPGA M2=1, M1=1, M0=1 Sampled User I/O configuration mode. See Design when INIT_B goes High. Considerations for the HSWAP, M[2:0], and VS[2:0] Pins. DIN Input Data Input. Serial data provided by host. User I/O FPGA captures data on rising CCLK edge. CCLK Input Configuration Clock. If CCLK External clock. User I/O PCB trace is long or has multiple connections, terminate this output to maintain signal integrity. See CCLK Design Considerations. INIT_B Open-drain Initialization Indicator. Active Active during configuration. If User I/O. If unused in the bidirectional I/O Low. Goes Low at start of CRC error detected during application, drive INIT_B configuration during Initialization configuration, FPGA drives High. memory clearing process. INIT_B Low. Released at end of memory clearing, when mode select pins are sampled. In daisy-chain applications, this signal requires an external 4.7 kΩ pull-up resistor to VCCO_2. DONE Open-drain FPGA Configuration Done. Low Low indicates that the FPGA is not Pulled High via external bidirectional I/O during configuration. Goes High yet configured. pull-up. When High, when FPGA successfully indicates that the FPGA completes configuration. Requires successfully configured. external 330 Ω pull-up resistor to 2.5V. PROG_B Input Program FPGA. Active Low. Must be High to allow Drive PROG_B Low and When asserted Low for 500ns or configuration to start. release to reprogram longer, forces the FPGA to restart FPGA. its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High. Recommend external 4.7 kΩ pull-up resistor to 2.5V. Internal pull-up value may be weaker (see Table78). If driving externally with a 3.3V output, use an open-drain or open-collector driver or use a current limiting series resistor. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 99

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 64 CCLK +1.2V +1.2V VCCINT VCCINT P HSWAP VCCO_0 VCCO_0 P HSWAP VCCO_0 VCCO_0 VCCO_2 V VCCO_2 VCCO_2 Slave Slave Serial V Serial Mode Mode ‘1’ M2 ‘1’ M2 Intelligent V Download Host ‘1’ M1 Ω ‘1’ M1 ‘1’ M0 7k ‘1’ M0 Spartan-3E 4. Spartan-3E VCC FPGA FPGA Configuration Memory CLOCK CCLK CCLK Source SERIAL_OUT DIN DOUT DIN DOUT DOUT PROG_B INIT_B INIT_B •••• IDOnivtseekrr n dnareilv tmweeomrkory IDNOITN_BE TDI VCCTADUOX +2.5V TDI VCCTADUOX +2.5V Over RF link GND TMS TMS TCK TCK •• Microcontroller +2.5V •• PTCeroosmtceeprsusteorr PROG_B GND DONE Ω330 Ω4.7k PROG_BGND DONE PROG_B PROG_B Recommend DONE open-drain driver INIT_B +2.5V JTAG TDI TMS TMS TCK TCK TDO DS312-2_55_082009 Figure 64: Daisy-Chaining using Slave Serial Mode JTAG Mode For additional information, refer to the “JTAG Configuration The FPGA bitstream may be corrupted and the DONE pin Mode and Boundary-Scan” chapter in UG332. may go High. The following Answer Record contains additional information. The Spartan-3E FPGA has a dedicated four-wire IEEE 1149.1/1532 JTAG port that is always available any time the http://www.xilinx.com/support/answers/22255.htm FPGA is powered and regardless of the mode pin settings. However, when the FPGA mode pins are set for JTAG mode (M[2:0]=<1:0:1>), the FPGA waits to be configured via the JTAG port after a power-on event or when PROG_B is asserted. Selecting the JTAG mode simply disables the other configuration modes. No other pins are required as part of the configuration interface. Figure65 illustrates a JTAG-only configuration interface. The JTAG interface is easily cascaded to any number of FPGAs by connecting the TDO output of one device to the TDI input of the next device in the chain. The TDO output of the last device in the chain loops back to the port connector. Design Note If using software versions prior to ISE 9.1.01i, avoid configuring the FPGA using JTAG if... (cid:129) the mode pins are set for a Master mode (cid:129) the attached Master mode PROM contains a valid FPGA configuration bitstream. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 100

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 65 +1.2V +1.2V VCCINT VCCINT P HSWAP VCCO_0 VCCO_0 P HSWAP VCCO_0 VCCO_0 VCCO_2 VCCO_2 VCCO_2 VCCO_2 JTAG JTAG Mode Mode Spartan-3E Spartan-3E ‘1’ M2 ‘1’ M2 FPGA FPGA ‘0’ M1 ‘0’ M1 ‘1’ M0 ‘1’ M0 VCCAUX +2.5V VCCAUX +2.5V TDI TDO TDI TDO TMS TMS TCK TCK PROG_B DONE PROG_B DONE GND GND +2.5V JTAG TDI TMS TMS TCK TCK TDO DS312-2_56_082009 Figure 65: JTAG Configuration Mode Voltage Compatibility JTAG Device ID The 2.5V V supply powers the JTAG interface. All of Each Spartan-3E FPGA array type has a 32-bit CCAUX the user I/Os are separately powered by their respective device-specific JTAG device identifier as shown in Table67. VCCO_# supplies. The lower 28 bits represent the device vendor (Xilinx) and device identifer. The upper four bits, ignored by most tools, When connecting the Spartan-3E JTAG port to a 3.3V represent the revision level of the silicon mounted on the interface, the JTAG input pins must be current-limited to printed circuit board. Table67 associates the revision code 10mA or less using series resistors. Similarly, the TDO pin with a specific stepping level. is a CMOS output powered from +2.5V. The TDO output can directly drive a 3.3V input but with reduced noise immunity. JTAG User ID See XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for additional information. The Spartan-3E JTAG interface also provides the option to store a 32-bit User ID, loaded during configuration. The Table 67: Spartan-3E JTAG Device Identifiers User ID value is specified via the UserID configuration bitstream option, shown in Table69, page108. 4-Bit Revision Code 28-Bit Spartan-3E Vendor/Device FPGA Step 0 Step 1 Identifier Using JTAG Interface to Communicate to a Configured FPGA Design XC3S100E 0x0 0x1 0x1C 10 093 After the FPGA is configured, using any of the available XC3S250E 0x0 0x1 0x1C 1A 093 modes, the JTAG interface offers a possible 0x0 XC3S500E 0x4 0x1C 22 093 communications channel to internal FPGA logic. The 0x2 BSCAN_SPARTAN3 design primitive provides two private 0x0 JTAG instructions to create an internal boundary scan XC3S1200E 0x2 0x1C 2E 093 0x1 chain. 0x0 XC3S1600E 0x2 0x1C 3A 093 0x1 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 101

Spartan-3E FPGA Family: Functional Description Maximum Bitstream Size for Daisy-Chains The FPGA configuration sequence can also be initiated by asserting PROG_B. Once released, the FPGA begins The maximum bitstream length supported by Spartan-3E clearing its internal configuration memory, and progresses FPGAs in serial daisy-chains is 4,294,967,264 bits through the remainder of the configuration process. (4Gbits), roughly equivalent to a daisy-chain with 720 XC3S1600E FPGAs. This is a limit only for serial daisy-chains where configuration data is passed via the FPGA’s DOUT pin. There is no such limit for JTAG chains. Configuration Sequence For additional information including I/O behavior before and during configuration, refer to the “Sequence of Events” chapter in UG332. The Spartan-3E configuration process is three-stage process that begins after the FPGA powers on (a POR event) or after the PROG_B input is asserted. Power-On Reset (POR) occurs after the V , V , and the CCINT CCAUX VCCO Bank 2 supplies reach their respective input threshold levels. After either a POR or PROG_B event, the three-stage configuration process begins. 1. The FPGA clears (initializes) the internal configuration memory. 2. Configuration data is loaded into the internal memory. 3. The user-application is activated by a start-up process. Figure66 is a generalized block diagram of the Spartan-3E configuration logic, showing the interaction of different device inputs and Bitstream Generator (BitGen) options. A flow diagram for the configuration sequence of the Serial and Parallel modes appears in Figure66. Figure67 shows the Boundary-Scan or JTAG configuration sequence. Initialization Configuration automatically begins after power-on or after asserting the FPGA PROG_B pin, unless delayed using the FPGA’s INIT_B pin. The FPGA holds the open-drain INIT_B signal Low while it clears its internal configuration memory. Externally holding the INIT_B pin Low forces the configuration sequencer to wait until INIT_B again goes High. The FPGA signals when the memory-clearing phase is complete by releasing the open-drain INIT_B pin, allowing the pin to go High via the external pull-up resistor to VCCO_2. Loading Configuration Data After initialization, configuration data is written to the FPGA’s internal memory. The FPGA holds the Global Set/Reset (GSR) signal active throughout configuration, holding all FPGA flip-flops in a reset state. The FPGA signals when the entire configuration process completes by releasing the DONE pin, allowing it to go High. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 102

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 66 DONE Force all I/Os Hi-Z Hold all storageelements reset Disable writeoperations tostorage elements INIT_B N N E E DriveDone STARTUP DONEDCMs_LOCKEDLCK_cycleDONE_cycleEnable application logic andI/O pins ENABLEGTSGTS_cycle GTS_INGSRGSR_IN GWERESETGWE_cycleWAIT DonePipe These connections are available via the*STARTUP_SPARTAN3E library primitive. ** R R R All DCMs CONFIGURATION ENABLEDONE Load applicationUSEdata into CMOSconfiguration latchesUSE RESET *USER_CLOCK StartupClk K ENABLECERRO Configuration ErrorDetection(CRC Checker) C R O C L C _ N D O LOCKE DCM in UserApplication STARTUP_WAIT=TRUE INITIALIZATION ENABLEDONE Clear internal CMOSconfiguration latches CLEARING_MEMORY RESETWAIT JTAG_CLOCK INTERNAL_CONFIGURATI D O O G _ R E W O 1 0 P n o pti O n) = Bitstream Generator (BitGe = Design Attribute ower On Reset (POR) VCCO2T VCCINTT VCCAUXT Glitch Filter 1 0ConfigRate InternalOscillator P n n Optio Optio CCO_2 CCINT CCAUX ROG_B CCLK TCK M1 M2 V V V P DS312-2_57_102605 Figure 66: Generalized Spartan-3E FPGA Configuration Logic Block Diagram DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 103

Spartan-3E FPGA Family: Functional Description Set PROG_B Low Power-On after Power-On VCCINT >1V and VCCAUX > 2V No and VCCO Bank 2 > 1V Yes Yes Clear configuration PROG_B = Low memory No No INIT_B = High? Yes M[2:0] and VS[2:0] Sample mode pins pins are sampled on INIT_B rising edge Load configuration data frames CRC No INIT_B goes Low. correct? Abort Start-Up Yes DONE pin goes High, Start-Up signaling end of sequence configuration User mode No Yes Reconfigure? DS312-2_58_051706 Figure 66: General Configuration Process DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 104

Spartan-3E FPGA Family: Functional Description X-Ref Target - Figure 67 Set PROG_B Low Power-On after Power-On VCCINT >1V and VCCAUX > 2V No and VCCO Bank 2 > 1V Load Yes JPROG instruction Clear Yes configuration PROG_B = Low memory No No INIT_B = High? Yes Sample mode pins (JTAG port becomes available) Load CFG_IN instruction Load configuration data frames No CRC INIT_B goes Low. correct? Abort Start-Up Yes Synchronous TAP reset (Clock five 1's on TMS) Load JSTART instruction Start-Up sequence User mode Yes No Reconfigure? DS312-2_59_051706 Figure 67: Boundary-Scan Configuration Flow Diagram DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 105

Spartan-3E FPGA Family: Functional Description Start-Up At the end of configuration, the FPGA automatically pulses The function of the dual-purpose I/O pins, such as M[2:0], the Global Set/Reset (GSR) signal, placing all flip-flops in a VS[2:0], HSWAP, and A[23:0], also changes when the known state. After configuration completes, the FPGA DONE pin goes High. When DONE is High, these pins switches over to the user application loaded into the FPGA. become user I/Os. Like all user-I/O pins, GTS controls when The sequence and timing of how the FPGA switches over is the dual-purpose pins can drive out. programmable as is the clock source controlling the The relative timing of configuration events is programmed sequence. via the Bitstream Generator (BitGen) options in the Xilinx The default start-up sequence appears in Figure68, where development software. For example, the GTS and GWE the Global Three-State signal (GTS) is released one clock events can be programmed to wait for all the DONE pins to cycle after DONE goes High. This sequence allows the High on all the devices in a multiple-FPGA daisy-chain, DONE signal to enable or disable any external logic used forcing the FPGAs to start synchronously. Similarly, the during configuration before the user application in the FPGA start-up sequence can be paused at any stage, waiting for starts driving output signals. One clock cycle later, the selected DCMs to lock to their respective input clock Global Write Enable (GWE) signal is released. This allows signals. See also Stabilizing DCM Clocks Before User signals to propagate within the FPGA before any clocked Mode. storage elements such as flip-flops and block ROM are By default, the start-up sequence is synchronized to CCLK. enabled. Alternatively, the start-up sequence can be synchronized to X-Ref Target - Figure 68 a user-specified clock from within the FPGA application Default Cycles using the STARTUP_SPARTAN3E library primitive and by setting the StartupClk bitstream generator option. The Start-Up Clock FPGA application can optionally assert the GSR and GTS signals via the STARTUP_SPARTAN3E primitive. For JTAG Phase 0 1 2 3 4 5 6 7 configuration, the start-up sequence can be synchronized to the TCK clock input. DONE GTS GWE Sync-to-DONE Start-Up Clock Phase 0 1 2 3 4 5 6 7 DONE High DONE GTS GWE DS312-2_60_022305 Figure 68: Default Start-Up Sequence DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 106

Spartan-3E FPGA Family: Functional Description Readback FPGA configuration data can be read back using either the Table 68: Readback Support in Spartan-3E FPGAs Slave Parallel or JTAG mode. This function is disabled if the Temperature Range Commercial Industrial Bitstream Generator Security option is set to either Level1 or Level2. Speed Grade -4 -5 -4 Along with the configuration data, it is possible to read back Block RAM Readback the contents of all registers and distributed RAM. All Spartan-3E FPGAs No Yes Yes To synchronously control when register values are captured General Readback (registers, distributed RAM) for readback, use the CAPTURE_SPARTAN3 library XC3S100E Yes Yes Yes primitive, which applies for both Spartan-3 and Spartan-3E XC3S250E Yes Yes Yes FPGA families. XC3S500E Yes Yes Yes The Readback feature is available in most Spartan-3E FPGA product options, as indicated in Table68. The XC3S1200E No Yes Yes Readback feature is not available in the XC3S1200E and XC3S1600E No Yes Yes XC3S1600E FPGAs when using the -4 speed grade in the Commercial temperature grade. Similarly, block RAM Readback support is not available in the -4 speed grade, Commercial temperature devices. If Readback is required in an XC3S1200E or XC3S1600E FPGA, or if block RAM Readback is required on any Spartan-3E FPGA, upgrade to either the Industrial temperature grade version or the -5 speed grade. The Xilinx iMPACT programming software uses the Readback feature for its optional Verify and Readback operations. The Xilinx ChipScope™ software presently does not use Readback but may in future updates. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 107

Spartan-3E FPGA Family: Functional Description Bitstream Generator (BitGen) Options For additional information, refer to the “Configuration values are specified when creating the bitstream image with Bitstream Generator (BitGen) Settings” chapter in UG332. the Bitstream Generator (BitGen) software. Various Spartan-3E FPGA functions are controlled by Table69 provides a list of all BitGen options for Spartan-3E specific bits in the configuration bitstream image. These FPGAs. Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options Pins/Function Values Option Name Description Affected (default) ConfigRate CCLK, 1, 3, 6, Sets the approximate frequency, in MHz, of the internal oscillator using for Master Configuration 12, 25, 50 Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest frequency, and the new setting is loaded as part of the configuration bitstream. The software default value is 1 (~1.5MHz) starting with ISE 8.1, Service Pack 1. StartupClk Configuration, Cclk Default. The CCLK signal (internally or externally generated) controls the startup Startup sequence when the FPGA transitions from configuration mode to the user mode. See Start-Up. UserClk A clock signal from within the FPGA application controls the startup sequence when the FPGA transitions from configuration mode to the user mode. See Start-Up. The FPGA application supplies the user clock on the CLK pin on the STARTUP_SPARTAN3E primitive. Jtag The JTAG TCK input controls the startup sequence when the FPGA transitions from the configuration mode to the user mode. See Start-Up. UnusedPin Unused I/O Pulldown Default. All unused I/O pins and input-only pins have a pull-down resistor to GND. Pins Pullup All unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply for its associated I/O bank. Pullnone All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance, three-state). Use external pull-up or pull-down resistors or logic to apply a valid signal level. DONE_cycle DONE pin, 1, 2, 3, 4, Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See Configuration 5, 6 Start-Up. Startup GWE_cycle All flip-flops, 1, 2, 3, 4, Selects the Configuration Startup phase that asserts the internal write-enable signal to LUT RAMs, and 5, 6 all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read and SRL16 shift write operations. See Start-Up. registers, Block Done Waits for the DONE pin input to go High before asserting the internal write-enable signal RAM, to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and write Configuration operations are enabled at this time. Startup Keep Retains the current GWE_cycle setting for partial reconfiguration applications. GTS_cycle All I/O pins, 1, 2, 3, 4, Selects the Configuration Startup phase that releases the internal three-state control, Configuration 5, 6 holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so configured, after this point. See Start-Up. Done Waits for the DONE pin input to go High before releasing the internal three-state control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so configured, after this point. Keep Retains the current GTS_cycle setting for partial reconfiguration applications. LCK_cycle DCMs, NoWait The FPGA does not wait for selected DCMs to lock before completing configuration. Configuration 0, 1, 2, 3, If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE, the Startup 4, 5, 6 FPGA waits for such DCMs to acquire their respective input clock and assert their LOCKED output. This setting selects the Configuration Startup phase where the FPGA waits for the DCMs to lock. DonePin DONE pin Pullup Internally connects a pull-up resistor between DONE pin and V . An external CCAUX 330Ω pull-up resistor to V is still recommended. CCAUX Pullnone No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to V CCAUX is required. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 108

Spartan-3E FPGA Family: Functional Description Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Cont’d) Pins/Function Values Option Name Description Affected (default) DriveDone DONE pin No When configuration completes, the DONE pin stops driving Low and relies on an external 330 Ω pull-up resistor to V for a valid logic High. CCAUX Yes When configuration completes, the DONE pin actively drives High. When using this option, an external pull-up resistor is no longer required. Only one device in an FPGA daisy-chain should use this setting. DonePipe DONE pin No The input path from DONE pin input back to the Startup sequencer is not pipelined. Yes This option adds a pipeline register stage between the DONE pin input and the Startup sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of StartupClk after the DONE pin input goes High. ProgPin PROG_B pin Pullup Internally connects a pull-up resistor or between PROG_B pin and V . An external CCAUX 4.7 kΩ pull-up resistor to V is still recommended since the internal pull-up value CCAUX may be weaker (see Table78). Pullnone No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to V is required. CCAUX TckPin JTAG TCK pin Pullup Internally connects a pull-up resistor between JTAG TCK pin and V . CCAUX Pulldown Internally connects a pull-down resistor between JTAG TCK pin and GND. Pullnone No internal pull-up resistor on JTAG TCK pin. TdiPin JTAG TDI pin Pullup Internally connects a pull-up resistor between JTAG TDI pin and V . CCAUX Pulldown Internally connects a pull-down resistor between JTAG TDI pin and GND. Pullnone No internal pull-up resistor on JTAG TDI pin. TdoPin JTAG TDO pin Pullup Internally connects a pull-up resistor between JTAG TDO pin and V . CCAUX Pulldown Internally connects a pull-down resistor between JTAG TDO pin and GND. Pullnone No internal pull-up resistor on JTAG TDO pin. TmsPin JTAG TMS pin Pullup Internally connects a pull-up resistor between JTAG TMS pin and V . CCAUX Pulldown Internally connects a pull-down resistor between JTAG TMS pin and GND. Pullnone No internal pull-up resistor on JTAG TMS pin. UserID JTAG User ID User string The 32-bit JTAG User ID register value is loaded during configuration. The default value register is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an 8-character hexadecimal value. Security JTAG, None Readback and limited partial reconfiguration are available via the JTAG port or via the SelectMAP, SelectMAP interface, if the Persist option is set to Yes. Readback, Level1 Readback function is disabled. Limited partial reconfiguration is still available via the Partial JTAG port or via the SelectMAP interface, if the Persist option is set to Yes. reconfiguration Level2 Readback function is disabled. Limited partial reconfiguration is disabled. CRC Configuration Enable Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA asserts INIT_B Low and DONE pin stays Low. Disable Turn off CRC checking. Persist SelectMAP No All BPI and Slave mode configuration pins are available as user-I/O after configuration. interface pins, Yes This option is required for Readback and partial reconfiguration using the SelectMAP BPI mode, interface. The SelectMAP interface pins (see Slave Parallel Mode) are reserved after Slave mode, configuration and are not available as user-I/O. Configuration DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 109

Spartan-3E FPGA Family: Functional Description Powering Spartan-3E FPGAs supply inputs for internal logic functions, V and CCINT V . Each of the four I/O banks has a separate V CCAUX CCO For additional information, refer to the “Powering Spartan-3 supply input that powers the output buffers within the Generation FPGAs” chapter in UG331. associated I/O bank. All of the V connections to a CCO specific I/O bank must be connected and must connect to Voltage Supplies the same voltage. Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple voltage supply inputs, as shown in Table70. There are two Table 70: Spartan-3E Voltage Supplies Supply Input Description Nominal Supply Voltage V Internal core supply voltage. Supplies all internal logic functions, such as CLBs, block 1.2V CCINT RAM, and multipliers. Input to Power-On Reset (POR) circuit. V Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential drivers, 2.5V CCAUX dedicated configuration pins, JTAG interface. Input to Power-On Reset (POR) circuit. VCCO_0 Supplies the output buffers in I/O Bank 0, the bank along the top edge of the FPGA. Selectable, 3.3V, 2.5V, 1.8, 1.5V, or 1.2V VCCO_1 Supplies the output buffers in I/O Bank 1, the bank along the right edge of the FPGA. In Selectable, 3.3V, 2.5V, 1.8, Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode, connects to the same voltage 1.5V, or 1.2V as the Flash PROM. VCCO_2 Supplies the output buffers in I/O Bank 2, the bank along the bottom edge of the FPGA. Selectable, 3.3V, 2.5V, 1.8, Connects to the same voltage as the FPGA configuration source. Input to Power-On 1.5V, or 1.2V Reset (POR) circuit. VCCO_3 Supplies the output buffers in I/O Bank 3, the bank along the left edge of the FPGA. Selectable, 3.3V, 2.5V, 1.8, 1.5V, or 1.2V In a 3.3V-only application, all four V supplies connect to CCO 3.3V. However, Spartan-3E FPGAs provide the ability to bridge between different I/O voltages and standards by applying different voltages to the V inputs of different CCO banks. Refer to I/O Banking Rules for which I/O standards can be intermixed within a single I/O bank. Each I/O bank also has an separate, optional input voltage reference supply, called V . If the I/O bank includes an I/O REF standard that requires a voltage reference such as HSTL or SSTL, then all V pins within the I/O bank must be REF connected to the same voltage. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 110

Spartan-3E FPGA Family: Functional Description Voltage Regulators do not require Power-On Surge (POS) current to successfully configure. Various power supply manufacturers offer complete power solutions for Xilinx FPGAs including some with integrated Surplus ICCINT if VCCINT Applied before VCCAUX three-rail regulators specifically designed for Spartan-3 and If the V supply is applied before the V supply, Spartan-3E FPGAs. The Xilinx Power Corner website CCINT CCAUX the FPGA might draw a surplus I current in addition to provides links to vendor solution guides and Xilinx power CCINT the I quiescent current levels specified in Table79, estimation and analysis tools. CCINT page119. The momentary additional I surplus current CCINT might be a few hundred milliamperes under nominal Power Distribution System (PDS) Design conditions, significantly less than the instantaneous current and Decoupling/Bypass Capacitors consumed by the bypass capacitors at power-on. However, the surplus current immediately disappears when the Good power distribution system (PDS) design is important V supply is applied, and, in response, the FPGA’s CCAUX for all FPGA designs, but especially so for high performance I quiescent current demand drops to the levels CCINT applications, greater than 100MHz. Proper design results specified in Table79. The FPGA does not use or require the in better overall performance, lower clock and DCM jitter, surplus current to successfully power-on and configure. If and a generally more robust system. Before designing the applying V before V , ensure that the regulator CCINT CCAUX printed circuit board (PCB) for the FPGA design, please does not have a foldback feature that could inadvertently review XAPP623: Power Distribution System (PDS) Design: shut down in the presence of the surplus current. Using Bypass/Decoupling Capacitors. Configuration Data Retention, Brown-Out Power-On Behavior The FPGA’s configuration data is stored in robust CMOS For additional power-on behavior information, including I/O configuration latches. The data in these latches is retained behavior before and during configuration, refer to the even when the voltages drop to the minimum levels “Sequence of Events” chapter in UG332. necessary to preserve RAM contents, as specified in Spartan-3E FPGAs have a built-in Power-On Reset (POR) Table76. circuit that monitors the three power rails required to If, after configuration, the V or V supply drops CCAUX CCINT successfully configure the FPGA. At power-up, the POR below its data retention voltage, the current device circuit holds the FPGA in a reset state until the V , CCINT configuration must be cleared using one of the following V , and V Bank 2 supplies reach their respective CCAUX CCO methods: input threshold levels (see Table74 in Module3). After all three supplies reach their respective thresholds, the POR (cid:129) Force the VCCAUX or VCCINT supply voltage below the reset is released and the FPGA begins its configuration minimum Power On Reset (POR) voltage threshold process. (Table74). (cid:129) Assert PROG_B Low. Supply Sequencing The POR circuit does not monitor the VCCO_2 supply after Because the three FPGA supply inputs must be valid to configuration. Consequently, dropping the VCCO_2 voltage release the POR reset and can be supplied in any order, does not reset the device by triggering a Power-On Reset there are no FPGA-specific voltage sequencing (POR) event. requirements. Applying the FPGA’s V supply before CCAUX the V supply uses the least I current. CCINT CCINT No Internal Charge Pumps or Free-Running Although the FPGA has no specific voltage sequence Oscillators requirements, be sure to consider any potential sequencing requirement of the configuration device attached to the Some system applications are sensitive to sources of FPGA, such as an SPI serial Flash PROM, a parallel NOR analog noise. Spartan-3E FPGA circuitry is fully static and Flash PROM, or a microcontroller. For example, Flash does not employ internal charge pumps. PROMs have a minimum time requirement before the The CCLK configuration clock is active during the FPGA PROM can be selected and this must be considered if the configuration process. After configuration completes, the 3.3V supply is the last in the sequence. See Power-On CCLK oscillator is automatically disabled unless the Precautions if 3.3V Supply is Last in Sequence for more Bitstream Generator (BitGen) option Persist=Yes. details. When all three supplies are valid, the minimum current required to power-on the FPGA equals the worst-case quiescent current, specified in Table79. Spartan-3E FPGAs DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 111

Spartan-3E FPGA Family: Functional Description Production Stepping The Spartan-3E FPGA family uses production stepping to Designs operating on the Stepping 0 devices perform indicate improved capabilities or enhanced features. similarly on a Stepping 1 device. Stepping 1 is, by definition, a functional superset of Differences Between Steppings Stepping 0. Furthermore, configuration bitstreams generated for Stepping 0 are compatible with Stepping 1. Table71 summarizes the feature and performance differences between Stepping 0 devices and Stepping 1 devices. Table 71: Differences between Spartan-3E Production Stepping Levels Stepping 0 Stepping 1 Production status Production starting Production from 2005 to 2007 March 2006 Speed grade and operating conditions -4C only -4C, -4I, -5C JTAG ID code Different revision fields. See Table67. DCM DLL maximum input frequency 90MHz 240MHz (-4 speed grade) (200MHz for XC3S1200E) 275MHz (-5 speed grade) DCM DFS output frequency range(s) Split ranges at 5 – 90MHz and Continuous range: 220 – 307MHz 5 – 311MHz (-4) (single range 5 – 307MHz for XC3S1200E) 5 – 333MHz (-5) Supports multi-FPGA daisy-chain configurations from No, single FPGA only Yes SPI Flash JTAG configuration supported when FPGA in BPI mode with a valid image in the attached parallel NOR No(1) Yes Flash PROM JTAG EXTEST, INTEST, SAMPLE support Yes: XC3S100E, XC3S250E, XC3S500E Yes No(2): XC3S1200E, XC3S1600E All Devices Power sequencing when using HSWAP Pull-Up Requires V before V Any sequence CCINT CCAUX PCI compliance No Yes Notes: 1. Workarounds exist. See Stepping 0 Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration. 2. JTAG BYPASS and JTAG configuration are supported. Ordering a Later Stepping Software Version Requirements -5C and -4I devices, and -4C devices (with date codes 0901 Production Spartan-3E applications must be processed (2009) and later) always support the Stepping 1 feature set using the Xilinx ISE 8.1i, Service Pack 3 or later independent of the stepping code. Optionally, to order only development software, using the v1.21 or later speed files. Stepping 1 for the -4C devices, append an “S1” suffix to the The ISE 8.1i software implements critical bitstream standard ordering code, where ‘1’ is the stepping number, generator updates. as indicated in Table72. For additional information on Spartan-3E development Table 72: Spartan-3E Optional Stepping Ordering software and known issues, see the following Answer Record: Stepping Suffix Code Status Number (cid:129) Xilinx Answer #22253 http://www.xilinx.com/support/answers/22253.htm 0 None Production 1 S1 Production DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 112

Spartan-3E FPGA Family: Functional Description Revision History The following table shows the revision history for this document. Date Version Revision 03/01/2005 1.0 Initial Xilinx release. 03/21/2005 1.1 Updated Figure45. Modified title on Table39 and Table45. 11/23/2005 2.0 Updated values of On-Chip Differential Termination resistors. Updated Table7. Updated configuration bitstream sizes for XC3S250E through XC3S1600E in Table45, Table51, Table57, and Table60. Added DLL Performance Differences Between Steppings. Added Stepping 0 Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration. Added Stepping 0 limitations when Daisy-Chaining in SPI configuration mode. Added Multiplier/Block RAM Interaction section. Updated Digital Clock Managers (DCMs) section, especially Phase Shifter (PS) portion. Corrected and enhanced the clock infrastructure diagram in Figure45 and Table41. Added CCLK Design Considerations section. Added Design Considerations for the HSWAP, M[2:0], and VS[2:0] Pins section. Added Spansion, Winbond, and Macronix to list of SPI Flash vendors in Table53 and Table56. Clarified that SPI mode configuration supports Atmel ‘C’- and ‘D’-series DataFlash. Updated the Programming Support section for SPI Flash PROMs. Added Power-On Precautions if PROM Supply is Last in Sequence, Compatible Flash Families, and BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs sections to BPI configuration mode topic. Updated and amplified Powering Spartan-3E FPGAs section. Added Production Stepping section. 03/22/2006 3.0 Upgraded data sheet status to Preliminary. Updated Input Delay Functions and Figure6. Added clarification that Input-only pins also have Pull-Up and Pull-Down Resistors. Added design note about address setup and hold requirements to Block RAM. Added warning message about software differences between ISE 8.1i, Service Pack 3 and earlier software to FIXED Phase Shift Mode and VARIABLE Phase Shift Mode. Added message about using GCLK1 in DLL Clock Input Connections and Clock Inputs. Updated Figure45. Added additional information on HSWAP behavior to Pin Behavior During Configuration. Highlighted which pins have configuration pull-up resistors unaffected by HSWAP in Table46. Updated bitstream image sizes for the XC3S1200E and XC3S1600E in Table45, Table51, Table57, and Table60. Clarified that ‘B’-series Atmel DataFlash SPI PROMs can be used in Commercial temperature range applications in Table53 and Figure54. Updated Figure56. Updated Dynamically Loading Multiple Configuration Images Using MultiBoot Option section. Added design note about BPI daisy-chaining software support to BPI Daisy-Chaining section. Updated JTAG revision codes in Table67. Added No Internal Charge Pumps or Free-Running Oscillators. Updated information on production stepping differences in Table71. Updated Software Version Requirements. 04/10/2006 3.1 Updated JTAG User ID information. Clarified Note 1, Figure5. Clarified that Figure45 shows electrical connectivity and corrected left- and right-edge DCM coordinates. Updated Table30, Table31, and Table32 to show the specific clock line driven by the associated BUFGMUX primitive. Corrected the coordinate locations for the associated BUFGMUX primitives in Table31 and Table32. Updated Table41 to show that the I0-input is the preferred connection to a BUFGMUX. 05/19/2006 3.2 Made further clarifying changes to Figure 46, showing both direct inputs to BUFGMUX primitives and to DCMs. Added Atmel AT45DBxxxD-series DataFlash serial PROMs to Table53. Added details that intermediate FPGAs in a BPI-mode, multi-FPGA configuration daisy-chain must be from either the Spartan-3E or the Virtex-5 FPGA families (see BPI Daisy-Chaining). Added Using JTAG Interface to Communicate to a Configured FPGA Design. Minor updates to Figure66 and Figure67. Clarified which Spartan-3E FPGA product options support the Readback feature, shown in Table68. 05/30/2006 3.2.1 Corrected various typos and incorrect links. 10/02/2006 3.3 Clarified that the block RAM Readback feature is available either on the -5 speed grade or the Industrial temperature range. 11/09/2006 3.4 Updated the description of the Input Delay Functions. The ODDR2 flip-flop with C0 or C1 Alignment is no longer supported. Updated Figure5. Updated Table6 for improved PCI input voltage tolerance. Replaced missing text in Clock Buffers/Multiplexers. Updated SPI Flash devices in Table53. Updated parallel NOR Flash devices in Table61. Direct, SPI Flash in-system Programming Support was added beginning with ISE 8.1i iMPACT software for STMicro and Atmel SPI PROMs. Updated Table71 and Table72 as Stepping 1 is in full production. Freshened various hyper links. Promoted Module2 to Production status. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 113

Spartan-3E FPGA Family: Functional Description Date Version Revision 03/16/2007 3.5 Added information about new Spartan-3 Generation user guides (Design Documentation Available). Added cross-references to UG331: Spartan-3 Generation FPGA User Guide and to UG332: Spartan-3 Generation Configuration User Guide. Added note about possible JTAG configuration issues when the FPGA mode pins are set for Master mode and using software prior to ISE 9.1.01i (JTAG Mode). Removed a few lingering references to “weak” pull-up resistors, including in Figure12. Removed vestigial references regarding the LDC[2:0] and HDC pins during Slave Parallel Mode configuration. These pins are not used in this configuration mode. 05/29/2007 3.6 Added information about HSWAP and PCI differences between steppings to Table71. Removed “Performance Differences between Global Buffers” to match improved specs in Module3. Updated PROG_B pulse width descriptions to match specification in Module3. 04/18/2008 3.7 Corrected Figure6 to show six taps and updated associated text. Added note for recommended pull-up on DONE in Table55 and elsewhere. Added a caution regarding Persist of pins A20-A23. Updated Stepping description in Table71 to note that only Stepping 1 is in production today. Updated links. 08/26/2009 3.8 Added a frequency limitation to Equation6. Added a new Equation7 with a frequency limitation. Added a Spread Spectrum, page57 paragraph. Added Table42, page61. Updated a Flash vendor name in Table61, page89. Removed the < symbol from the flash read access times in Table62, page89. Revised the first paragraph in Configuration Sequence, page102. Revised the first paragraph in Power-On Behavior, page111. Revised the second paragraph in Production Stepping, page112. Revised the first paragraph in Ordering a Later Stepping, page112. 10/29/2012 4.0 Added Notice of Disclaimer. This product is not recommended for new designs. Updated the design note section in VARIABLE Phase Shift Mode. Added the VQ100 to the Quadrant Clock Routing section. 07/19/2013 4.1 Removed banner. This product IS recommended for new designs. 12/14/2018 4.2 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024). Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 114

156 Spartan-3E FPGA Family: DC and Switching Characteristics DS312 (v4.2) December 14, 2018 Product Specification DC Electrical Characteristics In this section, specifications may be designated as All parameter limits are representative of worst-case supply Advance, Preliminary, or Production. These terms are voltage and junction temperature conditions. Unless defined as follows: otherwise noted, the published parameter values apply to all Spartan®-3E devices. AC and DC characteristics Advance: Initial estimates are based on simulation, early are specified using the same numbers for both characterization, and/or extrapolation from the commercial and industrial grades. characteristics of other families. Values are subject to change. Use as estimates, not for production. Absolute Maximum Ratings Preliminary: Based on characterization. Further changes are not expected. Stresses beyond those listed under Table73, Absolute Maximum Ratings may cause permanent damage to the Production: These specifications are approved once the device. These are stress ratings only; functional operation silicon has been characterized over numerous production of the device at these or any other conditions beyond those lots. Parameter values are considered stable with no future listed under the Recommended Operating Conditions is not changes expected. implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. Table 73: Absolute Maximum Ratings Symbol Description Conditions Min Max Units V Internal supply voltage –0.5 1.32 V CCINT V Auxiliary supply voltage –0.5 3.00 V CCAUX V Output driver supply voltage –0.5 3.75 V CCO V Input reference voltage –0.5 V +0.5(1) V REF CCO V (1,2,3,4) Voltage applied to all User I/O pins and Driver in a Commercial –0.95 4.4 V IN Dual-Purpose pins high-impedance Industrial –0.85 4.3 V state Voltage applied to all Dedicated pins All temp. ranges –0.5 V +0.5(3) V CCAUX I Input clamp current per I/O pin –0.5 V < V < (V + 0.5 V) – ±100 mA IK IN CCO V Electrostatic Discharge Voltage Human body model – ±2000 V ESD Charged device model – ±500 V Machine model – ±200 V T Junction temperature – 125 °C J T Storage temperature –65 150 °C STG Notes: 1. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ V rails. Keeping V within 500mV of the CCO IN associated V rails or ground rail ensures that the internal diode junctions do not turn on. Table77 specifies the V range used to CCO CCO evaluate the maximum V voltage. IN 2. Input voltages outside the -0.5V to V + 0.5V (or V + 0.5V) voltage range are require the I input diode clamp diode rating is met CCO CCAUX IK and no more than 100 pins exceed the range simultaneously. Prolonged exposure to such current may compromise device reliability. A sustained current of 10mA will not compromise device reliability. See XAPP459: Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families for more details. 3. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V rail (2.5V). Meeting the V max limit ensures CCAUX IN that the internal diode junctions that exist between each of these pins and the V rail do not turn on. Table77 specifies the V CCAUX CCAUX range used to evaluate the maximum V voltage. As long as the V max specification is met, oxide stress is not possible. IN IN 4. See XAPP459: Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families. 5. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages. © Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 115

Spartan-3E FPGA Family: DC and Switching Characteristics Power Supply Specifications Table 74: Supply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units V Threshold for the V supply 0.4 1.0 V CCINTT CCINT V Threshold for the V supply 0.8 2.0 V CCAUXT CCAUX V Threshold for the V Bank 2 supply 0.4 1.0 V CCO2T CCO Notes: 1. V , V , and V supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash, CCINT CCAUX CCO SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. In Step 0 devices using the HSWAP internal pull-up, V must be applied before V . CCINT CCAUX 2. To ensure successful power-on, V , V Bank 2, and V supplies must rise through their respective threshold-voltage ranges with CCINT CCO CCAUX no dips at any point. Table 75: Supply Voltage Ramp Rate Symbol Description Min Max Units V Ramp rate from GND to valid V supply level 0.2 50 ms CCINTR CCINT V Ramp rate from GND to valid V supply level 0.2 50 ms CCAUXR CCAUX V Ramp rate from GND to valid V Bank 2 supply level 0.2 50 ms CCO2R CCO Notes: 1. V , V , and V supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash, CCINT CCAUX CCO SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. In Step 0 devices using the HSWAP internal pull-up, V must be applied before V . CCINT CCAUX 2. To ensure successful power-on, V , V Bank 2, and V supplies must rise through their respective threshold-voltage ranges with CCINT CCO CCAUX no dips at any point. Table 76: Supply Voltage Levels Necessary for Preserving RAM Contents Symbol Description Min Units V V level required to retain RAM data 1.0 V DRINT CCINT V V level required to retain RAM data 2.0 V DRAUX CCAUX Notes: 1. RAM contents include configuration data. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 116

Spartan-3E FPGA Family: DC and Switching Characteristics General Recommended Operating Conditions Table 77: General Recommended Operating Conditions Symbol Description Min Nominal Max Units T Junction temperature Commercial 0 – 85 °C J Industrial –40 – 100 °C V Internal supply voltage 1.140 1.200 1.260 V CCINT V (1) Output driver supply voltage 1.100 - 3.465 V CCO V Auxiliary supply voltage 2.375 2.500 2.625 V CCAUX V (2,3) Input voltage extremes to avoid I/O, Input-only, and IP or IO_# –0.5 – V + 0.5 V IN CCO turning on I/O protection diodes Dual-Purpose pins (4) IO_Lxxy_#(5) –0.5 – V + 0.5 V CCO Dedicated pins(6) –0.5 – V + 0.5 V CCAUX T Input signal transition time(7) – – 500 ns IN Notes: 1. This V range spans the lowest and highest operating voltages for all supported I/O standards. Table80 lists the recommended V CCO CCO range specific to each of the single-ended I/O standards, and Table82 lists that specific to the differential standards. 2. Input voltages outside the recommended range require the I input clamp diode rating is met and no more than 100 pins exceed the range IK simultaneously. Refer to Table73. 3. See XAPP459: Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families. 4. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ V rails. Meeting the V limit ensures that the CCO IN internal diode junctions that exist between these pins and their associated V and GND rails do not turn on. The absolute maximum rating CCO is provided in Table73. 5. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage IN between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide. 6. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V rail (2.5V). Meeting the V max limit ensures CCAUX IN that the internal diode junctions that exist between each of these pins and the V and GND rails do not turn on. CCAUX 7. Measured between 10% and 90% V . Follow Signal Integrity recommendations. CCO DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 117

Spartan-3E FPGA Family: DC and Switching Characteristics General DC Characteristics for I/O Pins Table 78: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description Test Conditions Min Typ Max Units I (3) Leakage current at User I/O, Input-only, Driver is in a high-impedance state, V = –10 – +10 μA L IN Dual-Purpose, and Dedicated pins 0V or V max, sample-tested CCO I (2) Current through pull-up resistor at User I/O, V = 0V, V = 3.3V –0.36 – –1.24 mA RPU IN CCO Dual-Purpose, Input-only, and Dedicated V = 0V, V = 2.5V –0.22 – –0.80 mA pins IN CCO V = 0V, V = 1.8V –0.10 – –0.42 mA IN CCO V = 0V, V = 1.5V –0.06 – –0.27 mA IN CCO V = 0V, V = 1.2V –0.04 – –0.22 mA IN CCO R (2) Equivalent pull-up resistor value at User V = 0V, V = 3.0V to 3.465V 2.4 – 10.8 kΩ PU IN CCO I/O, Dual-Purpose, Input-only, and V = 0V, V = 2.3V to 2.7V 2.7 – 11.8 kΩ Dedicated pins (based on I per Note 2) IN CCO RPU V = 0V, V = 1.7V to 1.9V 4.3 – 20.2 kΩ IN CCO V = 0V, V =1.4V to 1.6V 5.0 – 25.9 kΩ IN CCO V = 0V, V = 1.14V to 1.26V 5.5 – 32.0 kΩ IN CCO I (2) Current through pull-down resistor at User V = V 0.10 – 0.75 mA RPD IN CCO I/O, Dual-Purpose, Input-only, and Dedicated pins R (2) Equivalent pull-down resistor value at User V = V = 3.0V to 3.465V 4.0 – 34.5 kΩ PD IN CCO I/O, Dual-Purpose, Input-only, and V = V = 2.3V to 2.7V 3.0 – 27.0 kΩ Dedicated pins (based on I per Note 2) IN CCO RPD V = V = 1.7V to 1.9V 2.3 – 19.0 kΩ IN CCO V = V = 1.4V to 1.6V 1.8 – 16.0 kΩ IN CCO V = V = 1.14V to 1.26V 1.5 – 12.6 kΩ IN CCO I V current per pin All V levels –10 – +10 μA REF REF CCO C Input capacitance – – – 10 pF IN R Resistance of optional differential V Min ≤ V ≤ V Max – 120 – Ω DT OCM ICM OCM termination circuit within a differential I/O V Min ≤ V ≤ V Max OD ID OD pair. Not available on Input-only pairs. V = 2.5V CCO Notes: 1. The numbers in this table are based on the conditions set forth in Table77. 2. This parameter is based on characterization. The pull-up resistance R = V / I . The pull-down resistance R =V /I . PU CCO RPU PD IN RPD 3. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage IN between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 118

Spartan-3E FPGA Family: DC and Switching Characteristics Quiescent Current Requirements Table 79: Quiescent Supply Current Characteristics Commercial Industrial Symbol Description Device Typical Units Maximum(1) Maximum(1) I Quiescent V supply current XC3S100E 8 27 36 mA CCINTQ CCINT XC3S250E 15 78 104 mA XC3S500E 25 106 145 mA XC3S1200E 50 259 324 mA XC3S1600E 65 366 457 mA I Quiescent V supply current XC3S100E 0.8 1.0 1.5 mA CCOQ CCO XC3S250E 0.8 1.0 1.5 mA XC3S500E 0.8 1.0 1.5 mA XC3S1200E 1.5 2.0 2.5 mA XC3S1600E 1.5 2.0 2.5 mA I Quiescent V supply current XC3S100E 8 12 13 mA CCAUXQ CCAUX XC3S250E 12 22 26 mA XC3S500E 18 31 34 mA XC3S1200E 35 52 59 mA XC3S1600E 45 76 86 mA Notes: 1. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. 2. The numbers in this table are based on the conditions set forth in Table77. 3. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices at room temperature (T of 25°C at V = 1.2 V, V = 3.3V, and V J CCINT CCO CCAUX = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with V = 1.26V, V = 3.465V, and V = 2.625V. The FPGA is programmed with a “blank” configuration data file (i.e., a CCINT CCO CCAUX design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements), measured quiescent current levels may be different than the values in the table. For more accurate estimates for a specific design, use the Xilinx® XPower tools. 4. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3E XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 119

Spartan-3E FPGA Family: DC and Switching Characteristics Single-Ended I/O Standards Table 80: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers(2) V V V (3) IOSTANDARD CCO REF IL IH Attribute Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V) LVTTL 3.0 3.3 3.465 0.8 2.0 LVCMOS33(4) 3.0 3.3 3.465 0.8 2.0 LVCMOS25(4,5) 2.3 2.5 2.7 0.7 1.7 LVCMOS18 1.65 1.8 1.95 V is not used for 0.4 0.8 REF LVCMOS15 1.4 1.5 1.6 these I/O standards 0.4 0.8 LVCMOS12 1.1 1.2 1.3 0.4 0.7 PCI33_3(6) 3.0 3.3 3.465 0.3• V 0.5• V CCO CCO PCI66_3(6) 3.0 3.3 3.465 0.3• V 0.5• V CCO CCO HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 V - 0.1 V + 0.1 REF REF HSTL_III_18 1.7 1.8 1.9 - 1.1 - V - 0.1 V + 0.1 REF REF SSTL18_I 1.7 1.8 1.9 0.833 0.900 0.969 V - 0.125 V + 0.125 REF REF SSTL2_I 2.3 2.5 2.7 1.15 1.25 1.35 V - 0.125 V + 0.125 REF REF Notes: 1. Descriptions of the symbols used in this table are as follows: V – the supply voltage for output drivers CCO V – the reference voltage for setting the input switching threshold REF V – the input voltage that indicates a Low logic level IL V – the input voltage that indicates a High logic level IH 2. The V rails supply only output drivers, not input circuits. CCO 3. For device operation, the maximum signal voltage (V max) may be as high as V max. See Table73. IH IN 4. There is approximately 100mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards. 5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V rail (2.5V). CCAUX The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V lines of Banks 0, 1, and 2 at power-on as well as throughout configuration. CCO 6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 120

Spartan-3E FPGA Family: DC and Switching Characteristics Table 81: DC Characteristics of User I/Os Using Table 81: DC Characteristics of User I/Os Using Single-Ended Standards Single-Ended Standards (Cont’d) Test Logic Level Test Logic Level IOSTANDARD Conditions Characteristics IOSTANDARD Conditions Characteristics Attribute IOL IOH VOL VOH Attribute IOL IOH VOL VOH (mA) (mA) Max (V) Min (V) (mA) (mA) Max (V) Min (V) LVTTL(3) 2 2 –2 0.4 2.4 SSTL2_I 8.1 –8.1 VTT – 0.61 VTT + 0.61 4 4 –4 Notes: 6 6 –6 1. The numbers in this table are based on the conditions set forth in Table77 and Table80. 8 8 –8 2. Descriptions of the symbols used in this table are as follows: I – the output current condition under which VOL is tested 12 12 –12 OL I – the output current condition under which VOH is tested OH 16 16 –16 VOL – the output voltage that indicates a Low logic level V – the output voltage that indicates a High logic level OH LVCMOS33(3) 2 2 –2 0.4 VCCO – 0.4 VCCO – the supply voltage for output drivers V – the voltage applied to a resistor termination 4 4 –4 TT 3. For the LVCMOS and LVTTL standards: the same V and V OL OH 6 6 –6 limits apply for both the Fast and Slow slew attributes. 4. Tested according to the relevant PCI specifications. For 8 8 –8 information on PCI IP solutions, see www.xilinx.com/pci. The PCIX IOSTANDARD is available and has equivalent 12 12 –12 characteristics but no PCI-X IP is supported. 16 16 –16 LVCMOS25(3) 2 2 –2 0.4 VCCO – 0.4 4 4 –4 6 6 –6 8 8 –8 12 12 –12 LVCMOS18(3) 2 2 –2 0.4 VCCO – 0.4 4 4 –4 6 6 –6 8 8 –8 LVCMOS15(3) 2 2 –2 0.4 V – 0.4 CCO 4 4 –4 6 6 –6 LVCMOS12(3) 2 2 –2 0.4 V – 0.4 CCO PCI33_3(4) 1.5 –0.5 10% V 90% V CCO CCO PCI66_3(4) 1.5 –0.5 10% V 90% V CCO CCO HSTL_I_18 8 –8 0.4 V – 0.4 CCO HSTL_III_18 24 –8 0.4 V – 0.4 CCO SSTL18_I 6.7 –6.7 V – 0.475 V + 0.475 TT TT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 121

Spartan-3E FPGA Family: DC and Switching Characteristics Differential I/O Standards X-Ref Target - Figure 69 V INP P Differential Internal N I/O Pair Pins V Logic INN V INN 50% V V ID INP V ICM GND level V +V V = Input common mode voltage = INP INN ICM 2 VID= Differential input voltage = VINP - VINN DS099-3_01_012304 Figure 69: Differential Input Voltages Table 82: Recommended Operating Conditions for User I/Os Using Differential Signal Standards IOSTANDARD VCCO for Drivers(1) VID VICM Attribute Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V) Nom (V) Max (V) LVDS_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 BLVDS_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 MINI_LVDS_25 2.375 2.50 2.625 200 - 600 0.30 - 2.2 LVPECL_25(2) Inputs Only 100 800 1000 0.5 1.2 2.0 RSDS_25 2.375 2.50 2.625 100 200 - 0.3 1.20 1.4 DIFF_HSTL_I_18 1.7 1.8 1.9 100 - - 0.8 - 1.1 DIFF_HSTL_III_18 1.7 1.8 1.9 100 - - 0.8 - 1.1 DIFF_SSTL18_I 1.7 1.8 1.9 100 - - 0.7 - 1.1 DIFF_SSTL2_I 2.3 2.5 2.7 100 - - 1.0 - 1.5 Notes: 1. The V rails supply only differential output drivers, not input circuits. CCO 2. V inputs are not used for any of the differential I/O standards. REF DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 122

Spartan-3E FPGA Family: DC and Switching Characteristics X-Ref Target - Figure 70 V OUTP P Differential Internal N I/O Pair Pins V Logic OUTN V V OH OUTN 50% V V OD OUTP V V OL OCM GND level V +V OUTP OUTN V = Output common mode voltage = OCM 2 VOD= Output differential voltage = VOUTP - VOUTN V = Output voltage indicating a High logic level OH V = Output voltage indicating a Low logic level OL DS312-3_03_021505 Figure 70: Differential Output Voltages Table 83: DC Characteristics of User I/Os Using Differential Signal Standards V ΔV V ΔV V V OD OD OCM OCM OH OL IOSTANDARD Attribute Min Typ Max Min Max Min Typ Max Min Max Min Max (mV) (mV) (mV) (mV) (mV) (V) (V) (V) (mV) (mV) (V) (V) LVDS_25 250 350 450 – – 1.125 – 1.375 – – – – BLVDS_25 250 350 450 – – – 1.20 – – – – – MINI_LVDS_25 300 – 600 – 50 1.0 – 1.4 – 50 – – RSDS_25 100 – 400 – – 1.1 – 1.4 – – – – DIFF_HSTL_I_18 – – – – – – – – – – V – 0.4 0.4 CCO DIFF_HSTL_III_18 – – – – – – – – – – V – 0.4 0.4 CCO DIFF_SSTL18_I – – – – – – – – – – V + 0.475 V – 0.475 TT TT DIFF_SSTL2_I – – – – – – – – – – V + 0.61 V – 0.61 TT TT Notes: 1. The numbers in this table are based on the conditions set forth in Table77 and Table82. 2. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ω across the N and P pins of the T differential signal pair. The exception is for BLVDS, shown in Figure71. 3. At any given time, no more than two of the following differential output standards may be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25 X-Ref Target - Figure 71 1/4th of Bourns 1/4th of Bourns Part Number Part Number CAT16-LV4F12 CAT16-PT4F4 VCCO = 2.5V 165Ω Z0 = 50Ω VCCO = 2.5V FPGA 140Ω 100Ω FPGA Out Z0 = 50Ω In 165Ω ds312-3_07_041108 Figure 71: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 123

Spartan-3E FPGA Family: DC and Switching Characteristics Switching Characteristics All Spartan-3E FPGAs ship in two speed grades: -4 and the Timing parameters and their representative values are higher performance -5. Switching characteristics in this selected for inclusion below either because they are document may be designated as Advance, Preliminary, or important as general design requirements or they indicate Production, as shown in Table84. Each category is defined fundamental device performance characteristics. The as follows: Spartan-3E speed files (v1.27), part of the Xilinx Development Software, are the original source for many but Advance: These specifications are based on simulations not all of the values. The speed grade designations for only and are typically available soon after establishing these files are shown in Table84. For more complete, more FPGA specifications. Although speed grades with this precise, and worst-case data, use the values reported by designation are considered relatively stable and the Xilinx static timing analyzer (TRACE in the Xilinx conservative, some under-reporting might still occur. development software) and back-annotated to the Preliminary: These specifications are based on complete simulation netlist. early silicon characterization. Devices and speed grades Table 84: Spartan-3E v1.27 Speed Grade Designations with this designation are intended to give a better indication of the expected performance of production silicon. The Device Advance Preliminary Production probability of under-reporting preliminary delays is greatly XC3S100E -MIN, -4, -5 reduced compared to Advance data. XC3S250E -MIN, -4, -5 Production: These specifications are approved once XC3S500E -MIN, -4, -5 enough production silicon of a particular device family member has been characterized to provide full correlation XC3S1200E -MIN, -4, -5 between speed files and devices over numerous production XC3S1600E -MIN, -4, -5 lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Table85 provides the history of the Spartan-3E speed files Typically, the slowest speed grades transition to Production since all devices reached Production status. before faster speed grades. Table 85: Spartan-3E Speed File Version History Software Version Requirements ISE Version Description Release Production-quality systems must use FPGA designs 1.27 9.2.03i Added XA Automotive. compiled using a speed file designated as PRODUCTION status. FPGAs designs using a less mature speed file 1.26 8.2.02i Added -0/-MIN speed grade, which designation should only be used during system prototyping includes minimum values. or pre-production qualification. FPGA designs with speed 1.25 8.2.01i Added XA Automotive devices to speed files designated as Advance or Preliminary should not be file. Improved model for left and right used in a production-quality system. DCMs. 1.23 8.2i Updated input setup/hold values based Whenever a speed file designation changes, as a device on default IFD_DELAY_VALUE matures toward Production status, rerun the latest Xilinx settings. ISE software on the FPGA design to ensure that the FPGA 1.21 8.1.03i All Spartan-3E FPGAs and all speed design incorporates the latest timing information and grades elevated to Production status. software updates. All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the published parameter values apply to all Spartan-3E devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades. Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. Sign Up for Alerts on Xilinx.com https://secure.xilinx.com/webreg/register.do ?group=myprofile&languageID=1 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 124

Spartan-3E FPGA Family: DC and Switching Characteristics I/O Timing Table 86: Pin-to-Pin Clock-to-Output Times for the IOB Output Path Speed Grade Symbol Description Conditions Device -5 -4 Units Max(2) Max(2) Clock-to-Output Times T When reading from the Output Flip-Flop LVCMOS25(3), 12mA XC3S100E 2.66 2.79 ns ICKOFDCM (OFF), the time from the active transition output drive, Fast slew on the Global Clock pin to data appearing rate, with DCM(4) XC3S250E 3.00 3.45 ns at the Output pin. The DCM is used. XC3S500E 3.01 3.46 ns XC3S1200E 3.01 3.46 ns XC3S1600E 3.00 3.45 ns T When reading from OFF, the time from the LVCMOS25(3), 12mA XC3S100E 5.60 5.92 ns ICKOF active transition on the Global Clock pin to output drive, Fast slew XC3S250E 4.91 5.43 ns data appearing at the Output pin. The rate, without DCM DCM is not used. XC3S500E 4.98 5.51 ns XC3S1200E 5.36 5.94 ns XC3S1600E 5.45 6.05 ns Notes: 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions set forth in Table77 and Table80. 2. For minimums, use the values reported by the Xilinx timing analyzer. 3. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Table91. If the latter is true, add the appropriate Output adjustment from Table94. 4. DCM output jitter is included in all measurements. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 125

Spartan-3E FPGA Family: DC and Switching Characteristics Table 87: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous) Speed Grade IFD_ Symbol Description Conditions DELAY_ Device -5 -4 Units VALUE= Min Min Setup Times T When writing to the Input LVCMOS25(2), 0 XC3S100E 2.65 2.98 ns PSDCM Flip-Flop (IFF), the time from the IFD_DELAY_VALUE = 0, setup of data at the Input pin to with DCM(3) XC3S250E 2.25 2.59 ns the active transition at a Global XC3S500E 2.25 2.59 ns Clock pin. The DCM is used. No Input Delay is programmed. XC3S1200E 2.25 2.58 ns XC3S1600E 2.25 2.59 ns T When writing to IFF, the time LVCMOS25(2), 2 XC3S100E 3.16 3.58 ns PSFD from the setup of data at the IFD_DELAY_VALUE = 3 XC3S250E 3.44 3.91 ns Input pin to an active transition at default software setting the Global Clock pin. The DCM is 3 XC3S500E 4.00 4.73 ns not used. The Input Delay is programmed. 3 XC3S1200E 2.60 3.31 ns 3 XC3S1600E 3.33 3.77 ns Hold Times T When writing to IFF, the time LVCMOS25(4), 0 XC3S100E –0.54 –0.52 ns PHDCM from the active transition at the IFD_DELAY_VALUE = 0, Global Clock pin to the point with DCM(3) XC3S250E 0.06 0.14 ns when data must be held at the XC3S500E 0.07 0.14 ns Input pin. The DCM is used. No Input Delay is programmed. XC3S1200E 0.07 0.15 ns XC3S1600E 0.06 0.14 ns T When writing to IFF, the time LVCMOS25(4), 2 XC3S100E –0.31 –0.24 ns PHFD from the active transition at the IFD_DELAY_VALUE = 3 XC3S250E –0.32 –0.32 ns Global Clock pin to the point default software setting when data must be held at the 3 XC3S500E –0.77 –0.77 ns Input pin. The DCM is not used. The Input Delay is programmed. 3 XC3S1200E 0.13 0.16 ns 3 XC3S1600E –0.05 –0.03 ns Notes: 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions set forth in Table77 and Table80. 2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table91. If this is true of the data Input, add the appropriate Input adjustment from the same table. 3. DCM output jitter is included in all measurements. 4. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table91. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active edge. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 126

Spartan-3E FPGA Family: DC and Switching Characteristics Table 88: Setup and Hold Times for the IOB Input Path Speed Grade IFD_ Symbol Description Conditions DELAY_ Device -5 -4 Units VALUE= Min Min Setup Times T Time from the setup of data at LVCMOS25(2), 0 All 1.84 2.12 ns IOPICK the Input pin to the active IFD_DELAY_VALUE = 0 transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed. T Time from the setup of data at LVCMOS25(2), 2 XC3S100E 6.12 7.01 ns IOPICKD the Input pin to the active IFD_DELAY_VALUE = 3 All Others 6.76 7.72 transition at the IFF’s ICLK input. default software setting The Input Delay is programmed. Hold Times T Time from the active transition at LVCMOS25(3), 0 All –0.76 –0.76 ns IOICKP the IFF’s ICLK input to the point IFD_DELAY_VALUE = 0 where data must be held at the Input pin. No Input Delay is programmed. T Time from the active transition at LVCMOS25(3), 2 XC3S100E –3.93 –3.93 ns IOICKPD the IFF’s ICLK input to the point IFD_DELAY_VALUE = 3 All Others –3.50 –3.50 where data must be held at the default software setting Input pin. The Input Delay is programmed. Set/Reset Pulse Width T Minimum pulse width to SR All 1.57 1.80 ns RPW_IOB control input on IOB Notes: 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions set forth in Table77 and Table80. 2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Table91. 3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Table91. When the hold time is negative, it is possible to change the data before the clock’s active edge. Table 89: Sample Window (Source Synchronous) Symbol Description Max Units T Setup and hold capture window of an The input capture sample window value is highly specific to a particular ps SAMP IOB input flip-flop application, device, package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the appropriate Xilinx application note for application-specific values. (cid:129) XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 127

Spartan-3E FPGA Family: DC and Switching Characteristics Table 90: Propagation Times for the IOB Input Path Speed Grade IFD_ Symbol Description Conditions DELAY_ Device -5 -4 Units VALUE= Min Min Propagation Times T The time it takes for data to travel LVCMOS25(2), 0 All 1.96 2.25 ns IOPLI from the Input pin through the IFD_DELAY_VALUE = 0 IFF latch to the I output with no input delay programmed T The time it takes for data to travel LVCMOS25(2), 2 XC3S100E 5.40 5.97 ns IOPLID from the Input pin through the IFD_DELAY_VALUE = 3 All Others 6.30 7.20 IFF latch to the I output with the default software setting input delay programmed Notes: 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions set forth in Table77 and Table80. 2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Table91. Table 91: Input Timing Adjustments by IOSTANDARD Table 91: Input Timing Adjustments by IOSTANDARD (Cont’d) Add the Add the Convert Input Time from Adjustment Below Convert Input Time from Adjustment Below LVCMOS25 to the Units LVCMOS25 to the Units Following Signal Standard Speed Grade Following Signal Standard Speed Grade (IOSTANDARD) (IOSTANDARD) -5 -4 -5 -4 Single-Ended Standards Differential Standards LVTTL 0.42 0.43 ns LVDS_25 0.48 0.49 ns LVCMOS33 0.42 0.43 ns BLVDS_25 0.39 0.39 ns LVCMOS25 0 0 ns MINI_LVDS_25 0.48 0.49 ns LVCMOS18 0.96 0.98 ns LVPECL_25 0.27 0.27 ns LVCMOS15 0.62 0.63 ns RSDS_25 0.48 0.49 ns LVCMOS12 0.26 0.27 ns DIFF_HSTL_I_18 0.48 0.49 ns PCI33_3 0.41 0.42 ns DIFF_HSTL_III_18 0.48 0.49 ns PCI66_3 0.41 0.42 ns DIFF_SSTL18_I 0.30 0.30 ns HSTL_I_18 0.12 0.12 ns DIFF_SSTL2_I 0.32 0.32 ns HSTL_III_18 0.17 0.17 ns Notes: SSTL18_I 0.30 0.30 ns 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions SSTL2_I 0.15 0.15 ns set forth in Table77, Table80, and Table82. 2. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 128

Spartan-3E FPGA Family: DC and Switching Characteristics Table 92: Timing for the IOB Output Path Speed Grade Symbol Description Conditions Device -5 -4 Units Min Min Clock-to-Output Times T When reading from the Output Flip-Flop (OFF), the LVCMOS25(2), All 2.18 2.50 ns IOCKP time from the active transition at the OCLK input to 12mA output drive, data appearing at the Output pin Fast slew rate Propagation Times T The time it takes for data to travel from the IOB’s O LVCMOS25(2), All 2.24 2.58 ns IOOP input to the Output pin 12mA output drive, Fast slew rate T The time it takes for data to travel from the O input 2.32 2.67 ns IOOLP through the OFF latch to the Output pin Set/Reset Times T Time from asserting the OFF’s SR input to LVCMOS25(2), All 3.27 3.76 ns IOSRP setting/resetting data at the Output pin 12mA output drive, Fast slew rate T Time from asserting the Global Set Reset (GSR) 8.40 9.65 ns IOGSRQ input on the STARTUP_SPARTAN3E primitive to setting/resetting data at the Output pin Notes: 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions set forth in Table77 and Table80. 2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table94. 3. For minimum delays use the values reported by the Timing Analyzer. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 129

Spartan-3E FPGA Family: DC and Switching Characteristics Table 93: Timing for the IOB Three-State Path Speed Grade Symbol Description Conditions Device -5 -4 Units Max Max Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK input LVCMOS25, 12mA All 1.49 1.71 ns IOCKHZ of the Three-state Flip-Flop (TFF) to when the output drive, Fast Output pin enters the high-impedance state slew rate T (2) Time from the active transition at TFF’s OTCLK All 2.70 3.10 ns IOCKON input to when the Output pin drives valid data Asynchronous Output Enable/Disable Times T Time from asserting the Global Three State (GTS) LVCMOS25, 12mA All 8.52 9.79 ns GTS input on the STARTUP_SPARTAN3E primitive to output drive, Fast when the Output pin enters the high-impedance slew rate state Set/Reset Times T Time from asserting TFF’s SR input to when the LVCMOS25, 12mA All 2.11 2.43 ns IOSRHZ Output pin enters a high-impedance state output drive, Fast slew rate T (2) Time from asserting TFF’s SR input at TFF to when All 3.32 3.82 ns IOSRON the Output pin drives valid data Notes: 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions set forth in Table77 and Table80. 2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table94. 3. For minimum delays use the values reported by the Timing Analyzer. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 130

Spartan-3E FPGA Family: DC and Switching Characteristics Table 94: Output Timing Adjustments for IOB Table 94: Output Timing Adjustments for IOB (Cont’d) Add the Add the Convert Output Time from Adjustment Convert Output Time from Adjustment LSFViagCsntMa SlO lSeSwt2a 5nR dwaatiterhd t 1o(I2 OtmhSeAT F ADoNrlilDvoeAw aRinnDgd) SpeBeedl oGwrade Units LSFViagCsntM aSlO lSeSwt2a 5nR dwaatiterhd t 1o(I2 OtmhSeAT F ADoNrlilDvoeAw aRinnDgd) SpeBeedl oGwrade Units -5 -4 -5 -4 Single-Ended Standards LVCMOS18 Slow 2mA 5.03 5.24 ns LVTTL Slow 2mA 5.20 5.41 ns 4mA 3.08 3.21 ns 4mA 2.32 2.41 ns 6mA 2.39 2.49 ns 6mA 1.83 1.90 ns 8mA 1.83 1.90 ns 8mA 0.64 0.67 ns Fast 2mA 3.98 4.15 ns 12mA 0.68 0.70 ns 4mA 2.04 2.13 ns 16mA 0.41 0.43 ns 6mA 1.09 1.14 ns Fast 2mA 4.80 5.00 ns 8mA 0.72 0.75 ns 4mA 1.88 1.96 ns LVCMOS15 Slow 2mA 4.49 4.68 ns 6mA 1.39 1.45 ns 4mA 3.81 3.97 ns 8mA 0.32 0.34 ns 6mA 2.99 3.11 ns 12mA 0.28 0.30 ns Fast 2mA 3.25 3.38 ns 16mA 0.28 0.30 ns 4mA 2.59 2.70 ns LVCMOS33 Slow 2mA 5.08 5.29 ns 6mA 1.47 1.53 ns 4mA 1.82 1.89 ns LVCMOS12 Slow 2mA 6.36 6.63 ns 6mA 1.00 1.04 ns Fast 2mA 4.26 4.44 ns 8mA 0.66 0.69 ns HSTL_I_18 0.33 0.34 ns 12mA 0.40 0.42 ns HSTL_III_18 0.53 0.55 ns 16mA 0.41 0.43 ns PCI33_3 0.44 0.46 ns Fast 2mA 4.68 4.87 ns PCI66_3 0.44 0.46 ns 4mA 1.46 1.52 ns SSTL18_I 0.24 0.25 ns 6mA 0.38 0.39 ns SSTL2_I –0.20 –0.20 ns 8mA 0.33 0.34 ns Differential Standards 12mA 0.28 0.30 ns LVDS_25 –0.55 –0.55 ns 16mA 0.28 0.30 ns BLVDS_25 0.04 0.04 ns LVCMOS25 Slow 2mA 4.04 4.21 ns MINI_LVDS_25 –0.56 –0.56 ns 4mA 2.17 2.26 ns LVPECL_25 Input Only ns 6mA 1.46 1.52 ns RSDS_25 –0.48 –0.48 ns 8mA 1.04 1.08 ns DIFF_HSTL_I_18 0.42 0.42 ns 12mA 0.65 0.68 ns DIFF_HSTL_III_18 0.53 0.55 ns Fast 2mA 3.53 3.67 ns DIFF_SSTL18_I 0.40 0.40 ns 4mA 1.65 1.72 ns DIFF_SSTL2_I 0.44 0.44 ns 6mA 0.44 0.46 ns Notes: 8mA 0.20 0.21 ns 1. The numbers in this table are tested using the methodology presented in Table95 and are based on the operating conditions 12mA 0 0 ns set forth in Table77, Table80, and Table82. 2. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 131

Spartan-3E FPGA Family: DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable LVCMOS, LVTTL), then R is set to 1MΩ to indicate an open T I/Os, different signal standards call for different test connection, and V is set to zero. The same measurement T conditions. Table95 lists the conditions to use for each point (V ) that was used at the Input is also used at the M standard. Output. The method for measuring Input timing is as follows: A X-Ref Target - Figure 72 signal that swings between a Low logic level of V and a V (V ) L T REF High logic level of V is applied to the Input under test. H Some standards also require the application of a bias FPGA Output R (R ) T REF voltage to the V pins of a given bank to properly set the REF input-switching threshold. The measurement point of the V (V ) M MEAS Input signal (V ) is commonly located halfway between V M L and VH. CL (CREF) The Output test setup is shown in Figure72. A termination voltage VT is applied to the termination resistor RT, the other ds312-3_04_090105 end of which is connected to the Output. For each standard, Notes: RT and VT generally take on the standard values 1. The names shown in parentheses are recommended for minimizing signal reflections. If the used in the IBIS file. standard does not ordinarily use terminations (e.g., Figure 72: Output Test Setup Table 95: Test Methods for Timing Measurement at I/Os Inputs and Inputs Outputs Signal Standard Outputs (IOSTANDARD) V (V) V (V) V (V) R (Ω) V (V) V (V) REF L H T T M Single-Ended LVTTL - 0 3.3 1M 0 1.4 LVCMOS33 - 0 3.3 1M 0 1.65 LVCMOS25 - 0 2.5 1M 0 1.25 LVCMOS18 - 0 1.8 1M 0 0.9 LVCMOS15 - 0 1.5 1M 0 0.75 LVCMOS12 - 0 1.2 1M 0 0.6 PCI33_3 Rising - Note 3 Note 3 25 0 0.94 Falling 25 3.3 2.03 PCI66_3 Rising - Note 3 Note 3 25 0 0.94 Falling 25 3.3 2.03 HSTL_I_18 0.9 V – 0.5 V + 0.5 50 0.9 V REF REF REF HSTL_III_18 1.1 V – 0.5 V + 0.5 50 1.8 V REF REF REF SSTL18_I 0.9 V – 0.5 V + 0.5 50 0.9 V REF REF REF SSTL2_I 1.25 V – 0.75 V + 0.75 50 1.25 V REF REF REF Differential LVDS_25 - V – 0.125 V + 0.125 50 1.2 V ICM ICM ICM BLVDS_25 - V – 0.125 V + 0.125 1M 0 V ICM ICM ICM MINI_LVDS_25 - V – 0.125 V + 0.125 50 1.2 V ICM ICM ICM LVPECL_25 - V – 0.3 V + 0.3 1M 0 V ICM ICM ICM RSDS_25 - V – 0.1 V + 0.1 50 1.2 V ICM ICM ICM DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 132

Spartan-3E FPGA Family: DC and Switching Characteristics Table 95: Test Methods for Timing Measurement at I/Os (Cont’d) Inputs and Inputs Outputs Signal Standard Outputs (IOSTANDARD) V (V) V (V) V (V) R (Ω) V (V) V (V) REF L H T T M DIFF_HSTL_I_18 - V – 0.5 V + 0.5 50 0.9 V REF REF ICM DIFF_HSTL_III_18 - V – 0.5 V + 0.5 50 1.8 V REF REF ICM DIFF_SSTL18_I - V – 0.5 V + 0.5 50 0.9 V REF REF ICM DIFF_SSTL2_I - V – 0.5 V + 0.5 50 1.25 V REF REF ICM Notes: 1. Descriptions of the relevant symbols are as follows: V – The reference voltage for setting the input switching threshold REF V – The common mode input voltage ICM V – Voltage of measurement point on signal transition M V – Low-level test voltage at Input pin L V – High-level test voltage at Input pin H R – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required T V – Termination voltage T 2. The load capacitance (C ) at the Output pin is 0 pF for all signal standards. L 3. According to the PCI specification. The capacitive load (C ) is connected between the output Delays for a given application are simulated according to its L and GND. The Output timing for all standards, as published specific load conditions as follows: in the speed files and the data sheet, is always based on a 1. Simulate the desired signal standard with the output C value of zero. High-impedance probes (less than 1 pF) L driver connected to the test setup shown in Figure72. are used for all measurements. Any delay that the test Use parameter values V , R , and V from Table95. fixture might contribute to test measurements is subtracted T T M C is zero. from those measurements to produce the final timing REF numbers as published in the speed files and data sheet. 2. Record the time to VM. 3. Simulate the same signal standard with the output Using IBIS Models to Simulate Load driver connected to the PCB trace with load. Use the Conditions in Application appropriate IBIS model (including VREF, RREF, CREF, and V values) or capacitive value to represent the MEAS IBIS models permit the most accurate prediction of timing load. delays for a given application. The parameters found in the 4. Record the time to V . IBIS model (V , R , and V ) correspond directly MEAS REF REF MEAS with the parameters used in Table95 (V , R , and V ). Do 5. Compare the results of steps 2 and 4. Add (or subtract) T T M the increase (or decrease) in delay to (or from) the not confuse V (the termination voltage) from the IBIS REF appropriate Output standard adjustment (Table94) to model with V (the input-switching threshold) from the REF yield the worst-case delay of the PCB trace. table. A fourth parameter, C , is always zero. The four REF parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link: http://www.xilinx.com/support/download/index.htm DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 133

Spartan-3E FPGA Family: DC and Switching Characteristics Simultaneously Switching Output Guidelines This section provides guidelines for the recommended equivalent number of pairs is based on characterization and maximum allowable number of Simultaneous Switching might not match the physical number of pairs. For each Outputs (SSOs). These guidelines describe the maximum output signal standard and drive strength, Table97 number of user I/O pins of a given output signal standard recommends the maximum number of SSOs, switching in that should simultaneously switch in the same direction, the same direction, allowed per V /GND pair within an CCO while maintaining a safe level of switching noise. Meeting I/O bank. The guidelines in Table97 are categorized by these guidelines for the stated test conditions ensures that package style. Multiply the appropriate numbers from the FPGA operates free from the adverse effects of ground Table96 and Table97 to calculate the maximum number of and power bounce. SSOs allowed within an I/O bank. Exceeding these SSO guidelines might result in increased power or ground Ground or power bounce occurs when a large number of bounce, degraded signal integrity, or increased system jitter. outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common SSO /IO Bank = Table96 x Table97 MAX voltage rail. Low-to-High transitions conduct to the V CCO The recommended maximum SSO values assumes that the rail; High-to-Low transitions conduct to the GND rail. The FPGA is soldered on the printed circuit board and that the resulting cumulative current transient induces a voltage board uses sound design practices. The SSO values do not difference across the inductance that exists between the die apply for FPGAs mounted in sockets, due to the lead pad and the power supply or ground return. The inductance inductance introduced by the socket. is associated with bonding wires, the package lead frame, and any other signal routing inside the package. Other The number of SSOs allowed for quad-flat packages (VQ, variables contribute to SSO noise levels, including stray TQ, PQ) is lower than for ball grid array packages (FG) due inductance on the PCB as well as capacitive loading at to the larger lead inductance of the quad-flat packages. The receivers. Any SSO-induced voltage consequently affects results for chip-scale packaging (CP132) are better than internal switching noise margins and ultimately signal quad-flat packaging but not as high as for ball grid array quality. packaging. Ball grid array packages are recommended for applications with a large number of simultaneously Table96 and Table97 provide the essential SSO switching outputs. guidelines. For each device/package combination, Table96 provides the number of equivalent V /GND pairs. The CCO Table 96: Equivalent V /GND Pairs per Bank CCO Package Style (including Pb-free) Device VQ100 CP132 TQ144 PQ208 FT256 FG320 FG400 FG484 XC3S100E 2 2 2 - - - - - XC3S250E 2 2 2 3 4 - - - XC3S500E 2 2 - 3 4 5 - - XC3S1200E - - - - 4 5 6 - XC3S1600E - - - - - 5 6 7 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 134

Spartan-3E FPGA Family: DC and Switching Characteristics Table 97: Recommended Number of Simultaneously Table 97: Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair Switching Outputs per VCCO/GND Pair (Cont’d) Package Type Package Type Signal Standard FT256 Signal Standard FT256 (IOSTANDARD) VQ TQ PQ CP FG320 (IOSTANDARD) VQ TQ PQ CP FG320 100 144 208 132 FG400 100 144 208 132 FG400 FG484 FG484 Single-Ended Standards LVCMOS15 Slow 2 16 10 10 19 55 LVTTL Slow 2 34 20 19 52 60 4 8 7 7 9 31 4 17 10 10 26 41 6 6 5 5 9 18 6 17 10 7 26 29 Fast 2 9 9 9 13 25 8 8 6 6 13 22 4 7 7 7 7 16 12 8 6 5 13 13 6 5 5 5 5 13 16 5 5 5 6 11 LVCMOS12 Slow 2 17 11 11 16 55 Fast 2 17 17 17 26 34 Fast 2 10 10 10 10 31 4 9 9 9 13 20 PCI33_3 8 8 8 16 16 6 7 7 7 13 15 PCI66_3 8 8 8 13 13 8 6 6 6 6 12 PCIX 7 7 7 11 11 12 5 5 5 6 10 HSTL_I_18 10 10 10 16 17 16 5 5 5 5 9 HSTL_III_18 10 10 10 16 16 LVCMOS33 Slow 2 34 20 20 52 76 SSTL18_I 9 9 9 15 15 4 17 10 10 26 46 SSTL2_I 12 12 12 18 18 6 17 10 7 26 27 Differential Standards (Number of I/O Pairs or Channels) 8 8 6 6 13 20 LVDS_25 6 6 6 12 20 12 8 6 5 13 13 BLVDS_25 4 4 4 4 4 16 5 5 5 6 10 MINI_LVDS_25 6 6 6 12 20 Fast 2 17 17 17 26 44 LVPECL_25 Input Only 4 8 8 8 13 26 RSDS_25 6 6 6 12 20 6 8 6 6 13 16 DIFF_HSTL_I_18 5 5 5 8 8 8 6 6 6 6 12 DIFF_HSTL_IIII_18 5 5 5 8 8 12 5 5 5 6 10 DIFF_SSTL18_I 4 4 4 7 7 16 8 8 5 5 8 DIFF_SSTL2_I 6 6 6 9 8 LVCMOS25 Slow 2 28 16 16 42 76 Notes: 4 13 10 10 19 46 1. The numbers in this table are recommendations that assume sound board layout practice. This table assumes the following 6 13 7 7 19 33 parasitic factors: combined PCB trace and land inductance per 8 6 6 6 9 24 VCCO and GND pin of 1.0 nH, receiver capacitive load of 15 pF. Test limits are the VIL/VIH voltage limits for the respective I/O 12 6 6 6 9 18 standard. Fast 2 17 16 16 26 42 2. The PQ208 results are based on physical measurements of a PQ208 package soldered to a typical printed circuit board. All 4 9 9 9 13 20 other results are based on worst-case simulation and an 6 9 7 7 13 15 interpolation of the PQ208 physical results. 8 6 6 6 6 13 3. If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689: Managing Ground Bounce in Large 12 5 5 5 6 11 FPGAs for information on how to perform weighted average SSO LVCMOS18 Slow 2 19 11 8 29 64 calculations. 4 13 7 6 19 34 6 6 5 5 9 22 8 6 4 4 9 18 Fast 2 13 8 8 19 36 4 8 5 5 13 21 6 4 4 4 6 13 8 4 4 4 6 10 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 135

Spartan-3E FPGA Family: DC and Switching Characteristics Configurable Logic Block (CLB) Timing Table 98: CLB (SLICEM) Timing Speed Grade Symbol Description -5 -4 Units Min Max Min Max Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time CKO from the active transition at the CLK input to data - 0.52 - 0.60 ns appearing at the XQ (YQ) output Setup Times T Time from the setup of data at the F or G input to the AS 0.46 - 0.52 - ns active transition at the CLK input of the CLB T Time from the setup of data at the BX or BY input to DICK 1.58 - 1.81 - ns the active transition at the CLK input of the CLB Hold Times T Time from the active transition at the CLK input to the AH 0 - 0 - ns point where data is last held at the F or G input T Time from the active transition at the CLK input to the CKDI 0 - 0 - ns point where data is last held at the BX or BY input Clock Timing T The High pulse width of the CLB’s CLK signal 0.70 - 0.80 - ns CH T The Low pulse width of the CLK signal 0.70 - 0.80 - ns CL F Toggle frequency (for export control) 0 657 0 572 MHz TOG Propagation Times T The time it takes for data to travel from the CLB’s F ILO - 0.66 - 0.76 ns (G) input to the X (Y) output Set/Reset Pulse Width T The minimum allowable pulse width, High or Low, to RPW_CLB 1.57 - 1.80 - ns the CLB’s SR input Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 136

Spartan-3E FPGA Family: DC and Switching Characteristics Table 99: CLB Distributed RAM Switching Characteristics -5 -4 Symbol Description Units Min Max Min Max Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on SHCKO - 2.05 - 2.35 ns the distributed RAM output Setup Times T Setup time of data at the BX or BY input before the active DS 0.40 - 0.46 - ns transition at the CLK input of the distributed RAM T Setup time of the F/G address inputs before the active transition AS 0.46 - 0.52 - ns at the CLK input of the distributed RAM T Setup time of the write enable input before the active transition at WS 0.34 - 0.40 - ns the CLK input of the distributed RAM Hold Times T Hold time of the BX, BY data inputs after the active transition at DH 0.13 - 0.15 - ns the CLK input of the distributed RAM T T Hold time of the F/G address inputs or the write enable input after AH, WH 0 - 0 - ns the active transition at the CLK input of the distributed RAM Clock Pulse Width T , T Minimum High or Low pulse width at CLK input 0.88 - 1.01 - ns WPH WPL Table 100: CLB Shift Register Switching Characteristics -5 -4 Symbol Description Units Min Max Min Max Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on REG - 3.62 - 4.16 ns the shift register output Setup Times T Setup time of data at the BX or BY input before the active SRLDS 0.41 - 0.46 - ns transition at the CLK input of the shift register Hold Times T Hold time of the BX or BY data input after the active transition at SRLDH 0.14 - 0.16 - ns the CLK input of the shift register Clock Pulse Width T , T Minimum High or Low pulse width at CLK input 0.88 - 1.01 - ns WPH WPL Clock Buffer/Multiplexer Switching Characteristics Table 101: Clock Distribution Switching Characteristics Maximum Description Symbol Speed Grade Units -5 -4 Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay T 1.46 1.46 ns GIO Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same T 0.55 0.63 ns as BUFGCE enable CE-input GSI Frequency of signals distributed on global buffers (all sides) F 333 311 MHz BUFG DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 137

Spartan-3E FPGA Family: DC and Switching Characteristics 18 x 18 Embedded Multiplier Timing Table 102: 18 x 18 Embedded Multiplier Timing Speed Grade Symbol Description -5 -4 Units Min Max Min Max Combinatorial Delay T Combinatorial multiplier propagation delay from the A and B inputs MULT to the P outputs, assuming 18-bit inputs and a 36-bit product - 4.34(1) - 4.88(1) ns (AREG, BREG, and PREG registers unused) Clock-to-Output Times T Clock-to-output delay from the active transition of the CLK input to MSCKP_P valid data appearing on the P outputs when using the PREG - 0.98 - 1.10 ns register(2) T Clock-to-output delay from the active transition of the CLK input to MSCKP_A T valid data appearing on the P outputs when using either the AREG - 4.42 - 4.97 ns MSCKP_B or BREG register(3) Setup Times T Data setup time at the A or B input before the active transition at the MSDCK_P CLK when using only the PREG output register (AREG, BREG 3.54 - 3.98 - ns registers unused)(2) T Data setup time at the A input before the active transition at the MSDCK_A 0.20 - 0.23 - ns CLK when using the AREG input register(3) T Data setup time at the B input before the active transition at the MSDCK_B 0.35 - 0.39 - ns CLK when using the BREG input register(3) Hold Times T Data hold time at the A or B input after the active transition at the MSCKD_P CLK when using only the PREG output register (AREG, BREG –0.97 - –0.97 - ns registers unused)(2) T Data hold time at the A input after the active transition at the CLK MSCKD_A 0.03 - 0.04 - ns when using the AREG input register(3) T Data hold time at the B input after the active transition at the CLK MSCKD_B 0.04 - 0.05 - ns when using the BREG input register(3) Clock Frequency F Internal operating frequency for a two-stage 18x18 multiplier using MULT the AREG and BREG input registers and the PREG output 0 270 0 240 MHz register(1) Notes: 1. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. 2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations. 3. Input registers AREG or BREG are typically used when inferring a two-stage multiplier. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 138

Spartan-3E FPGA Family: DC and Switching Characteristics Block RAM Timing Table 103: Block RAM Timing Speed Grade Symbol Description -5 -4 Units Min Max Min Max Clock-to-Output Times T When reading from block RAM, the delay from the active BCKO transition at the CLK input to data appearing at the DOUT - 2.45 - 2.82 ns output Setup Times T Setup time for the ADDR inputs before the active transition at BACK 0.33 - 0.38 - ns the CLK input of the block RAM T Setup time for data at the DIN inputs before the active BDCK 0.23 - 0.23 - ns transition at the CLK input of the block RAM T Setup time for the EN input before the active transition at the BECK 0.67 - 0.77 - ns CLK input of the block RAM T Setup time for the WE input before the active transition at the BWCK 1.09 - 1.26 - ns CLK input of the block RAM Hold Times T Hold time on the ADDR inputs after the active transition at the BCKA 0.12 - 0.14 - ns CLK input T Hold time on the DIN inputs after the active transition at the BCKD 0.12 - 0.13 - ns CLK input T Hold time on the EN input after the active transition at the CLK BCKE 0 - 0 - ns input T Hold time on the WE input after the active transition at the CLK BCKW 0 - 0 - ns input Clock Timing T High pulse width of the CLK signal 1.39 - 1.59 - ns BPWH T Low pulse width of the CLK signal 1.39 - 1.59 - ns BPWL Clock Frequency F Block RAM clock frequency. RAM read output value written BRAM back into RAM, for shift-registers and circular buffers. 0 270 0 230 MHz Write-only or read-only performance is faster. Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 139

Spartan-3E FPGA Family: DC and Switching Characteristics Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key Period jitter is the worst-case deviation from the ideal clock components: the Delay-Locked Loop (DLL), the Digital period over a collection of millions of samples. In a Frequency Synthesizer (DFS), and the Phase Shifter (PS). histogram of period jitter, the mean value is the clock period. Aspects of DLL operation play a role in all DCM Cycle-cycle jitter is the worst-case difference in clock period applications. All such applications inevitably use the CLKIN between adjacent clock cycles in the collection of clock and the CLKFB inputs connected to either the CLK0 or the periods sampled. In a histogram of cycle-cycle jitter, the CLK2X feedback, respectively. Thus, specifications in the mean value is zero. DLL tables (Table104 and Table105) apply to any Spread Spectrum application that only employs the DLL component. When the DFS and/or the PS components are used together with DCMs accept typical spread spectrum clocks as long as the DLL, then the specifications listed in the DFS and PS they meet the input requirements. The DLL will track the tables (Table106 through Table109) supersede any frequency changes created by the spread spectrum clock to corresponding ones in the DLL tables. DLL specifications drive the global clocks to the FPGA logic. See XAPP469, that do not change with the addition of DFS or PS functions Spread-SpectrumClockingReceptionforDisplays for are presented in Table104 and Table105. details. Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe statistical variation from a mean value. Delay-Locked Loop (DLL) Table 104: Recommended Operating Conditions for the DLL Speed Grade Symbol Description -5 -4 Units Min Max Min Max Input Frequency Ranges F CLKIN_FREQ_DLL Frequency of the CLKIN Stepping 0 XC3S100E N/A N/A 5(2) 90(3) MHz CLKIN clock input XC3S250E XC3S500E XC3S1600E XC3S1200E(3) 200(3) MHz Stepping 1 All 5(2) 275(3) 240(3) MHz Input Pulse Requirements CLKIN_PULSE CLKIN pulse width as a F ≤ 150MHz 40% 60% 40% 60% - CLKIN percentage of the CLKIN F > 150MHz 45% 55% 45% 55% - period CLKIN Input Clock Jitter Tolerance and Delay Path Variation(4) CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the F ≤ 150MHz - ±300 - ±300 ps CLKIN CLKIN input CLKIN_CYC_JITT_DLL_HF F > 150MHz - ±150 - ±150 ps CLKIN CLKIN_PER_JITT_DLL Period jitter at the CLKIN input - ±1 - ±1 ns CLKFB_DELAY_VAR_EXT Allowable variation of off-chip feedback delay from the DCM - ±1 - ±1 ns output to the CLKFB input Notes: 1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. 2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table106. 3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input. 4. CLKIN input jitter beyond these limits might cause the DCM to lose lock. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 140

Spartan-3E FPGA Family: DC and Switching Characteristics Table 105: Switching Characteristics for the DLL Speed Grade Symbol Description Device -5 -4 Units Min Max Min Max Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and Stepping 0 XC3S100E N/A N/A 5 90 MHz CLK180 outputs XC3S250E XC3S500E XC3S1600E XC3S1200E 200 MHz Stepping 1 All 5 275 240 MHz CLKOUT_FREQ_CLK90 Frequency for the CLK90 and Stepping 0 XC3S100E N/A N/A 5 90 MHz CLK270 outputs XC3S250E XC3S500E XC3S1600E XC3S1200E 167 MHz Stepping 1 All 5 200 200 MHz CLKOUT_FREQ_2X Frequency for the CLK2X and Stepping 0 XC3S100E N/A N/A 10 180 MHz CLK2X180 outputs XC3S250E XC3S500E XC3S1600E XC3S1200E 311 MHz Stepping 1 All 10 333 311 MHz CLKOUT_FREQ_DV Frequency for the CLKDV Stepping 0 XC3S100E N/A N/A 0.3125 60 MHz output XC3S250E XC3S500E XC3S1600E XC3S1200E 133 MHz Stepping 1 All 0.3125 183 160 MHz Output Clock Jitter(2,3,4) CLKOUT_PER_JITT_0 Period jitter at the CLK0 output All - ±100 - ±100 ps CLKOUT_PER_JITT_90 Period jitter at the CLK90 output - ±150 - ±150 ps CLKOUT_PER_JITT_180 Period jitter at the CLK180 output - ±150 - ±150 ps CLKOUT_PER_JITT_270 Period jitter at the CLK270 output - ±150 - ±150 ps CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs - ±[1% of - ±[1% of ps CLKIN CLKIN period period + 150] + 150] CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when - ±150 - ±150 ps performing integer division CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when - ±[1% of - ±[1% of ps performing non-integer division CLKIN CLKIN period period + 200] + 200] Duty Cycle(4) CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, All - ±[1% of - ±[1% of ps CLK180, CLK270, CLK2X, CLK2X180, and CLKIN CLKIN CLKDV outputs, including the BUFGMUX and period period clock tree duty-cycle distortion + 400] + 400] DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 141

Spartan-3E FPGA Family: DC and Switching Characteristics Table 105: Switching Characteristics for the DLL (Cont’d) Speed Grade Symbol Description Device -5 -4 Units Min Max Min Max Phase Alignment(4) CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB All - ±200 - ±200 ps inputs CLKOUT_PHASE_DLL Phase offset between DLL CLK0 to CLK2X - ±[1% of - ±[1% of ps outputs (not CLK2X180) CLKIN CLKIN period period + 100] + 100] All others - ±[1% of - ±[1% of ps CLKIN CLKIN period period + 200] + 200] Lock Time LOCK_DLL(3) When using the DLL alone: 5MHz≤F All - 5 - 5 ms CLKIN The time from deassertion at ≤15MHz the DCM’s Reset input to the F > 15MHz - 600 - 600 μs rising transition at its CLKIN LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase Delay Lines DCM_DELAY_STEP Finest delay resolution All 20 40 20 40 ps Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77 and Table104. 2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. 3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum jitter of ±[1% of CLKIN period + 150]. Assume the CLKIN frequency is 100MHz. The equivalent CLKIN period is 10ns and 1% of 10ns is 0.1ns or 100ps. According to the data sheet, the maximum jitter is ±[100ps + 150ps] = ±250ps. Digital Frequency Synthesizer (DFS) Table 106: Recommended Operating Conditions for the DFS Speed Grade Symbol Description -5 -4 Units Min Max Min Max Input Frequency Ranges(2) F CLKIN_FREQ_FX Frequency for the CLKIN input 0.200 333(4) 0.200 333(4) MHz CLKIN Input Clock Jitter Tolerance(3) CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the F ≤ 150MHz - ±300 - ±300 ps CLKFX CLKIN input, based on CLKFX CLKIN_CYC_JITT_FX_HF F > 150MHz - ±150 - ±150 ps output frequency CLKFX CLKIN_PER_JITT_FX Period jitter at the CLKIN input - ±1 - ±1 ns Notes: 1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used. 2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table104. 3. CLKIN input jitter beyond these limits may cause the DCM to lose lock. 4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 142

Spartan-3E FPGA Family: DC and Switching Characteristics Table 107: Switching Characteristics for the DFS Speed Grade Symbol Description Device -5 -4 Units Min Max Min Max Output Frequency Ranges CLKOUT_FREQ_FX_LF Frequency for the CLKFX and Stepping 0 XC3S100E N/A N/A 5 90 MHz CLKFX180 outputs, low XC3S250E frequencies XC3S500E XC3S1600E CLKOUT_FREQ_FX_HF Frequency for the CLKFX and 220 307 MHz CLKFX180 outputs, high frequencies CLKOUT_FREQ_FX Frequency for the CLKFX and Stepping 0 XC3S1200E 5 307 MHz CLKFX180 outputs Stepping 1 All 5 333 311 MHz Output Clock Jitter(2,3) CLKOUT_PER_JITT_FX Period jitter at the CLKFX and All Typ Max Typ Max CLKFX180 outputs. CLKIN≤20MHz Note 6 ps CLKIN>20MHz ±[1% of ±[1% of ±[1% of ±[1% of ps CLKFX CLKFX CLKFX CLKFX period period period period + 100] + 200] + 100] + 200] Duty Cycle(4,5) CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 All - ±[1% of - ±[1% of ps outputs, including the BUFGMUX and clock tree CLKFX CLKFX duty-cycle distortion period period + 400] + 400] Phase Alignment(5) CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the All - ±200 - ±200 ps DLL CLK0 output when both the DFS and DLL are used CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and All - ±[1% of - ±[1% of ps the DLL CLK0 output when both the DFS and DLL are CLKFX CLKFX used period period + 300] + 300] Lock Time LOCK_FX(2) The time from deassertion at the 5MHz≤F All - 5 - 5 ms CLKIN DCM’s Reset input to the rising ≤15MHz transition at its LOCKED output. F >15MHz - 450 - 450 μs The DFS asserts LOCKED when CLKIN the CLKFX and CLKFX180 signals are valid. If using both the DLL and the DFS, use the longer locking time. Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77 and Table106. 2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 3. Maximum output jitter is characterized within a reasonable noise environment (150ps input period jitter, 40 SSOs and 25% CLB switching). Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application. 4. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle. 5. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter of ±[1% of CLKFX period + 300]. Assume the CLKFX output frequency is 100MHz. The equivalent CLKFX period is 10ns and 1% of 10ns is 0.1ns or 100ps. According to the data sheet, the maximum jitter is ±[100ps + 300ps] = ±400ps. 6. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the Clocking Wizard to determine jitter for a specific design. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 143

Spartan-3E FPGA Family: DC and Switching Characteristics Phase Shifter (PS) Table 108: Recommended Operating Conditions for the PS in Variable Phase Mode Speed Grade Symbol Description -5 -4 Units Min Max Min Max Operating Frequency Ranges PSCLK_FREQ Frequency for the PSCLK input 1 167 1 167 MHz (F ) PSCLK Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period 40% 60% 40% 60% - Table 109: Switching Characteristics for the PS in Variable Phase Mode Symbol Description Equation Units Phase Shifting Range MAX_STEPS(2) Maximum allowed number of DCM_DELAY_STEP steps CLKIN<60MHz ±[INTEGER(10 • steps for a given CLKIN clock period, where T=CLKIN clock (T – 3ns))] CLKIN period in ns. If using CLKIN_DIVIDE_BY_2 =TRUE, double the effective clock period.(3) CLKIN≥60MHz ±[INTEGER(15 • steps (T – 3ns))] CLKIN FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting ±[MAX_STEPS • ns DCM_DELAY_STEP_MIN] FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting ±[MAX_STEPS • ns DCM_DELAY_STEP_MAX] Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77 and Table108. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the bottom of Table105. Miscellaneous DCM Timing Table 110: Miscellaneous DCM Timing Symbol Description Min Max Units DCM_RST_PW_MIN(1) Minimum duration of a RST pulse width 3 - CLKIN cycles DCM_RST_PW_MAX(2) Maximum duration of a RST pulse width N/A N/A seconds DCM_CONFIG_LAG_TIME(3) Maximum duration from V applied to FPGA configuration N/A N/A minutes CCINT successfully completed (DONE pin goes High) and clocks applied to DCM DLL Notes: 1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. 2. This specification is equivalent to the Virtex-4 DCM_RESET specfication.This specification does not apply for Spartan-3E FPGAs. 3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 144

Spartan-3E FPGA Family: DC and Switching Characteristics Configuration and JTAG Timing General Configuration Power-On/Reconfigure Timing X-Ref Target - Figure 73 VCCINT 1.2V (Supply) 1.0V VCCAUX 2.5V (Supply) 2.0V VCCO Bank 2 (Supply) 1.0V T POR PROG_B (Input) T T PROG PL INIT_B (Open-Drain) T ICCK CCLK (Output) DS312-3_01_103105 Notes: 1. The V , V , and V supplies may be applied in any order. CCINT CCAUX CCO 2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle. 3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2). Figure 73: Waveforms for Power-On and the Beginning of Configuration Table 111: Power-On Timing and the Beginning of Configuration All Speed Grades Symbol Description Device Units Min Max T (2) The time from the application of V , V , and V XC3S100E - 5 ms POR CCINT CCAUX CCO Bank 2 supply voltage ramps (whichever occurs last) to the XC3S250E - 5 ms rising transition of the INIT_B pin XC3S500E - 5 ms XC3S1200E - 5 ms XC3S1600E - 7 ms T The width of the low-going pulse on the PROG_B pin All 0.5 - μs PROG T (2) The time from the rising edge of the PROG_B pin to the XC3S100E - 0.5 ms PL rising transition on the INIT_B pin XC3S250E - 0.5 ms XC3S500E - 1 ms XC3S1200E - 2 ms XC3S1600E - 2 ms T Minimum Low pulse width on INIT_B output All 250 - ns INIT T (3) The time from the rising edge of the INIT_B pin to the All 0.5 4.0 μs ICCK generation of the configuration clock signal at the CCLK output pin Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77. This means power must be applied to all V , V , CCINT CCO and V lines. CCAUX 2. Power-on reset and the clearing of configuration memory occurs during this period. 3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 145

Spartan-3E FPGA Family: DC and Switching Characteristics Configuration Clock (CCLK) Characteristics Table 112: Master Mode CCLK Output Period by ConfigRate Option Setting ConfigRate Temperature Symbol Description Minimum Maximum Units Setting Range CCLK clock period by 1 Commercial 570 ns T ConfigRate setting (power-on value and 1,250 CCLK1 default value) Industrial 485 ns Commercial 285 ns T 3 625 CCLK3 Industrial 242 ns Commercial 142 ns T 6 313 CCLK6 Industrial 121 ns Commercial 71.2 ns T 12 157 CCLK12 Industrial 60.6 ns Commercial 35.5 ns T 25 78.2 CCLK25 Industrial 30.3 ns Commercial 17.8 ns T 50 39.1 CCLK50 Industrial 15.1 ns Notes: 1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in Module2. Table 113: Master Mode CCLK Output Frequency by ConfigRate Option Setting ConfigRate Temperature Symbol Description Minimum Maximum Units Setting Range Equivalent CCLK clock frequency 1 Commercial 1.8 MHz F by ConfigRate setting (power-on value and 0.8 CCLK1 default value) Industrial 2.1 MHz Commercial 3.6 MHz F 3 1.6 CCLK3 Industrial 4.2 MHz Commercial 7.1 MHz F 6 3.2 CCLK6 Industrial 8.3 MHz Commercial 14.1 MHz F 12 6.4 CCLK12 Industrial 16.5 MHz Commercial 28.1 MHz F 25 12.8 CCLK25 Industrial 33.0 MHz Commercial 56.2 MHz F 50 25.6 CCLK50 Industrial 66.0 MHz Table 114: Master Mode CCLK Output Minimum Low and High Time ConfigRate Setting Symbol Description Units 1 3 6 12 25 50 T Master mode CCLK minimum Commercial 276 138 69 34.5 17.1 8.5 ns MCCL, T Low and High time MCCH Industrial 235 117 58 29.3 14.5 7.3 ns Table 115: Slave Mode CCLK Input Low and High Time Symbol Description Min Max Units T CCLK Low and High time 5 ∞ ns SCCL, T SCCH DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 146

Spartan-3E FPGA Family: DC and Switching Characteristics Master Serial and Slave Serial Mode Timing X-Ref Target - Figure 74 PROG_B (Input) INIT_B (Open-Drain) T T MCCL MCCH T T SCCL SCCH CCLK (Input/Output) T T 1/F DCC CCD CCSER DIN (Input) Bit 0 Bit 1 Bit n Bit n+1 T CCO DOUT Bit n-64 Bit n-63 (Output) DS312-3_05_103105 Figure 74: Waveforms for Master Serial and Slave Serial Configuration Table 116: Timing for the Master Serial and Slave Serial Configuration Modes All Speed Grades Slave/ Symbol Description Units Master Min Max Clock-to-Output Times T The time from the falling transition on the CCLK pin to data appearing at the Both 1.5 10.0 ns CCO DOUT pin Setup Times T The time from the setup of data at the DIN pin to the active edge of the Both 11.0 - ns DCC CCLK pin Hold Times T The time from the active edge of the CCLK pin to the point when data is last Both 0 - ns CCD held at the DIN pin Clock Timing T High pulse width at the CCLK input pin Master See Table114 CCH Slave See Table115 T Low pulse width at the CCLK input pin Master See Table114 CCL Slave See Table115 F Frequency of the clock signal at the No bitstream compression Slave 0 66(2) MHz CCSER CCLK input pin With bitstream compression 0 20 MHz Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77. 2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25MHz. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 147

Spartan-3E FPGA Family: DC and Switching Characteristics Slave Parallel Mode Timing X-Ref Target - Figure 75 PROG_B (Input) INIT_B (Open-Drain) TSMCSCC TSMCCCS CSI_B (Input) T SMCCW T SMWCC RDWR_B (Input) T T MCCH MCCL T T SCCH SCCL CCLK (Input) T T 1/F SMDCC SMCCD CCPAR D0 - D7 Byte 0 Byte 1 Byte n Byte n+1 (Inputs) T T SMCKBY SMCKBY BUSY High-Z High-Z BUSY (Output) DS312-3_02_103105 Notes: 1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0 - D7 bus. Figure 75: Waveforms for Slave Parallel Configuration Table 117: Timing for the Slave Parallel Configuration Mode All Speed Grades Symbol Description Units Min Max Clock-to-Output Times T The time from the rising transition on the CCLK pin to a signal transition at the BUSY pin - 12.0 ns SMCKBY Setup Times T The time from the setup of data at the D0-D7 pins to the active edge the CCLK pin 11.0 - ns SMDCC T Setup time on the CSI_B pin before the active edge of the CCLK pin 10.0 - ns SMCSCC T (2) Setup time on the RDWR_B pin before active edge of the CCLK pin 23.0 - ns SMCCW Hold Times T The time from the active edge of the CCLK pin to the point when data is last held at the 1.0 - ns SMCCD D0-D7 pins T The time from the active edge of the CCLK pin to the point when a logic level is last held 0 - ns SMCCCS at the CSO_B pin T The time from the active edge of the CCLK pin to the point when a logic level is last held 0 - ns SMWCC at the RDWR_B pin DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 148

Spartan-3E FPGA Family: DC and Switching Characteristics Table 117: Timing for the Slave Parallel Configuration Mode (Cont’d) All Speed Grades Symbol Description Units Min Max Clock Timing T The High pulse width at the CCLK input pin 5 - ns CCH T The Low pulse width at the CCLK input pin 5 - ns CCL F Frequency of the clock signal No bitstream Not using the BUSY pin(2) 0 50 MHz CCPAR at the CCLK input pin compression Using the BUSY pin 0 66 MHz With bitstream compression 0 20 MHz Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77. 2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification. 3. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 149

Spartan-3E FPGA Family: DC and Switching Characteristics Serial Peripheral Interface (SPI) Configuration Timing X-Ref Target - Figure 76 PROG_B (Input) HSWAP HSWAP must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point these pins become user-I/O pins. M[2:0] <0:0:1> (Input) T T MINIT INITM INIT_B New ConfigRate active (Open-Drain) T T T TMCCL1 TMCCH1 TMCCLn TCCLKn CCLK1 CCLK1 MCCHn CCLK T V DIN Data Data Data Data (Input) T CSS T DCC CSO_B T CCD T CCO Command Command MOSI (msb) (msb-1) T T DSU DH Pin initially pulled High by internal pull-up resistor if HSWAP input is Low. Pin initially high-impedance (Hi-Z) if HSWAP input is High. External pull-up resistor required on CSO_B. Shaded values indicate specifications on attached SPI Flash PROM. ds312-3_06_110206 Figure 76: Waveforms for Serial Peripheral Interface (SPI) Configuration Table 118: Timing for Serial Peripheral Interface (SPI) Configuration Mode Symbol Description Minimum Maximum Units T Initial CCLK clock period See Table112 CCLK1 T CCLK clock period after FPGA loads ConfigRate setting See Table112 CCLKn T Setup time on VS[2:0] and M[2:0] mode pins before the rising edge of INIT_B 50 - ns MINIT T Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of INIT_B 0 - ns INITM T MOSI output valid after CCLK edge See Table116 CCO T Setup time on DIN data input before CCLK edge See Table116 DCC T Hold time on DIN data input after CCLK edge See Table116 CCD DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 150

Spartan-3E FPGA Family: DC and Switching Characteristics Table 119: Configuration Timing Requirements for Attached SPI Serial Flash Symbol Description Requirement Units TCCS SPI serial Flash PROM chip-select time T ≤ T –T ns CCS MCCL1 CCO TDSU SPI serial Flash PROM data input setup time T ≤ T –T ns DSU MCCL1 CCO TDH SPI serial Flash PROM data input hold time T ≤ T ns DH MCCH1 TV SPI serial Flash PROM data clock-to-output time T ≤ T –T ns V MCCLn DCC f or f Maximum SPI serial Flash PROM clock frequency (also depends on 1 MHz C R f ≥ ------------------------------- specific read command used) C T CCLKn(min) Notes: 1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source. 2. Subtract additional printed circuit board routing delay as required by the application. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 151

Spartan-3E FPGA Family: DC and Switching Characteristics Byte Peripheral Interface (BPI) Configuration Timing X-Ref Target - Figure 77 PROG_B (Input) HSWAP HSWAP must be stable before INIT_B goes High and constant throughout the configuration process. (Input) Mode input pins M[2:0] are sampled when INIT_B goes High. After this point, M[2:0] <0:1:0> input values do not matter until DONE goes High, at which point the mode pins (Input) become user-I/O pins. T T MINIT INITM INIT_B (Open-Drain) Pin initially pulled High by internal pull-up resistor if HSWAP input is Low. Pin initially high-impedance (Hi-Z) if HSWAP input is High. LDC[2:0] HDC CSO_B New ConfigRate active T T T INITADDR CCLK1 CCLKn T CCLK1 CCLK T CCO A[23:0] 000_0000 000_0001 Address Address Address T T T AVQV DCC CCD D[7:0] Byte 0 Byte 1 Data Data Data Data (Input) Shaded values indicate specifications on attached parallel NOR Flash PROM. DS312-3_08_032409 Figure 77: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown) Table 120: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode Symbol Description Minimum Maximum Units T Initial CCLK clock period See Table112 CCLK1 T CCLK clock period after FPGA loads ConfigRate setting See Table112 CCLKn T Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising edge of 50 - ns MINIT INIT_B T Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising edge of 0 - ns INITM INIT_B T Minimum period of initial A[23:0] address cycle; LDC[2:0] BPI-UP: 5 5 T INITADDR CCLK1 and HDC are asserted and valid (M[2:0]=<0:1:0>) cycles BPI-DN: 2 2 (M[2:0]=<0:1:1>) T Address A[23:0] outputs valid after CCLK falling edge See Table116 CCO T Setup time on D[7:0] data inputs before CCLK rising edge See Table116 DCC T Hold time on D[7:0] data inputs after CCLK rising edge See Table116 CCD DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 152

Spartan-3E FPGA Family: DC and Switching Characteristics Table 121: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description Requirement Units TCE (tELQV) Parallel NOR Flash PROM chip-select T ≤ T ns time CE INITADDR TOE (tGLQV) Parallel NOR Flash PROM T ≤ T ns output-enable time OE INITADDR TACC (tAVQV) Pacacraelslesl tNimOeR Flash PROM read TACC ≤ 0.5TCCLKn(min)–TCCO –TDCC–PCB ns TBYTE (tFLQV, tFHQV) For x8/x16 PROMs only: BYTE# to T ≤ T ns output valid time(3) BYTE INITADDR Notes: 1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded int o the FPGA and the resulting clock source. 2. Subtract additional printed circuit board routing delay as required by the application. 3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor value also depends on whether the FPGA’s HSWAP pin is High or Low. Table 122: MultiBoot Trigger (MBT) Timing Symbol Description Minimum Maximum Units T MultiBoot Trigger (MBT) Low pulse width required to initiate MultiBoot 300 ∞ ns MBT reconfiguration Notes: 1. MultiBoot re-configuration starts on the rising edge after MBT is Low for at least the prescribed minimum period. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 153

Spartan-3E FPGA Family: DC and Switching Characteristics IEEE 1149.1/1532 JTAG Test Access Port Timing X-Ref Target - Figure 78 TCCH TCCL TCK (Input) TTMSTCK TTCKTMS 1/FTCK TMS (Input) TTDITCK TTCKTDI TDI (Input) TTCKTDO TDO (Output) DS312-3_79_032409 Figure 78: JTAG Waveforms Table 123: Timing for the JTAG Test Access Port All Speed Grades Symbol Description Units Min Max Clock-to-Output Times T The time from the falling transition on the TCK pin to 1.0 11.0 ns TCKTDO data appearing at the TDO pin Setup Times T The time from the setup of data at the TDI pin to the 7.0 - ns TDITCK rising transition at the TCK pin T The time from the setup of a logic level at the TMS pin 7.0 - ns TMSTCK to the rising transition at the TCK pin Hold Times T The time from the rising transition at the TCK pin to the 0 - ns TCKTDI point when data is last held at the TDI pin T The time from the rising transition at the TCK pin to the 0 - ns TCKTMS point when a logic level is last held at the TMS pin Clock Timing T The High pulse width at the TCK pin 5 - ns CCH T The Low pulse width at the TCK pin 5 - ns CCL F Frequency of the TCK signal - 30 MHz TCK Notes: 1. The numbers in this table are based on the operating conditions set forth in Table77. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 154

Spartan-3E FPGA Family: DC and Switching Characteristics Revision History The following table shows the revision history for this document. Date Version Revision 03/01/2005 1.0 Initial Xilinx release. 11/23/2005 2.0 Added AC timing information and additional DC specifications. 03/22/2006 3.0 Upgraded data sheet status to Preliminary. Finalized production timing parameters. All speed grades for all Spartan-3E FPGAs are now Production status using the v1.21 speed files, as shown in Table84. Expanded description in Note 2, Table78. Updated pin-to-pin and clock-to-output timing based on final characterization, shown in Table86. Updated system-synchronous input setup and hold times based on final characterization, shown in Table87 and Table88. Updated other I/O timing in Table90. Provided input and output adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards that supersede the v1.21 speed file values, in Table91 and Table94. Reduced I/O three-state and set/reset delays in Table93. Added XC3S100E FPGA in CP132 package to Table96. Increased T AS slice flip-flop timing by 100ps in Table98. Updated distributed RAM timing in Table99 and SRL16 timing in Table100. Updated global clock timing, removed left/right clock buffer limits in Table101. Updated block RAM timing in Table103. Added DCM parameters for remainder of Step 0 device; added improved Step 1 DCM performance to Table104, Table105, Table106, and Table107. Added minimum INIT_B pulse width specification, T , in Table111. Increased data hold time for Slave INIT Parallel mode to 1.0ns (T ) in Table117. Improved the DCM performance for the XC3S1200E, SMCCD Stepping 0 in Table104, Table105, Table106, and Table107. Corrected links in Table118 and Table120. Added MultiBoot timing specifications to Table122. 04/07/2006 3.1 Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP packages (Table97). Removed potentially confusing Note 2 from Table78. 05/19/2006 3.2 Clarified that 100mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards (Note 4, Table80). Other minor edits. 05/30/2006 3.2.1 Corrected various typos and incorrect links. 11/09/2006 3.4 Improved absolute maximum voltage specifications in Table73, providing additional overshoot allowance. Widened the recommended voltage range for PCI and PCI-X standards in Table80. Clarified Note 2, Table83. Improved various timing specifications for v1.26 speed file. Added Table85 to summarize the history of speed file releases after which time all devices became Production status. Added absolute minimum values for Table86, Table92, and Table93. Updated pin-to-pin setup and hold timing based on default IFD_DELAY_VALUE settings in Table87, Table88, and Table90. Added Table89 about source-synchronous input capture sample window. Promoted Module3 to Production status. Synchronized all modules to v3.4. 03/16/2007 3.5 Based on extensive 90 nm production data, improved (reduced) the maximum quiescent current limits for the I , I , and I specifications in Table79 by an average of 50%. CCINTQ CCAUXQ CCOQ 05/29/2007 3.6 Added note to Table74 and Table75 regarding HSWAP in step 0 devices. Updated t in RPW_CLB Table98 to match value in speed file. Improved CLKOUT_FREQ_CLK90 to 200MHz for Stepping 1 in Table105. 04/18/2008 3.7 Clarified that Stepping 0 was offered only for -4C and removed Stepping 0 -5 specifications. Added reference to XAPP459 in Table73 and Table77. Improved recommended max V to 3.465V (3.3V CCO + 5%) in Table77. Removed minimum input capacitance from Table78. Updated Recommended Operating Conditions for LVCMOS and PCI I/O standards in Table80. Removed Absolute Minimums from Table86, Table92 and Table93 and added footnote recommending use of Timing Analyzer for minimum values. Updated T and T in Table87 to match current speed file. Update T PSFD PHFD RPW_IOB in Table88 to match current speed file and CLB equivalent spec. Added XC3S500E VQG100 to Table96. Replaced T with T for A, B, and P registers in Table102. Updated MULCKID MSCKD CLKOUT_PER_JITT_FX in Table107. Updated MAX_STEPS equation in Table109. Updated Figure77 and Table120 to correct CCLK active edge. Updated links. 08/26/2009 3.8 Added reference to XAPP459 in Table73 note 2. Updated BPI timing in Figure77, Table119, and Table120. Removed V requirements for differential HSTL and differential SSTL in Table95. Added REF Spread Spectrum paragraph. Revised hold times for T in Table88 and setup times for T in IOICKPD DICK Table98. Added note 4 to Table106 and note 3 to Table107, and updated note 6 for Table107 to add input jitter. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 155

Spartan-3E FPGA Family: DC and Switching Characteristics Date Version Revision 10/29/2012 4.0 Added Notice of Disclaimer. This product is not recommended for new designs. Revised note 2 in Table73. Revised note 2 and V description in Table77, and added note 5. Added IN note 3 to Table78. 07/19/2013 4.1 Removed banner. This product IS recommended for new designs. 12/14/2018 4.2 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024). Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 156

227 Spartan-3E FPGA Family: Pinout Descriptions DS312 (v4.2) December 14, 2018 Product Specification Introduction Pin Types This section describes the various pins on a Spartan®-3E Most pins on a Spartan-3E FPGA are general-purpose, FPGA and how they connect within the supported user-defined I/O pins. There are, however, up to 11 different component packages. functional types of pins on Spartan-3E packages, as outlined in Table124. In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table. Table 124: Types of Pins on Spartan-3E FPGAs Type / Color Description Pin Name(s) in Type(1) Code I/O Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form IO differential I/Os. IO_Lxxy_# INPUT Unrestricted, general-purpose input-only pin. This pin does not have an output IP structure, differential termination resistor, or PCI clamp diode. IP_Lxxy_# DUAL Dual-purpose pin used in some configuration modes during the configuration M[2:0] process and then usually available as a user I/O after configuration. If the pin is not HSWAP used during configuration, this pin behaves as an I/O-type pin. Some of the CCLK dual-purpose pins are also shared with bottom-edge global (GCLK) or right-half MOSI/CSI_B (RHCLK) clock inputs. See the Configuration section in Module2 for additional D[7:1] information on these signals. D0/DIN CSO_B RDWR_B BUSY/DOUT INIT_B A[23:20] A19/VS2 A18/VS1 A17/VS0 A[16:0] LDC[2:0] HDC VREF Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other IP/VREF_# VREF pins in the same bank, provides a reference voltage input for certain I/O IP_Lxxy_#/VREF_# standards. If used for a reference voltage within a bank, all VREF pins within the IO/VREF_# bank must be connected. IO_Lxxy_#/VREF_# CLK Either a user-I/O pin or Input-only pin, or an input to a specific clock buffer driver. IO_Lxxy_#/GCLK[15:10, 7:2] Every package has 16 global clock inputs that optionally clock the entire device. The IP_Lxxy_#/GCLK[9:8, 1:0] RHCLK inputs optionally clock the right-half of the device. The LHCLK inputs IO_Lxxy_#/LHCLK[7:0] optionally clock the left-half of the device. Some of the clock pins are shared with the IO_Lxxy_#/RHCLK[7:0] dual-purpose configuration pins and are considered DUAL-type. See the Clocking Infrastructure section in Module2 for additional information on these signals. CONFIG Dedicated configuration pin. Not available as a user-I/O pin. Every package has two DONE, PROG_B dedicated configuration pins. These pins are powered by VCCAUX. See the Configuration section in Module2 for details. JTAG Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four TDI, TMS, TCK, TDO dedicated JTAG pins. These pins are powered by VCCAUX. GND Dedicated ground pin. The number of GND pins depends on the package used. All GND must be connected. © Copyright 2005–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 157

Spartan-3E FPGA Family: Pinout Descriptions Table 124: Types of Pins on Spartan-3E FPGAs (Cont’d) Type / Color Description Pin Name(s) in Type(1) Code VCCAUX Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the VCCAUX package used. All must be connected to +2.5V. See the Powering Spartan-3E FPGAs section in Module2 for details. VCCINT Dedicated internal core logic power supply pin. The number of VCCINT pins VCCINT depends on the package used. All must be connected to +1.2V. See the Powering Spartan-3E FPGAs section in Module2 for details. VCCO Along with all the other VCCO pins in the same bank, this pin supplies power to the VCCO_# output buffers within the I/O bank and sets the input threshold voltage for some I/O standards. See the Powering Spartan-3E FPGAs section in Module2 for details. N.C. This package pin is not connected in this specific device/package combination but N.C. may be connected in larger devices in the same package. Notes: 1. # = I/O bank number, an integer between 0 and 3. 2. IRDY/TRDY designations are for PCI designs; refer to PCI documentation for details. Differential Pair Labeling ‘L’ indicates that the pin is part of a differential pair. ‘xx’ is a two-digit integer, unique for each bank, that I/Os with Lxxy_# are part of a differential pair. ‘L’ indicates identifies a differential pin-pair. differential capability. The ‘xx’ field is a two-digit integer, unique to each bank that identifies a differential pin-pair. ‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the The ‘y’ field is either ‘P’ for the true signal or ‘N’ for the inverted. These two pins form one differential pin-pair. inverted signal in the differential pair. The ‘#’ field is the I/O ‘#’ is an integer, 0 through 3, indicating the associated bank number. I/O bank. The pin name suffix has the following significance. Figure79 provides a specific example showing a differential input to and a differential output from Bank 1. X-Ref Target - Figure 79 Pair Number Bank 0 Bank Number IO_L38P_1 IO_L38N_1 Positive Polarity 3 1 k k True Receiver n n IO_L39P_1 a a B Spartan-3E B FPGA IO_L39N_1 Negative Polarity Inverted Receiver Bank 2 DS312-4_00_032409 Figure 79: Differential Pair Labeling DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 158

Spartan-3E FPGA Family: Pinout Descriptions Package Overview Table125 shows the eight low-cost, space-saving material declaration data sheets (MDDS) are available on production package styles for the Spartan-3E family. Each www.xilinx.com. package style is available as a standard and an Not all Spartan-3E densities are available in all packages. environmentally friendly lead-free (Pb-free) option. The For a specific package, however, there is a common Pb-free packages include an extra ‘G’ in the package style footprint that supports all the devices available in that name. For example, the standard “VQ100” package package. See the footprint diagrams that follow. becomes “VQG100” when ordered as the Pb-free option. The mechanical dimensions of the standard and Pb-free For additional package information, see UG112: Device packages are similar. Package drawings and package Package User Guide. Table 125: Spartan-3E Family Package Options(1) Lead Maximum Footprint Height Package Leads Type Pitch I/O Area (mm) (mm) (mm) VQ100 / VQG100 100 Very-thin Quad Flat Pack (VQFP) 66 0.5 16 x 16 1.20 CP132 / CPG132 132 Chip-Scale Package (CSP) 92 0.5 8.1 x 8.1 1.10 TQ144 / TQG144 144 Thin Quad Flat Pack (TQFP) 108 0.5 22 x 22 1.60 PQ208 / PQG208 208 Plastic Quad Flat Pack (PQFP) 158 0.5 30.6 x 30.6 4.10 FT256 / FTG256 256 Fine-pitch, Thin Ball Grid Array (FBGA) 190 1.0 17 x 17 1.55 FG320 / FGG320 320 Fine-pitch Ball Grid Array (FBGA) 250 1.0 19 x 19 2.00 FG400 / FGG400 400 Fine-pitch Ball Grid Array (FBGA) 304 1.0 21 x 21 2.43 FG484 / FGG484 484 Fine-pitch Ball Grid Array (FBGA) 376 1.0 23 x 23 2.60 Notes: 1. See the package material declaration data sheet for package mass. Selecting the Right Package Option packages are superior in almost every other aspect, as summarized in Table126. Consequently, Xilinx Spartan-3E FPGAs are available in both quad-flat pack recommends using BGA packaging whenever possible. (QFP) and ball grid array (BGA) packaging options. While QFP packaging offers the lowest absolute cost, the BGA Table 126: QFP and BGA Comparison Characteristic Quad Flat Pack (QFP) Ball Grid Array (BGA) Maximum User I/O 158 376 Packing Density (Logic/Area) Good Better Signal Integrity Fair Better Simultaneous Switching Output (SSO) Support Fair Better Thermal Dissipation Fair Better Minimum Printed Circuit Board (PCB) Layers 4 4-6 Hand Assembly/Rework Possible Difficult DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 159

Spartan-3E FPGA Family: Pinout Descriptions Mechanical Drawings Package drawings and package material declaration data sheets (MDDS) are available on www.xilinx.com. Package Pins by Type Each package has three separate voltage supply inputs— VCCINT, VCCAUX, and VCCO—and a common ground return, GND. The numbers of pins dedicated to these functions vary by package, as shown in Table127. Table 127: Power and Ground Supply Pins by Package Package VCCINT VCCAUX VCCO GND VQ100 4 4 8 12 CP132 6 4 8 16 TQ144 4 4 9 13 PQ208 4 8 12 20 FT256 8 8 16 28 FG320 8 8 20 28 FG400 16 8 24 42 FG484 16 10 28 48 A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/O depend on the device type and the package in which it is available, as shown in Table128. The table shows the maximum number of single-ended I/O pins available, assuming that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are used as general-purpose I/O. Likewise, the table shows the maximum number of differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by pin type, including the number of unconnected—i.e., N.C.—pins on the device. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 160

Spartan-3E FPGA Family: Pinout Descriptions Table 128: Maximum User I/O by Package Maximum All Possible I/Os by Type Maximum Maximum User I/Os Device Package Input- Differential and Only Pairs I/O INPUT DUAL VREF(1) CLK(2) N.C. Input-Only XC3S100E 66 7 30 16 1 21 4 24 0 XC3S250E VQ100 66 7 30 16 1 21 4 24 0 XC3S500E 66 7 30 16 1 21 4 24 0 XC3S100E 83 11 35 16 2 42 7 16 9 XC3S250E CP132 92 7 41 22 0 46 8 16 0 XC3S500E 92 7 41 22 0 46 8 16 0 XC3S100E 108 28 40 22 19 42 9 16 0 TQ144 XC3S250E 108 28 40 20 21 42 9 16 0 XC3S250E 158 32 65 58 25 46 13 16 0 PQ208 XC3S500E 158 32 65 58 25 46 13 16 0 XC3S250E 172 40 68 62 33 46 15 16 18 XC3S500E FT256 190 41 77 76 33 46 19 16 0 XC3S1200E 190 40 77 78 31 46 19 16 0 XC3S500E 232 56 92 102 48 46 20 16 18 XC3S1200E FG320 250 56 99 120 47 46 21 16 0 XC3S1600E 250 56 99 120 47 46 21 16 0 XC3S1200E 304 72 124 156 62 46 24 16 0 FG400 XC3S1600E 304 72 124 156 62 46 24 16 0 XC3S1600E FG484 376 82 156 214 72 46 28 16 0 Notes: 1. Some VREF pins are on INPUT pins. See pinout tables for details. 2. All devices have 24 possible global clock and right- and left-half side clock inputs. The right-half and bottom-edge clock pins have shared functionality in some FPGA configuration modes. Consequently, some clock pins are counted in the DUAL column. 4 GCLK pins, including 2 DUAL pins, are on INPUT pins. Electronic versions of the package pinout tables and foot- prints are available for download from the Xilinx website. Download the files from the following location: http://www.xilinx.com/support/documentation/data_sheets /s3e_pin.zip Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the ASCII-text file is easily parsed by most scripting programs. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 161

Spartan-3E FPGA Family: Pinout Descriptions Package Thermal Characteristics package body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ ) JB The power dissipated by an FPGA application has value similarly reports the difference between the board and implications on package selection and system design. The junction temperature. The junction-to-ambient (θ ) value JA power consumed by a Spartan-3E FPGA is reported using reports the temperature difference per watt between the either the XPower Estimator or the XPower Analyzer ambient environment and the junction temperature. The θ JA calculator integrated in the Xilinx ISE® development value is reported at different air velocities, measured in software. Table129 provides the thermal characteristics for linear feet per minute (LFM). The Still Air (0LFM) column the various Spartan-3E package offerings. shows the θ value in a system without a fan. The thermal JA The junction-to-case thermal resistance (θ ) indicates the resistance drops with increasing air flow. JC difference between the temperature measured on the Table 129: Spartan-3E Package Thermal Characteristics Junction-to-Ambient (θ ) JA at Different Air Flows Junction-to-Case Junction-to-Board Device Package Units (θ ) (θ ) JC JB Still Air 250 LFM 500 LFM 750 LFM (0LFM) XC3S100E 13.0 30.9 49.0 40.7 37.9 37.0 °C/Watt XC3S250E VQ100 11.0 25.9 43.3 36.0 33.6 32.7 °C/Watt XC3S500E 9.8 40.0 33.3 31.0 30.2 °C/Watt XC3S100E 19.3 42.0 62.1 55.3 52.8 51.2 °C/Watt XC3S250E CP132 11.8 28.1 48.3 41.8 39.5 38.0 °C/Watt XC3S500E 8.5 21.3 41.5 35.2 32.9 31.5 °C/Watt XC3S100E 8.2 31.9 52.1 40.5 34.6 32.5 °C/Watt TQ144 XC3S250E 7.2 25.7 37.6 29.2 25.0 23.4 °C/Watt XC3S250E 9.8 29.0 37.0 27.3 24.1 22.4 °C/Watt PQ208 XC3S500E 8.5 26.8 36.1 26.6 23.6 21.8 °C/Watt XC3S250E 12.4 27.7 35.8 29.3 28.4 28.1 °C/Watt XC3S500E FT256 9.6 22.2 31.1 25.0 24.0 23.6 °C/Watt XC3S1200E 6.5 16.4 26.2 20.5 19.3 18.9 °C/Watt XC3S500E 9.8 15.6 26.1 20.6 19.4 18.6 °C/Watt XC3S1200E FG320 8.2 12.5 23.0 17.7 16.4 15.7 °C/Watt XC3S1600E 7.1 10.6 21.1 15.9 14.6 13.8 °C/Watt XC3S1200E 7.5 12.4 22.3 17.2 16.0 15.3 °C/Watt FG400 XC3S1600E 6.0 10.4 20.3 15.2 14.0 13.3 °C/Watt XC3S1600E FG484 5.7 9.4 18.8 12.5 11.3 10.8 °C/Watt DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 162

Spartan-3E FPGA Family: Pinout Descriptions VQ100: 100-lead Very-thin Quad Flat Package The XC3S100E, XC3S250E, and the XC3S500E devices Table 130: VQ100 Package Pinout (Cont’d) are available in the 100-lead very-thin quad flat package, XC3S100E VQ100. All devices share a common footprint for this XC3S250E VQ100 Bank Pin Type package as shown in Table130 and Figure80. XC3S500E Number Pin Name Table130 lists all the package pins. They are sorted by 1 IO_L02P_1 P57 I/O bank number and then by pin name. Pins that form a differential I/O pair appear together in the table. The table 1 IO_L03N_1/RHCLK1 P61 RHCLK also shows the pin number for each pin and the pin type, as 1 IO_L03P_1/RHCLK0 P60 RHCLK defined earlier. 1 IO_L04N_1/RHCLK3 P63 RHCLK The VQ100 package does not support the Byte-wide 1 IO_L04P_1/RHCLK2 P62 RHCLK Peripheral Interface (BPI) configuration mode. 1 IO_L05N_1/RHCLK5 P66 RHCLK Consequently, the VQ100 footprint has fewer DUAL-type 1 IO_L05P_1/RHCLK4 P65 RHCLK pins than other packages. 1 IO_L06N_1/RHCLK7 P68 RHCLK An electronic version of this package pinout table and 1 IO_L06P_1/RHCLK6 P67 RHCLK footprint diagram is available for download from the Xilinx 1 IO_L07N_1 P71 I/O web site at: 1 IO_L07P_1 P70 I/O http://www.xilinx.com/support/documentation/data_sheets 1 IP/VREF_1 P69 VREF /s3e_pin.zip 1 VCCO_1 P55 VCCO Pinout Table 1 VCCO_1 P73 VCCO 2 IO/D5 P34 DUAL Table130 shows the pinout for production Spartan-3E 2 IO/M1 P42 DUAL FPGAs in the VQ100 package. 2 IO_L01N_2/INIT_B P25 DUAL Table 130: VQ100 Package Pinout 2 IO_L01P_2/CSO_B P24 DUAL XC3S100E 2 IO_L02N_2/MOSI/CSI_B P27 DUAL VQ100 XC3S250E Bank Pin Type 2 IO_L02P_2/DOUT/BUSY P26 DUAL XC3S500E Number Pin Name 2 IO_L03N_2/D6/GCLK13 P33 DUAL/GCLK 0 IO P92 I/O 2 IO_L03P_2/D7/GCLK12 P32 DUAL/GCLK 0 IO_L01N_0 P79 I/O 2 IO_L04N_2/D3/GCLK15 P36 DUAL/GCLK 0 IO_L01P_0 P78 I/O 2 IO_L04P_2/D4/GCLK14 P35 DUAL/GCLK 0 IO_L02N_0/GCLK5 P84 GCLK 2 IO_L06N_2/D1/GCLK3 P41 DUAL/GCLK 0 IO_L02P_0/GCLK4 P83 GCLK 2 IO_L06P_2/D2/GCLK2 P40 DUAL/GCLK 0 IO_L03N_0/GCLK7 P86 GCLK 2 IO_L07N_2/DIN/D0 P44 DUAL 0 IO_L03P_0/GCLK6 P85 GCLK 2 IO_L07P_2/M0 P43 DUAL 0 IO_L05N_0/GCLK11 P91 GCLK 2 IO_L08N_2/VS1 P48 DUAL 0 IO_L05P_0/GCLK10 P90 GCLK 2 IO_L08P_2/VS2 P47 DUAL 0 IO_L06N_0/VREF_0 P95 VREF 2 IO_L09N_2/CCLK P50 DUAL 0 IO_L06P_0 P94 I/O 2 IO_L09P_2/VS0 P49 DUAL 0 IO_L07N_0/HSWAP P99 DUAL 2 IP/VREF_2 P30 VREF 0 IO_L07P_0 P98 I/O 2 IP_L05N_2/M2/GCLK1 P39 DUAL/GCLK 0 IP_L04N_0/GCLK9 P89 GCLK 2 IP_L05P_2/RDWR_B/ P38 DUAL/GCLK GCLK0 0 IP_L04P_0/GCLK8 P88 GCLK 2 VCCO_2 P31 VCCO 0 VCCO_0 P82 VCCO 2 VCCO_2 P45 VCCO 0 VCCO_0 P97 VCCO 3 IO_L01N_3 P3 I/O 1 IO_L01N_1 P54 I/O 3 IO_L01P_3 P2 I/O 1 IO_L01P_1 P53 I/O 3 IO_L02N_3/VREF_3 P5 VREF 1 IO_L02N_1 P58 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 163

Spartan-3E FPGA Family: Pinout Descriptions Table 130: VQ100 Package Pinout (Cont’d) XC3S100E VQ100 XC3S250E Bank Pin Type XC3S500E Number Pin Name 3 IO_L02P_3 P4 I/O 3 IO_L03N_3/LHCLK1 P10 LHCLK 3 IO_L03P_3/LHCLK0 P9 LHCLK 3 IO_L04N_3/LHCLK3 P12 LHCLK 3 IO_L04P_3/LHCLK2 P11 LHCLK 3 IO_L05N_3/LHCLK5 P16 LHCLK 3 IO_L05P_3/LHCLK4 P15 LHCLK 3 IO_L06N_3/LHCLK7 P18 LHCLK 3 IO_L06P_3/LHCLK6 P17 LHCLK 3 IO_L07N_3 P23 I/O 3 IO_L07P_3 P22 I/O 3 IP P13 INPUT 3 VCCO_3 P8 VCCO 3 VCCO_3 P20 VCCO GND GND P7 GND GND GND P14 GND GND GND P19 GND GND GND P29 GND GND GND P37 GND GND GND P52 GND GND GND P59 GND GND GND P64 GND GND GND P72 GND GND GND P81 GND GND GND P87 GND GND GND P93 GND VCCAUX DONE P51 CONFIG VCCAUX PROG_B P1 CONFIG VCCAUX TCK P77 JTAG VCCAUX TDI P100 JTAG VCCAUX TDO P76 JTAG VCCAUX TMS P75 JTAG VCCAUX VCCAUX P21 VCCAUX VCCAUX VCCAUX P46 VCCAUX VCCAUX VCCAUX P74 VCCAUX VCCAUX VCCAUX P96 VCCAUX VCCINT VCCINT P6 VCCINT VCCINT VCCINT P28 VCCINT VCCINT VCCINT P56 VCCINT VCCINT VCCINT P80 VCCINT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 164

Spartan-3E FPGA Family: Pinout Descriptions User I/Os by Bank Table131 indicates how the 66 available user-I/O pins are distributed between the four I/O banks on the VQ100 package. Table 131: User I/Os Per Bank for XC3S100E, XC3S250E, and XC3S500E in the VQ100 Package All Possible I/O Pins by Type Package Maximum I/O Bank Edge I/O I/O INPUT DUAL VREF(1) CLK(2) Top 0 15 5 0 1 1 8 Right 1 15 6 0 0 1 8 Bottom 2 19 0 0 18 1 0(2) Left 3 17 5 1 2 1 8 TOTAL 66 16 1 21 4 24 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Footprint Migration Differences The production XC3S100E, XC3S250E, and XC3S500E FPGAs have identical footprints in the VQ100 package. Designs can migrate between the devices without further consideration. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 165

Spartan-3E FPGA Family: Pinout Descriptions VQ100 Footprint In Figure80, note pin 1 indicator in top-left corner and logo orientation. X-Ref Target - Figure 80 SWAP REF_0 CLK11 CLK10 CLK9 CLK8 CLK7 CLK6 CLK5 CLK4 H V G G G G G G G G TDI IO_L07N_0/ IO_L07P_0 VCCO_0 VCCAUX IO_L06N_0/ IO_L06P_0 GND IO IO_L05N_0/ IO_L05P_0/ IP_L04N_0/ IP_L04P_0/ GND IO_L03N_0/ IO_L03P_0/ IO_L02N_0/ IO_L02P_0/ VCCO_0 GND VCCINT IO_L01N_0 IO_L01P_0 TCK TDO 0 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 1 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 PROG_B 1 75 TMS Bank0 IO_L01P_3 2 74 VCCAUX IO_L01N_3 3 73 VCCO_1 IO_L02P_3 4 72 GND IO_L02N_3/VREF_3 5 71 IO_L07N_1 VCCINT 6 70 IO_L07P_1 GND 7 69 IP/VREF_1 VCCO_3 8 68 IO_L06N_1/RHCLK7 IO_L03P_3/LHCLK0 9 67 IO_L06P_1/RHCLK6 IO_L03N_3/LHCLK1 10 66 IO_L05N_1/RHCLK5 IO_L04P_3/LHCLK2 11 65 IO_L05P_1/RHCLK4 IO_L04N_3/LHCLK3 12 3 1 64 GND k k IP 13 n n 63 IO_L04N_1/RHCLK3 a a GND 14 B B 62 IO_L04P_1/RHCLK2 IO_L05P_3/LHCLK4 15 61 IO_L03N_1/RHCLK1 IO_L05N_3/LHCLK5 16 60 IO_L03P_1/RHCLK0 IO_L06P_3/LHCLK6 17 59 GND IO_L06N_3/LHCLK7 18 58 IO_L02N_1 GND 19 57 IO_L02P_1 VCCO_3 20 56 VCCINT VCCAUX 21 55 VCCO_1 IO_L07P_3 22 54 IO_L01N_1 IO_L07N_3 23 53 IO_L01P_1 IO_L01P_2/CSO_B 24 52 GND Bank2 IO_L01N_2/INIT_B 25 51 DONE 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 Y B T D 2 2 2 3 5 4 5 D 0 1 2 3 1 0 0 2 X 2 1 0 K IO_L02P_2/DOUT/BUS IO_L02N_2/MOSI/CSI_ VCCIN GN IP/VREF_ VCCO_ IO_L03P_2/D7/GCLK1 IO_L03N_2/D6/GCLK1 IO/D IO_L04P_2/D4/GCLK1 IO_L04N_2/D3/GCLK1 GN L05P_2/RDWR_B/GCLK IP_L05N_2/M2/GCLK IO_L06P_2/D2/GCLK IO_L06N_2/D1/GCLK IO/M IO_L07P_2/M IO_L07N_2/DIN/D VCCO_ VCCAU IO_L08P_2/VS IO_L08N_2/VS IO_L09P_2/VS IO_L09N_2/CCL _ P DS312-4_02_082009 I Figure 80: VQ100 Package Footprint (top view) I/O: Unrestricted, general-purpose DUAL: Configuration pin, then VREF: User I/O or input voltage 16 21 4 user I/O possible user-I/O reference for bank INPUT: Unrestricted, CLK: User I/O, input, or global VCCO: Output voltage supply for 1 24 8 general-purpose input pin buffer input bank CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply 2 4 4 pins voltage (+1.2V) N.C.: Not connected GND: Ground VCCAUX: Auxiliary supply voltage 0 12 4 (+2.5V) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 166

Spartan-3E FPGA Family: Pinout Descriptions CP132: 132-ball Chip-scale Package The XC3S100E, XC3S250E and the XC3S500E FPGAs Similarly, the A4, C1, and P10 balls on the XC3S100E are available in the 132-ball chip-scale package, CP132. FPGA are not connected but should be connected to GND The devices share a common footprint for this package as to maintain density migration compatibility. shown in Table132 and Figure81. The XC3S100E FPGA has four fewer BPI address pins, Table132 lists all the CP132 package pins. They are sorted A[19:0], whereas the XC3S250E and XC3S500E support by bank number and then by pin name. Pins that form a A[23:0]. differential I/O pair appear together in the table. The table An electronic version of this package pinout table and also shows the pin number for each pin and the pin type, as footprint diagram is available for download from the Xilinx defined earlier. web site at: Physically, the D14 and K2 balls on the XC3S100E and http://www.xilinx.com/support/documentation/data_sheets XC3S250E FPGAs are not connected but should be /s3e_pin.zip connected to VCCINT to maintain density migration compatibility. Pinout Table Table 132: CP132 Package Pinout XC3S250E XC3S100E Bank XC3S500E CP132 Ball Type Pin Name Pin Name 0 IO_L01N_0 IO_L01N_0 C12 I/O 0 IO_L01P_0 IO_L01P_0 A13 I/O 0 N.C. () IO_L02N_0 A12 100E: N.C. Others: I/O 0 N.C. () IO_L02P_0 B12 100E: N.C. Others: I/O 0 N.C. () IO_L03N_0/VREF_0 B11 100E: N.C. Others: VREF (I/O) 0 IP IO_L03P_0 C11 100E: INPUT Others: I/O 0 IO_L04N_0/GCLK5 IO_L04N_0/GCLK5 C9 GCLK 0 IO_L04P_0/GCLK4 IO_L04P_0/GCLK4 A10 GCLK 0 IO_L05N_0/GCLK7 IO_L05N_0/GCLK7 A9 GCLK 0 IO_L05P_0/GCLK6 IO_L05P_0/GCLK6 B9 GCLK 0 IO_L07N_0/GCLK11 IO_L07N_0/GCLK11 B7 GCLK 0 IO_L07P_0/GCLK10 IO_L07P_0/GCLK10 A7 GCLK 0 IO_L08N_0/VREF_0 IO_L08N_0/VREF_0 C6 VREF 0 IO_L08P_0 IO_L08P_0 B6 I/O 0 IO_L09N_0 IO_L09N_0 C5 I/O 0 IO_L09P_0 IO_L09P_0 B5 I/O 0 N.C. () IO_L10N_0 C4 100E: N.C. Others: I/O 0 IP IO_L10P_0 B4 100E: INPUT Others: I/O 0 IO_L11N_0/HSWAP IO_L11N_0/HSWAP B3 DUAL 0 IO_L11P_0 IO_L11P_0 A3 I/O 0 IP_L06N_0/GCLK9 IP_L06N_0/GCLK9 C8 GCLK 0 IP_L06P_0/GCLK8 IP_L06P_0/GCLK8 B8 GCLK 0 VCCO_0 VCCO_0 A6 VCCO DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 167

Spartan-3E FPGA Family: Pinout Descriptions Table 132: CP132 Package Pinout (Cont’d) XC3S250E XC3S100E Bank XC3S500E CP132 Ball Type Pin Name Pin Name 0 VCCO_0 VCCO_0 B10 VCCO 1 IO/A0 IO/A0 F12 DUAL 1 IO/VREF_1 IO/VREF_1 K13 VREF 1 IO_L01N_1/A15 IO_L01N_1/A15 N14 DUAL 1 IO_L01P_1/A16 IO_L01P_1/A16 N13 DUAL 1 IO_L02N_1/A13 IO_L02N_1/A13 M13 DUAL 1 IO_L02P_1/A14 IO_L02P_1/A14 M12 DUAL 1 IO_L03N_1/A11 IO_L03N_1/A11 L14 DUAL 1 IO_L03P_1/A12 IO_L03P_1/A12 L13 DUAL 1 IO_L04N_1/A9/RHCLK1 IO_L04N_1/A9/RHCLK1 J12 RHCLK/DUAL 1 IO_L04P_1/A10/RHCLK0 IO_L04P_1/A10/RHCLK0 K14 RHCLK/DUAL 1 IO_L05N_1/A7/RHCLK3/TRDY1 IO_L05N_1/A7/RHCLK3/TRDY1 J14 RHCLK/DUAL 1 IO_L05P_1/A8/RHCLK2 IO_L05P_1/A8/RHCLK2 J13 RHCLK/DUAL 1 IO_L06N_1/A5/RHCLK5 IO_L06N_1/A5/RHCLK5 H12 RHCLK/DUAL 1 IO_L06P_1/A6/RHCLK4/IRDY1 IO_L06P_1/A6/RHCLK4/IRDY1 H13 RHCLK/DUAL 1 IO_L07N_1/A3/RHCLK7 IO_L07N_1/A3/RHCLK7 G13 RHCLK/DUAL 1 IO_L07P_1/A4/RHCLK6 IO_L07P_1/A4/RHCLK6 G14 RHCLK/DUAL 1 IO_L08N_1/A1 IO_L08N_1/A1 F13 DUAL 1 IO_L08P_1/A2 IO_L08P_1/A2 F14 DUAL 1 IO_L09N_1/LDC0 IO_L09N_1/LDC0 D12 DUAL 1 IO_L09P_1/HDC IO_L09P_1/HDC D13 DUAL 1 IO_L10N_1/LDC2 IO_L10N_1/LDC2 C13 DUAL 1 IO_L10P_1/LDC1 IO_L10P_1/LDC1 C14 DUAL 1 IP/VREF_1 IP/VREF_1 G12 VREF 1 VCCO_1 VCCO_1 E13 VCCO 1 VCCO_1 VCCO_1 M14 VCCO 2 IO/D5 IO/D5 P4 DUAL 2 IO/M1 IO/M1 N7 DUAL 2 IP/VREF_2 IO/VREF_2 P11 100E: VREF(INPUT) Others: VREF(I/O) 2 IO_L01N_2/INIT_B IO_L01N_2/INIT_B N1 DUAL 2 IO_L01P_2/CSO_B IO_L01P_2/CSO_B M2 DUAL 2 IO_L02N_2/MOSI/CSI_B IO_L02N_2/MOSI/CSI_B N2 DUAL 2 IO_L02P_2/DOUT/BUSY IO_L02P_2/DOUT/BUSY P1 DUAL 2 IO_L03N_2/D6/GCLK13 IO_L03N_2/D6/GCLK13 N4 DUAL/GCLK 2 IO_L03P_2/D7/GCLK12 IO_L03P_2/D7/GCLK12 M4 DUAL/GCLK 2 IO_L04N_2/D3/GCLK15 IO_L04N_2/D3/GCLK15 N5 DUAL/GCLK 2 IO_L04P_2/D4/GCLK14 IO_L04P_2/D4/GCLK14 M5 DUAL/GCLK 2 IO_L06N_2/D1/GCLK3 IO_L06N_2/D1/GCLK3 P7 DUAL/GCLK 2 IO_L06P_2/D2/GCLK2 IO_L06P_2/D2/GCLK2 P6 DUAL/GCLK 2 IO_L07N_2/DIN/D0 IO_L07N_2/DIN/D0 N8 DUAL 2 IO_L07P_2/M0 IO_L07P_2/M0 P8 DUAL 2 N.C. () IO_L08N_2/A22 M9 100E: N.C. Others: DUAL DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 168

Spartan-3E FPGA Family: Pinout Descriptions Table 132: CP132 Package Pinout (Cont’d) XC3S250E XC3S100E Bank XC3S500E CP132 Ball Type Pin Name Pin Name 2 N.C. () IO_L08P_2/A23 N9 100E: N.C. Others: DUAL 2 N.C. () IO_L09N_2/A20 M10 100E: N.C. Others: DUAL 2 N.C. () IO_L09P_2/A21 N10 100E: N.C. Others: DUAL 2 IO_L10N_2/VS1/A18 IO_L10N_2/VS1/A18 M11 DUAL 2 IO_L10P_2/VS2/A19 IO_L10P_2/VS2/A19 N11 DUAL 2 IO_L11N_2/CCLK IO_L11N_2/CCLK N12 DUAL 2 IO_L11P_2/VS0/A17 IO_L11P_2/VS0/A17 P12 DUAL 2 IP/VREF_2 IP/VREF_2 N3 VREF 2 IP_L05N_2/M2/GCLK1 IP_L05N_2/M2/GCLK1 N6 DUAL/GCLK 2 IP_L05P_2/RDWR_B/GCLK0 IP_L05P_2/RDWR_B/GCLK0 M6 DUAL/GCLK 2 VCCO_2 VCCO_2 M8 VCCO 2 VCCO_2 VCCO_2 P3 VCCO 3 IO IO J3 I/O 3 IP/VREF_3 IO/VREF_3 K3 100E: VREF(INPUT) Others: VREF(I/O) 3 IO_L01N_3 IO_L01N_3 B1 I/O 3 IO_L01P_3 IO_L01P_3 B2 I/O 3 IO_L02N_3 IO_L02N_3 C2 I/O 3 IO_L02P_3 IO_L02P_3 C3 I/O 3 N.C. () IO_L03N_3 D1 100E: N.C. Others: I/O 3 IO IO_L03P_3 D2 I/O 3 IO_L04N_3/LHCLK1 IO_L04N_3/LHCLK1 F2 LHCLK 3 IO_L04P_3/LHCLK0 IO_L04P_3/LHCLK0 F3 LHCLK 3 IO_L05N_3/LHCLK3/IRDY2 IO_L05N_3/LHCLK3/IRDY2 G1 LHCLK 3 IO_L05P_3/LHCLK2 IO_L05P_3/LHCLK2 F1 LHCLK 3 IO_L06N_3/LHCLK5 IO_L06N_3/LHCLK5 H1 LHCLK 3 IO_L06P_3/LHCLK4/TRDY2 IO_L06P_3/LHCLK4/TRDY2 G3 LHCLK 3 IO_L07N_3/LHCLK7 IO_L07N_3/LHCLK7 H3 LHCLK 3 IO_L07P_3/LHCLK6 IO_L07P_3/LHCLK6 H2 LHCLK 3 IO_L08N_3 IO_L08N_3 L2 I/O 3 IO_L08P_3 IO_L08P_3 L1 I/O 3 IO_L09N_3 IO_L09N_3 M1 I/O 3 IO_L09P_3 IO_L09P_3 L3 I/O 3 IP/VREF_3 IP/VREF_3 E2 VREF 3 VCCO_3 VCCO_3 E1 VCCO 3 VCCO_3 VCCO_3 J2 VCCO GND N.C. (GND) GND A4 GND GND GND GND A8 GND GND N.C. (GND) GND C1 GND GND GND GND C7 GND DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 169

Spartan-3E FPGA Family: Pinout Descriptions Table 132: CP132 Package Pinout (Cont’d) XC3S250E XC3S100E Bank XC3S500E CP132 Ball Type Pin Name Pin Name GND GND GND C10 GND GND GND GND E3 GND GND GND GND E14 GND GND GND GND G2 GND GND GND GND H14 GND GND GND GND J1 GND GND GND GND K12 GND GND GND GND M3 GND GND GND GND M7 GND GND GND GND P5 GND GND N.C. (GND) GND P10 GND GND GND GND P14 GND VCCAUX DONE DONE P13 CONFIG VCCAUX PROG_B PROG_B A1 CONFIG VCCAUX TCK TCK B13 JTAG VCCAUX TDI TDI A2 JTAG VCCAUX TDO TDO A14 JTAG VCCAUX TMS TMS B14 JTAG VCCAUX VCCAUX VCCAUX A5 VCCAUX VCCAUX VCCAUX VCCAUX E12 VCCAUX VCCAUX VCCAUX VCCAUX K1 VCCAUX VCCAUX VCCAUX VCCAUX P9 VCCAUX VCCINT VCCINT VCCINT A11 VCCINT VCCINT VCCINT VCCINT D3 VCCINT VCCINT N.C. (VCCINT) VCCINT D14 VCCINT VCCINT N.C. (VCCINT) VCCINT K2 VCCINT VCCINT VCCINT VCCINT L12 VCCINT VCCINT VCCINT VCCINT P2 VCCINT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 170

Spartan-3E FPGA Family: Pinout Descriptions User I/Os by Bank Table133 shows how the 83 available user-I/O pins are pins are distributed on the XC3S250E and the XC3S500E distributed on the XC3S100E FPGA packaged in the CP132 FPGAs in the CP132 package. package. Table134 indicates how the 92 available user-I/O Table 133: User I/Os Per Bank for the XC3S100E in the CP132 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 18 6 2 1 1 8 Right 1 23 0 0 21 2 0(2) Bottom 2 22 0 0 20 2 0(2) Left 3 20 10 0 0 2 8 TOTAL 83 16 2 42 7 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Table 134: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 22 11 0 1 2 8 Right 1 23 0 0 21 2 0(2) Bottom 2 26 0 0 24 2 0(2) Left 3 21 11 0 0 2 8 TOTAL 92 22 0 46 8 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 171

Spartan-3E FPGA Family: Pinout Descriptions Footprint Migration Differences Table135 summarizes any footprint and functionality the two pins have identical functionality. A left-facing arrow differences between the XC3S100E, the XC3S250E, and () indicates that the pin on the device on the right the XC3S500E FPGAs that may affect easy migration unconditionally migrates to the pin on the device on the left. between devices in the CP132 package. There are 14 such It may be possible to migrate the opposite direction balls. All other pins not listed in Table135 unconditionally depending on the I/O configuration. For example, an I/O pin migrate between Spartan-3E devices available in the (Type=I/O) can migrate to an input-only pin CP132 package. (Type=INPUT) if the I/O pin is configured as an input. The XC3S100E is duplicated on both the left and right sides The XC3S100E FPGA in the CP132 package has four fewer of the table to show migrations to and from the XC3S250E BPI-mode address lines than the XC3S250E and and the XC3S500E. The arrows indicate the direction for XC3S500E. easy migration. A double-ended arrow () indicates that Table 135: CP132 Footprint Migration Differences CP132 XC3S100E XC3S250E XC3S500E XC3S100E Bank Migration Migration Migration Ball Type Type Type Type A12 0 N.C.  I/O  I/O  N.C. B4 0 INPUT  I/O  I/O  INPUT B11 0 N.C.  I/O  I/O  N.C. B12 0 N.C.  I/O  I/O  N.C. C4 0 N.C.  I/O  I/O  N.C. C11 0 INPUT  I/O  I/O  INPUT D1 3 N.C.  I/O  I/O  N.C. D2 3 I/O  I/O (Diff)  I/O (Diff)  I/O K3 3 VREF(INPUT)  VREF(I/O)  VREF(I/O)  VREF(INPUT) M9 2 N.C.  DUAL  DUAL  N.C. M10 2 N.C.  DUAL  DUAL  N.C. N9 2 N.C.  DUAL  DUAL  N.C. N10 2 N.C.  DUAL  DUAL  N.C. P11 2 VREF(INPUT)  VREF(I/O)  VREF(I/O)  VREF(INPUT) DIFFERENCES 14 0 14 Legend:  This pin is identical on the device on the left and the right. This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be  possible depending on how the pin is configured for the device on the right. This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be  possible depending on how the pin is configured for the device on the left. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 172

Spartan-3E FPGA Family: Pinout Descriptions CP132 Footprint X-Ref Target - Figure 81 Bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/O I/O I/O I/O I/O I/O A PROG_B TDI GND VCCAUX VCCO_0 L07P_0 GND L05N_0 L04P_0 VCCINT L02N_0 TDO L11P_0 GCLK10 GCLK7 GCLK4  L01P_0 I/O I/O I/O INPUT I/O I/O I/O B L0I1/ON_3 L0I1/OP_3 HL1S1WNA_P0 L10P_0 L0I9/OP_0 L0I8/OP_0 GLC07LNK_101 LG0C6LPK_08 LG0C5LPK_60 VCCO_0 VLR03ENF__00 L02P_0 TCK TMS I/O I/O I/O I/O I/O INPUT I/O I/O I/O I/O I/O C GND L10N_0 L08N_0 GND L06N_0 L04N_0 GND L03P_0 L10N_1 L10P_1 L02N_3 L02P_3  L09N_0 VREF_0 GCLK9 GCLK5  L01N_0 LDC2 LDC1 I/O I/O I/O I/O D L03N_3 L03P_3 VCCINT L09N_1 L09P_1 VCCINT   LDC0 HDC E VCCO_3 INPUT GND VCCAUX VCCO_1 GND VREF_3 I/O I/O I/O I/O I/O I/O F L05P_3 L04N_3 L04P_3 L08N_1 L08P_1 A0 LHCLK2 LHCLK1 LHCLK0 A1 A2 3 I/O I/O I/O I/O nk G L05N_3 GND L06P_3 INPUT L07N_1 L07P_1 a LHCLK3 LHCLK4 VREF_1 A3 A4 B IRDY2 TRDY2 RHCLK7 RHCLK6 H L0I6/ON_3 L0I7/OP_3 L0I7/ON_3 L0I6/ON_1 L0IA6/OP6_1 GND nk 1 LHCLK5 LHCLK6 LHCLK7 RHAC5LK5 RIHRCDLYK14 Ba I/O I/O I/O J GND VCCO_3 I/O L04N_1 L05P_1 L05AN7_1 A9 A8 RHCLK3 RHCLK1 RHCLK2 TRDY1 I/O K VCCAUX VCCINT VRI/EOF_3 GND I/O L04P_1  VREF_1 A10 RHCLK0 I/O I/O I/O I/O I/O L VCCINT L03P_1 L03N_1 L08P_3 L08N_3 L09P_3 A12 A11 I/O I/O I/O INPUT I/O I/O I/O I/O I/O M L0I9/ON_3 L01P_2 GND L03DP7_2 L04DP4_2 RLD0W5PR__2B GND VCCO_2 L0A82N2_2 L0A92N0_2 L1V0SN1_2 L02P_1 L02N_1 VCCO_1 CSO_B GCLK12 GCLK14 GCLK0   A18 A14 A13 I/O I/O I/O I/O INPUT I/O I/O I/O I/O I/O I/O I/O N LIN01ITN__B2 LCM0S2ONI_S_BI2 VINREPFU_T2 GL0C3DLN6K_123 GL0C4DLN3K_125 LG0CM5LN2K_12 IM/O1 L0D7DIN0N_2 L0A82P3_2 L0A92P1_2 L1VA0S1P92_2 LC11CNL_K2 L0A11P6_1 L0A11N5_1 I/O I/O I/O I/O I/O I/O P L02P_2 VCCINT VCCO_2 I/O GND L06P_2 L06N_2 L07P_2 VCCAUX GND VREF_2 L11P_2 DONE GND DBOUSUYT D5 GCDL2K2 GCDL1K3 M0  VAS170 Bank 2 DS312-4_07_030206 Figure 81: CP132 Package Footprint (top view) 16- I/O: Unrestricted, general-purpose 42- DUAL: Configuration pin, then VREF: User I/O or input voltage 7-8 22 user I/O 46 possible user I/O reference for bank INPUT: Unrestricted, CLK: User I/O, input, or global VCCO: Output voltage supply for 0-2 16 8 general-purpose input pin buffer input bank CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply 2 4 6 pins voltage (+1.2V) N.C.: Unconnected balls on the GND: Ground VCCAUX: Auxiliary supply voltage 9 16 4 XC3S100E FPGA () (+2.5V) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 173

Spartan-3E FPGA Family: Pinout Descriptions TQ144: 144-lead Thin Quad Flat Package The XC3S100E and the XC3S250E FPGAs are available in The TQ144 package only supports 20 address output pins the 144-lead thin quad flat package, TQ144. Both devices in the Byte-wide Peripheral Interface (BPI) configuration share a common footprint for this package as shown in mode. In larger packages, there are 24 BPI address Table136 and Figure82. outputs. Table136 lists all the package pins. They are sorted by An electronic version of this package pinout table and bank number and then by pin name of the largest device. footprint diagram is available for download from the Xilinx Pins that form a differential I/O pair appear together in the web site at: table. The table also shows the pin number for each pin and http://www.xilinx.com/support/documentation/data_sheets the pin type, as defined earlier. /s3e_pin.zip Pinout Table Table 136: TQ144 Package Pinout Bank XC3S100E Pin Name XC3S250E Pin Name TQ144 Pin Type 0 IO IO P132 I/O 0 IO/VREF_0 IO/VREF_0 P124 VREF 0 IO_L01N_0 IO_L01N_0 P113 I/O 0 IO_L01P_0 IO_L01P_0 P112 I/O 0 IO_L02N_0 IO_L02N_0 P117 I/O 0 IO_L02P_0 IO_L02P_0 P116 I/O 0 IO_L04N_0/GCLK5 IO_L04N_0/GCLK5 P123 GCLK 0 IO_L04P_0/GCLK4 IO_L04P_0/GCLK4 P122 GCLK 0 IO_L05N_0/GCLK7 IO_L05N_0/GCLK7 P126 GCLK 0 IO_L05P_0/GCLK6 IO_L05P_0/GCLK6 P125 GCLK 0 IO_L07N_0/GCLK11 IO_L07N_0/GCLK11 P131 GCLK 0 IO_L07P_0/GCLK10 IO_L07P_0/GCLK10 P130 GCLK 0 IO_L08N_0/VREF_0 IO_L08N_0/VREF_0 P135 VREF 0 IO_L08P_0 IO_L08P_0 P134 I/O 0 IO_L09N_0 IO_L09N_0 P140 I/O 0 IO_L09P_0 IO_L09P_0 P139 I/O 0 IO_L10N_0/HSWAP IO_L10N_0/HSWAP P143 DUAL 0 IO_L10P_0 IO_L10P_0 P142 I/O 0 IP IP P111 INPUT 0 IP IP P114 INPUT 0 IP IP P136 INPUT 0 IP IP P141 INPUT 0 IP_L03N_0 IP_L03N_0 P120 INPUT 0 IP_L03P_0 IP_L03P_0 P119 INPUT 0 IP_L06N_0/GCLK9 IP_L06N_0/GCLK9 P129 GCLK 0 IP_L06P_0/GCLK8 IP_L06P_0/GCLK8 P128 GCLK 0 VCCO_0 VCCO_0 P121 VCCO 0 VCCO_0 VCCO_0 P138 VCCO 1 IO/A0 IO/A0 P98 DUAL 1 IO/VREF_1 IO/VREF_1 P83 VREF 1 IO_L01N_1/A15 IO_L01N_1/A15 P75 DUAL 1 IO_L01P_1/A16 IO_L01P_1/A16 P74 DUAL 1 IO_L02N_1/A13 IO_L02N_1/A13 P77 DUAL DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 174

Spartan-3E FPGA Family: Pinout Descriptions Table 136: TQ144 Package Pinout (Cont’d) Bank XC3S100E Pin Name XC3S250E Pin Name TQ144 Pin Type 1 IO_L02P_1/A14 IO_L02P_1/A14 P76 DUAL 1 IO_L03N_1/A11 IO_L03N_1/A11 P82 DUAL 1 IO_L03P_1/A12 IO_L03P_1/A12 P81 DUAL 1 IO_L04N_1/A9/RHCLK1 IO_L04N_1/A9/RHCLK1 P86 RHCLK/DUAL 1 IO_L04P_1/A10/RHCLK0 IO_L04P_1/A10/RHCLK0 P85 RHCLK/DUAL 1 IO_L05N_1/A7/RHCLK3/TRDY1 IO_L05N_1/A7/RHCLK3 P88 RHCLK/DUAL 1 IO_L05P_1/A8/RHCLK2 IO_L05P_1/A8/RHCLK2 P87 RHCLK/DUAL 1 IO_L06N_1/A5/RHCLK5 IO_L06N_1/A5/RHCLK5 P92 RHCLK/DUAL 1 IO_L06P_1/A6/RHCLK4/IRDY1 IO_L06P_1/A6/RHCLK4 P91 RHCLK/DUAL 1 IO_L07N_1/A3/RHCLK7 IO_L07N_1/A3/RHCLK7 P94 RHCLK/DUAL 1 IO_L07P_1/A4/RHCLK6 IO_L07P_1/A4/RHCLK6 P93 RHCLK/DUAL 1 IO_L08N_1/A1 IO_L08N_1/A1 P97 DUAL 1 IO_L08P_1/A2 IO_L08P_1/A2 P96 DUAL 1 IO_L09N_1/LDC0 IO_L09N_1/LDC0 P104 DUAL 1 IO_L09P_1/HDC IO_L09P_1/HDC P103 DUAL 1 IO_L10N_1/LDC2 IO_L10N_1/LDC2 P106 DUAL 1 IO_L10P_1/LDC1 IO_L10P_1/LDC1 P105 DUAL 1 IP IP P78 INPUT 1 IP IP P84 INPUT 1 IP IP P89 INPUT 1 IP IP P101 INPUT 1 IP IP P107 INPUT 1 IP/VREF_1 IP/VREF_1 P95 VREF 1 VCCO_1 VCCO_1 P79 VCCO 1 VCCO_1 VCCO_1 P100 VCCO 2 IO/D5 IO/D5 P52 DUAL 2 IO/M1 IO/M1 P60 DUAL 2 IP/VREF_2 IO/VREF_2 P66 100E: VREF(INPUT) 250E: VREF(I/O) 2 IO_L01N_2/INIT_B IO_L01N_2/INIT_B P40 DUAL 2 IO_L01P_2/CSO_B IO_L01P_2/CSO_B P39 DUAL 2 IO_L02N_2/MOSI/CSI_B IO_L02N_2/MOSI/CSI_B P44 DUAL 2 IO_L02P_2/DOUT/BUSY IO_L02P_2/DOUT/BUSY P43 DUAL 2 IO_L04N_2/D6/GCLK13 IO_L04N_2/D6/GCLK13 P51 DUAL/GCLK 2 IO_L04P_2/D7/GCLK12 IO_L04P_2/D7/GCLK12 P50 DUAL/GCLK 2 IO_L05N_2/D3/GCLK15 IO_L05N_2/D3/GCLK15 P54 DUAL/GCLK 2 IO_L05P_2/D4/GCLK14 IO_L05P_2/D4/GCLK14 P53 DUAL/GCLK 2 IO_L07N_2/D1/GCLK3 IO_L07N_2/D1/GCLK3 P59 DUAL/GCLK 2 IO_L07P_2/D2/GCLK2 IO_L07P_2/D2/GCLK2 P58 DUAL/GCLK 2 IO_L08N_2/DIN/D0 IO_L08N_2/DIN/D0 P63 DUAL 2 IO_L08P_2/M0 IO_L08P_2/M0 P62 DUAL 2 IO_L09N_2/VS1/A18 IO_L09N_2/VS1/A18 P68 DUAL 2 IO_L09P_2/VS2/A19 IO_L09P_2/VS2/A19 P67 DUAL 2 IO_L10N_2/CCLK IO_L10N_2/CCLK P71 DUAL 2 IO_L10P_2/VS0/A17 IO_L10P_2/VS0/A17 P70 DUAL DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 175

Spartan-3E FPGA Family: Pinout Descriptions Table 136: TQ144 Package Pinout (Cont’d) Bank XC3S100E Pin Name XC3S250E Pin Name TQ144 Pin Type 2 IP IP P38 INPUT 2 IP IP P41 INPUT 2 IP IP P69 INPUT 2 IP_L03N_2/VREF_2 IP_L03N_2/VREF_2 P48 VREF 2 IP_L03P_2 IP_L03P_2 P47 INPUT 2 IP_L06N_2/M2/GCLK1 IP_L06N_2/M2/GCLK1 P57 DUAL/GCLK 2 IP_L06P_2/RDWR_B/GCLK0 IP_L06P_2/RDWR_B/GCLK0 P56 DUAL/GCLK 2 VCCO_2 VCCO_2 P42 VCCO 2 VCCO_2 VCCO_2 P49 VCCO 2 VCCO_2 VCCO_2 P64 VCCO 3 IP/VREF_3 IO/VREF_3 P31 100E: VREF(INPUT) 250E: VREF(I/O) 3 IO_L01N_3 IO_L01N_3 P3 I/O 3 IO_L01P_3 IO_L01P_3 P2 I/O 3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 P5 VREF 3 IO_L02P_3 IO_L02P_3 P4 I/O 3 IO_L03N_3 IO_L03N_3 P8 I/O 3 IO_L03P_3 IO_L03P_3 P7 I/O 3 IO_L04N_3/LHCLK1 IO_L04N_3/LHCLK1 P15 LHCLK 3 IO_L04P_3/LHCLK0 IO_L04P_3/LHCLK0 P14 LHCLK 3 IO_L05N_3/LHCLK3/IRDY2 IO_L05N_3/LHCLK3 P17 LHCLK 3 IO_L05P_3/LHCLK2 IO_L05P_3/LHCLK2 P16 LHCLK 3 IO_L06N_3/LHCLK5 IO_L06N_3/LHCLK5 P21 LHCLK 3 IO_L06P_3/LHCLK4/TRDY2 IO_L06P_3/LHCLK4 P20 LHCLK 3 IO_L07N_3/LHCLK7 IO_L07N_3/LHCLK7 P23 LHCLK 3 IO_L07P_3/LHCLK6 IO_L07P_3/LHCLK6 P22 LHCLK 3 IO_L08N_3 IO_L08N_3 P26 I/O 3 IO_L08P_3 IO_L08P_3 P25 I/O 3 IO_L09N_3 IO_L09N_3 P33 I/O 3 IO_L09P_3 IO_L09P_3 P32 I/O 3 IO_L10N_3 IO_L10N_3 P35 I/O 3 IO_L10P_3 IO_L10P_3 P34 I/O 3 IP IP P6 INPUT 3 IO IP P10 100E: I/O 250E: INPUT 3 IP IP P18 INPUT 3 IP IP P24 INPUT 3 IO IP P29 100E: I/O 250E: INPUT 3 IP IP P36 INPUT 3 IP/VREF_3 IP/VREF_3 P12 VREF 3 VCCO_3 VCCO_3 P13 VCCO 3 VCCO_3 VCCO_3 P28 VCCO GND GND GND P11 GND GND GND GND P19 GND DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 176

Spartan-3E FPGA Family: Pinout Descriptions Table 136: TQ144 Package Pinout (Cont’d) Bank XC3S100E Pin Name XC3S250E Pin Name TQ144 Pin Type GND GND GND P27 GND GND GND GND P37 GND GND GND GND P46 GND GND GND GND P55 GND GND GND GND P61 GND GND GND GND P73 GND GND GND GND P90 GND GND GND GND P99 GND GND GND GND P118 GND GND GND GND P127 GND GND GND GND P133 GND VCCAUX DONE DONE P72 CONFIG VCCAUX PROG_B PROG_B P1 CONFIG VCCAUX TCK TCK P110 JTAG VCCAUX TDI TDI P144 JTAG VCCAUX TDO TDO P109 JTAG VCCAUX TMS TMS P108 JTAG VCCAUX VCCAUX VCCAUX P30 VCCAUX VCCAUX VCCAUX VCCAUX P65 VCCAUX VCCAUX VCCAUX VCCAUX P102 VCCAUX VCCAUX VCCAUX VCCAUX P137 VCCAUX VCCINT VCCINT VCCINT P9 VCCINT VCCINT VCCINT VCCINT P45 VCCINT VCCINT VCCINT VCCINT P80 VCCINT VCCINT VCCINT VCCINT P115 VCCINT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 177

Spartan-3E FPGA Family: Pinout Descriptions User I/Os by Bank Table137 and Table138 indicate how the 108 available user-I/O pins are distributed between the four I/O banks on the TQ144 package. Table 137: User I/Os Per Bank for the XC3S100E in the TQ144 Package Package All Possible I/O Pins by Type I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 26 9 6 1 2 8 Right 1 28 0 5 21 2 0(2) Bottom 2 26 0 4 20 2 0(2) Left 3 28 13 4 0 3 8 TOTAL 108 22 19 42 9 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Table 138: User I/Os Per Bank for the XC3S250E in TQ144 Package Package All Possible I/O Pins by Type I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 26 9 6 1 2 8 Right 1 28 0 5 21 2 0(2) Bottom 2 26 0 4 20 2 0(2) Left 3 28 11 6 0 3 8 TOTAL 108 20 21 42 9 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Footprint Migration Differences The arrows indicate the direction for easy migration. For example, a left-facing arrow indicates that the pin on the Table139 summarizes any footprint and functionality XC3S250E unconditionally migrates to the pin on the differences between the XC3S100E and the XC3S250E XC3S100E. It may be possible to migrate the opposite FPGAs that may affect easy migration between devices. direction depending on the I/O configuration. For example, There are four such pins. All other pins not listed in an I/O pin (Type=I/O) can migrate to an input-only pin Table139 unconditionally migrate between Spartan-3E (Type=INPUT) if the I/O pin is configured as an input. devices available in the TQ144 package. Table 139: TQ144 Footprint Migration Differences TQ144 Pin Bank XC3S100E Type Migration XC3S250E Type P10 3 I/O  INPUT P29 3 I/O  INPUT P31 3 VREF(INPUT)  VREF(I/O) P66 2 VREF(INPUT)  VREF(I/O) DIFFERENCES 4 Legend: This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may  be possible depending on how the pin is configured for the device on the right. This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may  be possible depending on how the pin is configured for the device on the left. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 178

Spartan-3E FPGA Family: Pinout Descriptions TQ144 Footprint Note pin 1 indicator in top-left corner and logo orientation. Double arrows () indicates a pinout migration difference between the XC3S100E and XC3S250E. X-Ref Target - Figure 82 HSWAP VREF_0 GCLK11GCLK10GCLK9GCLK8 GCLK7GCLK6 GCLK5GCLK4 TDIIO_L10N_0/IO_L10P_0IPIO_L09N_0IO_L09P_0VCCO_0VCCAUXIPIO_L08N_0/IO_L08P_0GNDIOIO_L07N_0/IO_L07P_0/IP_L06N_0/IP_L06P_0/GNDIO_L05N_0/IO_L05P_0/IO/VREF_0IO_L04N_0/IO_L04P_0/VCCO_0IP_L03N_0IP_L03P_0GNDIO_L02N_0IO_L02P_0VCCINTIPIO_L01N_0IO_L01P_0IPTCKTDO 432109876543210987654321098765432109 444443333333333222222222211111111110 111111111111111111111111111111111111 PROG_B 1 108TMS Bank0 IO_L01P_3 2 107IP IO_L01N_3 3 106IO_L10N_1/LDC2 IO_L02P_3 4 105IO_L10P_1/LDC1 IO_L02N_3/VREF_3 5 104IO_L09N_1/LDC0 IP 6 103IO_L09P_1/HDC IO_L03P_3 7 102VCCAUX IO_L03N_3 8 101IP VCCINT 9 100VCCO_1 ((cid:2)(cid:2)(cid:2)(cid:2)(cid:3)(cid:3)(cid:3)(cid:3))IP 10 99 GND GND 11 98 IO/A0 IP/VREF_3 12 97 IO_L08N_1/A1 VCCO_3 13 96 IO_L08P_1/A2 IO_L04P_3/LHCLK0 14 95 IP/VREF_1 IO_L04N_3/LHCLK1 15 94 IO_L07N_1/A3/RHCLK7 IO_L05P_3/LHCLK2 16 93 IO_L07P_1/A4/RHCLK6 IO_L05N_3/LHCLK3 17 1 92 IO_L06N_1/A5/RHCLK5 IP 18 3 k 91 IO_L06P_1/A6/RHCLK4 k n GND 19 n a 90 GND IO_L06P_3/LHCLK4 20 Ba B 89 IP IO_L06N_3/LHCLK5 21 88 IO_L05N_1/A7/RHCLK3 IO_L07P_3/LHCLK6 22 87 IO_L05P_1/A8/RHCLK2 IO_L07N_3/LHCLK7 23 86 IO_L04N_1/A9/RHCLK1 IP 24 85 IO_L04P_1/A10/RHCLK0 IO_L08P_3 25 84 IP IO_L08N_3 26 83 IO/VREF_1 GND 27 82 IO_L03N_1/A11 VCCO_3 28 81 IO_L03P_1/A12 ((cid:2)(cid:2)(cid:2)(cid:2)(cid:3)(cid:3)(cid:3)(cid:3))IP 29 80 VCCINT VCCAUX 30 79 VCCO_1 ((cid:2)(cid:2)(cid:2)(cid:2)(cid:3)(cid:3)(cid:3)(cid:3))IO/VREF_3 31 78 IP IO_L09P_3 32 77 IO_L02N_1/A13 IO_L09N_3 33 76 IO_L02P_1/A14 IO_L10P_3 34 75 IO_L01N_1/A15 IO_L10N_3 35 Bank2 74 IO_L01P_1/A16 IP 36 73 GND 789012345678901234567890123456789012 333444444444455555555556666666666777 GNDIPIO_L01P_2/CSO_BIO_L01N_2/INIT_BIPVCCO_2IO_L02P_2/DOUT/BUSYIO_L02N_2/MOSI/CSI_BVCCINTGNDIP_L03P_2IP_L03N_2/VREF_2VCCO_2IO_L04P_2/D7/GCLK12IO_L04N_2/D6/GCLK13IO/D5IO_L05P_2/D4/GCLK14IO_L05N_2/D3/GCLK15GNDL06P_2/RDWR_B/GCLK0IP_L06N_2/M2/GCLK1IO_L07P_2/D2/GCLK2IO_L07N_2/D1/GCLK3IO/M1GNDIO_L08P_2/M0IO_L08N_2/DIN/D0VCCO_2VCCAUX(cid:2)(cid:3)(cid:2)(cid:3)(cid:2)(cid:3)(cid:2)(cid:3)()IO/VREF_2IO_L09P_2/VS2/A19IO_L09N_2/VS1/A18IPIO_L10P_2/VS0/A17IO_L10N_2/CCLKDONE P_ DS312-4_01_082009 I Figure 82: TQ144 Package Footprint (top view) I/O: Unrestricted, general-purpose DUAL: Configuration pin, then VREF: User I/O or input voltage 20 42 9 user I/O possible user I/O reference for bank INPUT: Unrestricted, CLK: User I/O, input, or global VCCO: Output voltage supply for 21 16 9 general-purpose input pin buffer input bank CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply 2 4 4 pins voltage (+1.2V) N.C.: Not connected GND: Ground VCCAUX: Auxiliary supply voltage 0 13 4 (+2.5V) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 179

Spartan-3E FPGA Family: Pinout Descriptions PQ208: 208-pin Plastic Quad Flat Package The 208-pin plastic quad flat package, PQ208, supports two Table 140: PQ208 Package Pinout (Cont’d) different Spartan-3E FPGAs, including the XC3S250E and XC3S250E the XC3S500E. Bank XC3S500E PQ208 Type Pin Pin Name Table140 lists all the PQ208 package pins. They are sorted 0 IO_L15P_0 P202 I/O by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The 0 IO_L16N_0/HSWAP P206 DUAL table also shows the pin number for each pin and the pin 0 IO_L16P_0 P205 I/O type, as defined earlier. 0 IP P159 INPUT An electronic version of this package pinout table and 0 IP P169 INPUT footprint diagram is available for download from the Xilinx 0 IP P194 INPUT website at: 0 IP P204 INPUT http://www.xilinx.com/support/documentation/data_sheets 0 IP_L06N_0 P175 INPUT /s3e_pin.zip 0 IP_L06P_0 P174 INPUT 0 IP_L09N_0/GCLK9 P184 GCLK Pinout Table 0 IP_L09P_0/GCLK8 P183 GCLK Table 140: PQ208 Package Pinout 0 VCCO_0 P176 VCCO XC3S250E 0 VCCO_0 P191 VCCO PQ208 Bank XC3S500E Type Pin 0 VCCO_0 P201 VCCO Pin Name 1 IO_L01N_1/A15 P107 DUAL 0 IO P187 I/O 1 IO_L01P_1/A16 P106 DUAL 0 IO/VREF_0 P179 VREF 1 IO_L02N_1/A13 P109 DUAL 0 IO_L01N_0 P161 I/O 1 IO_L02P_1/A14 P108 DUAL 0 IO_L01P_0 P160 I/O 1 IO_L03N_1/VREF_1 P113 VREF 0 IO_L02N_0/VREF_0 P163 VREF 1 IO_L03P_1 P112 I/O 0 IO_L02P_0 P162 I/O 1 IO_L04N_1 P116 I/O 0 IO_L03N_0 P165 I/O 1 IO_L04P_1 P115 I/O 0 IO_L03P_0 P164 I/O 1 IO_L05N_1/A11 P120 DUAL 0 IO_L04N_0/VREF_0 P168 VREF 1 IO_L05P_1/A12 P119 DUAL 0 IO_L04P_0 P167 I/O 1 IO_L06N_1/VREF_1 P123 VREF 0 IO_L05N_0 P172 I/O 1 IO_L06P_1 P122 I/O 0 IO_L05P_0 P171 I/O 1 IO_L07N_1/A9/RHCLK1 P127 RHCLK/DUAL 0 IO_L07N_0/GCLK5 P178 GCLK 1 IO_L07P_1/A10/RHCLK0 P126 RHCLK/DUAL 0 IO_L07P_0/GCLK4 P177 GCLK 1 IO_L08N_1/A7/RHCLK3 P129 RHCLK/DUAL 0 IO_L08N_0/GCLK7 P181 GCLK 1 IO_L08P_1/A8/RHCLK2 P128 RHCLK/DUAL 0 IO_L08P_0/GCLK6 P180 GCLK 1 IO_L09N_1/A5/RHCLK5 P133 RHCLK/DUAL 0 IO_L10N_0/GCLK11 P186 GCLK 1 IO_L09P_1/A6/RHCLK4 P132 RHCLK/DUAL 0 IO_L10P_0/GCLK10 P185 GCLK 1 IO_L10N_1/A3/RHCLK7 P135 RHCLK/DUAL 0 IO_L11N_0 P190 I/O 1 IO_L10P_1/A4/RHCLK6 P134 RHCLK/DUAL 0 IO_L11P_0 P189 I/O 1 IO_L11N_1/A1 P138 DUAL 0 IO_L12N_0/VREF_0 P193 VREF 1 IO_L11P_1/A2 P137 DUAL 0 IO_L12P_0 P192 I/O 1 IO_L12N_1/A0 P140 DUAL 0 IO_L13N_0 P197 I/O 1 IO_L12P_1 P139 I/O 0 IO_L13P_0 P196 I/O 1 IO_L13N_1 P145 I/O 0 IO_L14N_0/VREF_0 P200 VREF 1 IO_L13P_1 P144 I/O 0 IO_L14P_0 P199 I/O 1 IO_L14N_1 P147 I/O 0 IO_L15N_0 P203 I/O 1 IO_L14P_1 P146 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 180

Spartan-3E FPGA Family: Pinout Descriptions Table 140: PQ208 Package Pinout (Cont’d) Table 140: PQ208 Package Pinout (Cont’d) XC3S250E XC3S250E PQ208 PQ208 Bank XC3S500E Type Bank XC3S500E Type Pin Pin Pin Name Pin Name 1 IO_L15N_1/LDC0 P151 DUAL 2 IO_L16P_2/VS2/A19 P99 DUAL 1 IO_L15P_1/HDC P150 DUAL 2 IO_L17N_2/CCLK P103 DUAL 1 IO_L16N_1/LDC2 P153 DUAL 2 IO_L17P_2/VS0/A17 P102 DUAL 1 IO_L16P_1/LDC1 P152 DUAL 2 IP P54 INPUT 1 IP P110 INPUT 2 IP P91 INPUT 1 IP P118 INPUT 2 IP P101 INPUT 1 IP P124 INPUT 2 IP_L02N_2 P58 INPUT 1 IP P130 INPUT 2 IP_L02P_2 P57 INPUT 1 IP P142 INPUT 2 IP_L07N_2/VREF_2 P72 VREF 1 IP P148 INPUT 2 IP_L07P_2 P71 INPUT 1 IP P154 INPUT 2 IP_L10N_2/M2/GCLK1 P81 DUAL/GCLK 1 IP/VREF_1 P136 VREF 2 IP_L10P_2/RDWR_B/ P80 DUAL/GCLK GCLK0 1 VCCO_1 P114 VCCO 2 VCCO_2 P59 VCCO 1 VCCO_1 P125 VCCO 2 VCCO_2 P73 VCCO 1 VCCO_1 P143 VCCO 2 VCCO_2 P88 VCCO 2 IO/D5 P76 DUAL 3 IO/VREF_3 P45 VREF 2 IO/M1 P84 DUAL 3 IO_L01N_3 P3 I/O 2 IO/VREF_2 P98 VREF 3 IO_L01P_3 P2 I/O 2 IO_L01N_2/INIT_B P56 DUAL 3 IO_L02N_3/VREF_3 P5 VREF 2 IO_L01P_2/CSO_B P55 DUAL 3 IO_L02P_3 P4 I/O 2 IO_L03N_2/MOSI/CSI_B P61 DUAL 3 IO_L03N_3 P9 I/O 2 IO_L03P_2/DOUT/BUSY P60 DUAL 3 IO_L03P_3 P8 I/O 2 IO_L04N_2 P63 I/O 3 IO_L04N_3 P12 I/O 2 IO_L04P_2 P62 I/O 3 IO_L04P_3 P11 I/O 2 IO_L05N_2 P65 I/O 3 IO_L05N_3 P16 I/O 2 IO_L05P_2 P64 I/O 3 IO_L05P_3 P15 I/O 2 IO_L06N_2 P69 I/O 3 IO_L06N_3 P19 I/O 2 IO_L06P_2 P68 I/O 3 IO_L06P_3 P18 I/O 2 IO_L08N_2/D6/GCLK13 P75 DUAL/GCLK 3 IO_L07N_3/LHCLK1 P23 LHCLK 2 IO_L08P_2/D7/GCLK12 P74 DUAL/GCLK 3 IO_L07P_3/LHCLK0 P22 LHCLK 2 IO_L09N_2/D3/GCLK15 P78 DUAL/GCLK 3 IO_L08N_3/LHCLK3 P25 LHCLK 2 IO_L09P_2/D4/GCLK14 P77 DUAL/GCLK 3 IO_L08P_3/LHCLK2 P24 LHCLK 2 IO_L11N_2/D1/GCLK3 P83 DUAL/GCLK 3 IO_L09N_3/LHCLK5 P29 LHCLK 2 IO_L11P_2/D2/GCLK2 P82 DUAL/GCLK 3 IO_L09P_3/LHCLK4 P28 LHCLK 2 IO_L12N_2/DIN/D0 P87 DUAL 3 IO_L10N_3/LHCLK7 P31 LHCLK 2 IO_L12P_2/M0 P86 DUAL 3 IO_L10P_3/LHCLK6 P30 LHCLK 2 IO_L13N_2 P90 I/O 3 IO_L11N_3 P34 I/O 2 IO_L13P_2 P89 I/O 3 IO_L11P_3 P33 I/O 2 IO_L14N_2/A22 P94 DUAL 3 IO_L12N_3 P36 I/O 2 IO_L14P_2/A23 P93 DUAL 3 IO_L12P_3 P35 I/O 2 IO_L15N_2/A20 P97 DUAL 3 IO_L13N_3 P40 I/O 2 IO_L15P_2/A21 P96 DUAL 3 IO_L13P_3 P39 I/O 2 IO_L16N_2/VS1/A18 P100 DUAL 3 IO_L14N_3 P42 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 181

Spartan-3E FPGA Family: Pinout Descriptions Table 140: PQ208 Package Pinout (Cont’d) Table 140: PQ208 Package Pinout (Cont’d) XC3S250E XC3S250E PQ208 PQ208 Bank XC3S500E Type Bank XC3S500E Type Pin Pin Pin Name Pin Name 3 IO_L14P_3 P41 I/O VCCAUX VCCAUX P66 VCCAUX 3 IO_L15N_3 P48 I/O VCCAUX VCCAUX P92 VCCAUX 3 IO_L15P_3 P47 I/O VCCAUX VCCAUX P111 VCCAUX 3 IO_L16N_3 P50 I/O VCCAUX VCCAUX P149 VCCAUX 3 IO_L16P_3 P49 I/O VCCAUX VCCAUX P166 VCCAUX 3 IP P6 INPUT VCCAUX VCCAUX P195 VCCAUX 3 IP P14 INPUT VCCINT VCCINT P13 VCCINT 3 IP P26 INPUT VCCINT VCCINT P67 VCCINT 3 IP P32 INPUT VCCINT VCCINT P117 VCCINT 3 IP P43 INPUT VCCINT VCCINT P170 VCCINT 3 IP P51 INPUT 3 IP/VREF_3 P20 VREF 3 VCCO_3 P21 VCCO 3 VCCO_3 P38 VCCO 3 VCCO_3 P46 VCCO GND GND P10 GND GND GND P17 GND GND GND P27 GND GND GND P37 GND GND GND P52 GND GND GND P53 GND GND GND P70 GND GND GND P79 GND GND GND P85 GND GND GND P95 GND GND GND P105 GND GND GND P121 GND GND GND P131 GND GND GND P141 GND GND GND P156 GND GND GND P173 GND GND GND P182 GND GND GND P188 GND GND GND P198 GND GND GND P208 GND VCCAUX DONE P104 CONFIG VCCAUX PROG_B P1 CONFIG VCCAUX TCK P158 JTAG VCCAUX TDI P207 JTAG VCCAUX TDO P157 JTAG VCCAUX TMS P155 JTAG VCCAUX VCCAUX P7 VCCAUX VCCAUX VCCAUX P44 VCCAUX DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 182

Spartan-3E FPGA Family: Pinout Descriptions User I/Os by Bank Footprint Migration Differences Table141 indicates how the 158 available user-I/O pins are The XC3S250E and XC3S500E FPGAs have identical distributed between the four I/O banks on the PQ208 footprints in the PQ208 package. Designs can migrate package. between the XC3S250E and XC3S500E without further consideration. Table 141: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 38 18 6 1 5 8 Right 1 40 9 7 21 3 0(2) Bottom 2 40 8 6 24 2 0(2) Left 3 40 23 6 0 3 8 TOTAL 158 58 25 46 13 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 183

Spartan-3E FPGA Family: Pinout Descriptions PQ208 Footprint (Left) X-Ref Target - Figure 83 SWAP REF_0 REF_0 CLK11 CLK10 CLK9 CLK8 H V V G G G G GND TDI IO_L16N_0/ IO_L16P_0 IP IO_L15N_0 IO_L15P_0 VCCO_0 IO_L14N_0/ IO_L14P_0 GND IO_L13N_0 IO_L13P_0 VCCAUX IP IO_L12N_0/ IO_L12P_0 VCCO_0 IO_L11N_0 IO_L11P_0 GND IO IO_L10N_0/ IO_L10P_0/ IP_L09N_0/ IP_L09P_0/ GND 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PROG_B 1 Bank0 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 5 IP 6 VCCAUX 7 IO_L03P_3 8 IO_L03N_3 9 GND 10 IO_L04P_3 11 IO_L04N_3 12 VCCINT 13 IP 14 IO_L05P_3 15 IO_L05N_3 16 GND 17 IO_L06P_3 18 IO_L06N_3 19 IP/VREF_3 20 VCCO_3 21 IO_L07P_3/LHCLK0 22 IO_L07N_3/LHCLK1 23 IO_L08P_3/LHCLK2 24 3 IO_L08N_3/LHCLK3 25 k n IP 26 a GND 27 B IO_L09P_3/LHCLK4 28 IO_L09N_3/LHCLK5 29 IO_L10P_3/LHCLK6 30 IO_L10N_3/LHCLK7 31 IP 32 IO_L11P_3 33 IO_L11N_3 34 IO_L12P_3 35 IO_L12N_3 36 GND 37 VCCO_3 38 IO_L13P_3 39 IO_L13N_3 40 IO_L14P_3 41 IO_L14N_3 42 IP 43 VCCAUX 44 IO/VREF_3 45 VCCO_3 46 IO_L15P_3 47 IO_L15N_3 48 IO_L16P_3 49 IO_L16N_3 50 IP 51 Bank2 GND 52 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 D P B B 2 2 2 Y B 2 2 2 2 X T 2 2 D 2 2 2 2 3 5 4 5 D DS312-4_03_030705 GN I IO_L01P_2/CSO_ IO_L01N_2/INIT_ IP_L02P_ IP_L02N_ VCCO_ IO_L03P_2/DOUT/BUS IO_L03N_2/MOSI/CSI_ IO_L04P_ IO_L04N_ IO_L05P_ IO_L05N_ VCCAU VCCIN IO_L06P_ IO_L06N_ GN IP_L07P_ IP_L07N_2/VREF_ VCCO_ IO_L08P_2/D7/GCLK1 IO_L08N_2/D6/GCLK1 IO/D IO_L09P_2/D4/GCLK1 IO_L09N_2/D3/GCLK1 GN Figure 83: PQ208 Footprint (Left) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 184

Spartan-3E FPGA Family: Pinout Descriptions PQ208 Footprint (Right) X-Ref Target - Figure 84 0 0 K7 K6 K5 K4 F_ F_ L L L L E E C C C C R R G G G G V V IO_L08N_0/ IO_L08P_0/ IO/VREF_0 IO_L07N_0/ IO_L07P_0/ VCCO_0 IP_L06N_0 IP_L06P_0 GND IO_L05N_0 IO_L05P_0 VCCINT IP IO_L04N_0/ IO_L04P_0 VCCAUX IO_L03N_0 IO_L03P_0 IO_L02N_0/ IO_L02P_0 IO_L01N_0 IO_L01P_0 IP TCK TDO 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 156GND Bank0 155TMS 154IP 153IO_L16N_1/LDC2 152IO_L16P_1/LDC1 151IO_L15N_1/LDC0 150IO_L15P_1/HDC 149VCCAUX 148IP 147IO_L14N_1 146IO_L14P_1 145IO_L13N_1 144IO_L13P_1 143VCCO_1 142IP 141GND 140IO_L12N_1/A0 139IO_L12P_1 138IO_L11N_1/A1 137IO_L11P_1/A2 136IP/VREF_1 135IO_L10N_1/A3/RHCLK7 134IO_L10P_1/A4/RHCLK6 133IO_L09N_1/A5/RHCLK5 1 132IO_L09P_1/A6/RHCLK4 k n 131GND a 130IP B 129IO_L08N_1/A7/RHCLK3 128IO_L08P_1/A8/RHCLK2 127IO_L07N_1/A9/RHCLK1 126IO_L07P_1/A10/RHCLK 125VCCO_1 124IP 123IO_L06N_1/VREF_1 122IO_L06P_1 121GND 120IO_L05N_1/A11 119IO_L05P_1/A12 118IP 117VCCINT 116IO_L04N_1 115IO_L04P_1 114VCCO_1 113IO_L03N_1/VREF_1 112IO_L03P_1 111VCCAUX 110IP 109IO_L02N_1/A13 108IO_L02P_1/A14 107IO_L01N_1/A15 106IO_L01P_1/A16 Bank2 105GND 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 1 1 1 1 1 0 1 2 3 1 D 0 0 2 2 2 P X 3 2 D 1 0 2 9 8 P 7 K E P_2/RDWR_B/GCLK P_L10N_2/M2/GCLK O_L11P_2/D2/GCLK O_L11N_2/D1/GCLK IO/M GN IO_L12P_2/M IO_L12N_2/DIN/D VCCO_ IO_L13P_ IO_L13N_ I VCCAU IO_L14P_2/A2 IO_L14N_2/A2 GN IO_L15P_2/A2 IO_L15N_2/A2 IO/VREF_ IO_L16P_2/VS2/A1 IO_L16N_2/VS1/A1 I IO_L17P_2/VS0/A1 IO_L17N_2/CCL DON 0 I I I 1 L _ P DS312-4_04_082009 I Figure 84: PQ208 Footprint (Right) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 185

Spartan-3E FPGA Family: Pinout Descriptions FT256: 256-ball Fine-pitch, Thin Ball Grid Array The 256-ball fine-pitch, thin ball grid array package, FT256, to a VREF pin on the XC3S500E and XC3S1200E FPGA. If supports three different Spartan-3E FPGAs, including the the FPGA application uses an I/O standard that requires a XC3S250E, the XC3S500E, and the XC3S1200E. VREF voltage reference, connect the highlighted pin to the VREF voltage supply, even though this does not actually Table142 lists all the package pins. They are sorted by connect to the XC3S250E FPGA. This VREF connection on bank number and then by pin name of the largest device. the board allows future migration to the larger devices Pins that form a differential I/O pair appear together in the without modifying the printed-circuit board. table. The table also shows the pin number for each pin and the pin type, as defined earlier. All other balls have nearly identical functionality on all three devices. Table146 summarizes the Spartan-3E footprint The highlighted rows indicate pinout differences between migration differences for the FT256 package. the XC3S250E, the XC3S500E, and the XC3S1200E FPGAs. The XC3S250E has 18 unconnected balls, An electronic version of this package pinout table and indicated as N.C. (No Connection) in Table142 and with the footprint diagram is available for download from the Xilinx black diamond character () in Table142 and Figure83. web site at: If the table row is highlighted in tan, then this is an instance http://www.xilinx.com/support/documentation/data_sheets where an unconnected pin on the XC3S250E FPGA maps /s3e_pin.zip Pinout Table Table 142: FT256 Package Pinout FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball 0 IO IO IO A7 I/O 0 IO IO IO A12 I/O 0 IO IO IO B4 I/O 0 IP IP IO B6 250E: INPUT 500E: INPUT 1200E: I/O 0 IP IP IO B10 250E: INPUT 500E: INPUT 1200E: I/O 0 IO/VREF_0 IO/VREF_0 IO/VREF_0 D9 VREF 0 IO_L01N_0 IO_L01N_0 IO_L01N_0 A14 I/O 0 IO_L01P_0 IO_L01P_0 IO_L01P_0 B14 I/O 0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 A13 VREF 0 IO_L03P_0 IO_L03P_0 IO_L03P_0 B13 I/O 0 IO_L04N_0 IO_L04N_0 IO_L04N_0 E11 I/O 0 IO_L04P_0 IO_L04P_0 IO_L04P_0 D11 I/O 0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 B11 VREF 0 IO_L05P_0 IO_L05P_0 IO_L05P_0 C11 I/O 0 IO_L06N_0 IO_L06N_0 IO_L06N_0 E10 I/O 0 IO_L06P_0 IO_L06P_0 IO_L06P_0 D10 I/O 0 IO_L08N_0/GCLK5 IO_L08N_0/GCLK5 IO_L08N_0/GCLK5 F9 GCLK 0 IO_L08P_0/GCLK4 IO_L08P_0/GCLK4 IO_L08P_0/GCLK4 E9 GCLK 0 IO_L09N_0/GCLK7 IO_L09N_0/GCLK7 IO_L09N_0/GCLK7 A9 GCLK 0 IO_L09P_0/GCLK6 IO_L09P_0/GCLK6 IO_L09P_0/GCLK6 A10 GCLK 0 IO_L11N_0/GCLK11 IO_L11N_0/GCLK11 IO_L11N_0/GCLK11 D8 GCLK 0 IO_L11P_0/GCLK10 IO_L11P_0/GCLK10 IO_L11P_0/GCLK10 C8 GCLK 0 IO_L12N_0 IO_L12N_0 IO_L12N_0 F8 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 186

Spartan-3E FPGA Family: Pinout Descriptions Table 142: FT256 Package Pinout (Cont’d) FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball 0 IO_L12P_0 IO_L12P_0 IO_L12P_0 E8 I/O 0 N.C. () IO_L13N_0 IO_L13N_0 C7 250E: N.C. 500E: I/O 1200E: I/O 0 N.C. () IO_L13P_0 IO_L13P_0 B7 250E: N.C. 500E: I/O 1200E: I/O 0 IO_L14N_0/VREF_0 IO_L14N_0/VREF_0 IO_L14N_0/VREF_0 D7 VREF 0 IO_L14P_0 IO_L14P_0 IO_L14P_0 E7 I/O 0 IO_L15N_0 IO_L15N_0 IO_L15N_0 D6 I/O 0 IO_L15P_0 IO_L15P_0 IO_L15P_0 C6 I/O 0 IO_L17N_0/VREF_0 IO_L17N_0/VREF_0 IO_L17N_0/VREF_0 A4 VREF 0 IO_L17P_0 IO_L17P_0 IO_L17P_0 A5 I/O 0 IO_L18N_0 IO_L18N_0 IO_L18N_0 C4 I/O 0 IO_L18P_0 IO_L18P_0 IO_L18P_0 C5 I/O 0 IO_L19N_0/HSWAP IO_L19N_0/HSWAP IO_L19N_0/HSWAP B3 DUAL 0 IO_L19P_0 IO_L19P_0 IO_L19P_0 C3 I/O 0 IP IP IP A3 INPUT 0 IP IP IP C13 INPUT 0 IP_L02N_0 IP_L02N_0 IP_L02N_0 C12 INPUT 0 IP_L02P_0 IP_L02P_0 IP_L02P_0 D12 INPUT 0 IP_L07N_0 IP_L07N_0 IP_L07N_0 C9 INPUT 0 IP_L07P_0 IP_L07P_0 IP_L07P_0 C10 INPUT 0 IP_L10N_0/GCLK9 IP_L10N_0/GCLK9 IP_L10N_0/GCLK9 B8 GCLK 0 IP_L10P_0/GCLK8 IP_L10P_0/GCLK8 IP_L10P_0/GCLK8 A8 GCLK 0 IP_L16N_0 IP_L16N_0 IP_L16N_0 E6 INPUT 0 IP_L16P_0 IP_L16P_0 IP_L16P_0 D5 INPUT 0 VCCO_0 VCCO_0 VCCO_0 B5 VCCO 0 VCCO_0 VCCO_0 VCCO_0 B12 VCCO 0 VCCO_0 VCCO_0 VCCO_0 F7 VCCO 0 VCCO_0 VCCO_0 VCCO_0 F10 VCCO 1 IO_L01N_1/A15 IO_L01N_1/A15 IO_L01N_1/A15 R15 DUAL 1 IO_L01P_1/A16 IO_L01P_1/A16 IO_L01P_1/A16 R16 DUAL 1 IO_L02N_1/A13 IO_L02N_1/A13 IO_L02N_1/A13 P15 DUAL 1 IO_L02P_1/A14 IO_L02P_1/A14 IO_L02P_1/A14 P16 DUAL 1 N.C. () IO_L03N_1/VREF_1 IO_L03N_1/VREF_1 N15 250E: N.C. 500E: VREF 1200E: VREF 1 N.C. () IO_L03P_1 IO_L03P_1 N14 250E: N.C. 500E: I/O 1200E: I/O 1 IO_L04N_1/VREF_1 IO_L04N_1/VREF_1 IO_L04N_1/VREF_1 M16 VREF 1 IO_L04P_1 IO_L04P_1 IO_L04P_1 N16 I/O 1 N.C. () IO_L05N_1 IO_L05N_1 L13 250E: N.C. 500E: I/O 1200E: I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 187

Spartan-3E FPGA Family: Pinout Descriptions Table 142: FT256 Package Pinout (Cont’d) FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball 1 N.C. () IO_L05P_1 IO_L05P_1 L12 250E: N.C. 500E: I/O 1200E: I/O 1 IO_L06N_1 IO_L06N_1 IO_L06N_1 L15 I/O 1 IO_L06P_1 IO_L06P_1 IO_L06P_1 L14 I/O 1 IO_L07N_1/A11 IO_L07N_1/A11 IO_L07N_1/A11 K12 DUAL 1 IO_L07P_1/A12 IO_L07P_1/A12 IO_L07P_1/A12 K13 DUAL 1 IO_L08N_1/VREF_1 IO_L08N_1/VREF_1 IO_L08N_1/VREF_1 K14 VREF 1 IO_L08P_1 IO_L08P_1 IO_L08P_1 K15 I/O 1 IO_L09N_1/A9/RHCLK1 IO_L09N_1/A9/RHCLK1 IO_L09N_1/A9/RHCLK1 J16 RHCLK/DUAL 1 IO_L09P_1/A10/RHCLK0 IO_L09P_1/A10/RHCLK0 IO_L09P_1/A10/RHCLK0 K16 RHCLK/DUAL 1 IO_L10N_1/A7/RHCLK3/ IO_L10N_1/A7/RHCLK3/ IO_L10N_1/A7/RHCLK3/ J13 RHCLK/DUAL TRDY1 TRDY1 TRDY1 1 IO_L10P_1/A8/RHCLK2 IO_L10P_1/A8/RHCLK2 IO_L10P_1/A8/RHCLK2 J14 RHCLK/DUAL 1 IO_L11N_1/A5/RHCLK5 IO_L11N_1/A5/RHCLK5 IO_L11N_1/A5/RHCLK5 H14 RHCLK/DUAL 1 IO_L11P_1/A6/RHCLK4/ IO_L11P_1/A6/RHCLK4/ IO_L11P_1/A6/RHCLK4/ H15 RHCLK/DUAL IRDY1 IRDY1 IRDY1 1 IO_L12N_1/A3/RHCLK7 IO_L12N_1/A3/RHCLK7 IO_L12N_1/A3/RHCLK7 H11 RHCLK/DUAL 1 IO_L12P_1/A4/RHCLK6 IO_L12P_1/A4/RHCLK6 IO_L12P_1/A4/RHCLK6 H12 RHCLK/DUAL 1 IO_L13N_1/A1 IO_L13N_1/A1 IO_L13N_1/A1 G16 DUAL 1 IO_L13P_1/A2 IO_L13P_1/A2 IO_L13P_1/A2 G15 DUAL 1 IO_L14N_1/A0 IO_L14N_1/A0 IO_L14N_1/A0 G14 DUAL 1 IO_L14P_1 IO_L14P_1 IO_L14P_1 G13 I/O 1 IO_L15N_1 IO_L15N_1 IO_L15N_1 F15 I/O 1 IO_L15P_1 IO_L15P_1 IO_L15P_1 F14 I/O 1 IO_L16N_1 IO_L16N_1 IO_L16N_1 F12 I/O 1 IO_L16P_1 IO_L16P_1 IO_L16P_1 F13 I/O 1 N.C. () IO_L17N_1 IO_L17N_1 E16 250E: N.C. 500E: I/O 1200E: I/O 1 N.C. (). IO_L17P_1 IO_L17P_1 E13 250E: N.C. 500E: I/O 1200E: I/O 1 IO_L18N_1/LDC0 IO_L18N_1/LDC0 IO_L18N_1/LDC0 D14 DUAL 1 IO_L18P_1/HDC IO_L18P_1/HDC IO_L18P_1/HDC D15 DUAL 1 IO_L19N_1/LDC2 IO_L19N_1/LDC2 IO_L19N_1/LDC2 C15 DUAL 1 IO_L19P_1/LDC1 IO_L19P_1/LDC1 IO_L19P_1/LDC1 C16 DUAL 1 IP IP IP B16 INPUT 1 IP IP IP E14 INPUT 1 IP IP IP G12 INPUT 1 IP IP IP H16 INPUT 1 IP IP IP J11 INPUT 1 IP IP IP J12 INPUT 1 IP IP IP M13 INPUT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 188

Spartan-3E FPGA Family: Pinout Descriptions Table 142: FT256 Package Pinout (Cont’d) FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball 1 IO IO IP M14 250E: I/O 500E: I/O 1200E: INPUT 1 IO/VREF_1 IP/VREF_1 IP/VREF_1 D16 250E: VREF(I/O) 500E: VREF(INPUT) 1200E: VREF(INPUT) 1 IP/VREF_1 IP/VREF_1 IP/VREF_1 H13 VREF 1 VCCO_1 VCCO_1 VCCO_1 E15 VCCO 1 VCCO_1 VCCO_1 VCCO_1 G11 VCCO 1 VCCO_1 VCCO_1 VCCO_1 K11 VCCO 1 VCCO_1 VCCO_1 VCCO_1 M15 VCCO 2 IP IP IO M7 250E: INPUT 500E: INPUT 1200E: I/O 2 IP IP IO T12 250E: INPUT 500E: INPUT 1200E: I/O 2 IO/D5 IO/D5 IO/D5 T8 DUAL 2 IO/M1 IO/M1 IO/M1 T10 DUAL 2 IO/VREF_2 IO/VREF_2 IO/VREF_2 P13 VREF 2 IO/VREF_2 IO/VREF_2 IO/VREF_2 R4 VREF 2 IO_L01N_2/INIT_B IO_L01N_2/INIT_B IO_L01N_2/INIT_B P4 DUAL 2 IO_L01P_2/CSO_B IO_L01P_2/CSO_B IO_L01P_2/CSO_B P3 DUAL 2 IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B N5 DUAL 2 IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY P5 DUAL 2 IO_L04N_2 IO_L04N_2 IO_L04N_2 T5 I/O 2 IO_L04P_2 IO_L04P_2 IO_L04P_2 T4 I/O 2 IO_L05N_2 IO_L05N_2 IO_L05N_2 N6 I/O 2 IO_L05P_2 IO_L05P_2 IO_L05P_2 M6 I/O 2 IO_L06N_2 IO_L06N_2 IO_L06N_2 P6 I/O 2 IO_L06P_2 IO_L06P_2 IO_L06P_2 R6 I/O 2 N.C. () IO_L07N_2 IO_L07N_2 P7 250E: N.C. 500E: I/O 1200E: I/O 2 N.C. () IO_L07P_2 IO_L07P_2 N7 250E: N.C. 500E: I/O 1200E: I/O 2 IO_L09N_2/D6/GCLK13 IO_L09N_2/D6/GCLK13 IO_L09N_2/D6/GCLK13 L8 DUAL/GCLK 2 IO_L09P_2/D7/GCLK12 IO_L09P_2/D7/GCLK12 IO_L09P_2/D7/GCLK12 M8 DUAL/GCLK 2 IO_L10N_2/D3/GCLK15 IO_L10N_2/D3/GCLK15 IO_L10N_2/D3/GCLK15 P8 DUAL/GCLK 2 IO_L10P_2/D4/GCLK14 IO_L10P_2/D4/GCLK14 IO_L10P_2/D4/GCLK14 N8 DUAL/GCLK 2 IO_L12N_2/D1/GCLK3 IO_L12N_2/D1/GCLK3 IO_L12N_2/D1/GCLK3 N9 DUAL/GCLK 2 IO_L12P_2/D2/GCLK2 IO_L12P_2/D2/GCLK2 IO_L12P_2/D2/GCLK2 P9 DUAL/GCLK 2 IO_L13N_2/DIN/D0 IO_L13N_2/DIN/D0 IO_L13N_2/DIN/D0 M9 DUAL 2 IO_L13P_2/M0 IO_L13P_2/M0 IO_L13P_2/M0 L9 DUAL DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 189

Spartan-3E FPGA Family: Pinout Descriptions Table 142: FT256 Package Pinout (Cont’d) FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball 2 N.C. () IO_L14N_2/VREF_2 IO_L14N_2/VREF_2 R10 250E: N.C. 500E: VREF 1200E: VREF 2 N.C. () IO_L14P_2 IO_L14P_2 P10 250E: N.C. 500E: I/O 1200E: I/O 2 IO_L15N_2 IO_L15N_2 IO_L15N_2 M10 I/O 2 IO_L15P_2 IO_L15P_2 IO_L15P_2 N10 I/O 2 IO_L16N_2/A22 IO_L16N_2/A22 IO_L16N_2/A22 P11 DUAL 2 IO_L16P_2/A23 IO_L16P_2/A23 IO_L16P_2/A23 R11 DUAL 2 IO_L18N_2/A20 IO_L18N_2/A20 IO_L18N_2/A20 N12 DUAL 2 IO_L18P_2/A21 IO_L18P_2/A21 IO_L18P_2/A21 P12 DUAL 2 IO_L19N_2/VS1/A18 IO_L19N_2/VS1/A18 IO_L19N_2/VS1/A18 R13 DUAL 2 IO_L19P_2/VS2/A19 IO_L19P_2/VS2/A19 IO_L19P_2/VS2/A19 T13 DUAL 2 IO_L20N_2/CCLK IO_L20N_2/CCLK IO_L20N_2/CCLK R14 DUAL 2 IO_L20P_2/VS0/A17 IO_L20P_2/VS0/A17 IO_L20P_2/VS0/A17 P14 DUAL 2 IP IP IP T2 INPUT 2 IP IP IP T14 INPUT 2 IP_L02N_2 IP_L02N_2 IP_L02N_2 R3 INPUT 2 IP_L02P_2 IP_L02P_2 IP_L02P_2 T3 INPUT 2 IP_L08N_2/VREF_2 IP_L08N_2/VREF_2 IP_L08N_2/VREF_2 T7 VREF 2 IP_L08P_2 IP_L08P_2 IP_L08P_2 R7 INPUT 2 IP_L11N_2/M2/GCLK1 IP_L11N_2/M2/GCLK1 IP_L11N_2/M2/GCLK1 R9 DUAL/GCLK 2 IP_L11P_2/RDWR_B/ IP_L11P_2/RDWR_B/ IP_L11P_2/RDWR_B/ T9 DUAL/GCLK GCLK0 GCLK0 GCLK0 2 IP_L17N_2 IP_L17N_2 IP_L17N_2 M11 INPUT 2 IP_L17P_2 IP_L17P_2 IP_L17P_2 N11 INPUT 2 VCCO_2 VCCO_2 VCCO_2 L7 VCCO 2 VCCO_2 VCCO_2 VCCO_2 L10 VCCO 2 VCCO_2 VCCO_2 VCCO_2 R5 VCCO 2 VCCO_2 VCCO_2 VCCO_2 R12 VCCO 3 IO_L01N_3 IO_L01N_3 IO_L01N_3 B2 I/O 3 IO_L01P_3 IO_L01P_3 IO_L01P_3 B1 I/O 3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 C2 VREF 3 IO_L02P_3 IO_L02P_3 IO_L02P_3 C1 I/O 3 IO_L03N_3 IO_L03N_3 IO_L03N_3 E4 I/O 3 IO_L03P_3 IO_L03P_3 IO_L03P_3 E3 I/O 3 N.C. () IO_L04N_3/VREF_3 IO_L04N_3/VREF_3 F4 250E: N.C. 500E: VREF 1200E: VREF 3 N.C. () IO_L04P_3 IO_L04P_3 F3 250E: N.C. 500E: I/O 1200E: I/O 3 IO_L05N_3 IO_L05N_3 IO_L05N_3 E1 I/O 3 IO_L05P_3 IO_L05P_3 IO_L05P_3 D1 I/O 3 IO_L06N_3 IO_L06N_3 IO_L06N_3 G4 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 190

Spartan-3E FPGA Family: Pinout Descriptions Table 142: FT256 Package Pinout (Cont’d) FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball 3 IO_L06P_3 IO_L06P_3 IO_L06P_3 G5 I/O 3 IO_L07N_3 IO_L07N_3 IO_L07N_3 G2 I/O 3 IO_L07P_3 IO_L07P_3 IO_L07P_3 G3 I/O 3 IO_L08N_3/LHCLK1 IO_L08N_3/LHCLK1 IO_L08N_3/LHCLK1 H6 LHCLK 3 IO_L08P_3/LHCLK0 IO_L08P_3/LHCLK0 IO_L08P_3/LHCLK0 H5 LHCLK 3 IO_L09N_3/LHCLK3/ IO_L09N_3/LHCLK3/ IO_L09N_3/LHCLK3/ H4 LHCLK IRDY2 IRDY2 IRDY2 3 IO_L09P_3/LHCLK2 IO_L09P_3/LHCLK2 IO_L09P_3/LHCLK2 H3 LHCLK 3 IO_L10N_3/LHCLK5 IO_L10N_3/LHCLK5 IO_L10N_3/LHCLK5 J3 LHCLK 3 IO_L10P_3/LHCLK4/ IO_L10P_3/LHCLK4/ IO_L10P_3/LHCLK4/ J2 LHCLK TRDY2 TRDY2 TRDY2 3 IO_L11N_3/LHCLK7 IO_L11N_3/LHCLK7 IO_L11N_3/LHCLK7 J4 LHCLK 3 IO_L11P_3/LHCLK6 IO_L11P_3/LHCLK6 IO_L11P_3/LHCLK6 J5 LHCLK 3 IO_L12N_3 IO_L12N_3 IO_L12N_3 K1 I/O 3 IO_L12P_3 IO_L12P_3 IO_L12P_3 J1 I/O 3 IO_L13N_3 IO_L13N_3 IO_L13N_3 K3 I/O 3 IO_L13P_3 IO_L13P_3 IO_L13P_3 K2 I/O 3 N.C. () IO_L14N_3/VREF_3 IO_L14N_3/VREF_3 L2 250E: N.C. 500E: VREF 1200E: VREF 3 N.C. () IO_L14P_3 IO_L14P_3 L3 250E: N.C. 500E: I/O 1200E: I/O 3 IO_L15N_3 IO_L15N_3 IO_L15N_3 L5 I/O 3 IO_L15P_3 IO_L15P_3 IO_L15P_3 K5 I/O 3 IO_L16N_3 IO_L16N_3 IO_L16N_3 N1 I/O 3 IO_L16P_3 IO_L16P_3 IO_L16P_3 M1 I/O 3 N.C. () IO_L17N_3 IO_L17N_3 L4 250E: N.C. 500E: I/O 1200E: I/O 3 N.C. () IO_L17P_3 IO_L17P_3 M4 250E: N.C. 500E: I/O 1200E: I/O 3 IO_L18N_3 IO_L18N_3 IO_L18N_3 P1 I/O 3 IO_L18P_3 IO_L18P_3 IO_L18P_3 P2 I/O 3 IO_L19N_3 IO_L19N_3 IO_L19N_3 R1 I/O 3 IO_L19P_3 IO_L19P_3 IO_L19P_3 R2 I/O 3 IP IP IP D2 INPUT 3 IP IP IP F2 INPUT 3 IO IO IP F5 250E: I/O 500E: I/O 1200E: INPUT 3 IP IP IP H1 INPUT 3 IP IP IP J6 INPUT 3 IP IP IP K4 INPUT 3 IP IP IP M3 INPUT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 191

Spartan-3E FPGA Family: Pinout Descriptions Table 142: FT256 Package Pinout (Cont’d) FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball 3 IP IP IP N3 INPUT 3 IP/VREF_3 IP/VREF_3 IP/VREF_3 G1 VREF 3 IO/VREF_3 IO/VREF_3 IP/VREF_3 N2 250E: VREF(I/O) 500E: VREF(I/O) 1200E: VREF(INPUT) 3 VCCO_3 VCCO_3 VCCO_3 E2 VCCO 3 VCCO_3 VCCO_3 VCCO_3 G6 VCCO 3 VCCO_3 VCCO_3 VCCO_3 K6 VCCO 3 VCCO_3 VCCO_3 VCCO_3 M2 VCCO GND GND GND GND A1 GND GND GND GND GND A16 GND GND GND GND GND B9 GND GND GND GND GND F6 GND GND GND GND GND F11 GND GND GND GND GND G7 GND GND GND GND GND G8 GND GND GND GND GND G9 GND GND GND GND GND G10 GND GND GND GND GND H2 GND GND GND GND GND H7 GND GND GND GND GND H8 GND GND GND GND GND H9 GND GND GND GND GND H10 GND GND GND GND GND J7 GND GND GND GND GND J8 GND GND GND GND GND J9 GND GND GND GND GND J10 GND GND GND GND GND J15 GND GND GND GND GND K7 GND GND GND GND GND K8 GND GND GND GND GND K9 GND GND GND GND GND K10 GND GND GND GND GND L6 GND GND GND GND GND L11 GND GND GND GND GND R8 GND GND GND GND GND T1 GND GND GND GND GND T16 GND VCCAUX DONE DONE DONE T15 CONFIG VCCAUX PROG_B PROG_B PROG_B D3 CONFIG VCCAUX TCK TCK TCK A15 JTAG VCCAUX TDI TDI TDI A2 JTAG VCCAUX TDO TDO TDO C14 JTAG VCCAUX TMS TMS TMS B15 JTAG VCCAUX VCCAUX VCCAUX VCCAUX A6 VCCAUX DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 192

Spartan-3E FPGA Family: Pinout Descriptions Table 142: FT256 Package Pinout (Cont’d) FT256 Bank XC3S250E Pin Name XC3S500E Pin Name XC3S1200E Pin Name Type Ball VCCAUX VCCAUX VCCAUX VCCAUX A11 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX F1 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX F16 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX L1 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX L16 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX T6 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX T11 VCCAUX VCCINT VCCINT VCCINT VCCINT D4 VCCINT VCCINT VCCINT VCCINT VCCINT D13 VCCINT VCCINT VCCINT VCCINT VCCINT E5 VCCINT VCCINT VCCINT VCCINT VCCINT E12 VCCINT VCCINT VCCINT VCCINT VCCINT M5 VCCINT VCCINT VCCINT VCCINT VCCINT M12 VCCINT VCCINT VCCINT VCCINT VCCINT N4 VCCINT VCCINT VCCINT VCCINT VCCINT N13 VCCINT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 193

Spartan-3E FPGA Family: Pinout Descriptions User I/Os by Bank The XC3S250E FPGA in the FT256 package has 18 unconnected balls, labeled with an “N.C.” type. These pins Table143, Table144, and Table145 indicate how the are also indicated with the black diamond () symbol in available user-I/O pins are distributed between the four I/O Figure85. banks on the FT256 package. Table 143: User I/Os Per Bank on XC3S250E in the FT256 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 44 20 10 1 5 8 Right 1 42 10 7 21 4 0(2) Bottom 2 44 8 9 24 3 0(2) Left 3 42 24 7 0 3 8 TOTAL 172 62 33 46 15 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Table 144: User I/Os Per Bank on XC3S500E in the FT256 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 46 22 10 1 5 8 Right 1 48 15 7 21 5 0(2) Bottom 2 48 11 9 24 4 0(2) Left 3 48 28 7 0 5 8 TOTAL 190 76 33 46 19 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. .Table 145: User I/Os Per Bank on XC3S1200E in the FT256 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 46 24 8 1 5 8 Right 1 48 14 8 21 5 0(2) Bottom 2 48 13 7 24 4 0(2) Left 3 48 27 8 0 5 8 TOTAL 190 78 31 46 19 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 194

Spartan-3E FPGA Family: Pinout Descriptions Footprint Migration Differences Table146 summarizes any footprint and functionality and the XC3S1200E. The arrows indicate the direction for differences between the XC3S250E, the XC3S500E, and easy migration. A double-ended arrow () indicates that the XC3S1200E FPGAs that may affect easy migration the two pins have identical functionality. A left-facing arrow between devices in the FG256 package. There are 26 such () indicates that the pin on the device on the right balls. All other pins not listed in Table146 unconditionally unconditionally migrates to the pin on the device on the left. migrate between Spartan-3E devices available in the FT256 It may be possible to migrate the opposite direction package. depending on the I/O configuration. For example, an I/O pin (Type=I/O) can migrate to an input-only pin The XC3S250E is duplicated on both the left and right sides (Type=INPUT) if the I/O pin is configured as an input. of the table to show migrations to and from the XC3S500E Table 146: FT256 Footprint Migration Differences FT256 XC3S250E XC3S250E Bank Migration XC3S500E Type Migration XC3S1200E Type Migration Ball Type Type B6 0 INPUT  INPUT  I/O  INPUT B7 0 N.C.  I/O  I/O  N.C. B10 0 INPUT  INPUT  I/O  INPUT C7 0 N.C.  I/O  I/O  N.C. D16 1 VREF(I/O)  VREF(INPUT)  VREF(INPUT)  VREF(I/O) E13 1 N.C.  I/O  I/O  N.C. E16 1 N.C.  I/O  I/O  N.C. F3 3 N.C.  I/O  I/O  N.C. F4 3 N.C.  VREF  VREF  N.C. F5 3 I/O  I/O  INPUT  I/O L2 3 N.C.  VREF  VREF  N.C. L3 3 N.C.  I/O  I/O  N.C. L4 3 N.C.  I/O  I/O  N.C. L12 1 N.C.  I/O  I/O  N.C. L13 1 N.C.  I/O  I/O  N.C. M4 3 N.C.  I/O  I/O  N.C. M7 2 INPUT  INPUT  I/O  INPUT M14 1 I/O  I/O  INPUT  I/O N2 3 VREF(I/O)  VREF(I/O)  VREF(INPUT)  VREF(I/O) N7 2 N.C.  I/O  I/O  N.C. N14 1 N.C.  I/O  I/O  N.C. N15 1 N.C.  VREF  VREF  N.C. P7 2 N.C.  I/O  I/O  N.C. P10 2 N.C.  I/O  I/O  N.C. R10 2 N.C.  VREF  VREF  N.C. T12 2 INPUT  INPUT  I/O  INPUT DIFFERENCES 19 7 26 Legend:  This pin is identical on the device on the left and the right. This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be  possible depending on how the pin is configured for the device on the right. This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be  possible depending on how the pin is configured for the device on the left. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 195

Spartan-3E FPGA Family: Pinout Descriptions FT256 Footprint X-Ref Target - Figure 85 Bank0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O INPUT I/O I/O I/O I/O I/O A GND TDI INPUT L17N_0 VCCAUX I/O L10P_0 L09N_0 L09P_0 VCCAUX I/O L03N_0 TCK GND L17P_0 L01N_0 VREF_0 GCLK8 GCLK7 GCLK6 VREF_0 I/O I/O I/O INPUT I/O INPUT INPUT I/O I/O I/O B L01P_3 L01N_3 HL1S9WNA_0P I/O VCCO_0  L13P_0 LG1C0LNK_90 GND  VLR05ENF__00 VCCO_0 L03P_0 L01P_0 TMS INPUT I/O I/O I/O I/O I/O C I/O L02N_3 I/O I/O I/O I/O L13N_0 L11P_0 INPUT INPUT I/O INPUT INPUT TDO L19N_1 L19P_1 L02P_3 VREF_3 L19P_0 L18N_0 L18P_0 L15P_0  GCLK10 L07N_0 L07P_0 L05P_0 L02N_0 LDC2 LDC1 I/O I/O I/O I/O INPUT I/O INPUT I/O I/O I/O I/O INPUT D INPUT PROG_B VCCINT L14N_0 L11N_0 VCCINT L18N_1 L18P_1 VREF_1 L05P_3 L16P_0 L15N_0 VREF_0 GCLK11 VREF_0 L06P_0 L04P_0 L02P_0 LDC0 HDC  I/O I/O I/O I/O I/O I/O INPUT I/O I/O I/O I/O E VCCO_3 VCCINT L08P_0 VCCINT L17P_1 INPUT VCCO_1 L17N_1 L05N_3 L03P_3 L03N_3 L16N_0 L14P_0 L12P_0 GCLK4 L06N_0 L04N_0   F VCCAUX INPUT L0I4/OP_ 3 VLR0I4E/ONF__ 33 INPUT GND VCCO_0 L1I2/ON_ 0 LG0CI8/LONK_ 5 0 VCCO_0 GND L1I6/ON_ 1 L1I6/OP_ 1 L1I5/OP_ 1 L1I5/ON_ 1 VCCAUX I/O I/O I/O INPUT I/O I/O I/O I/O I/O G VCCO_3 GND GND GND GND VCCO_1 INPUT L14N_1 L13P_1 L13N_1 VREF_3 L07N_3 L07P_3 L06N_3 L06P_3 L14P_1 A0 A2 A1 I/O I/O I/O I/O I/O I/O I/O I/O k3 H INPUT GND LLH09CPL_K32 LLIHR09CDNLY_K233 LLH08CPL_K30 LLH08CNL_K31 GND GND GND GND RLH12ACN3L _K 1 7 RLH12ACP4L_ K 1 6 VINRPEFU_T1 RLH11ACN5L _K 1 5 RLIH1R1ACDP6LY_ K 11 4 INPUT k1 an I/O I/O I/O I/O I/O I/O I/O an B J I/O L10P_3 L10N_3 L11N_3 L11P_3 INPUT GND GND GND GND INPUT INPUT L10AN7 _ 1 L10P_1 GND L09N_1 B L12P_3 LTHRCDLYK24 LHCLK5 LHCLK7 LHCLK6 RTHRCDLYK13 RHAC8L K 2 RHAC9L K 1 I/O I/O I/O I/O K I/O I/O I/O INPUT I/O VCCO_3 GND GND GND GND VCCO_1 L07N_1 L07P_1 L08N_1 I/O L09P_1 L12N_3 L13P_3 L13N_3 L15P_3 L08P_1 A10 A11 A12 VREF_1 RHCLK0 I/O I/O I/O I/O I/O I/O I/O L VCCAUX VLR14ENF__33 L14P_3 L17N_3 L1I5/ON_ 3 GND VCCO_2 GL0C9DLN6K_ 1 2 3 L1M3P0_2 VCCO_2 GND L05P_1 L05N_1 L0I6/OP_ 1 L0I6/ON_ 1 VCCAUX M L1I6/OP_ 3 VCCO_3 INPUT L1I7/OP_ 3 VCCINT L0I5/OP_ 2 INPUT L0ID9/OP7_ 2 L1DI3/IONN_ 2 L1I5/ON_ 2 ILN17PNU_T2 VCCINT INPUT INPUT VCCO_1 L0I4/ON_ 1  GCLK12 D0 VREF_1 INPUT I/O I/O I/O I/O I/O I/O I/O N L1I6/ON_ 3 VREF_3 INPUT VCCINT LCM0S3ONI_S_BI2 L0I5/ON_ 2 L07P_2 GL1CD0LP4K_ 1 2 4 LG1C2DLN1K_ 32 L1I5/OP_ 2 ILN1P7PU_T2 L1A82N0_2 VCCINT L03P_1 VLR03ENF__11 L0I4/OP_ 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P I/O I/O L01P_2 L01N_2 L03P_2 I/O L07N_2 L10N_2 L12P_2 L14P_2 L16N_2 L18P_2 I/O L20P_2 L02N_1 L02P_1 L18N_3 L18P_3 CSO_B INIT_B DBOUSUYT L06N_2  GCDL3K 1 5 GCDL2K 2  A22 A21 VREF_2 VAS170 A13 A14 INPUT I/O I/O I/O I/O I/O I/O R L1I9/ON_ 3 L1I9/OP_ 3 ILN02PNU_T2 VRIE/OF_ 2 VCCO_2 L0I6/OP_ 2 ILN0P8PU_T2 GND L1M1N2_ 2 VLR14ENF__22 L16P_2 VCCO_2 L1V9SN1_ 2 L20N_2 L01N_1 L01P_1 GCLK1  A23 A18 CCLK A15 A16 T GND INPUT ILN0P2PU_T2 L0I4/OP_ 2 L0I4/ON_ 2 VCCAUX ILN08PNU_T2 ID/O5 RILND1W1PPUR__T2B IM/O1 VCCAUX INPUT L1VI9/SOP2_ 2 INPUT DONE GND VREF_2 GCLK0 A19 Bank 2 DS312-4_05_101805 Figure 85: FT256 Package Footprint (top view) CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply 2 4 8 pins voltage (+1.2V) GND: Ground VCCO: Output voltage supply for VCCAUX: Auxiliary supply voltage 28 16 8 bank (+2.5V) 6 Migration Difference: For flexible 18 Unconnected pins on XC3S250E package migration, use these pins  as inputs. () DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 196

Spartan-3E FPGA Family: Pinout Descriptions FG320: 320-ball Fine-pitch Ball Grid Array The 320-ball fine-pitch ball grid array package, FG320, If the table row is highlighted in tan, then this is an instance supports three different Spartan-3E FPGAs, including the where an unconnected pin on the XC3S500E FPGA maps XC3S500E, the XC3S1200E, and the XC3S1600E, as to a VREF pin on the XC3S1200E and XC3S1600E FPGA. shown in Table147 and Figure86. If the FPGA application uses an I/O standard that requires a VREF voltage reference, connect the highlighted pin to the The FG320 package is an 18x18 array of solder balls VREF voltage supply, even though this does not actually minus the four center balls. connect to the XC3S500E FPGA. This VREF connection on Table147 lists all the package pins. They are sorted by the board allows future migration to the larger devices bank number and then by pin name of the largest device. without modifying the printed-circuit board. Pins that form a differential I/O pair appear together in the All other balls have nearly identical functionality on all three table. The table also shows the pin number for each pin and devices. Table146 summarizes the Spartan-3E footprint the pin type, as defined earlier. migration differences for the FG320 package. The highlighted rows indicate pinout differences between An electronic version of this package pinout table and the XC3S500E, the XC3S1200E, and the XC3S1600E footprint diagram is available for download from the Xilinx FPGAs. The XC3S500E has 18 unconnected balls, web site at: indicated as N.C. (No Connection) in Table147 and with the black diamond character () in Table147 and Figure86. http://www.xilinx.com/support/documentation/data_sheets /s3e_pin.zip Pinout Table Table 147: FG320 Package Pinout FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 0 IP IO IO A7 500E: INPUT 1200E: I/O 1600E: I/O 0 IO IO IO A8 I/O 0 IO IO IO A11 I/O 0 N.C. () IO IO A12 500E: N.C. 1200E: I/O 1600E: I/O 0 IO IO IO C4 I/O 0 IP IO IO D13 500E: INPUT 1200E: I/O 1600E: I/O 0 IO IO IO E13 I/O 0 IO IO IO G9 I/O 0 IO/VREF_0 IO/VREF_0 IO/VREF_0 B11 VREF 0 IO_L01N_0 IO_L01N_0 IO_L01N_0 A16 I/O 0 IO_L01P_0 IO_L01P_0 IO_L01P_0 B16 I/O 0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 IO_L03N_0/VREF_0 C14 VREF 0 IO_L03P_0 IO_L03P_0 IO_L03P_0 D14 I/O 0 IO_L04N_0 IO_L04N_0 IO_L04N_0 A14 I/O 0 IO_L04P_0 IO_L04P_0 IO_L04P_0 B14 I/O 0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 IO_L05N_0/VREF_0 B13 VREF 0 IO_L05P_0 IO_L05P_0 IO_L05P_0 A13 I/O 0 IO_L06N_0 IO_L06N_0 IO_L06N_0 E12 I/O 0 IO_L06P_0 IO_L06P_0 IO_L06P_0 F12 I/O 0 IO_L08N_0 IO_L08N_0 IO_L08N_0 F11 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 197

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 0 IO_L08P_0 IO_L08P_0 IO_L08P_0 E11 I/O 0 IO_L09N_0 IO_L09N_0 IO_L09N_0 D11 I/O 0 IO_L09P_0 IO_L09P_0 IO_L09P_0 C11 I/O 0 IO_L11N_0/GCLK5 IO_L11N_0/GCLK5 IO_L11N_0/GCLK5 E10 GCLK 0 IO_L11P_0/GCLK4 IO_L11P_0/GCLK4 IO_L11P_0/GCLK4 D10 GCLK 0 IO_L12N_0/GCLK7 IO_L12N_0/GCLK7 IO_L12N_0/GCLK7 A10 GCLK 0 IO_L12P_0/GCLK6 IO_L12P_0/GCLK6 IO_L12P_0/GCLK6 B10 GCLK 0 IO_L14N_0/GCLK11 IO_L14N_0/GCLK11 IO_L14N_0/GCLK11 D9 GCLK 0 IO_L14P_0/GCLK10 IO_L14P_0/GCLK10 IO_L14P_0/GCLK10 C9 GCLK 0 IO_L15N_0 IO_L15N_0 IO_L15N_0 F9 I/O 0 IO_L15P_0 IO_L15P_0 IO_L15P_0 E9 I/O 0 IO_L17N_0 IO_L17N_0 IO_L17N_0 F8 I/O 0 IO_L17P_0 IO_L17P_0 IO_L17P_0 E8 I/O 0 IO_L18N_0/VREF_0 IO_L18N_0/VREF_0 IO_L18N_0/VREF_0 D7 VREF 0 IO_L18P_0 IO_L18P_0 IO_L18P_0 C7 I/O 0 IO_L19N_0/VREF_0 IO_L19N_0/VREF_0 IO_L19N_0/VREF_0 E7 VREF 0 IO_L19P_0 IO_L19P_0 IO_L19P_0 F7 I/O 0 IO_L20N_0 IO_L20N_0 IO_L20N_0 A6 I/O 0 IO_L20P_0 IO_L20P_0 IO_L20P_0 B6 I/O 0 N.C. () IO_L21N_0 IO_L21N_0 E6 500E: N.C. 1200E: I/O 1600E: I/O 0 N.C. () IO_L21P_0 IO_L21P_0 D6 500E: N.C. 1200E: I/O 1600E: I/O 0 IO_L23N_0/VREF_0 IO_L23N_0/VREF_0 IO_L23N_0/VREF_0 D5 VREF 0 IO_L23P_0 IO_L23P_0 IO_L23P_0 C5 I/O 0 IO_L24N_0 IO_L24N_0 IO_L24N_0 B4 I/O 0 IO_L24P_0 IO_L24P_0 IO_L24P_0 A4 I/O 0 IO_L25N_0/HSWAP IO_L25N_0/HSWAP IO_L25N_0/HSWAP B3 DUAL 0 IO_L25P_0 IO_L25P_0 IO_L25P_0 C3 I/O 0 IP IP IP A3 INPUT 0 IP IP IP C15 INPUT 0 IP_L02N_0 IP_L02N_0 IP_L02N_0 A15 INPUT 0 IP_L02P_0 IP_L02P_0 IP_L02P_0 B15 INPUT 0 IP_L07N_0 IP_L07N_0 IP_L07N_0 D12 INPUT 0 IP_L07P_0 IP_L07P_0 IP_L07P_0 C12 INPUT 0 IP_L10N_0 IP_L10N_0 IP_L10N_0 G10 INPUT 0 IP_L10P_0 IP_L10P_0 IP_L10P_0 F10 INPUT 0 IP_L13N_0/GCLK9 IP_L13N_0/GCLK9 IP_L13N_0/GCLK9 B9 GCLK 0 IP_L13P_0/GCLK8 IP_L13P_0/GCLK8 IP_L13P_0/GCLK8 B8 GCLK 0 IP_L16N_0 IP_L16N_0 IP_L16N_0 D8 INPUT 0 IP_L16P_0 IP_L16P_0 IP_L16P_0 C8 INPUT 0 IP_L22N_0 IP_L22N_0 IP_L22N_0 B5 INPUT 0 IP_L22P_0 IP_L22P_0 IP_L22P_0 A5 INPUT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 198

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 0 VCCO_0 VCCO_0 VCCO_0 A9 VCCO 0 VCCO_0 VCCO_0 VCCO_0 C6 VCCO 0 VCCO_0 VCCO_0 VCCO_0 C13 VCCO 0 VCCO_0 VCCO_0 VCCO_0 G8 VCCO 0 VCCO_0 VCCO_0 VCCO_0 G11 VCCO 1 N.C. () IO IO P16 500E: N.C. 1200E: I/O 1600E: I/O 1 IO_L01N_1/A15 IO_L01N_1/A15 IO_L01N_1/A15 T17 DUAL 1 IO_L01P_1/A16 IO_L01P_1/A16 IO_L01P_1/A16 U18 DUAL 1 IO_L02N_1/A13 IO_L02N_1/A13 IO_L02N_1/A13 T18 DUAL 1 IO_L02P_1/A14 IO_L02P_1/A14 IO_L02P_1/A14 R18 DUAL 1 IO_L03N_1/VREF_1 IO_L03N_1/VREF_1 IO_L03N_1/VREF_1 R16 VREF 1 IO_L03P_1 IO_L03P_1 IO_L03P_1 R15 I/O 1 N.C. () IO_L04N_1 IO_L04N_1 N14 500E: N.C. 1200E: I/O 1600E: I/O 1 N.C. () IO_L04P_1 IO_L04P_1 N15 500E: N.C. 1200E: I/O 1600E: I/O 1 IO_L05N_1/VREF_1 IO_L05N_1/VREF_1 IO_L05N_1/VREF_1 M13 VREF 1 IO_L05P_1 IO_L05P_1 IO_L05P_1 M14 I/O 1 IO_L06N_1 IO_L06N_1 IO_L06N_1 P18 I/O 1 IO_L06P_1 IO_L06P_1 IO_L06P_1 P17 I/O 1 IO_L07N_1 IO_L07N_1 IO_L07N_1 M16 I/O 1 IO_L07P_1 IO_L07P_1 IO_L07P_1 M15 I/O 1 IO_L08N_1 IO_L08N_1 IO_L08N_1 M18 I/O 1 IO_L08P_1 IO_L08P_1 IO_L08P_1 N18 I/O 1 IO_L09N_1/A11 IO_L09N_1/A11 IO_L09N_1/A11 L15 DUAL 1 IO_L09P_1/A12 IO_L09P_1/A12 IO_L09P_1/A12 L16 DUAL 1 IO_L10N_1/VREF_1 IO_L10N_1/VREF_1 IO_L10N_1/VREF_1 L17 VREF 1 IO_L10P_1 IO_L10P_1 IO_L10P_1 L18 I/O 1 IO_L11N_1/A9/RHCLK1 IO_L11N_1/A9/RHCLK1 IO_L11N_1/A9/RHCLK1 K12 RHCLK/DUAL 1 IO_L11P_1/A10/RHCLK0 IO_L11P_1/A10/RHCLK0 IO_L11P_1/A10/RHCLK0 K13 RHCLK/DUAL 1 IO_L12N_1/A7/RHCLK3/ IO_L12N_1/A7/RHCLK3/ IO_L12N_1/A7/RHCLK3/ K14 RHCLK/DUAL TRDY1 TRDY1 TRDY1 1 IO_L12P_1/A8/RHCLK2 IO_L12P_1/A8/RHCLK2 IO_L12P_1/A8/RHCLK2 K15 RHCLK/DUAL 1 IO_L13N_1/A5/RHCLK5 IO_L13N_1/A5/RHCLK5 IO_L13N_1/A5/RHCLK5 J16 RHCLK/DUAL 1 IO_L13P_1/A6/RHCLK4/ IO_L13P_1/A6/RHCLK4/ IO_L13P_1/A6/RHCLK4/ J17 RHCLK/DUAL IRDY1 IRDY1 IRDY1 1 IO_L14N_1/A3/RHCLK7 IO_L14N_1/A3/RHCLK7 IO_L14N_1/A3/RHCLK7 J14 RHCLK/DUAL 1 IO_L14P_1/A4/RHCLK6 IO_L14P_1/A4/RHCLK6 IO_L14P_1/A4/RHCLK6 J15 RHCLK/DUAL 1 IO_L15N_1/A1 IO_L15N_1/A1 IO_L15N_1/A1 J13 DUAL 1 IO_L15P_1/A2 IO_L15P_1/A2 IO_L15P_1/A2 J12 DUAL 1 IO_L16N_1/A0 IO_L16N_1/A0 IO_L16N_1/A0 H17 DUAL 1 IO_L16P_1 IO_L16P_1 IO_L16P_1 H16 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 199

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 1 IO_L17N_1 IO_L17N_1 IO_L17N_1 H15 I/O 1 IO_L17P_1 IO_L17P_1 IO_L17P_1 H14 I/O 1 IO_L18N_1 IO_L18N_1 IO_L18N_1 G16 I/O 1 IO_L18P_1 IO_L18P_1 IO_L18P_1 G15 I/O 1 IO_L19N_1 IO_L19N_1 IO_L19N_1 F17 I/O 1 IO_L19P_1 IO_L19P_1 IO_L19P_1 F18 I/O 1 IO_L20N_1 IO_L20N_1 IO_L20N_1 G13 I/O 1 IO_L20P_1 IO_L20P_1 IO_L20P_1 G14 I/O 1 IO_L21N_1 IO_L21N_1 IO_L21N_1 F14 I/O 1 IO_L21P_1 IO_L21P_1 IO_L21P_1 F15 I/O 1 N.C. () IO_L22N_1 IO_L22N_1 E16 500E: N.C. 1200E: I/O 1600E: I/O 1 N.C. () IO_L22P_1 IO_L22P_1 E15 500E: N.C. 1200E: I/O 1600E: I/O 1 IO_L23N_1/LDC0 IO_L23N_1/LDC0 IO_L23N_1/LDC0 D16 DUAL 1 IO_L23P_1/HDC IO_L23P_1/HDC IO_L23P_1/HDC D17 DUAL 1 IO_L24N_1/LDC2 IO_L24N_1/LDC2 IO_L24N_1/LDC2 C17 DUAL 1 IO_L24P_1/LDC1 IO_L24P_1/LDC1 IO_L24P_1/LDC1 C18 DUAL 1 IP IP IP B18 INPUT 1 IO IP IP E17 500E: I/O 1200E: INPUT 1600E: INPUT 1 IP IP IP E18 INPUT 1 IP IP IP G18 INPUT 1 IP IP IP H13 INPUT 1 IP IP IP K17 INPUT 1 IP IP IP K18 INPUT 1 IP IP IP L13 INPUT 1 IP IP IP L14 INPUT 1 IP IP IP N17 INPUT 1 IO IP IP P15 500E: I/O 1200E: INPUT 1600E: INPUT 1 IP IP IP R17 INPUT 1 IP/VREF_1 IP/VREF_1 IP/VREF_1 D18 VREF 1 IP/VREF_1 IP/VREF_1 IP/VREF_1 H18 VREF 1 VCCO_1 VCCO_1 VCCO_1 F16 VCCO 1 VCCO_1 VCCO_1 VCCO_1 H12 VCCO 1 VCCO_1 VCCO_1 VCCO_1 J18 VCCO 1 VCCO_1 VCCO_1 VCCO_1 L12 VCCO 1 VCCO_1 VCCO_1 VCCO_1 N16 VCCO 2 IO IO IO P9 I/O 2 IO IO IO R11 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 200

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 2 IP IO IO U6 500E: INPUT 1200E: I/O 1600E: I/O 2 IP IO IO U13 500E: INPUT 1200E: I/O 1600E: I/O 2 N.C. () IO IO V7 500E: N.C. 1200E: I/O 1600E: I/O 2 IO/D5 IO/D5 IO/D5 R9 DUAL 2 IO/M1 IO/M1 IO/M1 V11 DUAL 2 IO/VREF_2 IO/VREF_2 IO/VREF_2 T15 VREF 2 IO/VREF_2 IO/VREF_2 IO/VREF_2 U5 VREF 2 IO_L01N_2/INIT_B IO_L01N_2/INIT_B IO_L01N_2/INIT_B T3 DUAL 2 IO_L01P_2/CSO_B IO_L01P_2/CSO_B IO_L01P_2/CSO_B U3 DUAL 2 IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B IO_L03N_2/MOSI/CSI_B T4 DUAL 2 IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY IO_L03P_2/DOUT/BUSY U4 DUAL 2 IO_L04N_2 IO_L04N_2 IO_L04N_2 T5 I/O 2 IO_L04P_2 IO_L04P_2 IO_L04P_2 R5 I/O 2 IO_L05N_2 IO_L05N_2 IO_L05N_2 P6 I/O 2 IO_L05P_2 IO_L05P_2 IO_L05P_2 R6 I/O 2 N.C. () IO_L06N_2/VREF_2 IO_L06N_2/VREF_2 V6 500E: N.C. 1200E: VREF 1600E: VREF 2 N.C. () IO_L06P_2 IO_L06P_2 V5 500E: N.C. 1200E: I/O 1600E: I/O 2 IO_L07N_2 IO_L07N_2 IO_L07N_2 P7 I/O 2 IO_L07P_2 IO_L07P_2 IO_L07P_2 N7 I/O 2 IO_L09N_2 IO_L09N_2 IO_L09N_2 N8 I/O 2 IO_L09P_2 IO_L09P_2 IO_L09P_2 P8 I/O 2 IO_L10N_2 IO_L10N_2 IO_L10N_2 T8 I/O 2 IO_L10P_2 IO_L10P_2 IO_L10P_2 R8 I/O 2 IO_L12N_2/D6/GCLK13 IO_L12N_2/D6/GCLK13 IO_L12N_2/D6/GCLK13 M9 DUAL/GCLK 2 IO_L12P_2/D7/GCLK12 IO_L12P_2/D7/GCLK12 IO_L12P_2/D7/GCLK12 N9 DUAL/GCLK 2 IO_L13N_2/D3/GCLK15 IO_L13N_2/D3/GCLK15 IO_L13N_2/D3/GCLK15 V9 DUAL/GCLK 2 IO_L13P_2/D4/GCLK14 IO_L13P_2/D4/GCLK14 IO_L13P_2/D4/GCLK14 U9 DUAL/GCLK 2 IO_L15N_2/D1/GCLK3 IO_L15N_2/D1/GCLK3 IO_L15N_2/D1/GCLK3 P10 DUAL/GCLK 2 IO_L15P_2/D2/GCLK2 IO_L15P_2/D2/GCLK2 IO_L15P_2/D2/GCLK2 R10 DUAL/GCLK 2 IO_L16N_2/DIN/D0 IO_L16N_2/DIN/D0 IO_L16N_2/DIN/D0 N10 DUAL 2 IO_L16P_2/M0 IO_L16P_2/M0 IO_L16P_2/M0 M10 DUAL 2 IO_L18N_2 IO_L18N_2 IO_L18N_2 N11 I/O 2 IO_L18P_2 IO_L18P_2 IO_L18P_2 P11 I/O 2 IO_L19N_2/VREF_2 IO_L19N_2/VREF_2 IO_L19N_2/VREF_2 V13 VREF 2 IO_L19P_2 IO_L19P_2 IO_L19P_2 V12 I/O 2 IO_L20N_2 IO_L20N_2 IO_L20N_2 R12 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 201

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 2 IO_L20P_2 IO_L20P_2 IO_L20P_2 T12 I/O 2 N.C. () IO_L21N_2 IO_L21N_2 P12 500E: N.C. 1200E: I/O 1600E: I/O 2 N.C. () IO_L21P_2 IO_L21P_2 N12 500E: N.C. 1200E: I/O 1600E: I/O 2 IO_L22N_2/A22 IO_L22N_2/A22 IO_L22N_2/A22 R13 DUAL 2 IO_L22P_2/A23 IO_L22P_2/A23 IO_L22P_2/A23 P13 DUAL 2 IO_L24N_2/A20 IO_L24N_2/A20 IO_L24N_2/A20 R14 DUAL 2 IO_L24P_2/A21 IO_L24P_2/A21 IO_L24P_2/A21 T14 DUAL 2 IO_L25N_2/VS1/A18 IO_L25N_2/VS1/A18 IO_L25N_2/VS1/A18 U15 DUAL 2 IO_L25P_2/VS2/A19 IO_L25P_2/VS2/A19 IO_L25P_2/VS2/A19 V15 DUAL 2 IO_L26N_2/CCLK IO_L26N_2/CCLK IO_L26N_2/CCLK U16 DUAL 2 IO_L26P_2/VS0/A17 IO_L26P_2/VS0/A17 IO_L26P_2/VS0/A17 T16 DUAL 2 IP IP IP V2 INPUT 2 IP IP IP V16 INPUT 2 IP_L02N_2 IP_L02N_2 IP_L02N_2 V3 INPUT 2 IP_L02P_2 IP_L02P_2 IP_L02P_2 V4 INPUT 2 IP_L08N_2 IP_L08N_2 IP_L08N_2 R7 INPUT 2 IP_L08P_2 IP_L08P_2 IP_L08P_2 T7 INPUT 2 IP_L11N_2/VREF_2 IP_L11N_2/VREF_2 IP_L11N_2/VREF_2 V8 VREF 2 IP_L11P_2 IP_L11P_2 IP_L11P_2 U8 INPUT 2 IP_L14N_2/M2/GCLK1 IP_L14N_2/M2/GCLK1 IP_L14N_2/M2/GCLK1 T10 DUAL/GCLK 2 IP_L14P_2/RDWR_B/ IP_L14P_2/RDWR_B/ IP_L14P_2/RDWR_B/ U10 DUAL/GCLK GCLK0 GCLK0 GCLK0 2 IP_L17N_2 IP_L17N_2 IP_L17N_2 U11 INPUT 2 IP_L17P_2 IP_L17P_2 IP_L17P_2 T11 INPUT 2 IP_L23N_2 IP_L23N_2 IP_L23N_2 U14 INPUT 2 IP_L23P_2 IP_L23P_2 IP_L23P_2 V14 INPUT 2 VCCO_2 VCCO_2 VCCO_2 M8 VCCO 2 VCCO_2 VCCO_2 VCCO_2 M11 VCCO 2 VCCO_2 VCCO_2 VCCO_2 T6 VCCO 2 VCCO_2 VCCO_2 VCCO_2 T13 VCCO 2 VCCO_2 VCCO_2 VCCO_2 V10 VCCO 3 N.C. () IO IO D4 500E: N.C. 1200E: I/O 1600E: I/O 3 IO_L01N_3 IO_L01N_3 IO_L01N_3 C2 I/O 3 IO_L01P_3 IO_L01P_3 IO_L01P_3 C1 I/O 3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 D2 VREF 3 IO_L02P_3 IO_L02P_3 IO_L02P_3 D1 I/O 3 IO_L03N_3 IO_L03N_3 IO_L03N_3 E1 I/O 3 IO_L03P_3 IO_L03P_3 IO_L03P_3 E2 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 202

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 3 N.C. () IO_L04N_3 IO_L04N_3 E3 500E: N.C. 1200E: I/O 1600E: I/O 3 N.C. () IO_L04P_3 IO_L04P_3 E4 500E: N.C. 1200E: I/O 1600E: I/O 3 IO_L05N_3 IO_L05N_3 IO_L05N_3 F2 I/O 3 IO_L05P_3 IO_L05P_3 IO_L05P_3 F1 I/O 3 IO_L06N_3/VREF_3 IO_L06N_3/VREF_3 IO_L06N_3/VREF_3 G4 VREF 3 IO_L06P_3 IO_L06P_3 IO_L06P_3 G3 I/O 3 IO_L07N_3 IO_L07N_3 IO_L07N_3 G5 I/O 3 IO_L07P_3 IO_L07P_3 IO_L07P_3 G6 I/O 3 IO_L08N_3 IO_L08N_3 IO_L08N_3 H5 I/O 3 IO_L08P_3 IO_L08P_3 IO_L08P_3 H6 I/O 3 IO_L09N_3 IO_L09N_3 IO_L09N_3 H3 I/O 3 IO_L09P_3 IO_L09P_3 IO_L09P_3 H4 I/O 3 IO_L10N_3 IO_L10N_3 IO_L10N_3 H1 I/O 3 IO_L10P_3 IO_L10P_3 IO_L10P_3 H2 I/O 3 IO_L11N_3/LHCLK1 IO_L11N_3/LHCLK1 IO_L11N_3/LHCLK1 J4 LHCLK 3 IO_L11P_3/LHCLK0 IO_L11P_3/LHCLK0 IO_L11P_3/LHCLK0 J5 LHCLK 3 IO_L12N_3/LHCLK3/ IO_L12N_3/LHCLK3/ IO_L12N_3/LHCLK3/ J2 LHCLK IRDY2 IRDY2 IRDY2 3 IO_L12P_3/LHCLK2 IO_L12P_3/LHCLK2 IO_L12P_3/LHCLK2 J1 LHCLK 3 IO_L13N_3/LHCLK5 IO_L13N_3/LHCLK5 IO_L13N_3/LHCLK5 K4 LHCLK 3 IO_L13P_3/LHCLK4/ IO_L13P_3/LHCLK4/ IO_L13P_3/LHCLK4/ K3 LHCLK TRDY2 TRDY2 TRDY2 3 IO_L14N_3/LHCLK7 IO_L14N_3/LHCLK7 IO_L14N_3/LHCLK7 K5 LHCLK 3 IO_L14P_3/LHCLK6 IO_L14P_3/LHCLK6 IO_L14P_3/LHCLK6 K6 LHCLK 3 IO_L15N_3 IO_L15N_3 IO_L15N_3 L2 I/O 3 IO_L15P_3 IO_L15P_3 IO_L15P_3 L1 I/O 3 IO_L16N_3 IO_L16N_3 IO_L16N_3 L4 I/O 3 IO_L16P_3 IO_L16P_3 IO_L16P_3 L3 I/O 3 IO_L17N_3/VREF_3 IO_L17N_3/VREF_3 IO_L17N_3/VREF_3 L5 VREF 3 IO_L17P_3 IO_L17P_3 IO_L17P_3 L6 I/O 3 IO_L18N_3 IO_L18N_3 IO_L18N_3 M3 I/O 3 IO_L18P_3 IO_L18P_3 IO_L18P_3 M4 I/O 3 IO_L19N_3 IO_L19N_3 IO_L19N_3 M6 I/O 3 IO_L19P_3 IO_L19P_3 IO_L19P_3 M5 I/O 3 IO_L20N_3 IO_L20N_3 IO_L20N_3 N5 I/O 3 IO_L20P_3 IO_L20P_3 IO_L20P_3 N4 I/O 3 IO_L21N_3 IO_L21N_3 IO_L21N_3 P1 I/O 3 IO_L21P_3 IO_L21P_3 IO_L21P_3 P2 I/O 3 N.C. () IO_L22N_3 IO_L22N_3 P4 500E: N.C. 1200E: I/O 1600E: I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 203

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball 3 N.C. () IO_L22P_3 IO_L22P_3 P3 500E: N.C. 1200E: I/O 1600E: I/O 3 IO_L23N_3 IO_L23N_3 IO_L23N_3 R2 I/O 3 IO_L23P_3 IO_L23P_3 IO_L23P_3 R3 I/O 3 IO_L24N_3 IO_L24N_3 IO_L24N_3 T1 I/O 3 IO_L24P_3 IO_L24P_3 IO_L24P_3 T2 I/O 3 IP IP IP D3 INPUT 3 IO IP IP F4 500E: I/O 1200E: INPUT 1600E: INPUT 3 IP IP IP F5 INPUT 3 IP IP IP G1 INPUT 3 IP IP IP J7 INPUT 3 IP IP IP K2 INPUT 3 IP IP IP K7 INPUT 3 IP IP IP M1 INPUT 3 IP IP IP N1 INPUT 3 IP IP IP N2 INPUT 3 IP IP IP R1 INPUT 3 IP IP IP U1 INPUT 3 IP/VREF_3 IP/VREF_3 IP/VREF_3 J6 VREF 3 IO/VREF_3 IP/VREF_3 IP/VREF_3 R4 500E: VREF(I/O) 1200E: VREF(INPUT) 1600E: VREF(INPUT) 3 VCCO_3 VCCO_3 VCCO_3 F3 VCCO 3 VCCO_3 VCCO_3 VCCO_3 H7 VCCO 3 VCCO_3 VCCO_3 VCCO_3 K1 VCCO 3 VCCO_3 VCCO_3 VCCO_3 L7 VCCO 3 VCCO_3 VCCO_3 VCCO_3 N3 VCCO GND GND GND GND A1 GND GND GND GND GND A18 GND GND GND GND GND B2 GND GND GND GND GND B17 GND GND GND GND GND C10 GND GND GND GND GND G7 GND GND GND GND GND G12 GND GND GND GND GND H8 GND GND GND GND GND H9 GND GND GND GND GND H10 GND GND GND GND GND H11 GND GND GND GND GND J3 GND GND GND GND GND J8 GND GND GND GND GND J11 GND DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 204

Spartan-3E FPGA Family: Pinout Descriptions Table 147: FG320 Package Pinout (Cont’d) FG320 Bank XC3S500E Pin Name XC3S1200E Pin Name XC3S1600E Pin Name Type Ball GND GND GND GND K8 GND GND GND GND GND K11 GND GND GND GND GND K16 GND GND GND GND GND L8 GND GND GND GND GND L9 GND GND GND GND GND L10 GND GND GND GND GND L11 GND GND GND GND GND M7 GND GND GND GND GND M12 GND GND GND GND GND T9 GND GND GND GND GND U2 GND GND GND GND GND U17 GND GND GND GND GND V1 GND GND GND GND GND V18 GND VCCAUX DONE DONE DONE V17 CONFIG VCCAUX PROG_B PROG_B PROG_B B1 CONFIG VCCAUX TCK TCK TCK A17 JTAG VCCAUX TDI TDI TDI A2 JTAG VCCAUX TDO TDO TDO C16 JTAG VCCAUX TMS TMS TMS D15 JTAG VCCAUX VCCAUX VCCAUX VCCAUX B7 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX B12 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX G2 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX G17 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX M2 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX M17 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX U7 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX U12 VCCAUX VCCINT VCCINT VCCINT VCCINT E5 VCCINT VCCINT VCCINT VCCINT VCCINT E14 VCCINT VCCINT VCCINT VCCINT VCCINT F6 VCCINT VCCINT VCCINT VCCINT VCCINT F13 VCCINT VCCINT VCCINT VCCINT VCCINT N6 VCCINT VCCINT VCCINT VCCINT VCCINT N13 VCCINT VCCINT VCCINT VCCINT VCCINT P5 VCCINT VCCINT VCCINT VCCINT VCCINT P14 VCCINT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 205

Spartan-3E FPGA Family: Pinout Descriptions User I/Os by Bank Table148 and Table149 indicate how the available user-I/O pins are distributed between the four I/O banks on the FG320 package. Table 148: User I/Os Per Bank for XC3S500E in the FG320 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 58 29 14 1 6 8 Right 1 58 22 10 21 5 0(2) Bottom 2 58 17 13 24 4 0(2) Left 3 58 34 11 0 5 8 TOTAL 232 102 48 46 20 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Table 149: User I/Os Per Bank for XC3S1200E and XC3S1600E in the FG320 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 61 34 12 1 6 8 Right 1 63 25 12 21 5 0(2) Bottom 2 63 23 11 24 5 0(2) Left 3 63 38 12 0 5 8 TOTAL 250 120 47 46 21 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 206

Spartan-3E FPGA Family: Pinout Descriptions Footprint Migration Differences Table150 summarizes any footprint and functionality and the XC3S1600E. The arrows indicate the direction for differences between the XC3S500E, the XC3S1200E, and easy migration. A double-ended arrow () indicates that the XC3S1600E FPGAs that may affect easy migration the two pins have identical functionality. A left-facing arrow between devices available in the FG320 package. There are () indicates that the pin on the device on the right 26 such balls. All other pins not listed in Table150 unconditionally migrates to the pin on the device on the left. unconditionally migrate between Spartan-3E devices It may be possible to migrate the opposite direction available in the FG320 package. depending on the I/O configuration. For example, an I/O pin (Type=I/O) can migrate to an input-only pin The XC3S500E is duplicated on both the left and right sides (Type=INPUT) if the I/O pin is configured as an input. of the table to show migrations to and from the XC3S1200E Table 150: FG320 Footprint Migration Differences Pin Bank XC3S500E Migration XC3S1200E Migration XC3S1600E Migration XC3S500E A7 0 INPUT  I/O  I/O  INPUT A12 0 N.C.  I/O  I/O  N.C. D4 3 N.C.  I/O  I/O  N.C. D6 0 N.C.  I/O  I/O  N.C. D13 0 INPUT  I/O  I/O  INPUT E3 3 N.C.  I/O  I/O  N.C. E4 3 N.C.  I/O  I/O  N.C. E6 0 N.C.  I/O  I/O  N.C. E15 1 N.C.  I/O  I/O  N.C. E16 1 N.C.  I/O  I/O  N.C. E17 1 I/O  INPUT  INPUT  I/O F4 3 I/O  INPUT  INPUT  I/O N12 2 N.C.  I/O  I/O  N.C. N14 1 N.C.  I/O  I/O  N.C. N15 1 N.C.  I/O  I/O  N.C. P3 3 N.C.  I/O  I/O  N.C. P4 3 N.C.  I/O  I/O  N.C. P12 2 N.C.  I/O  I/O  N.C. P15 1 I/O  INPUT  INPUT  I/O P16 1 N.C.  I/O  I/O  N.C. R4 3 VREF(I/O)  VREF(INPUT)  VREF(INPUT)  VREF(I/O) U6 2 INPUT  I/O  I/O  INPUT U13 2 INPUT  I/O  I/O  INPUT V5 2 N.C.  I/O  I/O  N.C. V6 2 N.C.  VREF  VREF  N.C. V7 2 N.C.  I/O  I/O  N.C. DIFFERENCES 26 0 26 Legend:  This pin is identical on the device on the left and the right. This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be  possible depending on how the pin is configured for the device on the right. This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be  possible depending on how the pin is configured for the device on the left. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 207

Spartan-3E FPGA Family: Pinout Descriptions FG320 Footprint X-Ref Target - Figure 86 Bank0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A GND TDI INPUT L2I4/OP_0 ILN22PPU_T0 L2I0/ON_0 INPUT I/O VCCO_0 L1I2/ON_0 I/O I/O L0I5/OP_0 L0I4/ON_0 ILN02PNU_T0 L0I1/ON_0 TCK GND GCLK7 I/O INPUT INPUT I/O I/O B PROG_B GND L25N_0 I/O INPUT I/O VCCAUX L13P_0 L13N_0 L12P_0 I/O VCCAUX L05N_0 I/O INPUT I/O GND INPUT L24N_0 L22N_0 L20P_0 VREF_0 L04P_0 L02P_0 L01P_0 HSWAP GCLK8 GCLK9 GCLK6 VREF_0 I/O I/O I/O I/O C I/O I/O I/O I/O I/O VCCO_0 I/O INPUT L14P_0 GND I/O INPUT VCCO_0 L03N_0 INPUT TDO L24N_1 L24P_1 L01P_3 L01N_3 L25P_0 L23P_0 L18P_0 L16P_0 L09P_0 L07P_0 GCLK10 VREF_0 LDC2 LDC1 D L0I2/OP_3 VLR0I2E/ONF__33 INPUT I/O VLR2I3E/ONF__00 L2I1/OP_0 VLR1I8E/ONF__00 ILN16PNU_T0 GL1CI4/LONK_101 LG1CI1/LOPK_40 L0I9/ON_0 ILN07PNU_T0 INPUT L0I3/OP_0 TMS LL2ID3/ONC_01 L2HI3/DOPC_1 VINRPEFU_T1 E L0I3/ON_3 L0I3/OP_3 L0I4/ON_3 L0I4/OP_3 VCCINT L2I1/ON_0 VLR1I9E/ONF__00 L1I7/OP_0 L1I5/OP_0 LG1CI1/LONK_50 L0I8/OP_0 L0I6/ON_0 I/O VCCINT L2I2/OP_1 L2I2/ON_1 INPUT INPUT F L0I5/OP_3 L0I5/ON_3 VCCO_3 INPUT INPUT VCCINT L1I9/OP_0 L1I7/ON_0 L1I5/ON_0 ILN10PPU_T0 L0I8/ON_0 L0I6/OP_0 VCCINT L2I1/ON_1 L2I1/OP_1 VCCO_1 L1I9/ON_1 L1I9/OP_1 I/O G INPUT VCCAUX I/O L06N_3 I/O I/O GND VCCO_0 I/O INPUT VCCO_0 GND I/O I/O I/O I/O VCCAUX INPUT L06P_3 L07N_3 L07P_3 L10N_0 L20N_1 L20P_1 L18P_1 L18N_1 VREF_3 I/O H I/O I/O I/O I/O I/O I/O VCCO_3 GND GND GND GND VCCO_1 INPUT I/O I/O I/O L16N_1 INPUT L10N_3 L10P_3 L09N_3 L09P_3 L08N_3 L08P_3 L17P_1 L17N_1 L16P_1 VREF_1 A0 J L1I2/OP_3 L1I2/ON_3 GND L1I1/ON_3 L1I1/OP_3 INPUT INPUT GND GND L1I5/OP_1 L1I5/ON_1 L1I4/ON_1 L1I4/OP_1 L1I3/ON_1 L1I3A/OP6_1 VCCO_1 1 3 LHCLK2 LIHRCDLYK23 LHCLK1 LHCLK0 VREF_3 A2 A1 RHAC3LK7 RHAC44LK6 RHAC5LK5 RIHRCDLYK14 nk nk K VCCO_3 INPUT L1I3/OP_3 L1I3/ON_3 L1I4/ON_3 L1I4/OP_3 INPUT GND GND L1I1/ON_1 L1I1/OP_1 L1I2A/ON7_1 L1I2/OP_1 GND INPUT INPUT Ba Ba LTHRCDLYK24 LHCLK5 LHCLK7 LHCLK6 RHAC9LK1 RHAC1L0K0 RTHRCDLYK13 RHAC8LK2 I/O I/O I/O I/O L I/O I/O I/O I/O L17N_3 I/O VCCO_3 GND GND GND GND VCCO_1 INPUT INPUT L09N_1 L09P_1 L10N_1 I/O L15P_3 L15N_3 L16P_3 L16N_3 L17P_3 L10P_1 VREF_3 A11 A12 VREF_1 I/O I/O I/O M INPUT VCCAUX I/O I/O I/O I/O GND VCCO_2 L12N_2 L16P_2 VCCO_2 GND L05N_1 I/O I/O I/O VCCAUX I/O L18N_3 L18P_3 L19P_3 L19N_3 D6 L05P_1 L07P_1 L07N_1 L08N_1 GCLK13 M0 VREF_1 I/O I/O I/O I/O I/O N INPUT INPUT VCCO_3 I/O I/O VCCINT I/O I/O L12P_2 L16N_2 I/O L21P_2 VCCINT L04N_1 L04P_1 VCCO_1 INPUT I/O L20P_3 L20N_3 L07P_2 L09N_2 GCDL7K12 DDI0N L18N_2    L08P_1 P L2I1/ON_3 L2I1/OP_3 L2I2/OP_3 L2I2/ON_3 VCCINT L0I5/ON_2 L0I7/ON_2 L0I9/OP_2 I/O LG1CI5D/LON1K_32 L1I8/OP_2 L2I1/ON_2 L2AI2/2OP3_2 VCCINT INPUT I/O L0I6/OP_1 L0I6/ON_1 INPUT I/O I/O I/O I/O I/O R INPUT I/O I/O VREF_3 I/O I/O INPUT I/O I/O L15P_2 I/O I/O L22N_2 L24N_2 I/O L03N_1 INPUT L02P_1 L23N_3 L23P_3  L04P_2 L05P_2 L08N_2 L10P_2 D5 GCDL2K2 L20N_2 A22 A20 L03P_1 VREF_1 A14 I/O I/O INPUT I/O I/O I/O I/O T I/O I/O L01N_2 L03N_2 I/O VCCO_2 INPUT I/O GND L14N_2 INPUT I/O VCCO_2 L24P_2 I/O L26P_2 L01N_1 L02N_1 L24N_3 L24P_3 MOSI L04N_2 L08P_2 L10N_2 M2 L17P_2 L20P_2 VREF_2 VS0 INIT_B CSI_B GCLK1 A21 A17 A15 A13 U INPUT GND L0I1/OP_2 LD0IO3/OPU_T2 VRIE/OF_2 INPUT VCCAUX ILN11PPU_T2 L1ID3/OP4_2 RILDN1W4PPUR__T2B ILN17PNU_T2 VCCAUX INPUT ILN23PNU_T2 L2VI5/SON1_2 L2I6/ON_2 GND L0I1/OP_1 CSO_B BUSY GCLK14 GCLK0 A18 CCLK A16 V GND INPUT ILN02PNU_T2 ILN02PPU_T2 L0I6/OP_2 VLR0I6E/ONF__22 I/O VILNR11PENFU__T22 GL1CI3D/LON3K_125 VCCO_2 IM/O1 L1I9/OP_2 VLR1I9E/ONF__22 ILN23PPU_T2 L2VAI5/S1OP92_2 INPUT DONE GND Bank2 DS312-4_06_022106 Figure 86: FG320 Package Footprint (top view) 102- I/O: Unrestricted, general-purpose DUAL: Configuration pin, then 20- VREF: User I/O or input voltage 46 120 user I/O possible user-I/O 21 reference for bank 47- INPUT: Unrestricted, CLK: User I/O, input, or global VCCO: Output voltage supply for 16 20 48 general-purpose input pin buffer input bank CONFIG: Dedicated configuration JTAG: Dedicated JTAG port pins VCCINT: Internal core supply 2 4 8 pins voltage (+1.2V) N.C.: Not connected. Only the GND: Ground VCCAUX: Auxiliary supply voltage 18 28 8 XC3S500E has these pins (). (+2.5V) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 208

Spartan-3E FPGA Family: Pinout Descriptions FG400: 400-ball Fine-pitch Ball Grid Array The 400-ball fine-pitch ball grid array, FG400, supports two Table 151: FG400 Package Pinout (Cont’d) different Spartan-3E FPGAs, including the XC3S1200E and XC3S1200E the XC3S1600E. Both devices share a common footprint for Bank XC3S1600E FG400 Type Ball this package as shown in Table151 and Figure87. Pin Name 0 IO_L12P_0 D12 I/O Table151 lists all the FG400 package pins. They are sorted by bank number and then by pin name. Pairs of pins that 0 IO_L13N_0 E12 I/O form a differential I/O pair appear together in the table. The 0 IO_L13P_0 F12 I/O table also shows the pin number for each pin and the pin 0 IO_L15N_0/GCLK5 G11 GCLK type, as defined earlier. 0 IO_L15P_0/GCLK4 F11 GCLK An electronic version of this package pinout table and 0 IO_L16N_0/GCLK7 E10 GCLK footprint diagram is available for download from the Xilinx 0 IO_L16P_0/GCLK6 E11 GCLK website at: 0 IO_L18N_0/GCLK11 A9 GCLK http://www.xilinx.com/support/documentation/data_sheets 0 IO_L18P_0/GCLK10 A10 GCLK /s3e_pin.zip 0 IO_L19N_0 F9 I/O Pinout Table 0 IO_L19P_0 E9 I/O 0 IO_L21N_0 C9 I/O Table 151: FG400 Package Pinout 0 IO_L21P_0 D9 I/O XC3S1200E FG400 0 IO_L22N_0/VREF_0 B8 VREF Bank XC3S1600E Type Pin Name Ball 0 IO_L22P_0 B9 I/O 0 IO A3 I/O 0 IO_L24N_0/VREF_0 F7 VREF 0 IO A8 I/O 0 IO_L24P_0 F8 I/O 0 IO A12 I/O 0 IO_L25N_0 A6 I/O 0 IO C7 I/O 0 IO_L25P_0 A7 I/O 0 IO C10 I/O 0 IO_L27N_0 B5 I/O 0 IO E8 I/O 0 IO_L27P_0 B6 I/O 0 IO E13 I/O 0 IO_L28N_0 D6 I/O 0 IO E16 I/O 0 IO_L28P_0 C6 I/O 0 IO F13 I/O 0 IO_L30N_0/VREF_0 C5 VREF 0 IO F14 I/O 0 IO_L30P_0 D5 I/O 0 IO G7 I/O 0 IO_L31N_0 A2 I/O 0 IO/VREF_0 C11 VREF 0 IO_L31P_0 B2 I/O 0 IO_L01N_0 B17 I/O 0 IO_L32N_0/HSWAP D4 DUAL 0 IO_L01P_0 C17 I/O 0 IO_L32P_0 C4 I/O 0 IO_L03N_0/VREF_0 A18 VREF 0 IP B18 INPUT 0 IO_L03P_0 A19 I/O 0 IP E5 INPUT 0 IO_L04N_0 A17 I/O 0 IP_L02N_0 C16 INPUT 0 IO_L04P_0 A16 I/O 0 IP_L02P_0 D16 INPUT 0 IO_L06N_0 A15 I/O 0 IP_L05N_0 D15 INPUT 0 IO_L06P_0 B15 I/O 0 IP_L05P_0 C15 INPUT 0 IO_L07N_0 C14 I/O 0 IP_L08N_0 E14 INPUT 0 IO_L07P_0 D14 I/O 0 IP_L08P_0 E15 INPUT 0 IO_L09N_0/VREF_0 A13 VREF 0 IP_L11N_0 G14 INPUT 0 IO_L09P_0 A14 I/O 0 IP_L11P_0 G13 INPUT 0 IO_L10N_0 B13 I/O 0 IP_L14N_0 B11 INPUT 0 IO_L10P_0 C13 I/O 0 IP_L14P_0 B12 INPUT 0 IO_L12N_0 C12 I/O 0 IP_L17N_0/GCLK9 G10 GCLK DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 209

Spartan-3E FPGA Family: Pinout Descriptions Table 151: FG400 Package Pinout (Cont’d) Table 151: FG400 Package Pinout (Cont’d) XC3S1200E XC3S1200E FG400 FG400 Bank XC3S1600E Type Bank XC3S1600E Type Ball Ball Pin Name Pin Name 0 IP_L17P_0/GCLK8 H10 GCLK 1 IO_L14P_1/A10/RHCLK0 M16 RHCLK/ DUAL 0 IP_L20N_0 G9 INPUT 1 IO_L15N_1/A7/RHCLK3/ L14 RHCLK/ 0 IP_L20P_0 G8 INPUT TRDY1 DUAL 0 IP_L23N_0 C8 INPUT 1 IO_L15P_1/A8/RHCLK2 L15 RHCLK/ 0 IP_L23P_0 D8 INPUT DUAL 0 IP_L26N_0 E6 INPUT 1 IO_L16N_1/A5/RHCLK5 K14 RHCLK/ DUAL 0 IP_L26P_0 E7 INPUT 1 IO_L16P_1/A6/RHCLK4/ K13 RHCLK/ 0 IP_L29N_0 A4 INPUT IRDY1 DUAL 0 IP_L29P_0 A5 INPUT 1 IO_L17N_1/A3/RHCLK7 J20 RHCLK/ 0 VCCO_0 B4 VCCO DUAL 0 VCCO_0 B10 VCCO 1 IO_L17P_1/A4/RHCLK6 K20 RHCLK/ 0 VCCO_0 B16 VCCO DUAL 0 VCCO_0 D7 VCCO 1 IO_L18N_1/A1 K16 DUAL 0 VCCO_0 D13 VCCO 1 IO_L18P_1/A2 J16 DUAL 0 VCCO_0 F10 VCCO 1 IO_L19N_1/A0 J13 DUAL 1 IO_L01N_1/A15 U18 DUAL 1 IO_L19P_1 J14 I/O 1 IO_L01P_1/A16 U17 DUAL 1 IO_L20N_1 J17 I/O 1 IO_L02N_1/A13 T18 DUAL 1 IO_L20P_1 J18 I/O 1 IO_L02P_1/A14 T17 DUAL 1 IO_L21N_1 H19 I/O 1 IO_L03N_1/VREF_1 V19 VREF 1 IO_L21P_1 J19 I/O 1 IO_L03P_1 U19 I/O 1 IO_L22N_1 H15 I/O 1 IO_L04N_1 W20 I/O 1 IO_L22P_1 H16 I/O 1 IO_L04P_1 V20 I/O 1 IO_L23N_1 H18 I/O 1 IO_L05N_1 R18 I/O 1 IO_L23P_1 H17 I/O 1 IO_L05P_1 R17 I/O 1 IO_L24N_1/VREF_1 H20 VREF 1 IO_L06N_1 T20 I/O 1 IO_L24P_1 G20 I/O 1 IO_L06P_1 U20 I/O 1 IO_L25N_1 G16 I/O 1 IO_L07N_1 P18 I/O 1 IO_L25P_1 F16 I/O 1 IO_L07P_1 P17 I/O 1 IO_L26N_1 F19 I/O 1 IO_L08N_1/VREF_1 P20 VREF 1 IO_L26P_1 F20 I/O 1 IO_L08P_1 R20 I/O 1 IO_L27N_1 F18 I/O 1 IO_L09N_1 P16 I/O 1 IO_L27P_1 F17 I/O 1 IO_L09P_1 N16 I/O 1 IO_L28N_1 D20 I/O 1 IO_L10N_1 N19 I/O 1 IO_L28P_1 E20 I/O 1 IO_L10P_1 N18 I/O 1 IO_L29N_1/LDC0 D18 DUAL 1 IO_L11N_1 N15 I/O 1 IO_L29P_1/HDC E18 DUAL 1 IO_L11P_1 M15 I/O 1 IO_L30N_1/LDC2 C19 DUAL 1 IO_L12N_1/A11 M18 DUAL 1 IO_L30P_1/LDC1 C20 DUAL 1 IO_L12P_1/A12 M17 DUAL 1 IP B20 INPUT 1 IO_L13N_1/VREF_1 L19 VREF 1 IP G15 INPUT 1 IO_L13P_1 M19 I/O 1 IP G18 INPUT 1 IO_L14N_1/A9/RHCLK1 L16 RHCLK/ 1 IP H14 INPUT DUAL 1 IP J15 INPUT DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 210

Spartan-3E FPGA Family: Pinout Descriptions Table 151: FG400 Package Pinout (Cont’d) Table 151: FG400 Package Pinout (Cont’d) XC3S1200E XC3S1200E FG400 FG400 Bank XC3S1600E Type Bank XC3S1600E Type Ball Ball Pin Name Pin Name 1 IP L18 INPUT 2 IO_L13N_2 Y8 I/O 1 IP M20 INPUT 2 IO_L13P_2 Y9 I/O 1 IP N14 INPUT 2 IO_L15N_2/D6/GCLK13 W10 DUAL/ GCLK 1 IP N20 INPUT 2 IO_L15P_2/D7/GCLK12 W9 DUAL/ 1 IP P15 INPUT GCLK 1 IP R16 INPUT 2 IO_L16N_2/D3/GCLK15 P10 DUAL/ 1 IP R19 INPUT GCLK 1 IP/VREF_1 E19 VREF 2 IO_L16P_2/D4/GCLK14 R10 DUAL/ GCLK 1 IP/VREF_1 K18 VREF 2 IO_L18N_2/D1/GCLK3 V11 DUAL/ 1 VCCO_1 D19 VCCO GCLK 1 VCCO_1 G17 VCCO 2 IO_L18P_2/D2/GCLK2 V10 DUAL/ 1 VCCO_1 K15 VCCO GCLK 1 VCCO_1 K19 VCCO 2 IO_L19N_2/DIN/D0 Y12 DUAL 1 VCCO_1 N17 VCCO 2 IO_L19P_2/M0 Y11 DUAL 1 VCCO_1 T19 VCCO 2 IO_L21N_2 U12 I/O 2 IO P8 I/O 2 IO_L21P_2 V12 I/O 2 IO P13 I/O 2 IO_L22N_2/VREF_2 W12 VREF 2 IO R9 I/O 2 IO_L22P_2 W13 I/O 2 IO R13 I/O 2 IO_L24N_2 U13 I/O 2 IO W15 I/O 2 IO_L24P_2 V13 I/O 2 IO Y5 I/O 2 IO_L25N_2 P14 I/O 2 IO Y7 I/O 2 IO_L25P_2 R14 I/O 2 IO Y13 I/O 2 IO_L27N_2/A22 Y14 DUAL 2 IO/D5 N11 DUAL 2 IO_L27P_2/A23 Y15 DUAL 2 IO/M1 T11 DUAL 2 IO_L28N_2 T15 I/O 2 IO/VREF_2 Y3 VREF 2 IO_L28P_2 U15 I/O 2 IO/VREF_2 Y17 VREF 2 IO_L30N_2/A20 V16 DUAL 2 IO_L01N_2/INIT_B V4 DUAL 2 IO_L30P_2/A21 U16 DUAL 2 IO_L01P_2/CSO_B U4 DUAL 2 IO_L31N_2/VS1/A18 Y18 DUAL 2 IO_L03N_2/MOSI/CSI_B V5 DUAL 2 IO_L31P_2/VS2/A19 W18 DUAL 2 IO_L03P_2/DOUT/BUSY U5 DUAL 2 IO_L32N_2/CCLK W19 DUAL 2 IO_L04N_2 Y4 I/O 2 IO_L32P_2/VS0/A17 Y19 DUAL 2 IO_L04P_2 W4 I/O 2 IP T16 INPUT 2 IO_L06N_2 T6 I/O 2 IP W3 INPUT 2 IO_L06P_2 T5 I/O 2 IP_L02N_2 Y2 INPUT 2 IO_L07N_2 U7 I/O 2 IP_L02P_2 W2 INPUT 2 IO_L07P_2 V7 I/O 2 IP_L05N_2 V6 INPUT 2 IO_L09N_2/VREF_2 R7 VREF 2 IP_L05P_2 U6 INPUT 2 IO_L09P_2 T7 I/O 2 IP_L08N_2 Y6 INPUT 2 IO_L10N_2 V8 I/O 2 IP_L08P_2 W6 INPUT 2 IO_L10P_2 W8 I/O 2 IP_L11N_2 R8 INPUT 2 IO_L12N_2 U9 I/O 2 IP_L11P_2 T8 INPUT 2 IO_L12P_2 V9 I/O 2 IP_L14N_2/VREF_2 T10 VREF DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 211

Spartan-3E FPGA Family: Pinout Descriptions Table 151: FG400 Package Pinout (Cont’d) Table 151: FG400 Package Pinout (Cont’d) XC3S1200E XC3S1200E FG400 FG400 Bank XC3S1600E Type Bank XC3S1600E Type Ball Ball Pin Name Pin Name 2 IP_L14P_2 T9 INPUT 3 IO_L13P_3 K6 I/O 2 IP_L17N_2/M2/GCLK1 P12 DUAL/ 3 IO_L14N_3/LHCLK1 K2 LHCLK GCLK 3 IO_L14P_3/LHCLK0 K3 LHCLK 2 IP_L17P_2/RDWR_B/ P11 DUAL/ 3 IO_L15N_3/LHCLK3/IRDY2 L7 LHCLK GCLK0 GCLK 3 IO_L15P_3/LHCLK2 K7 LHCLK 2 IP_L20N_2 T12 INPUT 3 IO_L16N_3/LHCLK5 L1 LHCLK 2 IP_L20P_2 R12 INPUT 3 IO_L16P_3/LHCLK4/TRDY2 M1 LHCLK 2 IP_L23N_2/VREF_2 T13 VREF 3 IO_L17N_3/LHCLK7 L3 LHCLK 2 IP_L23P_2 T14 INPUT 3 IO_L17P_3/LHCLK6 M3 LHCLK 2 IP_L26N_2 V14 INPUT 3 IO_L18N_3 M7 I/O 2 IP_L26P_2 V15 INPUT 3 IO_L18P_3 M8 I/O 2 IP_L29N_2 W16 INPUT 3 IO_L19N_3 M4 I/O 2 IP_L29P_2 Y16 INPUT 3 IO_L19P_3 M5 I/O 2 VCCO_2 R11 VCCO 3 IO_L20N_3/VREF_3 N6 VREF 2 VCCO_2 U8 VCCO 3 IO_L20P_3 M6 I/O 2 VCCO_2 U14 VCCO 3 IO_L21N_3 N2 I/O 2 VCCO_2 W5 VCCO 3 IO_L21P_3 N1 I/O 2 VCCO_2 W11 VCCO 3 IO_L22N_3 P7 I/O 2 VCCO_2 W17 VCCO 3 IO_L22P_3 N7 I/O 3 IO_L01N_3 D2 I/O 3 IO_L23N_3 N4 I/O 3 IO_L01P_3 D3 I/O 3 IO_L23P_3 N3 I/O 3 IO_L02N_3/VREF_3 E3 VREF 3 IO_L24N_3 R1 I/O 3 IO_L02P_3 E4 I/O 3 IO_L24P_3 P1 I/O 3 IO_L03N_3 C1 I/O 3 IO_L25N_3 R5 I/O 3 IO_L03P_3 B1 I/O 3 IO_L25P_3 P5 I/O 3 IO_L04N_3 E1 I/O 3 IO_L26N_3 T2 I/O 3 IO_L04P_3 D1 I/O 3 IO_L26P_3 R2 I/O 3 IO_L05N_3 F3 I/O 3 IO_L27N_3 R4 I/O 3 IO_L05P_3 F4 I/O 3 IO_L27P_3 R3 I/O 3 IO_L06N_3 F1 I/O 3 IO_L28N_3/VREF_3 T1 VREF 3 IO_L06P_3 F2 I/O 3 IO_L28P_3 U1 I/O 3 IO_L07N_3 G4 I/O 3 IO_L29N_3 T3 I/O 3 IO_L07P_3 G3 I/O 3 IO_L29P_3 U3 I/O 3 IO_L08N_3 G5 I/O 3 IO_L30N_3 V1 I/O 3 IO_L08P_3 H5 I/O 3 IO_L30P_3 V2 I/O 3 IO_L09N_3/VREF_3 H3 VREF 3 IP F5 INPUT 3 IO_L09P_3 H2 I/O 3 IP G1 INPUT 3 IO_L10N_3 H7 I/O 3 IP G6 INPUT 3 IO_L10P_3 H6 I/O 3 IP H1 INPUT 3 IO_L11N_3 J4 I/O 3 IP J5 INPUT 3 IO_L11P_3 J3 I/O 3 IP L5 INPUT 3 IO_L12N_3 J1 I/O 3 IP L8 INPUT 3 IO_L12P_3 J2 I/O 3 IP M2 INPUT 3 IO_L13N_3 J6 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 212

Spartan-3E FPGA Family: Pinout Descriptions Table 151: FG400 Package Pinout (Cont’d) Table 151: FG400 Package Pinout (Cont’d) XC3S1200E XC3S1200E FG400 FG400 Bank XC3S1600E Type Bank XC3S1600E Type Ball Ball Pin Name Pin Name 3 IP N5 INPUT GND GND P19 GND 3 IP P3 INPUT GND GND R6 GND 3 IP T4 INPUT GND GND R15 GND 3 IP W1 INPUT GND GND U11 GND 3 IP/VREF_3 K5 VREF GND GND V3 GND 3 IP/VREF_3 P6 VREF GND GND V18 GND 3 VCCO_3 E2 VCCO GND GND W7 GND 3 VCCO_3 H4 VCCO GND GND W14 GND 3 VCCO_3 L2 VCCO GND GND Y1 GND 3 VCCO_3 L6 VCCO GND GND Y10 GND 3 VCCO_3 P4 VCCO GND GND Y20 GND 3 VCCO_3 U2 VCCO VCCAUX DONE V17 CONFIG GND GND A1 GND VCCAUX PROG_B C2 CONFIG GND GND A11 GND VCCAUX TCK D17 JTAG GND GND A20 GND VCCAUX TDI B3 JTAG GND GND B7 GND VCCAUX TDO B19 JTAG GND GND B14 GND VCCAUX TMS E17 JTAG GND GND C3 GND VCCAUX VCCAUX D11 VCCAUX GND GND C18 GND VCCAUX VCCAUX H12 VCCAUX GND GND D10 GND VCCAUX VCCAUX J7 VCCAUX GND GND F6 GND VCCAUX VCCAUX K4 VCCAUX GND GND F15 GND VCCAUX VCCAUX L17 VCCAUX GND GND G2 GND VCCAUX VCCAUX M14 VCCAUX GND GND G12 GND VCCAUX VCCAUX N9 VCCAUX GND GND G19 GND VCCAUX VCCAUX U10 VCCAUX GND GND H8 GND VCCINT VCCINT H9 VCCINT GND GND J9 GND VCCINT VCCINT H11 VCCINT GND GND J11 GND VCCINT VCCINT H13 VCCINT GND GND K1 GND VCCINT VCCINT J8 VCCINT GND GND K8 GND VCCINT VCCINT J10 VCCINT GND GND K10 GND VCCINT VCCINT J12 VCCINT GND GND K12 GND VCCINT VCCINT K9 VCCINT GND GND K17 GND VCCINT VCCINT K11 VCCINT GND GND L4 GND VCCINT VCCINT L10 VCCINT GND GND L9 GND VCCINT VCCINT L12 VCCINT GND GND L11 GND VCCINT VCCINT M9 VCCINT GND GND L13 GND VCCINT VCCINT M11 VCCINT GND GND L20 GND VCCINT VCCINT M13 VCCINT GND GND M10 GND VCCINT VCCINT N8 VCCINT GND GND M12 GND VCCINT VCCINT N10 VCCINT GND GND N13 GND VCCINT VCCINT N12 VCCINT GND GND P2 GND GND GND P9 GND DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 213

Spartan-3E FPGA Family: Pinout Descriptions User I/Os by Bank Table152 indicates how the 304 available user-I/O pins are distributed between the four I/O banks on the FG400 package. Table 152: User I/Os Per Bank for the XC3S1200E and XC3S1600E in the FG400 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 78 43 20 1 6 8 Right 1 74 35 12 21 6 0(2) Bottom 2 78 30 18 24 6 0(2) Left 3 74 48 12 0 6 8 TOTAL 304 156 62 46 24 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Footprint Migration Differences The XC3S1200E and XC3S1600E FPGAs have identical footprints in the FG400 package. Designs can migrate between the XC3S1200E and XC3S1600E FPGAs without further consideration. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 214

Spartan-3E FPGA Family: Pinout Descriptions FG400 Footprint X-Ref Target - Figure 87 Bank 0 Left Half of Package 1 2 3 4 5 6 7 8 9 10 (top view) I/O I/O I/O INPUT INPUT I/O I/O A GND I/O I/O L18N_0 L18P_0 L31N_0 L29N_0 L29P_0 L25N_0 L25P_0 GCLK11 GCLK10 I/O I/O I/O I/O I/O I/O 156 Ig/Oen: eUranlr-epsutrrpicotesed ,u ser I/O B L03P_3 L31P_0 TDI VCCO_0 L27N_0 L27P_0 GND VLR22ENF__00 L22P_0 VCCO_0 I/O I/O I/O I/O INPUT I/O 62 IgNePnUerTa:l -Upunrrpeosstreic itnepdu, t pin C L03N_3 PROG_B GND L32P_0 VLR30ENF__00 L28P_0 I/O L23N_0 L21N_0 I/O I/O I/O I/O I/O I/O I/O INPUT I/O DUAL: Configuration pin, D L32N_0 VCCO_0 GND 46 L04P_3 L01N_3 L01P_3 L30P_0 L28N_0 L23P_0 L21P_0 then possible user I/O HSWAP I/O I/O I/O I/O INPUT INPUT I/O VREF: User I/O or input E VCCO_3 L02N_3 INPUT I/O L16N_0 24 L04N_3 L02P_3 L26N_0 L26P_0 L19P_0 voltage reference for bank VREF_3 GCLK7 I/O I/O I/O I/O I/O I/O I/O 16 CLK: User I/O, input, or F L06N_3 L06P_3 L05N_3 L05P_3 INPUT GND L24N_0 L24P_0 L19N_0 VCCO_0 clock buffer input VREF_0 INPUT I/O I/O I/O INPUT INPUT 2 CONFIG: Dedicated G INPUT GND L07P_3 L07N_3 L08N_3 INPUT I/O L20P_0 L20N_0 L17N_0 configuration pins GCLK9 I/O INPUT I/O I/O I/O I/O 4 JTAG: Dedicated JTAG H INPUT L09P_3 L09N_3 VCCO_3 L08P_3 L10P_3 L10N_3 GND VCCINT L17P_0 port pins VREF_3 GCLK8 42 GND: Ground J L1I2/ON_3 L1I2/OP_3 L1I1/OP_3 L1I1/ON_3 INPUT L1I3/ON_3 VCCAUX VCCINT GND VCCINT I/O I/O I/O 24 VCCO: Output voltage 3 K GND L14N_3 L14P_3 VCCAUX INPUT I/O L15P_3 GND VCCINT GND supply for bank k LHCLK1 LHCLK0 VREF_3 L13P_3 LHCLK2 n a I/O I/O I/O 16 VCCINT: Internal core B L L16N_3 VCCO_3 L17N_3 GND INPUT VCCO_3 L15N_3 INPUT GND VCCINT supply voltage (+1.2V) LHCLK5 LHCLK7 LIHRCDLYK23 I/O I/O 8 VCCAUX: Auxiliary supply M L16P_3 INPUT L17P_3 I/O I/O I/O I/O I/O VCCINT GND voltage (+2.5V) LHCLK4 L19N_3 L19P_3 L20P_3 L18N_3 L18P_3 TRDY2 LHCLK6 I/O N.C.: Not connected I/O I/O I/O I/O I/O 0 N INPUT L20N_3 VCCINT VCCAUX VCCINT L21P_3 L21N_3 L23P_3 L23N_3 L22P_3 VREF_3 I/O I/O I/O INPUT I/O P GND INPUT VCCO_3 I/O GND L16N_2 L24P_3 L25P_3 VREF_3 L22N_3 D3 GCLK15 I/O I/O I/O I/O I/O I/O I/O INPUT R GND L09N_2 I/O L16P_2 L24N_3 L26P_3 L27P_3 L27N_3 L25N_3 L11N_2 D4 VREF_2 GCLK14 I/O INPUT I/O I/O I/O I/O I/O INPUT INPUT T L28N_3 INPUT L14N_2 L26N_3 L29N_3 L06P_2 L06N_2 L09P_2 L11P_2 L14P_2 VREF_3 VREF_2 I/O I/O I/O I/O INPUT I/O I/O U VCCO_3 L01P_2 L03P_2 VCCO_2 VCCAUX L28P_3 L29P_3 DOUT L05P_2 L07N_2 L12N_2 CSO_B BUSY I/O I/O I/O I/O I/O INPUT I/O I/O I/O V GND L01N_2 L03N_2 L18P_2 L30N_3 L30P_3 MOSI L05N_2 L07P_2 L10N_2 L12P_2 D2 INIT_B CSI_B GCLK2 I/O I/O INPUT I/O INPUT I/O W INPUT INPUT VCCO_2 GND L15P_2 L15N_2 L02P_2 L04P_2 L08P_2 L10P_2 D7 D6 GCLK12 GCLK13 INPUT I/O I/O INPUT I/O I/O Y GND I/O I/O GND L02N_2 VREF_2 L04N_2 L08N_2 L13N_2 L13P_2 Bank 2 DS312-4_08_101905 Figure 87: FG400 Package Footprint (top view) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 215

Spartan-3E FPGA Family: Pinout Descriptions FG400 Footprint Bank 0 11 12 13 14 15 16 17 18 19 20 Right Half of Package I/O I/O (top view) I/O I/O I/O I/O I/O GND I/O L09N_0 L03N_0 GND A L09P_0 L06N_0 L04P_0 L04N_0 L03P_0 VREF_0 VREF_0 INPUT INPUT I/O I/O I/O GND VCCO_0 INPUT TDO INPUT B L14N_0 L14P_0 L10N_0 L06P_0 L01N_0 I/O I/O I/O I/O I/O I/O INPUT INPUT I/O GND L30N_1 L30P_1 C VREF_0 L12N_0 L10P_0 L07N_0 L05P_0 L02N_0 L01P_0 LDC2 LDC1 I/O I/O I/O INPUT INPUT I/O VCCAUX VCCO_0 TCK L29N_1 VCCO_1 D L12P_0 L07P_0 L05N_0 L02P_0 L28N_1 LDC0 I/O I/O I/O INPUT INPUT INPUT I/O L16P_0 I/O I/O TMS L29P_1 E L13N_0 L08N_0 L08P_0 VREF_1 L28P_1 GCLK6 HDC I/O I/O I/O I/O I/O I/O I/O L15P_0 I/O I/O GND F L13P_0 L25P_1 L27P_1 L27N_1 L26N_1 L26P_1 GCLK4 I/O INPUT INPUT I/O I/O L15N_0 GND INPUT VCCO_1 INPUT GND G L11P_0 L11N_0 L25N_1 L24P_1 GCLK5 I/O I/O I/O I/O I/O I/O VCCINT VCCAUX VCCINT INPUT L24N_1 H L22N_1 L22P_1 L23P_1 L23N_1 L21N_1 VREF_1 I/O I/O I/O I/O I/O I/O I/O GND VCCINT L19N_1 INPUT L18P_1 L17N_1 J L19P_1 L20N_1 L20P_1 L21P_1 A3 A0 A2 RHCLK7 I/O I/O I/O I/O L16P_1 INPUT VCCINT GND A6 L16N_1 VCCO_1 L18N_1 GND VCCO_1 L17P_1 K 1 RIHRCDLYK14 RHAC5LK5 A1 VREF_1 RHAC4LK6 k n I/O I/O I/O I/O a GND VCCINT GND L15AN7_1 L15P_1 L14N_1 VCCAUX INPUT L13N_1 GND L B RTHRCDLYK13 RHAC8LK2 RHAC9LK1 VREF_1 I/O I/O I/O I/O I/O VCCINT GND VCCINT VCCAUX L14P_1 L12P_1 L12N_1 INPUT M L11P_1 A10 L13P_1 RHCLK0 A12 A11 I/O I/O I/O I/O I/O VCCINT GND INPUT VCCO_1 INPUT N D5 L11N_1 L09P_1 L10P_1 L10N_1 INPUT INPUT I/O I/O I/O I/O I/O L17P_2 L17N_2 I/O INPUT GND L08N_1 P RDWR_B M2 L25N_2 L09N_1 L07P_1 L07N_1 GCLK0 GCLK1 VREF_1 INPUT I/O I/O I/O I/O VCCO_2 I/O GND INPUT INPUT R L20P_2 L25P_2 L05P_1 L05N_1 L08P_1 INPUT I/O I/O I/O INPUT INPUT I/O I/O L23N_2 INPUT L02P_1 L02N_1 VCCO_1 T M1 L20N_2 L23P_2 L28N_2 L06N_1 VREF_2 A14 A13 I/O I/O I/O I/O I/O I/O I/O I/O GND VCCO_2 L30P_2 L01P_1 L01N_1 U L21N_2 L24N_2 L28P_2 L03P_1 L06P_1 A21 A16 A15 I/O I/O I/O I/O I/O INPUT INPUT I/O L18N_2 L30N_2 DONE GND L03N_1 V D1 L21P_2 L24P_2 L26N_2 L26P_2 L04P_1 GCLK3 A20 VREF_1 I/O I/O I/O I/O INPUT I/O VCCO_2 L22N_2 GND I/O VCCO_2 L31P_2 L32N_2 W L22P_2 L29N_2 VS2 L04N_1 VREF_2 A19 CCLK I/O I/O I/O I/O I/O I/O INPUT I/O L19P_2 L19N_2 I/O L27N_2 L27P_2 L31N_2 L32P_2 GND Y DIN L29P_2 VREF_2 VS1 VS0 M0 D0 A22 A23 A18 A17 Bank 2 DS312-4_09_101905 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 216

Spartan-3E FPGA Family: Pinout Descriptions FG484: 484-ball Fine-pitch Ball Grid Array The 484-ball fine-pitch ball grid array, FG484, supports the Table 153: FG484 Package Pinout (Cont’d) XC3S1600E FPGA. XC3S1600E FG484 Bank Type Pin Name Ball Table153 lists all the FG484 package pins. They are sorted by bank number and then by pin name. Pairs of pins that 0 IO_L12P_0 A15 I/O form a differential I/O pair appear together in the table. The 0 IO_L13N_0 H14 I/O table also shows the pin number for each pin and the pin 0 IO_L13P_0 G14 I/O type, as defined earlier. 0 IO_L15N_0 G13 I/O An electronic version of this package pinout table and 0 IO_L15P_0 F13 I/O footprint diagram is available for download from the Xilinx 0 IO_L16N_0 J13 I/O website at: 0 IO_L16P_0 H13 I/O http://www.xilinx.com/support/documentation/data_sheets 0 IO_L18N_0/GCLK5 E12 GCLK /s3e_pin.zip 0 IO_L18P_0/GCLK4 F12 GCLK Pinout Table 0 IO_L19N_0/GCLK7 C12 GCLK 0 IO_L19P_0/GCLK6 B12 GCLK Table 153: FG484 Package Pinout 0 IO_L21N_0/GCLK11 B11 GCLK Bank XC3S1600E FG484 Type 0 IO_L21P_0/GCLK10 C11 GCLK Pin Name Ball 0 IO_L22N_0 D11 I/O 0 IO B6 I/O 0 IO_L22P_0 E11 I/O 0 IO B13 I/O 0 IO_L24N_0 A9 I/O 0 IO C5 I/O 0 IO_L24P_0 A10 I/O 0 IO C14 I/O 0 IO_L25N_0/VREF_0 D10 VREF 0 IO E16 I/O 0 IO_L25P_0 C10 I/O 0 IO F9 I/O 0 IO_L27N_0 H8 I/O 0 IO F16 I/O 0 IO_L27P_0 H9 I/O 0 IO G8 I/O 0 IO_L28N_0 C9 I/O 0 IO H10 I/O 0 IO_L28P_0 B9 I/O 0 IO H15 I/O 0 IO_L29N_0 E9 I/O 0 IO J11 I/O 0 IO_L29P_0 D9 I/O 0 IO/VREF_0 G12 VREF 0 IO_L30N_0 B8 I/O 0 IO_L01N_0 C18 I/O 0 IO_L30P_0 A8 I/O 0 IO_L01P_0 C19 I/O 0 IO_L32N_0/VREF_0 F7 VREF 0 IO_L03N_0/VREF_0 A20 VREF 0 IO_L32P_0 F8 I/O 0 IO_L03P_0 A21 I/O 0 IO_L33N_0 A6 I/O 0 IO_L04N_0 A19 I/O 0 IO_L33P_0 A7 I/O 0 IO_L04P_0 A18 I/O 0 IO_L35N_0 A4 I/O 0 IO_L06N_0 C16 I/O 0 IO_L35P_0 A5 I/O 0 IO_L06P_0 D16 I/O 0 IO_L36N_0 E7 I/O 0 IO_L07N_0 A16 I/O 0 IO_L36P_0 D7 I/O 0 IO_L07P_0 A17 I/O 0 IO_L38N_0/VREF_0 D6 VREF 0 IO_L09N_0/VREF_0 B15 VREF 0 IO_L38P_0 D5 I/O 0 IO_L09P_0 C15 I/O 0 IO_L39N_0 B4 I/O 0 IO_L10N_0 G15 I/O 0 IO_L39P_0 B3 I/O 0 IO_L10P_0 F15 I/O 0 IO_L40N_0/HSWAP D4 DUAL 0 IO_L11N_0 D14 I/O 0 IO_L40P_0 C4 I/O 0 IO_L11P_0 E14 I/O 0 IP B19 INPUT 0 IO_L12N_0/VREF_0 A14 VREF DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 217

Spartan-3E FPGA Family: Pinout Descriptions Table 153: FG484 Package Pinout (Cont’d) Table 153: FG484 Package Pinout (Cont’d) XC3S1600E FG484 XC3S1600E FG484 Bank Type Bank Type Pin Name Ball Pin Name Ball 0 IP E6 INPUT 1 IO_L08N_1 T22 I/O 0 IP_L02N_0 D17 INPUT 1 IO_L08P_1 U22 I/O 0 IP_L02P_0 D18 INPUT 1 IO_L09N_1 R19 I/O 0 IP_L05N_0 C17 INPUT 1 IO_L09P_1 R18 I/O 0 IP_L05P_0 B17 INPUT 1 IO_L10N_1 R16 I/O 0 IP_L08N_0 E15 INPUT 1 IO_L10P_1 T16 I/O 0 IP_L08P_0 D15 INPUT 1 IO_L11N_1 R21 I/O 0 IP_L14N_0 D13 INPUT 1 IO_L11P_1 R20 I/O 0 IP_L14P_0 C13 INPUT 1 IO_L12N_1/VREF_1 P18 VREF 0 IP_L17N_0 A12 INPUT 1 IO_L12P_1 P17 I/O 0 IP_L17P_0 A13 INPUT 1 IO_L13N_1 P22 I/O 0 IP_L20N_0/GCLK9 H11 GCLK 1 IO_L13P_1 R22 I/O 0 IP_L20P_0/GCLK8 H12 GCLK 1 IO_L14N_1 P15 I/O 0 IP_L23N_0 F10 INPUT 1 IO_L14P_1 P16 I/O 0 IP_L23P_0 F11 INPUT 1 IO_L15N_1 N18 I/O 0 IP_L26N_0 G9 INPUT 1 IO_L15P_1 N19 I/O 0 IP_L26P_0 G10 INPUT 1 IO_L16N_1/A11 N16 DUAL 0 IP_L31N_0 C8 INPUT 1 IO_L16P_1/A12 N17 DUAL 0 IP_L31P_0 D8 INPUT 1 IO_L17N_1/VREF_1 M20 VREF 0 IP_L34N_0 C7 INPUT 1 IO_L17P_1 N20 I/O 0 IP_L34P_0 C6 INPUT 1 IO_L18N_1/A9/RHCLK1 M22 RHCLK/ DUAL 0 IP_L37N_0 A3 INPUT 1 IO_L18P_1/A10/RHCLK0 N22 RHCLK/ 0 IP_L37P_0 A2 INPUT DUAL 0 VCCO_0 B5 VCCO 1 IO_L19N_1/A7/RHCLK3/ M16 RHCLK/ 0 VCCO_0 B10 VCCO TRDY1 DUAL 0 VCCO_0 B14 VCCO 1 IO_L19P_1/A8/RHCLK2 M15 RHCLK/ DUAL 0 VCCO_0 B18 VCCO 1 IO_L20N_1/A5/RHCLK5 L21 RHCLK/ 0 VCCO_0 E8 VCCO DUAL 0 VCCO_0 F14 VCCO 1 IO_L20P_1/A6/RHCLK4/ L20 RHCLK/ 0 VCCO_0 G11 VCCO IRDY1 DUAL 1 IO_L01N_1/A15 Y22 DUAL 1 IO_L21N_1/A3/RHCLK7 L19 RHCLK/ 1 IO_L01P_1/A16 AA22 DUAL DUAL 1 IO_L02N_1/A13 W21 DUAL 1 IO_L21P_1/A4/RHCLK6 L18 RHCLK/ DUAL 1 IO_L02P_1/A14 Y21 DUAL 1 IO_L22N_1/A1 K22 DUAL 1 IO_L03N_1/VREF_1 W20 VREF 1 IO_L22P_1/A2 L22 DUAL 1 IO_L03P_1 V20 I/O 1 IO_L23N_1/A0 K17 DUAL 1 IO_L04N_1 U19 I/O 1 IO_L23P_1 K16 I/O 1 IO_L04P_1 V19 I/O 1 IO_L24N_1 K19 I/O 1 IO_L05N_1 V22 I/O 1 IO_L24P_1 K18 I/O 1 IO_L05P_1 W22 I/O 1 IO_L25N_1 K15 I/O 1 IO_L06N_1 T19 I/O 1 IO_L25P_1 J15 I/O 1 IO_L06P_1 T18 I/O 1 IO_L26N_1 J20 I/O 1 IO_L07N_1/VREF_1 U20 VREF 1 IO_L26P_1 J21 I/O 1 IO_L07P_1 U21 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 218

Spartan-3E FPGA Family: Pinout Descriptions Table 153: FG484 Package Pinout (Cont’d) Table 153: FG484 Package Pinout (Cont’d) XC3S1600E FG484 XC3S1600E FG484 Bank Type Bank Type Pin Name Ball Pin Name Ball 1 IO_L27N_1 J17 I/O 1 VCCO_1 K21 VCCO 1 IO_L27P_1 J18 I/O 1 VCCO_1 L16 VCCO 1 IO_L28N_1/VREF_1 H21 VREF 1 VCCO_1 P21 VCCO 1 IO_L28P_1 H22 I/O 1 VCCO_1 R17 VCCO 1 IO_L29N_1 H20 I/O 1 VCCO_1 V21 VCCO 1 IO_L29P_1 H19 I/O 2 IO Y8 I/O 1 IO_L30N_1 H17 I/O 2 IO Y9 I/O 1 IO_L30P_1 G17 I/O 2 IO AA10 I/O 1 IO_L31N_1 F22 I/O 2 IO AB5 I/O 1 IO_L31P_1 G22 I/O 2 IO AB13 I/O 1 IO_L32N_1 F20 I/O 2 IO AB14 I/O 1 IO_L32P_1 G20 I/O 2 IO AB16 I/O 1 IO_L33N_1 G18 I/O 2 IO AB18 I/O 1 IO_L33P_1 G19 I/O 2 IO/D5 AB11 DUAL 1 IO_L34N_1 D22 I/O 2 IO/M1 AA12 DUAL 1 IO_L34P_1 E22 I/O 2 IO/VREF_2 AB4 VREF 1 IO_L35N_1 F19 I/O 2 IO/VREF_2 AB21 VREF 1 IO_L35P_1 F18 I/O 2 IO_L01N_2/INIT_B AB3 DUAL 1 IO_L36N_1 E20 I/O 2 IO_L01P_2/CSO_B AA3 DUAL 1 IO_L36P_1 E19 I/O 2 IO_L03N_2/MOSI/CSI_B Y5 DUAL 1 IO_L37N_1/LDC0 C21 DUAL 2 IO_L03P_2/DOUT/BUSY W5 DUAL 1 IO_L37P_1/HDC C22 DUAL 2 IO_L04N_2 W6 I/O 1 IO_L38N_1/LDC2 B21 DUAL 2 IO_L04P_2 V6 I/O 1 IO_L38P_1/LDC1 B22 DUAL 2 IO_L06N_2 W7 I/O 1 IP D20 INPUT 2 IO_L06P_2 Y7 I/O 1 IP F21 INPUT 2 IO_L07N_2 U7 I/O 1 IP G16 INPUT 2 IO_L07P_2 V7 I/O 1 IP H16 INPUT 2 IO_L09N_2/VREF_2 V8 VREF 1 IP J16 INPUT 2 IO_L09P_2 W8 I/O 1 IP J22 INPUT 2 IO_L10N_2 T8 I/O 1 IP K20 INPUT 2 IO_L10P_2 U8 I/O 1 IP L15 INPUT 2 IO_L11N_2 AB8 I/O 1 IP M18 INPUT 2 IO_L11P_2 AA8 I/O 1 IP N15 INPUT 2 IO_L12N_2 W9 I/O 1 IP N21 INPUT 2 IO_L12P_2 V9 I/O 1 IP P20 INPUT 2 IO_L13N_2/VREF_2 R9 VREF 1 IP R15 INPUT 2 IO_L13P_2 T9 I/O 1 IP T17 INPUT 2 IO_L14N_2 AB9 I/O 1 IP T20 INPUT 2 IO_L14P_2 AB10 I/O 1 IP U18 INPUT 2 IO_L16N_2 U10 I/O 1 IP/VREF_1 D21 VREF 2 IO_L16P_2 T10 I/O 1 IP/VREF_1 L17 VREF 2 IO_L17N_2 R10 I/O 1 VCCO_1 E21 VCCO 2 IO_L17P_2 P10 I/O 1 VCCO_1 H18 VCCO DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 219

Spartan-3E FPGA Family: Pinout Descriptions Table 153: FG484 Package Pinout (Cont’d) Table 153: FG484 Package Pinout (Cont’d) XC3S1600E FG484 XC3S1600E FG484 Bank Type Bank Type Pin Name Ball Pin Name Ball 2 IO_L19N_2/D6/GCLK13 U11 DUAL/ 2 IP_L08N_2 AB7 INPUT GCLK 2 IP_L08P_2 AB6 INPUT 2 IO_L19P_2/D7/GCLK12 V11 DUAL/ 2 IP_L15N_2 Y10 INPUT GCLK 2 IP_L15P_2 W10 INPUT 2 IO_L20N_2/D3/GCLK15 T11 DUAL/ GCLK 2 IP_L18N_2/VREF_2 AA11 VREF 2 IO_L20P_2/D4/GCLK14 R11 DUAL/ 2 IP_L18P_2 Y11 INPUT GCLK 2 IP_L21N_2/M2/GCLK1 P12 DUAL/ 2 IO_L22N_2/D1/GCLK3 W12 DUAL/ GCLK GCLK 2 IP_L21P_2/RDWR_B/ GCLK0 R12 DUAL/ 2 IO_L22P_2/D2/GCLK2 Y12 DUAL/ GCLK GCLK 2 IP_L24N_2 R13 INPUT 2 IO_L23N_2/DIN/D0 U12 DUAL 2 IP_L24P_2 T13 INPUT 2 IO_L23P_2/M0 V12 DUAL 2 IP_L31N_2/VREF_2 T15 VREF 2 IO_L25N_2 Y13 I/O 2 IP_L31P_2 U15 INPUT 2 IO_L25P_2 W13 I/O 2 IP_L34N_2 Y16 INPUT 2 IO_L26N_2/VREF_2 U14 VREF 2 IP_L34P_2 W16 INPUT 2 IO_L26P_2 U13 I/O 2 IP_L37N_2 AA19 INPUT 2 IO_L27N_2 T14 I/O 2 IP_L37P_2 AB19 INPUT 2 IO_L27P_2 R14 I/O 2 VCCO_2 T12 VCCO 2 IO_L28N_2 Y14 I/O 2 VCCO_2 U9 VCCO 2 IO_L28P_2 AA14 I/O 2 VCCO_2 V15 VCCO 2 IO_L29N_2 W14 I/O 2 VCCO_2 AA5 VCCO 2 IO_L29P_2 V14 I/O 2 VCCO_2 AA9 VCCO 2 IO_L30N_2 AB15 I/O 2 VCCO_2 AA13 VCCO 2 IO_L30P_2 AA15 I/O 2 VCCO_2 AA18 VCCO 2 IO_L32N_2 W15 I/O 3 IO_L01N_3 C1 I/O 2 IO_L32P_2 Y15 I/O 3 IO_L01P_3 C2 I/O 2 IO_L33N_2 U16 I/O 3 IO_L02N_3/VREF_3 D2 VREF 2 IO_L33P_2 V16 I/O 3 IO_L02P_3 D3 I/O 2 IO_L35N_2/A22 AB17 DUAL 3 IO_L03N_3 E3 I/O 2 IO_L35P_2/A23 AA17 DUAL 3 IO_L03P_3 E4 I/O 2 IO_L36N_2 W17 I/O 3 IO_L04N_3 E1 I/O 2 IO_L36P_2 Y17 I/O 3 IO_L04P_3 D1 I/O 2 IO_L38N_2/A20 Y18 DUAL 3 IO_L05N_3 F4 I/O 2 IO_L38P_2/A21 W18 DUAL 3 IO_L05P_3 F3 I/O 2 IO_L39N_2/VS1/A18 AA20 DUAL 3 IO_L06N_3 G5 I/O 2 IO_L39P_2/VS2/A19 AB20 DUAL 3 IO_L06P_3 G4 I/O 2 IO_L40N_2/CCLK W19 DUAL 3 IO_L07N_3 F1 I/O 2 IO_L40P_2/VS0/A17 Y19 DUAL 3 IO_L07P_3 G1 I/O 2 IP V17 INPUT 3 IO_L08N_3/VREF_3 G6 VREF 2 IP AB2 INPUT 3 IO_L08P_3 G7 I/O 2 IP_L02N_2 AA4 INPUT 3 IO_L09N_3 H4 I/O 2 IP_L02P_2 Y4 INPUT 3 IO_L09P_3 H5 I/O 2 IP_L05N_2 Y6 INPUT 3 IO_L10N_3 H2 I/O 2 IP_L05P_2 AA6 INPUT 3 IO_L10P_3 H3 I/O DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 220

Spartan-3E FPGA Family: Pinout Descriptions Table 153: FG484 Package Pinout (Cont’d) Table 153: FG484 Package Pinout (Cont’d) XC3S1600E FG484 XC3S1600E FG484 Bank Type Bank Type Pin Name Ball Pin Name Ball 3 IO_L11N_3 H1 I/O 3 IO_L33N_3 W1 I/O 3 IO_L11P_3 J1 I/O 3 IO_L33P_3 V1 I/O 3 IO_L12N_3 J6 I/O 3 IO_L34N_3 U4 I/O 3 IO_L12P_3 J5 I/O 3 IO_L34P_3 U3 I/O 3 IO_L13N_3/VREF_3 J3 VREF 3 IO_L35N_3 V4 I/O 3 IO_L13P_3 K3 I/O 3 IO_L35P_3 V3 I/O 3 IO_L14N_3 J8 I/O 3 IO_L36N_3/VREF_3 W3 VREF 3 IO_L14P_3 K8 I/O 3 IO_L36P_3 W2 I/O 3 IO_L15N_3 K4 I/O 3 IO_L37N_3 Y2 I/O 3 IO_L15P_3 K5 I/O 3 IO_L37P_3 Y1 I/O 3 IO_L16N_3 K1 I/O 3 IO_L38N_3 AA1 I/O 3 IO_L16P_3 L1 I/O 3 IO_L38P_3 AA2 I/O 3 IO_L17N_3 L7 I/O 3 IP F2 INPUT 3 IO_L17P_3 K7 I/O 3 IP F5 INPUT 3 IO_L18N_3/LHCLK1 L5 LHCLK 3 IP G3 INPUT 3 IO_L18P_3/LHCLK0 M5 LHCLK 3 IP H7 INPUT 3 IO_L19N_3/LHCLK3/IRDY2 M8 LHCLK 3 IP J7 INPUT 3 IO_L19P_3/LHCLK2 L8 LHCLK 3 IP K2 INPUT 3 IO_L20N_3/LHCLK5 N1 LHCLK 3 IP K6 INPUT 3 IO_L20P_3/LHCLK4/TRDY2 M1 LHCLK 3 IP M2 INPUT 3 IO_L21N_3/LHCLK7 M4 LHCLK 3 IP M6 INPUT 3 IO_L21P_3/LHCLK6 M3 LHCLK 3 IP N3 INPUT 3 IO_L22N_3 N6 I/O 3 IP P3 INPUT 3 IO_L22P_3 N7 I/O 3 IP R8 INPUT 3 IO_L23N_3 P8 I/O 3 IP T1 INPUT 3 IO_L23P_3 N8 I/O 3 IP T7 INPUT 3 IO_L24N_3/VREF_3 N4 VREF 3 IP U5 INPUT 3 IO_L24P_3 N5 I/O 3 IP W4 INPUT 3 IO_L25N_3 P2 I/O 3 IP/VREF_3 L3 VREF 3 IO_L25P_3 P1 I/O 3 IP/VREF_3 T3 VREF 3 IO_L26N_3 R7 I/O 3 VCCO_3 E2 VCCO 3 IO_L26P_3 P7 I/O 3 VCCO_3 H6 VCCO 3 IO_L27N_3 P6 I/O 3 VCCO_3 J2 VCCO 3 IO_L27P_3 P5 I/O 3 VCCO_3 M7 VCCO 3 IO_L28N_3 R2 I/O 3 VCCO_3 N2 VCCO 3 IO_L28P_3 R1 I/O 3 VCCO_3 R5 VCCO 3 IO_L29N_3 R3 I/O 3 VCCO_3 V2 VCCO 3 IO_L29P_3 R4 I/O GND GND A1 GND 3 IO_L30N_3 T6 I/O GND GND A11 GND 3 IO_L30P_3 R6 I/O GND GND A22 GND 3 IO_L31N_3 U2 I/O GND GND B7 GND 3 IO_L31P_3 U1 I/O GND GND B16 GND 3 IO_L32N_3 T4 I/O GND GND C3 GND 3 IO_L32P_3 T5 I/O GND GND C20 GND DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 221

Spartan-3E FPGA Family: Pinout Descriptions Table 153: FG484 Package Pinout (Cont’d) Table 153: FG484 Package Pinout (Cont’d) XC3S1600E FG484 XC3S1600E FG484 Bank Type Bank Type Pin Name Ball Pin Name Ball GND GND E10 GND GND GND AB1 GND GND GND E13 GND GND GND AB12 GND GND GND F6 GND GND GND AB22 GND GND GND F17 GND VCCAUX DONE AA21 CONFIG GND GND G2 GND VCCAUX PROG_B B1 CONFIG GND GND G21 GND VCCAUX TCK E17 JTAG GND GND J4 GND VCCAUX TDI B2 JTAG GND GND J9 GND VCCAUX TDO B20 JTAG GND GND J12 GND VCCAUX TMS D19 JTAG GND GND J14 GND VCCAUX VCCAUX D12 VCCAUX GND GND J19 GND VCCAUX VCCAUX E5 VCCAUX GND GND K10 GND VCCAUX VCCAUX E18 VCCAUX GND GND K12 GND VCCAUX VCCAUX K14 VCCAUX GND GND L2 GND VCCAUX VCCAUX L4 VCCAUX GND GND L6 GND VCCAUX VCCAUX M19 VCCAUX GND GND L9 GND VCCAUX VCCAUX N9 VCCAUX GND GND L13 GND VCCAUX VCCAUX V5 VCCAUX GND GND M10 GND VCCAUX VCCAUX V18 VCCAUX GND GND M14 GND VCCAUX VCCAUX W11 VCCAUX GND GND M17 GND VCCINT VCCINT J10 VCCINT GND GND M21 GND VCCINT VCCINT K9 VCCINT GND GND N11 GND VCCINT VCCINT K11 VCCINT GND GND N13 GND VCCINT VCCINT K13 VCCINT GND GND P4 GND VCCINT VCCINT L10 VCCINT GND GND P9 GND VCCINT VCCINT L11 VCCINT GND GND P11 GND VCCINT VCCINT L12 VCCINT GND GND P14 GND VCCINT VCCINT L14 VCCINT GND GND P19 GND VCCINT VCCINT M9 VCCINT GND GND T2 GND VCCINT VCCINT M11 VCCINT GND GND T21 GND VCCINT VCCINT M12 VCCINT GND GND U6 GND VCCINT VCCINT M13 VCCINT GND GND U17 GND VCCINT VCCINT N10 VCCINT GND GND V10 GND VCCINT VCCINT N12 VCCINT GND GND V13 GND VCCINT VCCINT N14 VCCINT GND GND Y3 GND VCCINT VCCINT P13 VCCINT GND GND Y20 GND GND GND AA7 GND GND GND AA16 GND User I/Os by Bank Table154 indicates how the 304 available user-I/O pins are distributed between the four I/O banks on the FG484 package. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 222

Spartan-3E FPGA Family: Pinout Descriptions Table 154: User I/Os Per Bank for the XC3S1600E in the FG484 Package All Possible I/O Pins by Type Package I/O Bank Maximum I/O Edge I/O INPUT DUAL VREF(1) CLK(2) Top 0 94 56 22 1 7 8 Right 1 94 50 16 21 7 0(2) Bottom 2 94 45 18 24 7 0(2) Left 3 94 63 16 0 7 8 TOTAL 376 214 72 46 28 16 Notes: 1. Some VREF and CLK pins are on INPUT pins. 2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column. Footprint Migration Differences The XC3S1600E FPGA is the only Spartan-3E device offered in the FG484 package. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 223

Spartan-3E FPGA Family: Pinout Descriptions FG484 Footprint X-Ref Target - Figure 88 Bank0 Left Half of Package 1 2 3 4 5 6 7 8 9 10 11 (top view) INPUT INPUT I/O I/O I/O I/O I/O I/O I/O A GND GND L37P_0 L37N_0 L35N_0 L35P_0 L33N_0 L33P_0 L30P_0 L24N_0 L24P_0 I/O I/O I/O I/O I/O B PROG_B TDI VCCO_0 I/O GND VCCO_0 L21N_0 L39P_0 L39N_0 L30N_0 L28P_0 I/O: Unrestricted, GCLK11 214 general-purpose user I/O I/O I/O I/O I/O INPUT INPUT INPUT I/O I/O C GND I/O L21P_0 L01N_3 L01P_3 L40P_0 L34P_0 L34N_0 L31N_0 L28N_0 L25P_0 GCLK10 INPUT: User I/O or 72 reference resistor input for I/O I/O I/O I/O I/O I/O I/O INPUT I/O I/O I/O bank D L04P_3 L02N_3 L02P_3 L40N_0 L38P_0 L38N_0 L36P_0 L31P_0 L29P_0 L25N_0 L22N_0 VREF_3 HSWAP VREF_0 VREF_0 DUAL: Configuration pin, I/O I/O I/O I/O I/O I/O 46 E VCCO_3 VCCAUX INPUT VCCO_0 GND then possible user I/O L04N_3 L03N_3 L03P_3 L36N_0 L29N_0 L22P_0 I/O 28 VvoRltEaFge: Uresfeerr eI/nOc eo rf oinr pbuatn k F L0I7/ON_3 INPUT L0I5/OP_3 L0I5/ON_3 INPUT GND VLR32ENF__00 L3I2/OP_0 I/O ILN23PNU_T0 ILN2P3PU_T0 I/O I/O I/O I/O I/O INPUT INPUT 16 CLK: User I/O, input, or G L07P_3 GND INPUT L06P_3 L06N_3 L08N_3 L08P_3 I/O L26N_0 L26P_0 VCCO_0 clock buffer input VREF_3 INPUT I/O I/O I/O I/O I/O I/O I/O 2 CcoOnNfigFuIGra:t iDone dpiicnasted H L11N_3 L10N_3 L10P_3 L09N_3 L09P_3 VCCO_3 INPUT L27N_0 L27P_0 I/O LG2C0LNK_90 I/O I/O I/O I/O I/O 4 JTAG: Dedicated JTAG J L11P_3 VCCO_3 VLR13ENF__33 GND L12P_3 L12N_3 INPUT L14N_3 GND VCCINT I/O port pins I/O I/O I/O I/O I/O I/O K INPUT INPUT VCCINT GND VCCINT GND: Ground L16N_3 L13P_3 L15N_3 L15P_3 L17P_3 L14P_3 48 I/O I/O I/O INPUT I/O 3 L GND VCCAUX L18N_3 GND L19P_3 GND VCCINT VCCINT 28 VsuCpCpOly: f oOru btpauntk voltage ank L1I6/OP_3 VRIE/OF_3 I/O LHIC/OLK1 L17N_3 LHIC/OLK2 B M L20P_3 INPUT L21P_3 L21N_3 L18P_3 INPUT VCCO_3 L19N_3 VCCINT GND VCCINT LHCLK4 LHCLK3 VCCINT: Internal core TRDY2 LHCLK6 LHCLK7 LHCLK0 IRDY2 16 supply voltage (+1.2V) I/O I/O I/O I/O I/O I/O N L20N_3 VCCO_3 INPUT L24N_3 VCCAUX VCCINT GND L24P_3 L22N_3 L22P_3 L23P_3 LHCLK5 VREF_3 VCCAUX: Auxiliary supply 10 voltage (+2.5V) I/O I/O I/O I/O I/O I/O I/O P INPUT GND GND GND L25P_3 L25N_3 L27P_3 L27N_3 L26P_3 L23N_3 L17P_2 N.C.: Not connected 0 I/O I/O I/O I/O I/O I/O I/O I/O I/O R VCCO_3 INPUT L13N_2 L20P_2 L28P_3 L28N_3 L29N_3 L29P_3 L30P_3 L26N_3 L17N_2 D4 VREF_2 GCLK14 I/O T INPUT GND INPUT I/O I/O I/O INPUT I/O I/O I/O L20N_2 VREF_3 L32N_3 L32P_3 L30N_3 L10N_2 L13P_2 L16P_2 D3 GCLK15 I/O I/O I/O I/O I/O I/O I/O I/O U INPUT GND VCCO_2 L19N_2 L31P_3 L31N_3 L34P_3 L34N_3 L07N_2 L10P_2 L16N_2 D6 GCLK13 I/O I/O V I/O VCCO_3 I/O I/O VCCAUX I/O I/O L09N_2 I/O GND L19P_2 L33P_3 L35P_3 L35N_3 L04P_2 L07P_2 L12P_2 D7 VREF_2 GCLK12 I/O I/O I/O I/O I/O I/O I/O I/O INPUT W L36N_3 INPUT L03P_2 VCCAUX L33N_3 L36P_3 DOUT L04N_2 L06N_2 L09P_2 L12N_2 L15P_2 VREF_3 BUSY I/O Y I/O I/O GND INPUT L03N_2 INPUT I/O I/O I/O INPUT INPUT L37P_3 L37N_3 L02P_2 MOSI L05N_2 L06P_2 L15N_2 L18P_2 CSI_B A I/O I/O I/O INPUT INPUT I/O INPUT L01P_2 VCCO_2 GND VCCO_2 I/O L18N_2 A L38N_3 L38P_3 L02N_2 L05P_2 L11P_2 CSO_B VREF_2 A I/O I/O INPUT INPUT I/O I/O I/O I/O GND INPUT L01N_2 I/O B VREF_2 L08P_2 L08N_2 L11N_2 L14N_2 L14P_2 D5 INIT_B Bank 2 DS312_10_101905 Figure 88: FG484 Package Footprint (top view) DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 224

Spartan-3E FPGA Family: Pinout Descriptions FG484 Footprint Bank0 12 13 14 15 16 17 18 19 20 21 22 Right Half of Package INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O (top view) L12N_0 L03N_0 GND A L17N_0 L17P_0 L12P_0 L07N_0 L07P_0 L04P_0 L04N_0 L03P_0 VREF_0 VREF_0 I/O I/O I/O I/O INPUT L19P_0 I/O VCCO_0 L09N_0 GND VCCO_0 INPUT TDO L38N_1 L38P_1 B L05P_0 GCLK6 VREF_0 LDC2 LDC1 I/O I/O I/O INPUT I/O I/O INPUT I/O I/O L19N_0 I/O GND L37N_1 L37P_1 C L14P_0 L09P_0 L06N_0 L05N_0 L01N_0 L01P_0 GCLK7 LDC0 HDC INPUT I/O INPUT I/O INPUT INPUT INPUT I/O VCCAUX TMS INPUT D L14N_0 L11N_0 L08P_0 L06P_0 L02N_0 L02P_0 VREF_1 L34N_1 I/O I/O INPUT I/O I/O I/O L18N_0 GND I/O TCK VCCAUX VCCO_1 E L11P_0 L08N_0 L36P_1 L36N_1 L34P_1 GCLK5 I/O I/O I/O I/O I/O I/O I/O L18P_0 VCCO_0 I/O GND INPUT F L15P_0 L10P_0 L35P_1 L35N_1 L32N_1 L31N_1 GCLK4 I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT GND G VREF_0 L15N_0 L13P_0 L10N_0 L30P_1 L33N_1 L33P_1 L32P_1 L31P_1 INPUT I/O I/O I/O I/O I/O I/O I/O L20P_0 I/O INPUT VCCO_1 L28N_1 H L16P_0 L13N_0 L30N_1 L29P_1 L29N_1 L28P_1 GCLK8 VREF_1 I/O I/O I/O I/O I/O I/O GND GND INPUT GND INPUT J L16N_0 L25P_1 L27N_1 L27P_1 L26N_1 L26P_1 I/O I/O I/O I/O I/O I/O GND VCCINT VCCAUX L23N_1 INPUT VCCO_1 L22N_1 K L25N_1 L23P_1 L24P_1 L24N_1 A0 A1 INPUT I/O I/O L2I0/OP_1 I/O I/O VCCINT GND VCCINT INPUT VCCO_1 L21P_1 L21N_1 A6 L20N_1 L22P_1 L 1 VREF_1 RHAC4LK6 RHAC3LK7 RIHRCDLYK14 RHAC5LK5 A2 k n VCCINT VCCINT GND L1I9/OP_1 L1I9A/ON7_1 GND INPUT VCCAUX L1I7/ON_1 GND L1I8/ON_1 M Ba RHAC8LK2 RTHRCDLYK13 VREF_1 RHAC9LK1 I/O I/O I/O I/O I/O I/O VCCINT GND VCCINT INPUT L16N_1 L16P_1 INPUT L18P_1 N L15N_1 L15P_1 L17P_1 A10 A11 A12 RHCLK0 INPUT I/O L21N_2 VCCINT GND I/O I/O I/O L12N_1 GND INPUT VCCO_1 I/O P M2 L14N_1 L14P_1 L12P_1 L13N_1 GCLK1 VREF_1 INPUT INPUT I/O I/O I/O I/O I/O I/O I/O L21P_2 INPUT VCCO_1 R RDWR_B L24N_2 L27P_2 L10N_1 L09P_1 L09N_1 L11P_1 L11N_1 L13P_1 GCLK0 INPUT INPUT I/O I/O I/O I/O I/O VCCO_2 L31N_2 INPUT INPUT GND T L24P_2 L27N_2 L10P_1 L06P_1 L06N_1 L08N_1 VREF_2 I/O I/O I/O I/O INPUT I/O I/O I/O I/O L23N_2 L26N_2 GND INPUT L07N_1 U DIN L26P_2 L31P_2 L33N_2 L04N_1 L07P_1 L08P_1 D0 VREF_2 VREF_1 I/O I/O I/O I/O I/O I/O L23P_2 GND VCCO_2 INPUT VCCAUX VCCO_1 V L29P_2 L33P_2 L04P_1 L03P_1 L05N_1 M0 I/O I/O I/O I/O I/O I/O I/O I/O INPUT I/O I/O L22N_2 L38P_2 L40N_2 L03N_1 L02N_1 W D1 L25P_2 L29N_2 L32N_2 L34P_2 L36N_2 L05P_1 GCLK3 A21 CCLK VREF_1 A13 I/O I/O I/O I/O I/O L22P_2 I/O I/O I/O INPUT I/O L38N_2 L40P_2 GND L02P_1 L01N_1 Y D2 L25N_2 L28N_2 L32P_2 L34N_2 L36P_2 VS0 GCLK2 A20 A17 A14 A15 I/O I/O I/O I/O INPUT I/O I/O A VCCO_2 GND L35P_2 VCCO_2 L39N_2 DONE L01P_1 M1 L28P_2 L30P_2 L37N_2 VS1 A A23 A18 A16 GND I/O I/O I/O I/O L3I5/ON_2 I/O INPUT L3I9/OP_2 I/O GND A L30N_2 L37P_2 VS2 VREF_2 B A22 A19 Bank 2 DS312_11_101905 DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 225

Spartan-3E FPGA Family: Pinout Descriptions Revision History The following table shows the revision history for this document. Date Version Revision 03/01/2005 1.0 Initial Xilinx release. 03/21/2005 1.1 Added XC3S250E in the CP132 package to Table128. Corrected number of differential I/O pairs on CP132. Added pinout and footprint information for the CP132, FG400, and FG484 packages. Removed IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages. 11/23/2005 2.0 Corrected title of Table152. Updated differential pair numbering for some pins in Bank 0 of the FG400 package, affecting Table151 and Figure87. Pin functionality and ball assignment were not affected. Added Package Thermal Characteristics section. Added package mass values to Table125. 03/22/2006 3.0 Included I/O pins, not just input-only pins under the VREF description in Table124. Clarified that some global clock inputs are Input-only pins in Table124. Added information on the XC3S100E in the CP132 package, affecting Table128, Table129, Table132, Table133, Table135, and Figure81. Ball A12 on the XC3S1600E in the FG320 package a full I/O pin, not an Input-only pin. Corrected the I/O counts for the XC3S1600E in the FG320 package, affecting Table128, Table149, Table150, and Figure86. Corrected pin type for XC3S1600E balls N14 and N15 in Table147. 05/19/2006 3.1 Minor text edits. 11/09/2006 3.4 Added package thermal data for the XC3S100E in the CP132 package to Table129. Corrected pin migration arrows for balls E17 and F4 between the XC3S500E and XC3S1600E in Table150. Promoted Module4 to Production status. Synchronized all modules to v3.4. 03/16/2007 3.5 Minor formatting changes. 05/29/2007 3.6 Corrected ‘Lxx’ to ‘Lxxy’ in Table124. Noted that some GCLK and VREF pins are on INPUT pins in Table124 and Table128. Added link before Table 127 to Material Declaration Data Sheets. 04/18/2008 3.7 Added XC3S500E VQG100 package. Added Material Declaration Data Sheet links in Table 127. Updated Thermal Characteristics in Table129. Updated links. 08/26/2009 3.8 Minor typographical updates. 10/29/2012 4.0 Added Notice of Disclaimer. This product is not recommended for new designs. Updated the XC3S250E-FT256 in Table128. 07/19/2013 4.1 Removed banner. This product IS recommended for new designs. 12/14/2018 4.2 Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024). Updated Table125 and Note1. Updated the Mechanical Drawings section and removed Table 127. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 226

Spartan-3E FPGA Family: Pinout Descriptions Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 227