0 R XC2C64A CoolRunner-II CPLD DS311 (v2.3) November 19, 2008 Product Specification 0 0 Features Description (cid:129) Optimized for 1.8V systems The CoolRunner-II 64-macrocell device is designed for both - As fast as 4.6 ns pin-to-pin logic delays high performance and low power applications. This lends - As low as 15 μA quiescent current power savings to high-end communication equipment and high speed to battery operated devices. Due to the low (cid:129) Industry’s best 0.18 micron CMOS CPLD power stand-by and dynamic operation, overall system reli- - Optimized architecture for effective logic synthesis ability is improved. - Multi-voltage I/O operation — 1.5V to 3.3V This device consists of four Function Blocks inter-connected (cid:129) Available in multiple package options by a low power Advanced Interconnect Matrix (AIM). The - 44-pin VQFP with 33 user I/Os AIM feeds 40 true and complement inputs to each Function - 48-land QFN with 37 user I/Os Block. The Function Blocks consist of a 40 by 56 P-term - 56-ball CP BGA with 45 user I/Os PLA and 16 macrocells which contain numerous configura- - 100-pin VQFP with 64 user I/Os tion bits that allow for combinational or registered modes of - Pb-free available for all packages operation. (cid:129) Advanced system features Additionally, these registers can be globally reset or preset - Fastest in system programming and configured as a D or T flip-flop or as a D latch. There · 1.8V ISP using IEEE 1532 (JTAG) interface are also multiple clock signals, both global and local product - IEEE1149.1 JTAG Boundary Scan Test term types, configured on a per macrocell basis. Output pin - Optional Schmitt-trigger input (per pin) configurations include slew rate limit, bus hold, pull-up, - Two separate I/O banks open drain, and programmable grounds. A Schmitt trigger - RealDigital 100% CMOS product term generation input is available on a per input pin basis. In addition to stor- - Flexible clocking modes ing macrocell output states, the macrocell registers can be · Optional DualEDGE triggered registers configured as "direct input" registers to store signals directly - Global signal options with macrocell control from input pins. · Multiple global clocks with phase selection per macrocell Clocking is available on a global or Function Block basis. · Multiple global output enables Three global clocks are available for all Function Blocks as a · Global set/reset synchronous clock source. Macrocell registers can be indi- - Efficient control term clocks, output enables, and vidually configured to power up to the zero or one state. A set/resets for each macrocell and shared across global set/reset control line is also available to asynchro- function blocks nously set or reset selected registers during operation. - Advanced design security Additional local clock, synchronous clock-enable, asynchro- - Optional bus-hold, 3-state, or weak pullup on nous set/reset, and output enable signals can be formed selected I/O pins using product terms on a per-macrocell or per-Function - Open-drain output option for Wired-OR and LED Block basis. drive A DualEDGE flip-flop feature is also available on a per mac- - Optional configurable grounds on unused I/Os rocell basis. This feature allows high performance synchro- - Mixed I/O voltages compatible with 1.5V, 1.8V, nous operation based on lower frequency clocking to help 2.5V, and 3.3V logic levels reduce the total power consumption of the device. - PLA architecture The CoolRunner-II 64-macrocell CPLD is I/O compatible · Superior pinout retention with standard LVTTL and LVCMOS18, LVCMOS25, and · 100% product term routability across function LVCMOS33 (see Table1). This device is also 1.5V I/O com- block patible with the use of Schmitt-trigger inputs. - Hot pluggable Another feature that eases voltage translation is I/O bank- Refer to the CoolRunner™-II family data sheet for architec- ing. Two I/O banks are available on the CoolRunner-II64A ture description. macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. © 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS311 (v2.3) November 19, 2008 www.xilinx.com 1 Product Specification

XC2C64A CoolRunner-II CPLD R RealDigital Design Technology LVTTL input buffer and Push-Pull output buffer. The LVCMOSstandard is used in 3.3V, 2.5V, and 1.8V applica- Xilinx® CoolRunner-II CPLDs are fabricated on a tions. CoolRunner-II CPLDs are also 1.5V I/O compatible 0.18micron process technology which is derived from lead- with the use of Schmitt-trigger inputs. ing edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes Table 1: I/O Standards for XC2C64A use of CMOS technology in both the fabrication and design Board methodology. RealDigital design technology employs a cas- IOSTANDARD Output Input Input Termination cade of CMOS gates to implement sum of products instead Attribute V V V Voltage V of traditional sense amplifier methodology. Due to this tech- CCIO CCIO REF T nology, Xilinx CoolRunner-II CPLDs achieve both high per- LVTTL 3.3 3.3 N/A N/A formance and low power operation. LVCMOS33 3.3 3.3 N/A N/A Supported I/O Standards LVCMOS25 2.5 2.5 N/A N/A The CoolRunner-II 64 macrocell features both LVCMOS LVCMOS18 1.8 1.8 N/A N/A and LVTTL I/O implementations. See Table1 for I/O stan- LVCMOS15(1) 1.5 1.5 N/A N/A dard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an 1. LVCMOS15 requires Schmitt-trigger inputs. 20 15 A) m (C 10 C I 5 0 0 50 100 150 200 250 Frequency (MHz) DS092_01_092302 Figure 1: I vs Frequency CC Table 2: I vs Frequency (LVCMOS 1.8V T = 25°C)(1) CC A Frequency (MHz) 0 25 50 75 100 150 175 200 225 240 Typical I (mA) 0.017 1.8 3.7 5.5 7.48 11.0 12.7 14.6 15.3 17.77 CC Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block). 2 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification

R XC2C64A CoolRunner-II CPLD Absolute Maximum Ratings Symbol Description Value Units V Supply voltage relative to ground –0.5 to 2.0 V CC V Supply voltage for output drivers –0.5 to 4.0 V CCIO V (2) JTAG input voltage limits –0.5 to 4.0 V JTAG V JTAG input supply voltage –0.5 to 4.0 V CCAUX V (1) Input voltage relative to ground(1) –0.5 to 4.0 V IN V (1) Voltage applied to 3-state output(1) –0.5 to 4.0 V TS V (3) Storage Temperature (ambient) –65 to +150 °C STG T Junction Temperature +150 °C J Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins might undershoot to –2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427. Recommended Operating Conditions Symbol Parameter Min Max Units V Supply voltage for internal logic Commercial T = 0°C to +70°C 1.7 1.9 V CC A and input buffers Industrial T = –40°C to +85°C 1.7 1.9 V A V Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V CCIO Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V V JTAG programming pins 1.7 3.6 V CCAUX DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions Typical Max. Units I Standby current Commercial V = 1.9V, V = 3.6V 31 100 μA CCSB CC CCIO I Standby current Industrial V = 1.9V, V = 3.6V 43 165 μA CCSB CC CCIO I (1) Dynamic current f = 1 MHz - 500 μA CC f = 50 MHz - 5 mA C JTAG input capacitance f = 1 MHz - 10 pF JTAG C Global clock input capacitance f = 1 MHz - 12 pF CLK C I/O capacitance f = 1 MHz - 10 pF IO I (2) Input leakage current V = 0V or V to 3.9V - +/–1 μA IL IN CCIO I (2) I/O High-Z leakage V = 0V or V to 3.9V - +/–1 μA IH IN CCIO Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at V =V = 1.9V. CC CCIO 2. See Quality and Reliability section of the CoolRunner-II family data sheet. DS311 (v2.3) November 19, 2008 www.xilinx.com 3 Product Specification

XC2C64A CoolRunner-II CPLD R LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage 3.0 3.6 V CCIO V High level input voltage 2 3.9 V IH V Low level input voltage –0.3 0.8 V IL V High level output voltage I = –8 mA, V = 3V V – 0.4V - V OH OH CCIO CCIO I = –0.1 mA, V = 3V V – 0.2V - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 3V - 0.4 V OL OL CCIO I = 0.1 mA, V = 3V - 0.2 V OL CCIO LVCMOS 2.5V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage 2.3 2.7 V CCIO V High level input voltage 1.7 V + 0.3(1) V IH CCIO V Low level input voltage –0.3 0.7 V IL V High level output voltage I = –8 mA, V = 2.3V V – 0.4V - V OH OH CCIO CCIO I = –0.1 mA, V = 2.3V V – 0.2V - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 2.3V - 0.4 V OL OL CCIO I = 0.1 mA, V = 2.3V - 0.2 V OL CCIO 1. The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V without physical damage. LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage - 1.7 1.9 V CCIO V High level input voltage - 0.65 x V V + 0.3(1) V IH CCIO CCIO V Low level input voltage - –0.3 0.35 x V V IL CCIO V High level output voltage I = –8 mA, V = 1.7V V – 0.45 - V OH OH CCIO CCIO I = –0.1 mA, V = 1.7V V – 0.2 - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 1.7V - 0.45 V OL OL CCIO I = 0.1 mA, V = 1.7V - 0.2 V OL CCIO 1. The V Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V IH without physical damage. 4 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification

R XC2C64A CoolRunner-II CPLD LVCMOS 1.5V DC Voltage Specifications Symbol Parameter(1) Test Conditions Min. Max. Units V Input source voltage - 1.4 1.6 V CCIO V Input hysteresis threshold voltage - 0.5 x V 0.8 x V V T+ CCIO CCIO V - 0.2 x V 0.5 x V V T- CCIO CCIO V High level output voltage I = –8 mA, V = 1.4V V – 0.45 - V OH OH CCIO CCIO I = –0.1 mA, V = 1.4V V – 0.2 - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 1.4V - 0.4 V OL OL CCIO I = 0.1 mA, V = 1.4V - 0.2 V OL CCIO Notes: 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage - 1.4 3.9 V CCIO V Input hysteresis threshold voltage - 0.5 x V 0.8 x V V T+ CCIO CCIO V - 0.2 x V 0.5 x V V T- CCIO CCIO DS311 (v2.3) November 19, 2008 www.xilinx.com 5 Product Specification

XC2C64A CoolRunner-II CPLD R AC Electrical Characteristics Over Recommended Operating Conditions -5 -7 Symbol Parameter Min. Max. Min. Max. Units T Propagation delay single p-term - 4.6 - 6.7 ns PD1 T Propagation delay OR array - 5.0 - 7.5 ns PD2 T Direct input register clock setup time 2.4 - 3.3 - ns SUD T Setup time (single p-term) 2.0 - 2.5 - ns SU1 T Setup time (OR array) 2.4 - 3.3 - ns SU2 T Direct input register hold time 0 - 0 - ns HD T P-term hold time 0 - 0 - ns H T Clock to output - 3.9 - 6.0 ns CO F (1) Internal toggle rate(1) - 500 - 300 MHz TOGGLE F (2) Maximum system frequency(2) - 263 - 159 MHz SYSTEM1 F (2) Maximum system frequency(2) - 238 - 141 MHz SYSTEM2 F (3) Maximum external frequency(3) - 169 - 118 MHz EXT1 F (3) Maximum external frequency(3) - 159 - 108 MHz EXT2 T Direct input register p-term clock setup time 0.9 - 1.7 - ns PSUD T P-term clock setup time (single p-term) 0.6 - 0.9 - ns PSU1 T P-term clock setup time (OR array) 1.0 - 1.7 - ns PSU2 T Direct input register p-term clock hold time 1.3 - 1.4 - ns PHD T P-term clock hold 1.5 - 1.7 - ns PH T P-term clock to output - 6.0 - 8.4 ns PCO T /T Global OE to output enable/disable - 8.0 - 10.0 ns OE OD T /T P-term OE to output enable/disable - 9.0 - 11.0 ns POE POD T /T Macrocell driven OE to output enable/disable - 9.0 - 11.0 ns MOE MOD T P-term set/reset to output valid - 7.3 - 9.7 ns PAO T Global set/reset to output valid - 6.0 - 8.3 ns AO T Register clock enable setup time 3.0 - 3.7 - ns SUEC T Register clock enable hold time 0 - 0 - ns HEC T Global clock pulse width High or Low 1.4 - 2.2 - ns CW T P-term pulse width High or Low 5.0 - 7.5 - ns PCW T Asynchronous preset/reset pulse width (High or Low) 5.0 - 7.5 - ns APRPW T (4) Configuration time - 50.0 - 50.0 μs CONFIG Notes: 1. F is the maximum frequency of a dual edge triggered T flip-flop with output enabled. TOGGLE 2. F (1/T ) is the internal operating frequency for a device fully populated with 16-bit up/down, Resetable binary counter SYSTEM CYCLE (one counter per function block). 3. F (1/T +T ) is the maximum external frequency. EXT SU1 CO 4. Typical configuration current during T is 2.3 mA. CONFIG 6 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification

R XC2C64A CoolRunner-II CPLD Internal Timing Parameters -5 -7 Symbol Parameter(1) Min. Max. Min. Max. Units Buffer Delays T Input buffer delay - 1.7 - 2.4 ns IN T Direct data register input delay - 2.6 - 4.0 ns DIN T Global clock buffer delay - 1.6 - 2.5 ns GCK T Global set/reset buffer delay - 2.4 - 3.5 ns GSR T Global 3-state buffer delay - 2.7 - 3.9 ns GTS T Output buffer delay - 1.9 - 2.8 ns OUT T Output buffer enable/disable delay - 5.3 - 6.1 ns EN P-term Delays T Control term delay - 2.0 - 2.5 ns CT T Single P-term delay adder - 0.5 - 0.8 ns LOGI1 T Multiple P-term delay adder - 0.4 - 0.8 ns LOGI2 Macrocell Delay T Input to output valid - 0.5 - 0.7 ns PDI T Setup before clock 1.4 - 1.8 - ns SUI T Hold after clock 0.0 - 0.0 - ns HI T Enable clock setup time 0.9 - 1.3 - ns ECSU T Enable clock hold time 0 - 0 - ns ECHO T Clock to output valid - 0.4 - 0.7 ns COI T Set/reset to output valid - 1.7 - 2.0 ns AOI T Clock doubler delay - 0 - 0 ns CDBL Feedback Delays T Feedback delay - 1.5 - 3.0 ns F T Macrocell to global OE delay - 1.7 - 1.7 ns OEM I/O Standard Time Adder Delays 1.5V CMOS T Hysteresis input adder - 4.0 - 6.0 ns HYS15 T Output adder - 0.9 - 1.5 ns OUT15 T Output slew rate adder - 4.0 - 6.0 ns SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Hysteresis input adder - 3.0 - 4.0 ns HYS18 T Output adder - 0 - 0 ns OUT18 T Output slew rate adder - 3.5 - 5.0 ns SLEW DS311 (v2.3) November 19, 2008 www.xilinx.com 7 Product Specification

XC2C64A CoolRunner-II CPLD R Internal Timing Parameters (Continued) -5 -7 Symbol Parameter(1) Min. Max. Min. Max. Units I/O Standard Time Adder Delays 2.5V CMOS T Standard input adder - 0.5 - 0.6 ns IN25 T Hysteresis input adder - 2.5 - 3.0 ns HYS25 T Output adder - 0.8 - 0.9 ns OUT25 T Output slew rate adder - 4.0 - 5.0 ns SLEW25 I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder - 0.5 - 0.6 ns IN33 T Hysteresis input adder - 2.0 - 3.0 ns HYS33 T Output adder - 1.2 - 1.4 ns OUT33 T Output slew rate adder - 4.0 - 5.0 ns SLEW33 1. 1.5 ns input pin signal rise/fall. 8 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification

R XC2C64A CoolRunner-II CPLD Switching Characteristics Typical I/O Output Curves VCC = VCCIO = 1.8V, T = 25oC Vdde1 5.5 )A 1.5V m 5.0 ( tne 12..85VV r ru 3.3V C 4.5 tu p s) tuO n (D2 4.0 O/I P T 3.5 3.0 Vo Output Volts 1 2 4 8 16 Figure 4: Typical I/O Output Curves Number of Outputs Switching DS092_02_092302 Figure 2: Derating Curve for T PD AC Test Circuit VCC R1 Device Test Point Under Test R2 CL Output Type R1 R2 CL LVTTL33 268Ω 235Ω 35 pF LVCMOS33 275Ω 275Ω 35 pF LVCMOS25 188Ω 188Ω 35 pF LVCMOS18 112.5Ω 112.5Ω 35 pF LVCMOS15 150Ω 150Ω 35 pF Notes: 1. CL includes test fixtures and probe capacitance. 2. 1.5 ns maximum rise/fall times on inputs. DS311_03_102108 Figure 3: AC Load Circuit DS311 (v2.3) November 19, 2008 www.xilinx.com 9 Product Specification

XC2C64A CoolRunner-II CPLD R Pin Descriptions Function Block Macrocell PC44(1) VQ44 QFG48 CP56 VQ100 I/O Banking 1 1 44 38 F1 13 Bank 2 1 2 43 37 5 E3 12 Bank 2 1 3 42 36 4 E1 11 Bank 2 1 4 - - - 10 Bank 2 1 5 - - - 9 Bank 2 1 6 - - - 8 Bank 2 1 7 - - - 7 Bank 2 1 8 - - - 6 Bank 2 1(GTS1) 9 40 34 2 D1 4 Bank 2 1(GTS0) 10 39 33 1 C1 3 Bank 2 1(GTS3) 11 38 32 48 A3 2 Bank 2 1(GTS2) 12 37 31 47 A2 1 Bank 2 1(GSR) 13 36 30 46 B1 99 Bank 2 1 14 - - A1 97 Bank 2 1 15 - - C3 94 Bank 2 1 16 - - - 92 Bank 2 2 1 1 39 6 G1 14 Bank 1 2 2 2 40 7 F3 15 Bank 1 2 3 - - 8 - 16 Bank 1 2 4 - - 9 - 17 Bank 1 2 5 3 41 10 H1 18 Bank 1 2 6 4 42 G3 19 Bank 1 2(GCK0) 7 5 43 11 J1 22 Bank 1 2(GCK1) 8 6 44 12 K1 23 Bank 1 2 9 - - K4 24 Bank 1 2(GCK2) 10 7 1 13 K2 27 Bank 1 2 11 - - - 28 Bank 1 2 12 8 2 14 K3 29 Bank 1 2 13 9 3 15 H3 30 Bank 1 2 14 - - K5 32 Bank 1 2 15 - - - 33 Bank 1 2 16 - - - 34 Bank 1 10 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification

R XC2C64A CoolRunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell PC44(1) VQ44 QFG48 CP56 VQ100 I/O Banking 3 1 35 29 45 C4 91 Bank 2 3 2 34 28 44 A4 90 Bank 2 3 3 33 27 43 C5 89 Bank 2 3 4 - - A7 81 Bank 2 3 5 - - 39 C8 79 Bank 2 3 6 29 23 38 A8 78 Bank 2 3 7 - - A9 77 Bank 2 3 8 - - - 76 Bank 2 3 9 - - 37 A5 74 Bank 2 3 10 28 22 36 A10 72 Bank 2 3 11 27 21 35 B10 71 Bank 2 3 12 26 20 34 C10 70 Bank 2 3 13 - - D8 68 Bank 2 3 14 25 19 33 E8 67 Bank 2 3 15 24 18 32 D10 64 Bank 2 3 16 - - - 61 Bank 2 4 1 11 5 17 K6 35 Bank 1 4 2 12 6 18 H5 36 Bank 1 4 3 - - K7 37 Bank 1 4 4 - - - 39 Bank 1 4 5 - - H7 40 Bank 1 4 6 - - - 41 Bank 1 4 7 14 8 20 H8 42 Bank 1 4 8 - - - 43 Bank 1 4 9 - - - 49 Bank 1 4 10 - - 24 K8 50 Bank 1 4 11 18 12 25 H10 52 Bank 1 4 12 - - 26 - 53 Bank 1 4 13 19 13 27 G10 55 Bank 1 4 14 20 14 28 - 56 Bank 1 4 15 22 16 F10 58 Bank 1 4 16 - - 30 E10 60 Bank 1 1. This is an obsolete package type. It remains here for legacy support only. 2. GTS = global output enable, GSR = global set reset, GCK = global clock. 3. GCK, GSR, and GTS pins can also be used for general purpose I/Os. DS311 (v2.3) November 19, 2008 www.xilinx.com 11 Product Specification

XC2C64A CoolRunner-II CPLD R XC2C64A Global, JTAG, Power/Ground, and No Connect Pins Pin Type PC44(1) VQ44 QFG48 CP56 VQ100 TCK 17 11 23 K10 48 TDI 15 9 21 J10 45 TDO 30 24 40 A6 83 TMS 16 10 22 K9 47 V (JTAG supply voltage) 41 35 3 D3 5 CCAUX Power internal (V ) 21 15 29 G8 26,57 CC Power bank 1 I/O (V ) 13 7 19 H6 38, 51 CCIO1 Power bank 2 I/O (V ) 32 26 42 C6 88, 98 CCIO2 Ground 10, 23, 31 4,17,25 16, 31, 41 H4, F8, C7 21, 31, 62, 69, 84,100 No connects 20, 25, 44, 46, 54, 59, 63, 65, 66, 73, 75, 80, 82, 85, 86, 87, 93, 95, 96 Total user I/O 33 33 37 45 64 1. This is an obsolete package type. It remains here for legacy support only. Ordering Information Device Ordering No. Pin/Ball θ θ Package Body Comm(C) JA JC and Part Marking No. Spacing (°C/Watt) ({C/Watt) Package Type Dimensions I/O Ind. (I)(1) XC2C64A-5QFG48C 0.5mm 31.2 21.2 Quad Flat No Lead 7mm x 7mm 37 C XC2C64A-7QFG48C 0.5mm 31.2 21.2 Quad Flat No Lead 7mm x 7mm 37 C XC2C64A-5VQ44C 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 10mm x 10mm 33 C XC2C64A-7VQ44C 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 10mm x 10mm 33 C XC2C64A-5CP56C 0.5mm 65.0 15.0 Chip Scale Package 6mm x 6mm 45 C XC2C64A-7CP56C 0.5mm 65.0 15.0 Chip Scale Package 6mm x 6mm 45 C XC2C64A-5VQ100C 0.5mm 53.2 14.6 Very Thin Quad Flat Pack 14mm x 14mm 64 C XC2C64A-7VQ100C 0.5mm 53.2 14.6 Very Thin Quad Flat Pack 14mm x 14mm 64 C XC2C64A-5VQG44C 0.8mm 46.6 8.2 Very Thin Quad Flat 10mm x 10mm 33 C Pack; Pb-free XC2C64A-7VQG44C 0.8mm 46.6 8.2 Very Thin Quad Flat 10mm x 10mm 33 C Pack; Pb-free XC2C64A-5CPG56C 0.5mm 65.0 15.0 Chip Scale Package; 6mm x 6mm 45 C Pb-free XC2C64A-7CPG56C 0.5mm 65.0 15.0 Chip Scale Package; 6mm x 6mm 45 C Pb-free XC2C64A-5VQG100C 0.5mm 53.2 14.6 Very Thin Quad Flat 14mm x 14mm 64 C Pack; Pb-free XC2C64A-7VQG100C 0.5mm 53.2 14.6 Very Thin Quad Flat 14mm x 14mm 64 C Pack; Pb-free XC2C64A-7VQ44I 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 10mm x 10mm 33 I XC2C64A-7QFG48I 0.5mm 31.2 21.2 Quad Flat No Lead; 7mm x 7mm 37 I Pb-free XC2C64A-7CP56I 0.5mm 65.0 15.0 Chip Scale Package 6mm x 6mm 45 I XC2C64A-7VQ100I 0.5mm 53.2 14.6 Very Thin Quad Flat Pack 14mm x 14mm 64 I 12 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification

R XC2C64A CoolRunner-II CPLD Device Ordering No. Pin/Ball θ θ Package Body Comm(C) JA JC and Part Marking No. Spacing (°C/Watt) ({C/Watt) Package Type Dimensions I/O Ind. (I)(1) XC2C64A-7VQG44I 0.8mm 46.6 8.2 Very Thin Quad Flat 10mm x 10mm 33 I Pack; Pb-free XC2C64A-7CPG56I 0.5mm 65.0 15.0 Chip Scale Package; 6mm x 6mm 45 I Pb-free XC2C64A-7VQG100I 0.5mm 53.2 14.6 Very Thin Quad Flat 14mm x 14mm 64 I Pack; Pb-free Notes: 1. C = Commercial (TA = 0°C to +70°C); I = Industrial (TA = –40°C to +85°C). Standard Example: X C 2 C 1 28 - 4 TQ 144 C Pb-Free Example: X C 2 C 1 28 -4 TQ G 144 C Device Device Speed Grade Speed Grade Package Type Package Type Number of Pins Pb-Free Temperature Range Number of Pins Temperature Range Device Part Marking R Device Type XC2Cxxx Package TQ144 This line not related to device part number Speed 7C Operating Range Part marking for non-chip scale package DS311_05_102108 Figure 5: Sample Package with Part Marking Note: Due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale and quad flat no lead packages by line are: 1. X (Xilinx logo) then truncated part number 4. Device code, speed, operating temperature, three digits not related to device part number. Device codes: C3 = 2. Not related to device part number CP56, C4 = CPG56, Q2 = QFG48. 3. Not related to device part number DS311 (v2.3) November 19, 2008 www.xilinx.com 13 Product Specification

XC2C64A CoolRunner-II CPLD R Package Pinout Diagrams I/O(2) I/O(2) I/OI/OI/OI/OI/OI/OI/OVAUXI/O(1) I/O(1) 1I/O(1)48I/O(1)47I/O(3)46I/O45I/O44I/O43Vccio242Gnd41TDO40I/O3938I/O37I/O36 I/O I/O(1) 2 35 I/O 43210987654 I/O(2) 1 4444433333333 I/O(1) VAUX 3 34 I/O I/O 2 32 I/O(1) I/O 4 33 I/O QFG48 I/O 3 31 I/O(1) I/O 5 32 I/O GND 4 30 I/O(3) I/O 6 31 Gnd VQ44 I/O 5 29 I/O I/O 7 Top View 30 I/O I/O 6 Top View 28 I/O I/O 8 29 Vcc VCCIO1 7 27 I/O I/O 9 28 I/O I/O 8 26 VCCIO2 I/O 10 27 I/O TDI 9 25 GND TMS 10 24 TDO I/O(2) 11 26 I/O TCK 11 23 I/O I/O(2) 1213141516171819202122232425 I/O 23456789012 O1O1O11CO1D1O1O1O2O2O2 I/O(2)I/OI/OGndI/OI/OVccio1I/OTDITMSTCKI/O I/I/I/VCI/GNI/I/I/I/I/ (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (1) - Global Output Enable (2) - Global Clock Figure 8: QFG48 Package (3) - Global Set/Reset Figure 6: VQ44 Package 0 1 2 3 4 5 6 7 8 9 1 K I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O TMS TCK O(2) O(2) OOOOOOO AUXO(1) J I/O(2) TDI I/I/I/I/I/I/I/I/I/VI/ H I/O I/O GND I/O VCCIO1 I/O I/O I/O I/O(2) 7 654321444342414039 I/O(1) G I/O I/O VCC I/O I/O 8 38 I/O(1) I/O 9 37 I/O(1) F I/O I/O CP56 GND I/O GND 10 36 I/O(3) Bottom View I/O 11 PC44 35 I/O E I/O I/O I/O I/O I/O 12 Top View 34 I/O VCCIO1 13 33 I/O D I/O(1) VAUX I/O I/O I/O 14 32 VCCIO2 TDI 15 31 Gnd C I/O(1) I/O I/O I/O VCCIO2 GND I/O I/O TMS 16 30 TDO TCK 17 29 I/O B I/O(3) I/O 89012345678 11222222222 A I/O I/O(1) I/O(1) I/O I/O TDO I/O I/O I/O I/O OOO CODOOOOO I/I/I/VCI/GNI/I/I/I/I/ (1) - Global Output Enable (1) - Global Output Enable (2) - Global Clock (2) - Global Clock (3) - Global Set/Reset (3) - Global Set/Reset Figure 9: CP56 Package Figure 7: PC44 Package (Obsolete package shown for legacy support only) 14 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification

R XC2C64A CoolRunner-II CPLD 2 2 ND(3)O CCIOOCCOCOOOO CCIOCCCNDDOCOCOOOO GI/VI/NNI/NI/I/I/I/VNNNGTNI/NI/I/I/I/ 0987654321098765432109876 0999999999988888888887777 I/O(1) 11 75 NC I/O(1) 2 74 I/O I/O(1) 3 73 NC I/O(1) 4 72 I/O VAUX 5 71 I/O I/O 6 70 I/O I/O 7 69 GND I/O 8 68 I/O I/O 9 67 I/O I/O 10 66 NC I/O 11 VQ100 65 NC I/O 12 Top View 64 I/O I/O 13 63 NC I/O 14 62 GND I/O 15 61 I/O I/O 16 60 I/O I/O 17 59 NC I/O 18 58 I/O I/O 19 57 Vcc NC 20 56 I/O GND 21 55 I/O I/O(2) 22 54 NC I/O(2) 23 53 I/O I/O 24 52 I/O NC 25 51 VCCIO1 6789012345678901234567890 2222333333333344444444445 VCC(2)I/OI/OI/OI/OGNDI/OI/OI/OI/OI/OI/OVCCIO1I/OI/OI/OI/OI/ONCTDINCTMSTCKI/OI/O (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Figure 12: VQ100 Package Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS311 (v2.3) November 19, 2008 www.xilinx.com 15 Product Specification

XC2C64A CoolRunner-II CPLD R Additional Information Additional information is available for the following (cid:129) Reliability data in the Device Reliability Report CoolRunner-II CPLD topics at (cid:129) Packaging thermal and electrical data in the Device www.xilinx.com/support/documentation/coolrunner-ii.htm: Package User Guide (cid:129) Device pinouts in the density specific data sheets Package drawings and dimensions are available at: (cid:129) Termination, power sequencing, voltage thresholds, www.xilinx.com/support/documentation/package_specifications.htm and slew rate data in the CPLD IO User Guide Revision History The following table shows the revision history for this document. Date Version Revision 5/15/04 1.0 Initial Xilinx release. 8/30/04 1.1 Pb-free documentation 10/01/04 1.2 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. 11/08/04 1.3 Product Release. No change to documentation. 11/29/04 1.4 Change to QFG package drawing (Figure 8). Pin 29 relabelled. 12/14/04 1.5 Changes to Figure 4, Typical I/O Output Curves; Changes to t and t , Internal OUT25 OUT33 Timing Parameters, page 8. 01/18/05 1.6 Changes to I , f , t , t , t , t , t , and t CCSB TOGGLE PSU1 PSU2 PHD CW SLEW25 SLEW33 03/07/05 1.7 Format change to specifications I and I , page 3. Improvement to pin-to-pin logic delay, IL IH page 1. Modifications to Table 1, IOSTANDARDs. 06/28/05 1.8 Move to Product Specification. Change to T , T , T , and T . IN25 OUT25 IN33 OUT33 01/30/06 1.9 Modified footnote 1 from AC Specifications Table to remove incorrect equation. 03/20/06 2.0 Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can also be used for general purpose I/O. 02/15/07 2.1 Change to V specification for 2.5V and 1.8V LVCMOS. Change T specification on -7 IH F speed grade from 2.0 to 3.0 ns. 03/08/07 2.2 Fixed typo in note for V for LVCMOS18; removed note for V for LVCMOS33. IL IL 11/19/08 2.3 Added note to Pin Description tables to indicate the PC44 packages are obsolete. Removed part numbers for devices in PC44 packages the Features section and from the ordering information. See Product Discontinuation Notice xcn07022.pdf. 16 www.xilinx.com DS311 (v2.3) November 19, 2008 Product Specification