0 R XC2C384 CoolRunner-II CPLD DS095 (v3.2) March 8, 2007 Product Specification 0 0 Features Description • Optimized for 1.8V systems The CoolRunner-II 384-macrocell device is designed for - As fast as 7.1 ns pin-to-pin delays both high performance and low power applications. This - As low as 14 μA quiescent current lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low • Industry’s best 0.18 micron CMOS CPLD power stand-by and dynamic operation, overall system reli- - Optimized architecture for effective logic synthesis ability is improved - Multi-voltage I/O operation — 1.5V to 3.3V • Available in multiple package options This device consists of twenty four Function Blocks - 144-pin TQFP with 118 user I/O inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs - 208-pin PQFP with 173 user I/O to each Function Block. The Function Blocks consist of a 40 - 256-ball FT (1.0mm) BGA with 212 user I/O by 56 P-term PLA and 16 macrocells which contain numer- - 324-ball FG (1.0mm) BGA with 240 user I/O ous configuration bits that allow for combinational or regis- - Pb-free available for all packages tered modes of operation. • Advanced system features Additionally, these registers can be globally reset or preset - Fastest in system programming and configured as a D or T flip-flop or as a D latch. There · 1.8V ISP using IEEE 1532 (JTAG) interface are also multiple clock signals, both global and local product - IEEE1149.1 JTAG Boundary Scan Test term types, configured on a per macrocell basis. Output pin - Optional Schmitt-trigger input (per pin) configurations include slew rate limit, bus hold, pull-up, - Unsurpassed low power management open drain and programmable grounds. A Schmitt-trigger · DataGATE enable (DGE) signal control input is available on a per input pin basis. In addition to stor- - Four separate I/O banks ing macrocell output states, the macrocell registers may be - RealDigital 100% CMOS product term generation configured as direct input registers to store signals directly - Flexible clocking modes from input pins. · Optional DualEDGE triggered registers · Clock divider (divide by 2,4,6,8,10,12,14,16) Clocking is available on a global or Function Block basis. · CoolCLOCK Three global clocks are available for all Function Blocks as - Global signal options with macrocell control a synchronous clock source. Macrocell registers can be · Multiple global clocks with phase selection per individually configured to power up to the zero or one state. macrocell A global set/reset control line is also available to asynchro- · Multiple global output enables nously set or reset selected registers during operation. · Global set/reset Additional local clock, synchronous clock-enable, asynchro- - Advanced design security nous set/reset and output enable signals can be formed - PLA architecture using product terms on a per-macrocell or per-Function · Superior pinout retention Block basis. · 100% product term routability across function A DualEDGE flip-flop feature is also available on a per mac- block rocell basis. This feature allows high performance synchro- - Open-drain output option for Wired-OR and LED nous operation based on lower frequency clocking to help drive reduce the total power consumption of the device. - Optional bus-hold, 3-state or weak pullup on selected I/O pins Circuitry has also been included to divide one externally - Optional configurable grounds on unused I/Os supplied global clock (GCK2) by eight different selections. - Mixed I/O voltages compatible with 1.5V, 1.8V, This yields divide by even and odd clock frequencies. 2.5V, and 3.3V logic levels The use of the clock divide (division by 2) and DualEDGE · SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility flip-flop gives the resultant CoolCLOCK feature. - Hot pluggable DataGATE is a method to selectively disable inputs of the Refer to the CoolRunner™-II family data sheet for architec- CPLD that are not of interest during certain points in time. ture description. © 2002--2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS095 (v3.2) March 8, 2007 www.xilinx.com 1 Product Specification

XC2C384 CoolRunner-II CPLD R By mapping a signal to the DataGATE function, lower power for I/O standard voltages. The LVTTL I/O standard is a gen- can be achieved due to reduction in signal switching. eral purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The Another feature that eases voltage translation is I/O bank- LVCMOSstandard is used in 3.3V, 2.5V, 1.8V applications. ing. Four I/O banks are available on the CoolRunner-II384 Both HSTL and SSTL I/O standards make use of a V pin macrocell device that permit easy interfacing to 3.3V, 2.5V, REF for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V 1.8V, and 1.5V devices. I/O compatible with the use of Schmitt-trigger inputs. The CoolRunner-II 384 macrocell CPLD is I/O compatible with various I/O standards (see Table1). This device is also Table 1: I/O Standards for XC2C384(1) 1.5V I/O compatible with the use of Schmitt-trigger inputs. Board IOSTANDARD Output Input Input Termination RealDigital Design Technology Attribute V V V Voltage V CCIO CCIO REF TT Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron LVTTL 3.3 3.3 N/A N/A process technology which is derived from leading edge LVCMOS33 3.3 3.3 N/A N/A FPGA product development. CoolRunner-II CPLDs employ RealDigital a design technique that makes use of CMOS LVCMOS25 2.5 2.5 N/A N/A technology in both the fabrication and design methodology. LVCMOS18 1.8 1.8 N/A N/A RealDigital design technology employs a cascade of CMOS LVCMOS15(2) 1.5 1.5 N/A N/A gates to implement sum of products instead of traditional HSTL_1 1.5 1.5 0.75 0.75 sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance and SSTL2_1 2.5 2.5 1.25 1.25 low power operation. SSTL3_1 3.3 3.3 1.5 1.5 (1)For information on assigning Vref pins, see XAPP399. Supported I/O Standards (2) LVCMOS15 requires Schmitt-trigger inputs. The CoolRunner-II 384 macrocell features LVCMOS, LVTTL, SSTL and HSTL I/O implementations. See Table1 200 150 A) m (C100 C I 50 0 0 25 50 75 100 125 150 175 200 Frequency (MHz) DS095_01_030705 Figure 1: I vs Frequency CC Table 2: I vs Frequency (LVCMOS 1.8V T = 25°C)(1) CC A Frequency (MHz) 0 25 50 75 100 125 150 175 200 Typical I (mA) 0.023 17.5 35.03 52.53 70.03 87.53 105.03 122.35 140.03 CC Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block). 2 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Absolute Maximum Ratings (1) Symbol Description Value Units V Supply voltage relative to ground –0.5 to 2.0 V CC V Supply voltage for output drivers –0.5 to 4.0 V CCIO V (2) JTAG input voltage limits –0.5 to 4.0 V JTAG V JTAG input supply voltage –0.5 to 4.0 V CCAUX V (1) Input voltage relative to ground –0.5 to 4.0 V IN V (1) Voltage applied to 3-state output –0.5 to 4.0 V TS T (3) Storage Temperature (ambient) –65 to +150 °C STG T Junction Temperature +150 °C J Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427. Recommended Operating Conditions Symbol Parameter Min Max Units V Supply voltage for internal logic Commercial T = 0°C to +70°C 1.7 1.9 V CC A and input buffers Industrial T = –40°C to +85°C 1.7 1.9 V A V Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V CCIO Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V V Supply voltage for JTAG programming 1.7 3.6 V CCAUX DC Electrical Characteristics (Over Recommended Operating Conditions) Symbol Parameter Test Conditions Typical Max. Units I Standby current Commercial V = 1.9V, V = 3.6V 44 200 μA CCSB CC CCIO I Standby current Industrial V = 1.9V, V = 3.6V 79 350 μA CCSB CC CCIO I (1) Dynamic current f = 1 MHz 1.5 mA CC f = 50 MHz 45 mA C JTAG input capacitance f = 1 MHz - 10 pF JTAG C Global clock input capacitance f = 1 MHz - 12 pF CLK C I/O capacitance f = 1 MHz - 10 pF IO I (2) Input leakage current V = 0V or V to 3.9V - +/–1 μA IL IN CCIO I (2) I/O High-Z leakage V = 0V or V to 3.9V - +/–1 μA IH IN CCIO Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block). 2. See Quality and Reliability section of the CoolRunner-II family data sheet. DS095 (v3.2) March 8, 2007 www.xilinx.com 3 Product Specification

XC2C384 CoolRunner-II CPLD R LVCMOS and LVTTL 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage 3.0 3.6 V CCIO V High level input voltage 2 3.9 V IH V Low level input voltage –0.3 0.8 V IL V High level output voltage I = –8 mA, V = 3V V – 0.4V - V OH OH CCIO CCIO I = –0.1 mA, V = 3V V – 0.2V - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 3V - 0.4 V OL OL CCIO I = 0.1 mA, V = 3V - 0.2 V OL CCIO LVCMOS 2.5V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage 2.3 2.7 V CCIO V High level input voltage 1.7 V + 0.3(1) V IH CCIO V Low level input voltage –0.3 0.7 V IL V High level output voltage I = –8 mA, V = 2.3V V – 0.4V - V OH OH CCIO CCIO I = –0.1 mA, V = 2.3V V – 0.2V - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 2.3V - 0.4 V OL OL CCIO I = 0.1 mA, V = 2.3V - 0.2 V OL CCIO (1) The V Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without IH physical damage. LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage 1.7 1.9 V CCIO V High level input voltage 0.65 x V V + 0.3(1) V IH CCIO CCIO V Low level input voltage –0.3 0.35 x V V IL CCIO V High level output voltage I = –8 mA, V = 1.7V V – 0.45 - V OH OH CCIO CCIO I = –0.1 mA, V = 1.7V V – 0.2 - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 1.7V - 0.45 V OL OL CCIO I = 0.1 mA, V = 1.7V - 0.2 V OL CCIO (1) The V Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without IH physical damage. LVCMOS 1.5V DC Voltage Specifications(1) Symbol Parameter Test Conditions Min. Max. Units V Input source voltage 1.4 1.6 V CCIO V Input hysteresis threshold voltage 0.5 x V 0.8 x V V T+ CCIO CCIO V 0.2 x V 0.5 x V V T- CCIO CCIO V High level output voltage I = –8 mA, V = 1.4V V – 0.45 - V OH OH CCIO CCIO I = –0.1 mA, V = 1.4V V – 0.2 - V OH CCIO CCIO 4 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Symbol Parameter Test Conditions Min. Max. Units V Low level output voltage I = 8 mA, V = 1.4V - 0.4 V OL OL CCIO I = 0.1 mA, V = 1.4V - 0.2 V OL CCIO Notes: 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage 1.4 3.9 V CCIO V Input hysteresis threshold voltage 0.5 x V 0.8 x V V T+ CCIO CCIO V 0.2 x V 0.5 x V V T- CCIO CCIO SSTL2-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V Input source voltage - 2.3 2.5 2.7 V CCIO V Input reference voltage - 1.15 1.25 1.35 V REF(1) V Termination voltage - V – 0.04 1.25 V + 0.04 V TT(2) REF REF V High level input voltage - V + 0.18 - 3.9 V IH REF V Low level input voltage - –0.3 - V – 0.18 V IL REF V High level output voltage I = –8 mA, V = 2.3V V – 0.62 - - V OH OH CCIO CCIO V Low level output voltage I = 8 mA, V = 2.3V - - 0.54 V OL OL CCIO Notes: 1. V should track the variations in V , also peak to peak AC noise on V may not exceed ±2% V REF CCIO REF REF. 2. V of transmitting device must track V of receiving devices. TT REF SSTL3-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V Input source voltage - 3.0 3.3 3.6 V CCIO V Input reference voltage - 1.3 1.5 1.7 V REF(1) V Termination voltage - V – 0.05 1.5 V + 0.05 V TT(2) REF REF V High level input voltage - V + 0.2 - V + 0.3 V IH REF CCIO V Low level input voltage - –0.3 - V – 0.2 V IL REF V High level output voltage I = –8 mA, V = 3V V – 1.1 - - V OH OH CCIO CCIO V Low level output voltage I = 8 mA, V = 3V - - 0.7 V OL OL CCIO Notes: 1. V should track the variations in V , also peak to peak AC noise on V may not exceed ±2% V REF CCIO REF REF. 2. V of transmitting device must track V of receiving devices. TT REF HSTL1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V Input source voltage 1.4 1.5 1.6 V CCIO V Input reference voltage 0.68 0.75 0.90 V REF(1) V Termination voltage - V * 0.5 - V TT(2) CCIO V High level input voltage V + 0.1 - 1.9 V IH REF DS095 (v3.2) March 8, 2007 www.xilinx.com 5 Product Specification

XC2C384 CoolRunner-II CPLD R Symbol Parameter Test Conditions Min. Typ Max. Units V Low level input voltage –0.3 - V – 0.1 V IL REF V High level output voltage I = –8 mA, V = 1.4V V – 0.4 - - V OH OH CCIO CCIO V Low level output voltage I = 8 mA, V = 1.4V - - 0.4 V OL OL CCIO 6 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD AC Electrical Characteristics Over Recommended Operating Conditions -7 -10 Symbol Parameter Min. Max. Min. Max. Units T Propagation delay single p-term - 7.1 - 9.2 ns PD1 T Propagation delay OR array - 7.5 - 10.0 ns PD2 T Direct input register set-up time 4.1 - 4.2 - ns SUD T Setup time fast (single p-term) 3.2 - 3.3 - ns SU1 T Setup time (OR array) 3.6 - 4.1 - ns SU2 T Direct input register hold time 0.0 - 0.0 - ns HD T Hold time (OR array or p-term) 0.0 - 0.0 - ns H T Clock to output - 5.3 - 7.9 ns CO F (1) Internal toggle rate - 350 - 166 MHz TOGGLE F (2) Maximum system frequency - 217 - 125 MHz SYSTEM1 F (2) Maximum system frequency - 200 - 114 MHz SYSTEM2 F (3) Maximum external frequency - 118 - 89 MHz EXT1 F (3) Maximum external frequency - 112 - 83 MHz EXT2 T Direct input register p-term clock setup time 2.3 - 2.5 - ns PSUD T P-term clock setup time (single p-term) 1.4 - 1.9 - ns PSU1 T P-term clock setup time (OR array) 1.8 - 2.7 - ns PSU2 T Direct input register p-term clock hold time 0.9 - 0.4 - ns PHD T P-term clock hold 1.8 - 1.3 - ns PH T P-term clock to output - 7.1 - 9.3 ns PCO T /T Global OE to output enable/disable - 6.0 - 9.2 ns OE OD T /T P-term OE to output enable/disable - 7.0 - 10.2 ns POE POD T /T Macrocell driven OE to output enable/disable - 8.0 - 12.5 ns MOE MOD T P-term set/reset to output valid - 7.5 - 11.6 ns PAO T Global set/reset to output valid - 6.0 - 11.5 ns AO T Register clock enable setup time 3.3 - 3.4 - ns SUEC T Register clock enable hold time 0.0 - 0.0 - ns HEC T Global clock pulse width High or Low 1.4 - 3.0 - ns CW T P-term pulse width High or Low 7.5 - 10.0 - ns PCW T Asynchronous preset/reset pulse width (High or Low) 7.5 - 10.0 - ns APRPW T Set-up before DataGATE latch assertion 0.0 0.0 ns DGSU T Hold to DataGATE latch assertion 4.0 6.0 ns DGH T DataGATE recovery to new data 8.5 11.0 ns DGR T DataGATE low pulse width 3.0 5.0 ns DGW T CDRST setup time before falling edge GCLK2 1.7 2.5 ns CDRSU T CDRST hold time before falling edge GCLK2 0.0 0.0 ns CDRH T Configuration time 200 200 μs CONFIG Notes: 1. F is the maximum frequency of a T flip-flop can reliably toggle (see CoolRunner-II family data sheet). TOGGLE 2. F (1/T ) is the internal operating frequency for a device with 16-bit Resetable binary counter through one p-term per SYSTEM1 CYCLE macrocell while F is through the OR array (one counter per function block) SYSTEM2 3. F (1/T +T ) is the maximum external frequency using one p-term while F is through the OR array EXT1 SU1 CO EXT2 4. Typical configuration current during T is 25 mA. CONFIG DS095 (v3.2) March 8, 2007 www.xilinx.com 7 Product Specification

XC2C384 CoolRunner-II CPLD R Internal Timing Parameters -7 -10 Symbol Parameter(1) Min. Max. Min. Max. Units Buffer Delays T Input buffer delay - 3.1 - 3.8 ns IN T Direct data register input delay - 4.5 - 5.5 ns DIN T Global Clock buffer delay - 2.1 - 3.3 ns GCK T Global set/reset buffer delay - 2.4 - 4.6 ns GSR T Global 3-state buffer delay - 2.9 - 3.7 ns GTS T Output buffer delay - 3.0 - 3.9 ns OUT T Output buffer enable/disable delay - 3.1 - 5.5 ns EN P-term Delays T Control term delay - 0.8 - 0.9 ns CT T Single P-term delay adder - 0.5 - 0.8 ns LOGI1 T Multiple P-term delay adder - 0.4 - 0.8 ns LOGI2 Macrocell Delay T Input to output valid - 0.5 - 0.7 ns PDI T Setup before clock 1.7 - 2.0 - ns SUI T Hold after clock 0.0 - 0.0 - ns HI T Enable clock setup time 1.5 - 2.0 - ns ECSU T Enable clock hold time 0.0 - 0.0 - ns ECHO T Clock to output valid - 0.2 - 0.7 ns COI T Set/reset to output valid - 0.6 - 3.0 ns AOI T Clock doubler delay - 0 - 0 ns CDBL Feedback Delays T Feedback delay - 2.2 - 4.5 ns F T Macrocell to global OE delay - 2.6 - 3.0 ns OEM I/O Standard Time Adder Delays 1.5V CMOS T Hysteresis input adder - 3.0 - 4.0 ns HYS15 T Output adder - 0.8 - 1.0 ns OUT15 T Output slew rate adder - 4.0 - 4.0 ns SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Hysteresis input adder - 2.0 - 4.0 ns HYS18 T Output adder - 0.0 - 0.0 ns OUT18 T Output slew rate adder - 2.0 - 4.0 ns SLEW I/O Standard Time Adder Delays 2.5V CMOS T Standard input adder - 0.6 - 1.0 ns IN25 T Hysteresis input adder - 1.5 - 3.0 ns HYS25 T Output adder - 0.8 - 3.0 ns OUT25 T Output slew rate adder - 3.0 - 4.0 ns SLEW25 8 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Internal Timing Parameters (Continued) -7 -10 Symbol Parameter(1) Min. Max. Min. Max. Units I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder - 0.5 - 2.0 ns IN33 T Hysteresis input adder - 1.2 - 3.0 ns HYS33 T Output adder - 1.2 - 3.0 ns OUT33 T Output slew rate adder - 3.0 - 4.0 ns SLEW33 I/O Standard Time Adder Delays HSTL, SSTL SSTL2-1 Input adder to T , T , T , T , - 0.8 - 2.5 ns IN DIN GCK GSR T GTS Output adder to T - -0.5 - 0.0 ns OUT SSTL3-1 Input adder to T , T , T , T , - 0.8 - 2.5 ns IN DIN GCK GSR T GTS Output adder to T - -0.50 - 0.00 ns OUT HSTL-1 Input adder to T , T , T , T , - 1.0 - 2.5 ns IN DIN GCK GSR T GTS Output adder to T - 0.0 - 0.0 ns OUT Notes: 1. 1.5 ns input pin signal rise/fall. Switching Characteristics Switching Test Conditions VCC VCC = VCCIO = 1.8V, 25oC R1 6.0 Device Test Point Under Test 5.5 R2 CL s) n (2 5.0 D P T Output Type R1 R2 CL 4.5 LVTTL33 268Ω 235Ω 35 pF LVCMOS33 275Ω 275Ω 35 pF 4.0 LVCMOS25 188Ω 188Ω 35 pF 1 2 4 8 16 LVCMOS18 112.5Ω 112.5Ω 35 pF Number of Outputs Switching LVCMOS15 150Ω 150Ω 35 pF Notes: DS095_02_053103 1. CL includes test fixtures and probe capacitance. Figure 2: Derating Curve for T 2. 1.5 nsec maximum rise/fall times on inputs. PD DS092_03_092302 Figure 3: AC Load Circuit DS095 (v3.2) March 8, 2007 www.xilinx.com 9 Product Specification

XC2C384 CoolRunner-II CPLD R Typical I/V Output Curves The I/V curve illustrates the nominal amount of current that an I/O can source/sink at different voltage levels. 3.3V 60 50 A) m nt 40 2.5V e urr 1.8V C ut Iol p 30 ut O O ( I 20 1.5V 10 0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5 VO (Output Volts) XC384_IV_050703 Figure 4: Typical I/V Curves for XC2C384 1P1 in Descriptions Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell TQ144 PQ208 FT256 FG324 Bank Block cell TQ144 PQ208 FT256 FG324 Bank 1 1 - 2 B3 C3 2 2(GTS2) 1 2 3 D3 D3 2 1 2 - 208 B4 A1 2 2 2 - 4 C3 B2 2 1(GSR) 3 143 206 C4 A2 2 2(GTS3) 3 3 5 E3 B1 2 1 4 142 205 A2 B3 2 2 4 4 6 B2 C2 2 1 5 - - - C4 2 2(GTS0) 5 5 7 D4 C1 2 1 6 - - - - - 2 6 - - - - - 1 7 - - - - - 2 7 - - - - - 1 8 - - - - - 2 8 - - - - - 1 9 - - - - - 2 9 - - - - - 1 10 - - - - - 2 10 - - - - - 1 11 - - - - - 2 11 - - - - - 1 12 140 203 C5 B4 2 2 12 - - A1 D2 2 1 13 139 202 A3 C5 2 2 13 - 8 D2 F4 2 1 14 - 201 - B5 2 2 14 - - C2 E2 2 1 15 - 200 E7 A3 2 2(GTS1) 15 6 9 E5 E1 2 1 16 - 199 - A4 2 2 16 7 10 B1 F2 2 10 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell TQ144 PQ208 FT256 FG324 Bank Block cell TQ144 PQ208 FT256 FG324 Bank 3 1 - 198 A4 D6 2 5 1 - - D7 C8 2 3 2 - 197 - A5 2 5 2 133 - B7 B8 2 3 3 138 196 C6 C6 2 5 3 132 - E9 A8 2 3 4 137 195 B5 B6 2 5 4 - 189 A7 D9 2 3 5 136 194 D6 A6 2 5 5 - 188 D8 C9 2 3 6 - - - - - 5 6 - - - - - 3 7 - - - - - 5 7 - - - - - 3 8 - - - - - 5 8 - - - - - 3 9 - - - - - 5 9 - - - - - 3 10 - - - - - 5 10 - - - - - 3 11 - - - - - 5 11 - - - - - 3 12 135 193 A5 D7 2 5 12 - 187 B8 B9 2 3 13 - 192 E8 C7 2 5 13 131 186 C8 A9 2 3 14 - - B6 B7 2 5 14 - 185 A8 D10 2 3 15 - 191 C7 A7 2 5 15 130 184 E11 C10 2 3 16 134 - A6 D8 2 5 16 129 183 E10 B10 2 4 1 9 12 E4 G4 2 6 1 - 22 G2 J1 2 4 2 10 - C1 G3 2 6 2 13 - F5 K3 2 4 3 11 14 E2 G2 2 6 3 14 23 F1 K2 2 4 4 12 15 F2 G1 2 6 4 15 - G5 K1 2 4 5 - 16 E6 H4 2 6 5 - - H2 L1 2 4 6 - - - - - 6 6 - - - - - 4 7 - - - - - 6 7 - - - - - 4 8 - - - - - 6 8 - - - - - 4 9 - - - - - 6 9 - - - - - 4 10 - - - - - 6 10 - - - - - 4 11 - - - - - 6 11 - - - - - 4 12 - 17 F3 H3 2 6 12 - - H4 L3 2 4 13 - 18 D1 H2 2 6 13 16 - G1 L2 2 4 14 - 19 G4 H1 2 6 14 17 - H3 M1 2 4 15 - 20 E1 J3 2 6 15 - - H1 M2 2 4 16 - 21 G3 J2 2 6 16 18 25 H5 M3 2 DS095 (v3.2) March 8, 2007 www.xilinx.com 11 Product Specification

XC2C384 CoolRunner-II CPLD R Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell TQ144 PQ208 FT256 FG324 Bank Block cell TQ144 PQ208 FT256 FG324 Bank 7(CDRST) 1 35 51 P2 AB2 1 9 1 - 41 N1 V2 1 7 2 - 50 N3 AA2 1 9 2 28 40 L4 V1 1 7 3 - 49 R1 AA1 1 9 3 - 39 M1 U3 1 7 4 34 48 N4 W4 1 9 4 - 38 L5 U2 1 7 5 33 47 N2 Y2 1 9 5 - 37 K4 U1 1 7 6 - - - - - 9 6 - - - - - 7 7 - - - - - 9 7 - - - - - 7 8 - - - - - 9 8 - - - - - 7 9 - - - - - 9 9 - - - - - 7 10 - - - - - 9 10 - - - - - 7 11 - - - - - 9 11 -- - - - - 7(GCK1) 12 32 46 M3 Y1 1 9 12 - 36 L2 T4 1 7 13 - - P1 W2 1 9 13 - 35 K3 T3 1 7 14 31 45 M4 W1 1 9 14 - 34 L1 T2 1 7(GCK0) 15 30 44 M2 V3 1 9 15 26 32 - T1 1 7 16 - 43 L3 U4 1 9 16 25 - - R4 1 8 1 - 54 P4 Y4 1 10 1 44 62 - AB6 1 8(GCK2) 2 38 55 P5 AB3 1 10 2 45 63 R5 W7 1 8 3 - 56 R2 AA4 1 10 3 - - - Y7 1 8 4 - 57 T1 Y5 1 10 4 46 64 R6 AA7 1 8(DGE) 5 39 58 T2 AA5 1 10 5 - 65 N6 AB7 1 8 6 - - - - - 10 6 - - - - - 8 7 - - - - - 10 7 - - - - - 8 8 - - - - - 10 8 - - - - - 8 9 - - - - - 10 9 - - - - - 8 10 - - - - - 10 10 - - - - - 8 11 - - - - - 10 11 - - - - - 8 12 - - - AB4 1 10 12 - 66 R3 W8 1 8 13 40 60 N5 W6 1 10 13 - 67 M6 Y8 1 8 14 41 - - AB5 1 10 14 48 69 - AA8 1 8 15 42 61 R4 Y6 1 10 15 49 70 T3 AB8 1 8 16 43 - M5 AA6 1 10 16 50 71 P6 Y9 1 12 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell TQ144 PQ208 FT256 FG324 Bank Block cell TQ144 PQ208 FT256 FG324 Bank 11 1 24 31 K5 R3 1 13 1 - - B16 C21 4 11 2 23 - K2 R2 1 13 2 - - G11 C20 4 11 3 22 30 J4 R1 1 13 3 112 160 C14 B22 4 11 4 21 29 K1 P4 1 13 4 113 161 B15 B21 4 11 5 20 28 J3 P3 1 13 5 - - A16 A22 4 11 6 - - - - - 13 6 - - - - - 11 7 - - - - - 13 7 - - - - - 11 8 - - - - - 13 8 - - - - - 11 9 - - - - - 13 9 - - - - - 11 10 - - - - - 13 10 - - - - - 11 11 - - - - - 13 11 - - - - - 11 12 19 27 J2 P2 1 13 12 114 162 B13 A21 4 11 13 - - J5 P1 1 13 13 115 163 B14 B20 4 11 14 - - J1 N3 1 13 14 - - C13 C19 4 11 15 - - - N2 1 13 15 - - A15 B19 4 11 16 - - - N1 1 13 16 - 164 C12 C18 4 12 1 51 72 T4 AA9 1 14 1 111 159 D14 D19 4 12 2 52 73 P7 AB9 1 14 2 110 158 C15 D20 4 12 3 53 74 T5 W10 1 14 3 107 155 G12 C22 4 12 4 - 75 N7 Y10 1 14 4 106 154 D15 D21 4 12 5 54 76 R7 AA10 1 14 5 105 153 E14 D22 4 12 6 - - - - - 14 6 - - - - - 12 7 - - - - - 14 7 - - - - - 12 8 - - - - - 14 8 - - - - - 12 9 - - - - - 14 9 - - - - - 12 10 - - - - - 14 10 - - - - - 12 11 - - - - - 14 11 - - - - - 12 12 - 77 M7 AB10 1 14 12 - - C16 E20 4 12 13 - - - AB11 1 14 13 104 152 F14 F19 4 12 14 - - - W11 1 14 14 - 151 D16 E21 4 12 15 - - - AA11 1 14 15 - - F13 E22 4 12 16 - 78 T6 Y11 1 14 16 - 150 E15 F20 4 DS095 (v3.2) March 8, 2007 www.xilinx.com 13 Product Specification

XC2C384 CoolRunner-II CPLD R Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell TQ144 PQ208 FT256 FG324 Bank Block cell TQ144 PQ208 FT256 FG324 Bank 15 1 - - B12 B18 4 17 1 - 173 D10 C15 4 15 2 116 165 D13 A19 4 17 2 121 174 B10 B15 4 15 3 - 166 A14 D17 4 17 3 - 175 E12 D14 4 15 4 - - E13 A18 4 17 4 - - - B14 4 15 5 117 167 A13 C17 4 17 5 - - F12 C13 4 15 6 - - - - - 17 6 - - - - - 15 7 - - - - - 17 7 - - - - - 15 8 - - - - - 17 8 - - - - - 15 9 - - - - - 17 9 - - - - - 15 10 - - - - - 17 10 - - - - - 15 11 - - - - - 17 11 - - - - - 15 12 - 168 C11 B17 4 17 12 124 178 B9 A13 4 15 13 118 169 A12 D16 4 17 13 125 179 C9 D12 4 15 14 - - B11 C16 4 17 14 126 180 C10 C12 4 15 15 119 170 D11 B16 4 17 15 - - A9 B11 4 15 16 120 171 A11 D15 4 17 16 128 182 D9 A10 4 16 1 103 149 G13 F21 4 18 1 - - G15 J20 4 16 2 - 148 F15 F22 4 18 2 - 142 - J21 4 16 3 102 147 G14 G19 4 18 3 98 140 - J22 4 16 4 - 146 E16 G20 4 18 4 97 139 H13 K19 4 16 5 - - H12 G21 4 18 5 96 138 G16 K20 4 16 6 - - - - - 18 6 - - - - - 16 7 - - - - - 18 7 - - - - - 16 8 - - - - - 18 8 - - - - - 16 9 - - - - - 18 9 - - - - - 16 10 - - - - - 18 10 - - - - - 16 11 - - - - - 18 11 - - - - - 16 12 - 145 F16 G22 4 18 12 95 137 H14 K21 4 16 13 - - H16 H19 4 18 13 94 136 H15 K22 4 16 14 101 144 - H21 4 18 14 - 135 J12 L19 4 16 15 - - - H22 4 18 15 - 134 K12 L20 4 16 16 100 143 - J19 4 18 16 - - J16 L21 4 14 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell TQ144 PQ208 FT256 FG324 Bank Block cell TQ144 PQ208 FT256 FG324 Bank 19 1 - 103 P13 AA22 3 21 1 80 114 P16 V22 3 19 2 - - P14 Y20 3 21 2 - 115 N16 U20 3 19 3 74 106 P15 Y21 3 21 3 81 116 L14 U21 3 19 4 75 107 R15 W20 3 21 4 - 117 M14 U22 3 19 5 76 108 T16 W21 3 21 5 - 118 L15 T19 3 19 6 - - - - - 21 6 - - - - - 19 7 - - - - - 21 7 - - - - - 19 8 - - - - - 21 8 - - - - - 19 9 - - - - - 21 9 - - - - - 19 10 - - - - - 21 10 - - - - - 19 11 - - - - - 21 11 - - - - - 19 12 77 109 N14 Y22 3 21 12 82 119 L13 T20 3 19 13 78 110 R16 W22 3 21 13 - 120 M12 T21 3 19 14 79 111 N15 V20 3 21 14 - 121 M16 T22 3 19 15 - 112 M15 V21 3 21 15 83 122 K14 R21 3 19 16 - 113 M13 U19 3 21 16 - 123 - R22 3 20 1 71 102 R13 AB22 3 22 1 - - N10 AA17 3 20 2 70 101 N13 AA21 3 22 2 61 91 T12 AB17 3 20 3 69 100 R14 AB21 3 22 3 - 90 P10 Y16 3 20 4 68 99 T15 W19 3 22 4 - 89 T11 AA16 3 20 5 66 97 R12 AA20 3 22 5 - - R10 AB16 3 20 6 - - - - - 22 6 - - - - - 20 7 - - - - - 22 7 - - - - - 20 8 - - - - - 22 8 - - - - - 20 9 - - - - - 22 9 - - - - - 20 10 - - - - - 22 10 - - - - - 20 11 - - - - - 22 11 - - - - - 20 12 - - T14 Y18 3 22 12 60 88 M10 W15 3 20 13 64 95 N11 AA19 3 22 13 - 87 T10 Y15 3 20 14 - - P11 Y17 3 22 14 59 86 M9 AA15 3 20 15 - - M11 AA18 3 22 15 - 85 R9 AB15 3 20 16 - - T13 AB18 3 22 16 - - P9 W14 3 DS095 (v3.2) March 8, 2007 www.xilinx.com 15 Product Specification

XC2C384 CoolRunner-II CPLD R Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell TQ144 PQ208 FT256 FG324 Bank Block cell TQ144 PQ208 FT256 FG324 Bank 23 1 - - L16 P20 3 24 1 - - N9 Y14 3 23 2 - 125 K15 P21 3 24 2 58 84 T9 AA14 3 23 3 85 126 L12 N19 3 24 3 - - - AB14 3 23 4 86 127 - N21 3 24 4 - 83 - Y13 3 23 5 87 - K16 N22 3 24 5 - 82 M8 AA13 3 23 6 - - - - - 24 6 - - - - - 23 7 - - - - - 24 7 - - - - - 23 8 - - - - - 24 8 - - - - - 23 9 - - - - - 24 9 - - - - - 23 10 - - - - - 24 10 - - - - - 23 11 - - - - - 24 11 - - - - - 23 12 88 128 J14 M22 3 24 12 57 - T8 AB13 3 23 13 91 - J15 M19 3 24 13 - - P8 W12 3 23 14 92 131 J13 M20 3 24 14 56 80 R8 Y12 3 23 15 - - - M21 3 24 15 - - T7 AA12 3 23 16 - - - L22 3 24 16 - - N8 AB12 3 Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable. 2. GCK, GSR, and GTS pins can also be used for general purpose I/O. XC2C384 JTAG, Power/Ground, No Connect Pins and Total User I/O Pin Type TQ144 PQ208 FT256 FG324 TCK 67 98 P12 Y19 TDI 63 94 R11 AB19 TDO 122 176 A10 C14 TMS 65 96 N12 AB20 V (JTAG supply 8 11 F4 F1 CCAUX voltage) Power internal (V ) 1, 37, 84 1, 53, 124 P3, K13, D12, D5 AA3, N20, A20, D4, E3 CC Power Bank 1 I/O (V ) 27, 55 33, 59, 79 J6, K6, L7, L8 M9, N9, P10, P11 CCIO1 Power Bank 2 I/O (V ) 141 26, 204 F7, F8, G6, H6 J10, J11, K9, L9 CCIO2 Power Bank 3 I/O (V ) 73, 93 92, 105, 132 J11, K11, L10, L9 M14, N14, P12, P13 CCIO3 Power Bank 4 I/O (V ) 109, 127 133, 157, 172, F10, F9, H11 J12, J13, K14, L14 CCIO4 181 16 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD XC2C384 JTAG, Power/Ground, No Connect Pins and Total User I/O (Continued) Pin Type TQ144 PQ208 FT256 FG324 Ground 29, 36, 47, 13, 24, 42, 52, F11, F6, G10, G7, G8, D5, D18, E4, E19, J9, J14, 62, 72, 89, 68, 81, 93, 104, G9, H10, H7, H8, H9, K10, K11, K12, K13, L10, L11, 90, 99, 108, 129, 130, 141, J10, J7, J8, J9, K10, L12, L13, M10, M11, M12, 123, 144 156, 177, 190, K7, K8, K9, L11, L6 M13, N10, N11, N12, N13, P9, 207 P14, V4, V19, W5, W18 No connects - - A11,A12,A14,A15,A16,A17,B 12,B13,C11,D1,D11,D13,F3,H 20,J4,K4,L4,M4,N4,P19,P22, R19,R20,W3,W9,W13,W16,W 17,Y3,AB1 Total user I/O (includes dual 118 173 212 240 function pins) DS095 (v3.2) March 8, 2007 www.xilinx.com 17 Product Specification

XC2C384 CoolRunner-II CPLD R Ordering Information Comm. Pin/Ball θ θ Package Body (C) JA JC Part Number Spacing (C/Watt) (C/Watt) Package Type Dimensions I/O Ind. (I)(1) XC2C384-7TQ144C 0.5mm 34.1 6.5 Thin Quad Flat Pack 20mm x 20mm 118 C XC2C384-10TQ144C 0.5mm 34.1 6.5 Thin Quad Flat Pack 20mm x 20mm 118 C XC2C384-7PQ208C 0.5mm 36.1 8.4 Plastic Quad Flat Pack 28mm x 28mm 173 C XC2C384-10PQ208C 0.5mm 36.1 8.4 Plastic Quad Flat Pack 28mm x 28mm 173 C XC2C384-7FT256C 1.0mm 33.5 5.5 Fine Pitch Thin BGA 17mm x 17mm 212 C XC2C384-10FT256C 1.0mm 33.5 5.5 Fine Pitch Thin BGA 17mm x 17mm 212 C XC2C384-7FG324C 1.0mm 39.3 5.3 Fine Pitch BGA 23mm x 23mm 240 C XC2C384-10FG324C 1.0mm 39.3 5.3 Fine Pitch BGA 23mm x 23mm 240 C XC2C384-7TQG144C 0.5mm 34.1 6.5 Thin Quad Flat Pack; 20mm x 20mm 118 C Pb-free XC2C384-10TQG144C 0.5mm 34.1 6.5 Thin Quad Flat Pack; 20mm x 20mm 118 C Pb-free XC2C384-7PQG208C 0.5mm 36.1 8.4 Plastic Quad Flat Pack; 28mm x 28mm 173 C Pb-free XC2C384-10PQG208C 0.5mm 36.1 8.4 Plastic Quad Flat Pack; 28mm x 28mm 173 C Pb-free XC2C384-7FTG256C 1.0mm 33.5 5.5 Fine Pitch Thin BGA; 17mm x 17mm 212 C Pb-free XC2C384-10FTG256C 1.0mm 33.5 5.5 Fine Pitch Thin BGA; 17mm x 17mm 212 C Pb-free XC2C384-7FGG324C 1.0mm 39.3 5.3 Fine Pitch BGA; Pb-free 23mm x 23mm 240 C XC2C384-10FGG324C 1.0mm 39.3 5.3 Fine Pitch BGA; Pb-free 23mm x 23mm 240 C XC2C384-10TQ144I 0.5mm 34.1 6.5 Plastic Quad Flat Pack 20mm x 20mm 118 I XC2C384-10PQ208I 0.5mm 36.1 8.4 Plastic Quad Flat Pack 28mm x 28mm 173 I XC2C384-10FT256I 1.0mm 33.5 5.5 Fine Pitch Thin BGA 17mm x 17mm 212 I XC2C384-10FG324I 1.0mm 39.3 5.3 Fine Pitch BGA 23mm x 23mm 240 I XC2C384-10TQG144I 0.5mm 34.1 6.5 Plastic Quad Flat Pack; 20mm x 20mm 118 I Pb-free XC2C384-10PQG208I 0.5mm 36.1 8.4 Plastic Quad Flat Pack; 28mm x 28mm 173 I Pb-free XC2C384-10FTG256I 1.0mm 33.5 5.5 Fine Pitch Thin BGA; 17mm x 17mm 212 I Pb-free XC2C384-10FGG324I 1.0mm 39.3 5.3 Fine Pitch BGA; Pb-free 23mm x 23mm 240 I Notes: 1. C = Commercial (TA = 0°C to +70°C); I = Industrial (TA = –40°C to +85°C).. Standard Example: X C 2 C 1 28 - 7 TQ 144 C Pb-Free Example: X C 2 C 1 28 -7 TQ G 144 C Device Device Speed Grade Speed Grade Package Type Package Type Number of Pins Pb-Free Temperature Range Number of Pins Temperature Range 18 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Device Part Marking R Device Type XC2Cxxx Package TQ144 This line not related to device part number Speed 7C Operating Range Part marking for non-chip scale package Figure 5: Sample Package with Part Marking DS095 (v3.2) March 8, 2007 www.xilinx.com 19 Product Specification

XC2C384 CoolRunner-II CPLD R 2 4 4 O O O ND(3)OO CCIOOOOOOOOOOOOO CCIOOONDDOOOOOOOOOOOOO CCI GI/I/VI/I/I/I/I/I/I/I/I/I/I/I/I/VI/I/I/GTI/I/I/I/I/I/I/I/I/I/I/I/V 432109876543210987654321098765432109 I/VOC(1C) 12 141414141413131313131313131313121212121212121212121111111111111111111110108 GND I/O(1) 3 107 I/O I/O 4 106 I/O I/O(1) 5 105 I/O I/O(1) 6 104 I/O I/O 7 103 I/O VAUX 8 102 I/O I/O 9 101 I/O I/O 10 100 I/O I/O 11 99 GND I/O 12 98 I/O I/O 13 97 I/O I/O 14 96 I/O I/O 15 95 I/O I/O 16 94 I/O I/O 17 93 VCCIO3 I/O 18 TQ144 92 I/O I/O 19 91 I/O I/O 20 Top View 90 GND I/O 21 89 GND I/O 22 88 I/O I/O 23 87 I/O I/O 24 86 I/O I/O 25 85 I/O I/O 26 84 VCC VCCIO1 27 83 I/O I/O 28 82 I/O GND 29 81 I/O I/O(2) 30 80 I/O I/O 31 79 I/O I/O(2) 32 78 I/O I/O 33 77 I/O I/O 34 76 I/O I/O(4) 35 75 I/O GND 36 74 I/O 73 VCCIO3 789012345678901234567890123456789012 333444444444455555555556666666666777 VCC(2)I/O(5)I/OI/OI/OI/OI/OI/OI/OI/OGNDI/OI/OI/OI/OI/OI/OI/O CCIO1I/OI/OI/OI/OI/OI/OGNDTDII/OTMSI/OTCKI/OI/OI/OI/OGND V (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 6: TQ144 Thin Quad Flat Pack 20 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD 2 4 4 4 O O O O D3) CI D CI DO CI CI ONO(OCOOOOOOOOOOOOONOOOOOOOOCOOONDOOOCOOOOOOOOOOOOOOC I/GI/I/VI/I/I/I/I/I/I/I/I/I/I/I/I/GI/I/I/I/I/I/I/I/VI/I/I/GTI/I/I/VI/I/I/I/I/I/I/I/I/I/I/I/I/I/V 8765432109876543210987654321098765432109876543210987 0000000009999999999888888888877777777776666666666555 2222222221111111111111111111111111111111111111111111 VCC 1 156 GND I/O 2 155 I/O I/O(1) 3 154 I/O I/O 4 153 I/O I/O(1) 5 152 I/O I/O 6 151 I/O I/O(1) 7 150 I/O I/O 8 149 I/O I/O(1) 9 148 I/O I/O 10 147 I/O VAUX 11 146 I/O I/O 12 145 I/O GND 13 144 I/O I/O 14 143 I/O I/O 15 142 I/O I/O 16 141 GND I/O 17 140 I/O I/O 18 139 I/O I/O 19 138 I/O I/O 20 137 I/O I/O 21 136 I/O I/O 22 135 I/O I/O 23 134 I/O GND 24 133 VCCIO4 I/O 25 132 VCCIO3 VCCIO2 26 131 I/O I/O 27 130 GND I/O 28 PQ208 129 GND I/O 29 Top View 128 I/O I/O 30 127 I/O I/O 31 126 I/O I/O 32 125 I/O VCCIO1 33 124 VCC I/O 34 123 I/O I/O 35 122 I/O I/O 36 121 I/O I/O 37 120 I/O I/O 38 119 I/O I/O 39 118 I/O I/O 40 117 I/O I/O 41 116 I/O GND 42 115 I/O I/O 43 114 I/O I/O(2) 44 113 I/O I/O 45 112 I/O I/O(2) 46 111 I/O I/O 47 110 I/O I/O 48 109 I/O I/O 49 108 I/O I/O 50 107 I/O I/O(4) 51 106 I/O GND 52 105 VCCIO3 01234 3456789012345678901234567890123456789012345678900000 5555555666666666677777777778888888888999999999911111 VCCI/OO(2)I/OI/OO(5)CIO1I/OI/OI/OI/OI/OI/OI/OI/OGNDI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OCIO1I/OGNDI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OCIO3GNDTDII/OTMSI/OTCKI/OI/OI/OI/OI/OGND I/ I/C C C V V V (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 7: PQ208 Plastic Quad Flat Package DS095 (v3.2) March 8, 2007 www.xilinx.com 21 Product Specification

XC2C384 CoolRunner-II CPLD R 6 5 4 3 2 1 0 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 A I/O I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O B I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O C I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(3) I/O I/O I/O D I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O VCC I/O(1) I/O(1) I/O I/O E I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(1) I/O I/O(1) I/O I/O F I/O I/O I/O I/O I/O GND VCCIO4 VCCIO4 VCCIO2 VCCIO2 GND I/O VAUX I/O I/O I/O G I/O I/O I/O I/O I/O I/O GND GND GND GND VCCIO2 I/O I/O I/O I/O I/O H I/O I/O I/O I/O I/O VCCIO4 GND GND GND GND VCCIO2 I/O I/O I/O I/O I/O J I/O I/O I/O I/O I/O VCCIO3 GND GND GND GND VCCIO1 I/O I/O I/O I/O I/O K I/O I/O I/O VCC I/O VCCIO3 GND GND GND GND VCCIO1 I/O I/O I/O I/O I/O L I/O I/O I/O I/O I/O GND VCCIO3 VCCIO3 VCCIO1 VCCIO1 GND I/O I/O I/O I/O I/O M I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(2) I/O(2) I/O N I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P I/O I/O I/O I/O TCK I/O I/O I/O I/O I/O I/O I/O(2) I/O VCC I/O(4) I/O R I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O T I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(5) I/O FT256 Bottom View (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 8: FT256 Fine Pitch Thin BGA 22 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD 2 1 0 9 8 7 6 5 4 3 2 1 0 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 A I/O I/O VCC I/O I/O NC NC NC NC I/O NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O(3) I/O B I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(1) C I/O I/O I/O I/O I/O I/O I/O I/O TDO I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(1) D I/O I/O I/O I/O GND I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O GND VCC I/O(1) I/O NC E I/O I/O I/O GND GND VCC I/O I/O(1) F I/O I/O I/O I/O I/O NC I/O VAUX G I/O I/O I/O I/O I/O I/O I/O I/O H I/O I/O NC I/O I/O I/O I/O I/O J I/O I/O I/O I/O GND VCCIO4 VCCIO4 VCCIO2 VCCIO2 GND NC I/O I/O I/O K I/O I/O I/O I/O VCCIO4 GND GND GND GND VCCIO2 NC I/O I/O I/O L I/O I/O I/O I/O VCCIO4 GND GND GND GND VCCIO2 NC I/O I/O I/O M I/O I/O I/O I/O VCCIO3 GND GND GND GND VCCIO1 NC I/O I/O I/O N I/O I/O VCC I/O VCCIO3 GND GND GND GND VCCIO1 NC I/O I/O I/O P NC I/O I/O NC GND VCCIO3 VCCIO3 VCCIO1 VCCIO1 GND I/O I/O I/O I/O R I/O I/O NC NC I/O I/O I/O I/O T I/O I/O I/O I/O I/O I/O I/O I/O U I/O I/O I/O I/O I/O I/O I/O I/O V I/O I/O I/O GND GND I/O(2) I/O I/O W I/O I/O I/O I/O GND NC NC I/O I/O NC I/O I/O I/O NC I/O I/O I/O GND I/O NC I/O I/O Y I/O I/O I/O TCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O(2) AA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(5) I/O VCC I/O I/O AB I/O I/O TMS TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(2) I/O(4) NC FG324 Bottom View (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 9: FG324 Fine Pitch BGA DS095 (v3.2) March 8, 2007 www.xilinx.com 23 Product Specification

XC2C384 CoolRunner-II CPLD R Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Additional Information Additional information is available for the following CoolRunner-II topics: • XAPP784: Bulletproof CPLD Design Practices To access these and all application notes with their associ- • XAPP375: Timing Model ated reference designs, click the following link and scroll down the page until you find the document you want: • XAPP376: Logic Engine • XAPP378: Advanced Features CoolRunner-II Data Sheets and Application Notes • XAPP382: I/O Characteristics Device Packages • XAPP389: Powering CoolRunner-II • XAPP399: Assigning VREF Pins Revision History The following table shows the revision history for this document. Date Version Revision 5/31/02 1.0 Initial Xilinx release 9/23/02 1.1 Updated FT256 and TQ144 pinouts 4/16/03 1.2 Updated FG324 package, updated No Connect pins 5/30/03 2.0 Added -6, -10 characterization data 11/7/03 2.1 Corrected typo on page 1. 324-ball FG BGA package has ball pitch of 1.0mm 1/26/04 2.2 Added links to Application notes and Data sheets 5/7/04 2.3 Corrected error in package dimensions of XC2C384-10TQ144I 8/03/04 2.4 Pb-free documentation 10/01/04 2.5 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics 01/30/05 2.6 Change to I MAX for Industrial devices CCSB 03/07/05 2.7 Deleted -6 speed grade. Modifications to Table 1, IOSTANDARDs 2/06/06 2.8 Change to T for -7 speed grade. Previous value was typographical error SUI 03/20/06 2.9 Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can also be used for general purpose I/O 24 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification

R XC2C384 CoolRunner-II CPLD Date Version Revision 07/14/06 3.0 Move to Product Specification. Changes to - 7 speed grade: T , T , T , T , T , SUD SU1 SU2 CO PCO T , F , T , T , T , T , T and F . Changes to -10 speed grade: T , F EXT1 GCK ECSU COI SUEC CW EXT2 SUD T , T , T , F , F , F , and F Change to Test Conditions for SU1 SU2 PSUD SYSTEM1 SYSTEM2 EXT EXT2. V and V on HSTL1 DC Voltage Specifications, page 5 (V goes to 1.4V from 1.7V). OH OL CCIO 02/15/07 3.1 Corrections to timing parameters t for -6 speed grade, and to t , t , t , t , OEM DIN SUI ECSU PSU1 t , t ,and t for the -7 speed grade. Values now match the software. There were PSU2 PHD SUEC no changes to silicon or characterization. Change to V specification for 2.5V and 1.8V IH LVCMOS. 03/08/07 3.2 Fixed typo in note for V for LVCMOS18; removed note for V for LVCMOS33. IL IL DS095 (v3.2) March 8, 2007 www.xilinx.com 25 Product Specification

XC2C384 CoolRunner-II CPLD R 26 www.xilinx.com DS095 (v3.2) March 8, 2007 Product Specification