0 R XC2C256 CoolRunner-II CPLD DS094 (v3.2) March 8, 2007 Product Specification 0 0 Features Description • Optimized for 1.8V systems The CoolRunner™-II 256-macrocell device is designed for - As fast as 5.7 ns pin-to-pin delays both high performance and low power applications. This - As low as 13 μA quiescent current lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low • Industry’s best 0.18 micron CMOS CPLD power stand-by and dynamic operation, overall system reli- - Optimized architecture for effective logic synthesis. ability is improved Refer to the CoolRunner™-II family data sheet for architecture description. This device consists of sixteen Function Blocks inter-con- - Multi-voltage I/O operation — 1.5V to 3.3V nected by a low power Advanced Interconnect Matrix (AIM). • Available in multiple package options The AIM feeds 40 true and complement inputs to each - 100-pin VQFP with 80 user I/O Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous - 144-pin TQFP with 118 user I/O configuration bits that allow for combinational or registered - 132-ball CP (0.5mm) BGA with 106 user I/O modes of operation. - 208-pin PQFP with 173 user I/O Additionally, these registers can be globally reset or preset - 256-ball FT (1.0mm) BGA with 184 user I/O and configured as a D or T flip-flop or as a D latch. There - Pb-free available for all packages are also multiple clock signals, both global and local product • Advanced system features term types, configured on a per macrocell basis. Output pin - Fastest in system programming configurations include slew rate limit, bus hold, pull-up, · 1.8V ISP using IEEE 1532 (JTAG) interface open drain and programmable grounds. A Schmitt-trigger - IEEE1149.1 JTAG Boundary Scan Test input is available on a per input pin basis. In addition to stor- - Optional Schmitt-trigger input (per pin) ing macrocell output states, the macrocell registers may be - Unsurpassed low power management configured as "direct input" registers to store signals directly · DataGATE enable (DGE) signal control from input pins. - Two separate I/O banks - RealDigital 100% CMOS product term generation Clocking is available on a global or Function Block basis. - Flexible clocking modes Three global clocks are available for all Function Blocks as · Optional DualEDGE triggered registers a synchronous clock source. Macrocell registers can be · Clock divider (divide by 2,4,6,8,10,12,14,16) individually configured to power up to the zero or one state. · CoolCLOCK A global set/reset control line is also available to asynchro- - Global signal options with macrocell control nously set or reset selected registers during operation. · Multiple global clocks with phase selection per Additional local clock, synchronous clock-enable, asynchro- macrocell nous set/reset and output enable signals can be formed · Multiple global output enables using product terms on a per-macrocell or per-Function · Global set/reset Block basis. - Advanced design security A DualEDGE flip-flop feature is also available on a per mac- - PLA architecture rocell basis. This feature allows high performance synchro- · Superior pinout retention nous operation based on lower frequency clocking to help · 100% product term routability across function reduce the total power consumption of the device. block - Open-drain output option for Wired-OR and LED Circuitry has also been included to divide one externally drive supplied global clock (GCK2) by eight different selections. - Optional bus-hold, 3-state or weak pull-up on This yields divide by even and odd clock frequencies. selected I/O pins The use of the clock divide (division by 2) and DualEDGE - Optional configurable grounds on unused I/Os flip-flop gives the resultant CoolCLOCK feature. - Mixed I/O voltages compatible with 1.5V, 1.8V, DataGATE is a method to selectively disable inputs of the 2.5V, and 3.3V logic levels CPLD that are not of interest during certain points in time. · SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility - Hot pluggable © 2002-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS094 (v3.2) March 8, 2007 www.xilinx.com 1 Product Specification

XC2C256 CoolRunner-II CPLD R By mapping a signal to the DataGATE function, lower power for I/O standard voltages. The LVTTL I/O standard is a gen- can be achieved due to reduction in signal switching. eral purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The Another feature that eases voltage translation is I/O bank- LVCMOSstandard is used in 3.3V, 2.5V, 1.8V applications. ing. Two I/O banks are available on the CoolRunner-II256 Both HSTL and SSTL I/O standards make use of a V pin macrocell device that permit easy interfacing to 3.3V, 2.5V, REF for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V 1.8V, and 1.5V devices. I/O compatible with the use of Schmitt-trigger inputs The CoolRunner-II 256 macrocell CPLD is I/O compatible with various I/O standards (see Table1). This device is also Table 1: I/O Standards for XC2C256(1) 1.5V I/O compatible with the use of Schmitt-trigger inputs. Board IOSTANDARD Output Input Input Termination RealDigital Design Technology Attribute V V V Voltage V CCIO CCIO REF TT Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron LVTTL 3.3 3.3 N/A N/A process technology which is derived from leading edge LVCMOS33 3.3 3.3 N/A N/A FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS LVCMOS25 2.5 2.5 N/A N/A technology in both the fabrication and design methodology. LVCMOS18 1.8 1.8 N/A N/A RealDigital design technology employs a cascade of CMOS LVCMOS15 (2) 1.5 1.5 N/A N/A gates to implement sum of products instead of traditional HSTL_1 1.5 1.5 0.75 0.75 sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance and SSTL2_1 2.5 2.5 1.25 1.25 low power operation. SSTL3_1 3.3 3.3 1.5 1.5 (1)For information on Vref, see XAPP399. Supported I/O Standards (2) LVCMOS15 requires Schmitt-trigger inputs. The CoolRunner-II 256 macrocell features LVCMOS, LVTTL, SSTL and HSTL I/O implementations. See Table1 100 75 A) m (C 50 C I 25 0 0 50 100 150 200 250 Frequency (MHz) Figure 1: I vs Frequency CC Table 2: I vs Frequency (LVCMOS 1.8V T = 25°C)(1) CC A Frequency (MHz) 0 30 50 70 100 120 150 170 190 220 240 Typical I (mA) 0.021 11.68 19.40 27.01 38.18 45.54 56.32 63.37 70.40 80.90 88.03 CC Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). 2 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD Absolute Maximum Ratings Symbol Description Value Units V Supply voltage relative to ground –0.5 to 2.0 V CC V Supply voltage for output drivers –0.5 to 4.0 V CCIO V (2) JTAG input voltage limits –0.5 to 4.0 V JTAG V JTAG input supply voltage –0.5 to 4.0 V CCAUX V (1) Input voltage relative to ground –0.5 to 4.0 V IN V (1) Voltage applied to 3-state output –0.5 to 4.0 V TS T (3) Storage Temperature (ambient) –65 to +150 °C STG T Junction Temperature +150 °C J Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427. Recommended Operating Conditions Symbol Parameter Min Max Units V Supply voltage for internal logic Commercial T = 0°C to +70°C 1.7 1.9 V CC A and input buffers Industrial T = –40°C to +85°C 1.7 1.9 V A V Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V CCIO Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V V JTAG programming 1.7 3.6 V CCAUX DC Electrical Characteristics (Over Recommended Operating Conditions) Symbol Parameter Test Conditions Typical Max. Units I Standby current Commercial V = 1.9V, V = 3.6V 33 150 μA CCSB CC CCIO I Standby current Industrial V = 1.9V, V = 3.6V 54 300 μA CCSB CC CCIO I Dynamic current f = 1 MHz - 410 μA CC f = 50 MHz - 27 mA C JTAG input capacitance f = 1 MHz - 10 pF JTAG C Global clock input capacitance f = 1 MHz - 12 pF CLK C I/O capacitance f = 1 MHz - 10 pF IO I (2) Input leakage current V = 0V or V to 3.9V - +/–1 μA IL IN CCIO I (2) I/O High-Z leakage V = 0V or V to 3.9V - +/–1 μA IH IN CCIO Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block) tested at V = V = 1.9V CC CCIO 2. See Quality and Reliability section of the CoolRunner-II family data sheet DS094 (v3.2) March 8, 2007 www.xilinx.com 3 Product Specification

XC2C256 CoolRunner-II CPLD R LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage - 3.0 3.6 V CCIO V High level input voltage - 2 3.9 V IH V Low level input voltage - –0.3 0.8 V IL V High level output voltage I = –8 mA, V = 3V V – 0.4V - V OH OH CCIO CCIO I = –0.1 mA, V = 3V V – 0.2V - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 3V - 0.4 V OL OL CCIO I = 0.1 mA, V = 3V - 0.2 V OL CCIO LVCMOS 2.5V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage - 2.3 2.7 V CCIO V High level input voltage - 1.7 V + 0.3(1) V IH CCIO V Low level input voltage - –0.3 0.7 V IL V High level output voltage I = –8 mA, V = 2.3V V – 0.4V - V OH OH CCIO CCIO I = –0.1 mA, V = 2.3V V – 0.2V - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 2.3V - 0.4 V OL OL CCIO I = 0.1 mA, V = 2.3V - 0.2 V OL CCIO (1) The V Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without IH physical damage. LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage - 1.7 1.9 V CCIO V High level input voltage - 0.65 x V V + 0.3(1) V IH CCIO CCIO V Low level input voltage - –0.3 0.35 x V V IL CCIO V High level output voltage I = –8 mA, V = 1.7V V – 0.45 - V OH OH CCIO CCIO I = –0.1 mA, V = 1.7V V – 0.2 - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 1.7V - 0.45 V OL OL CCIO I = 0.1 mA, V = 1.7V - 0.2 V OL CCIO (1) The V Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without IH physical damage. LVCMOS 1.5V DC Voltage Specifications(1) Symbol Parameter Test Conditions Min. Max. Units V Input source voltage - 1.4 1.6 V CCIO V Input hysteresis threshold voltage - 0.5 x V 0.8 x V V T+ CCIO CCIO V - 0.2 x V 0.5 x V V T- CCIO CCIO 4 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD Symbol Parameter Test Conditions Min. Max. Units V High level output voltage I = –8 mA, V = 1.4V V – 0.45 - V OH OH CCIO CCIO I = –0.1 mA, V = 1.4V V – 0.2 - V OH CCIO CCIO V Low level output voltage I = 8 mA, V = 1.4V - 0.4 V OL OL CCIO I = 0.1 mA, V = 1.4V - 0.2 V OL CCIO Notes: 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V Input source voltage - 1.4 3.9 V CCIO V Input hysteresis threshold voltage - 0.5 x V 0.8 x V V T+ CCIO CCIO V - 0.2 x V 0.5 x V V T- CCIO CCIO SSTL2-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V Input source voltage - 2.3 2.5 2.7 V CCIO V (1) Input reference voltage - 1.15 1.25 1.35 V REF V (2) Termination voltage - V – 0.04 1.25 V + 0.04 V TT REF REF V High level input voltage - V + 0.18 - 3.9 V IH REF V Low level input voltage - –0.3 - V – 0.18 V IL REF V High level output voltage I = –8 mA, V = 2.3V V – 0.62 - - V OH OH CCIO CCIO V Low level output voltage I = 8 mA, V = 2.3V - - 0.54 V OL OL CCIO Notes: 1. V should track the variations in V , also peak to peak AC noise on V may not exceed ± 2% V REF CCIO REF REF 2. V of transmitting device must track V of receiving devices TT REF DS094 (v3.2) March 8, 2007 www.xilinx.com 5 Product Specification

XC2C256 CoolRunner-II CPLD R SSTL3-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V Input source voltage - 3.0 3.3 3.6 V CCIO V (1) Input reference voltage - 1.3 1.5 1.7 V REF V (2) Termination voltage - V – 0.05 1.5 V + 0.05 V TT REF REF V High level input voltage - V + 0.2 - V + 0.3 V IH REF CCIO V Low level input voltage - –0.3 - V – 0.2 V IL REF V High level output voltage I = –8 mA, V = 3V V – 1.1 - - V OH OH CCIO CCIO V Low level output voltage I = 8 mA, V = 3V - - 0.7 V OL OL CCIO Notes: 1. V should track the variations in V , also peak to peak AC noise on V may not exceed ± 2% V REF CCIO REF REF 2. V of transmitting device must track V of receiving devices TT REF HSTL1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V Input source voltage - 1.4 1.5 1.6 V CCIO V (1) Input reference voltage - 0.68 0.75 0.90 V REF V (2) Termination voltage - - V x0.5 - V TT CCIO V High level input voltage - V + 0.1 - 1.9 V IH REF V Low level input voltage - –0.3 - V – 0.1 V IL REF V High level output voltage I = –8 mA, V = 1.7V V – 0.4 - - V OH OH CCIO CCIO V Low level output voltage I = 8 mA, V = 1.7V - - 0.4 V OL OL CCIO Notes: 1. V should track the variations in V , also peak-to-peak AC noise on V may not exceed ± 2% V REF CCIO REF REF 2. V of transmitting device must track V of receiving devices TT REF AC Electrical Characteristics Over Recommended Operating Conditions -6 -7 Symbol Parameter Min. Max. Min. Max. Units T Propagation delay single p-term - 5.7 - 6.7 ns PD1 T Propagation delay OR array - 6.0 - 7.5 ns PD2 T Direct input register clock setup time 2.6 - 3.0 - ns SUD T Setup time (single p-term) 2.4 - 2.8 - ns SU1 T Setup time (OR array) 2.7 - 3.3 - ns SU2 T Direct input register hold time 0 - 0 - ns HD T P-term hold time 0 - 0 - ns H T Clock to output - 4.5 - 6.0 ns CO F (1) Internal toggle rate - 450 - 300 MHz TOGGLE F (2) Maximum system frequency - 256 - 152 MHz SYSTEM1 F (2) Maximum system frequency - 238 - 141 MHz SYSTEM2 F (3) Maximum external frequency - 145 - 114 MHz EXT1 F (3) Maximum external frequency - 139 - 108 MHz EXT2 T Direct input register p-term clock setup time 1.3 - 1.7 - ns PSUD 6 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD -6 -7 Symbol Parameter Min. Max. Min. Max. Units T P-term clock setup time (single p-term) 1.2 - 1.5 - ns PSU1 T P-term clock setup time (OR array) 1.5 - 2.0 - ns PSU2 T Direct input register p-term clock hold time 1.1 - 1.2 - ns PHD T P-term clock hold 1.0 - 1.0 - ns PH T P-term clock to output - 6.5 - 7.3 ns PCO T /T Global OE to output enable/disable - 5.6 - 7.0 ns OE OD T /T P-term OE to output enable/disable - 7.3 - 8.0 ns POE POD T /T Macrocell driven OE to output enable/disable - 7.4 - 9.9 ns MOE MOD T P-term set/reset to output valid - 7.5 - 8.1 ns PAO T Global set/reset to output valid - 5.7 - 7.6 ns AO T Register clock enable setup time 2.8 - 3.1 - ns SUEC T Register clock enable hold time 0 - 0 - ns HEC T Global clock pulse width High or Low 1.1 - 1.6 - ns CW T P-term pulse width High or Low 6.0 - 7.5 - ns PCW T Asynchronous preset/reset pulse width (High or Low) 6.0 - 7.5 - ns APRPW T Set-up before DataGATE latch assertion 0 - 0 - ns DGSU T Hold to DataGATE latch assertion 4.0 - 6.0 - ns DGH T DataGATE recovery to new data - 8.2 - 9.0 ns DGR T DataGATE low pulse width 2.5 - 3.5 - ns DGW T CDRST setup time before falling edge GCLK2 1.6 - 2.0 - ns CDRSU T Hold time CDRST after falling edge GCLK2 0 - 0 - ns CDRH T (4) Configuration time - 150 - 150 μs CONFIG Notes: 1. F is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more TOGGLE information). 2. F (1/T ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per SYSTEM1 CYCLE macrocell while F is through the OR array. SYSTEM2 3. F (1/T +T ) is the maximum external frequency using one p-term while F is through the OR array. EXT1 SU1 CO EXT2 4. Typical configuration current during T is approximately 7.7 mA. CONFIG DS094 (v3.2) March 8, 2007 www.xilinx.com 7 Product Specification

XC2C256 CoolRunner-II CPLD R (Internal Timing Parameters -6 -7 Symbol Parameter(2) Min. Max. Min. Max. Units Buffer Delays T Input buffer delay - 2.4 - 2.6 ns IN T Direct data register input delay - 3.1 - 3.9 ns DIN T Global Clock buffer delay - 1.8 - 2.7 ns GCK T Global set/reset buffer delay - 2.0 - 3.5 ns GSR T Global 3-state buffer delay - 2.1 - 3.0 ns GTS T Output buffer delay - 2.3 - 2.6 ns OUT T Output buffer enable/disable delay - 3.5 - 4.0 ns EN P-term Delays T Control term delay - 1.1 - 1.4 ns CT T Single P-term delay adder - 0.5 - 1.1 ns LOGI1 T Multiple P-term delay adder - 0.3 - 0.5 ns LOGI2 Macrocell Delay T Input to output valid - 0.5 - 0.7 ns PDI T Setup before clock 1.3 - 1.8 - ns SUI T Hold after clock 0 - 0 - ns HI T Enable clock setup time 0.8 - 1.8 - ns ECSU T Enable clock hold time 0 - 0 - ns ECHO T Clock to output valid - 0.4 - 0.7 ns COI T Set/reset to output valid - 1.4 - 1.5 ns AOI T Clock doubler delay - 0 - 0 ns CDBL Feedback Delays T Feedback delay - 1.7 - 3.0 ns F T Macrocell to global OE delay - 1.7 - 2.5 ns OEM I/O Standard Time Adder Delays 1.5V CMOS T Hysteresis input adder - 3.0 - 4.0 ns HYS15 T Output adder - 0.8 - 1.0 ns OUT15 T Output slew rate adder - 4.0 - 5.0 ns SLEW15 I/O Standard Time Adder Delays 1.8V CMOS T Hysteresis input adder - 2.0 - 3.0 ns HYS18 T Output adder - 0 - 0 ns OUT18 T Output slew rate adder - 2.0 - 4.0 ns SLEW 8 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD Internal Timing Parameters (Continued) -6 -7 Symbol Parameter(2) Min. Max. Min. Max. Units I/O Standard Time Adder Delays 2.5V CMOS T Standard input adder - 0.6 - 0.7 ns IN25 T Hysteresis input adder - 1.5 - 3.0 ns HYS25 T Output adder - 0.8 - 1.0 ns OUT25 T Output slew rate adder - 3.0 - 4.0 ns SLEW25 I/O Standard Time Adder Delays 3.3V CMOS/TTL T Standard input adder - 0.5 - 0.7 ns IN33 T Hysteresis input adder - 1.2 - 3.0 ns HYS33 T Output adder - 1.2 - 1.6 ns OUT33 T Output slew rate adder - 3.0 - 4.0 ns SLEW33 I/O Standard Time Adder Delays HSTL, SSTL SSTL2-1 Input adder to T , T , T , T ,T - 0.4 - 1.0 ns IN DIN GCK GSR GTS Output adder to T - -0.5 - 0.0 ns OUT SSTL3-1 Input adder to T , T , T , T ,T - 0.4 - 1.0 ns IN DIN GCK GSR GTS Output adder to T - -0.5 - 0.0 ns OUT HSTL-1 Input adder to T , T , T , T ,T - 0.6 - 1.0 ns IN DIN GCK GSR GTS Output adder to T - 0 - 0 ns OUT Notes: 1. 1.5 ns input pin signal rise/fall. Switching Characteristics AC Test Circuit VCC = VCCIO = 1.8V, T = 25oC VCC 5.5 R1 Device Test Point 5.0 Under Test R2 CL 4.5 s) Output Type R1 R2 CL (nD2 4.0 LLVVTCTMLO3S333 226785ΩΩ 223755ΩΩ 3355 ppFF P T LVCMOS25 188Ω 188Ω 35pF 3.5 LVCMOS18 112.5Ω 112.5Ω 35pF LVCMOS15 150Ω 150Ω 35pF CL includes test fixtures and probe capacitance. 3.0 1.5 nsec maximum rise/fall times on inputs. 1 2 4 8 16 DS_ACT_08_14_02 Number of Outputs Switching Figure 3: AC Load Circuit DS092_02_092302 Figure 2: Derating Curve for T PD DS094 (v3.2) March 8, 2007 www.xilinx.com 9 Product Specification

XC2C256 CoolRunner-II CPLD R Typical I/V Output Curves The I/V curve illustrates the nominal amount of current that an I/O can source/sink at different voltage levels. 3.3V 60 50 A) m nt 40 2.5V e urr 1.8V C ut Iol p 30 ut O O ( I 20 1.5V 10 0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5 VO (Output Volts) XC256_VoIo_all_020703 Figure 4: Typical I/V Curve for XC2C256 10 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD 1P1 in Descriptions Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank 1 1 - - - 2 B3 2 3 1 - - 136 196 A6 2 1 2 - - - 208 B4 2 3 2 - B5 135 195 D7 2 1(GSR) 3 99 A3 143 206 C4 2 3 3 - - 134 194 B7 2 1 4 - - 142 205 A2 2 3 4 - A5 - 193 E9 2 1 5 - - - 203 A3 2 3 5 93 - 133 192 A7 2 1 6 97 B4 140 202 A4 2 3 6 C6 191 D8 2 1 7 - - - - - - 3 7 - - - - - - 1 8 - - - - - - 3 8 - - - - - - 1 9 - - - - - - 3 9 - - - - - - 1 10 - - - - - - 3 10 - - - - - - 1 11 - - - - - - 3 11 - - - - - - 1 12 96 - 139 201 B5 2 3 12 92 - - 189 B8 2 1 13 95 - 138 200 A5 2 3 13 - B6 - 188 C8 2 1 14 94 A4 137 199 E8 2 3 14 91 A6 132 187 A8 2 1 15 - - - 198 B6 2 3 15 - C7 - 186 E11 2 1 16 - C5 - 197 C7 2 3 16 90 B7 131 185 E10 2 2(GTS2) 1 1 A1 2 3 D3 2 4 1 8 E3 11 15 F2 2 2 2 - - - 4 C3 2 4 2 9 - 12 16 F3 2 2(GTS3) 3 2 B2 3 5 E3 2 4 3 10 E2 13 17 G4 2 2 4 - B1 4 6 B2 2 4 4 - E1 14 18 G3 2 2(GTS0) 5 3 C3 5 7 D4 2 4 5 11 F3 15 19 F5 2 2 6 - - - 8 D2 2 4 6 12 F2 16 20 G5 2 2 7 - - - - - - 4 7 - - - - - - 2 8 - - - - - - 4 8 - - - - - - 2 9 - - - - - - 4 9 - - - - - - 2 10 - - - - - - 4 10 - - - - - - 2 11 - - - - - - 4 11 - - - - - - 2(GTS1) 12 4 C2 6 9 E5 2 4 12 - F1 17 21 H2 2 2 13 - C1 7 10 B1 2 4 13 13 G1 - 22 H4 2 2 14 6 D2 9 12 E4 2 4 14 - - 18 23 H3 2 2 15 7 - 10 14 C1 2 4 15 - - - - H1 2 2 16 - D1 - - E2 2 4 16 - - - 25 H5 2 DS094 (v3.2) March 8, 2007 www.xilinx.com 11 Product Specification

XC2C256 CoolRunner-II CPLD R Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank 5 1 - L3 - 49 R1 1 7 1 - - - 37 K4 1 5 2 - - 33 48 N4 1 7 2 - - - 36 L2 1 5 3 - - - 47 N2 1 7 3 - - - 35 K3 1 5(GCK1) 4 23 L2 32 46 M3 1 7 4 - - - 34 L1 1 5 5 L1 31 45 P1 1 7 5 19 J2 26 32 K5 1 5(GCK0) 6 22 K3 30 44 M2 1 7 6 18 J1 25 31 K2 1 5 7 - - - - - - 7 7 - - - - - - 5 8 - - - - - - 7 8 - - - - - - 5 9 - - - - - - 7 9 - - - - - - 5 10 - - - - - - 7 10 - - - - - - 5 11 - - - - - - 7 11 17 H3 24 30 J4 1 5 12 - - - 43 L3 1 7 12 16 H2 23 29 K1 1 5 13 - - - 41 N1 1 7 13 15 H1 22 28 J3 1 5 14 - - 28 40 L4 1 7 14 14 G3 21 27 J2 1 5 15 - - - 39 M1 1 7 15 - G2 20 - J5 1 5 16 - K1 - 38 L5 1 7 16 - - 19 - J1 1 6 1 - M1 34 50 N3 1 8 1 - N4 44 64 R6 1 6 2 24 M2 35 51 P2 1 8 2 - - 45 65 N6 1 (CDRST) 8 3 - - 46 66 R3 1 6 3 - - - 54 P4 1 8 4 - - - 67 M6 1 6(GCK2) 4 27 N2 38 55 P5 1 8 5 - - 48 69 T3 1 6 5 - - - 56 R2 1 8 6 32 - 49 70 P6 1 6 6 - - - 57 T1 1 8 7 - - - - - - 6 7 - - - - - - 8 8 - - - - - - 6 8 - - - - - - 8 9 - - - - - - 6 9 - - - - - - 8 10 - - - - - - 6 10 - - - - - - 8 11 33 M5 50 71 T4 1 6 11 - - - - - - 8 12 34 N5 51 72 P7 1 6(DGE) 12 28 P2 39 58 T2 1 8 13 35 P5 52 73 T5 1 6 13 - M3 40 60 N5 1 8 14 36 M6 - 74 N7 1 6 14 29 N3 41 61 R4 1 8 15 37 N6 - 75 R7 1 6 15 - P3 42 62 M5 1 8 16 - - - 76 M7 1 6 16 30 M4 43 63 R5 1 12 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank 9 1 78 C12 112 160 B13 2 11 1 - B10 - - B11 2 9 2 79 B12 113 161 B14 2 11 2 - - 173 D11 2 9 3 - - - 162 C13 2 11 3 - A10 - 174 A11 2 9 4 80 A12 114 163 A15 2 11 4 - - - 175 D10 2 9 5 164 C12 2 11 5 - C9 120 - B10 2 9 6 81 C11 115 165 B12 2 11 6 - - 121 - E12 2 9 7 - - - - - - 11 7 - - - - - - 9 8 - - - - - - 11 8 - - - - - - 9 9 - - - - - - 11 9 - - - - - - 9 10 - - - - - - 11 10 - - - - - - 9 11 - - - 166 D13 2 11 11 85 A8 124 178 F12 2 9 12 82 B11 116 167 A14 2 11 12 86 B8 125 179 B9 2 9 13 - - 117 168 E13 2 11 13 87 C8 126 180 C9 2 9 14 - A11 118 169 A13 2 11 14 89 - 128 182 C10 2 9 15 - - 119 170 C11 2 11 15 - - 129 183 A9 2 9 16 - C10 - 171 A12 2 11 16 - - 130 184 D9 2 10 1 77 A13 111 159 A16 2 12 1 - - - 145 F15 2 10 2 76 B13 110 158 B15 2 12 2 - - 100 144 G14 2 10 3 74 C13 107 155 C14 2 12 3 - - - 143 E16 2 10 4 73 C14 106 154 G11 2 12 4 - - - 142 H12 2 10 5 72 D12 105 153 B16 2 12 5 - F12 - 140 F16 2 10 6 71 D13 104 152 D15 2 12 6 - F13 - 139 H16 2 10 7 - - - - - - 12 7 - - - - - - 10 8 - - - - - - 12 8 - - - - - - 10 9 - - - - - - 12 9 - - - - - - 10 10 - - - - - - 12 10 - - - - - - 10 11 151 E14 2 12 11 68 F14 98 138 G15 2 10 12 70 D14 103 150 C16 2 12 12 - G12 97 137 H13 2 10 13 - - - 149 F14 2 12 13 67 G13 96 136 G16 2 10 14 - E12 102 148 F13 2 12 14 66 - 95 135 H14 2 10 15 - - - 147 E15 2 12 15 65 - 94 134 H15 2 10 16 - E13 101 146 G13 2 12 16 - - - - J12 2 DS094 (v3.2) March 8, 2007 www.xilinx.com 13 Product Specification

XC2C256 CoolRunner-II CPLD R Pin Descriptions (Continued) Pin Descriptions (Continued) Function Macro- I/O Function Macro- I/O Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank Block cell VQ100 CP132 TQ144 PQ208 FT256 Bank 13 1 - N13 75 107 R15 1 15 1 - - - 118 L15 1 13 2 53 N14 76 108 T16 1 15 2 - L14 83 119 L13 1 13 3 - M12 77 109 N14 1 15 3 - - - 120 M12 1 13 4 54 - - 110 R16 1 15 4 - - - 121 M16 1 13 5 - M13 78 111 N15 1 15 5 - - - 122 K14 1 13 6 55 - 79 112 M15 1 15 6 - - - 123 L16 1 13 7 - - - - - - 15 7 - - - - - - 13 8 - - - - - - 15 8 - - - - - - 13 9 - - - - - - 15 9 - - - - - - 13 10 - - - - - - 15 10 - - - - - - 13 11 - - - - - - 15 11 58 K13 85 125 K15 1 13 12 - M14 80 113 M13 1 15 12 59 K14 86 126 L12 1 13 13 56 - 81 114 P16 1 15 13 60 J12 87 127 K16 1 13 14 - L12 82 115 N16 1 15 14 61 J13 88 128 J14 1 13 15 - - - 116 L14 1 15 15 63 H13 91 - J15 1 13 16 - L13 - 117 M14 1 15 16 64 H12 92 131 J13 1 14 1 52 P14 74 106 P15 1 16 1 - - - 90 P10 1 14 2 - - 71 103 P14 1 16 2 - - - 89 R10 1 14 3 50 P12 70 102 P13 1 16 3 - M8 - 88 T10 1 14 4 - M11 69 101 R13 1 16 4 - - - 87 R9 1 14 5 49 N11 - 100 N13 1 16 5 43 N8 60 86 N9 1 14 6 - P11 68 - R14 1 16 6 42 - 59 85 M8 1 14 7 - - - - - - 16 7 - - - - - - 14 8 - - - - - - 16 8 - - - - - - 14 9 - - - - - - 16 9 - - - - - - 14 10 - - - - - - 16 10 - - - - - - 14 11 - - - - - - 16 11 41 P8 58 84 T8 1 14 12 - - - 99 T15 1 16 12 40 M7 57 83 P8 1 14 13 - - 66 97 R12 1 16 13 39 N7 56 82 R8 1 14 14 46 P10 64 95 N11 1 16 14 - - - 80 T7 1 14 15 44 - - - M11 1 16 15 - - 54 78 N8 1 14 16 - P9 61 91 N10 1 16 16 - P6 53 77 T6 1 Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable. 2. GTS, GSR and GCK pins can be used for general purpose I/O. 14 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD XC2C256 JTAG, Power/Ground, No Connect Pins and Total User I/O Pin Type VQ100 CP132 TQ144 PQ208 FT256 TCK 48 M10 67 98 P12 TDI 45 M9 63 94 R11 TDO 83 B9 122 176 A10 TMS 47 N10 65 96 N12 V (JTAG supply 5 D3 8 11 F4 CCAUX voltage) Power internal (V ) 26, 57 P1, K12, A2 1, 37, 84 1, 53, 124 P3, K13, D12, D5 CC Power Bank 1 I/O (V ) 20, 38, 51 J3, P7, 27, 55, 73, 93 33, 59, 79, 92, J6, K6, L7, L8, J11, CCIO1 G14, P13 105, 132 K11, L10, L9 Power Bank 2 I/O (V ) 88, 98 A14, C4, A7 109, 127, 141 26, 133, 157, F7, F8, G6, H6, F10, CCIO2 172, 181, 204 F9, H11 Ground 21, 25, 31, K2, N1, P4, 29, 36, 47, 62, 13, 24, 42, 52, F11, F6, G10, G7, G8, 62, 69, 75, N9, N12, 72, 89, 90, 99, 68, 81, 93, 104, G9, H10, H7, H8, H9, 84, 100 J14, H14, 108, 123, 144 129, 130, 141, J10, J7, J8, J9, K10, E14, B14, 156, 177, 190, K7, K8, K9, L11, L6 A9, B3 207 No connects - - - - A1, C2, E6, D1, E1, G2, F1, G1, M4, T9, P9, M9, M10, T11, T12, T13, P11, T14, J16, K12, D16, G12, C15, D14, D6, C6, E7, C5 Total user I/O 80 106 118 173 184 DS094 (v3.2) March 8, 2007 www.xilinx.com 15 Product Specification

XC2C256 CoolRunner-II CPLD R Ordering Information Commercia l (C) Pin/Ball θ θ Package Body Industrial JA JC Part Number Spacing (C/Watt) (C/Watt) Package Type Dimensions I/O (I)(1) XC2C256-6VQ100C 0.5mm 43.1 10.9 Very Thin Quad Flat 14mm x 14mm 80 C Pack XC2C256-7VQ100C 0.5mm 43.1 10.9 Very Thin Quad Flat 14mm x 14mm 80 C Pack XC2C256-6CP132C 0.5mm 65.0 15.0 Chip Scale Package 8mm x 8mm 106 C XC2C256-7CP132C 0.5mm 65.0 15.0 Chip Scale Package 8mm x 8mm 106 C XC2C256-6TQ144C 0.5mm 37.2 7.2 Thin Quad Flat Pack 20mm x 20mm 118 C XC2C256-7TQ144C 0.5mm 37.2 7.2 Thin Quad Flat Pack 20mm x 20mm 118 C XC2C256-6PQ208C 0.5mm 36.9 9.7 Plastic Quad Flat 28mm x 28mm 173 C Pack XC2C256-7PQ208C 0.5mm 36.9 9.7 Plastic Quad Flat 28mm x 28mm 173 C Pack XC2C256-6FT256C 1.0mm 34.6 6.1 Fine Pitch Thin BGA 17mm x 17mm 184 C XC2C256-7FT256C 1.0mm 34.6 6.1 Fine Pitch Thin BGA 17mm x 17mm 184 C XC2C256-6VQG100C 0.5mm 43.1 10.9 Very Thin Quad Flat 14mm x 14mm 80 C Pack; Pb-free XC2C256-7VQG100C 0.5mm 43.1 10.9 Very Thin Quad Flat 14mm x 14mm 80 C Pack; Pb-free XC2C256-6CPG132C 0.5mm 65.0 15.0 Chip Scale Package; 8mm x 8mm 106 C Pb-free XC2C256-7CPG132C 0.5mm 65.0 15.0 Chip Scale Package; 8mm x 8mm 106 C Pb-free XC2C256-6TQG144C 0.5mm 37.2 7.2 Thin Quad Flat Pack; 20mm x 20mm 118 C Pb-free XC2C256-7TQG144C 0.5mm 37.2 7.2 Thin Quad Flat Pack; 20mm x 20mm 118 C Pb-free XC2C256-6PQG208C 0.5mm 36.9 9.7 Plastic Quad Flat 28mm x 28mm 173 C Pack; Pb-free XC2C256-7PQG208C 0.5mm 36.9 9.7 Plastic Quad Flat 28mm x 28mm 173 C Pack; Pb-free XC2C256-6FTG256C 1.0mm 34.6 6.1 Fine Pitch Thin BGA; 17mm x 17mm 184 C Pb-free XC2C256-7FTG256C 1.0mm 34.6 6.1 Fine Pitch Thin BGA; 17mm x 17mm 184 C Pb-free XC2C256-7VQ100I 0.5mm 43.1 10.9 Very Thin Quad Flat 14mm x 14mm 80 I Pack XC2C256-7CP132I 0.5mm 65.0 15.0 Chip Scale Package 8mm x 8mm 106 I XC2C256-7TQ144I 0.5mm 37.2 7.2 Thin Quad Flat Pack 20mm x 20mm 118 I XC2C256-7PQ208I 0.5mm 36.9 9.7 Plastic Quad Flat 28mm x 28mm 173 I Pack XC2C256-7FT256I 1.0mm 34.6 6.1 Fine Pitch Thin BGA 17mm x 17mm 184 I 16 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD Commercia l (C) Pin/Ball θ θ Package Body Industrial JA JC Part Number Spacing (C/Watt) (C/Watt) Package Type Dimensions I/O (I)(1) XC2C256-7VQG100I 0.5mm 43.1 10.9 Very Thin Quad Flat 14mm x 14mm 80 I Pack; Pb-free XC2C256-7CPG132I 0.5mm 65.0 15.0 Chip Scale Package; 8mm x 8mm 106 I Pb-free XC2C256-7TQG144I 0.5mm 37.2 7.2 Thin Quad Flat Pack; 20mm x 20mm 118 I Pb-free XC2C256-7PQG208I 0.5mm 36.9 9.7 Plastic Quad Flat 28mm x 28mm 173 I Pack; Pb-free XC2C256-7FTG256I 1.0mm 34.6 6.1 Fine Pitch Thin BGA; 17mm x 17mm 184 I Pb-free Notes: 1. C = Commercial (TA = 0°C to +70°C); I = Industrial (TA = –40°C to +85°C). Standard Example: X C 2 C 1 28 - 6 TQ 144 C Pb-Free Example: X C 2 C 1 28 -6 TQ G 144 C Device Device Speed Grade Speed Grade Package Type Package Type Number of Pins Pb-Free Temperature Range Number of Pins Temperature Range Device Part Marking R Device Type XC2Cxxx Package TQ144 This line not related to device part number Speed 7C Operating Range Part marking for non-chip scale package Figure 5: Sample Package with Part Marking Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale packages by line are: • Line 1 = X (Xilinx logo) then truncated part number 1. Line 4 = Package code, speed, operating temperature, • Line 2 = Not related to device part number three digits not related to device part number. Package codes: C5 = CP132, C6 = CPG132. • Line 3 = Not related to device part number DS094 (v3.2) March 8, 2007 www.xilinx.com 17 Product Specification

XC2C256 CoolRunner-II CPLD R O2 O2 ND(3)OCCIOOOOOOOOOCCIOOONDDOOOOOOOO GI/VI/I/I/I/I/I/I/I/I/VI/I/I/GTI/I/I/I/I/I/I/ 0987654321098765432109876 I/O(1) 11099999999998888888888777775 GND I/O(1) 2 74 I/O I/O(1) 3 73 I/O I/O(1) 4 72 I/O VAUX 5 71 I/O I/O 6 70 I/O I/O 7 69 GND I/O 8 68 I/O I/O 9 67 I/O I/O 10 66 I/O I/O 11 VQ100 65 I/O I/O 12 Top View 64 I/O I/O 13 63 I/O I/O 14 62 GND I/O 15 61 I/O I/O 16 60 I/O I/O 17 59 I/O I/O 18 58 I/O I/O 19 57 VCC VCCIO1 20 56 I/O GND 21 55 I/O I/O(2) 22 54 I/O I/O(2) 23 53 I/O I/O(4) 24 52 I/O GND 25 51 VCCIO1 6789012345678901234567890 2222333333333344444444445 VCC(2)I/O(5)I/OI/OI/OGNDI/OI/OI/OI/OI/OI/OCCIO1I/OI/OI/OI/OI/OI/OTDII/OTMSTCKI/OI/O V (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - Data Gate Figure 6: VQ100 Very Thin Quad Flat Pack 18 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD 0 1 2 3 4 1 2 3 4 5 6 7 8 9 1 1 1 1 1 P VCC I/O(5) I/O GND I/O I/O VCCIO1 I/O I/O I/O I/O I/O VCCIO1 I/O N GND I/O(2) I/O I/O I/O I/O I/O I/O GND TMS I/O GND I/O I/O M I/O I/O(4) I/O I/O I/O I/O I/O I/O TDI TCK I/O I/O I/O I/O L I/O I/O(2) I/O I/O I/O I/O K I/O GND I/O(2) VCC I/O I/O J I/O I/O VCCIO1 I/O I/O GND H I/O I/O I/O I/O I/O GND CP132 G I/O I/O I/O Bottom View I/O I/O VCCIO1 F I/O I/O I/O I/O I/O I/O E I/O I/O I/O I/O I/O GND D I/O I/O VAUX I/O I/O I/O C I/O I/O(1) I/O(1) VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O B I/O I/O(1) GND I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O GND A I/O(1) VCC I/O(3) I/O I/O I/O VCCIO2 I/O GND I/O I/O I/O I/O VCCIO2 (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 7: CP132 Chip Scale Package DS094 (v3.2) March 8, 2007 www.xilinx.com 19 Product Specification

XC2C256 CoolRunner-II CPLD R 2 2 2 O O O ND(3)OOCCIOOOOOOOOOOOOOCCIOOONDDOOOOOOOOOOOOOCCI GI/I/VI/I/I/I/I/I/I/I/I/I/I/I/I/VI/I/I/GTI/I/I/I/I/I/I/I/I/I/I/I/V 432109876543210987654321098765432109 I/VOC(1C) 12 141414141413131313131313131313121212121212121212121111111111111111111110108 GND I/O(1) 3 107 I/O I/O 4 106 I/O I/O(1) 5 105 I/O I/O(1) 6 104 I/O I/O 7 103 I/O VAUX 8 102 I/O I/O 9 101 I/O I/O 10 100 I/O I/O 11 99 GND I/O 12 98 I/O I/O 13 97 I/O I/O 14 96 I/O I/O 15 95 I/O I/O 16 94 I/O I/O 17 93 VCCIO1 I/O 18 TQ144 92 I/O I/O 19 91 I/O I/O 20 Top View 90 GND I/O 21 89 GND I/O 22 88 I/O I/O 23 87 I/O I/O 24 86 I/O I/O 25 85 I/O I/O 26 84 VCC VCCIO1 27 83 I/O I/O 28 82 I/O GND 29 81 I/O I/O(2) 30 80 I/O I/O 31 79 I/O I/O(2) 32 78 I/O I/O 33 77 I/O I/O 34 76 I/O I/O(4) 35 75 I/O GND 36 74 I/O 73 VCCIO1 789012345678901234567890123456789012 333444444444455555555556666666666777 VCC(2)I/O(5)I/OI/OI/OI/OI/OI/OI/OI/OGNDI/OI/OI/OI/OI/OI/OI/OCCIO1I/OI/OI/OI/OI/OI/OGNDTDII/OTMSI/OTCKI/OI/OI/OI/OGND V (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 8: TQ144 Thin Quad Flat Pack 20 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD 2 2 2 2 O O O O D3) CI D CI DO CI CI ONO(OCOOOOOOOOOOOOONOOOOOOOOCOOONDOOOCOOOOOOOOOOOOOOC I/GI/I/VI/I/I/I/I/I/I/I/I/I/I/I/I/GI/I/I/I/I/I/I/I/VI/I/I/GTI/I/I/VI/I/I/I/I/I/I/I/I/I/I/I/I/I/V 8765432109876543210987654321098765432109876543210987 0000000009999999999888888888877777777776666666666555 2222222221111111111111111111111111111111111111111111 VCC 1 156 GND I/O 2 155 I/O I/O(1) 3 154 I/O I/O 4 153 I/O I/O(1) 5 152 I/O I/O 6 151 I/O I/O(1) 7 150 I/O I/O 8 149 I/O I/O(1) 9 148 I/O I/O 10 147 I/O VAUX 11 146 I/O I/O 12 145 I/O GND 13 144 I/O I/O 14 143 I/O I/O 15 142 I/O I/O 16 141 GND I/O 17 140 I/O I/O 18 139 I/O I/O 19 138 I/O I/O 20 137 I/O I/O 21 136 I/O I/O 22 135 I/O I/O 23 134 I/O GND 24 133 VCCIO2 I/O 25 132 VCCIO1 VCCIO2 26 131 I/O I/O 27 130 GND I/O 28 PQ208 129 GND I/O 29 Top View 128 I/O I/O 30 127 I/O I/O 31 126 I/O I/O 32 125 I/O VCCIO1 33 124 VCC I/O 34 123 I/O I/O 35 122 I/O I/O 36 121 I/O I/O 37 120 I/O I/O 38 119 I/O I/O 39 118 I/O I/O 40 117 I/O I/O 41 116 I/O GND 42 115 I/O I/O 43 114 I/O I/O(2) 44 113 I/O I/O 45 112 I/O I/O(2) 46 111 I/O I/O 47 110 I/O I/O 48 109 I/O I/O 49 108 I/O I/O 50 107 I/O I/O(4) 51 106 I/O GND 52 105 VCCIO1 01234 3456789012345678901234567890123456789012345678900000 5555555666666666677777777778888888888999999999911111 VCCI/OI/O(2)I/OI/OI/O(5)CCIO1I/OI/OI/OI/OI/OI/OI/OI/OGNDI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OCCIO1I/OGNDI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OCCIO1GNDTDII/OTMSI/OTCKI/OI/OI/OI/OI/OGND V V V (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 9: PQ208 Quad Flat Package DS094 (v3.2) March 8, 2007 www.xilinx.com 21 Product Specification

XC2C256 CoolRunner-II CPLD R 6 5 4 3 2 1 0 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 A I/O I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O I/O NC B I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O C I/O NC I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O(3) I/O NC I/O D NC I/O NC I/O VCC I/O I/O I/O I/O I/O NC VCC I/O(1) I/O(1) I/O NC E I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O(1) I/O I/O(1) I/O NC F I/O I/O I/O I/O I/O GND VCCIO2 VCCIO2 VCCIO2 VCCIO2 GND I/O VAUX I/O I/O NC G I/O I/O I/O I/O NC I/O GND GND GND GND VCCIO2 I/O I/O I/O NC NC H I/O I/O I/O I/O I/O VCCIO2 GND GND GND GND VCCIO2 I/O I/O I/O I/O I/O J NC I/O I/O I/O I/O VCCIO1 GND GND GND GND VCCIO1 I/O I/O I/O I/O I/O K I/O I/O I/O VCC NC VCCIO1 GND GND GND GND VCCIO1 I/O I/O I/O I/O I/O L I/O I/O I/O I/O I/O GND VCCIO1 VCCIO1 VCCIO1 VCCIO1 GND I/O I/O I/O I/O I/O M I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O I/O NC I/O(2) I/O(2) I/O N I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P I/O I/O I/O I/O TCK NC I/O NC I/O I/O I/O I/O(2) I/O VCC I/O(4) I/O R I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O T I/O I/O NC NC NC NC I/O NC I/O I/O I/O I/O I/O I/O I/O(5) I/O FT256 Bottom View (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 10: FT256 Fine Pitch Thin BGA Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. 22 www.xilinx.com DS094 (v3.2) March 8, 2007 Product Specification

R XC2C256 CoolRunner-II CPLD Additional Information Additional information is available for the following CoolRunner-II topics: • XAPP784: Bulletproof CPLD Design Practices To access these and all application notes with their associ- • XAPP375: Timing Model ated reference designs, click the following link and scroll down the page until you find the document you want: • XAPP376: Logic Engine • XAPP378: Advanced Features CoolRunner-II Data Sheets and Application Notes • XAPP382: I/O Characteristics Device Packages • XAPP389: Powering CoolRunner-II • XAPP399: Assigning VREF Pins Revision History The following table shows the revision history for this document. Date Version Revision 05/09/02 1.0 Initial Xilinx release. 05/13/02 1.1 Updated AC Electrical Characteristics and added new parameters. 10/31/02 1.2 Corrected package user I/O, added Voltage Referenced DC tables. 03/17/03 2.0 Added Characterization numbers for product release and device part marking 04/02/03 2.1 Updated T max from 260 to 220. Changed I units from mA to μA. SOL CCSB 01/26/04 2.2 Updated Device Part Marking. Updated links and Tsol. 02/26/04 2.3 Corrected Theta JC value on XC2C256-7TQ144. 08/03/04 2.4 Pb-free documentation 08/19/04 2.5 Changes to I maximum specifications in DC Electrical Characteristics table, on page 3. CCSB 10/01/04 2.6 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. 03/07/05 2.7 Removed -5 speed grade. Changes to Table 1, I/O Standards. 06/28/05 2.8 Move to Product Specification. Change to T , T , T , and T for -7 speed IN25 OUT25 IN33 OUT33 grade. 03/20/06 2.9 Add Warranty Disclaimer. Add note to Pin Description table that GTS, GSR and GCK pins can be used for general purpose I/O. 5/20/06 3.0 Moved T specification values from MIN column to MAX column, page 7. CONFIG 02/15/07 3.1 Corrections to timing parameters t , t , t , t , t , t , t , t , t , AOI PSUD PSU1 PSU2 PHD PCO POE PAO AO t , t , t , and f for -6 speed grade. Corrections to t , t , and t SUEC CW CDRSU TOGGLE PSUD CW CDRSU for the -7 speed grade. Values now match the software. There were no changes to silicon or characterization. Change to V specification for 2.5V and 1.8V LVCMOS. IH 03/08/07 3.2 Fixed typo in note for V for LVCMOS18; removed note for V for LVCMOS33. IL IL DS094 (v3.2) March 8, 2007 www.xilinx.com 23 Product Specification