Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 AM335x Sitara™ Processors 1 Device Overview 1.1 Features 1 • Upto1-GHz Sitara™ARM®Cortex®-A832‑Bit PROFIBUS,PROFINET,EtherNet/IP™,and RISCProcessor More – NEON™SIMDCoprocessor – TwoProgrammableReal-TimeUnits(PRUs) – 32KBofL1Instructionand32KBofDataCache – 32-BitLoad/StoreRISCProcessorCapable WithSingle-ErrorDetection(Parity) ofRunningat200MHz – 256KBofL2CacheWithErrorCorrectingCode – 8KBofInstructionRAMWithSingle-Error (ECC) Detection(Parity) – 176KBofOn-ChipBootROM – 8KBofDataRAMWithSingle-ErrorDetection (Parity) – 64KBofDedicatedRAM – Single-Cycle32-BitMultiplierWith64-Bit – EmulationandDebug-JTAG Accumulator – InterruptController(upto128Interrupt – EnhancedGPIOModuleProvidesShift- Requests) In/OutSupportandParallelLatchonExternal • On-ChipMemory(SharedL3RAM) Signal – 64KBofGeneral-PurposeOn-ChipMemory – 12KBofSharedRAMWithSingle-Error Controller(OCMC)RAM Detection(Parity) – AccessibletoAllMasters – Three120-ByteRegisterBanksAccessibleby – SupportsRetentionforFastWakeup EachPRU • ExternalMemoryInterfaces(EMIF) – InterruptController(INTC)forHandlingSystem – mDDR(LPDDR),DDR2,DDR3,DDR3L InputEvents Controller: – LocalInterconnectBusforConnectingInternal – mDDR:200-MHzClock(400-MHzDataRate) andExternalMasterstotheResourcesInside – DDR2:266-MHzClock(532-MHzDataRate) thePRU-ICSS – DDR3:400-MHzClock(800-MHzDataRate) – PeripheralsInsidethePRU-ICSS: – DDR3L:400-MHzClock(800-MHzData – OneUARTPortWithFlowControlPins, Rate) Supportsupto12Mbps – 16-BitDataBus – OneEnhancedCapture(eCAP)Module – 1GBofTotalAddressableSpace – TwoMIIEthernetPortsthatSupportIndustrial – SupportsOnex16orTwox8MemoryDevice Ethernet,suchasEtherCAT Configurations – OneMDIOPort – General-PurposeMemoryController(GPMC) • Power,Reset,andClockManagement(PRCM) – Flexible8-Bitand16-BitAsynchronous Module MemoryInterfaceWithuptoSevenChip – ControlstheEntryandExitofStand-Byand Selects(NAND,NOR,Muxed-NOR,SRAM) Deep-SleepModes – UsesBCHCodetoSupport4-,8-,or16-Bit – ResponsibleforSleepSequencing,Power ECC DomainSwitch-OffSequencing,Wake-Up – UsesHammingCodetoSupport1-BitECC Sequencing,andPowerDomainSwitch-On – ErrorLocatorModule(ELM) Sequencing – UsedinConjunctionWiththeGPMCto – Clocks LocateAddressesofDataErrorsfrom – Integrated15-to35-MHzHigh-Frequency SyndromePolynomialsGeneratedUsinga OscillatorUsedtoGenerateaReference BCHAlgorithm ClockforVariousSystemandPeripheral – Supports4-,8-,and16-Bitper512-Byte Clocks BlockErrorLocationBasedonBCH – SupportsIndividualClockEnableandDisable Algorithms ControlforSubsystemsandPeripheralsto • ProgrammableReal-TimeUnitSubsystemand FacilitateReducedPowerConsumption IndustrialCommunicationSubsystem(PRU-ICSS) – FiveADPLLstoGenerateSystemClocks – SupportsProtocolssuchasEtherCAT®, (MPUSubsystem,DDRInterface,USBand 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Peripherals[MMCandSD,UART,SPI,I2C], – SupportsDigitalAudioInterfaceTransmission L3,L4,Ethernet,GFX[SGX530],LCDPixel (SPDIF,IEC60958-1,andAES-3Formats) Clock) – FIFOBuffersforTransmitandReceive(256 – Power Bytes) – TwoNonswitchablePowerDomains(Real- – UptoSixUARTs TimeClock[RTC],Wake-UpLogic – AllUARTsSupportIrDAandCIRModes [WAKEUP]) – AllUARTsSupportRTSandCTSFlow – ThreeSwitchablePowerDomains(MPU Control Subsystem[MPU], SGX530[GFX], – UART1SupportsFullModemControl PeripheralsandInfrastructure[PER]) – UptoTwoMasterandSlaveMcSPISerial – ImplementsSmartReflex™Class2BforCore Interfaces VoltageScalingBasedOnDieTemperature, – UptoTwoChipSelects ProcessVariation,andPerformance – Upto48MHz (AdaptiveVoltageScaling[AVS]) – UptoThreeMMC,SD,SDIOPorts – DynamicVoltageFrequencyScaling(DVFS) – 1-,4-and8-BitMMC,SD,SDIOModes • Real-TimeClock(RTC) – MMCSD0hasDedicatedPowerRailfor1.8‑V – Real-TimeDate(Day-Month-Year-DayofWeek) or3.3-VOperation andTime(Hours-Minutes-Seconds)Information – Upto48-MHzDataTransferRate – Internal32.768-kHzOscillator,RTCLogicand 1.1-VInternalLDO – SupportsCardDetectandWriteProtect – IndependentPower-on-Reset – CompliesWithMMC4.3,SD,SDIO2.0 (RTC_PWRONRSTn)Input Specifications – DedicatedInputPin(EXT_WAKEUP)for – UptoThreeI2CMasterandSlaveInterfaces ExternalWakeEvents – StandardMode(upto100kHz) – ProgrammableAlarmCanbeUsedtoGenerate – FastMode(upto400kHz) InternalInterruptstothePRCM(forWakeup)or – UptoFourBanksofGeneral-PurposeI/O Cortex-A8(forEventNotification) (GPIO)Pins – ProgrammableAlarmCanbeUsedWith – 32GPIOPinsperBank(MultiplexedWith ExternalOutput(PMIC_POWER_EN)toEnable OtherFunctionalPins) thePowerManagementICtoRestoreNon-RTC – GPIOPinsCanbeUsedasInterruptInputs PowerDomains (uptoTwoInterruptInputsperBank) • Peripherals – UptoThreeExternalDMAEventInputsthatcan – UptoTwoUSB2.0High-SpeedDRD(Dual- AlsobeUsedasInterruptInputs RoleDevice)PortsWithIntegratedPHY – Eight32-BitGeneral-PurposeTimers – UptoTwoIndustrialGigabitEthernetMACs(10, – DMTIMER1isa1-msTimerUsedfor 100,1000Mbps) OperatingSystem(OS)Ticks – IntegratedSwitch – DMTIMER4–DMTIMER7arePinnedOut – EachMACSupportsMII,RMII,RGMII,and – OneWatchdogTimer MDIOInterfaces – SGX5303DGraphicsEngine – EthernetMACsandSwitchCanOperate – Tile-BasedArchitectureDeliveringupto20 IndependentofOtherFunctions MillionPolygonsperSecond – IEEE1588v1PrecisionTimeProtocol(PTP) – UniversalScalableShaderEngine(USSE)is – UptoTwoController-AreaNetwork(CAN)Ports aMultithreadedEngineIncorporatingPixel – SupportsCANVersion2PartsAandB andVertexShaderFunctionality – UptoTwoMultichannelAudioSerialPorts – AdvancedShaderFeatureSetinExcessof (McASPs) MicrosoftVS3.0,PS3.0,andOGL2.0 – TransmitandReceiveClocksupto50MHz – IndustryStandardAPISupportofDirect3D – UptoFourSerialDataPinsperMcASPPort Mobile,OGL-ES1.1and2.0,andOpenMax WithIndependentTXandRXClocks – Fine-GrainedTaskSwitching,Load – SupportsTimeDivisionMultiplexing(TDM), Balancing,andPowerManagement Inter-ICSound(I2S),andSimilarFormats – AdvancedGeometryDMA-DrivenOperation forMinimumCPUInteraction 2 DeviceOverview Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 – ProgrammableHigh-QualityImageAnti- – UptoThree32-BitEnhancedQuadrature Aliasing EncoderPulse(eQEP)Modules – FullyVirtualizedMemoryAddressingforOS • DeviceIdentification OperationinaUnifiedMemoryArchitecture – ContainsElectricalFuseFarm(FuseFarm)of – LCDController WhichSomeBitsareFactoryProgrammable – Upto24-BitDataOutput;8BitsperPixel – ProductionID (RGB) – DevicePartNumber(UniqueJTAGID) – Resolutionupto2048 ×2048(With – DeviceRevision(ReadablebyHostARM) Maximum126-MHzPixelClock) • DebugInterfaceSupport – IntegratedLCDInterfaceDisplayDriver – JTAGandcJTAGforARM(Cortex-A8and (LIDD)Controller PRCM),PRU-ICSSDebug – IntegratedRasterController – SupportsDeviceBoundaryScan – IntegratedDMAEnginetoPullDatafromthe – SupportsIEEE1500 ExternalFrameBufferWithoutBurdeningthe • DMA ProcessorviaInterruptsoraFirmwareTimer – On-ChipEnhancedDMAController(EDMA)has – 512-WordDeepInternalFIFO ThreeThird-PartyTransferControllers(TPTCs) – SupportedDisplayTypes: andOneThird-PartyChannelController – CharacterDisplays-UsesLIDDController (TPCC),WhichSupportsupto64 toProgramtheseDisplays ProgrammableLogicalChannelsandEight – PassiveMatrixLCDDisplays-UsesLCD QDMAChannels.EDMAisUsedfor: RasterDisplayControllertoProvide – TransferstoandfromOn-ChipMemories TimingandDataforConstantGraphics – TransferstoandfromExternalStorage RefreshtoaPassiveDisplay (EMIF,GPMC,SlavePeripherals) – ActiveMatrixLCDDisplays-Uses • Inter-ProcessorCommunication(IPC) ExternalFrameBufferSpaceandthe – IntegratesHardware-BasedMailboxforIPCand InternalDMAEnginetoDriveStreaming SpinlockforProcessSynchronizationBetween DatatothePanel Cortex-A8,PRCM,andPRU-ICSS – 12-BitSuccessiveApproximationRegister – MailboxRegistersthatGenerateInterrupts (SAR)ADC – FourInitiators(Cortex-A8,PRCM,PRU0, – 200KSamplesperSecond PRU1) – InputcanbeSelectedfromanyoftheEight – Spinlockhas128Software-AssignedLock AnalogInputsMultiplexedThroughan8:1 Registers AnalogSwitch • Security – CanbeConfiguredtoOperateasa4-Wire,5- – CryptoHardwareAccelerators(AES,SHA, Wire,or8-WireResistiveTouchScreen RNG) Controller(TSC)Interface – SecureBoot(optional;requirescustompart – UptoThree32-BiteCAPModules engagementwithTI) – ConfigurableasThreeCaptureInputsor • BootModes ThreeAuxiliaryPWMOutputs – BootModeisSelectedThroughBoot – UptoThreeEnhancedHigh-ResolutionPWM ConfigurationPinsLatchedontheRisingEdge Modules(eHRPWMs) ofthePWRONRSTnResetInputPin – Dedicated16-BitTime-BaseCounterWith • Packages: TimeandFrequencyControls – 298-PinS-PBGA-N298ViaChannelPackage – ConfigurableasSixSingle-Ended,SixDual- (ZCESuffix),0.65-mmBallPitch EdgeSymmetric,orThreeDual-Edge AsymmetricOutputs – 324-PinS-PBGA-N324Package (ZCZSuffix),0.80-mmBallPitch Copyright©2011–2020,TexasInstrumentsIncorporated DeviceOverview 3 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 1.2 Applications • GamingPeripherals • ConnectedVendingMachines • HomeandIndustrialAutomation • WeighingScales • ConsumerMedicalAppliances • EducationalConsoles • Printers • AdvancedToys • SmartTollSystems 1.3 Description The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available freeofchargefromTI. The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief descriptionofeachfollows: The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows: The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects. The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor coresofSoC. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE AM3359ZCZ NFBGA(324) 15.0mm×15.0mm AM3358ZCZ NFBGA(324) 15.0mm×15.0mm AM3357ZCZ NFBGA(324) 15.0mm×15.0mm AM3356ZCZ,AM3356ZCE NFBGA(324),NFBGA(298) 15.0mm×15.0mm,13.0mm×13.0mm AM3354ZCZ,AM3354ZCE NFBGA(324),NFBGA(298) 15.0mm×15.0mm,13.0mm×13.0mm AM3352ZCZ,AM3352ZCE NFBGA(324),NFBGA(298) 15.0mm×15.0mm,13.0mm×13.0mm AM3351ZCE NFBGA(298) 13.0mm×13.0mm (1) Formoreinformation,seeSection9,Mechanical,Packaging,andOrderableInformation. 4 DeviceOverview Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 1.4 Functional Block Diagram Figure1-1showstheAM335xmicroprocessorfunctionalblockdiagram. Graphics Display ARM® Cortex®-A8 PowerVR 24-bit LCD controller Up to 1 Ghz SGX Touch screen controller 3D GFX PRU-ICSS 32KB and 32KB L1 + SED Crypto EtherCAT, PROFINET, 256KB L2 + ECC 64KB EtherNet/IP, shared 176KB ROM 64KB RAM and more RAM L3 and L4 interconnect Serial System Parallel eCAPx3 UARTx6 eDMA MMC, SD and ADC (8 channel) SPI x2 Timers x8 SDIO x3 12-bit SAR I2C x3 WDT GPIO McASPx2 RTC JTAG (4 channel) eHRPWM x3 CAN x2 Crystal eQEPx3 (Ver. 2Aand B) Oscillator x2 PRCM USB 2.0 HS Memory interface DRD + PHYx2 mDDR(LPDDR), DDR2, DDR3, DDR3L EMAC (2-port) 10M, 100M, 1G (16-bit; 200, 266, 400, 400 MHz) IEEE 1588v1, and switch (MII, RMII, RGMII) NAND and NOR (16-bit ECC) Figure1-1.AM335xFunctionalBlockDiagram Copyright©2011–2020,TexasInstrumentsIncorporated DeviceOverview 5 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table of Contents 1 DeviceOverview......................................... 1 7.2 RecommendedClockandControlSignalTransition ............................................ .............................................. Behavior 115 1.1 Features 1 .................................... ........................................... 7.3 OPP50 Support 115 1.2 Applications 4 .................... ............................................ 7.4 ControllerAreaNetwork(CAN) 116 1.3 Description 4 ........................................... ........................... 7.5 DMTimer 117 1.4 FunctionalBlockDiagram 5 2 Revision History......................................... 7 7.6 EthernetMediaAccessController(EMAC)and .............................................. Switch 118 3 DeviceComparison ..................................... 8 ........................ 7.7 ExternalMemoryInterfaces 126 ..................................... 3.1 RelatedProducts 9 7.8 I2C.................................................. 189 4 TerminalConfigurationandFunctions............ 10 .................. 7.9 JTAGElectricalDataandTiming 190 ......................................... 4.1 PinDiagram 10 ............................ 7.10 LCDController(LCDC) 192 ........................................ 4.2 PinAttributes 18 .......... 7.11 MultichannelAudioSerialPort(McASP) 208 .................................. 4.3 SignalDescriptions 50 ........ 7.12 MultichannelSerialPortInterface(McSPI) 213 5 Specifications........................................... 79 ................. 7.13 MultimediaCard(MMC)Interface 219 ......................... 5.1 AbsoluteMaximumRatings 79 7.14 ProgrammableReal-TimeUnitSubsystemand ........................................ 5.2 ESDRatings 80 IndustrialCommunicationSubsystem(PRU-ICSS) 222 ............................. 5.3 Power-OnHours(POH) 81 7.15 UniversalAsynchronousReceiverTransmitter 5.4 OperatingPerformancePoints(OPPs)............. 81 (UART)............................................. 231 5.5 RecommendedOperatingConditions............... 84 8 DeviceandDocumentationSupport.............. 234 5.6 PowerConsumptionSummary...................... 86 8.1 Device Nomenclature.............................. 234 5.7 DCElectricalCharacteristics........................ 88 8.2 ToolsandSoftware................................ 235 ............................ 5.8 ThermalResistanceCharacteristicsforZCEand 8.3 DocumentationSupport 239 ZCZ Packages...................................... 92 8.4 RelatedLinks...................................... 242 5.9 ExternalCapacitors................................. 93 8.5 SupportResources................................ 242 5.10 TouchScreenControllerandAnalog-to-Digital ........................................ 8.6 Trademarks 243 ................... SubsystemElectricalParameters 96 ................... 8.7 ElectrostaticDischargeCaution 243 6 PowerandClocking................................... 98 ............................................ 8.8 Glossary 243 ...................................... 6.1 PowerSupplies 98 9 Mechanical,Packaging,andOrderable ................................ 6.2 ClockSpecifications 106 Information............................................. 244 7 PeripheralInformationandTimings.............. 115 ........................................ 9.1 ViaChannel 244 ............................. 7.1 ParameterInformation 115 ............................. 9.2 PackagingInformation 244 6 TableofContents Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromDecember1,2018toMarch31,2020(fromKRevision(December2018)toLRevision) Page • ChangedIEEE1588v2featuretoIEEE1588v1. ................................................................................ 2 • UpdatedSecureBootfeaturedescription. ........................................................................................ 3 • UpdatedAM335xFunctionalBlockDiagram. .................................................................................... 5 • AddedU16tormii2_crs_dvSignalintheGEMAC_CPSW/RMII2SignalsDescriptiontable.............................. 71 • UpdatedADCClockFrequencyintheTSC_ADCElectricalParameterstable............................................. 97 • UpdatedDCANTimingConditionstable. ...................................................................................... 116 • UpdatedDMTimerTimingConditionstable. .................................................................................. 117 • UpdatedSwitchingCharacteristicsforMDIO_DATA.......................................................................... 119 • UpdatedMDIO_DATATiming-OutputModeimage.......................................................................... 119 • AddedTransitiontime,RDandTransitiontime,RX_CTLtoTimingRequirementsforRGMII[x]_RD[3:0],and RGMII[x]_RCTL-RGMIIMode. ................................................................................................. 124 • UpdatedGPMCandNORFlash—SynchronousBurstRead—4x16-Bit(GpmcFCLKDivider=0)image. ............ 132 • UpdatedGPMCandMultiplexedNORFlash—SynchronousBurstWriteimage. ........................................ 134 • UpdatedJTAGTimingConditionstable. ....................................................................................... 191 • UpdatedMMC[x]_CLK(Output)Timingimage................................................................................. 220 • UpdatedPRU-ICSSMDIOSwitchingCharacteristics-MDIO_DATA...................................................... 228 • UpdatedPRU-ICSSMDIO_DATATiming–OutputModeimage........................................................... 228 Copyright©2011–2020,TexasInstrumentsIncorporated RevisionHistory 7 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 3 Device Comparison Table3-1liststhefeaturessupportedacrossdifferentAM335xdevices. Table3-1.DeviceFeaturesComparison FUNCTION AM3351 AM3352 AM3354 AM3356 AM3357 AM3358 AM3359 ARMCortex-A8 Yes Yes Yes Yes Yes Yes Yes 300MHz 600MHz 300MHz 300MHz 600MHz Frequency(1) 300MHz 600MHz 800MHz 600MHz 600MHz 800MHz 800MHz 600MHz 800MHz 1000MHz 800MHz 800MHz 1000MHz 1000MHz 600 1200 600 600 1200 MIPS(2) 600 1200 1600 1200 1200 1600 1600 1200 1600 2000 1600 1600 2000 2000 On-chipL1cache 64KB 64KB 64KB 64KB 64KB 64KB 64KB On-chipL2cache 256KB 256KB 256KB 256KB 256KB 256KB 256KB Graphicsaccelerator — — 3D — — 3D 3D (SGX530) Crypto Crypto Crypto Crypto Crypto Crypto Crypto Hardwareacceleration accelerator accelerator accelerator accelerator accelerator accelerator accelerator Features includingbasic Programmablereal-time Features Features Features Industrial unitsubsystemand includingall includingbasic includingall — — — protocols; industrialcommunication Industrial Industrial Industrial ZCE:Limited subsystem(PRU-ICSS) protocols protocols protocols PRUI/Ospinned out On-chipmemory 128KB 128KB 128KB 128KB 128KB 128KB 128KB Displayoptions LCD LCD LCD LCD LCD LCD LCD 116-bit(GPMC, 116-bit(GPMC, 116-bit(GPMC, 116-bit(GPMC, 116-bit(GPMC, 116-bit(GPMC, 116-bit(GPMC, NANDflash, NANDflash, NANDflash, NANDflash, NANDflash, NANDflash, NANDflash, General-purposememory NORflash, NORflash, NORflash, NORflash, NORflash, NORflash, NORflash, SRAM) SRAM) SRAM) SRAM) SRAM) SRAM) SRAM) 116-bit 116-bit 116-bit 116-bit 116-bit 116-bit 116-bit DRAM(3) (LPDDR-400, (LPDDR-400, (LPDDR-400, (LPDDR-400, (LPDDR-400, (LPDDR-400, (LPDDR-400, DDR2-532, DDR2-532, DDR2-532, DDR2-532, DDR2-532, DDR2-532, DDR2-532, DDR3-800) DDR3-800) DDR3-800) DDR3-800) DDR3-800) DDR3-800) DDR3-800) NoZCE NoZCE NoZCE ZCE:1port ZCE:1port ZCE:1port Universalserialbus(USB) ZCE:1port Available Available Available ZCZ:2ports ZCZ:2ports ZCZ:2ports ZCZ:2ports ZCZ:2ports ZCZ:2ports 10/100/1000 10/100/1000 10/100/1000 Ethernetmediaaccess 10/100/1000 10/100/1000 10/100/1000 10/100/1000 NoZCE NoZCE NoZCE controller(EMAC)with2- ZCE:1port ZCE:1port ZCE:1port ZCE:1port Available Available Available portswitch ZCZ:2ports ZCZ:2ports ZCZ:2ports ZCZ:2ports ZCZ:2ports ZCZ:2ports Multimediacard(MMC) 3 3 3 3 3 3 3 Controller-areanetwork — 2 2 2 2 2 2 (CAN) Universalasynchronous receiverandtransmitter 6 6 6 6 6 6 6 (UART) Analog-to-digitalconverter 8-ch12-bit 8-ch12-bit 8-ch12-bit 8-ch12-bit 8-ch12-bit 8-ch12-bit 8-ch12-bit (ADC) Enhancedhigh-resolution PWMmodules 3 3 3 3 3 3 3 (eHRPWM) Enhancedcapture 3 3 3 3 3 3 3 modules(eCAP) Enhancedquadrature 3 3 3 3 3 3 3 encoderpulse(eQEP) Real-timeclock(RTC) 1 1 1 1 1 1 1 Inter-integratedcircuit 3 3 3 3 3 3 3 (I2C) 8 DeviceComparison Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table3-1.DeviceFeaturesComparison(continued) FUNCTION AM3351 AM3352 AM3354 AM3356 AM3357 AM3358 AM3359 Multichannelaudioserial 2 2 2 2 2 2 2 port(McASP) Multichannelserialport 2 2 2 2 2 2 2 interface(McSPI) Enhanceddirectmemory 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch access(EDMA) Input/output(I/O)supply 1.8V,3.3V 1.8V,3.3V 1.8V,3.3V 1.8V,3.3V 1.8V,3.3V 1.8V,3.3V 1.8V,3.3V -40to125°C(4) –40to105°C –40to105°C –40to105°C Operatingtemperature 0to90°C –40to105°C –40to105°C –40to105°C –40to90°C –40to90°C –40to90°C range –40to105°C –40to90°C –40to90°C –40to90°C 0to90°C 0to90°C 0to90°C 0to90°C DEV_FEATUREregister value(5) 0x00FC0302 0x00FC0382 0x20FC0382 0x00FD0383 0x00FF0383 0x20FD0383 0x20FF0383 (1) Frequencieslistedcorrespondtosiliconrevision2.x.Earliersiliconrevisionssupport275MHz,500MHz,600MHz,and720MHz. (2) MIPSlistedcorrespondtosiliconrevision2.x.Earliersiliconrevisionssupport560,1000,1200,and1440. (3) DRAMspeedslistedaredatarates. (4) Industrialextendedtemperatureonlysupportedfor300-MHzand600-MHzfrequencies. (5) FormoredetailsabouttheDEV_FEATUREregister,seetheAM335xTRM. 3.1 Related Products Forinformationaboutotherdevicesinthisfamilyofproducts,seethefollowinglinks: SitaraProcessors Scalable processors based on ARM Cortex-A cores with flexible peripherals, connectivityandunifiedsoftwaresupport –perfectforsensorstoservers. TI'sARMCortex-A8Advantage The ARM Cortex-A8 core is highly-optimized by ARM for performance and power efficiency. With the ability to scale in speed from 300 MHz to 1.35 GHz, the ARM Cortex-A8-based processor can meet the requirements for power optimized devices with a power budget of less than the Cortex-A8 core a dual-issue superscalar, achieving twice the instructionsexecutedperclockcycleat2DMIPS/MHz. AM335xSitaraProcessors Scalable ARM Cortex-A8-based core from 300 MHz up to 1 GHz, 3D graphics option for enhanced user interface, dual-core PRU-ICSS for industrial Ethernet protocolsandpositionfeedbackcontrol,andpremiumsecurebootoption. CompanionProductsforAM335xSitaraProcessors Review products that are frequently purchased or usedwiththisproduct. TIDesignsforAM335xSitaraProcessors The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designsat ti.com/tidesigns. Copyright©2011–2020,TexasInstrumentsIncorporated DeviceComparison 9 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagram NOTE The terms 'ball', 'pin', and 'terminal' are used interchangeably throughout the document. An attemptismadetouse'ball'onlywhenreferringtothephysicalpackage. 4.1.1 ZCE Package Pin Maps (Top View) The pin maps that follow show the pin assignments on the ZCE package in three sections (left, middle, andright). 10 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-1.ZCEPinMap[SectionLeft-TopView] A B C D E F 19 VSS I2C0_SCL UART1_TXD UART1_RTSn UART0_RXD UART0_CTSn 18 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RXD ECAP0_IN_PWM0_OUT UART0_RTSn 17 SPI0_CS0 SPI0_D1 EXTINTn XXXX UART1_CTSn UART0_TXD 16 WARMRSTn SPI0_CS1 XXXX XXXX XXXX VDDS 15 EMU0 XDMA_EVENT_INTR1 XDMA_EVENT_INTR0 XXXX PWRONRSTn XXXX 14 TDO TCK TMS EMU1 XXXX VDDSHV6 13 TRSTn TDI CAP_VBB_MPU CAP_VDD_SRAM_MPU VDDSHV6 VSS 12 AIN7 AIN5 VDDS_SRAM_MPU_BB VDDS VDDSHV6 VSS 11 AIN1 AIN3 XXXX XXXX VDDSHV6 VDD_CORE 10 AIN6 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VSS VSS XXXX 9 VREFP VREFN XXXX XXXX VSS VDD_CORE 8 AIN2 AIN0 AIN4 VSSA_ADC VSS VSS 7 RTC_KALDO_ENn RTC_PWRONRSTn PMIC_POWER_EN VDDA_ADC VSS VSS 6 RTC_XTALIN RESERVED VDDS_RTC CAP_VDD_RTC XXXX VSS 5 RTC_XTALOUT EXT_WAKEUP VDDS_PLL_DDR XXXX DDR_A4 XXXX 4 DDR_WEn DDR_BA2 XXXX XXXX XXXX DDR_A12 3 DDR_BA0 DDR_A3 DDR_A8 XXXX DDR_A15 DDR_A0 2 DDR_A5 DDR_A9 DDR_CK DDR_A7 DDR_A10 DDR_RASn 1 VSS DDR_A6 DDR_CKn DDR_A2 DDR_BA1 DDR_CASn Pin map section location Left Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com ZCEPinMap[SectionMiddle-TopView] G H J K L M 19 MMC0_CLK MMC0_DAT3 MII1_COL MII1_RX_ER MII1_RX_DV MII1_RX_CLK 18 MMC0_DAT0 MMC0_DAT2 MII1_CRS RMII1_REF_CLK MII1_TXD0 MII1_TXD1 17 MMC0_CMD MMC0_DAT1 XXXX MII1_TX_EN XXXX MII1_TXD3 16 USB0_DRVVBUS VDDS_PLL_MPU XXXX VDD_CORE XXXX VDDS 15 VDDSHV4 VDDSHV4 VSS VDD_CORE VSS VDDSHV5 14 XXXX VDDSHV4 VSS XXXX VSS VDDSHV5 13 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE 12 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE 11 VDD_CORE VSS VSS VSS VSS VSS 10 XXXX VSS XXXX XXXX XXXX VSS 9 VDD_CORE VSS VSS VSS VSS VSS 8 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE 7 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE 6 XXXX VDDS_DDR VSS XXXX VSS VDDS_DDR 5 VDDS_DDR VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR 4 DDR_A11 DDR_VREF XXXX VDDS_DDR XXXX DDR_D11 3 DDR_CKE DDR_A14 XXXX DDR_DQM1 XXXX DDR_D10 2 DDR_RESETn DDR_CSn0 DDR_A1 DDR_D8 DDR_DQSn1 DDR_D12 1 DDR_ODT DDR_A13 DDR_VTP DDR_D9 DDR_DQS1 DDR_D13 Pin map section location Middle 12 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 ZCEPinMap[SectionRight-TopView] N P R T U V W 19 MII1_TX_CLK MII1_RXD1 MDC USB0_VBUS USB0_DP USB0_ID VSS 18 MII1_TXD2 MII1_RXD0 VDDA3P3V_USB0 USB0_CE USB0_DM GPMC_BEn1 GPMC_WPn 17 MII1_RXD3 MDIO VDDA1P8V_USB0 XXXX GPMC_CSn3 GPMC_AD15 GPMC_AD14 16 MII1_RXD2 VSSA_USB XXXX XXXX XXXX GPMC_CLK GPMC_AD9 15 VDDSHV5 XXXX GPMC_WAIT0 XXXX GPMC_CSn2 GPMC_AD8 GPMC_AD7 14 XXXX VSS XXXX VDDS GPMC_AD6 GPMC_CSn1 GPMC_AD5 13 XXXX VSS VDDSHV1 GPMC_AD13 GPMC_AD12 GPMC_AD4 GPMC_AD3 12 VSS VSS VDDSHV1 GPMC_AD10 GPMC_AD11 GPMC_AD2 XTALOUT 11 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX VSS_OSC XTALIN 10 XXXX XXXX VSS VSS VDDS_OSC GPMC_ADVn_ALE GPMC_AD0 9 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX GPMC_AD1 GPMC_OEn_REn 8 VSS VSS VDDSHV1 VDDS_PLL_CORE_LCD GPMC_WEn GPMC_BEn0_CLE GPMC_CSn0 7 XXXX VSS VDDSHV6 LCD_HSYNC LCD_VSYNC LCD_DATA15 LCD_AC_BIAS_EN 6 XXXX VDDSHV6 XXXX VDDS LCD_DATA13 LCD_DATA12 LCD_DATA14 5 VDDS_DDR XXXX VPP XXXX LCD_DATA10 LCD_DATA11 LCD_PCLK 4 DDR_D0 DDR_D1 XXXX XXXX XXXX LCD_DATA8 LCD_DATA9 3 DDR_DQM0 DDR_D4 DDR_D7 XXXX LCD_DATA7 LCD_DATA6 LCD_DATA5 2 DDR_D14 DDR_D2 DDR_DQSn0 DDR_D6 LCD_DATA1 LCD_DATA3 LCD_DATA4 1 DDR_D15 DDR_D3 DDR_DQS0 DDR_D5 LCD_DATA0 LCD_DATA2 VSS Pin map section location Right Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 13 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.1.2 ZCZ Package Pin Maps (Top View) The pin maps that follow show the pin assignments on the ZCZ package in three sections (left, middle, andright). 14 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 ZCZPinMap[SectionLeft-TopView] A B C D E F 18 VSS EXTINTn ECAP0_IN_PWM0_OUT UART1_CTSn UART0_CTSn MMC0_DAT2 17 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RTSn UART0_RTSn MMC0_DAT3 16 SPI0_CS0 SPI0_D1 I2C0_SCL UART1_RXD UART0_TXD USB0_DRVVBUS 15 XDMA_EVENT_INTR0 PWRONRSTn SPI0_CS1 UART1_TXD UART0_RXD USB1_DRVVBUS 14 MCASP0_AHCLKX EMU1 EMU0 XDMA_EVENT_INTR1 VDDS VDDSHV6 13 MCASP0_ACLKX MCASP0_FSX MCASP0_FSR MCASP0_AXR1 VDDSHV6 VDD_MPU 12 TCK MCASP0_ACLKR MCASP0_AHCLKR MCASP0_AXR0 VDDSHV6 VDD_MPU 11 TDO TDI TMS CAP_VDD_SRAM_MPU VDDSHV6 VDD_MPU 10 WARMRSTn TRSTn CAP_VBB_MPU VDDS_SRAM_MPU_BB VDDSHV6 VDD_MPU 9 VREFN VREFP AIN7 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDS 8 AIN6 AIN5 AIN4 VDDA_ADC VSSA_ADC VSS 7 AIN3 AIN2 AIN1 VDDS_RTC VDDS_PLL_DDR VDD_CORE 6 RTC_XTALIN AIN0 PMIC_POWER_EN CAP_VDD_RTC VDDS VDD_CORE 5 VSS_RTC RTC_PWRONRSTn EXT_WAKEUP DDR_A6 VDDS_DDR VDDS_DDR 4 RTC_XTALOUT RTC_KALDO_ENn DDR_BA0 DDR_A8 DDR_A2 DDR_A10 3 RESERVED DDR_BA2 DDR_A3 DDR_A15 DDR_A12 DDR_A0 2 VDD_MPU_MON DDR_WEn DDR_A4 DDR_CK DDR_A7 DDR_A11 1 VSS DDR_A5 DDR_A9 DDR_CKn DDR_BA1 DDR_CASn Pin map section location Left Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 15 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com ZCZPinMap[SectionMiddle-TopView] G H J K L M 18 MMC0_CMD RMII1_REF_CLK MII1_TXD3 MII1_TX_CLK MII1_RX_CLK MDC 17 MMC0_CLK MII1_CRS MII1_RX_DV MII1_TXD0 MII1_RXD3 MDIO 16 MMC0_DAT0 MII1_COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0 15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE 14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB 13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE 12 VSS VSS VDD_CORE VDD_CORE VSS VSS 11 VSS VDD_CORE VSS VSS VSS VDD_CORE 10 VDD_CORE VSS VSS VSS VSS VSS 9 VSS VSS VSS VSS VDD_CORE VSS 8 VSS VSS VSS VDD_CORE VDD_CORE VSS 7 VDD_CORE VSS VSS VSS VDD_CORE VSS 6 VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS 5 VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP 4 DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1 3 DDR_CKE DDR_A13 DDR_VTP DDR_D11 DDR_D13 DDR_D0 2 DDR_RESETn DDR_CSn0 DDR_DQM1 DDR_D10 DDR_DQSn1 DDR_DQM0 1 DDR_ODT DDR_A1 DDR_D8 DDR_D9 DDR_DQS1 DDR_D15 Pin map section location Middle 16 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 ZCZPinMap[SectionRight-TopView] N P R T U V 18 USB0_DM USB1_CE USB1_DM USB1_VBUS GPMC_BEn1 VSS 17 USB0_DP USB1_ID USB1_DP GPMC_WAIT0 GPMC_WPn GPMC_A11 16 VDDA1P8V_USB0 USB0_ID VDDA1P8V_USB1 GPMC_A10 GPMC_A9 GPMC_A8 15 VDDA3P3V_USB0 USB0_VBUS VDDA3P3V_USB1 GPMC_A7 GPMC_A6 GPMC_A5 14 VSSA_USB VDDS GPMC_A4 GPMC_A3 GPMC_A2 GPMC_A1 13 VDD_CORE VDDSHV3 GPMC_A0 GPMC_CSn3 GPMC_AD15 GPMC_AD14 12 VDD_CORE VDDSHV3 GPMC_AD13 GPMC_AD12 GPMC_AD11 GPMC_CLK 11 VSS VDDSHV2 VDDS_OSC GPMC_AD10 XTALOUT VSS_OSC 10 VSS VDDSHV2 VDDS_PLL_CORE_LCD GPMC_AD9 GPMC_AD8 XTALIN 9 VDD_CORE VDDS GPMC_AD6 GPMC_AD7 GPMC_CSn1 GPMC_CSn2 8 VDD_CORE VDDSHV1 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5 7 VSS VDDSHV1 GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD0 GPMC_AD1 6 VDDS VDDSHV6 LCD_AC_BIAS_EN GPMC_BEn0_CLE GPMC_WEn GPMC_CSn0 5 VDDSHV6 VDDSHV6 LCD_HSYNC LCD_DATA15 LCD_VSYNC LCD_PCLK 4 DDR_D5 DDR_D7 LCD_DATA3 LCD_DATA7 LCD_DATA11 LCD_DATA14 3 DDR_D4 DDR_D6 LCD_DATA2 LCD_DATA6 LCD_DATA10 LCD_DATA13 2 DDR_D3 DDR_DQSn0 LCD_DATA1 LCD_DATA5 LCD_DATA9 LCD_DATA12 1 DDR_D2 DDR_DQS0 LCD_DATA0 LCD_DATA4 LCD_DATA8 VSS Pin map section location Right Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 17 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.2 Pin Attributes The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may reference internal signal names when discussing peripheral input and output signals because many of the AM335x package terminals can be multiplexed to one of several peripheral signals. The following table has a Pin Name column that lists all device terminal names and a Signal Name column that lists all internal signal names multiplexed to each terminal which provides a cross reference of internal signal namestoterminalnames.Thistablealsoidentifiesotherimportantterminalcharacteristics. (1) BALLNUMBER:Packageballnumbersassociatedwitheachsignals. (2) PINNAME:Thenameofthepackagepinorterminal. Note:Thetabledoesnottakeintoaccountsubsystemterminalmultiplexingoptions. (3) SIGNALNAME:Thesignalnameforthatpininthemodebeingused. (4) MODE:Multiplexingmodenumber. a. Mode0istheprimarymode;thismeansthatwhenmode0isset,thefunctionmappedontheterminalcorrespondstothenameof theterminal.Thereisalwaysafunctionmappedontheprimarymode.Noticethatprimarymodeisnotnecessarilythedefault mode. Note:Thedefaultmodeisthemodeatthereleaseofthereset;alsoseetheRESETREL.MODEcolumn. b. Modes1to7arepossiblemodesforalternatefunctions.Oneachterminal,somemodesareeffectivelyusedforalternate functions,whilesomemodesarenotusedanddonotcorrespondtoafunctionalconfiguration. (5) TYPE:Signaldirection – I=Input – O=Output – I/O=InputandOutput – D=Opendrain – DS=Differential – A=Analog – PWR=Power – GND=Ground Note:Inthesafe_mode,thebufferisconfiguredinhigh-impedance. (6) BALLRESETSTATE:StateoftheterminalwhiletheactivelowPWRONRSTnterminalislow. – 0:ThebufferdrivesV (pulldownorpullupresistornotactivated) OL 0(PD):ThebufferdrivesV withanactivepulldownresistor OL – 1:ThebufferdrivesV (pulldownorpullupresistornotactivated) OH 1(PU):ThebufferdrivesV withanactivepullupresistor OH – Z:High-impedance – L:High-impedancewithanactivepulldownresistor – H:High-impedancewithanactivepullupresistor (7) BALLRESETREL.STATE:StateoftheterminalaftertheactivelowPWRONRSTnterminaltransitionsfromlowtohigh. – 0:ThebufferdrivesV (pulldownorpullupresistornotactivated) OL 0(PD):ThebufferdrivesV withanactivepulldownresistor OL – 1:ThebufferdrivesV (pulldownorpullupresistornotactivated) OH 1(PU):ThebufferdrivesV withanactivepullupresistor OH – Z:High-impedance. – L:High-impedancewithanactivepulldownresistor – H:High-impedancewithanactivepullupresistor (8) RESETREL.MODE:ThemodeisautomaticallyconfiguredaftertheactivelowPWRONRSTnterminaltransitionsfromlowtohigh. (9) POWER:ThevoltagesupplythatpowerstheI/Obuffersoftheterminal. (10) HYS:Indicatesiftheinputbufferiswithhysteresis. (11) BUFFERSTRENGTH:Drivestrengthoftheassociatedoutputbuffer. (12) PULLUPORPULLDOWNTYPE:Denotesthepresenceofaninternalpulluporpulldownresistor.Pullupandpulldownresistorscan beenabledordisabledviasoftware. (13) I/OCELL:I/Ocellinformation. Note:Configuringtwoterminalstothesameinputsignalisnotsupportedasitcanyieldunexpectedresults.Thiscanbeeasilyprevented withthepropersoftwareconfiguration. 18 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] B8 B6 AIN0 AIN0 0 A(22) Z Z 0 VDDA_ADC/ NA 25 NA Analog VDDA_ADC A11 C7 AIN1 AIN1 0 A(21) Z Z 0 VDDA_ADC/ NA 25 NA Analog VDDA_ADC A8 B7 AIN2 AIN2 0 A(21) Z Z 0 VDDA_ADC/ NA 25 NA Analog VDDA_ADC B11 A7 AIN3 AIN3 0 A(20) Z Z 0 VDDA_ADC/ NA 25 NA Analog VDDA_ADC C8 C8 AIN4 AIN4 0 A(20) Z Z 0 VDDA_ADC/ NA 25 NA Analog VDDA_ADC B12 B8 AIN5 AIN5 0 A Z Z 0 VDDA_ADC/ NA NA NA Analog VDDA_ADC A10 A8 AIN6 AIN6 0 A Z Z 0 VDDA_ADC/ NA NA NA Analog VDDA_ADC A12 C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC/ NA NA NA Analog VDDA_ADC C13 C10 CAP_VBB_MPU CAP_VBB_MPU NA A D6 D6 CAP_VDD_RTC CAP_VDD_RTC NA A B10 D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL D1 E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL B3 C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL E5 C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL A2 B1 DDR_A5 ddr_a5 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL B1 D5 DDR_A6 ddr_a6 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL D2 E2 DDR_A7 ddr_a7 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL C3 D4 DDR_A8 ddr_a8 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL B2 C1 DDR_A9 ddr_a9 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL E2 F4 DDR_A10 ddr_a10 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL G4 F2 DDR_A11 ddr_a11 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 19 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] F4 E3 DDR_A12 ddr_a12 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL H1 H3 DDR_A13 ddr_a13 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL H3 H4 DDR_A14 ddr_a14 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL E3 D3 DDR_A15 ddr_a15 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL A3 C4 DDR_BA0 ddr_ba0 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL E1 E1 DDR_BA1 ddr_ba1 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL B4 B3 DDR_BA2 ddr_ba2 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL F1 F1 DDR_CASn ddr_casn 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL C2 D2 DDR_CK ddr_ck 0 O L 0 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL G3 G3 DDR_CKE ddr_cke 0 O L 0 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL C1 D1 DDR_CKn ddr_nck 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL H2 H2 DDR_CSn0 ddr_csn0 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL N4 M3 DDR_D0 ddr_d0 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL P4 M4 DDR_D1 ddr_d1 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL P2 N1 DDR_D2 ddr_d2 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL P1 N2 DDR_D3 ddr_d3 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL P3 N3 DDR_D4 ddr_d4 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL T1 N4 DDR_D5 ddr_d5 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL T2 P3 DDR_D6 ddr_d6 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL R3 P4 DDR_D7 ddr_d7 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL K2 J1 DDR_D8 ddr_d8 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL K1 K1 DDR_D9 ddr_d9 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL M3 K2 DDR_D10 ddr_d10 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL 20 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] M4 K3 DDR_D11 ddr_d11 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL M2 K4 DDR_D12 ddr_d12 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL M1 L3 DDR_D13 ddr_d13 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL N2 L4 DDR_D14 ddr_d14 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL N1 M1 DDR_D15 ddr_d15 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL N3 M2 DDR_DQM0 ddr_dqm0 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL K3 J2 DDR_DQM1 ddr_dqm1 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL R1 P1 DDR_DQS0 ddr_dqs0 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL L1 L1 DDR_DQS1 ddr_dqs1 0 I/O L Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL R2 P2 DDR_DQSn0 ddr_dqsn0 0 I/O H Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL L2 L2 DDR_DQSn1 ddr_dqsn1 0 I/O H Z 0 VDDS_DDR/ Yes 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL G1 G1 DDR_ODT ddr_odt 0 O L 0 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL F2 G4 DDR_RASn ddr_rasn 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL G2 G2 DDR_RESETn ddr_resetn 0 O L 0 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL H4 J4 DDR_VREF ddr_vref 0 A(18) NA NA NA VDDS_DDR/ NA NA NA Analog VDDS_DDR J1 J3 DDR_VTP ddr_vtp 0 I(19) NA NA NA VDDS_DDR/ NA NA NA Analog VDDS_DDR A4 B2 DDR_WEn ddr_wen 0 O H 1 0 VDDS_DDR/ NA 8 PU/PD LVCMOS/SSTL/ VDDS_DDR HSTL E18 C18 ECAP0_IN_PWM0_OUT eCAP0_in_PWM0_out 0 I/O Z L 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 uart3_txd 1 O spi1_cs1 2 I/O pr1_ecap0_ecap_capin_apwm_o 3 I/O spi1_sclk 4 I/O mmc0_sdwp 5 I xdma_event_intr2 6 I gpio0_7 7 I/O A15 C14 EMU0 EMU0 0 I/O H H 0 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpio3_7 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 21 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] D14 B14 EMU1 EMU1 0 I/O H H 0 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpio3_8 7 I/O C17 B18 EXTINTn nNMI 0 I Z H 0 VDDSHV6/ Yes NA PU/PD LVCMOS VDDSHV6 B5 C5 EXT_WAKEUP EXT_WAKEUP 0 I L Z 0 VDDS_RTC/ Yes NA NA LVCMOS VDDS_RTC NA R13 GPMC_A0 gpmc_a0 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_txen 1 O rgmii2_tctl 2 O rmii2_txen 3 O gpmc_a16 4 O pr1_mii_mt1_clk 5 I ehrpwm1_tripzone_input 6 I gpio1_16 7 I/O NA V14 GPMC_A1 gpmc_a1 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_rxdv 1 I rgmii2_rctl 2 I mmc2_dat0 3 I/O gpmc_a17 4 O pr1_mii1_txd3 5 O ehrpwm0_synco 6 O gpio1_17 7 I/O NA U14 GPMC_A2 gpmc_a2 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_txd3 1 O rgmii2_td3 2 O mmc2_dat1 3 I/O gpmc_a18 4 O pr1_mii1_txd2 5 O ehrpwm1A 6 O gpio1_18 7 I/O NA T14 GPMC_A3 gpmc_a3 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_txd2 1 O rgmii2_td2 2 O mmc2_dat2 3 I/O gpmc_a19 4 O pr1_mii1_txd1 5 O ehrpwm1B 6 O gpio1_19 7 I/O 22 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] NA R14 GPMC_A4 gpmc_a4 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_txd1 1 O rgmii2_td1 2 O rmii2_txd1 3 O gpmc_a20 4 O pr1_mii1_txd0 5 O eQEP1A_in 6 I gpio1_20 7 I/O NA V15 GPMC_A5 gpmc_a5 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_txd0 1 O rgmii2_td0 2 O rmii2_txd0 3 O gpmc_a21 4 O pr1_mii1_rxd3 5 I eQEP1B_in 6 I gpio1_21 7 I/O NA U15 GPMC_A6 gpmc_a6 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_txclk 1 I rgmii2_tclk 2 O mmc2_dat4 3 I/O gpmc_a22 4 O pr1_mii1_rxd2 5 I eQEP1_index 6 I/O gpio1_22 7 I/O NA T15 GPMC_A7 gpmc_a7 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_rxclk 1 I rgmii2_rclk 2 I mmc2_dat5 3 I/O gpmc_a23 4 O pr1_mii1_rxd1 5 I eQEP1_strobe 6 I/O gpio1_23 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 23 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] NA V16 GPMC_A8 gpmc_a8 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_rxd3 1 I rgmii2_rd3 2 I mmc2_dat6 3 I/O gpmc_a24 4 O pr1_mii1_rxd0 5 I mcasp0_aclkx 6 I/O gpio1_24 7 I/O NA U16 GPMC_A9(10) gpmc_a9 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_rxd2 1 I rgmii2_rd2 2 I mmc2_dat7/rmii2_crs_dv 3 I/O gpmc_a25 4 O pr1_mii_mr1_clk 5 I mcasp0_fsx 6 I/O gpio1_25 7 I/O NA T16 GPMC_A10 gpmc_a10 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_rxd1 1 I rgmii2_rd1 2 I rmii2_rxd1 3 I gpmc_a26 4 O pr1_mii1_rxdv 5 I mcasp0_axr0 6 I/O gpio1_26 7 I/O NA V17 GPMC_A11 gpmc_a11 0 O L L 7 NA/VDDSHV3 Yes 6 PU/PD LVCMOS gmii2_rxd0 1 I rgmii2_rd0 2 I rmii2_rxd0 3 I gpmc_a27 4 O pr1_mii1_rxer 5 I mcasp0_axr1 6 I/O gpio1_27 7 I/O W10 U7 GPMC_AD0 gpmc_ad0 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat0 1 I/O gpio1_0 7 I/O V9 V7 GPMC_AD1 gpmc_ad1 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat1 1 I/O gpio1_1 7 I/O 24 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] V12 R8 GPMC_AD2 gpmc_ad2 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat2 1 I/O gpio1_2 7 I/O W13 T8 GPMC_AD3 gpmc_ad3 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat3 1 I/O gpio1_3 7 I/O V13 U8 GPMC_AD4 gpmc_ad4 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat4 1 I/O gpio1_4 7 I/O W14 V8 GPMC_AD5 gpmc_ad5 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat5 1 I/O gpio1_5 7 I/O U14 R9 GPMC_AD6 gpmc_ad6 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat6 1 I/O gpio1_6 7 I/O W15 T9 GPMC_AD7 gpmc_ad7 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 mmc1_dat7 1 I/O gpio1_7 7 I/O V15 U10 GPMC_AD8 gpmc_ad8 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data23 1 O mmc1_dat0 2 I/O mmc2_dat4 3 I/O ehrpwm2A 4 O pr1_mii_mt0_clk 5 I gpio0_22 7 I/O W16 T10 GPMC_AD9 gpmc_ad9 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data22 1 O mmc1_dat1 2 I/O mmc2_dat5 3 I/O ehrpwm2B 4 O pr1_mii0_col 5 I gpio0_23 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 25 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] T12 T11 GPMC_AD10 gpmc_ad10 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data21 1 O mmc1_dat2 2 I/O mmc2_dat6 3 I/O ehrpwm2_tripzone_input 4 I pr1_mii0_txen 5 O gpio0_26 7 I/O U12 U12 GPMC_AD11 gpmc_ad11 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data20 1 O mmc1_dat3 2 I/O mmc2_dat7 3 I/O ehrpwm0_synco 4 O pr1_mii0_txd3 5 O gpio0_27 7 I/O U13 T12 GPMC_AD12 gpmc_ad12 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data19 1 O mmc1_dat4 2 I/O mmc2_dat0 3 I/O eQEP2A_in 4 I pr1_mii0_txd2 5 O pr1_pru0_pru_r30_14 6 O gpio1_12 7 I/O T13 R12 GPMC_AD13 gpmc_ad13 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data18 1 O mmc1_dat5 2 I/O mmc2_dat1 3 I/O eQEP2B_in 4 I pr1_mii0_txd1 5 O pr1_pru0_pru_r30_15 6 O gpio1_13 7 I/O W17 V13 GPMC_AD14 gpmc_ad14 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data17 1 O mmc1_dat6 2 I/O mmc2_dat2 3 I/O eQEP2_index 4 I/O pr1_mii0_txd0 5 O pr1_pru0_pru_r31_14 6 I gpio1_14 7 I/O 26 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] V17 U13 GPMC_AD15 gpmc_ad15 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_data16 1 O mmc1_dat7 2 I/O mmc2_dat3 3 I/O eQEP2_strobe 4 I/O pr1_ecap0_ecap_capin_apwm_o 5 I/O pr1_pru0_pru_r31_15 6 I gpio1_15 7 I/O V10 R7 GPMC_ADVn_ALE gpmc_advn_ale 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 timer4 2 I/O gpio2_2 7 I/O V8 T6 GPMC_BEn0_CLE gpmc_be0n_cle 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 timer5 2 I/O gpio2_5 7 I/O V18 U18 GPMC_BEn1 gpmc_be1n 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV3 gmii2_col 1 I gpmc_csn6 2 O mmc2_dat3 3 I/O gpmc_dir 4 O pr1_mii1_rxlink 5 I mcasp0_aclkr 6 I/O gpio1_28 7 I/O V16 V12 GPMC_CLK gpmc_clk 0 I/O L L 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 lcd_memory_clk 1 O gpmc_wait1 2 I mmc2_clk 3 I/O pr1_mii1_crs 4 I pr1_mdio_mdclk 5 O mcasp0_fsr 6 I/O gpio2_1 7 I/O W8 V6 GPMC_CSn0 gpmc_csn0 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 gpio1_29 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 27 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] V14 U9 GPMC_CSn1 gpmc_csn1 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 gpmc_clk 1 I/O mmc1_clk 2 I/O pr1_edio_data_in6 3 I pr1_edio_data_out6 4 O pr1_pru1_pru_r30_12 5 O pr1_pru1_pru_r31_12 6 I gpio1_30 7 I/O U15 V9 GPMC_CSn2 gpmc_csn2 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 gpmc_be1n 1 O mmc1_cmd 2 I/O pr1_edio_data_in7 3 I pr1_edio_data_out7 4 O pr1_pru1_pru_r30_13 5 O pr1_pru1_pru_r31_13 6 I gpio1_31 7 I/O U17 T13 GPMC_CSn3(6) gpmc_csn3 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV2 gpmc_a3 1 O rmii2_crs_dv 2 I mmc2_cmd 3 I/O pr1_mii0_crs 4 I pr1_mdio_data 5 I/O EMU4 6 I/O gpio2_0 7 I/O W9 T7 GPMC_OEn_REn gpmc_oen_ren 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 timer7 2 I/O gpio2_3 7 I/O R15 T17 GPMC_WAIT0 gpmc_wait0 0 I H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV3 gmii2_crs 1 I gpmc_csn4 2 O rmii2_crs_dv 3 I mmc1_sdcd 4 I pr1_mii1_col 5 I uart4_rxd 6 I gpio0_30 7 I/O U8 U6 GPMC_WEn gpmc_wen 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV1 timer6 2 I/O gpio2_4 7 I/O 28 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] W18 U17 GPMC_WPn gpmc_wpn 0 O H H 7 VDDSHV1/ Yes 6 PU/PD LVCMOS VDDSHV3 gmii2_rxerr 1 I gpmc_csn5 2 O rmii2_rxerr 3 I mmc2_sdcd 4 I pr1_mii1_txen 5 O uart4_txd 6 O gpio0_31 7 I/O C18 C17 I2C0_SDA I2C0_SDA 0 I/OD Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 timer4 1 I/O uart2_ctsn 2 I eCAP2_in_PWM2_out 3 I/O gpio3_5 7 I/O B19 C16 I2C0_SCL I2C0_SCL 0 I/OD Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 timer7 1 I/O uart2_rtsn 2 O eCAP1_in_PWM1_out 3 I/O gpio3_6 7 I/O W7 R6 LCD_AC_BIAS_EN lcd_ac_bias_en 0 O Z L 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a11 1 O pr1_mii1_crs 2 I pr1_edio_data_in5 3 I pr1_edio_data_out5 4 O pr1_pru1_pru_r30_11 5 O pr1_pru1_pru_r31_11 6 I gpio2_25 7 I/O U1 R1 LCD_DATA0(5) lcd_data0 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a0 1 O pr1_mii_mt0_clk 2 I ehrpwm2A 3 O pr1_pru1_pru_r30_0 5 O pr1_pru1_pru_r31_0 6 I gpio2_6 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 29 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] U2 R2 LCD_DATA1(5) lcd_data1 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a1 1 O pr1_mii0_txen 2 O ehrpwm2B 3 O pr1_pru1_pru_r30_1 5 O pr1_pru1_pru_r31_1 6 I gpio2_7 7 I/O V1 R3 LCD_DATA2(5) lcd_data2 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a2 1 O pr1_mii0_txd3 2 O ehrpwm2_tripzone_input 3 I pr1_pru1_pru_r30_2 5 O pr1_pru1_pru_r31_2 6 I gpio2_8 7 I/O V2 R4 LCD_DATA3(5) lcd_data3 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a3 1 O pr1_mii0_txd2 2 O ehrpwm0_synco 3 O pr1_pru1_pru_r30_3 5 O pr1_pru1_pru_r31_3 6 I gpio2_9 7 I/O W2 T1 LCD_DATA4(5) lcd_data4 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a4 1 O pr1_mii0_txd1 2 O eQEP2A_in 3 I pr1_pru1_pru_r30_4 5 O pr1_pru1_pru_r31_4 6 I gpio2_10 7 I/O W3 T2 LCD_DATA5(5) lcd_data5 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a5 1 O pr1_mii0_txd0 2 O eQEP2B_in 3 I pr1_pru1_pru_r30_5 5 O pr1_pru1_pru_r31_5 6 I gpio2_11 7 I/O 30 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] V3 T3 LCD_DATA6(5) lcd_data6 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a6 1 O pr1_edio_data_in6 2 I eQEP2_index 3 I/O pr1_edio_data_out6 4 O pr1_pru1_pru_r30_6 5 O pr1_pru1_pru_r31_6 6 I gpio2_12 7 I/O U3 T4 LCD_DATA7(5) lcd_data7 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a7 1 O pr1_edio_data_in7 2 I eQEP2_strobe 3 I/O pr1_edio_data_out7 4 O pr1_pru1_pru_r30_7 5 O pr1_pru1_pru_r31_7 6 I gpio2_13 7 I/O V4 U1 LCD_DATA8(5) lcd_data8 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a12 1 O ehrpwm1_tripzone_input 2 I mcasp0_aclkx 3 I/O uart5_txd 4 O pr1_mii0_rxd3 5 I uart2_ctsn 6 I gpio2_14 7 I/O W4 U2 LCD_DATA9(5) lcd_data9 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a13 1 O ehrpwm0_synco 2 O mcasp0_fsx 3 I/O uart5_rxd 4 I pr1_mii0_rxd2 5 I uart2_rtsn 6 O gpio2_15 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 31 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] U5 U3 LCD_DATA10(5) lcd_data10 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a14 1 O ehrpwm1A 2 O mcasp0_axr0 3 I/O pr1_mii0_rxd1 5 I uart3_ctsn 6 I gpio2_16 7 I/O V5 U4 LCD_DATA11(5) lcd_data11 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a15 1 O ehrpwm1B 2 O mcasp0_ahclkr 3 I/O mcasp0_axr2 4 I/O pr1_mii0_rxd0 5 I uart3_rtsn 6 O gpio2_17 7 I/O V6 V2 LCD_DATA12(5) lcd_data12 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a16 1 O eQEP1A_in 2 I mcasp0_aclkr 3 I/O mcasp0_axr2 4 I/O pr1_mii0_rxlink 5 I uart4_ctsn 6 I gpio0_8 7 I/O U6 V3 LCD_DATA13(5) lcd_data13 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a17 1 O eQEP1B_in 2 I mcasp0_fsr 3 I/O mcasp0_axr3 4 I/O pr1_mii0_rxer 5 I uart4_rtsn 6 O gpio0_9 7 I/O 32 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] W6 V4 LCD_DATA14(5) lcd_data14 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a18 1 O eQEP1_index 2 I/O mcasp0_axr1 3 I/O uart5_rxd 4 I pr1_mii_mr0_clk 5 I uart5_ctsn 6 I gpio0_10 7 I/O V7 T5 LCD_DATA15(5) lcd_data15 0 I/O Z Z 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a19 1 O eQEP1_strobe 2 I/O mcasp0_ahclkx 3 I/O mcasp0_axr3 4 I/O pr1_mii0_rxdv 5 I uart5_rtsn 6 O gpio0_11 7 I/O T7 R5 LCD_HSYNC(7) lcd_hsync 0 O Z L 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a9 1 O gpmc_a2 2 O pr1_edio_data_in3 3 I pr1_edio_data_out3 4 O pr1_pru1_pru_r30_9 5 O pr1_pru1_pru_r31_9 6 I gpio2_23 7 I/O W5 V5 LCD_PCLK lcd_pclk 0 O Z L 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a10 1 O pr1_mii0_crs 2 I pr1_edio_data_in4 3 I pr1_edio_data_out4 4 O pr1_pru1_pru_r30_10 5 O pr1_pru1_pru_r31_10 6 I gpio2_24 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 33 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] U7 U5 LCD_VSYNC(7) lcd_vsync 0 O Z L 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 gpmc_a8 1 O gpmc_a1 2 O pr1_edio_data_in2 3 I pr1_edio_data_out2 4 O pr1_pru1_pru_r30_8 5 O pr1_pru1_pru_r31_8 6 I gpio2_22 7 I/O NA B13 MCASP0_FSX mcasp0_fsx 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS ehrpwm0B 1 O spi1_d0 3 I/O mmc1_sdcd 4 I pr1_pru0_pru_r30_1 5 O pr1_pru0_pru_r31_1 6 I gpio3_15 7 I/O NA B12 MCASP0_ACLKR mcasp0_aclkr 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS eQEP0A_in 1 I mcasp0_axr2 2 I/O mcasp1_aclkx 3 I/O mmc0_sdwp 4 I pr1_pru0_pru_r30_4 5 O pr1_pru0_pru_r31_4 6 I gpio3_18 7 I/O NA C12 MCASP0_AHCLKR mcasp0_ahclkr 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS ehrpwm0_synci 1 I mcasp0_axr2 2 I/O spi1_cs0 3 I/O eCAP2_in_PWM2_out 4 I/O pr1_pru0_pru_r30_3 5 O pr1_pru0_pru_r31_3 6 I gpio3_17 7 I/O 34 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] NA A14 MCASP0_AHCLKX mcasp0_ahclkx 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS eQEP0_strobe 1 I/O mcasp0_axr3 2 I/O mcasp1_axr1 3 I/O EMU4 4 I/O pr1_pru0_pru_r30_7 5 O pr1_pru0_pru_r31_7 6 I gpio3_21 7 I/O NA A13 MCASP0_ACLKX mcasp0_aclkx 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS ehrpwm0A 1 O spi1_sclk 3 I/O mmc0_sdcd 4 I pr1_pru0_pru_r30_0 5 O pr1_pru0_pru_r31_0 6 I gpio3_14 7 I/O NA C13 MCASP0_FSR mcasp0_fsr 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS eQEP0B_in 1 I mcasp0_axr3 2 I/O mcasp1_fsx 3 I/O EMU2 4 I/O pr1_pru0_pru_r30_5 5 O pr1_pru0_pru_r31_5 6 I gpio3_19 7 I/O NA D12 MCASP0_AXR0 mcasp0_axr0 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS ehrpwm0_tripzone_input 1 I spi1_d1 3 I/O mmc2_sdcd 4 I pr1_pru0_pru_r30_2 5 O pr1_pru0_pru_r31_2 6 I gpio3_16 7 I/O NA D13 MCASP0_AXR1 mcasp0_axr1 0 I/O L L 7 NA/VDDSHV6 Yes 6 PU/PD LVCMOS eQEP0_index 1 I/O mcasp1_axr0 3 I/O EMU3 4 I/O pr1_pru0_pru_r30_6 5 O pr1_pru0_pru_r31_6 6 I gpio3_20 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 35 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] R19 M18 MDC mdio_clk 0 O H H 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 timer5 1 I/O uart5_txd 2 O uart3_rtsn 3 O mmc0_sdwp 4 I mmc1_clk 5 I/O mmc2_clk 6 I/O gpio0_1 7 I/O P17 M17 MDIO mdio_data 0 I/O H H 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 timer6 1 I/O uart5_rxd 2 I uart3_ctsn 3 I mmc0_sdcd 4 I mmc1_cmd 5 I/O mmc2_cmd 6 I/O gpio0_0 7 I/O L19 J17 MII1_RX_DV gmii1_rxdv 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 lcd_memory_clk 1 O rgmii1_rctl 2 I uart5_txd 3 O mcasp1_aclkx 4 I/O mmc2_dat0 5 I/O mcasp0_aclkr 6 I/O gpio3_4 7 I/O K17 J16 MII1_TX_EN gmii1_txen 0 O L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii1_txen 1 O rgmii1_tctl 2 O timer4 3 I/O mcasp1_axr0 4 I/O eQEP0_index 5 I/O mmc2_cmd 6 I/O gpio3_3 7 I/O 36 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] K19 J15 MII1_RX_ER gmii1_rxerr 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii1_rxerr 1 I spi1_d1 2 I/O I2C1_SCL 3 I/OD mcasp1_fsx 4 I/O uart5_rtsn 5 O uart2_txd 6 O gpio3_2 7 I/O M19 L18 MII1_RX_CLK gmii1_rxclk 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 uart2_txd 1 O rgmii1_rclk 2 I mmc0_dat6 3 I/O mmc1_dat1 4 I/O uart1_dsrn 5 I mcasp0_fsx 6 I/O gpio3_10 7 I/O N19 K18 MII1_TX_CLK gmii1_txclk 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 uart2_rxd 1 I rgmii1_tclk 2 O mmc0_dat7 3 I/O mmc1_dat0 4 I/O uart1_dcdn 5 I mcasp0_aclkx 6 I/O gpio3_9 7 I/O J19 H16 MII1_COL gmii1_col 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii2_refclk 1 I/O spi1_sclk 2 I/O uart5_rxd 3 I mcasp1_axr2 4 I/O mmc2_dat3 5 I/O mcasp0_axr2 6 I/O gpio3_0 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 37 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] J18 H17 MII1_CRS gmii1_crs 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii1_crs_dv 1 I spi1_d0 2 I/O I2C1_SDA 3 I/OD mcasp1_aclkx 4 I/O uart5_ctsn 5 I uart2_rxd 6 I gpio3_1 7 I/O P18 M16 MII1_RXD0 gmii1_rxd0 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii1_rxd0 1 I rgmii1_rd0 2 I mcasp1_ahclkx 3 I/O mcasp1_ahclkr 4 I/O mcasp1_aclkr 5 I/O mcasp0_axr3 6 I/O gpio2_21 7 I/O P19 L15 MII1_RXD1 gmii1_rxd1 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii1_rxd1 1 I rgmii1_rd1 2 I mcasp1_axr3 3 I/O mcasp1_fsr 4 I/O eQEP0_strobe 5 I/O mmc2_clk 6 I/O gpio2_20 7 I/O N16 L16 MII1_RXD2 gmii1_rxd2 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 uart3_txd 1 O rgmii1_rd2 2 I mmc0_dat4 3 I/O mmc1_dat3 4 I/O uart1_rin 5 I mcasp0_axr1 6 I/O gpio2_19 7 I/O 38 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] N17 L17 MII1_RXD3 gmii1_rxd3 0 I L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 uart3_rxd 1 I rgmii1_rd3 2 I mmc0_dat5 3 I/O mmc1_dat2 4 I/O uart1_dtrn 5 O mcasp0_axr0 6 I/O gpio2_18 7 I/O L18 K17 MII1_TXD0 gmii1_txd0 0 O L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii1_txd0 1 O rgmii1_td0 2 O mcasp1_axr2 3 I/O mcasp1_aclkr 4 I/O eQEP0B_in 5 I mmc1_clk 6 I/O gpio0_28 7 I/O M18 K16 MII1_TXD1 gmii1_txd1 0 O L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 rmii1_txd1 1 O rgmii1_td1 2 O mcasp1_fsr 3 I/O mcasp1_axr1 4 I/O eQEP0A_in 5 I mmc1_cmd 6 I/O gpio0_21 7 I/O N18 K15 MII1_TXD2 gmii1_txd2 0 O L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 dcan0_rx 1 I rgmii1_td2 2 O uart4_txd 3 O mcasp1_axr0 4 I/O mmc2_dat2 5 I/O mcasp0_ahclkx 6 I/O gpio0_17 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 39 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] M17 J18 MII1_TXD3 gmii1_txd3 0 O L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 dcan0_tx 1 O rgmii1_td3 2 O uart4_rxd 3 I mcasp1_fsx 4 I/O mmc2_dat1 5 I/O mcasp0_fsr 6 I/O gpio0_16 7 I/O G17 G18 MMC0_CMD mmc0_cmd 0 I/O H H 7 VDDSHV4/ Yes 6 PU/PD LVCMOS VDDSHV4 gpmc_a25 1 O uart3_rtsn 2 O uart2_txd 3 O dcan1_rx 4 I pr1_pru0_pru_r30_13 5 O pr1_pru0_pru_r31_13 6 I gpio2_31 7 I/O G19 G17 MMC0_CLK mmc0_clk 0 I/O H H 7 VDDSHV4/ Yes 6 PU/PD LVCMOS VDDSHV4 gpmc_a24 1 O uart3_ctsn 2 I uart2_rxd 3 I dcan1_tx 4 O pr1_pru0_pru_r30_12 5 O pr1_pru0_pru_r31_12 6 I gpio2_30 7 I/O G18 G16 MMC0_DAT0 mmc0_dat0 0 I/O H H 7 VDDSHV4/ Yes 6 PU/PD LVCMOS VDDSHV4 gpmc_a23 1 O uart5_rtsn 2 O uart3_txd 3 O uart1_rin 4 I pr1_pru0_pru_r30_11 5 O pr1_pru0_pru_r31_11 6 I gpio2_29 7 I/O 40 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] H17 G15 MMC0_DAT1 mmc0_dat1 0 I/O H H 7 VDDSHV4/ Yes 6 PU/PD LVCMOS VDDSHV4 gpmc_a22 1 O uart5_ctsn 2 I uart3_rxd 3 I uart1_dtrn 4 O pr1_pru0_pru_r30_10 5 O pr1_pru0_pru_r31_10 6 I gpio2_28 7 I/O H18 F18 MMC0_DAT2 mmc0_dat2 0 I/O H H 7 VDDSHV4/ Yes 6 PU/PD LVCMOS VDDSHV4 gpmc_a21 1 O uart4_rtsn 2 O timer6 3 I/O uart1_dsrn 4 I pr1_pru0_pru_r30_9 5 O pr1_pru0_pru_r31_9 6 I gpio2_27 7 I/O H19 F17 MMC0_DAT3 mmc0_dat3 0 I/O H H 7 VDDSHV4/ Yes 6 PU/PD LVCMOS VDDSHV4 gpmc_a20 1 O uart4_ctsn 2 I timer5 3 I/O uart1_dcdn 4 I pr1_pru0_pru_r30_8 5 O pr1_pru0_pru_r31_8 6 I gpio2_26 7 I/O C7 C6 PMIC_POWER_EN PMIC_POWER_EN 0 O H 1 0 VDDS_RTC/ NA 6 NA LVCMOS VDDS_RTC E15 B15 PWRONRSTn porz 0 I Z Z 0 VDDSHV6/ Yes NA NA LVCMOS VDDSHV6(12) B6 A3 RESERVED(3) testout 0 O NA NA NA VDDSHV6/ NA NA NA Analog VDDSHV6 K18 H18 RMII1_REF_CLK rmii1_refclk 0 I/O L L 7 VDDSHV5/ Yes 6 PU/PD LVCMOS VDDSHV5 xdma_event_intr2 1 I spi1_cs0 2 I/O uart5_txd 3 O mcasp1_axr3 4 I/O mmc0_pow 5 O mcasp1_ahclkx 6 I/O gpio0_29 7 I/O A7 B4 RTC_KALDO_ENn ENZ_KALDO_1P8V 0 I Z Z 0 VDDS_RTC/ NA NA NA Analog VDDS_RTC Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 41 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] B7 B5 RTC_PWRONRSTn RTC_PORz 0 I Z Z 0 VDDS_RTC/ Yes NA NA LVCMOS VDDS_RTC A6 A6 RTC_XTALIN OSC1_IN 0 I H H 0 VDDS_RTC/ Yes NA PU(1) LVCMOS VDDS_RTC A5 A4 RTC_XTALOUT OSC1_OUT 0 O Z(23) Z(23) 0 VDDS_RTC/ NA NA(15) NA LVCMOS VDDS_RTC A18 A17 SPI0_SCLK spi0_sclk 0 I/O Z H 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 uart2_rxd 1 I I2C2_SDA 2 I/OD ehrpwm0A 3 O pr1_uart0_cts_n 4 I pr1_edio_sof 5 O EMU2 6 I/O gpio0_2 7 I/O A17 A16 SPI0_CS0 spi0_cs0 0 I/O Z H 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 mmc2_sdwp 1 I I2C1_SCL 2 I/OD ehrpwm0_synci 3 I pr1_uart0_txd 4 O pr1_edio_data_in1 5 I pr1_edio_data_out1 6 O gpio0_5 7 I/O B16 C15 SPI0_CS1 spi0_cs1 0 I/O Z H 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 uart3_rxd 1 I eCAP1_in_PWM1_out 2 I/O mmc0_pow 3 O xdma_event_intr2 4 I mmc0_sdcd 5 I EMU4 6 I/O gpio0_6 7 I/O B18 B17 SPI0_D0 spi0_d0 0 I/O Z H 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 uart2_txd 1 O I2C2_SCL 2 I/OD ehrpwm0B 3 O pr1_uart0_rts_n 4 O pr1_edio_latch_in 5 I EMU3 6 I/O gpio0_3 7 I/O 42 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] B17 B16 SPI0_D1 spi0_d1 0 I/O Z H 7 VDDSHV6/ Yes 6 PU/PD LVCMOS VDDSHV6 mmc1_sdwp 1 I I2C1_SDA 2 I/OD ehrpwm0_tripzone_input 3 I pr1_uart0_rxd 4 I pr1_edio_data_in0 5 I pr1_edio_data_out0 6 O gpio0_4 7 I/O B14 A12 TCK TCK 0 I H H 0 VDDSHV6/ Yes NA PU/PD LVCMOS VDDSHV6 B13 B11 TDI TDI 0 I H H 0 VDDSHV6/ Yes NA PU/PD LVCMOS VDDSHV6 A14 A11 TDO TDO 0 O H H 0 VDDSHV6/ NA 4 PU/PD LVCMOS VDDSHV6 C14 C11 TMS TMS 0 I H H 0 VDDSHV6/ Yes NA PU/PD LVCMOS VDDSHV6 A13 B10 TRSTn nTRST 0 I L L 0 VDDSHV6/ Yes NA PU/PD LVCMOS VDDSHV6 F17 E16 UART0_TXD uart0_txd 0 O Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 spi1_cs1 1 I/O dcan0_rx 2 I I2C2_SCL 3 I/OD eCAP1_in_PWM1_out 4 I/O pr1_pru1_pru_r30_15 5 O pr1_pru1_pru_r31_15 6 I gpio1_11 7 I/O F19 E18 UART0_CTSn uart0_ctsn 0 I Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 uart4_rxd 1 I dcan1_tx 2 O I2C1_SDA 3 I/OD spi1_d0 4 I/O timer7 5 I/O pr1_edc_sync0_out 6 O gpio1_8 7 I/O Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 43 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] E19 E15 UART0_RXD uart0_rxd 0 I Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 spi1_cs0 1 I/O dcan0_tx 2 O I2C2_SDA 3 I/OD eCAP2_in_PWM2_out 4 I/O pr1_pru1_pru_r30_14 5 O pr1_pru1_pru_r31_14 6 I gpio1_10 7 I/O F18 E17 UART0_RTSn uart0_rtsn 0 O Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 uart4_txd 1 O dcan1_rx 2 I I2C1_SCL 3 I/OD spi1_d1 4 I/O spi1_cs0 5 I/O pr1_edc_sync1_out 6 O gpio1_9 7 I/O C19 D15 UART1_TXD uart1_txd 0 O Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 mmc2_sdwp 1 I dcan1_rx 2 I I2C1_SCL 3 I/OD pr1_uart0_txd 5 O pr1_pru0_pru_r31_16 6 I gpio0_15 7 I/O D18 D16 UART1_RXD uart1_rxd 0 I Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 mmc1_sdwp 1 I dcan1_tx 2 O I2C1_SDA 3 I/OD pr1_uart0_rxd 5 I pr1_pru1_pru_r31_16 6 I gpio0_14 7 I/O D19 D17 UART1_RTSn uart1_rtsn 0 O Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 timer5 1 I/O dcan0_rx 2 I I2C2_SCL 3 I/OD spi1_cs1 4 I/O pr1_uart0_rts_n 5 O pr1_edc_latch1_in 6 I gpio0_13 7 I/O 44 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] E17 D18 UART1_CTSn uart1_ctsn 0 I Z H 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 timer6 1 I/O dcan0_tx 2 O I2C2_SDA 3 I/OD spi1_cs0 4 I/O pr1_uart0_cts_n 5 I pr1_edc_latch0_in 6 I gpio0_12 7 I/O T18 M15 USB0_CE USB0_CE 0 A Z Z 0 VDDA*_USB0/ NA NA NA Analog VDDA*_USB0 (26) T19 P15 USB0_VBUS USB0_VBUS 0 A Z Z 0 VDDA*_USB0/ NA NA NA Analog VDDA*_USB0 (26) U18 N18 USB0_DM USB0_DM 0 A Z Z 0(13) VDDA*_USB0/ Yes 8(16) NA Analog VDDA*_USB0 (16) (26) G16 F16 USB0_DRVVBUS USB0_DRVVBUS 0 O L 0(PD) 0 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 gpio0_18 7 I/O V19 P16 USB0_ID USB0_ID 0 A Z Z 0 VDDA*_USB0/ NA NA NA Analog VDDA*_USB0 (26) U19 N17 USB0_DP USB0_DP 0 A Z Z 0(13) VDDA*_USB0/ Yes 8(16) NA Analog VDDA*_USB0 (16) (26) NA P18 USB1_CE USB1_CE 0 A Z Z 0 NA/ NA NA NA Analog VDDA*_USB1 (27) NA P17 USB1_ID USB1_ID 0 A Z Z 0 NA/ NA NA NA Analog VDDA*_USB1 (27) NA T18 USB1_VBUS USB1_VBUS 0 A Z Z 0 NA/ NA NA NA Analog VDDA*_USB1 (27) NA R17 USB1_DP USB1_DP 0 A Z Z 0(14) NA/ Yes 8(17) NA Analog VDDA*_USB1 (17) (27) NA F15 USB1_DRVVBUS USB1_DRVVBUS 0 O L 0(PD) 0 NA/VDDSHV6 Yes 4 PU/PD LVCMOS gpio3_13 7 I/O NA R18 USB1_DM USB1_DM 0 A Z Z 0(14) NA/ Yes 8(17) NA Analog VDDA*_USB1 (17) (27) R17 N16 VDDA1P8V_USB0 VDDA1P8V_USB0 NA PWR NA R16 VDDA1P8V_USB1 VDDA1P8V_USB1 NA PWR R18 N15 VDDA3P3V_USB0 VDDA3P3V_USB0 NA PWR NA R15 VDDA3P3V_USB1 VDDA3P3V_USB1 NA PWR Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 45 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] D7 D8 VDDA_ADC VDDA_ADC NA PWR D12,F16, E6,E14,F9, VDDS VDDS NA PWR M16,T6,T14 K13,N6,P9, P14 R8,R9,R11, P7,P8 VDDSHV1 VDDSHV1 NA PWR R12,R13 NA P10,P11 VDDSHV2 VDDSHV2 NA PWR NA P12,P13 VDDSHV3 VDDSHV3 NA PWR G15,H14, H14,J14 VDDSHV4 VDDSHV4 NA PWR H15 M14,M15, K14,L14 VDDSHV5 VDDSHV5 NA PWR N15 E11,E12, E10,E11, VDDSHV6 VDDSHV6 NA PWR E13,F14,P6, E12,E13, R7 F14,G14,N5, P5,P6 G5,H5,H6, E5,F5,G5, VDDS_DDR VDDS_DDR NA PWR K4,K5,M5, H5,J5,K5,L5 M6,N5 U10 R11 VDDS_OSC VDDS_OSC NA PWR T8 R10 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA PWR C5 E7 VDDS_PLL_DDR VDDS_PLL_DDR NA PWR H16 H15 VDDS_PLL_MPU VDDS_PLL_MPU NA PWR C6 D7 VDDS_RTC VDDS_RTC NA PWR C10 E9 VDDS_SRAM_CORE_BG VDDS_SRAM_CORE_BG NA PWR C12 D10 VDDS_SRAM_MPU_BB VDDS_SRAM_MPU_BB NA PWR F9,F11,G9, F6,F7,G6, VDD_CORE VDD_CORE NA PWR G11,H7,H8, G7,G10, H12,H13,J7, H11,J12,K6, J8,J12,J13, K8,K12,L6, K15,K16,L7, L7,L8,L9, L8,L12,L13, M11,M13, M7,M8,M12, N8,N9,N12, M13,N9, N13 N11,P9,P11 NA F10,F11, VDD_MPU VDD_MPU(30) NA PWR F12,F13, G13,H13, J13 NA A2 VDD_MPU_MON VDD_MPU_MON(31) NA A R5 M5 VPP VPP NA PWR B9 A9 VREFN VREFN 0 AP Z Z 0 VDDA_ADC/ NA NA NA Analog VDDA_ADC A9 B9 VREFP VREFP 0 AP Z Z 0 VDDA_ADC/ NA NA NA Analog VDDA_ADC 46 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-2.PinAttributes(ZCEandZCZPackages)(continued) BALLRESET BUFFER PULLUP ZCEBALL ZCZBALL TYPE BALLRESET RESETREL. ZCEPOWER/ HYS NUMBER[1] NUMBER[1] PINNAME[2] SIGNALNAME[3] MODE[4] [5] STATE[6](25) REL.STATE MODE[8] ZCZPOWER[9] [10] STRENGTH /DOWNTYPE I/OCELL[13] [7] (mA)[11] [12] A1,A19,D10, A1,A18,F8, VSS VSS NA GND E7,E8,E9, G8,G9,G11, E10,F6,F7, G12,H6,H7, F8,F12,F13, H8,H9,H10, G8,G12,H9, H12,J6,J7, H10,H11,J5, J8,J9,J10, J6,J9,J11, J11,K7,K9, J14,J15,K8, K10,K11, K9,K11,K12, L10,L11,L12, L5,L6,L9, L13,M6,M7, L11,L14,L15,M8,M9,M10, M9,M10, M12,N7, M11,N8, N10,N11,V1, N12,P7,P8, V18 P12,P13, P14,R10, T10,W1,W19 D8 E8 VSSA_ADC VSSA_ADC NA GND P16 M14,N14 VSSA_USB VSSA_USB NA GND V11 V11 VSS_OSC VSS_OSC(28) NA A NA A5 VSS_RTC VSS_RTC(29) NA A A16 A10 WARMRSTn nRESETIN_OUT 0 I/OD 0 0(PU)(11) 0 VDDSHV6/ Yes 4 PU/PD LVCMOS (8) VDDSHV6 C15 A15 XDMA_EVENT_INTR0 xdma_event_intr0 0 I Z (4) (9) VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 timer4 2 I/O clkout1 3 O spi1_cs1 4 I/O pr1_pru1_pru_r31_16 5 I EMU2 6 I/O gpio0_19 7 I/O B15 D14 XDMA_EVENT_INTR1 xdma_event_intr1 0 I Z L 7 VDDSHV6/ Yes 4 PU/PD LVCMOS VDDSHV6 tclkin 2 I clkout2 3 O timer7 4 I/O pr1_pru0_pru_r31_16 5 I EMU3 6 I/O gpio0_20 7 I/O W11 V10 XTALIN OSC0_IN 0 I Z Z 0 VDDS_OSC/ Yes NA PD(2) LVCMOS VDDS_OSC W12 U11 XTALOUT OSC0_OUT 0 O (24) (24) 0 VDDS_OSC/ NA NA(15) NA LVCMOS VDDS_OSC Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 47 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com (1) Aninternal10kohmpullupisturnedonwhentheoscillatorisdisabled.Theoscillatorisdisabledbydefaultafterpowerisapplied. (2) Aninternal15kohmpulldownisturnedonwhentheoscillatorisdisabled.Theoscillatorisenabledbydefaultafterpowerisapplied. (3) Donotconnectanythingtothisterminal. (4) Ifsysboot[5]islowontherisingedgeofPWRONRSTn,thisterminalhasaninternalpulldownturnedonafterresetisreleased.Ifsysboot[5]ishighontherisingedgeorPWRONRSTn, thisterminalwillinitiallybedrivenlowafterresetisreleasedthenitbeginstotoggleatthesamefrequencyoftheXTALINterminal. (5) LCD_DATA[15:0]terminalsarerespectivelySYSBOOT[15:0]inputs,latchedontherisingedgeofPWRONRSTn. (6) Mode1andMode2signalassignmentsforthisterminalareonlyavailablewithsiliconrevision2.0ornewerdevices. (7) Mode2signalassignmentforthisterminalisonlyavailablewithsiliconrevision2.0ornewerdevices. (8) RefertotheExternalWarmResetsectionoftheAM335xTechnicalReferenceManualformoreinformationrelatedtotheoperationofthisterminal. (9) ResetReleaseMode=7ifsysboot[5]islow.Mode=3ifsysboot[5]ishigh. (10) Siliconrevision1.0devicesonlyprovidetheMMC2_DAT7signalwhenMode3isselected.Siliconrevision2.0andnewerdevicesimplementanotherlevelofpinmultiplexingwhich providestheoriginalMMC2_DAT7signalorRMII2_CRS_DVsignalwhenMode3isselected.ThisnewlevelofofpinmultiplexingisselectedwithbitzerooftheSMA2register.Formore detailsrefertoSection1.2oftheAM335xTechnicalReferenceManual. (11) The0(PU)indicatesthatthisterminalisinitiallylowbasedonthedescriptionintheAM335xTechnicalReferenceManual.However,itisalsohasaweakinternalpullupapplied. (12) TheinputvoltagethresholdsforthisinputarenotafunctionofVDDSHV6.PleaserefertotheDCElectricalCharacteristicssectionfordetailsrelatedtoelectricalparametersassociated withthisinputterminal. (13) TheinternalUSBPHYcanbeconfiguredtomultiplextheUART2_TXorUART2_RXsignalstothisterminal.FormoredetailsrefertoUSBGPIODetailssectionoftheAM335xTechnical ReferenceManual. (14) TheinternalUSBPHYcanbeconfiguredtomultiplextheUART3_TXorUART3_RXsignalstothisterminal.FormoredetailsrefertoUSBGPIODetailssectionoftheAM335xTechnical ReferenceManual. (15) Thisoutputshouldonlybeusedtosourcetherecommendedcrystalcircuit. (16) ThisparameteronlyapplieswhenthisUSBPHYterminalisoperatinginUART2mode. (17) ThisparameteronlyapplieswhenthisUSBPHYterminalisoperatinginUART3mode. (18) ThisterminalisaanaloginputusedtosettheswitchingthresholdoftheDDRinputbuffersto(VDDS_DDR/2). (19) Thisterminalisaanalogpassivesignalthatconnectstoanexternal49.9ohm1%,20mWreferenceresistorwhichisusedtocalibratetheDDRinput/outputbuffers. (20) Thisterminalisanaloginputthatmayalsobeconfiguredasanopen-drainoutput. (21) Thisterminalisanaloginputthatmayalsobeconfiguredasanopen-sourceoropen-drainoutput. (22) Thisterminalisanaloginputthatmayalsobeconfiguredasanopen-sourceoutput. (23) Thisterminalishigh-Zwhentheoscillatorisdisabled.ThisterminalisdrivenhighifRTC_XTALINislessthanVIL,drivenlowifRTC_XTALINisgreaterthanVIH,anddriventoa unknownvalueifRTC_XTALINisbetweenVILandVIHwhentheoscillatorisenabled.Theoscillatorisdisabledbydefaultafterpowerisapplied. (24) Thisterminalishigh-Zwhentheoscillatorisdisabled.ThisterminalisdrivenhighifXTALINislessthanVIL,drivenlowifXTALINisgreaterthanVIH,anddriventoaunknownvalueif XTALINisbetweenVILandVIHwhentheoscillatorisenabled.Theoscillatorisenabledbydefaultafterpowerisapplied. (25) ForallpinswithcontentintheBallResetStatecolumnofthistable,theterminalisnotdefineduntilallthesuppliesareramped. (26) Thisterminalrequirestwopowersupplies,VDDA3p3v_USB0andVDDA1p8v_USB0.The"*"characterinthepowersupplynameisawildcardthatrepresents"3p3v"and"1p8v". (27) Thisterminalrequirestwopowersupplies,VDDA3p3v_USB1andVDDA1p8v_USB1.The"*"characterinthepowersupplynameisawildcardthatrepresents"3p3v"and"1p8v". (28) RefertoSection6.2.2foradditionaldetailsaboutVSS_OSC. (29) RefertoSection6.2.2foradditionaldetailsaboutVSS_RTC. (30) ThispowerrailisconnectedtoVDD_COREintheZCEpackage. (31) ThisterminalprovidesaKelvinconnectiontoVDD_MPU.Itcanbeconnectedtothepowersupplyfeedbackinputtoprovideremotesensingwhichcompensatesforvoltagedropinthe 48 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 PCBpowerdistributionnetworkandpackage.WhentheKelvinconnectionisnotuseditshouldbeconnectedtothesamepowersourceasVDD_MPU. Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 49 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3 Signal Descriptions The AM335x device contains many peripheral interfaces. In order to reduce package size and lower overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal functions. Although there are many combinations of pin multiplexing that are possible, onlyacertainnumberofsets,calledI/OSets,arevalidduetotiminglimitations.ThesevalidI/OSets were carefullychosentoprovidemanypossibleapplicationscenariosfortheuser. Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the pin- multiplexingconfigurationselectedforadesignonlyusesvalidI/OSetssupportedbythe AM335xdevice. 50 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 (1) SIGNALNAME:Thesignalname (2) DESCRIPTION:Descriptionofthesignal (3) TYPE:Balltypeforthisspecificfunction: – I=Input – O=Output – I/O=Input/Output – D=Opendrain – DS=Differential – A=Analog (4) BALL:Packageballlocation Table4-3.ADCSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] AIN0 AnalogInput/Output A B8 B6 AIN1 AnalogInput/Output A A11 C7 AIN2 AnalogInput/Output A A8 B7 AIN3 AnalogInput/Output A B11 A7 AIN4 AnalogInput/Output A C8 C8 AIN5 AnalogInput A B12 B8 AIN6 AnalogInput A A10 A8 AIN7 AnalogInput A A12 C9 VREFN AnalogNegativeReferenceInput AP B9 A9 VREFP AnalogPositiveReferenceInput AP A9 B9 Table4-4.DebugSubsystemSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] EMU0 MISCEMULATIONPIN I/O A15 C14 EMU1 MISCEMULATIONPIN I/O D14 B14 EMU2 MISCEMULATIONPIN I/O A18,C15 A15,A17,C13 EMU3 MISCEMULATIONPIN I/O B15,B18 B17,D13,D14 EMU4 MISCEMULATIONPIN I/O B16,U17 A14,C15,T13 nTRST JTAGTESTRESET(ACTIVELOW) I A13 B10 TCK JTAGTESTCLOCK I B14 A12 TDI JTAGTESTDATAINPUT I B13 B11 TDO JTAGTESTDATAOUTPUT O A14 A11 TMS JTAGTESTMODESELECT I C14 C11 Table4-5.LCDControllerSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] lcd_ac_bias_en LCDACbiasenablechipselect O W7 R6 lcd_data0 LCDdatabus I/O U1 R1 lcd_data1 LCDdatabus I/O U2 R2 lcd_data10 LCDdatabus I/O U5 U3 lcd_data11 LCDdatabus I/O V5 U4 lcd_data12 LCDdatabus I/O V6 V2 lcd_data13 LCDdatabus I/O U6 V3 lcd_data14 LCDdatabus I/O W6 V4 lcd_data15 LCDdatabus I/O V7 T5 lcd_data16 LCDdatabus O V17 U13 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 51 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-5.LCDControllerSignalsDescription(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] lcd_data17 LCDdatabus O W17 V13 lcd_data18 LCDdatabus O T13 R12 lcd_data19 LCDdatabus O U13 T12 lcd_data2 LCDdatabus I/O V1 R3 lcd_data20 LCDdatabus O U12 U12 lcd_data21 LCDdatabus O T12 T11 lcd_data22 LCDdatabus O W16 T10 lcd_data23 LCDdatabus O V15 U10 lcd_data3 LCDdatabus I/O V2 R4 lcd_data4 LCDdatabus I/O W2 T1 lcd_data5 LCDdatabus I/O W3 T2 lcd_data6 LCDdatabus I/O V3 T3 lcd_data7 LCDdatabus I/O U3 T4 lcd_data8 LCDdatabus I/O V4 U1 lcd_data9 LCDdatabus I/O W4 U2 lcd_hsync LCDHorizontalSync O T7 R5 lcd_memory_clk LCDMCLK O L19,V16 J17,V12 lcd_pclk LCDpixelclock O W5 V5 lcd_vsync LCDVerticalSync O U7 U5 52 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.1 External Memory Interfaces Table4-6.ExternalMemoryInterfaces/DDRSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] ddr_a0 DDRSDRAMROW/COLUMNADDRESS O F3 F3 OUTPUT ddr_a1 DDRSDRAMROW/COLUMNADDRESS O J2 H1 OUTPUT ddr_a10 DDRSDRAMROW/COLUMNADDRESS O E2 F4 OUTPUT ddr_a11 DDRSDRAMROW/COLUMNADDRESS O G4 F2 OUTPUT ddr_a12 DDRSDRAMROW/COLUMNADDRESS O F4 E3 OUTPUT ddr_a13 DDRSDRAMROW/COLUMNADDRESS O H1 H3 OUTPUT ddr_a14 DDRSDRAMROW/COLUMNADDRESS O H3 H4 OUTPUT ddr_a15 DDRSDRAMROW/COLUMNADDRESS O E3 D3 OUTPUT ddr_a2 DDRSDRAMROW/COLUMNADDRESS O D1 E4 OUTPUT ddr_a3 DDRSDRAMROW/COLUMNADDRESS O B3 C3 OUTPUT ddr_a4 DDRSDRAMROW/COLUMNADDRESS O E5 C2 OUTPUT ddr_a5 DDRSDRAMROW/COLUMNADDRESS O A2 B1 OUTPUT ddr_a6 DDRSDRAMROW/COLUMNADDRESS O B1 D5 OUTPUT ddr_a7 DDRSDRAMROW/COLUMNADDRESS O D2 E2 OUTPUT ddr_a8 DDRSDRAMROW/COLUMNADDRESS O C3 D4 OUTPUT ddr_a9 DDRSDRAMROW/COLUMNADDRESS O B2 C1 OUTPUT ddr_ba0 DDRSDRAMBANKADDRESSOUTPUT O A3 C4 ddr_ba1 DDRSDRAMBANKADDRESSOUTPUT O E1 E1 ddr_ba2 DDRSDRAMBANKADDRESSOUTPUT O B4 B3 ddr_casn DDRSDRAMCOLUMNADDRESSSTROBE O F1 F1 OUTPUT(ACTIVELOW) ddr_ck DDRSDRAMCLOCKOUTPUT(Differential+) O C2 D2 ddr_cke DDRSDRAMCLOCKENABLEOUTPUT O G3 G3 ddr_csn0 DDRSDRAMCHIPSELECTOUTPUT O H2 H2 ddr_d0 DDRSDRAMDATAINPUT/OUTPUT I/O N4 M3 ddr_d1 DDRSDRAMDATAINPUT/OUTPUT I/O P4 M4 ddr_d10 DDRSDRAMDATAINPUT/OUTPUT I/O M3 K2 ddr_d11 DDRSDRAMDATAINPUT/OUTPUT I/O M4 K3 ddr_d12 DDRSDRAMDATAINPUT/OUTPUT I/O M2 K4 ddr_d13 DDRSDRAMDATAINPUT/OUTPUT I/O M1 L3 ddr_d14 DDRSDRAMDATAINPUT/OUTPUT I/O N2 L4 ddr_d15 DDRSDRAMDATAINPUT/OUTPUT I/O N1 M1 ddr_d2 DDRSDRAMDATAINPUT/OUTPUT I/O P2 N1 ddr_d3 DDRSDRAMDATAINPUT/OUTPUT I/O P1 N2 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 53 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-6.ExternalMemoryInterfaces/DDRSignalsDescription(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] ddr_d4 DDRSDRAMDATAINPUT/OUTPUT I/O P3 N3 ddr_d5 DDRSDRAMDATAINPUT/OUTPUT I/O T1 N4 ddr_d6 DDRSDRAMDATAINPUT/OUTPUT I/O T2 P3 ddr_d7 DDRSDRAMDATAINPUT/OUTPUT I/O R3 P4 ddr_d8 DDRSDRAMDATAINPUT/OUTPUT I/O K2 J1 ddr_d9 DDRSDRAMDATAINPUT/OUTPUT I/O K1 K1 ddr_dqm0 DDRWRITEENABLE/DATAMASKFOR O N3 M2 DATA[7:0] ddr_dqm1 DDRWRITEENABLE/DATAMASKFOR O K3 J2 DATA[15:8] ddr_dqs0 DDRDATASTROBEFORDATA[7:0] I/O R1 P1 (Differential+) ddr_dqs1 DDRDATASTROBEFORDATA[15:8] I/O L1 L1 (Differential+) ddr_dqsn0 DDRDATASTROBEFORDATA[7:0] I/O R2 P2 (Differential-) ddr_dqsn1 DDRDATASTROBEFORDATA[15:8] I/O L2 L2 (Differential-) ddr_nck DDRSDRAMCLOCKOUTPUT(Differential-) O C1 D1 ddr_odt ODTOUTPUT O G1 G1 ddr_rasn DDRSDRAMROWADDRESSSTROBE O F2 G4 OUTPUT(ACTIVELOW) ddr_resetn DDR3/DDR3LRESETOUTPUT(ACTIVELOW) O G2 G2 ddr_vref VoltageReferenceInput A H4 J4 ddr_vtp VTPCompensationResistor I J1 J3 ddr_wen DDRSDRAMWRITEENABLEOUTPUT O A4 B2 (ACTIVELOW) Table4-7.ExternalMemoryInterfaces/General-PurposeMemoryControllerSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpmc_a0 GPMCAddress O U1 R1,R13 gpmc_a1 GPMCAddress O U2,U7 R2,U5,V14 gpmc_a10 GPMCAddress O W5 T16,V5 gpmc_a11 GPMCAddress O W7 R6,V17 gpmc_a12 GPMCAddress O V4 U1 gpmc_a13 GPMCAddress O W4 U2 gpmc_a14 GPMCAddress O U5 U3 gpmc_a15 GPMCAddress O V5 U4 gpmc_a16 GPMCAddress O V6 R13,V2 gpmc_a17 GPMCAddress O U6 V14,V3 gpmc_a18 GPMCAddress O W6 U14,V4 gpmc_a19 GPMCAddress O V7 T14,T5 gpmc_a2 GPMCAddress O T7,V1 R3,R5,U14 gpmc_a20 GPMCAddress O H19 F17,R14 gpmc_a21 GPMCAddress O H18 F18,V15 gpmc_a22 GPMCAddress O H17 G15,U15 gpmc_a23 GPMCAddress O G18 G16,T15 gpmc_a24 GPMCAddress O G19 G17,V16 54 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-7.ExternalMemoryInterfaces/General-PurposeMemoryControllerSignals Description(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpmc_a25 GPMCAddress O G17 G18,U16 gpmc_a26 GPMCAddress O NA T16 gpmc_a27 GPMCAddress O NA V17 gpmc_a3 GPMCAddress O U17,V2 R4,T13,T14 gpmc_a4 GPMCAddress O W2 R14,T1 gpmc_a5 GPMCAddress O W3 T2,V15 gpmc_a6 GPMCAddress O V3 T3,U15 gpmc_a7 GPMCAddress O U3 T15,T4 gpmc_a8 GPMCAddress O U7 U5,V16 gpmc_a9 GPMCAddress O T7 R5,U16 gpmc_ad0 GPMCAddressandData I/O W10 U7 gpmc_ad1 GPMCAddressandData I/O V9 V7 gpmc_ad10 GPMCAddressandData I/O T12 T11 gpmc_ad11 GPMCAddressandData I/O U12 U12 gpmc_ad12 GPMCAddressandData I/O U13 T12 gpmc_ad13 GPMCAddressandData I/O T13 R12 gpmc_ad14 GPMCAddressandData I/O W17 V13 gpmc_ad15 GPMCAddressandData I/O V17 U13 gpmc_ad2 GPMCAddressandData I/O V12 R8 gpmc_ad3 GPMCAddressandData I/O W13 T8 gpmc_ad4 GPMCAddressandData I/O V13 U8 gpmc_ad5 GPMCAddressandData I/O W14 V8 gpmc_ad6 GPMCAddressandData I/O U14 R9 gpmc_ad7 GPMCAddressandData I/O W15 T9 gpmc_ad8 GPMCAddressandData I/O V15 U10 gpmc_ad9 GPMCAddressandData I/O W16 T10 gpmc_advn_ale GPMCAddressValid/AddressLatchEnable O V10 R7 gpmc_be0n_cle GPMCByteEnable0/CommandLatchEnable O V8 T6 gpmc_be1n GPMCByteEnable1 O U15,V18 U18,V9 gpmc_clk GPMCClock I/O V14,V16 U9,V12 gpmc_csn0 GPMCChipSelect O W8 V6 gpmc_csn1 GPMCChipSelect O V14 U9 gpmc_csn2 GPMCChipSelect O U15 V9 gpmc_csn3 GPMCChipSelect O U17 T13 gpmc_csn4 GPMCChipSelect O R15 T17 gpmc_csn5 GPMCChipSelect O W18 U17 gpmc_csn6 GPMCChipSelect O V18 U18 gpmc_dir GPMCDataDirection O V18 U18 gpmc_oen_ren GPMCOutput/ReadEnable O W9 T7 gpmc_wait0 GPMCWait0 I R15 T17 gpmc_wait1 GPMCWait1 I V16 V12 gpmc_wen GPMCWriteEnable O U8 U6 gpmc_wpn GPMCWriteProtect O W18 U17 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 55 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.2 General-Purpose IOs Table4-8.General-PurposeIOs/GPIO0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpio0_0 GPIO I/O P17 M17 gpio0_1 GPIO I/O R19 M18 gpio0_10 GPIO I/O W6 V4 gpio0_11 GPIO I/O V7 T5 gpio0_12 GPIO I/O E17 D18 gpio0_13 GPIO I/O D19 D17 gpio0_14 GPIO I/O D18 D16 gpio0_15 GPIO I/O C19 D15 gpio0_16 GPIO I/O M17 J18 gpio0_17 GPIO I/O N18 K15 gpio0_18 GPIO I/O G16 F16 gpio0_19 GPIO I/O C15 A15 gpio0_2 GPIO I/O A18 A17 gpio0_20 GPIO I/O B15 D14 gpio0_21 GPIO I/O M18 K16 gpio0_22 GPIO I/O V15 U10 gpio0_23 GPIO I/O W16 T10 gpio0_26 GPIO I/O T12 T11 gpio0_27 GPIO I/O U12 U12 gpio0_28 GPIO I/O L18 K17 gpio0_29 GPIO I/O K18 H18 gpio0_3 GPIO I/O B18 B17 gpio0_30 GPIO I/O R15 T17 gpio0_31 GPIO I/O W18 U17 gpio0_4 GPIO I/O B17 B16 gpio0_5 GPIO I/O A17 A16 gpio0_6 GPIO I/O B16 C15 gpio0_7 GPIO I/O E18 C18 gpio0_8 GPIO I/O V6 V2 gpio0_9 GPIO I/O U6 V3 Table4-9.General-PurposeIOs/GPIO1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpio1_0 GPIO I/O W10 U7 gpio1_1 GPIO I/O V9 V7 gpio1_10 GPIO I/O E19 E15 gpio1_11 GPIO I/O F17 E16 gpio1_12 GPIO I/O U13 T12 gpio1_13 GPIO I/O T13 R12 gpio1_14 GPIO I/O W17 V13 gpio1_15 GPIO I/O V17 U13 gpio1_16 GPIO I/O NA R13 gpio1_17 GPIO I/O NA V14 gpio1_18 GPIO I/O NA U14 56 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-9.General-PurposeIOs/GPIO1SignalsDescription(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpio1_19 GPIO I/O NA T14 gpio1_2 GPIO I/O V12 R8 gpio1_20 GPIO I/O NA R14 gpio1_21 GPIO I/O NA V15 gpio1_22 GPIO I/O NA U15 gpio1_23 GPIO I/O NA T15 gpio1_24 GPIO I/O NA V16 gpio1_25 GPIO I/O NA U16 gpio1_26 GPIO I/O NA T16 gpio1_27 GPIO I/O NA V17 gpio1_28 GPIO I/O V18 U18 gpio1_29 GPIO I/O W8 V6 gpio1_3 GPIO I/O W13 T8 gpio1_30 GPIO I/O V14 U9 gpio1_31 GPIO I/O U15 V9 gpio1_4 GPIO I/O V13 U8 gpio1_5 GPIO I/O W14 V8 gpio1_6 GPIO I/O U14 R9 gpio1_7 GPIO I/O W15 T9 gpio1_8 GPIO I/O F19 E18 gpio1_9 GPIO I/O F18 E17 Table4-10.General-PurposeIOs/GPIO2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpio2_0 GPIO I/O U17 T13 gpio2_1 GPIO I/O V16 V12 gpio2_10 GPIO I/O W2 T1 gpio2_11 GPIO I/O W3 T2 gpio2_12 GPIO I/O V3 T3 gpio2_13 GPIO I/O U3 T4 gpio2_14 GPIO I/O V4 U1 gpio2_15 GPIO I/O W4 U2 gpio2_16 GPIO I/O U5 U3 gpio2_17 GPIO I/O V5 U4 gpio2_18 GPIO I/O N17 L17 gpio2_19 GPIO I/O N16 L16 gpio2_2 GPIO I/O V10 R7 gpio2_20 GPIO I/O P19 L15 gpio2_21 GPIO I/O P18 M16 gpio2_22 GPIO I/O U7 U5 gpio2_23 GPIO I/O T7 R5 gpio2_24 GPIO I/O W5 V5 gpio2_25 GPIO I/O W7 R6 gpio2_26 GPIO I/O H19 F17 gpio2_27 GPIO I/O H18 F18 gpio2_28 GPIO I/O H17 G15 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 57 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-10.General-PurposeIOs/GPIO2SignalsDescription(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpio2_29 GPIO I/O G18 G16 gpio2_3 GPIO I/O W9 T7 gpio2_30 GPIO I/O G19 G17 gpio2_31 GPIO I/O G17 G18 gpio2_4 GPIO I/O U8 U6 gpio2_5 GPIO I/O V8 T6 gpio2_6 GPIO I/O U1 R1 gpio2_7 GPIO I/O U2 R2 gpio2_8 GPIO I/O V1 R3 gpio2_9 GPIO I/O V2 R4 Table4-11.General-PurposeIOs/GPIO3SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gpio3_0 GPIO I/O J19 H16 gpio3_1 GPIO I/O J18 H17 gpio3_10 GPIO I/O M19 L18 gpio3_13 GPIO I/O NA F15 gpio3_14 GPIO I/O NA A13 gpio3_15 GPIO I/O NA B13 gpio3_16 GPIO I/O NA D12 gpio3_17 GPIO I/O NA C12 gpio3_18 GPIO I/O NA B12 gpio3_19 GPIO I/O NA C13 gpio3_2 GPIO I/O K19 J15 gpio3_20 GPIO I/O NA D13 gpio3_21 GPIO I/O NA A14 gpio3_3 GPIO I/O K17 J16 gpio3_4 GPIO I/O L19 J17 gpio3_5 GPIO I/O C18 C17 gpio3_6 GPIO I/O B19 C16 gpio3_7 GPIO I/O A15 C14 gpio3_8 GPIO I/O D14 B14 gpio3_9 GPIO I/O N19 K18 58 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.3 Miscellaneous Table4-12.Miscellaneous/MiscellaneousSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] clkout1 Clockout1 O C15 A15 clkout2 Clockout2 O B15 D14 ENZ_KALDO_1P8V Activelowenableinputforinternal I A7 B4 CAP_VDD_RTCvoltageregulator EXT_WAKEUP EXT_WAKEUPinput I B5 C5 nNMI ExternalInterrupttoARMCortex-A8core I C17 B18 nRESETIN_OUT ActivelowWarmReset I/OD A16 A10 OSC0_IN Highfrequencyoscillatorinput I W11 V10 OSC0_OUT Highfrequencyoscillatoroutput O W12 U11 OSC1_IN Lowfrequency(32.768kHz)RealTimeClock I A6 A6 oscillatorinput OSC1_OUT Lowfrequency(32.768kHz)RealTimeClock O A5 A4 oscillatoroutput PMIC_POWER_EN PMIC_POWER_ENoutput O C7 C6 porz ActivelowPoweronReset I E15 B15 RTC_PORz ActivelowRTCresetinput I B7 B5 tclkin TimerClockIn I B15 D14 xdma_event_intr0 ExternalDMAEventorInterrupt0 I C15 A15 xdma_event_intr1 ExternalDMAEventorInterrupt1 I B15 D14 xdma_event_intr2 ExternalDMAEventorInterrupt2 I B16,E18,K18 C15,C18,H18 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 59 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.3.1 eCAP Table4-13.eCAP/eCAP0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] eCAP0_in_PWM0_out EnhancedCapture0inputorAuxiliaryPWM0 I/O E18 C18 output Table4-14.eCAP/eCAP1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] eCAP1_in_PWM1_out EnhancedCapture1inputorAuxiliaryPWM1 I/O B16,B19,F17 C15,C16,E16 output Table4-15.eCAP/eCAP2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] eCAP2_in_PWM2_out EnhancedCapture2inputorAuxiliaryPWM2 I/O C18,E19 C12,C17,E15 output 60 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.3.2 eHRPWM Table4-16.eHRPWM/eHRPWM0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] ehrpwm0A eHRPWM0Aoutput. O A18 A13,A17 ehrpwm0B eHRPWM0Boutput. O B18 B13,B17 ehrpwm0_synci SyncinputtoeHRPWM0modulefroman I A17 A16,C12 externalpin ehrpwm0_synco SyncOutputfromeHRPWM0moduletoan O U12,V2,W4 R4,U12,U2,V14 externalpin ehrpwm0_tripzone_input eHRPWM0tripzoneinput I B17 B16,D12 Table4-17.eHRPWM/eHRPWM1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] ehrpwm1A eHRPWM1Aoutput. O U5 U14,U3 ehrpwm1B eHRPWM1Boutput. O V5 T14,U4 ehrpwm1_tripzone_input eHRPWM1tripzoneinput I V4 R13,U1 Table4-18.eHRPWM/eHRPWM2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] ehrpwm2A eHRPWM2Aoutput. O U1,V15 R1,U10 ehrpwm2B eHRPWM2Boutput. O U2,W16 R2,T10 ehrpwm2_tripzone_input eHRPWM2tripzoneinput I T12,V1 R3,T11 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 61 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.3.3 eQEP Table4-19.eQEP/eQEP0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] eQEP0A_in eQEP0Aquadratureinput I M18 B12,K16 eQEP0B_in eQEP0Bquadratureinput I L18 C13,K17 eQEP0_index eQEP0index. I/O K17 D13,J16 eQEP0_strobe eQEP0strobe. I/O P19 A14,L15 Table4-20.eQEP/eQEP1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] eQEP1A_in eQEP1Aquadratureinput I V6 R14,V2 eQEP1B_in eQEP1Bquadratureinput I U6 V15,V3 eQEP1_index eQEP1index. I/O W6 U15,V4 eQEP1_strobe eQEP1strobe. I/O V7 T15,T5 Table4-21.eQEP/eQEP2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] eQEP2A_in eQEP2Aquadratureinput I U13,W2 T1,T12 eQEP2B_in eQEP2Bquadratureinput I T13,W3 R12,T2 eQEP2_index eQEP2index. I/O V3,W17 T3,V13 eQEP2_strobe eQEP2strobe. I/O U3,V17 T4,U13 62 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.3.4 Timer Table4-22.Timer/Timer4SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] timer4 Timertriggerevent/PWMout I/O C15,C18,K17, A15,C17,J16, V10 R7 Table4-23.Timer/Timer5SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] timer5 Timertriggerevent/PWMout I/O D19,H19,R19, D17,F17,M18, V8 T6 Table4-24.Timer/Timer6SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] timer6 Timertriggerevent/PWMout I/O E17,H18,P17, D18,F18,M17, U8 U6 Table4-25.Timer/Timer7SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] timer7 Timertriggerevent/PWMout I/O B15,B19,F19, C16,D14,E18, W9 T7 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 63 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.4 PRU-ICSS Table4-26.PRU-ICSS/eCAPSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_ecap0_ecap_capin_apwm_o EnhancedcaptureinputorAuxiliaryPWMout I/O E18,V17 C18,U13 Table4-27.PRU-ICSS/ECATSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_edc_latch0_in DataIn I E17 D18 pr1_edc_latch1_in DataIn I D19 D17 pr1_edc_sync0_out DataOut O F19 E18 pr1_edc_sync1_out DataOut O F18 E17 pr1_edio_data_in0 DataIn I B17 B16 pr1_edio_data_in1 DataIn I A17 A16 pr1_edio_data_in2 DataIn I U7 U5 pr1_edio_data_in3 DataIn I T7 R5 pr1_edio_data_in4 DataIn I W5 V5 pr1_edio_data_in5 DataIn I W7 R6 pr1_edio_data_in6 DataIn I V14,V3 T3,U9 pr1_edio_data_in7 DataIn I U15,U3 T4,V9 pr1_edio_data_out0 DataOut O B17 B16 pr1_edio_data_out1 DataOut O A17 A16 pr1_edio_data_out2 DataOut O U7 U5 pr1_edio_data_out3 DataOut O T7 R5 pr1_edio_data_out4 DataOut O W5 V5 pr1_edio_data_out5 DataOut O W7 R6 pr1_edio_data_out6 DataOut O V14,V3 T3,U9 pr1_edio_data_out7 DataOut O U15,U3 T4,V9 pr1_edio_latch_in LatchIn I B18 B17 pr1_edio_sof StartofFrame O A18 A17 Table4-28.PRU-ICSS/MDIOSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_mdio_data MDIOData I/O U17 T13 pr1_mdio_mdclk MDIOClk O V16 V12 Table4-29.PRU-ICSS/MII0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_mii0_col MIICollisionDetect I W16 T10 pr1_mii0_crs MIICarrierSense I U17,W5 T13,V5 pr1_mii0_rxd0 MIIReceiveDatabit0 I V5 U4 pr1_mii0_rxd1 MIIReceiveDatabit1 I U5 U3 pr1_mii0_rxd2 MIIReceiveDatabit2 I W4 U2 pr1_mii0_rxd3 MIIReceiveDatabit3 I V4 U1 pr1_mii0_rxdv MIIReceiveDataValid I V7 T5 pr1_mii0_rxer MIIReceiveDataError I U6 V3 64 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-29.PRU-ICSS/MII0SignalsDescription(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_mii0_rxlink MIIReceiveLink I V6 V2 pr1_mii0_txd0 MIITransmitDatabit0 O W17,W3 T2,V13 pr1_mii0_txd1 MIITransmitDatabit1 O T13,W2 R12,T1 pr1_mii0_txd2 MIITransmitDatabit2 O U13,V2 R4,T12 pr1_mii0_txd3 MIITransmitDatabit3 O U12,V1 R3,U12 pr1_mii0_txen MIITransmitEnable O T12,U2 R2,T11 pr1_mii_mr0_clk MIIReceiveClock I W6 V4 pr1_mii_mt0_clk MIITransmitClock I U1,V15 R1,U10 Table4-30.PRU-ICSS/MII1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_mii1_col MIICollisionDetect I R15 T17 pr1_mii1_crs MIICarrierSense I V16,W7 R6,V12 pr1_mii1_rxd0 MIIReceiveDatabit0 I NA V16 pr1_mii1_rxd1 MIIReceiveDatabit1 I NA T15 pr1_mii1_rxd2 MIIReceiveDatabit2 I NA U15 pr1_mii1_rxd3 MIIReceiveDatabit3 I NA V15 pr1_mii1_rxdv MIIReceiveDataValid I NA T16 pr1_mii1_rxer MIIReceiveDataError I NA V17 pr1_mii1_rxlink MIIReceiveLink I V18 U18 pr1_mii1_txd0 MIITransmitDatabit0 O NA R14 pr1_mii1_txd1 MIITransmitDatabit1 O NA T14 pr1_mii1_txd2 MIITransmitDatabit2 O NA U14 pr1_mii1_txd3 MIITransmitDatabit3 O NA V14 pr1_mii1_txen MIITransmitEnable O W18 U17 pr1_mii_mr1_clk MIIReceiveClock I NA U16 pr1_mii_mt1_clk MIITransmitClock I NA R13 Table4-31.PRU-ICSS/UART0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_uart0_cts_n UARTCleartoSend I A18,E17 A17,D18 pr1_uart0_rts_n UARTRequesttoSend O B18,D19 B17,D17 pr1_uart0_rxd UARTReceiveData I B17,D18 B16,D16 pr1_uart0_txd UARTTransmitData O A17,C19 A16,D15 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 65 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.4.1 PRU0 Table4-32.PRU0/General-PurposeInputsSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_pru0_pru_r31_0 PRU0DataIn I NA A13 pr1_pru0_pru_r31_1 PRU0DataIn I NA B13 pr1_pru0_pru_r31_10 PRU0DataIn I H17 G15 pr1_pru0_pru_r31_11 PRU0DataIn I G18 G16 pr1_pru0_pru_r31_12 PRU0DataIn I G19 G17 pr1_pru0_pru_r31_13 PRU0DataIn I G17 G18 pr1_pru0_pru_r31_14 PRU0DataIn I W17 V13 pr1_pru0_pru_r31_15 PRU0DataIn I V17 U13 pr1_pru0_pru_r31_16 PRU0DataInCaptureEnable I B15,C19 D14,D15 pr1_pru0_pru_r31_2 PRU0DataIn I NA D12 pr1_pru0_pru_r31_3 PRU0DataIn I NA C12 pr1_pru0_pru_r31_4 PRU0DataIn I NA B12 pr1_pru0_pru_r31_5 PRU0DataIn I NA C13 pr1_pru0_pru_r31_6 PRU0DataIn I NA D13 pr1_pru0_pru_r31_7 PRU0DataIn I NA A14 pr1_pru0_pru_r31_8 PRU0DataIn I H19 F17 pr1_pru0_pru_r31_9 PRU0DataIn I H18 F18 Table4-33.PRU0/General-PurposeOutputsSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_pru0_pru_r30_0 PRU0DataOut O NA A13 pr1_pru0_pru_r30_1 PRU0DataOut O NA B13 pr1_pru0_pru_r30_10 PRU0DataOut O H17 G15 pr1_pru0_pru_r30_11 PRU0DataOut O G18 G16 pr1_pru0_pru_r30_12 PRU0DataOut O G19 G17 pr1_pru0_pru_r30_13 PRU0DataOut O G17 G18 pr1_pru0_pru_r30_14 PRU0DataOut O U13 T12 pr1_pru0_pru_r30_15 PRU0DataOut O T13 R12 pr1_pru0_pru_r30_2 PRU0DataOut O NA D12 pr1_pru0_pru_r30_3 PRU0DataOut O NA C12 pr1_pru0_pru_r30_4 PRU0DataOut O NA B12 pr1_pru0_pru_r30_5 PRU0DataOut O NA C13 pr1_pru0_pru_r30_6 PRU0DataOut O NA D13 pr1_pru0_pru_r30_7 PRU0DataOut O NA A14 pr1_pru0_pru_r30_8 PRU0DataOut O H19 F17 pr1_pru0_pru_r30_9 PRU0DataOut O H18 F18 66 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.4.2 PRU1 Table4-34.PRU1/General-PurposeInputsSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_pru1_pru_r31_0 PRU1DataIn I U1 R1 pr1_pru1_pru_r31_1 PRU1DataIn I U2 R2 pr1_pru1_pru_r31_10 PRU1DataIn I W5 V5 pr1_pru1_pru_r31_11 PRU1DataIn I W7 R6 pr1_pru1_pru_r31_12 PRU1DataIn I V14 U9 pr1_pru1_pru_r31_13 PRU1DataIn I U15 V9 pr1_pru1_pru_r31_14 PRU1DataIn I E19 E15 pr1_pru1_pru_r31_15 PRU1DataIn I F17 E16 pr1_pru1_pru_r31_16 PRU1DataInCaptureEnable I C15,D18 A15,D16 pr1_pru1_pru_r31_2 PRU1DataIn I V1 R3 pr1_pru1_pru_r31_3 PRU1DataIn I V2 R4 pr1_pru1_pru_r31_4 PRU1DataIn I W2 T1 pr1_pru1_pru_r31_5 PRU1DataIn I W3 T2 pr1_pru1_pru_r31_6 PRU1DataIn I V3 T3 pr1_pru1_pru_r31_7 PRU1DataIn I U3 T4 pr1_pru1_pru_r31_8 PRU1DataIn I U7 U5 pr1_pru1_pru_r31_9 PRU1DataIn I T7 R5 Table4-35.PRU1/General-PurposeOutputsSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] pr1_pru1_pru_r30_0 PRU1DataOut O U1 R1 pr1_pru1_pru_r30_1 PRU1DataOut O U2 R2 pr1_pru1_pru_r30_10 PRU1DataOut O W5 V5 pr1_pru1_pru_r30_11 PRU1DataOut O W7 R6 pr1_pru1_pru_r30_12 PRU1DataOut O V14 U9 pr1_pru1_pru_r30_13 PRU1DataOut O U15 V9 pr1_pru1_pru_r30_14 PRU1DataOut O E19 E15 pr1_pru1_pru_r30_15 PRU1DataOut O F17 E16 pr1_pru1_pru_r30_2 PRU1DataOut O V1 R3 pr1_pru1_pru_r30_3 PRU1DataOut O V2 R4 pr1_pru1_pru_r30_4 PRU1DataOut O W2 T1 pr1_pru1_pru_r30_5 PRU1DataOut O W3 T2 pr1_pru1_pru_r30_6 PRU1DataOut O V3 T3 pr1_pru1_pru_r30_7 PRU1DataOut O U3 T4 pr1_pru1_pru_r30_8 PRU1DataOut O U7 U5 pr1_pru1_pru_r30_9 PRU1DataOut O T7 R5 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 67 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.5 Removable Media Interfaces Table4-36.RemovableMediaInterfaces/MMC0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] mmc0_clk MMC/SD/SDIOClock I/O G19 G17 mmc0_cmd MMC/SD/SDIOCommand I/O G17 G18 mmc0_dat0 MMC/SD/SDIODataBus I/O G18 G16 mmc0_dat1 MMC/SD/SDIODataBus I/O H17 G15 mmc0_dat2 MMC/SD/SDIODataBus I/O H18 F18 mmc0_dat3 MMC/SD/SDIODataBus I/O H19 F17 mmc0_dat4 MMC/SD/SDIODataBus I/O N16 L16 mmc0_dat5 MMC/SD/SDIODataBus I/O N17 L17 mmc0_dat6 MMC/SD/SDIODataBus I/O M19 L18 mmc0_dat7 MMC/SD/SDIODataBus I/O N19 K18 mmc0_pow MMC/SDPowerSwitchControl O B16,K18 C15,H18 mmc0_sdcd SDCardDetect I B16,P17 A13,C15,M17 mmc0_sdwp SDWriteProtect I E18,R19 B12,C18,M18 Table4-37.RemovableMediaInterfaces/MMC1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] mmc1_clk MMC/SD/SDIOClock I/O L18,R19,V14 K17,M18,U9 mmc1_cmd MMC/SD/SDIOCommand I/O M18,P17,U15 K16,M17,V9 mmc1_dat0 MMC/SD/SDIODataBus I/O N19,V15,W10 K18,U10,U7 mmc1_dat1 MMC/SD/SDIODataBus I/O M19,V9,W16 L18,T10,V7 mmc1_dat2 MMC/SD/SDIODataBus I/O N17,T12,V12 L17,R8,T11 mmc1_dat3 MMC/SD/SDIODataBus I/O N16,U12,W13 L16,T8,U12 mmc1_dat4 MMC/SD/SDIODataBus I/O U13,V13 T12,U8 mmc1_dat5 MMC/SD/SDIODataBus I/O T13,W14 R12,V8 mmc1_dat6 MMC/SD/SDIODataBus I/O U14,W17 R9,V13 mmc1_dat7 MMC/SD/SDIODataBus I/O V17,W15 T9,U13 mmc1_sdcd SDCardDetect I R15 B13,T17 mmc1_sdwp SDWriteProtect I B17,D18 B16,D16 Table4-38.RemovableMediaInterfaces/MMC2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] mmc2_clk MMC/SD/SDIOClock I/O P19,R19,V16 L15,M18,V12 mmc2_cmd MMC/SD/SDIOCommand I/O K17,P17,U17 J16,M17,T13 mmc2_dat0 MMC/SD/SDIODataBus I/O L19,U13 J17,T12,V14 mmc2_dat1 MMC/SD/SDIODataBus I/O M17,T13 J18,R12,U14 mmc2_dat2 MMC/SD/SDIODataBus I/O N18,W17 K15,T14,V13 mmc2_dat3 MMC/SD/SDIODataBus I/O J19,V17,V18 H16,U13,U18 mmc2_dat4 MMC/SD/SDIODataBus I/O V15 U10,U15 mmc2_dat5 MMC/SD/SDIODataBus I/O W16 T10,T15 mmc2_dat6 MMC/SD/SDIODataBus I/O T12 T11,V16 mmc2_dat7 MMC/SD/SDIODataBus I/O U12 U12 mmc2_sdcd SDCardDetect I W18 D12,U17 mmc2_sdwp SDWriteProtect I A17,C19 A16,D15 68 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.6 Serial Communication Interfaces 4.3.6.1 CAN Table4-39.CAN/DCAN0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] dcan0_rx DCAN0ReceiveData I D19,F17,N18 D17,E16,K15 dcan0_tx DCAN0TransmitData O E17,E19,M17 D18,E15,J18 Table4-40.CAN/DCAN1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] dcan1_rx DCAN1ReceiveData I C19,F18,G17 D15,E17,G18 dcan1_tx DCAN1TransmitData O D18,F19,G19 D16,E18,G17 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 69 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.6.2 GEMAC_CPSW Table4-41.GEMAC_CPSW/MDIOSignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] mdio_clk MDIOClk O R19 M18 mdio_data MDIOData I/O P17 M17 Table4-42.GEMAC_CPSW/MII1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gmii1_col MIIColision I J19 H16 gmii1_crs MIICarrierSense I J18 H17 gmii1_rxclk MIIReceiveClock I M19 L18 gmii1_rxd0 MIIReceiveDatabit0 I P18 M16 gmii1_rxd1 MIIReceiveDatabit1 I P19 L15 gmii1_rxd2 MIIReceiveDatabit2 I N16 L16 gmii1_rxd3 MIIReceiveDatabit3 I N17 L17 gmii1_rxdv MIIReceiveDataValid I L19 J17 gmii1_rxer MIIReceiveDataError I K19 J15 gmii1_txclk MIITransmitClock I N19 K18 gmii1_txd0 MIITransmitDatabit0 O L18 K17 gmii1_txd1 MIITransmitDatabit1 O M18 K16 gmii1_txd2 MIITransmitDatabit2 O N18 K15 gmii1_txd3 MIITransmitDatabit3 O M17 J18 gmii1_txen MIITransmitEnable O K17 J16 Table4-43.GEMAC_CPSW/MII2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] gmii2_col MIIColision I V18 U18 gmii2_crs MIICarrierSense I R15 T17 gmii2_rxclk MIIReceiveClock I NA T15 gmii2_rxd0 MIIReceiveDatabit0 I NA V17 gmii2_rxd1 MIIReceiveDatabit1 I NA T16 gmii2_rxd2 MIIReceiveDatabit2 I NA U16 gmii2_rxd3 MIIReceiveDatabit3 I NA V16 gmii2_rxdv MIIReceiveDataValid I NA V14 gmii2_rxer MIIReceiveDataError I W18 U17 gmii2_txclk MIITransmitClock I NA U15 gmii2_txd0 MIITransmitDatabit0 O NA V15 gmii2_txd1 MIITransmitDatabit1 O NA R14 gmii2_txd2 MIITransmitDatabit2 O NA T14 gmii2_txd3 MIITransmitDatabit3 O NA U14 gmii2_txen MIITransmitEnable O NA R13 Table4-44.GEMAC_CPSW/RGMII1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] rgmii1_rclk RGMIIReceiveClock I M19 L18 70 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-44.GEMAC_CPSW/RGMII1SignalsDescription(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] rgmii1_rctl RGMIIReceiveControl I L19 J17 rgmii1_rd0 RGMIIReceiveDatabit0 I P18 M16 rgmii1_rd1 RGMIIReceiveDatabit1 I P19 L15 rgmii1_rd2 RGMIIReceiveDatabit2 I N16 L16 rgmii1_rd3 RGMIIReceiveDatabit3 I N17 L17 rgmii1_tclk RGMIITransmitClock O N19 K18 rgmii1_tctl RGMIITransmitControl O K17 J16 rgmii1_td0 RGMIITransmitDatabit0 O L18 K17 rgmii1_td1 RGMIITransmitDatabit1 O M18 K16 rgmii1_td2 RGMIITransmitDatabit2 O N18 K15 rgmii1_td3 RGMIITransmitDatabit3 O M17 J18 Table4-45.GEMAC_CPSW/RGMII2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] rgmii2_rclk RGMIIReceiveClock I NA T15 rgmii2_rctl RGMIIReceiveControl I NA V14 rgmii2_rd0 RGMIIReceiveDatabit0 I NA V17 rgmii2_rd1 RGMIIReceiveDatabit1 I NA T16 rgmii2_rd2 RGMIIReceiveDatabit2 I NA U16 rgmii2_rd3 RGMIIReceiveDatabit3 I NA V16 rgmii2_tclk RGMIITransmitClock O NA U15 rgmii2_tctl RGMIITransmitControl O NA R13 rgmii2_td0 RGMIITransmitDatabit0 O NA V15 rgmii2_td1 RGMIITransmitDatabit1 O NA R14 rgmii2_td2 RGMIITransmitDatabit2 O NA T14 rgmii2_td3 RGMIITransmitDatabit3 O NA U14 Table4-46.GEMAC_CPSW/RMII1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] rmii1_crs_dv RMIICarrierSense/DataValid I J18 H17 rmii1_refclk RMIIReferenceClock I/O K18 H18 rmii1_rxd0 RMIIReceiveDatabit0 I P18 M16 rmii1_rxd1 RMIIReceiveDatabit1 I P19 L15 rmii1_rxer RMIIReceiveDataError I K19 J15 rmii1_txd0 RMIITransmitDatabit0 O L18 K17 rmii1_txd1 RMIITransmitDatabit1 O M18 K16 rmii1_txen RMIITransmitEnable O K17 J16 Table4-47.GEMAC_CPSW/RMII2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] rmii2_crs_dv RMIICarrierSense/DataValid I R15,U17 T13,T17,U16 rmii2_refclk RMIIReferenceClock I/O J19 H16 rmii2_rxd0 RMIIReceiveDatabit0 I NA V17 rmii2_rxd1 RMIIReceiveDatabit1 I NA T16 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 71 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table4-47.GEMAC_CPSW/RMII2SignalsDescription(continued) TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] rmii2_rxer RMIIReceiveDataError I W18 U17 rmii2_txd0 RMIITransmitDatabit0 O NA V15 rmii2_txd1 RMIITransmitDatabit1 O NA R14 rmii2_txen RMIITransmitEnable O NA R13 72 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.6.3 I2C Table4-48.I2C/I2C0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] I2C0_SCL I2C0Clock I/OD B19 C16 I2C0_SDA I2C0Data I/OD C18 C17 Table4-49.I2C/I2C1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] I2C1_SCL I2C1Clock I/OD A17,C19,F18, A16,D15,E17, K19 J15 I2C1_SDA I2C1Data I/OD B17,D18,F19, B16,D16,E18, J18 H17 Table4-50.I2C/I2C2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] I2C2_SCL I2C2Clock I/OD B18,D19,F17 B17,D17,E16 I2C2_SDA I2C2Data I/OD A18,E17,E19 A17,D18,E15 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 73 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.6.4 McASP Table4-51.McASP/MCASP0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] mcasp0_aclkr McASP0ReceiveBitClock I/O L19,V18,V6 B12,J17,U18, V2 mcasp0_aclkx McASP0TransmitBitClock I/O N19,V4 A13,K18,U1, V16 mcasp0_ahclkr McASP0ReceiveMasterClock I/O V5 C12,U4 mcasp0_ahclkx McASP0TransmitMasterClock I/O N18,V7 A14,K15,T5 mcasp0_axr0 McASP0SerialData(IN/OUT) I/O N17,U5 D12,L17,T16, U3 mcasp0_axr1 McASP0SerialData(IN/OUT) I/O N16,W6 D13,L16,V17, V4 mcasp0_axr2 McASP0SerialData(IN/OUT) I/O J19,V5,V6 B12,C12,H16, U4,V2 mcasp0_axr3 McASP0SerialData(IN/OUT) I/O P18,U6,V7 A14,C13,M16, T5,V3 mcasp0_fsr McASP0ReceiveFrameSync I/O M17,U6,V16 C13,J18,V12, V3 mcasp0_fsx McASP0TransmitFrameSync I/O M19,W4 B13,L18,U16, U2 Table4-52.McASP/MCASP1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] mcasp1_aclkr McASP1ReceiveBitClock I/O L18,P18 K17,M16 mcasp1_aclkx McASP1TransmitBitClock I/O J18,L19 B12,H17,J17 mcasp1_ahclkr McASP1ReceiveMasterClock I/O P18 M16 mcasp1_ahclkx McASP1TransmitMasterClock I/O K18,P18 H18,M16 mcasp1_axr0 McASP1SerialData(IN/OUT) I/O K17,N18 D13,J16,K15 mcasp1_axr1 McASP1SerialData(IN/OUT) I/O M18 A14,K16 mcasp1_axr2 McASP1SerialData(IN/OUT) I/O J19,L18 H16,K17 mcasp1_axr3 McASP1SerialData(IN/OUT) I/O K18,P19 H18,L15 mcasp1_fsr McASP1ReceiveFrameSync I/O M18,P19 K16,L15 mcasp1_fsx McASP1TransmitFrameSync I/O K19,M17 C13,J15,J18 74 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 4.3.6.5 SPI Table4-53.SPI/SPI0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] spi0_cs0 SPIChipSelect I/O A17 A16 spi0_cs1 SPIChipSelect I/O B16 C15 spi0_d0 SPIData I/O B18 B17 spi0_d1 SPIData I/O B17 B16 spi0_sclk SPIClock I/O A18 A17 Table4-54.SPI/SPI1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] spi1_cs0 SPIChipSelect I/O E17,E19,F18, C12,D18,E15, K18 E17,H18 spi1_cs1 SPIChipSelect I/O C15,D19,E18, A15,C18,D17, F17 E16 spi1_d0 SPIData I/O F19,J18 B13,E18,H17 spi1_d1 SPIData I/O F18,K19 D12,E17,J15 spi1_sclk SPIClock I/O E18,J19 A13,C18,H16 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 75 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.6.6 UART Table4-55.UART/UART0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] uart0_ctsn UARTCleartoSend I F19 E18 uart0_rtsn UARTRequesttoSend O F18 E17 uart0_rxd UARTReceiveData I E19 E15 uart0_txd UARTTransmitData O F17 E16 Table4-56.UART/UART1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] uart1_ctsn UARTCleartoSend I E17 D18 uart1_dcdn UARTDataCarrierDetect I H19,N19 F17,K18 uart1_dsrn UARTDataSetReady I H18,M19 F18,L18 uart1_dtrn UARTDataTerminalReady O H17,N17 G15,L17 uart1_rin UARTRingIndicator I G18,N16 G16,L16 uart1_rtsn UARTRequesttoSend O D19 D17 uart1_rxd UARTReceiveData I D18 D16 uart1_txd UARTTransmitData O C19 D15 Table4-57.UART/UART2SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] uart2_ctsn UARTCleartoSend I C18,V4 C17,U1 uart2_rtsn UARTRequesttoSend O B19,W4 C16,U2 uart2_rxd UARTReceiveData I A18,G19,J18, A17,G17,H17, N19 K18 uart2_txd UARTTransmitData O B18,G17,K19, B17,G18,J15, M19 L18 Table4-58.UART/UART3SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] uart3_ctsn UARTCleartoSend I G19,P17,U5 G17,M17,U3 uart3_rtsn UARTRequesttoSend O G17,R19,V5 G18,M18,U4 uart3_rxd UARTReceiveData I B16,H17,N17 C15,G15,L17 uart3_txd UARTTransmitData O E18,G18,N16 C18,G16,L16 Table4-59.UART/UART4SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] uart4_ctsn UARTCleartoSend I H19,V6 F17,V2 uart4_rtsn UARTRequesttoSend O H18,U6 F18,V3 uart4_rxd UARTReceiveData I F19,M17,R15 E18,J18,T17 uart4_txd UARTTransmitData O F18,N18,W18 E17,K15,U17 76 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table4-60.UART/UART5SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] uart5_ctsn UARTCleartoSend I H17,J18,W6 G15,H17,V4 uart5_rtsn UARTRequesttoSend O G18,K19,V7 G16,J15,T5 uart5_rxd UARTReceiveData I J19,P17,W4, H16,M17,U2,V4 W6 uart5_txd UARTTransmitData O K18,L19,R19, H18,J17,M18, V4 U1 Copyright©2011–2020,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 77 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 4.3.6.7 USB Table4-61.USB/USB0SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] USB0_CE USB0ActivehighChargerEnableoutput A T18 M15 USB0_DM USB0Dataminus A U18 N18 USB0_DP USB0Dataplus A U19 N17 USB0_DRVVBUS USB0ActivehighVBUScontroloutput O G16 F16 USB0_ID USB0ID(Micro-AorMicro-BPlug) A V19 P16 USB0_VBUS USB0VBUS A T19 P15 Table4-62.USB/USB1SignalsDescription TYPE SIGNALNAME[1] DESCRIPTION[2] ZCEBALL[4] ZCZBALL[4] [3] USB1_CE USB1ActivehighChargerEnableoutput A NA P18 USB1_DM USB1Dataminus A NA R18 USB1_DP USB1Dataplus A NA R17 USB1_DRVVBUS USB1ActivehighVBUScontroloutput O NA F15 USB1_ID USB1ID(Micro-AorMicro-BPlug) A NA P17 USB1_VBUS USB1VBUS A NA T18 78 TerminalConfigurationandFunctions Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 5 Specifications 5.1 Absolute Maximum Ratings overjunctiontemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT VDD_MPU(3) SupplyvoltagefortheMPUcoredomain –0.5 1.5 V VDD_CORE Supplyvoltageforthecoredomain –0.5 1.5 V CAP_VDD_RTC(4) SupplyvoltagefortheRTCcoredomain –0.5 1.5 V VPP(5) SupplyvoltagefortheFUSEROMdomain –0.5 2.2 V VDDS_RTC SupplyvoltagefortheRTCdomain –0.5 2.1 V VDDS_OSC SupplyvoltagefortheSystemoscillator –0.5 2.1 V VDDS_SRAM_CORE_BG SupplyvoltagefortheCoreSRAMLDOs –0.5 2.1 V VDDS_SRAM_MPU_BB SupplyvoltagefortheMPUSRAMLDOs –0.5 2.1 V VDDS_PLL_DDR SupplyvoltagefortheDPLLDDR –0.5 2.1 V VDDS_PLL_CORE_LCD SupplyvoltagefortheDPLLCoreandLCD –0.5 2.1 V VDDS_PLL_MPU SupplyvoltagefortheDPLLMPU –0.5 2.1 V VDDS_DDR SupplyvoltagefortheDDRI/Odomain –0.5 2.1 V VDDS Supplyvoltageforalldual-voltageI/Odomains –0.5 2.1 V VDDA1P8V_USB0 SupplyvoltageforUSBPHY –0.5 2.1 V VDDA1P8V_USB1(6) SupplyvoltageforUSBPHY –0.5 2.1 V VDDA_ADC SupplyvoltageforADC –0.5 2.1 V VDDSHV1 Supplyvoltageforthedual-voltageI/Odomain –0.5 3.8 V VDDSHV2(6) Supplyvoltageforthedual-voltageI/Odomain –0.5 3.8 V VDDSHV3(6) Supplyvoltageforthedual-voltageI/Odomain –0.5 3.8 V VDDSHV4 Supplyvoltageforthedual-voltageI/Odomain –0.5 3.8 V VDDSHV5 Supplyvoltageforthedual-voltageI/Odomain –0.5 3.8 V VDDSHV6 Supplyvoltageforthedual-voltageI/Odomain –0.5 3.8 V VDDA3P3V_USB0 SupplyvoltageforUSBPHY –0.5 4 V VDDA3P3V_USB1(6) SupplyvoltageforUSBPHY –0.5 4 V USB0_VBUS(7) SupplyvoltageforUSBVBUScomparatorinput –0.5 5.25 V USB1_VBUS(6)(7) SupplyvoltageforUSBVBUScomparatorinput –0.5 5.25 V DDR_VREF SupplyvoltagefortheDDRSSTLandHSTLreferencevoltage –0.3 1.1 V Steadystatemaxvoltage atallI/Opins(8) –0.5VtoI/Osupplyvoltage+0.3V USB0_ID(9) SteadystatemaximumvoltagefortheUSBIDinput –0.5 2.1 V USB1_ID(6)(9) SteadystatemaximumvoltagefortheUSBIDinput –0.5 2.1 V Transientovershootand 25%ofcorrespondingI/Osupply undershootspecificationat voltageforupto30%ofsignal I/Oterminal period ClassII(105°C) 45 mA 1.8-Vmode –100 100 3.3-Vmode;appliestoallI/Opinsexceptthose Latch-upperformance(10) includedinlatch-uppingroupsA(12),B(13),andC(14) –100 100 ClassII(125°C) 3.3-Vmode;appliestolatch-uppingroupA(12) –35 100 mA 3.3-Vmode;appliestolatch-uppingroupB(13) –45 75 3.3-Vmode;appliestolatch-uppingroupC(14) –100 70 Storagetemperature, Tstg(11) –55 155 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesarewithrespecttotheirassociatedVSSorVSSA_x. (3) NotavailableontheZCEpackage.VDD_MPUismergedwithVDD_COREontheZCEpackage. (4) ThissupplyissourcedfromaninternalLDOwhenRTC_KALDO_ENnislow.IfRTC_KALDO_ENnishigh,thissupplymustbesourced fromanexternalpowersupply. Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 79 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Absolute Maximum Ratings (continued) overjunctiontemperaturerange(unlessotherwisenoted)(1)(2) (5) Duringfunctionaloperation,thispinisanoconnect. (6) NotavailableontheZCEpackage. (7) Thisterminalisconnectedtoafail-safeI/OanddoesnothaveadependenceonanyI/Osupplyvoltage. (8) ThisparameterappliestoallI/Oterminalswhicharenotfail-safeandtherequirementappliestoallvaluesofI/Osupplyvoltage.For example,ifthevoltageappliedtoaspecificI/Osupplyis0voltsthevalidinputvoltagerangeforanyI/Opoweredbythatsupplywillbe –0.5to+0.3V.Applyspecialattentionanytimeperipheraldevicesarenotpoweredfromthesamepowersourcesusedtopowerthe respectiveI/Osupply.Itisimportanttheattachedperipheralneversourcesavoltageoutsidethevalidinputvoltagerange,including powersupplyramp-upandramp-downsequences. (9) ThisterminalisconnectedtoanalogcircuitsintherespectiveUSBPHY.Thecircuitsourcesaknowncurrentwhilemeasuringthe voltagetodetermineiftheterminalisconnectedtoVSSA_USBwitharesistancelessthan10Ωorgreaterthan100kΩ.Theterminal shouldbeconnectedtogroundforUSBhostoperationoropen-circuitforUSBperipheraloperation,andshouldneverbeconnectedto anyexternalvoltagesource. (10) BasedonJEDECJESD78D[ICLatch-UpTest]. (11) Fortapeandreelthestoragetemperaturerangeis[–10°C;+50°C]withamaximumrelativehumidityof70%.TIrecommendsreturning toambientroomtemperaturebeforeusage. (12) Latch-uppingroupA:V7,R8,T8,U8,V8,R9,T9,U10,T10,T11,U12,T12,R12,V13,U13,R13,V14,U14,T14,R14,V15,U15,T15, V16,U16,T16,V17,U17,U18,U9,V9,T13,V12,V4 (13) Latch-uppingroupB:R1,R2,R3,R4,T1,T2,T3,V2,V3 (14) Latch-uppingroupC:T4,U1,U2,U3,U4,V5,F17,F18,G15,G16,G17,G18,H16,H17,J15,J16,J17,J18,K15,K16,K17,K18, L18,L17,L16,L15,M16,H18,M17,M18 Fail-safeI/OterminalsaredesignedsuchtheydonothavedependenciesontherespectiveI/Opowersupplyvoltage.Thisallows externalvoltagesourcestobeconnectedtotheseI/OterminalswhentherespectiveI/Opowersuppliesareturnedoff.TheUSB0_VBUS andUSB1_VBUSaretheonlyfail-safeI/Oterminals.AllotherI/Oterminalsarenotfail-safeandthevoltageappliedtothemshouldbe limitedtothevaluedefinedbythesteadystatemax.VoltageatallI/OpinsparameterinSection5.1. 5.2 ESD Ratings VALUE UNIT Electrostaticdischarge HumanBodyModel(HBM),perANSI/ESDA/JEDECJS001(1) ±2000 V V ESD (ESD)performance: ChargedDeviceModel(CDM),perJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 80 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 5.3 Power-On Hours (POH) Table5-1.ReliabilityData(1)(2)(3)(4) COMMERCIAL INDUSTRIAL EXTENDED INDUSTRIALEXTENDED OPERATING CONDITION JUNCTION LIFETIME JUNCTION LIFETIME JUNCTION LIFETIME JUNCTION LIFETIME TEMP(T ) (POH)(5) TEMP(T ) (POH)(5) TEMP(T ) (POH)(5) TEMP(T ) (POH)(5) J J J J Nitro 0°Cto90°C 100K –40°Cto90°C 100K –40°Cto105°C 37K –40°Cto125°C – Turbo 0°Cto90°C 100K –40°Cto90°C 100K –40°Cto105°C 80K –40°Cto125°C – OPP120 0°Cto90°C 100K –40°Cto90°C 100K –40°Cto105°C 100K –40°Cto125°C – OPP100 0°Cto90°C 100K –40°Cto90°C 100K –40°Cto105°C 100K –40°Cto125°C 35K OPP50 0°Cto90°C 100K –40°Cto90°C 100K –40°Cto105°C 100K –40°Cto125°C 95K (1) Thepower-onhours(POH)informationinthistableisprovidedsolelyforyourconvenienceanddoesnotextendormodifythewarranty providedunderTI'sstandardtermsandconditionsforTIsemiconductorproducts. (2) Toavoidsignificantdegradation,thedevicepower-onhours(POH)mustbelimitedasdescribedinthistable. (3) Logicfunctionsandparametervaluesarenotassuredoutoftherangespecifiedintherecommendedoperatingconditions. (4) ThepreviousnotationscannotbedeemedawarrantyordeemedtoextendormodifythewarrantyunderTI'sstandardtermsand conditionsforTIsemiconductorproducts. (5) POH=Power-onhourswhenthedeviceisfullyfunctional. 5.4 Operating Performance Points (OPPs) DeviceOPPsaredefinedinTable5-2throughTable5-9. Table5-2.VDD_COREOPPsfor ZCZPackage DeviceRev."AorNewer"(1) DevicVeDDR_eCv.O"RAEoOrNPPewer" MIN VDDN_OCMORE MAX DDDDRR3L3(,2) DDR2(2) mDDR(2) L3andL4 200and100 OPP100 1.056V 1.100V 1.144V 400MHz 266MHz 200MHz MHz 100and50 OPP50 0.912V 0.950V 0.988V — 125MHz 90MHz MHz (1) FrequenciesinthistableindicatemaximumperformanceforagivenOPPcondition. (2) Thisparameterrepresentsthemaximummemoryclockfrequency.Becausedataistransferredonbothedgesoftheclock,double-data rate(DDR),themaximumdatarateistwotimesthemaximummemoryclockfrequencydefinedinthistable. Table5-3.VDD_MPUOPPsfor ZCZPackage WithDeviceRevisionCode "Blank"(1) VDD_MPUOPP VDD_MPU ARM(A8) DeviceRev."Blank" MIN NOM MAX Turbo 1.210V 1.260V 1.326V 720MHz OPP120 1.152V 1.200V 1.248V 600MHz OPP100(2) 1.056V 1.100V 1.144V 500MHz OPP100(3) 1.056V 1.100V 1.144V 275MHz (1) FrequenciesinthistableindicatemaximumperformanceforagivenOPPcondition. (2) AppliestoallorderableAM335__ZCZ_50(500-MHzspeedgrade)orhigherdevices. (3) AppliestoallorderableAM335__ZCZ_27(275-MHzspeedgrade)devices. Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 81 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table5-4.ValidCombinationsofVDD_COREand VDD_MPUOPPsfor ZCZPackage WithDeviceRevisionCode "Blank" VDD_CORE VDD_MPU OPP50 OPP100 OPP100 OPP100 OPP100 OPP120 OPP100 Turbo Table5-5.VDD_COREOPPsforZCEPackage WithDeviceRevisionCode "Blank"(1) VDD_CORE VDD_MPU(2) DevOicPePRev. MIN NOM MAX ARM(A8) DDDDRR3L3(,3) DDR2(3) mDDR(3) L3andL4 "Blank" 200and100 OPP100 1.056V 1.100V 1.144V 500MHz 400MHz 266MHz 200MHz MHz 200and100 OPP100 1.056V 1.100V 1.144V 275MHz 400MHz 266MHz 200MHz MHz (1) FrequenciesinthistableindicatemaximumperformanceforagivenOPPcondition. (2) VDD_MPUismergedwithVDD_COREontheZCEpackage. (3) Thisparameterrepresentsthemaximummemoryclockfrequency.Becausedataistransferredonbothedgesoftheclock,double-data rate(DDR),themaximumdatarateistwotimesthemaximummemoryclockfrequencydefinedinthistable. Table5-6.VDD_COREOPPsfor ZCZPackage WithDeviceRevisionCode "A"orNewer(1) RVeDvD"_AC"OoRrENOewPePr MIN VDDN_OCMORE MAX DDDDRR3L3(,2) DDR2(2) mDDR(2) L3andL4 Industrialextended temperature(–40°C 333MHz OPP100 to125°C) 1.056V 1.100V 1.144V 266MHz 200MHz 200and100 MHz Allother 400MHz temperatureranges Industrialextended temperature(–40°C OPP50 to125°C) 0.912V 0.950V 0.988V — 125MHz 90MHz 100and50 MHz Allother temperatureranges (1) FrequenciesinthistableindicatemaximumperformanceforagivenOPPcondition. (2) Thisparameterrepresentsthemaximummemoryclockfrequency.Becausedataistransferredonbothedgesoftheclock,double-data rate(DDR),themaximumdatarateistwotimesthemaximummemoryclockfrequencydefinedinthistable. Table5-7.VDD_MPUOPPsfor ZCZPackage WithDeviceRevisionCode "A"orNewer(1) VDD_MPUOPP VDD_MPU ARM(A8) Rev"A"orNewer MIN NOM MAX Nitro 1.272V 1.325V 1.378V 1GHz Turbo 1.210V 1.260V 1.326V 800MHz OPP120 1.152V 1.200V 1.248V 720MHz OPP100(2) 1.056V 1.100V 1.144V 600MHz OPP100(3) 1.056V 1.100V 1.144V 300MHz OPP50 0.912V 0.950V 0.988V 300MHz 82 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 (1) FrequenciesinthistableindicatemaximumperformanceforagivenOPPcondition. (2) AppliestoallorderableAM335__ZCZ_60(600-MHzspeedgrade)orhigherdevices. (3) AppliestoallorderableAM335__ZCZ_30(300-MHzspeedgrade)devices. Table5-8.ValidCombinationsofVDD_COREand VDD_MPUOPPsfor ZCZPackageWithDevice RevisionCode"A"orNewer VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 OPP100 Turbo OPP100 Nitro Table5-9.VDD_COREOPPsforZCEPackage WithDeviceRevisionCode "A"orNewer(1) VDD_CORE VDD_MPU(2) RevO"PAP"or MIN NOM MAX ARM(A8) DDDDRR3L3(,3) DDR2(3) mDDR(3) L3andL4 newer 200and100 OPP100 1.056V 1.100V 1.144V 600MHz 400MHz 266MHz 200MHz MHz 200and100 OPP100 1.056V 1.100V 1.144V 300MHz 400MHz 266MHz 200MHz MHz 100and50 OPP50 0.912V 0.950V 0.988V 300MHz – 125MHz 90MHz MHz (1) FrequenciesinthistableindicatemaximumperformanceforagivenOPPcondition. (2) VDD_MPUismergedwithVDD_COREontheZCEpackage. (3) Thisparameterrepresentsthemaximummemoryclockfrequency.Becausedataistransferredonbothedgesoftheclock,double-data rate(DDR),themaximumdatarateistwotimesthemaximummemoryclockfrequencydefinedinthistable. Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 83 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 5.5 Recommended Operating Conditions overjunctiontemperaturerange(unlessotherwisenoted) SUPPLYNAME DESCRIPTION MIN NOM MAX UNIT Supplyvoltagerangeforcore 1.056 1.100 1.144 domain;OPP100 VDD_CORE(1) V Supplyvoltagerangeforcore 0.912 0.950 0.988 domain;OPP50 SupplyvoltagerangeforMPU 1.272 1.325 1.378 domain,Nitro SupplyvoltagerangeforMPU 1.210 1.260 1.326 domain;Turbo VDD_MPU(1)(2) SupplyvoltagerangeforMPU 1.152 1.200 1.248 V domain;OPP120 SupplyvoltagerangeforMPU 1.056 1.100 1.144 domain;OPP100 SupplyvoltagerangeforMPU 0.912 0.950 0.988 domain;OPP50 CAP_VDD_RTC(3) SupplyvoltagerangeforRTC 0.900 1.100 1.250 V domaininput SupplyvoltagerangeforRTC VDDS_RTC 1.710 1.800 1.890 V domain SupplyvoltagerangeforDDR 1.710 1.800 1.890 I/Odomain(DDR2) SupplyvoltagerangeforDDR VDDS_DDR 1.425 1.500 1.575 V I/Odomain(DDR3) SupplyvoltagerangeforDDR 1.283 1.350 1.418 I/Odomain(DDR3L) VDDS(4) Supplyvoltagerangeforalldual- 1.710 1.800 1.890 V voltageI/Odomains SupplyvoltagerangeforCore VDDS_SRAM_CORE_BG 1.710 1.800 1.890 V SRAMLDOs,analog SupplyvoltagerangeforMPU VDDS_SRAM_MPU_BB 1.710 1.800 1.890 V SRAMLDOs,analog VDDS_PLL_DDR(5) SupplyvoltagerangeforDPLL 1.710 1.800 1.890 V DDR,analog VDDS_PLL_CORE_LCD(5) SupplyvoltagerangeforDPLL 1.710 1.800 1.890 V COREandLCD,analog VDDS_PLL_MPU(5) SupplyvoltagerangeforDPLL 1.710 1.800 1.890 V MPU,analog Supplyvoltagerangeforsystem VDDS_OSC 1.710 1.800 1.890 V oscillatorI/Os,analog Supplyvoltagerangefor VDDA1P8V_USB0(5) USBPHYandPERDPLL, 1.710 1.800 1.890 V analog,1.8V VDDA1P8V_USB1(6) SupplyvoltagerangeforUSB 1.710 1.800 1.890 V PHY,analog,1.8V SupplyvoltagerangeforUSB VDDA3P3V_USB0 3.135 3.300 3.465 V PHY,analog,3.3V VDDA3P3V_USB1(6) SupplyvoltagerangeforUSB 3.135 3.300 3.465 V PHY,analog,3.3V SupplyvoltagerangeforADC, VDDA_ADC 1.710 1.800 1.890 V analog Supplyvoltagerangefordual- VDDSHV1 voltageI/Odomain(1.8-V 1.710 1.800 1.890 V operation) Supplyvoltagerangefordual- VDDSHV2(6) voltageI/Odomain(1.8-V 1.710 1.800 1.890 V operation) 84 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Recommended Operating Conditions (continued) overjunctiontemperaturerange(unlessotherwisenoted) SUPPLYNAME DESCRIPTION MIN NOM MAX UNIT Supplyvoltagerangefordual- VDDSHV3(6) voltageI/Odomain(1.8-V 1.710 1.800 1.890 V operation) Supplyvoltagerangefordual- VDDSHV4 voltageI/Odomain(1.8-V 1.710 1.800 1.890 V operation) Supplyvoltagerangefordual- VDDSHV5 voltageI/Odomain(1.8-V 1.710 1.800 1.890 V operation) Supplyvoltagerangefordual- VDDSHV6 voltageI/Odomain(1.8-V 1.710 1.800 1.890 V operation) Supplyvoltagerangefordual- VDDSHV1 voltageI/Odomain(3.3-V 3.135 3.300 3.465 V operation) Supplyvoltagerangefordual- VDDSHV2(6) voltageI/Odomain(3.3-V 3.135 3.300 3.465 V operation) Supplyvoltagerangefordual- VDDSHV3(6) voltageI/Odomain(3.3-V 3.135 3.300 3.465 V operation) Supplyvoltagerangefordual- VDDSHV4 voltageI/Odomain(3.3-V 3.135 3.300 3.465 V operation) Supplyvoltagerangefordual- VDDSHV5 voltageI/Odomain(3.3-V 3.135 3.300 3.465 V operation) Supplyvoltagerangefordual- VDDSHV6 voltageI/Odomain(3.3-V 3.135 3.300 3.465 V operation) VoltagerangeforDDRSSTLand DDR_VREF HSTLreferenceinput(DDR2, 0.49×VDDS_DDR 0.50×VDDS_DDR 0.51×VDDS_DDR V DDR3,DDR3L) VoltagerangeforUSBVBUS USB0_VBUS 0.000 5.000 5.250 V comparatorinput USB1_VBUS(6) VoltagerangeforUSBVBUS 0.000 5.000 5.250 V comparatorinput VoltagerangefortheUSBID USB0_ID (7) V input USB1_ID(6) VoltagerangefortheUSBID (7) V input Commercialtemperature 0 90 Operatingtemperature Industrialtemperature –40 90 °C range,TJ Extendedtemperature –40 105 IndustrialExtendedtemperature –40 125 (1) ThesupplyvoltagedefinedbyOPP100shouldbeappliedtothispowerdomainbeforethedeviceisreleasedfromreset. (2) NotavailableontheZCEpackage.VDD_MPUismergedwithVDD_COREontheZCEpackage. (3) ThissupplyissourcedfromaninternalLDOwhenRTC_KALDO_ENnislow.IfRTC_KALDO_ENnishigh,thissupplymustbesourced fromanexternalpowersupply. (4) VDDSshouldbesuppliedirrespectiveof1.8-or3.3-Vmodeofoperationofthedual-voltageI/Os. (5) Formoredetailsonpowersupplyrequirements,seeSection6.1.4. (6) NotavailableontheZCEpackage. (7) ThisterminalisconnectedtoanalogcircuitsintherespectiveUSBPHY.Thecircuitsourcesaknowncurrentwhilemeasuringthe voltagetodetermineiftheterminalisconnectedtoVSSA_USBwitharesistancelessthan10Ωorgreaterthan100kΩ.Theterminal shouldbeconnectedtogroundforUSBhostoperationoropen-circuitforUSBperipheraloperation,andshouldneverbeconnectedto anyexternalvoltagesource. Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 85 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 5.6 Power Consumption Summary Table5-10summarizesthepowerconsumptionattheAM335xpowerterminals. Table5-10.MaximumCurrentRatingsat AM335xPowerTerminals(1) SUPPLYNAME DESCRIPTION MAX UNIT Maximumcurrentratingforthecoredomain;OPP100 400 VDD_CORE(2) mA Maximumcurrentratingforthecoredomain;OPP50 250 MaximumcurrentratingfortheMPUdomain;Nitro at1GHz 1000 at800MHz 800 MaximumcurrentratingfortheMPUdomain;Turbo at720MHz 720 at720MHz 720 MaximumcurrentratingfortheMPUdomain;OPP120 at600MHz 600 VDD_MPU(2) at600MHz 600 mA at500MHz 500 MaximumcurrentratingfortheMPUdomain;OPP100 at300MHz 380 at275MHz 350 at300MHz 330 MaximumcurrentratingfortheMPUdomain;OPP50 at275MHz 300 CAP_VDD_RTC(3) MaximumcurrentratingforRTCdomaininputandLDOoutput 2 mA VDDS_RTC MaximumcurrentratingfortheRTCdomain 5 mA VDDS_DDR MaximumcurrentratingforDDRI/Odomain 250 mA VDDS Maximumcurrentratingforalldual-voltageI/Odomains 50 mA VDDS_SRAM_CORE_BG MaximumcurrentratingforcoreSRAMLDOs 10 mA VDDS_SRAM_MPU_BB MaximumcurrentratingforMPUSRAMLDOs 10 mA VDDS_PLL_DDR MaximumcurrentratingfortheDPLLDDR 10 mA VDDS_PLL_CORE_LCD MaximumcurrentratingfortheDPLLCoreandLCD 20 mA VDDS_PLL_MPU MaximumcurrentratingfortheDPLLMPU 10 mA VDDS_OSC MaximumcurrentratingforthesystemoscillatorI/Os 5 mA VDDA1P8V_USB0 MaximumcurrentratingforUSBPHY1.8V 25 mA VDDA1P8V_USB1(4) MaximumcurrentratingforUSBPHY1.8V 25 mA VDDA3P3V_USB0 MaximumcurrentratingforUSBPHY3.3V 40 mA VDDA3P3V_USB1(4) MaximumcurrentratingforUSBPHY3.3V 40 mA VDDA_ADC MaximumcurrentratingforADC 10 mA VDDSHV1(5) Maximumcurrentratingfordual-voltageI/Odomain 50 mA VDDSHV2(4) Maximumcurrentratingfordual-voltageI/Odomain 50 mA VDDSHV3(4) Maximumcurrentratingfordual-voltageI/Odomain 50 mA VDDSHV4 Maximumcurrentratingfordual-voltageI/Odomain 50 mA VDDSHV5 Maximumcurrentratingfordual-voltageI/Odomain 50 mA VDDSHV6 Maximumcurrentratingfordual-voltageI/Odomain 100 mA (1) Currentratingsspecifiedinthistableareworst-caseestimates.Actualapplicationpowersupplyestimatescouldbelower.Formore information,seeAM335xPowerConsumptionSummary. (2) VDD_MPUismergedwithVDD_COREandisnotavailableseparatelyontheZCEpackage.Themaximumcurrentratingfor VDD_COREontheZCEpackageisthesumofVDD_COREandVDD_MPUshowninthistable. (3) ThissupplyissourcedfromaninternalLDOwhenRTC_KALDO_ENnislow.IfRTC_KALDO_ENnishigh,thissupplymustbesourced fromanexternalpowersupply. (4) NotavailableontheZCEpackage. (5) VDDSHV1andVDDSHV2aremergedintheZCEpackage.ThemaximumcurrentratingforVDDSHV1ontheZCEpackageisthesum ofVDDSHV1andVDDSHV2showninthistable. 86 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table5-11summarizesthepowerconsumptionoftheAM335xlow-powermodes. Table5-11. AM335xLow-PowerModesPowerConsumptionSummary POWER POWERDOMAINS,CLOCKS,AND APPLICATIONSTATE NOM MAX UNIT MODES VOLTAGESUPPLYSTATES Powersupplies: • AllpowersuppliesareON. • VDD_MPU=0.95V(nom) DDRmemoryisinself-refreshand • VDD_CORE=0.95V(nom) contentsarepreserved.Wakeup Clocks: fromanyGPIO.Cortex-A8 context/registercontentsarelost • MainOscillator(OSC0)=ON Standby andmustbesavedbeforeentering • AllDPLLsareinbypass. 16.5 22.0 mW standby.Onexit,contextmustbe Powerdomains: restoredfromDDR.Forwakeup, • PD_PER=ON bootROMexecutesandbranches tosystemresume. • PD_MPU=OFF • PD_GFX=OFF • PD_WKUP=ON DDRisinself-refresh. Powersupplies: • AllpowersuppliesareON. • VDD_MPU=0.95V(nom) On-chipperipheralregistersare • VDD_CORE=0.95V(nom) preserved.Cortex-A8 Clocks: context/registersarelost,sothe applicationmustsavethemtothe • MainOscillator(OSC0)=OFF Deepsleep1 L3OCMCRAMorDDRbefore • AllDPLLsareinbypass. 6.0 10.0 mW enteringDeepSleep.DDRisinself- Powerdomains: refresh.Forwakeup,bootROM • PD_PER=ON executesandbranchestosystem resume. • PD_MPU=OFF • PD_GFX=OFF • PD_WKUP=ON DDRisinself-refresh. Powersupplies: • AllpowersuppliesareON. PD_PERperipheralandCortex- • VDD_MPU=0.95V(nom) A8/MPUregisterinformationwillbe • VDD_CORE=0.95V(nom) lost.On-chipperipheralregister Clocks: (context)informationofPD-PER domainmustbesavedby • MainOscillator(OSC0)=OFF Deepsleep0 applicationtoSDRAMbefore • AllDPLLsareinbypass. 3.0 4.3 mW enteringthismode.DDRisinself- Powerdomains: refresh.Forwakeup,bootROM • PD_PER=OFF executesandbranchesto peripheralcontextrestorefollowed • PD_MPU=OFF bysystemresume. • PD_GFX=OFF • PD_WKUP=ON DDRisinself-refresh. Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 87 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 5.7 DC Electrical Characteristics overrecommendedrangesofsupplyvoltageandoperatingtemperature(unlessotherwisenoted)(1) PARAMETER MIN NOM MAX UNIT DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A 2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM 0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1Pins(mDDR-LVCMOSMode) 0.65× VIH High-levelinputvoltage VDDS_DDR V 0.35× VIL Low-levelinputvoltage VDDS_DDR V VHYS Hysteresisvoltageataninput 0.07 0.25 V Highleveloutputvoltage,driverenabled,pullupor VDDS_DDR– VOH pulldowndisabled IOH=8mA 0.4 V Lowleveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=8mA 0.4 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 10 II Inputleakagecurrent,Receiverdisabled,pullupenabled –240 –80 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 80 240 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis 10 µA disabledandthepulluporpulldownisinhibited. DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A 2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM 0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1Pins(DDR2-SSTLMode) DDR_VREF+ VIH High-levelinputvoltage 0.125 V VHYS Hysteresisvoltageataninput N/A V High-leveloutputvoltage,driverenabled,pullupor VDDS_DDR– VOH pulldowndisabled IOH=8mA 0.4 V Low-leveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=8mA 0.4 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 10 II Inputleakagecurrent,Receiverdisabled,pullupenabled –240 –80 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 80 240 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis 10 µA disabledandthepulluporpulldownisinhibited. DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A 2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM 0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1Pins(DDR3,DDR3L-HSTLMode) VDDS_DDR= DDR_VREF+ 1.5V 0.1 VIH High-levelinputvoltage V VDDS_DDR= DDR_VREF+ 1.35V 0.09 VDDS_DDR= DDR_VREF– 1.5V 0.1 VIL Low-levelinputvoltage V VDDS_DDR= DDR_VREF– 1.35V 0.09 VHYS Hysteresisvoltageataninput N/A V High-leveloutputvoltage,driverenabled,pullupor VDDS_DDR– VOH pulldowndisabled IOH=8mA 0.4 V Low-leveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=8mA 0.4 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 10 II Inputleakagecurrent,Receiverdisabled,pullupenabled –240 –80 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 80 240 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis 10 µA disabledandthepulluporpulldownisinhibited. 88 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 DC Electrical Characteristics (continued) overrecommendedrangesofsupplyvoltageandoperatingtemperature(unlessotherwisenoted)(1) PARAMETER MIN NOM MAX UNIT ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_TXD,I2C0_SDA,I2C0_ SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,EXTINTn,TMS,TDO,USB0_DRVVBUS,USB1_DRVVBUS(VDDSHV6=1.8V) VIH High-levelinputvoltage 0.65×VDDSHV6 V VIL Low-levelinputvoltage 0.35×VDDSHV6 V VHYS Hysteresisvoltageataninput 0.18 0.305 V High-leveloutputvoltage,driverenabled,pullupor VOH pulldowndisabled IOH=4mA VDDSHV6–0.45 V Low-leveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=4mA 0.45 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 8 II Inputleakagecurrent,Receiverdisabled,pullupenabled –161 –100 –52 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 52 100 170 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis 8 µA disabledandthepulluporpulldownisinhibited. ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_TXD,I2C0_SDA,I2C0_ SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,EXTINTn,TMS,TDO,USB0_DRVVBUS,USB1_DRVVBUS(VDDSHV6=3.3V) VIH High-levelinputvoltage 2 V VIL Low-levelinputvoltage 0.8 V VHYS Hysteresisvoltageataninput 0.265 0.44 V High-leveloutputvoltage,driverenabled,pullupor VOH pulldowndisabled IOH=4mA VDDSHV6–0.45 V Low-leveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=4mA 0.45 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 18 II Inputleakagecurrent,Receiverdisabled,pullupenabled –243 –100 –19 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 51 110 210 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis 18 µA disabledandthepulluporpulldownisinhibited. TCK(VDDSHV6=1.8V) VIH High-levelinputvoltage 1.45 V VIL Low-levelinputvoltage 0.46 V VHYS Hysteresisvoltageataninput 0.4 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 8 II Inputleakagecurrent,Receiverdisabled,pullupenabled –161 –100 –52 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 52 100 170 TCK(VDDSHV6=3.3V) VIH High-levelinputvoltage 2.15 V VIL Low-levelinputvoltage 0.46 V VHYS Hysteresisvoltageataninput 0.4 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 18 II Inputleakagecurrent,Receiverdisabled,pullupenabled –243 –100 –19 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 51 110 210 PWRONRSTn(VDDSHV6=1.8or3.3V)(2) VIH High-levelinputvoltage 1.35 V VIL Low-levelinputvoltage 0.5 V VHYS Hysteresisvoltageataninput 0.07 V VI=1.8V 0.1 II Inputleakagecurrent µA VI=3.3V 2 RTC_PWRONRSTn 0.65× VIH High-levelinputvoltage VDDS_RTC V Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 89 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com DC Electrical Characteristics (continued) overrecommendedrangesofsupplyvoltageandoperatingtemperature(unlessotherwisenoted)(1) PARAMETER MIN NOM MAX UNIT 0.35× VIL Low-levelinputvoltage VDDS_RTC V VHYS Hysteresisvoltageataninput 0.065 V II Inputleakagecurrent –1 1 µA PMIC_POWER_EN High-leveloutputvoltage,driverenabled,pullupor VDDS_RTC– VOH pulldowndisabled IOH=6mA 0.45 V Low-leveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=6mA 0.45 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited –1 1 II Inputleakagecurrent,Receiverdisabled,pullupenabled –200 –40 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 40 200 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis –1 1 µA disabledandthepulluporpulldownisinhibited. EXT_WAKEUP 0.65× VIH High-levelinputvoltage VDDS_RTC V 0.35× VIL Low-levelinputvoltage VDDS_RTC V VHYS Hysteresisvoltageataninput 0.15 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited –1 1 II Inputleakagecurrent,Receiverdisabled,pullupenabled –200 –40 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 40 200 XTALIN(OSC0) 0.65× VIH High-levelinputvoltage VDDS_OSC V 0.35× VIL Low-levelinputvoltage VDDS_OSC V RTC_XTALIN(OSC1) 0.65× VIH High-levelinputvoltage VDDS_RTC V 0.35× VIL Low-levelinputvoltage VDDS_RTC V AllotherLVCMOSpins(VDDSHVx=1.8V;x=1to6) VIH High-levelinputvoltage 0.65×VDDSHVx V VIL Low-levelinputvoltage 0.35×VDDSHVx V VHYS Hysteresisvoltageataninput 0.18 0.305 V High-leveloutputvoltage,driverenabled,pullupor VOH pulldowndisabled IOH=6mA VDDSHVx–0.45 V Low-leveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=6mA 0.45 V Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 8 II Inputleakagecurrent,Receiverdisabled,pullupenabled –161 –100 –52 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 52 100 170 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis 8 µA disabledandthepulluporpulldownisinhibited. AllotherLVCMOSpins(VDDSHVx=3.3V;x=1to6) VIH High-levelinputvoltage 2 V VIL Low-levelinputvoltage 0.8 V VHYS Hysteresisvoltageataninput 0.265 0.44 V High-leveloutputvoltage,driverenabled,pullupor VOH pulldowndisabled IOH=6mA VDDSHVx–0.45 V Low-leveloutputvoltage,driverenabled,pullupor VOL pulldowndisabled IOL=6mA 0.45 V 90 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 DC Electrical Characteristics (continued) overrecommendedrangesofsupplyvoltageandoperatingtemperature(unlessotherwisenoted)(1) PARAMETER MIN NOM MAX UNIT Inputleakagecurrent,Receiverdisabled,pulluporpulldowninhibited 18 II Inputleakagecurrent,Receiverdisabled,pullupenabled –243 –100 –19 µA Inputleakagecurrent,Receiverdisabled,pulldownenabled 51 110 210 Totalleakagecurrentthroughtheterminalconnectionofadriver-receiver IOZ combinationthatmayincludeapulluporpulldown. Thedriveroutputis 18 µA disabledandthepulluporpulldownisinhibited. (1) Theinterfacesorsignalsdescribedinthistablecorrespondtotheinterfacesorsignalsavailableinmultiplexingmode0.Allinterfacesor signalsmultiplexedontheterminalsdescribedinthistablehavethesameDCelectricalcharacteristics. (2) TheinputvoltagethresholdsforthisinputarenotafunctionofVDDSHV6. Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 91 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 5.8 Thermal Resistance Characteristics for ZCE and ZCZ Packages Failure to maintain a junction temperature within the range specified in Section 5.5 reduces operating lifetime, reliability, and performance—and may cause irreversible damage to the system. Therefore, the product design cycle should include thermal analysis to verify the maximum operating junction temperature of the device. It is important this thermal analysis is performed using specific system use cases and conditions. TI provides an application report to aid users in overcoming some of the existing challenges of producing a good thermal design. For more information, see AM335x Thermal Considerations. Table5-12providesthermalcharacteristicsforthe packagesusedonthisdevice. NOTE Table5-12providessimulationdataandmaynotrepresentactualuse-casevalues. Table5-12.ThermalResistanceCharacteristics(PBGAPackage)[ZCEandZCZ] ZCE(°C/W)(1) ZCZ(°C/W)(1) AIRFLOW (2) (2) (m/s)(3) R Junction-to-case 10.3 10.2 N/A ΘJC R Junction-to-board 11.6 12.1 N/A ΘJB 24.7 24.2 0 20.5 20.1 1.0 R Junction-to-freeair ΘJA 19.7 19.3 2.0 19.2 18.8 3.0 0.4 0.3 0.0 0.6 0.6 1.0 φ Junction-to-packagetop JT 0.7 0.7 2.0 0.9 0.8 3.0 11.9 12.7 0.0 11.7 12.3 1.0 φ Junction-to-board JB 11.7 12.3 2.0 11.6 12.2 3.0 (1) ThesevaluesarebasedonaJEDEC-defined2S2Psystem(withtheexceptionofthethetaJC[R ]value,whichisbasedona ΘJC JEDEC-defined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements Powerdissipationof2Wandanambienttemperatureof70ºCisassumed. (2) °C/W=degreesCelsiusperwatt. (3) m/s=meterspersecond. 92 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 5.9 External Capacitors To improve module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the device, because this minimizes the inductance of the circuit board wiring and interconnects. 5.9.1 Voltage Decoupling Capacitors Table5-13summarizestheCorevoltagedecouplingcharacteristics. 5.9.1.1 CoreVoltageDecouplingCapacitors Toimprovemoduleperformance, decoupling capacitors are required to suppress high-frequency switching noise and to stabilize the supply voltage. A decoupling capacitor is most effective when located close to the AM335xdevice,becausethisminimizestheinductanceofthecircuitboardwiringandinterconnects. Table5-13.CoreVoltageDecouplingCharacteristics PARAMETER TYP UNIT C (1) 10.08 μF VDD_CORE C (2)(3) 10.05 μF VDD_MPU (1) Thetypicalvaluecorrespondstoonecapacitorof10μFandeightcapacitorsof10nF. (2) NotavailableontheZCEpackage.VDD_MPUismergedwithVDD_COREontheZCEpackage. (3) Thetypicalvaluecorrespondstoonecapacitorof10μFandfivecapacitorsof10nF. 5.9.1.2 I/OandAnalogVoltageDecouplingCapacitors Table5-14summarizesthepower-supplydecouplingcapacitorrecommendations. Table5-14.Power-SupplyDecouplingCapacitorCharacteristics PARAMETER TYP UNIT C 10 nF VDDA_ADC C 10 nF VDDA1P8V_USB0 C 10 nF CVDDA3P3V_USB0 C (1) 10 nF VDDA1P8V_USB1 C (1) 10 nF VDDA3P3V_USB1 C (2) 10.04 μF VDDS C (3) VDDS_DDR C 10 nF VDDS_OSC C 10 nF VDDS_PLL_DDR C 10 nF VDDS_PLL_CORE_LCD C (4) 10.01 μF VDDS_SRAM_CORE_BG C (5) 10.01 μF VDDS_SRAM_MPU_BB C 10 nF VDDS_PLL_MPU C 10 nF VDDS_RTC C (6) 10.02 μF VDDSHV1 C (1)(6) 10.02 μF VDDSHV2 C (1)(6) 10.02 μF VDDSHV3 C (6) 10.02 μF VDDSHV4 C (6) 10.02 μF VDDSHV5 C (7) 10.06 μF VDDSHV6 Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 93 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com (1) NotavailableontheZCEpackage. (2) Typicalvaluesconsistofonecapacitorof10μFandfourcapacitorsof10nF. (3) FormoredetailsondecouplingcapacitorrequirementsforthemDDR(LPDDR),DDR2,DDR3,DDR3Lmemoryinterface,see Section7.7.2.1.2.6andSection7.7.2.1.2.7whenusingmDDR(LPDDR)memorydevices,Section7.7.2.2.2.6andSection7.7.2.2.2.7 whenusingDDR2memorydevices,orSection7.7.2.3.3.6andSection7.7.2.3.3.7whenusingDDR3orDDR3Lmemorydevices. (4) VDDS_SRAM_CORE_BGsupplypowersaninternalLDOforSRAMsupplies.Inrushcurrentscouldcausevoltagedroponthe VDDS_SRAM_CORE_BGsupplieswhentheSRAMLDOisenabledafterpoweringupVDDS_SRAM_CORE_BGterminals.A10µFis recommendedtobeplacedclosetotheterminalandroutedwithwidesttracespossibletominimizethevoltagedropon VDDS_SRAM_CORE_BGterminals. (5) VDDS_SRAM_MPU_BBsupplypowersaninternalLDOforSRAMsupplies.Inrushcurrentscouldcausevoltagedroponthe VDDS_SRAM_MPU_BBsupplieswhentheSRAMLDOisenabledafterpoweringupVDDS_SRAM_MPU_BBterminals.A10µFis recommendedtobeplacedclosetotheterminalandroutedwithwidesttracespossibletominimizethevoltagedropon VDDS_SRAM_MPU_BBterminals. (6) Typicalvaluesconsistofonecapacitorof10μFandtwocapacitorsof10nF. (7) Typicalvaluesconsistofonecapacitorof10μFandsixcapacitorsof10nF. 5.9.2 Output Capacitors Internal low dropout output (LDO) regulators require external capacitors to stabilize their outputs. These capacitorsshouldbeplacedascloseaspossibletotherespectiveterminalsofthe AM335xdevice .Table5-15summarizestheLDOoutputcapacitorrecommendations. Table5-15.OutputCapacitorCharacteristics PARAMETER TYP UNIT C (1) 1 μF CAP_VDD_SRAM_CORE C (1)(2) 1 μF CAP_VDD_RTC C (1) 1 μF CAP_VDD_SRAM_MPU C (1) 1 μF CAP_VBB_MPU (1) LDOregulatoroutputsshouldnotbeusedasapowersourceforanyexternalcomponents. (2) TheCAP_VDD_RTCterminaloperatesasaninputtotheRTCcorevoltagedomainwhentheRTC_KALDO_ENnterminalishigh. 94 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Figure5-1showsanexampleoftheexternalcapacitors. AM335x Device VDDS_PLL_MPU MPU PLL CVDDS_PLL_MPU VDD_MPU MPU CVDD_MPU VDDS_PLL_CORE_LCD CORE PLL CVDDS_PLL_CORE_LCD VDD_CORE LCD PLL CORE CVDD_CORE CAP_VBB_MPU CCAP_VBB_MPU VDDS CVDDS I/O VDDS_SRAM_MPU_BB CVDDS_SRAM_MPU_BB VDDSHV1 MPU SRAM CVDDSHV1 I/Os LDO Back Bias CAP_VDD_SRAM_MPU LDO VDDSHV2 CCAP_VDD_SRAM_MPU CVDDSHV2 I/Os VDDS_SRAM_CORE_BG VDDSHV3 CVDDS_SRAM_CORE_BG CVDDSHV3 I/Os CORE SRAM LDO Band Gap CAP_VDD_SRAM_CORE Reference VDDSHV4 CVDDSHV4 I/Os CCAP_VDD_SRAM_CORE VDDA_3P3V_USBx VDDSHV5 CVDDSHV5 I/Os CVDDA_3P3V_USBx VSSA_USB USB PHYx VDDSHV6 VDDA_1P8V_USBx CVDDSHV6 I/Os CVDDA_1P8V_USBx VSSA_USB VDDS_DDR CVDDS_DDR I/Os VDDA_ADC ADC CVDDA_ADC VDDS_RTC I/Os VSSA_ADC CVDDS_RTC VDDS_OSC CVDDS_OSC VDDS_PLL_DDR DDR CVDDS_PLL_DDR PLL CAP_VDD_RTC RTC CCAP_VDD_RTC A. Decouplingcapacitorsmustbeplacedasclosedaspossibletothepowerterminal.Choosethegroundclosesttothe powerpinforeachdecouplingcapacitor.Incaseofinterconnectingpowers,firstinsertthedecoupling capacitor and theninterconnectthepowers. B. Thedecouplingcapacitorvaluedependsonthecharacteristicsoftheboard. Figure5-1.ExternalCapacitors Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 95 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters The touch screen controller (TSC) and analog-to-digital converter (ADC) subsystem (TSC_ADC) is an 8- channel general-purpose ADC with optional support for interleaving TSC conversions for 4-wire, 5-wire, or 8-wire resistive panels. The TSC_ADC subsystem can be configured for use in one of the following applications: • 8general-purposeADCchannels • 4-wireTSCwith4general-purposeADCchannels • 5-wireTSCwith3general-purposeADCchannels • 8-wireTSC. Table5-16summarizestheTSC_ADCsubsystemelectricalparameters. Table5-16.TSC_ADCElectricalParameters PARAMETER TESTCONDITIONS MIN NOM MAX UNIT AnalogInput VREFP(1) (0.5×VDDA_ADC)+ VDDA_ADC V 0.25 VREFN(1) 0 (0.5×VDDA_ADC)– V 0.25 VREFP +VREFN(1) VDDA_ADC V Internalvoltagereference 0 VDDA_ADC Full-scaleinputrange V Externalvoltagereference VREFN VREFP Internalvoltagereference: Differentialnonlinearity VDDA_ADC=1.8V –1 0.5 1 LSB (DNL) Externalvoltagereference: VREFP–VREFN=1.8V Sourceimpedance=50Ω Internalvoltagereference: VDDA_ADC=1.8V –2 ±1 2 Externalvoltagereference: VREFP–VREFN=1.8V Integralnonlinearity(INL) LSB Sourceimpedance=1kΩ Internalvoltagereference: VDDA_ADC=1.8V ±1 Externalvoltagereference: VREFP–VREFN=1.8V Internalvoltagereference: VDDA_ADC=1.8V Gainerror ±2 LSB Externalvoltagereference: VREFP–VREFN=1.8V Internalvoltagereference: VDDA_ADC=1.8V Offseterror ±2 LSB Externalvoltagereference: VREFP–VREFN=1.8V Inputsamplingcapacitance 5.5 pF Internalvoltagereference: VDDA_ADC=1.8V Externalvoltagereference: Signal-to-noiseratio(SNR) 70 dB VREFP–VREFN=1.8V Inputsignal:30-kHzsinewaveat –0.5-dBfullscale Internalvoltagereference: VDDA_ADC=1.8V Totalharmonicdistortion Externalvoltagereference: 75 dB (THD) VREFP–VREFN=1.8V Inputsignal:30-kHzsinewaveat –0.5-dBfullscale 96 Specifications Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table5-16.TSC_ADCElectricalParameters(continued) PARAMETER TESTCONDITIONS MIN NOM MAX UNIT Internalvoltagereference: VDDA_ADC=1.8V Spuriousfreedynamic Externalvoltagereference: 80 dB range VREFP–VREFN=1.8V Inputsignal:30-kHzsinewaveat –0.5-dBfullscale Internalvoltagereference: VDDA_ADC=1.8V Signal-to-noiseplus Externalvoltagereference: 69 dB distortion VREFP–VREFN=1.8V Inputsignal:30-kHzsinewaveat –0.5-dBfullscale VREFPandVREFNinputimpedance 20 kΩ IAnIpNu[7t:im0]p(2e)danceof ƒ=Inputfrequency [1/((65.97×10–12)׃)] Ω SamplingDynamics ADCclockfrequency 1 3 MHz ADC Conversiontime 13 clock cycles ADC Acquisitiontime 2 257 clock cycles Samplingrate 200 kSPS Channel-to-channelisolation 100 dB TouchScreenSwitchDrivers PullupandpulldownswitchONresistance(Ron) 2 Ω Pullupandpulldownswitch Sourceimpedance=500Ω 0.5 uA currentleakageIleak Drivecurrent 25 mA Touchscreenresistance 6 kΩ Pentouchdetect 2 kΩ (1) VREFP andVREFNmustbetiedtogroundiftheinternalvoltagereferenceisused. (2) ThisparameterisvalidwhentherespectiveAINterminalisconfiguredtooperateasageneral-purposeADCinput. Copyright©2011–2020,TexasInstrumentsIncorporated Specifications 97 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 6 Power and Clocking 6.1 Power Supplies 6.1.1 Power Supply Slew Rate Requirement To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the maximum slew rate for powering on the supplies to be less than 1.0E +5 V/s. For instance, as shown in Figure6-1,TIrecommendsavaluegreaterthan18 µsforthesupplyrampslewfora1.8-Vsupply. Supply value t slew rate < 1E + 5 V/s slew > (supply value) / (1E + 5V/s) supply value´10 µs 0 Figure6-1.PowerSupplySlewandSlewRate 98 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 1.8 V VDDS_RTC 1.8 V RTC_PWRONRSTn 1.8 V PMIC_POWER_EN 1.8 V All 1.8-V Supplies 1.8 V/1.5 V/1.35 V VDDS_DDR 3.3 V I/O 3.3-V Supplies 1.1 V VDD_CORE, VDD_MPU PWRONRSTn CLK_M_OSC A. RTC_PWRONRSTnshouldbeassertedforatleast1mstoprovideenoughtimefortheinternalRTCLDOoutputto reachavalidlevelbeforeRTCresetisreleased. B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same sourceiftheapplicationonlyusesoperatingperformancepoints(OPPs)thatdefineacommonpowersupplyvoltage forVDD_MPUandVDD_CORE.TheZCEpackageoptionhastheVDD_MPUdomainmergedwiththeVDD_CORE domain. C. IfaUSBportisnotused,therespectiveVDDA1P8V_USBterminalmaybeconnectedtoany1.8-Vpowersupplyand therespectiveVDDA3P3V_USBterminalmaybeconnectedtoany3.3-Vpowersupply.Ifthesystemdoesnothavea 3.3-Vpowersupply,theVDDA3P3V_USBterminalmaybeconnectedtoground. D. IfthesystemusesmDDRorDDR2memorydevices,VDDS_DDRcanberampedsimultaneouslywiththeother1.8-V I/Opowersupplies. E. VDDS_RTCcanberampedindependentofotherpowersuppliesifPMIC_POWER_ENfunctionalityisnotrequired.If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE.Thepowersequenceshownprovidesthelowestleakageoption. F. ToconfigureVDDSHVx[1-6]as1.8V,poweruptherespectiveVDDSHVx[1-6]to1.8Vfollowingtherecommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommendedsequence. G. Ifallthe1.8-Vsuppliesarenotsourced fromthesamepowersupply, itis requiredtopower up VDDS before other 1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V fromthesamepowersupply. Figure6-2.PreferredPower-SupplySequencingWithDual-VoltageI/OsConfiguredas3.3V Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 99 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 1.8 V VDDS_RTC 1.8 V RTC_PWRONRSTn 1.8 V PMIC_POWER_EN 3.3 V See Notes Below 1.8 V All 1.8-V Supplies All 3.3-V Supplies 1.8 V/1.5 V/1.35 V VDDS_DDR 1.1 V VDD_CORE, VDD_MPU PWRONRSTn CLK_M_OSC A. RTC_PWRONRSTnshouldbeassertedforatleast1mstoprovideenoughtimefortheinternalRTCLDOoutputto reachavalidlevelbeforeRTCresetisreleased. B. The3.3-VI/Opowersuppliesmayberampedsimultaneouslywiththe1.8-VI/Opowersuppliesifthevoltagesourced by any 3.3-V power supplies does not exceed the voltage sourced by any 1.8-V power supply by more than 2 V. Seriousreliabilityissuesmayoccurifthesystempowersupplydesignallowsany3.3-VI/Opowersuppliestoexceed any1.8-VI/Opowersuppliesbymorethan2V. C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same sourceiftheapplicationonlyusesoperatingperformancepoints(OPPs)thatdefineacommonpowersupplyvoltage forVDD_MPUandVDD_CORE.TheZCEpackageoptionhastheVDD_MPUdomainmergedwiththeVDD_CORE domain. D. IfaUSBportisnotused,therespectiveVDDA1P8V_USBterminalmaybeconnectedtoany1.8-Vpowersupplyand therespectiveVDDA3P3V_USBterminalmaybeconnectedtoany3.3-Vpowersupply.Ifthesystemdoesnothavea 3.3-Vpowersupply,theVDDA3P3V_USBterminalmaybeconnectedtoground. E. IfthesystemusesmDDRorDDR2memorydevices,VDDS_DDRcanberampedsimultaneouslywiththeother1.8-V I/Opowersupplies. F. VDDS_RTCcanberampedindependentofotherpowersuppliesifPMIC_POWER_ENfunctionalityisnotrequired.If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE.Thepowersequenceshownprovidesthelowestleakageoption. G. ToconfigureVDDSHVx[1-6]as1.8V,poweruptherespectiveVDDSHVx[1-6]to1.8Vfollowingtherecommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommendedsequence. H. Ifallthe1.8-Vsuppliesarenotsourced fromthesamepowersupply, itis requiredtopower up VDDS before other 1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V fromthesamepowersupply. Figure6-3.AlternatePower-SupplySequencingWithDual-VoltageI/OsConfiguredas3.3V 100 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 1.8 V VDDS_RTC 1.8V RTC_PWRONRSTn 1.8 V PMIC_POWER_EN 1.8 V All 1.8-V Supplies 1.8 V/1.5 V/1.35 V VDDS_DDR 3.3 V All 3.3-V Supplies 1.1 V VDD_CORE, VDD_MPU PWRONRSTn CLK_M_OSC A. RTC_PWRONRSTnshouldbeassertedforatleast1mstoprovideenoughtimefortheinternalRTCLDOoutputto reachavalidlevelbeforeRTCresetisreleased. B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same sourceiftheapplicationonlyusesoperatingperformancepoints(OPPs)thatdefineacommonpowersupplyvoltage forVDD_MPUandVDD_CORE.TheZCEpackageoptionhastheVDD_MPUdomainmergedwiththeVDD_CORE domain. C. IfaUSBportisnotused,therespectiveVDDA1P8V_USBterminalmaybeconnectedtoany1.8-Vpowersupplyand therespectiveVDDA3P3V_USBterminalmaybeconnectedtoany3.3-Vpowersupply.Ifthesystemdoesnothavea 3.3-Vpowersupply,theVDDA3P3V_USBterminalmaybeconnectedtoground. D. IfthesystemusesmDDRorDDR2memorydevices,VDDS_DDRcanberampedsimultaneouslywiththeother1.8-V I/Opowersupplies. E. VDDS_RTCcanberampedindependentofotherpowersuppliesifPMIC_POWER_ENfunctionalityisnotrequired.If VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE.Thepowersequenceshownprovidesthelowestleakageoption. F. ToconfigureVDDSHVx[1-6]as1.8V,poweruptherespectiveVDDSHVx[1-6]to1.8Vfollowingtherecommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommendedsequence. G. Ifallthe1.8-Vsuppliesarenotsourced fromthesamepowersupply, itis requiredtopower up VDDS before other 1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V fromthesamepowersupply. Figure6-4.Power-SupplySequencingWithDual-VoltageI/OsConfiguredas1.8V Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 101 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 1.8 V VDDS_RTC, 1.1 V CAP_VDD_RTC 1.8 V RTC_PWRONRSTn 1.8 V PMIC_POWER_EN 1.8 V VDDSHV 1-6 All other 1.8-V Supplies 1.8 V/1.5 V/1.35 V VDDS_DDR 3.3 V All 3.3-V Supplies 1.1 V VDD_CORE, VDD_MPU PWRONRSTn CLK_M_OSC A. RTC_PWRONRSTnshouldbeassertedforatleast1mstoprovideenoughtimefortheinternalRTCLDOoutputto reachavalidlevelbeforeRTCresetisreleased. B. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTCshouldbesourcedfromanexternal1.1-Vpowersupply. C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same sourceiftheapplicationonlyusesoperatingperformancepoints(OPPs)thatdefineacommonpowersupplyvoltage forVDD_MPUandVDD_CORE.TheZCEpackageoptionhastheVDD_MPUdomainmergedwiththeVDD_CORE domain. D. IfaUSBportisnotused,therespectiveVDDA1P8V_USBterminalmaybeconnectedtoany1.8-Vpowersupplyand therespectiveVDDA3P3V_USBterminalmaybeconnectedtoany3.3-Vpowersupply.Ifthesystemdoesnothavea 3.3-Vpowersupply,theVDDA3P3V_USBterminalmaybeconnectedtoground. E. IfthesystemusesmDDRorDDR2memorydevices,VDDS_DDRcanberampedsimultaneouslywiththeother1.8-V I/Opowersupplies. F. VDDS_RTC should be rampedatthesametimeorbeforeCAP_VDD_RTC, butthesepower inputs can be ramped independentofotherpowersuppliesifPMIC_POWER_ENfunctionalityisnotrequired.IfCAP_VDD_RTCisramped afterVDD_CORE,theremightbeasmallamountofadditionalleakagecurrentonVDD_CORE.Thepowersequence shownprovidesthelowestleakageoption. G. ToconfigureVDDSHVx[1-6]as1.8V,poweruptherespectiveVDDSHVx[1-6]to1.8Vfollowingtherecommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommendedsequence. H. Ifallthe1.8-Vsuppliesarenotsourced fromthesamepowersupply, itis requiredtopower up VDDS before other 1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V fromthesamepowersupply. Figure6-5.Power-SupplySequencingWithInternalRTCLDODisabled 102 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 1.8 V VDDS_RTC, All other 1.8-V Supplies 1.8 V/1.5 V/1.35 V VDDS_DDR 3.3 V All 3.3-V Supplies 1.1 V VDD_CORE, VDD_MPU CAP_VDD_RTC PWRONRSTn CLK_M_OSC A. CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTCshouldbesourcedfroman external 1.1-Vpowersupply. The PMIC_POWER_EN outputcannot be usedwhentheRTCisdisabled. B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same sourceiftheapplicationonlyusesoperatingperformancepoints(OPPs)thatdefineacommonpowersupplyvoltage forVDD_MPUandVDD_CORE.TheZCEpackageoptionhastheVDD_MPUdomainmergedwiththeVDD_CORE domain. C. IfaUSBportisnotused,therespectiveVDDA1P8V_USBterminalmaybeconnectedtoany1.8-Vpowersupplyand therespectiveVDDA3P3V_USBterminalmaybeconnectedtoany3.3-Vpowersupply.Ifthesystemdoesnothavea 3.3-Vpowersupply,theVDDA3P3V_USBterminalmaybeconnectedtoground. D. IfthesystemusesmDDRorDDR2memorydevices,VDDS_DDRcanberampedsimultaneouslywiththeother1.8-V I/Opowersupplies. E. VDDS_RTC should be rampedatthesametimeorbeforeCAP_VDD_RTC, butthesepower inputs can be ramped independentofotherpowersuppliesifPMIC_POWER_ENfunctionalityisnotrequired.IfCAP_VDD_RTCisramped afterVDD_CORE,theremightbeasmallamountofadditionalleakagecurrentonVDD_CORE.Thepowersequence shownprovidesthelowestleakageoption. F. ToconfigureVDDSHVx[1-6]as1.8V,poweruptherespectiveVDDSHVx[1-6]to1.8Vfollowingtherecommended sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommendedsequence. G. Ifallthe1.8-Vsuppliesarenotsourced fromthesamepowersupply, itis requiredtopower up VDDS before other 1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V fromthesamepowersupply. Figure6-6.Power-SupplySequencingWithRTCFeatureDisabled 6.1.2 Power-Down Sequencing PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies areturnedoff.Allotherexternalclockstothedeviceshouldbeshutoff. Thepreferredwaytosequencepowerdown is to have all the power supplies ramped down sequentially in the exact reverse order of the power-up sequencing. In other words, the power supply that has been ramped up first should be the last one that should be ramped down. This ensures there would be no spurious current paths during the power-down sequence. The VDDS power supply must ramp down after all3.3-VVDDSHVx[1-6]powersupplies. If it is desired to ramp down VDDS and VDDSHVx [1-6] simultaneously, it should always be ensured that the difference between VDDS and VDDSHVx [1-6] during the entire power-down sequence is <2 V. Any violation of this could cause reliability risks for the device. TI recommends maintaining VDDS ≥1.5V as all theothersuppliesfullyrampdowntominimizein-rushcurrents. Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 103 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com If none of the VDDSHVx [1-6] power supplies are configured as 3.3 V, the VDDS power supply may ramp down along with the VDDSHVx [1-6] supplies or after all the VDDSHVx [1-6] supplies have ramped down. TI recommends maintaining VDDS ≥1.5V as all the other supplies fully ramp down to minimize in-rush currents. 6.1.3 VDD_MPU_MON Connections Figure6-7showstheVDD_MPU_MONconnectivity.VDD_MPU_MONconnectivityisavailableonlyon the ZCZpackage. VDD_MPU Power AM335x Device VDD_MPU_MON Management IC Vfeedback Connection for VDD_MPU_MON if voltage monitoring is used VDD_MPU Power AM335x Device VDD_MPU_MON Source Preferred connection for VDD_MPU_MON if voltage monitoring is NOTused VDD_MPU Power AM335x Device VDD_MPU_MON Source N/C Optional connection for VDD_MPU_MON if voltage monitoring is NOTused Figure6-7.VDD_MPU_MONConnectivity 104 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 6.1.4 Digital Phase-Locked Loop Power Supply Requirements The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM335x device. The AM335x device integrates five different DPLLs—Core DPLL, Per DPLL, LCD DPLL,DDRDPLL,MPUDPLL. Figure 6-8 shows the power supply connectivity implemented in the AM335x device. Table 6-1 provides thepowersupplyrequirementsfortheDPLL. MPU PER PLL PLL VDDS_PLL_MPU VDDA1P8V_USB0 CORE PLL DDR PLL VDDS_PLL_CORE_LCD LCD VDDS_PLL_DDR PLL Figure6-8.DPLLPowerSupplyConnectivity Table6-1.DPLLPowerSupplyRequirements SUPPLYNAME DESCRIPTION MIN NOM MAX UNIT SupplyvoltagerangeforUSBPHYandPERDPLL,Analog,1.8V 1.71 1.8 1.89 V VDDA1P8V_USB0 Maxpeak-to-peaksupplynoise 50 mV(p-p) SupplyvoltagerangeforDPLLMPU,analog 1.71 1.8 1.89 V VDDS_PLL_MPU Maxpeak-to-peaksupplynoise 50 mV(p-p) SupplyvoltagerangeforDPLLCOREandLCD,analog 1.71 1.8 1.89 V VDDS_PLL_CORE_LCD Maxpeak-to-peaksupplynoise 50 mV(p-p) SupplyvoltagerangeforDPLLDDR,analog 1.71 1.8 1.89 V VDDS_PLL_DDR Maxpeak-to-peaksupplynoise 50 mV(p-p) Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 105 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 6.2 Clock Specifications 6.2.1 Input Clock Specifications TheAM335xdevicehas two clock inputs. Each clock input passes through an internal oscillator which can beconnectedtoanexternalcrystalcircuit(oscillator mode) or external LVCMOS square-wave digital clock source (bypass mode). The oscillators automatically operate in bypass mode when their input is connected to an external LVCMOS square-wave digital clock source. The oscillator associated with a specificclockinputmustbeenabledwhentheclockinputisbeingusedineitheroscillator mode or bypass mode. The OSC1 oscillator provides a 32.768-kHz reference clock to the real-time clock (RTC) and is connected to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator (CLK_32K_RTC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual. OSC1 is disabled by default after power is applied. This clock input is optional and may not be required if the RTC is configured to receive a clock from the internal 32k RC oscillator (CLK_RC32K) or peripheral PLL (CLK_32KHZ)whichreceivesareferenceclockfromtheOSC0input. The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to clockallnon-RTCfunctionsandisconnectedtotheXTALINandXTALOUTterminals.This clock source is referred to as the master oscillator (CLK_M_OSC) in the AM335x and AMIC110 Sitara Processors TechnicalReferenceManual.OSC0isenabledbydefaultafterpowerisapplied. For more information related to recommended circuit topologies and crystal oscillator circuit requirements fortheseclockinputs,seeSection6.2.2. 6.2.2 Input Clock Requirements 6.2.2.1 OSC0InternalOscillatorClockSource Figure 6-9 shows the recommended crystal circuit. TI recommends that preproduction printed-circuit board (PCB)designsincludethetwooptionalresistorsR andR incasethey are required for proper oscillator bias d operation when combined with production crystal circuit components. In most cases, R is not required bias and R is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating d oscillatorperformancewithproductioncrystalcircuitcomponentsinstalledonpreproductionPCBs. The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which mayincreaseleakagecurrentthroughtheoscillatorinputbuffer. 106 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 AM335x XTALIN VSS_OSC XTALOUT C 1 C 2 Crystal Optional R d Optional R bias Copyright © 2016,Texas Instruments Incorporated A. Oscillator components (Crystal, C , C , optional R and R ) must be located close to the AM335x package. 1 2 bias d ParasiticcapacitancetotheVSS_OSCandrespectivecrystalcircuitcomponentgroundsshouldbeconnecteddirectly tothenearestPCBdigitalground(VSS). B. C and C represent the total capacitance of the respective PCB trace, load capacitor, and other components 1 2 (excluding thecrystal) connectedto each crystal terminal. The value of capacitors C and C should be selected to 1 2 providethetotalloadcapacitance,C ,specifiedbythecrystalmanufacturer.ThetotalloadcapacitanceisC =[(C × L L 1 C )/(C +C )]+C ,whereC isthecrystalshuntcapacitance(C )specifiedbythecrystalmanufacturerplus 2 1 2 shunt shunt 0 any mutual capacitance (C + C ) seen across theAM335x XTALIN and XTALOUT signals. For recommended pkg PCB valuesofcrystalcircuitcomponents,seeTable6-2. Figure6-9.OSC0CrystalCircuitSchematic Table6-2.OSC0CrystalCircuitRequirements PARAMETER MIN TYP MAX UNIT Crystalparallelresonance Fundamentalmodeoscillationonly 19.2,24, MHz frequency 25,or26 ƒ xtal Crystalfrequencystability andtolerance(1) –50 50 ppm C ≤5pF 12 24 shunt C C capacitance pF C1 1 C >5pF 18 24 shunt C ≤5pF 12 24 shunt C C capacitance pF C2 2 C >5pF 18 24 shunt C Shuntcapacitance 7 pF shunt ƒ =19.2MHz,oscillatorhasnominal xtal negativeresistanceof272Ωandworst- 54.4 casenegativeresistanceof163Ω ƒ =24MHz,oscillatorhasnominal xtal negativeresistanceof240Ωandworst- 48.0 Crystaleffectiveseries casenegativeresistanceof144Ω ESR Ω resistance ƒ =25MHz,oscillatorhasnominal xtal negativeresistanceof233Ωandworst- 46.6 casenegativeresistanceof140Ω ƒ =26MHz,oscillatorhasnominal xtal negativeresistanceof227Ωandworst- 45.3 casenegativeresistanceof137Ω (1) Initialaccuracy,temperaturedrift,andagingeffectsshouldbecombinedwhenevaluatingareferenceclockforthisrequirement. Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 107 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table6-3.OSC0CrystalCircuitCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT Shuntcapacitanceof ZCEpackage 0.01 C pF pkg package ZCZpackage 0.01 TheactualvaluesoftheESR,ƒ ,andC shouldbeusedtoyielda xtal L typicalcrystalpowerdissipationvalue.Usingthemaximumvalues P =0.5ESR(2πƒ Pxtal specifiedforESR,ƒ ,andC parametersyieldsamaximumpower xtaCl VDDS_OSC)2 xtal xtal L L dissipationvalue. t Start-uptime 1.5 ms sX VDD_CORE (min.) VDD_CORE VSS e ag VDDS_OSC (min.) VDDS_OSC olt V VSS XTALOUT t sX Time Figure6-10.OSC0Start-UpTime 108 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 6.2.2.2 OSC0LVCMOSDigitalClockSource Figure 6-11 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. The ground for the LVCMOS clock source and VSS_OSC should be connected directly to the nearest PCB digital ground (VSS). In this mode of operation, the XTALOUT terminal should not be used to source any external components. The PCB design should provide a mechanism to disconnect the XTALOUT terminal from any external components or signal traces that may couple noise into OSC0 via the XTALOUT terminal. The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which mayincreaseleakagecurrentthroughtheoscillatorinputbuffer. AM335x XTALIN VSS_OSC XTALOUT VDDS_OSC LVCMOS Digital Clock Source Copyright © 2016,Texas Instruments Incorporated Figure6-11.OSC0LVCMOSCircuitSchematic Table6-4.OSC0LVCMOSReferenceClockRequirements NAME DESCRIPTION MIN TYP MAX UNIT 19.2,24,25, Frequency,LVCMOSreferenceclock MHz ƒ or26 (XTALIN) Frequency,LVCMOSreferenceclockstabilityandtolerance(1) –50 50 ppm t Dutycycle,LVCMOSreferenceclockperiod 45% 55% dc(XTALIN) t Jitterpeak-to-peak,LVCMOSreferenceclockperiod –1% 1% jpp(XTALIN) t Time,LVCMOSreferenceclockrise 5 ns R(XTALIN) t Time,LVCMOSreferenceclockfall 5 ns F(XTALIN) (1) Initialaccuracy,temperaturedrift,andagingeffectsshouldbecombinedwhenevaluatingareferenceclockforthisrequirement. 6.2.2.3 OSC1InternalOscillatorClockSource Figure 6-12 shows the recommended crystal circuit for OSC1 of the ZCE package and Figure 6-13 shows the recommended crystal circuit for OSC1 of the ZCZ package. TI recommends that preproduction PCB designs include the two optional resistors R and R in case they are required for proper oscillator bias d operation when combined with production crystal circuit components. In most cases, R is not required bias and R is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating d oscillatorperformancewithproductioncrystalcircuitcomponentsinstalledonpreproductionPCBs. The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level whichmayincreaseleakagecurrentthroughtheoscillatorinputbuffer. Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 109 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com AM335x (ZCE Package) RTC_XTALIN RTC_XTALOUT Optional R bias Crystal Optional R d C C 1 2 Copyright © 2016,Texas Instruments Incorporated A. Oscillator components (Crystal, C , C , optional R and R ) must be located close to the AM335x package. 1 2 bias d Parasitic capacitance to the PCB ground and other signals should be minimized to reduce noise coupled into the oscillator. VSS_RTC and respective crystal circuit component grounds should be connected directly to the nearest PCBdigitalground(VSS). B. C and C represent the total capacitance of the respective PCB trace, load capacitor, and other components 1 2 (excluding thecrystal) connectedto each crystal terminal. The value of capacitors C and C should be selected to 1 2 providethetotalloadcapacitance,C ,specifiedbythecrystalmanufacturer.ThetotalloadcapacitanceisC =[(C × L L 1 C )/(C +C )]+C ,whereC isthecrystalshuntcapacitance(C )specifiedbythecrystalmanufacturerplus 2 1 2 shunt shunt 0 any mutual capacitance (C + C ) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For pkg PCB recommendedvaluesofcrystalcircuitcomponents,seeTable6-5. Figure6-12.OSC1(ZCEPackage)CrystalCircuitSchematic AM335x (ZCZ Package) RTC_XTALIN VSS_RTC RTC_XTALOUT C 1 C 2 Crystal Optional R d Optional R bias Copyright © 2016,Texas Instruments Incorporated A. Oscillator components (Crystal, C , C , optional R and R ) must be located close to the AM335x package. 1 2 bias d Parasitic capacitance to the PCB ground and other signals should be minimized to reduce noise coupled into the oscillator. VSS_RTC and respective crystal circuit component grounds should be connected directly to the nearest PCBdigitalground(VSS). B. C and C represent the total capacitance of the respective PCB trace, load capacitor, and other components 1 2 (excluding thecrystal) connectedto each crystal terminal. The value of capacitors C and C should be selected to 1 2 providethetotalloadcapacitance,C ,specifiedbythecrystalmanufacturer.ThetotalloadcapacitanceisC =[(C × L L 1 C )/(C +C )]+C ,whereC isthecrystalshuntcapacitance(C )specifiedbythecrystalmanufacturerplus 2 1 2 shunt shunt 0 any mutual capacitance (C + C ) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For pkg PCB recommendedvaluesofcrystalcircuitcomponents,seeTable6-5. Figure6-13.OSC1(ZCZPackage)CrystalCircuitSchematic 110 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table6-5.OSC1CrystalCircuitRequirements NAME DESCRIPTION MIN TYP MAX UNIT Crystalparallelresonance Fundamentalmodeoscillationonly 32.768 kHz frequency MaximumRTCerror=10.512minutes ƒ –20.0 20.0 ppm xtal Crystalfrequencystability peryear andtolerance(1) MaximumRTCerror=26.28minutesper –50.0 50.0 ppm year C C capacitance 12.0 24.0 pF C1 1 C C capacitance 12.0 24.0 pF C2 2 C Shuntcapacitance 1.5 pF shunt ƒ =32.768kHz,oscillatorhasnominal Crystaleffectiveseries xtal ESR negativeresistanceof725kΩandworst- 80 kΩ resistance casenegativeresistanceof250kΩ (1) Initialaccuracy,temperaturedrift,andagingeffectsshouldbecombinedwhenevaluatingareferenceclockforthisrequirement. Table6-6.OSC1CrystalCircuitCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT Shuntcapacitanceof ZCEpackage 0.17 pF C pkg package ZCZpackage 0.01 pF TheactualvaluesoftheESR,ƒ ,andC shouldbeusedtoyielda xtal L typicalcrystalpowerdissipationvalue.Usingthemaximumvalues P =0.5ESR(2πƒ C Pxtal specifiedforESR,ƒ ,andC parametersyieldsamaximumpower xtal VDDS_RTC)2 xtal L xtal L dissipationvalue. t Start-uptime 2 s sX CAP_VDD_RTC (min.) CAP_VDD_RTC VSS_RTC e ag VDDS_RTC (min.) VDDS_RTC olt V RTC_XTALOUT VSS_RTC t sX Time Figure6-14.OSC1Start-upTime Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 111 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 6.2.2.4 OSC1LVCMOSDigitalClockSource Figure6-15showstherecommendedoscillatorconnectionswhenOSC1oftheZCEpackageis connected to an LVCMOS square-wave digital clock source and Figure 6-16 shows the recommended oscillator connections when OSC1 of the ZCZ package is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the RTC_XTALIN terminal. The ground for the LVCMOS clock source and VSS_RTC of the ZCZ package should be connected directly to the nearest PCB digital ground (VSS). In this mode of operation, the RTC_XTALOUT terminal should not be used to source any external components. The PCB design should provide a mechanism to disconnect the RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1 throughtheRTC_XTALOUTterminal. The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level whichmayincreaseleakagecurrentthroughtheoscillatorinputbuffer. AM335x (ZCE Package) RTC_XTALIN RTC_XTALOUT VDDS_RTC LVCMOS Digital N/C Clock Source Copyright © 2016,Texas Instruments Incorporated Figure6-15.OSC1(ZCEPackage)LVCMOSCircuitSchematic AM335x (ZCZ Package) RTC_XTALIN VSS_RTC RTC_XTALOUT VDDS_RTC LVCMOS Digital N/C Clock Source Copyright © 2016,Texas Instruments Incorporated Figure6-16.OSC1(ZCZPackage)LVCMOSCircuitSchematic Table6-7.OSC1LVCMOSReferenceClockRequirements NAME DESCRIPTION MIN TYP MAX UNIT Frequency,LVCMOSreferenceclock 32.768 kHz MaximumRTCerror= –20 20 ppm ƒ(RTC_XTALIN) Frequency,LVCMOSreferenceclock 10.512minutes/year stabilityandtolerance(1) MaximumRTCerror=26.28 –50 50 ppm minutes/year t Dutycycle,LVCMOSreferenceclockperiod 45% 55% dc(RTC_XTALIN) t Jitterpeak-to-peak,LVCMOSreferenceclockperiod –1% 1% jpp(RTC_XTALIN) t Time,LVCMOSreferenceclockrise 5 ns R(RTC_XTALIN) t Time,LVCMOSreferenceclockfall 5 ns F(RTC_XTALIN) (1) Initialaccuracy,temperaturedrift,andagingeffectsshouldbecombinedwhenevaluatingareferenceclockforthisrequirement. 112 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 6.2.2.5 OSC1NotUsed Figure 6-17 shows the recommended oscillator connections when OSC1 of the ZCE package is not used and Figure 6-18 shows the recommended oscillator connections when OSC1 of the ZCZ package is not used. An internal 10-kΩ pullup on the RTC_XTALIN terminal is turned on when OSC1 is disabled to prevent this input from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. OSC1 is disabled by default after power is applied. Therefore, both RTC_XTALIN andRTC_XTALOUTterminalsshouldbeanoconnect(NC)whenOSC1isnotused. AM335x (ZCE Package) RTC_XTALIN RTC_XTALOUT N/C N/C Copyright © 2016,Texas Instruments Incorporated Figure6-17.OSC1(ZCEPackage)NotUsedSchematic AM335x (ZCZ Package) RTC_XTALIN VSS_RTC RTC_XTALOUT N/C N/C Copyright © 2016,Texas Instruments Incorporated Figure6-18.OSC1(ZCZPackage)NotUsedSchematic Copyright©2011–2020,TexasInstrumentsIncorporated PowerandClocking 113 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 6.2.3 Output Clock Specifications The AM335x device has two clock output signals. The CLKOUT1 signal is always a replica of the OSC0 inputclockwhichisreferredtoasthemaster oscillator (CLK_M_OSC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual. The CLKOUT2 signal can be configured to output the OSC1 input clock, which is referred to as the 32K oscillator (CLK_32K_RTC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual, or four other internal clocks. For more information related to configuring these clock output signals, see the CLKOUT Signals section of the AM335x and AMIC110 SitaraProcessorsTechnicalReferenceManual. 6.2.4 Output Clock Characteristics NOTE The AM335x CLKOUT1 and CLKOUT2 clock outputs should not be used as a synchronous clock for any of the peripheral interfaces because they were not timing closed to any other signals. These clock outputs also were not designed to source any time critical external circuits that require a low jitter reference clock. The jitter performance of these outputs is unpredictable due to complex combinations of many system variables. For example, CLKOUT2maybesourcedfromseveralPLLswitheachPLLsupportingmanyconfigurations that yield different jitter performance. There are also other unpredictable contributors to jitter performance such asapplicationspecific noiseorcrosstalk into the clock circuits. Therefore, therearenoplanstospecifyjitterperformancefortheseoutputs. 6.2.4.1 CLKOUT1 The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be configuredforMode3toconnecttheCLKOUT1signaltotheXDMA_EVENT_INTR0terminal. The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level applied to the LCD_DATA5 terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0 multiplexer is configured to Mode 7 if the LCD_DATA5 terminal is low on the rising edge of PWRONRSTn or Mode 3 if the LCD_DATA5 terminal is high on the rising edge of PWRONRSTn. This allows the CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software intervention. In this mode, the output is held low while PWRONRSTn is active and begins to toggle after PWRONRSTn is released. 6.2.4.2 CLKOUT2 The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be configuredforMode3toconnecttheCLKOUT2signaltotheXDMA_EVENT_INTR1terminal. The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the XDMA_EVENT_INTR1terminal. 114 PowerandClocking Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7 Peripheral Information and Timings The AM335x device contains many peripheral interfaces. In order to reduce package size and lower overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex up to eight signal functions. Although there are many combinations of pin multiplexing that are possible, onlyacertainnumberofsets,calledI/OSets,arevalidduetotiminglimitations.ThesevalidI/OSets were carefullychosentoprovidemanypossibleapplicationscenariosfortheuser. Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the pin- multiplexingconfigurationselectedforadesignonlyusesvalidI/OSetssupportedbythe AM335xdevice. 7.1 Parameter Information Thedataprovidedinthe following Timing Requirements and Switching Characteristics tables assumes the device is operating within the Recommended Operating Conditions defined in Section 5, unless otherwise noted. 7.1.1 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing or decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logichardwaresuchasbuffersmaybeusedtocompensateanytimingdifferences. The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control registerisconfiguredforfastmode(0b). For the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routingrulestoensurethemDDR(LPDDR),DDR2,DDR3,DDR3Lmemoryinterfacetimingsaremet. 7.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between V and V (or between V and V ) in a monotonic IH IL IL IH manner. 7.3 OPP50 Support Some peripherals and features have limited support when the device is operating in OPP50. A complete listoftheselimitationsfollows. NotsupportedwhenoperatinginOPP50: Reducedperformancewhenoperatingin OPP50: • CPSW • DDR2 • DDR3 • DEBUGSS-JTAG • DEBUGSS-Trace • GPMCSynchronousMode • GPMCAsynchronousMode • LCDCRasterMode • LCDCLIDDMode • LPDDR • MDIO • McASP • PRU-ICSSMII • McSPI • MMCSD Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 115 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.4 Controller Area Network (CAN) For more information, see the Controller Area Network (CAN) section of the AM335x and AMIC110 Sitara ProcessorsTechnicalReferenceManual. 7.4.1 DCAN Electrical Data and Timing Table7-1.DCANTimingConditions (seeFigure7-1) PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 10 ns R t Inputsignalfalltime 10 ns F OutputConditions C Outputloadcapacitance 10 pF LOAD Table7-2.TimingRequirementsforDCANxReceive (seeFigure7-1) NO. MIN MAX UNIT ƒ Maximumprogrammablebaudrate 1 Mbps baud(baud) 1 t Pulseduration,receivedatabit H–2(1) H+2(1) ns w(RX) (1) H=Periodofbaudrate,1/programmedbaudrate Table7-3.SwitchingCharacteristicsforDCANxTransmit (seeFigure7-1) NO. PARAMETER MIN MAX UNIT ƒ Maximumprogrammablebaudrate 1 Mbps baud(baud) 2 t Pulseduration,transmitdatabit H–2(1) H+2(1) ns w(TX) (1) H=Periodofbaudrate,1/programmedbaudrate 1 DCANx_RX 2 DCANx_TX Figure7-1.DCANxTimings 116 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.5 DMTimer 7.5.1 DMTimer Electrical Data and Timing Table7-4.DMTimerTimingConditions (seeFigure7-1) PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 10 ns R t Inputsignalfalltime 10 ns F OutputConditions C Outputloadcapacitance 10 pF LOAD Table7-5.TimingRequirementsforDMTimer[1-7] (seeFigure7-2) NO. MIN MAX UNIT 1 t Cycletime,TCLKIN 4P+1(1) ns c(TCLKIN) (1) P=PeriodofPICLKOCP(interfaceclock). Table7-6.SwitchingCharacteristicsforDMTimer[4-7] (seeFigure7-2) NO. PARAMETER MIN MAX UNIT 2 t Pulseduration,high 4P–3(1) ns w(TIMERxH) 3 t Pulseduration,low 4P–3(1) ns w(TIMERxL) (1) P=PeriodofPICLKTIMER(functionalclock). 1 TCLKIN 2 3 TIMER[x] Figure7-2.TimerTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 117 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.6 Ethernet Media Access Controller (EMAC) and Switch 7.6.1 EMAC and Switch Electrical Data and Timing The EMAC and Switch implemented in the AM335x device supports GMII mode, but the AM335x design does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package terminals. Therefore, the AM335x device does not support GMII mode. MII mode is supported with the remaining GMIIsignals. The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may reference internal signal names when discussing peripheral input and output signals because many of the AM335x package terminals can be multiplexed to one of several peripheral signals. For example, the AM335x terminal names for port 1 of the EMAC and switch have been changed from GMII to MII to indicate their Mode 0 function, but the internal signal is named GMII. However, documents that describe the Ethernet switch reference these signals by their internal signal name. For a cross-reference of internal signalnamestoterminalnames,seeTable4-2. OperationoftheEMACandswitchisnotsupportedforOPP50. Table7-7.EMACandSwitchTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 1(1) 5(1) ns R t Inputsignalfalltime 1(1) 5(1) ns F OutputCondition C Outputloadcapacitance 3 30 pF LOAD (1) Exceptwhenspecifiedotherwise. 7.6.1.1 EMAC/SwitchMDIOElectricalDataandTiming Table7-8.TimingRequirementsforMDIO_DATA (seeFigure7-3) NO. MIN TYP MAX UNIT 1 t Setuptime,MDIOvalidbeforeMDChigh 90 ns su(MDIO-MDC) 2 t Holdtime,MDIOvalidfromMDChigh 0 ns h(MDIO-MDC) 1 2 MDIO_CLK (Output) MDIO_DATA(Input) Figure7-3.MDIO_DATATiming-InputMode Table7-9.SwitchingCharacteristicsforMDIO_CLK (seeFigure7-4) NO. PARAMETER MIN TYP MAX UNIT 1 t Cycletime,MDC 400 ns c(MDC) 2 t Pulseduration,MDChigh 160 ns w(MDCH) 3 t Pulseduration,MDClow 160 ns w(MDCL) 118 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 1 2 3 MDIO_CLK Figure7-4.MDIO_CLKTiming Table7-10.SwitchingCharacteristicsforMDIO_DATA (seeFigure7-5) NO. PARAMETER MIN TYP MAX UNIT 1 t Delaytime,MDChightoMDIOvalid -150 150 ns d(MDC-MDIO) 1 MDIO_CLK (Output) MDIO_DATA(Output) Figure7-5.MDIO_DATATiming-OutputMode 7.6.1.2 EMACandSwitchMIIElectricalDataandTiming Table7-11.TimingRequirementsforGMII[x]_RXCLK-MIIMode (seeFigure7-6) 10Mbps 100Mbps NO. UNIT MIN TYP MAX MIN TYP MAX 1 t Cycletime,RX_CLK 399.96 400.04 39.996 40.004 ns c(RX_CLK) 2 t Pulseduration,RX_CLKhigh 140 260 14 26 ns w(RX_CLKH) 3 t Pulseduration,RX_CLKlow 140 260 14 26 ns w(RX_CLKL) 4 t Transitiontime,RX_CLK 5 5 ns t(RX_CLK) 1 4 2 3 GMII[x]_RXCLK 4 Figure7-6.GMII[x]_RXCLKTiming-MIIMode Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 119 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table7-12.TimingRequirementsforGMII[x]_TXCLK-MIIMode (seeFigure7-7) 10Mbps 100Mbps NO. UNIT MIN TYP MAX MIN TYP MAX 1 t Cycletime,TX_CLK 399.96 400.04 39.996 40.004 ns c(TX_CLK) 2 t Pulseduration,TX_CLKhigh 140 260 14 26 ns w(TX_CLKH) 3 t Pulseduration,TX_CLKlow 140 260 14 26 ns w(TX_CLKL) 4 t Transitiontime,TX_CLK 5 5 ns t(TX_CLK) 1 4 2 3 GMII[x]_TXCLK 4 Figure7-7.GMII[x]_TXCLKTiming-MIIMode Table7-13.TimingRequirementsforGMII[x]_RXD[3:0],GMII[x]_RXDV,andGMII[x]_RXER-MIIMode (seeFigure7-8) NO 10Mbps 100Mbps UNIT . MIN TYP MAX MIN TYP MAX t Setuptime,RXD[3:0]validbeforeRX_CLK su(RXD-RX_CLK) 1 t Setuptime,RX_DVvalidbeforeRX_CLK 8 8 ns su(RX_DV-RX_CLK) t Setuptime,RX_ERvalidbeforeRX_CLK su(RX_ER-RX_CLK) t HoldtimeRXD[3:0]validafterRX_CLK h(RX_CLK-RXD) 2 t HoldtimeRX_DVvalidafterRX_CLK 8 8 ns h(RX_CLK-RX_DV) t HoldtimeRX_ERvalidafterRX_CLK h(RX_CLK-RX_ER) 1 2 GMII[x]_MRCLK (Input) GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER(Inputs) Figure7-8.GMII[x]_RXD[3:0],GMII[x]_RXDV,GMII[x]_RXERTiming-MIIMode 120 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-14.SwitchingCharacteristicsforGMII[x]_TXD[3:0],andGMII[x]_TXEN-MIIMode (seeFigure7-9) 10Mbps 100Mbps NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX t Delaytime,TX_CLKhightoTXD[3:0]valid d(TX_CLK-TXD) 1 5 25 5 25 ns t Delaytime,TX_CLKtoTX_ENvalid d(TX_CLK-TX_EN) 1 GMII[x]_TXCLK (input) GMII[x]_TXD[3:0], GMII[x]_TXEN(outputs) Figure7-9.GMII[x]_TXD[3:0],GMII[x]_TXENTiming-MIIMode Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 121 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.6.1.3 EMACandSwitchRMIIElectricalDataandTiming Table7-15.TimingRequirementsforRMII[x]_REFCLK-RMIIMode (seeFigure7-10) NO. MIN TYP MAX UNIT 1 t Cycletime,REF_CLK 19.999 20.001 ns c(REF_CLK) 2 t Pulseduration,REF_CLKhigh 7 13 ns w(REF_CLKH) 3 t Pulseduration,REF_CLKlow 7 13 ns w(REF_CLKL) 1 2 RMII[x]_REFCLK (Input) 3 Figure7-10.RMII[x]_REFCLKTiming-RMIIMode Table7-16.TimingRequirementsforRMII[x]_RXD[1:0],RMII[x]_CRS_DV,andRMII[x]_RXER-RMIIMode (seeFigure7-11) NO. MIN TYP MAX UNIT t Setuptime,RXD[1:0]validbeforeREF_CLK su(RXD-REF_CLK) 1 t Setuptime,CRS_DVvalidbeforeREF_CLK 4 ns su(CRS_DV-REF_CLK) t Setuptime,RX_ERvalidbeforeREF_CLK su(RX_ER-REF_CLK) t HoldtimeRXD[1:0]validafterREF_CLK h(REF_CLK-RXD) 2 t Holdtime,CRS_DVvalidafterREF_CLK 2 ns h(REF_CLK-CRS_DV) t Holdtime,RX_ERvalidafterREF_CLK h(REF_CLK-RX_ER) 1 2 RMII[x]_REFCLK (input) RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER(inputs) Figure7-11.RMII[x]_RXD[1:0],RMII[x]_CRS_DV,RMII[x]_RXERTiming-RMIIMode 122 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-17.SwitchingCharacteristicsforRMII[x]_TXD[1:0],andRMII[x]_TXEN-RMIIMode (seeFigure7-12) NO. PARAMETER MIN TYP MAX UNIT td(REF_CLK-TXD) Delaytime,REF_CLKhightoTXD[1:0]validDelaytime, 1 2 13 ns t REF_CLKtoTXENvalid d(REF_CLK-TXEN) 1 RMII[x]_REFCLK (Input) RMII[x]_TXD[1:0], RMII[x]_TXEN (Outputs) Figure7-12.RMII[x]_TXD[1:0],RMII[x]_TXENTiming-RMIIMode Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 123 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.6.1.4 EMACandSwitchRGMIIElectricalDataandTiming Table7-18.TimingRequirementsforRGMII[x]_RCLK-RGMIIMode (seeFigure7-13) 10Mbps 100Mbps 1000Mbps NO. UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 1 t Cycletime,RXC 360 440 36 44 7.2 8.8 ns c(RXC) Pulseduration,RXC 2 t 160 240 16 24 3.6 4.4 ns w(RXCH) high 3 t Pulseduration,RXClow 160 240 16 24 3.6 4.4 ns w(RXCL) 4 t Transitiontime,RXC 0.75 0.75 0.75 ns t(RXC) 1 2 3 RGMII[x]_RCLK Figure7-13.RGMII[x]_RCLKTiming-RGMIIMode Table7-19.TimingRequirementsforRGMII[x]_RD[3:0],andRGMII[x]_RCTL-RGMIIMode (seeFigure7-14) 10Mbps 100Mbps 1000Mbps NO. UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX Setuptime,RD[3:0]valid t 1 1 1 su(RD-RXC) beforeRXChighorlow 1 ns Setuptime,RX_CTLvalid t 1 1 1 su(RX_CTL-RXC) beforeRXChighorlow Holdtime,RD[3:0]validafter t 1 1 1 h(RXC-RD) RXChighorlow 2 ns Holdtime,RX_CTLvalidafter t 1 1 1 h(RXC-RX_CTL) RXChighorlow t Transitiontime,RD 0.75 0.75 0.75 t(RD) 3 ns t Transitiontime,RX_CTL 0.75 0.75 0.75 t(RX_CTL) RGMII[x]_RCLK(A) 1 1st Half-byte 2 2nd Half-byte RGMII[x]_RD[3:0](B) RGRXD[3:0] RGRXD[7:4] RGMII[x]_RCTL(B) RXDV RXERR A. RGMII[x]_RCLKmustbeexternallydelayedrelativetotheRGMII[x]_RD[3:0]andRGMII[x]_RCTLsignalstomeetthe respectivetimingrequirements. B. Dataandcontrolinformationisreceivedusingbothedgesoftheclocks.RGMII[x]_RD[3:0]carriesdatabits3-0onthe rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL carriesRXDVonrisingedgeofRGMII[x]_RCLKandRXERRonfallingedgeofRGMII[x]_RCLK. Figure7-14.RGMII[x]_RD[3:0],RGMII[x]_RCTLTiming-RGMIIMode 124 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-20.SwitchingCharacteristicsforRGMII[x]_TCLK-RGMIIMode (seeFigure7-15) 10Mbps 100Mbps 1000Mbps NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX 1 t Cycletime,TXC 360 440 36 44 7.2 8.8 ns c(TXC) Pulseduration,TXC 2 t 160 240 16 24 3.6 4.4 ns w(TXCH) high 3 t Pulseduration,TXClow 160 240 16 24 3.6 4.4 ns w(TXCL) 1 2 3 RGMII[x]_TCLK Figure7-15.RGMII[x]_TCLKTiming-RGMIIMode Table7-21.SwitchingCharacteristicsforRGMII[x]_TD[3:0],andRGMII[x]_TCTL-RGMIIMode (seeFigure7-16) 10Mbps 100Mbps 1000Mbps NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX t TDtoTXCoutputskew –0.5 0.5 –0.5 0.5 –0.5 0.5 sk(TD-TXC) 1 ns t TX_CTLtoTXCoutputskew –0.5 0.5 –0.5 0.5 –0.5 0.5 sk(TX_CTL-TXC) RGMII[x]_TCLK(A) 1 1 RGMII[x]_TD[3:0](B) 1st Half-byte 2nd Half-byte RGMII[x]_TCTL(B) TXEN TXERR A. TheEMACandswitchimplementedintheAM335xdevicesupportsinternaldelaymode,buttiming closurewasnot performedforthismodeofoperation.Therefore,theAM335xdevicedoesnotsupportinternaldelaymode. B. Dataandcontrolinformationistransmittedusingbothedgesoftheclocks.RGMII[x]_TD[3:0]carriesdatabits3-0on therisingedgeofRGMII[x]_TCLKanddatabits7-4onthefallingedgeofRGMII[x]_TCLK.Similarly,RGMII[x]_TCTL carriesTXENonrisingedgeofRGMII[x]_TCLKandTXERRoffallingedgeofRGMII[x]_TCLK. Figure7-16.RGMII[x]_TD[3:0],RGMII[x]_TCTLTiming-RGMIIMode Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 125 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7 External Memory Interfaces Thedeviceincludesthefollowingexternalmemoryinterfaces: • General-purposememorycontroller(GPMC) • mDDR(LPDDR),DDR2,DDR3,DDR3LMemoryInterface(EMIF) 7.7.1 General-Purpose Memory Controller (GPMC) NOTE For more information, see the Memory Subsystem and General-Purpose Memory Controller sectionoftheAM335xandAMIC110SitaraProcessorsTechnicalReferenceManual. TheGPMCistheunifiedmemorycontrollerusedtointerfaceexternalmemorydevicessuchas: • AsynchronousSRAM-likememoriesandASICdevices • AsynchronouspagemodeandsynchronousburstNORflash • NANDflash 7.7.1.1 GPMCandNORFlash—SynchronousMode Table 7-23 and Table 7-24 assume testing over the recommended operating conditions and electrical characteristicconditionsshowninTable7-22 (seeFigure7-17throughFigure7-21). Table7-22.GPMCandNORFlashTimingConditions—SynchronousMode PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 1 5 ns R t Inputsignalfalltime 1 5 ns F OutputCondition C Outputloadcapacitance 3 30 pF LOAD Table7-23.GPMCandNORFlashTimingRequirements—SynchronousMode OPP100 OPP50 NO. UNIT MIN MAX MIN MAX Setuptime,inputdatagpmc_ad[15:0]validbeforeoutputclock F12 t 3.2 13.2 ns su(dV-clkH) gpmc_clkhigh Industrialextended Holdtime,inputdatagpmc_ad[15:0] temperature 4.74 4.74 F13 th(clkH-dV) validafteroutputclockgpmc_clk (-40°Cto125°C) ns high Allothertemperatureranges 4.74 2.75 Setuptime,inputwaitgpmc_wait[x](1)validbeforeoutputclock F21 t 3.2 13.2 ns su(waitV-clkH) gpmc_clkhigh Industrialextended Holdtime,inputwaitgpmc_wait[x](1) temperature 4.74 4.74 F22 th(clkH-waitV) validafteroutputclockgpmc_clk (-40°Cto125°C) ns high Allothertemperatureranges 4.74 2.75 (1) Ingpmc_wait[x],xisequalto0or1. 126 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-24.GPMCandNORFlashSwitchingCharacteristics—SynchronousMode(2) OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX F0 1/t Frequency(18),outputclockgpmc_clk 100 50 MHz c(clk) F1 t Typicalpulseduration,outputclockgpmc_clkhigh 0.5P(15) 0.5P(15) 0.5P(15) 0.5P(15) ns w(clkH) F1 t Typicalpulseduration,outputclockgpmc_clklow 0.5P(15) 0.5P(15) 0.5P(15) 0.5P(15) ns w(clkL) t Dutycycleerror,outputclockgpmc_clk –500 500 –500 500 ps dc(clk) t Jitterstandarddeviation(19),outputclockgpmc_clk 33.33 33.33 ps J(clk) F2 td(clkH-csnV) Douetlpauyttcimhiep,soeultepcuttgcplomcck_gcpsmn[cx_](c14lk)trriasninsgitieodngeto F(6)-2.2 F(6)+4.5 F(6)-3.2 F(6)+9.5 ns F3 td(clkH-csnIV) Douetlpauyttcimhiep,soeultepcuttgcplomcck_gcpsmn[cx_](c14lk)irnisvianlgidedgeto E(5)–2.2 E(5)+4.5 E(5)–3.2 E(5)+9.5 ns F4 t Delaytime,outputaddressgpmc_a[27:1]validto B(2)–4.5 B(2)+2.3 B(2)–5.5 B(2)+12.3 ns d(aV-clk) outputclockgpmc_clkfirstedge Delaytime,outputclockgpmc_clkrisingedgeto F5 t –2.3 4.5 –3.3 14.5 ns d(clkH-aIV) outputaddressgpmc_a[27:1]invalid Delaytime,outputlowerbyteenableandcommand F6 t latchenablegpmc_be0n_cle,outputupperbyte B(2)–1.9 B(2)+2.3 B(2)–2.9 B(2)+12.3 ns d(be[x]nV-clk) enablegpmc_be1nvalidtooutputclockgpmc_clk firstedge Delaytime,outputclockgpmc_clkrisingedgeto F7 t outputlowerbyteenableandcommandlatchenable D(4)–2.3 D(4)+1.9 D(4)–3.3 D(4)+6.9 ns d(clkH-be[x]nIV) gpmc_be0n_cle,outputupperbyteenable gpmc_be1ninvalid(11) F7 td(clkL-be[x]nIV) Dgpemlacy_tnimbee0,_gcplme,cg_pcmlkcf_anllibneg1eidngvealitdo(12) D(4)–2.3 D(4)+1.9 D(4)–3.3 D(4)+6.9 ns F7 td(clkL-be[x]nIV) Dgpemlacy_tnimbee0,_gcplme,cg_pcmlkcf_anllibneg1eidngvealitdo(13) D(4)–2.3 D(4)+1.9 D(4)–3.3 D(4)+11.9 ns Delaytime,outputclockgpmc_clkrisingedgeto F8 t outputaddressvalidandaddresslatchenable G(7)–2.3 G(7)+4.5 G(7)–3.3 G(7)+9.5 ns d(clkH-advn) gpmc_advn_aletransition Delaytime,outputclockgpmc_clkrisingedgeto F9 t outputaddressvalidandaddresslatchenable D(4)–2.3 D(4)+3.5 D(4)–3.3 D(4)+9.5 ns d(clkH-advnIV) gpmc_advn_aleinvalid F10 t Delaytime,outputclockgpmc_clkrisingedgeto H(8)–2.3 H(8)+3.5 H(8)–3.3 H(8)+8.5 ns d(clkH-oen) outputenablegpmc_oentransition F11 t Delaytime,outputclockgpmc_clkrisingedgeto H(8)–2.3 H(8)+3.5 H(8)–3.3 H(8)+8.5 ns d(clkH-oenIV) outputenablegpmc_oeninvalid F14 t Delaytime,outputclockgpmc_clkrisingedgeto I(9)–2.3 I(9)+4.5 I(9)–3.3 I(9)+9.5 ns d(clkH-wen) outputwriteenablegpmc_wentransition F15 td(clkH-do) Douetlpauyttdimaeta,oguptmpuc_tacdlo[c1k5:g0p]mtracn_sciltkiornis(1in1g) edgeto J(10)–2.3 J(10)+1.9 J(10)–3.3 J(10)+6.9 ns F15 td(clkL-do) Ddaetlaaybutimster,agnpsimtiocn_(c1l2k)fallingedgetogpmc_ad[15:0] J(10)–2.3 J(10)+1.9 J(10)–3.3 J(10)+6.9 ns F15 td(clkL-do) Ddaetlaaybutimster,agnpsimtiocn_(c1l3k)fallingedgetogpmc_ad[15:0] J(10)–2.3 J(10)+1.9 J(10)–3.3 J(10)+11.9 ns Delaytime,outputclockgpmc_clkrisingedgeto F17 t outputlowerbyteenableandcommandlatchenable J(10)–2.3 J(10)+1.9 J(10)–3.3 J(10)+6.9 ns d(clkH-be[x]n) gpmc_be0n_cletransition(11) F17 td(clkL-be[x]n) Dgpemlacy_tnimbee0,_gcplme,cg_pcmlkcf_anllibneg1etdragnestiotion(12) J(10)–2.3 J(10)+1.9 J(10)–3.3 J(10)+6.9 ns F17 td(clkL-be[x]n) Dgpemlacy_tnimbee0,_gcplme,cg_pcmlkcf_anllibneg1etdragnestiotion(13) J(10)–2.3 J(10)+1.9 J(10)–3.3 J(10)+11.9 ns Pulseduration,outputchipselect Read A(1) A(1) ns F18 tw(csnV) gpmc_csn[x](14)low Write A(1) A(1) ns Pulseduration,outputlowerbyteenable Read C(3) C(3) ns andcommandlatchenable F19 t Write w(be[x]nV) gpmc_be0n_cle,outputupperbyteenable C(3) C(3) ns gpmc_be1nlow Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 127 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table7-24.GPMCandNORFlashSwitchingCharacteristics—SynchronousMode(2) (continued) OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX Pulseduration,outputaddressvalidand Read K(16) K(16) ns F20 t w(advnV) addresslatchenablegpmc_advn_alelow Write K(16) K(16) ns (1) Forsingleread:A=(CSRdOffTime–CSOnTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstread:A=(CSRdOffTime–CSOnTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstwrite:A=(CSWrOffTime–CSOnTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Withnbeingthepageburstaccessnumber. (2) B=ClkActivationTime×GPMC_FCLK(17) (3) Forsingleread:C=RdCycleTime×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstread:C=(RdCycleTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstwrite:C=(WrCycleTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Withnbeingthepageburstaccessnumber. (4) Forsingleread:D=(RdCycleTime–AccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstread:D=(RdCycleTime–AccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstwrite:D=(WrCycleTime–AccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) (5) Forsingleread:E=(CSRdOffTime–AccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstread:E=(CSRdOffTime–AccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forburstwrite:E=(CSWrOffTime–AccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) (6) Forcsnfallingedge(CSactivated): – CaseGpmcFCLKDivider=0: – F=0.5×CSExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – F=0.5×CSExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandCSOnTimeareodd)or(ClkActivationTimeand CSOnTimeareeven) – F=(1+0.5×CSExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – F=0.5×CSExtraDelay×GPMC_FCLK(17)if((CSOnTime–ClkActivationTime)isamultipleof3) – F=(1+0.5×CSExtraDelay)×GPMC_FCLK(17)if((CSOnTime–ClkActivationTime–1)isamultipleof3) – F=(2+0.5×CSExtraDelay)×GPMC_FCLK(17)if((CSOnTime–ClkActivationTime–2)isamultipleof3) (7) ForADVfallingedge(ADVactivated): – CaseGpmcFCLKDivider=0: – G=0.5×ADVExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – G=0.5×ADVExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandADVOnTimeareodd)or(ClkActivationTimeand ADVOnTimeareeven) – G=(1+0.5×ADVExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – G=0.5×ADVExtraDelay×GPMC_FCLK(17)if((ADVOnTime–ClkActivationTime)isamultipleof3) – G=(1+0.5×ADVExtraDelay)×GPMC_FCLK(17)if((ADVOnTime–ClkActivationTime–1)isamultipleof3) – G=(2+0.5×ADVExtraDelay)×GPMC_FCLK(17)if((ADVOnTime–ClkActivationTime–2)isamultipleof3) ForADVrisingedge(ADVdeactivated)inReadingmode: – CaseGpmcFCLKDivider=0: – G=0.5×ADVExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – G=0.5×ADVExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandADVRdOffTimeareodd)or(ClkActivationTimeand ADVRdOffTimeareeven) – G=(1+0.5×ADVExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – G=0.5×ADVExtraDelay×GPMC_FCLK(17)if((ADVRdOffTime–ClkActivationTime)isamultipleof3) – G=(1+0.5×ADVExtraDelay)×GPMC_FCLK(17)if((ADVRdOffTime–ClkActivationTime–1)isamultipleof3) – G=(2+0.5×ADVExtraDelay)×GPMC_FCLK(17)if((ADVRdOffTime–ClkActivationTime–2)isamultipleof3) ForADVrisingedge(ADVdeactivated)inWritingmode: – CaseGpmcFCLKDivider=0: – G=0.5×ADVExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – G=0.5×ADVExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandADVWrOffTimeareodd)or(ClkActivationTimeand ADVWrOffTimeareeven) – G=(1+0.5×ADVExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – G=0.5×ADVExtraDelay×GPMC_FCLK(17)if((ADVWrOffTime–ClkActivationTime)isamultipleof3) – G=(1+0.5×ADVExtraDelay)×GPMC_FCLK(17)if((ADVWrOffTime–ClkActivationTime–1)isamultipleof3) – G=(2+0.5×ADVExtraDelay)×GPMC_FCLK(17)if((ADVWrOffTime–ClkActivationTime–2)isamultipleof3) 128 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 (8) ForOEfallingedge(OEactivated)andI/ODIRrisingedge(DataBusinputdirection): – CaseGpmcFCLKDivider=0: – H=0.5×OEExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – H=0.5×OEExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandOEOnTimeareodd)or(ClkActivationTimeand OEOnTimeareeven) – H=(1+0.5×OEExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – H=0.5×OEExtraDelay×GPMC_FCLK(17)if((OEOnTime–ClkActivationTime)isamultipleof3) – H=(1+0.5×OEExtraDelay)×GPMC_FCLK(17)if((OEOnTime–ClkActivationTime–1)isamultipleof3) – H=(2+0.5×OEExtraDelay)×GPMC_FCLK(17)if((OEOnTime–ClkActivationTime–2)isamultipleof3) ForOErisingedge(OEdeactivated): – CaseGpmcFCLKDivider=0: – H=0.5×OEExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – H=0.5×OEExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandOEOffTimeareodd)or(ClkActivationTimeand OEOffTimeareeven) – H=(1+0.5×OEExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – H=0.5×OEExtraDelay×GPMC_FCLK(17)if((OEOffTime–ClkActivationTime)isamultipleof3) – H=(1+0.5×OEExtraDelay)×GPMC_FCLK(17)if((OEOffTime–ClkActivationTime–1)isamultipleof3) – H=(2+0.5×OEExtraDelay)×GPMC_FCLK(17)if((OEOffTime–ClkActivationTime–2)isamultipleof3) (9) ForWEfallingedge(WEactivated): – CaseGpmcFCLKDivider=0: – I=0.5×WEExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – I=0.5×WEExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandWEOnTimeareodd)or(ClkActivationTimeand WEOnTimeareeven) – I=(1+0.5×WEExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – I=0.5×WEExtraDelay×GPMC_FCLK(17)if((WEOnTime–ClkActivationTime)isamultipleof3) – I=(1+0.5×WEExtraDelay)×GPMC_FCLK(17)if((WEOnTime–ClkActivationTime–1)isamultipleof3) – I=(2+0.5×WEExtraDelay)×GPMC_FCLK(17)if((WEOnTime–ClkActivationTime–2)isamultipleof3) ForWErisingedge(WEdeactivated): – CaseGpmcFCLKDivider=0: – I=0.5×WEExtraDelay×GPMC_FCLK(17) – CaseGpmcFCLKDivider=1: – I=0.5×WEExtraDelay×GPMC_FCLK(17)if(ClkActivationTimeandWEOffTimeareodd)or(ClkActivationTimeand WEOffTimeareeven) – I=(1+0.5×WEExtraDelay)×GPMC_FCLK(17)otherwise – CaseGpmcFCLKDivider=2: – I=0.5×WEExtraDelay×GPMC_FCLK(17)if((WEOffTime–ClkActivationTime)isamultipleof3) – I=(1+0.5×WEExtraDelay)×GPMC_FCLK(17)if((WEOffTime–ClkActivationTime–1)isamultipleof3) – I=(2+0.5×WEExtraDelay)×GPMC_FCLK(17)if((WEOffTime–ClkActivationTime–2)isamultipleof3) (10) J=GPMC_FCLK(17) (11) FirsttransferonlyforCLKDIV1mode. (12) Halfcycle;foralldataafterinitialtransferforCLKDIV1mode. (13) HalfcycleofGPMC_CLK_OUT;foralldataformodesotherthanCLKDIV1mode.GPMC_CLK_OUTdividedownfromGPMC_FCLK. (14) Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. (15) P=gpmc_clkperiodinns (16) Forread:K=(ADVRdOffTime–ADVOnTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) Forwrite:K=(ADVWrOffTime–ADVOnTime)×(TimeParaGranularity+1)×GPMC_FCLK(17) (17) GPMC_FCLKisgeneral-purposememorycontrollerinternalfunctionalclockperiodinns. (18) Relatedtothegpmc_clkoutputclockmaximumandminimumfrequenciesprogrammableintheGPMCmodulebysettingthe GPMC_CONFIG1_CSxconfigurationregisterbitfieldGpmcFCLKDivider. (19) ThejitterprobabilitydensitycanbeapproximatedbyaGaussianfunction. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 129 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com F1 F0 F1 gpmc_clk F2 F3 F18 gpmc_csn[x] F4 gpmc_a[10:1] ValidAddress F6 F7 F19 gpmc_be0n_cle F19 gpmc_be1n F6 F8 F8 F20 F9 gpmc_advn_ale F10 F11 gpmc_oen F13 F12 gpmc_ad[15:0] D 0 gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. B. Ingpmc_wait[x],xisequalto0or1. Figure7-17.GPMCandNORFlash—SynchronousSingleRead—(GpmcFCLKDivider=0) 130 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 F1 F0 F1 gpmc_clk F2 F3 gpmc_csn[x] F4 gpmc_a[10:1] ValidAddress F6 F7 gpmc_be0n_cle F7 gpmc_be1n F6 F8 F8 F9 gpmc_advn_ale F10 F11 gpmc_oen F13 F13 F12 F12 gpmc_ad[15:0] D 0 D 1 D 2 D 3 F21 F22 gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. B. Ingpmc_wait[x],xisequalto0or1. Figure7-18.GPMCandNORFlash—SynchronousBurstRead—4x16-Bit(GpmcFCLKDivider=0) Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 131 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com F1 F1 F0 gpmc_clk F2 F3 gpmc_csn[x] F4 gpmc_a[10:1] ValidAddress F17 F6 F17 F17 gpmc_be0n_cle F17 F17 F17 gpmc_be1n F6 F8 F8 F9 gpmc_advn_ale F14 F14 gpmc_wen F15 F15 F15 gpmc_ad[15:0] D 0 D 1 D 2 D 3 gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. B. Ingpmc_wait[x],xisequalto0or1. Figure7-19.GPMCandNORFlash—SynchronousBurstWrite—(GpmcFCLKDivider >0) 132 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 F1 F0 F1 gpmc_clk F2 F3 gpmc_csn[x] F6 F7 gpmc_be0n_cle Valid F6 F7 gpmc_be1n Valid F4 gpmc_a[27:17] Address (MSB) F12 F4 F5 F13 F12 gpmc_ad[15:0] Address (LSB) D0 D1 D2 D3 F8 F8 F9 gpmc_advn_ale F10 F11 gpmc_oen gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. B. Ingpmc_wait[x],xisequalto0or1. Figure7-20.GPMCandMultiplexedNORFlash—SynchronousBurstRead Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 133 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com F1 F1 F0 gpmc_clk F2 F3 F18 gpmc_csn[x] F4 gpmc_a[27:17] Address (MSB) F17 F6 F17 F17 gpmc_be1n F17 F6 F17 F17 gpmc_be0n_cle F8 F8 F20 F9 gpmc_advn_ale F14 F14 gpmc_wen F15 F15 F15 gpmc_ad[15:0] Address (LSB) D 0 D 1 D 2 D 3 F21 F22 gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. B. Ingpmc_wait[x],xisequalto0or1. Figure7-21.GPMCandMultiplexedNORFlash—SynchronousBurstWrite 134 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.1.2 GPMCandNORFlash—AsynchronousMode Table 7-26 and Table 7-27 assume testing over the recommended operating conditions and electrical characteristicconditionsshowninTable7-25 (seeFigure7-22throughFigure7-27). Table7-25.GPMCandNORFlashTimingConditions—AsynchronousMode MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 1 5 ns R t Inputsignalfalltime 1 5 ns F OutputCondition C Outputloadcapacitance 3 30 pF LOAD Table7-26.GPMCandNORFlashInternalTimingRequirements—AsynchronousMode(1)(2) OPP100 OPP50 NO. UNIT MIN MAX MIN MAX Delaytime,outputdatagpmc_ad[15:0]generationfrominternalfunctionalclock FI1 GPMC_FCLK(3) 6.5 6.5 ns Delaytime,inputdatagpmc_ad[15:0]capturefrominternalfunctionalclock FI2 GPMC_FCLK(3) 4 4 ns Delaytime,outputchipselectgpmc_csn[x]generationfrominternalfunctional FI3 clockGPMC_FCLK(3) 6.5 6.5 ns Delaytime,outputaddressgpmc_a[27:1]generationfrominternalfunctionalclock FI4 GPMC_FCLK(3) 6.5 6.5 ns Delaytime,outputaddressgpmc_a[27:1]validfrominternalfunctionalclock FI5 GPMC_FCLK(3) 6.5 6.5 ns Delaytime,outputlower-byteenableandcommandlatchenablegpmc_be0n_cle, FI6 outputupper-byteenablegpmc_be1ngenerationfrominternalfunctionalclock 6.5 6.5 ns GPMC_FCLK(3) Delaytime,outputenablegpmc_oengenerationfrominternalfunctionalclock FI7 GPMC_FCLK(3) 6.5 6.5 ns Delaytime,outputwriteenablegpmc_wengenerationfrominternalfunctional FI8 clockGPMC_FCLK(3) 6.5 6.5 ns FI9 Skew,internalfunctionalclockGPMC_FCLK(3) 100 100 ps (1) TheinternalparameterstablemustbeusedtocalculatedataaccesstimestoredinthecorrespondingCSregisterbitfield. (2) InternalparametersarereferredtotheGPMCfunctionalinternalclockwhichisnotprovidedexternally. (3) GPMC_FCLKisgeneral-purposememorycontrollerinternalfunctionalclock. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 135 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table7-27.GPMCandNORFlashTimingRequirements—AsynchronousMode NO. OPP100 OPP50 UNIT MIN MAX MIN MAX FA5(1) t Dataaccesstime H(5) H(5) ns acc(d) FA20(2) t Pagemodesuccessivedataaccesstime P(4) P(4) ns acc1-pgmode(d) FA21(3) t Pagemodefirstdataaccesstime H(5) H(5) ns acc2-pgmode(d) (1) TheFA5parametershowstheamountoftimerequiredtointernallysampleinputdata.ItisexpressedinnumberofGPMCfunctional clockcycles.FromstartofreadcycleandafterFA5functionalclockcycles,inputdataisinternallysampledbyactivefunctionalclock edge.FA5valuemustbestoredinsidetheAccessTimeregisterbitfield. (2) TheFA20parametershowsamountoftimerequiredtointernallysamplesuccessiveinputpagedata.Itisexpressedinnumberof GPMCfunctionalclockcycles.Aftereachaccesstoinputpagedata,nextinputpagedataisinternallysampledbyactivefunctionalclock edgeafterFA20functionalclockcycles.TheFA20valuemustbestoredinthePageBurstAccessTimeregisterbitfield. (3) TheFA21parametershowsamountoftimerequiredtointernallysamplefirstinputpagedata.ItisexpressedinnumberofGPMC functionalclockcycles.FromstartofreadcycleandafterFA21functionalclockcycles,firstinputpagedataisinternallysampledby activefunctionalclockedge.FA21valuemustbestoredinsidetheAccessTimeregisterbitfield. (4) P=PageBurstAccessTime×(TimeParaGranularity+1)×GPMC_FCLK(6) (5) H=AccessTime×(TimeParaGranularity+1)×GPMC_FCLK(6) (6) GPMC_FCLKisgeneral-purposememorycontrollerinternalfunctionalclockperiodinns. Table7-28.GPMCandNORFlashSwitchingCharacteristics—AsynchronousMode OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX Pulseduration,outputlower-byte Read N(12) N(12) enableandcommandlatchenable FA0 t ns w(be[x]nV) gpmc_be0n_cle,outputupper-byte Write N(12) N(12) enablegpmc_be1nvalidtime Pulseduration,outputchipselect Read A(1) A(1) FA1 tw(csnV) gpmc_csn[x](13)low Write A(1) A(1) ns Delaytime,outputchipselect Read B(2)–0.2 B(2)+2.0 B(2)–5 B(2)+5 gpmc_csn[x](13)validtooutput FA3 t ns d(csnV-advnIV) addressvalidandaddresslatch Write B(2)–0.2 B(2)+2.0 B(2)–5 B(2)+5 enablegpmc_advn_aleinvalid Delaytime,outputchipselectgpmc_csn[x](13) FA4 t validtooutputenablegpmc_oeninvalid(Single C(3)–0.2 C(3)+2.0 C(3)–5 C(3)+5 ns d(csnV-oenIV) read) FA9 td(aV-csnV) Dtoeolauytptuimtech,iopustpeuletcatdgdprmescs_cgspnm[xc]_(1a3[)2v7a:1lid]valid J(9)–0.2 J(9)+2.0 J(9)–5 J(9)+5 ns Delaytime,outputlower-byteenableand FA10 t commandlatchenablegpmc_be0n_cle,output J(9)–0.2 J(9)+2.0 J(9)–5 J(9)+5 ns d(be[x]nV-csnV) upper-byteenablegpmc_be1nvalidtooutput chipselectgpmc_csn[x](13)valid Delaytime,outputchipselectgpmc_csn[x](13) FA12 t validtooutputaddressvalidandaddresslatch K(10)–0.2 K(10)+2.0 K(10)–5 K(10)+5 ns d(csnV-advnV) enablegpmc_advn_alevalid FA13 t Delaytime,outputchipselectgpmc_csn[x](13) L(11)–0.2 L(11)+2.0 L(11)–5 L(11)+5 ns d(csnV-oenV) validtooutputenablegpmc_oenvalid Pulsedurationmoutputaddressgpmc_a[26:1] FA16 t invalidbetween2successivereadandwrite G(7) G(7) ns w(aIV) accesses Delaytime,outputchipselectgpmc_csn[x](13) FA18 t validtooutputenablegpmc_oeninvalid(Burst I(8)–0.2 I(8)+2.0 I(8)–5 I(8)+5 ns d(csnV-oenIV) read) FA20 t Pulseduration,outputaddressgpmc_a[27:1] D(4) D(4) ns w(aV) valid-2nd,3rd,and4thaccesses FA25 t Delaytime,outputchipselectgpmc_csn[x](13) E(5)–0.2 E(5)+2.0 E(5)–5 E(5)+5 ns d(csnV-wenV) validtooutputwriteenablegpmc_wenvalid FA27 t Delaytime,outputchipselectgpmc_csn[x](13) F(6)–0.2 F(6)+2.0 F(6)–5 F(6)+5 ns d(csnV-wenIV) validtooutputwriteenablegpmc_weninvalid 136 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-28.GPMCandNORFlashSwitchingCharacteristics—AsynchronousMode(continued) OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX Delaytime,outputwriteenablegpmc_wen FA28 t 2.0 5 ns d(wenV-dV) validtooutputdatagpmc_ad[15:0]valid FA29 td(dV-csnV) Douetlpauyttcimhiep,soeultepcuttgdpamtac_gcpsmnc[x_]a(1d3[)1v5a:l0id]validto J(9)–0.2 J(9)+2.0 J(9)–5 J(9)+5 ns Delaytime,outputenablegpmc_oenvalidto FA37 t 2.0 5 ns d(oenV-aIV) outputaddressgpmc_ad[15:0]phaseend (1) Forsingleread:A=(CSRdOffTime–CSOnTime)×(TimeParaGranularity+1)×GPMC_FCLK(14) Forsinglewrite:A=(CSWrOffTime–CSOnTime)×(TimeParaGranularity+1)×GPMC_FCLK(14) Forburstread:A=(CSRdOffTime–CSOnTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(14) Forburstwrite:A=(CSWrOffTime–CSOnTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(14) withnbeingthepageburstaccessnumber (2) Forreading:B=((ADVRdOffTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(ADVExtraDelay–CSExtraDelay))× GPMC_FCLK(14) Forwriting:B=((ADVWrOffTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(ADVExtraDelay–CSExtraDelay))× GPMC_FCLK(14) (3) C=((OEOffTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(OEExtraDelay–CSExtraDelay))×GPMC_FCLK(14) (4) D=PageBurstAccessTime×(TimeParaGranularity+1)×GPMC_FCLK(14) (5) E=((WEOnTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(WEExtraDelay–CSExtraDelay))×GPMC_FCLK(14) (6) F=((WEOffTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(WEExtraDelay–CSExtraDelay))×GPMC_FCLK(14) (7) G=Cycle2CycleDelay×GPMC_FCLK(14) (8) I=((OEOffTime+(n–1)×PageBurstAccessTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(OEExtraDelay–CSExtraDelay)) ×GPMC_FCLK(14) (9) J=(CSOnTime×(TimeParaGranularity+1)+0.5×CSExtraDelay)×GPMC_FCLK(14) (10) K=((ADVOnTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(ADVExtraDelay–CSExtraDelay))×GPMC_FCLK(14) (11) L=((OEOnTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(OEExtraDelay–CSExtraDelay))×GPMC_FCLK(14) (12) Forsingleread:N=RdCycleTime×(TimeParaGranularity+1)×GPMC_FCLK(14) Forsinglewrite:N=WrCycleTime×(TimeParaGranularity+1)×GPMC_FCLK(14) Forburstread:N=(RdCycleTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(14) Forburstwrite:N=(WrCycleTime+(n–1)×PageBurstAccessTime)×(TimeParaGranularity+1)×GPMC_FCLK(14) (13) Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. (14) GPMC_FCLKisgeneral-purposememorycontrollerinternalfunctionalclockperiodinns. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 137 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com GPMC_FCLK gpmc_clk FA5 FA1 gpmc_csn[x] FA9 gpmc_a[10:1] ValidAddress FA0 FA10 gpmc_be0n_cle Valid FA0 gpmc_be1n Valid FA10 FA3 FA12 gpmc_advn_ale FA4 FA13 gpmc_oen gpmc_ad[15:0] Data IN 0 Data IN 0 gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. B. FA5parameterillustratesamountoftimerequiredtointernallysampleinputdata.ItisexpressedinnumberofGPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampledbyactivefunctionalclockedge.FA5valuemustbestoredinsideAccessTimeregisterbitsfield. C. GPMC_FCLKisaninternalclock(GPMCfunctionalclock)notprovidedexternally. Figure7-22.GPMCandNORFlash—AsynchronousRead—SingleWord 138 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 GPMC_FCLK gpmc_clk FA5 FA5 FA1 FA1 gpmc_csn[x] FA16 FA9 FA9 gpmc_a[10:1] Address 0 Address 1 FA0 FA0 FA10 FA10 gpmc_be0n_cle Valid Valid FA0 FA0 gpmc_be1n Valid Valid FA10 FA10 FA3 FA3 FA12 FA12 gpmc_advn_ale FA4 FA4 FA13 FA13 gpmc_oen gpmc_ad[15:0] Data Upper gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. B. FA5parameterillustratesamountoftimerequiredtointernallysampleinputdata.ItisexpressedinnumberofGPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampledbyactivefunctionalclockedge.FA5valuemustbestoredinsideAccessTimeregisterbitsfield. C. GPMC_FCLKisaninternalclock(GPMCfunctionalclock)notprovidedexternally. Figure7-23.GPMCandNORFlash—AsynchronousRead—32-Bit Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 139 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com GPMC_FCLK gpmc_clk FA21 FA20 FA20 FA20 FA1 gpmc_csn[x] FA9 gpmc_a[10:1] Add0 Add1 Add2 Add3 Add4 FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA12 gpmc_advn_ale FA18 FA13 gpmc_oen gpmc_ad[15:0] D0 D1 D2 D3 D3 gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in numberofGPMCfunctionalclockcycles.From startofread cycleandafterFA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTimeregisterbitsfield. C. FA20parameterillustratesamountoftimerequiredtointernallysamplesuccessiveinputpagedata.Itisexpressedin numberofGPMCfunctionalclockcycles.Aftereachaccesstoinputpagedata,nextinputpagedatawillbeinternally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTimeregisterbitsfield. D. GPMC_FCLKisaninternalclock(GPMCfunctionalclock)notprovidedexternally. Figure7-24.GPMCandNORFlash—AsynchronousRead—PageMode4x16-Bit 140 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 gpmc_fclk gpmc_clk FA1 gpmc_csn[x] FA9 gpmc_a[10:1] ValidAddress FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA3 FA12 gpmc_advn_ale FA27 FA25 gpmc_wen FA29 gpmc_ad[15:0] Data OUT gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. Figure7-25.GPMCandNORFlash—AsynchronousWrite—SingleWord Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 141 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com GPMC_FCLK gpmc_clk FA1 FA5 gpmc_csn[x] FA9 gpmc_a[27:17] Address (MSB) FA0 FA10 gpmc_be0n_cle Valid FA0 FA10 gpmc_be1n Valid FA3 FA12 gpmc_advn_ale FA4 FA13 gpmc_oen FA29 FA37 gpmc_ad[15:0] Address (LSB) Data IN Data IN gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. B. FA5parameterillustratesamountoftimerequiredtointernallysampleinputdata.ItisexpressedinnumberofGPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampledbyactivefunctionalclockedge.FA5valuemustbestoredinsideAccessTimeregisterbitsfield. C. GPMC_FCLKisaninternalclock(GPMCfunctionalclock)notprovidedexternally. Figure7-26.GPMCandMultiplexedNORFlash—AsynchronousRead—SingleWord 142 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 gpmc_fclk gpmc_clk FA1 gpmc_csn[x] FA9 gpmc_a[27:17] Address (MSB) FA0 FA10 gpmc_be0n_cle FA0 FA10 gpmc_be1n FA3 FA12 gpmc_advn_ale FA27 FA25 gpmc_wen FA29 FA28 gpmc_ad[15:0] ValidAddress (LSB) Data OUT gpmc_wait[x] A. Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. Figure7-27.GPMCandMultiplexedNORFlash—AsynchronousWrite—SingleWord Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 143 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.1.3 GPMCandNANDFlash—AsynchronousMode Table 7-30 and Table 7-31 assume testing over the recommended operating conditions and electrical characteristicconditionsshowninTable7-29 (seeFigure7-28throughFigure7-31). Table7-29.GPMCandNANDFlashTimingConditions—AsynchronousMode PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 1 5 ns R t Inputsignalfalltime 1 5 ns F OutputCondition C Outputloadcapacitance 3 30 pF LOAD Table7-30.GPMCandNANDFlashInternalTimingRequirements—AsynchronousMode(1)(2) OPP100 OPP50 NO. UNIT MIN MAX MIN MAX Delaytime,outputdatagpmc_ad[15:0]generationfrominternal GNFI1 functionalclockGPMC_FCLK(3) 6.5 6.5 ns Delaytime,inputdatagpmc_ad[15:0]capturefrominternalfunctional GNFI2 clockGPMC_FCLK(3) 4.0 4.0 ns Delaytime,outputchipselectgpmc_csn[x]generationfrominternal GNFI3 functionalclockGPMC_FCLK(3) 6.5 6.5 ns Delaytime,outputaddressvalidandaddresslatchenable GNFI4 gpmc_advn_alegenerationfrominternalfunctionalclock 6.5 6.5 ns GPMC_FCLK(3) Delaytime,outputlower-byteenableandcommandlatchenable GNFI5 gpmc_be0n_clegenerationfrominternalfunctionalclock 6.5 6.5 ns GPMC_FCLK(3) Delaytime,outputenablegpmc_oengenerationfrominternalfunctional GNFI6 clockGPMC_FCLK(3) 6.5 6.5 ns Delaytime,outputwriteenablegpmc_wengenerationfrominternal GNFI7 functionalclockGPMC_FCLK(3) 6.5 6.5 ns GNFI8 Skew,functionalclockGPMC_FCLK(3) 100 100 ps (1) InternalparameterstablemustbeusedtocalculatedataaccesstimestoredinthecorrespondingCSregisterbitfield. (2) InternalparametersarereferredtotheGPMCfunctionalinternalclockwhichisnotprovidedexternally. (3) GPMC_FCLKisgeneral-purposememorycontrollerinternalfunctionalclock. Table7-31.GPMCandNANDFlashTimingRequirements—AsynchronousMode OPP100 OPP50 NO. UNIT MIN MAX MIN MAX GNF12(1) t Accesstime,inputdatagpmc_ad[15:0] J(2) J(2) ns acc(d) (1) TheGNF12parameterillustratestheamountoftimerequiredtointernallysampleinputdata.ItisexpressedinnumberofGPMC functionalclockcycles.FromstartofthereadcycleandafterGNF12functionalclockcycles,inputdataisinternallysampledbythe activefunctionalclockedge.TheGNF12valuemustbestoredinsideAccessTimeregisterbitfield. (2) J=AccessTime×(TimeParaGranularity+1)×GPMC_FCLK(3) (3) GPMC_FCLKisgeneral-purposememorycontrollerinternalfunctionalclockperiodinns. 144 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-32.GPMCandNANDFlashSwitchingCharacteristics—AsynchronousMode OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX GNF0 t Pulseduration,outputwriteenablegpmc_wen A(1) A(1) ns w(wenV) valid GNF1 t Delaytime,outputchipselectgpmc_csn[x](13) B(2)–0.2 B(2)+2.0 B(2)–5 B(2)+5 ns d(csnV-wenV) validtooutputwriteenablegpmc_wenvalid Delaytime,outputlower-byteenableand GNF2 t commandlatchenablegpmc_be0n_clehighto C(3)–0.2 C(3)+2.0 C(3)–5 C(3)+5 ns w(cleH-wenV) outputwriteenablegpmc_wenvalid GNF3 t Delaytime,outputdatagpmc_ad[15:0]validto D(4)–0.2 D(4)+2.0 D(4)–5 D(4)+5 ns w(wenV-dV) outputwriteenablegpmc_wenvalid GNF4 t Delaytime,outputwriteenablegpmc_wen E(5)–0.2 E(5)+5 E(5)–5 E(5)+5 ns w(wenIV-dIV) invalidtooutputdatagpmc_ad[15:0]invalid Delaytime,outputwriteenablegpmc_wen GNF5 t invalidtooutputlower-byteenableandcommand F(6)–0.2 F(6)+2.0 F(6)–5 F(6)+5 ns w(wenIV-cleIV) latchenablegpmc_be0n_cleinvalid Delaytime,outputwriteenablegpmc_wen GNF6 t invalidtooutputchipselectgpmc_csn[x](13) G(7)–0.2 G(7)+2.0 G(7)–5 G(7)+5 ns w(wenIV-csnIV) invalid Delaytime,outputaddressvalidandaddress GNF7 t latchenablegpmc_advn_alehightooutputwrite C(3)–0.2 C(3)+2.0 C(3)–5 C(3)+5 ns w(aleH-wenV) enablegpmc_wenvalid Delaytime,outputwriteenablegpmc_wen GNF8 t invalidtooutputaddressvalidandaddresslatch F(6)–0.2 F(6)+2.0 F(6)–5 F(6)+5 ns w(wenIV-aleIV) enablegpmc_advn_aleinvalid GNF9 t Cycletime,write H(8) H(8) ns c(wen) GNF10 t Delaytime,outputchipselectgpmc_csn[x](13) I(9)–0.2 I(9)+2.0 I(9)–5 I(9)+5 ns d(csnV-oenV) validtooutputenablegpmc_oenvalid GNF13 t Pulseduration,outputenablegpmc_oenvalid K(10) K(10) ns w(oenV) GNF14 t Cycletime,read L(11) L(11) ns c(oen) GNF15 tw(oenIV-csnIV) Douetlpauyttcimhiep,soeultepcuttgepnmabc_lecsgnp[mx]c(1_3o)einnvainlivdalidto M(12)–0.2 M(12)+2.0 M(12)–5 M(12)+5 ns (1) A=(WEOffTime–WEOnTime)×(TimeParaGranularity+1)×GPMC_FCLK(14) (2) B=((WEOnTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(WEExtraDelay–CSExtraDelay))×GPMC_FCLK(14) (3) C=((WEOnTime–ADVOnTime)×(TimeParaGranularity+1)+0.5×(WEExtraDelay–ADVExtraDelay))×GPMC_FCLK(14) (4) D=(WEOnTime×(TimeParaGranularity+1)+0.5×WEExtraDelay)×GPMC_FCLK(14) (5) E=((WrCycleTime–WEOffTime)×(TimeParaGranularity+1)–0.5×WEExtraDelay)×GPMC_FCLK(14) (6) F=((ADVWrOffTime–WEOffTime)×(TimeParaGranularity+1)+0.5×(ADVExtraDelay–WEExtraDelay))×GPMC_FCLK(14) (7) G=((CSWrOffTime–WEOffTime)×(TimeParaGranularity+1)+0.5×(CSExtraDelay–WEExtraDelay))×GPMC_FCLK(14) (8) H=WrCycleTime×(1+TimeParaGranularity)×GPMC_FCLK(14) (9) I=((OEOnTime–CSOnTime)×(TimeParaGranularity+1)+0.5×(OEExtraDelay–CSExtraDelay))×GPMC_FCLK(14) (10) K=(OEOffTime–OEOnTime)×(1+TimeParaGranularity)×GPMC_FCLK(14) (11) L=RdCycleTime×(1+TimeParaGranularity)×GPMC_FCLK(14) (12) M=((CSRdOffTime–OEOffTime)×(TimeParaGranularity+1)+0.5×(CSExtraDelay–OEExtraDelay))×GPMC_FCLK(14) (13) Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. (14) GPMC_FCLKisgeneral-purposememorycontrollerinternalfunctionalclockperiodinns. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 145 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com GPMC_FCLK GNF1 GNF6 gpmc_csn[x] GNF2 GNF5 gpmc_be0n_cle gpmc_advn_ale gpmc_oen GNF0 gpmc_wen GNF3 GNF4 gpmc_ad[15:0] Command (1) Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. Figure7-28.GPMCandNANDFlash—CommandLatchCycle GPMC_FCLK GNF1 GNF6 gpmc_csn[x] gpmc_be0n_cle GNF7 GNF8 gpmc_advn_ale gpmc_oen GNF9 GNF0 gpmc_wen GNF3 GNF4 gpmc_ad[15:0] Address (1) Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. Figure7-29.GPMCandNANDFlash—AddressLatchCycle 146 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 GPMC_FCLK GNF12 GNF10 GNF15 gpmc_csn[x] gpmc_be0n_cle gpmc_advn_ale GNF14 GNF13 gpmc_oen gpmc_ad[15:0] DATA gpmc_wait[x] (1) GNF12parameterillustratesamountoftimerequiredtointernallysampleinputdata.ItisexpressedinnumberofGPMCfunctional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functionalclockedge.GNF12valuemustbestoredinsideAccessTimeregisterbitsfield. (2) GPMC_FCLKisaninternalclock(GPMCfunctionalclock)notprovidedexternally. (3) Ingpmc_csn[x],xisequalto0,1,2,3,4,or5.Ingpmc_wait[x],xisequalto0or1. Figure7-30.GPMCandNANDFlash—DataReadCycle GPMC_FCLK GNF1 GNF6 gpmc_csn[x] gpmc_be0n_cle gpmc_advn_ale gpmc_oen GNF9 GNF0 gpmc_wen GNF3 GNF4 gpmc_ad[15:0] DATA (1) Ingpmc_csn[x],xisequalto0,1,2,3,4,or5. Figure7-31.GPMCandNANDFlash—DataWriteCycle Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 147 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface The device has a dedicated interface to mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM. It supports JEDEC standard compliant mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM devices with a 16-bit datapathtoexternalSDRAMmemory. For more details on the mDDR(LPDDR), DDR2, DDR3, and DDR3L memory interface, see the EMIF sectionofthe AM335xandAMIC110SitaraProcessorsTechnicalReferenceManual. 7.7.2.1 mDDR(LPDDR)RoutingGuidelines It is common to find industry references to mobile double data rate (mDDR) when discussing JEDEC defined low-power double-data rate (LPDDR) memory devices. The following guidelines use LPDDR when referencingJEDECdefinedlow-powerdouble-dataratememorydevices. 7.7.2.1.1 BoardDesigns TI only supports board designs that follow the guidelines outlined in this document. The switching characteristics and the timing diagram for the LPDDR memory interface are shown in Table 7-33 and Figure7-32. Table7-33.SwitchingCharacteristicsforLPDDRMemoryInterface NO. PARAMETER MIN MAX UNIT 1 tc(DDR_CK) Cycletime,DDR_CKandDDR_CKn 5 (1) ns t c(DDR_CKn) (1) TheJEDECJESD209BspecificationonlydefinesthemaximumclockperiodforLPDDR333andfasterspeedbinLPDDRmemory devices.Todeterminethemaximumclockperiod,seetherespectiveLPDDRmemorydatasheet. 1 DDR_CK DDR_CKn Figure7-32.LPDDRMemoryInterfaceClockTiming 7.7.2.1.2 LPDDRInterface Thissectionprovidesthetimingspecification for the LPDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the need for a complex timing closure process. For more information regarding the guidelines for using this LPDDR specification, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable LPDDR interfaceoperation. 7.7.2.1.2.1 LPDDRInterfaceSchematic Figure 7-33 shows the schematic connections for 16-bit interface on the AM335x device using one x16 LPDDR device. The AM335x LPDDR memory interface only supports 16-bit-wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and one loadconnectedto the CK and ADDR_CTRL net class signals. For more information related to net classes, seeSection7.7.2.1.2.8. 148 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 16-Bit LPDDR AM335x Device DDR_D0 DQ0 DDR_D7 DQ7 DDR_DQM0 LDM DDR_DQS0 LDQS DDR_DQSn0 NC(A) DDR_D8 DQ8 DDR_D15 DQ15 DDR_DQM1 UDM DDR_DQS1 UDQS DDR_DQSn1 NC(A) DDR_ODT NC DDR_BA0 T BA0 DDR_BA1 T BA1 DDR_BA2 NC DDR_A0 T A0 DDR_A15 T A15 DDR_CSn0 T CS DDR_CASn T CAS DDR_RASn T RAS DDR_WEn T WE DDR_CKE T CKE DDR_CK T CK DDR_CKn T CK DDR_VREF NC DDR_RESETn NC DDR_VTP 49.9Ω (±1%, 20 mW) A. Enableinternalweakpulldownonthesepins.Fordetails,seetheEMIFsectionofthe AM335x andAMIC110 Sitara ProcessorsTechnicalReferenceManual. B. Foralltheterminationrequirements,seeSection7.7.2.1.2.9. Figure7-33.16-BitLPDDRInterfaceUsingOne16-BitLPDDRDevice Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 149 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.1.2.2 CompatibleJEDECLPDDRDevices Table 7-34 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface. Generally,theLPDDRinterfaceiscompatiblewithx16LPDDR400speedgradeLPDDRdevices. Table7-34.CompatibleJEDECLPDDRDevices(PerInterface)(1) NO. PARAMETER MIN MAX UNIT 1 JEDECLPDDRdevicespeedgrade LPDDR400 2 JEDECLPDDRdevicebitwidth x16 x16 Bits 3 JEDECLPDDRdevicecount 1 Devices 4 JEDECLPDDRdeviceterminalcount 60 Terminals (1) IftheLPDDRinterfaceisoperatedwithaclockfrequencylessthan200MHz,lower-speedgradeLPDDRdevicesmaybeusedifthe minimumclockperiodspecifiedfortheLPDDRdeviceislessthanorequaltotheminimumclockperiodselectedfortheAM335x LPDDRinterface. 7.7.2.1.2.3 PCBStackup The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7- 35. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrityandelectromagneticinterferenceperformance,ortoreducethesizeofthePCBfootprint. Table7-35.MinimumPCBStackup(1) LAYER TYPE DESCRIPTION 1 Signal Topsignalrouting 2 Plane Ground 3 Plane SplitPowerPlane 4 Signal Bottomsignalrouting (1) Allsignalsthathavecriticalsignalintegrityrequirementsshouldberoutedfirstonlayer1.Itmaynotbepossibletorouteallofthese signalsonlayer1,thereforerequiringroutingofsomesignalsonlayer4.Whenthisisdone,thesignalroutesonlayer4mustnotcross splitsinthepowerplane. 150 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 CompletestackupspecificationsareprovidedinTable7-36. Table7-36.PCBStackupSpecifications(1) NO. PARAMETER MIN TYP MAX UNIT 1 PCBroutingandplanelayers 4 2 Signalroutinglayers 2 3 FullgroundlayersunderLPDDRroutingregion 1 4 NumberofgroundplanecutsallowedwithinLPDDRroutingregion 0 5 FullVDDS_DDRpowerreferencelayersunderLPDDRroutingregion 1 NumberoflayersbetweenLPDDRroutinglayerandreferenceground 6 0 plane 7 PCBroutingfeaturesize 4 mils 8 PCBtracewidth,w 4 mils 9 PCBBGAescapeviapadsize(2) 18 20 mils 10 PCBBGAescapeviaholesize(2) 10 mils 11 Single-endedimpedance,Zo(3) 50 75 Ω 12 Impedancecontrol(4)(5) Zo-5 Zo Zo+5 Ω (1) FortheLPDDRdeviceBGApadsize,seetheLPDDRdevicemanufacturerdocumentation. (2) A20-10viamaybeusedifenoughpowerroutingresourcesareavailable.An18-10viaallowsformoreflexiblepowerroutingtothe AM335xdevice. (3) Zoisthenominalsingled-endedimpedanceselectedforthePCB. (4) ThisparameterspecifiestheACcharacteristicimpedancetoleranceforeachsegmentofaPCBsignaltracerelativetothechosenZo definedbythesingle-endedimpedanceparameter. (5) Tighterimpedancecontrolisrequiredtoensureflighttimeskewisminimal. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 151 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.1.2.4 Placement Figure 7-34 shows the required placement for the LPDDR devices. The dimensions for this figure are defined in Table 7-37. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory LPDDR systems, the second LPDDR device is omitted from the placement. X A1 Y OFFSET Y LDPeDviDcRe DDRrface Pe Y LInt OFFSET AM335x A1 Recommended LPDDR Device Orientation Figure7-34.AM335xDeviceandLPDDRDevicePlacement Table7-37.PlacementSpecifications(1) NO. PARAMETER MIN MAX UNIT 1 X(2)(3) 1750 mils 2 Y(2)(3) 1280 mils 3 YOffset(2)(3)(4) 650 mils 4 Clearancefromnon-LPDDRsignaltoLPDDRkeepoutregion(5)(6) 4 w (1) LPDDRkeepoutregiontoencompassentireLPDDRroutingarea. (2) Fordimensiondefinitions,seeFigure7-34. (3) MeasurementsfromcenteroftheAM335xdevicetocenterofLPDDRdevice. (4) Forsingle-memorysystems,TIrecommendsthatYoffsetbeassmallaspossible. (5) wisdefinedasthesignaltracewidth. (6) Non-LPDDRsignalsallowedwithinLPDDRkeepoutregionprovidedtheyareseparatedfromLPDDRroutinglayersbyagroundplane. 152 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.1.2.5 LPDDRKeepoutRegion The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keepout region is defined for this purpose and is shown in Figure 7-35. This region should encompass all LPDDR circuitry and the region size varies with component placement and LPDDR routing. Additional clearances required for the keepout region are shown in Table 7-37. Non-LPDDR signals must not be routed on the same signal layer as LPDDR signals within the LPDDR keepout region. Non-LPDDR signals may be routed in the region provided they are routed on layers separated from LPDDR signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region.Inaddition,theVDDS_DDRpowerplaneshouldcovertheentirekeepoutregion. A1 Rce LPDDR Da Device Drf Pe Lnt I A1 Figure7-35.LPDDRKeepoutRegion 7.7.2.1.2.6 BulkBypassCapacitors Bulk bypass capacitors are required for moderate speed bypassing of the LPDDR and other circuitry. Table 7-38 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x LPDDR interface and LPDDR devices. Additionalbulkbypasscapacitancemaybeneededforothercircuitry. Table7-38.BulkBypassCapacitors(1) NO. PARAMETER MIN MAX UNIT 1 AM335xVDDS_DDRbulkbypasscapacitorcount 1 Devices 2 AM335xVDDS_DDRbulkbypasstotalcapacitance 10 μF 3 LPDDR#1bulkbypasscapacitorcount 1 Devices 4 LPDDR#1bulkbypasstotalcapacitance 10 μF 5 LPDDR#2bulkbypasscapacitorcount(2) 1 Devices 6 LPDDR#2bulkbypasstotalcapacitance(2) 10 μF (1) Thesedevicesshouldbeplacednearthedevicetheyarebypassing,butpreferenceshouldbegiventotheplacementofthehigh-speed (HS)bypasscapacitors. (2) OnlyusedwhentwoLPDDRdevicesareused. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 153 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.1.2.7 High-SpeedBypassCapacitors High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device LPDDR power, and the AM335x device LPDDR ground connections. Table 7-39 contains the specification fortheHSbypasscapacitorsaswellasforthepowerconnectionsonthePCB. Table7-39.High-SpeedBypassCapacitors NO. PARAMETER MIN MAX UNIT 1 HSbypasscapacitorpackagesize(1) 0402 10mils 2 DistancefromHSbypasscapacitortodevicebeingbypassed 250 mils 3 NumberofconnectionviasforeachHSbypasscapacitor(2) 2 Vias 4 Tracelengthfrombypasscapacitorcontacttoconnectionvia 30 mils 5 NumberofconnectionviasforeachAM335xVDDS_DDRandVSSterminal 1 Vias 6 TracelengthfromAM335xVDDS_DDRandVSSterminaltoconnectionvia 35 mils 7 NumberofconnectionviasforeachLPDDRdevicepowerandgroundterminal 1 Vias 8 TracelengthfromLPDDRdevicepowerandgroundterminaltoconnectionvia 35 mils 9 AM335xVDDS_DDRHSbypasscapacitorcount(3) 10 Devices 10 AM335xVDDS_DDRHSbypasscapacitortotalcapacitance 0.6 μF 11 LPDDRdeviceHSbypasscapacitorcount(3)(4) 8 Devices 12 LPDDRdeviceHSbypasscapacitortotalcapacitance(4) 0.4 μF (1) LxW,10-milunits;forexample,a0402isa40x20-milsurface-mountcapacitor. (2) AnadditionalHSbypasscapacitorcansharetheconnectionviasonlyifitismountedontheoppositesideoftheboard. (3) Thesedevicesshouldbeplacedascloseaspossibletothedevicebeingbypassed. (4) PerLPDDRdevice. 7.7.2.1.2.8 NetClasses Table 7-40 lists the clock net classes for the LPDDR interface. Table 7-41 lists the signal net classes, and associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the terminationandroutingrulesthatfollow. Table7-40.ClockNetClassDefinitions CLOCKNETCLASS AM335xPINNAMES CK DDR_CKandDDR_CKn DQS0 DDR_DQS0 DQS1 DDR_DQS1 Table7-41.SignalNetClassDefinitions ASSOCIATEDCLOCK SIGNALNETCLASS AM335xPINNAMES NETCLASS DDR_BA[1:0],DDR_A[15:0],DDR_CSn0,DDR_CASn,DDR_RASn, ADDR_CTRL CK DDR_WEn,DDR_CKE DQ0 DQS0 DDR_D[7:0],DDR_DQM0 DQ1 DQS1 DDR_D[15:8],DDR_DQM1 154 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.1.2.9 LPDDRSignalTermination There is no specific need for adding terminations on the LPDDR interface. However, system designers may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis. PlacementofserialterminationsforADDR_CTRL net class signals should be close to the AM335x device. Table7-42showsthespecificationsfortheserialterminatorsinsuchcases. Table7-42.LPDDRSignalTerminations NO. PARAMETER MIN TYP MAX UNIT 1 CKnetclass(1) 0 22 Zo(2) Ω 2 ADDR_CTRLnetclass(1)(3)(4) 0 22 Zo(2) Ω 3 DQS0,DQS1,DQ0,andDQ1netclasses 0 22 Zo(2) Ω (1) Onlyseriesterminationispermitted. (2) ZoistheLPDDRPCBtracecharacteristicimpedance. (3) SeriesterminationvalueslargerthantypicalonlyrecommendedtoaddressEMIissues. (4) Seriesterminationvaluesshouldbeuniformacrossnetclass. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 155 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.1.3 LPDDRCKandADDR_CTRLRouting Figure 7-36 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length AisthemajorityofthetotallengthofsignalpathABandAC. A1 B Rce A DDrfa Pe Lnt C I AM335x A1 Figure7-36.CKandADDR_CTRLRoutingandTopology Table7-43.CKandADDR_CTRLRoutingSpecification(1)(2) NO. PARAMETER MIN TYP MAX UNIT 1 Center-to-centerCKspacing 2w 2 CKdifferentialpairskewlengthmismatch(2)(3) 25 mils 3 CKB-to-CKCskewlengthmismatch 25 mils 4 Center-to-centerCKtootherLPDDRtracespacing(4) 4w 5 CKandADDR_CTRLnominaltracelength(5) CACLM-50 CACLM CACLM+50 mils 6 ADDR_CTRL-to-CKskewlengthmismatch 100 mils 7 ADDR_CTRL-to-ADDR_CTRLskewlengthmismatch 100 mils 8 Center-to-centerADDR_CTRLtootherLPDDRtracespacing(4) 4w 9 Center-to-centerADDR_CTRLtootherADDR_CTRLtracespacing(4) 3w 10 ADDR_CTRLA-to-BandADDR_CTRLA-to-Cskewlengthmismatch(2) 100 mils 11 ADDR_CTRLB-to-Cskewlengthmismatch 100 mils (1) CKrepresentstheclocknetclass,andADDR_CTRLrepresentstheaddressandcontrolsignalnetclass. (2) Seriesterminator,ifused,shouldbelocatedclosesttotheAM335xdevice. (3) DifferentialimpedanceshouldbeZox2,whereZoisthesingle-endedimpedancedefinedinTable7-36. (4) Center-to-centerspacingisallowedtofalltominimum(w)forupto500milsofroutedlengthtoaccommodateBGAescapeandrouting congestion. (5) CACLMisthelongestManhattandistanceoftheCKandADDR_CTRLnetclasses. 156 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Figure 7-37 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to point.Skewmatchingacrossbytesisnotneedednorrecommended. A1 DQ[0] DDRrface Pe DQ[1] Lnt I AM335x Figure7-37.DQS[x]andDQ[x]RoutingandTopology Table7-44.DQS[x]andDQ[x]RoutingSpecification(1) NO. PARAMETER MIN TYP MAX UNIT 1 Center-to-centerDQS[x]spacing 2w 2 Center-to-centerDDR_DQS[x]tootherLPDDRtracespacing(2) 4w 3 DQS[x]andDQ[x]nominaltracelength(3) DQLM-50 DQLM DQLM+50 mils 4 DQ[x]-to-DQS[x]skewlengthmismatch(3) 100 mils 5 DQ[x]-to-DQ[x]skewlengthmismatch(3) 100 mils 6 Center-to-centerDQ[x]tootherLPDDRtracespacing(2)(4) 4w 7 Center-to-centerDQ[x]tootherDQ[x]tracespacing(2)(5) 3w (1) DQS[x]representstheDQS0andDQS1clocknetclasses,andDQ[x]representstheDQ0andDQ1signalnetclasses. (2) Center-to-centerspacingisallowedtofalltominimum(w)forupto500milsofroutedlengthtoaccommodateBGAescapeandrouting congestion. (3) Thereisnorequirementforskewmatchingbetweendatabytes;thatis,fromnetclassesDQS0andDQ0tonetclassesDQS1andDQ1. (4) SignalsfromoneDQnetclassshouldbeconsideredotherLPDDRtracestoanotherDQnetclass. (5) DQLMisthelongestManhattandistanceofeachoftheDQS[x]andDQ[x]netclasses. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 157 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.2 DDR2RoutingGuidelines 7.7.2.2.1 BoardDesigns TI only supports board designs that follow the guidelines outlined in this document. Table 7-45 and Figure7-38showtheswitchingcharacteristicsandtimingdiagramfortheDDR2memoryinterface. Table7-45.SwitchingCharacteristicsforDDR2MemoryInterface NO. PARAMETER MIN MAX UNIT 1 tc(DDR_CK) Cycletime,DDR_CKandDDR_CKn 3.75 8(1) ns t c(DDR_CKn) (1) TheJEDECJESD79-2Fspecificationdefinesthemaximumclockperiodof8nsforallstandard-speedbinDDR2memorydevices. Therefore,allstandard-speedbinDDR2memorydevicesarerequiredtooperateat125MHz. 1 DDR_CK DDR_CKn Figure7-38.DDR2MemoryInterfaceClockTiming 7.7.2.2.2 DDR2Interface This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process. For more information regarding the guidelines for using this DDR2 specification,see UnderstandingTI’s PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedenceoverthegenericguidelinesandmustbeadheredtoforareliableDDR2interfaceoperation. 7.7.2.2.2.1 DDR2InterfaceSchematic Figure 7-39 shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR2 device and Figure 7-40 shows the schematic connections for 16-bit interface on the AM335x device using two x8 DDR2 devices. The AM335x DDR2 memory interface only supports 16-bit-wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads connected to the CK and ADDR_CTRL net class signals. For more information relatedtonetclasses,seeSection7.7.2.2.2.8. 158 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 16-Bit DDR2 AM335x Device DDR_D0 DQ0 DDR_D7 DQ7 DDR_DQM0 LDM DDR_DQS0 LDQS DDR_DQSn0 LDQS DDR_D8 DQ8 DDR_D15 DQ15 DDR_DQM1 UDM DDR_DQS1 UDQS DDR_DQSn1 UDQS DDR_ODT T ODT DDR_BA0 T BA0 DDR_BA1 T BA1 DDR_BA2 T BA2 DDR_A0 T A0 DDR_A15 T A15 DDR_CSn0 T CS DDR_CASn T CAS (A) DDR_RASn T RAS VDDS_DDR DDR_WEn T WE DDR_CKE T CKE DDR_CK T CK DDR_CKn T CK 0.1µF 1 kΩ1% DDR_VREF VREF DDR_VREF (B) (B) 0.1µF 0.1µF 0.1µF 1 kΩ1% DDR_RESETn NC DDR_VTP 49.9Ω (±1%, 20 mW) Copyright © 2016,Texas Instruments Incorporated A. VDDS_DDRisthepowersupplyfortheDDR2memoriesandtheAM335xDDR2interface. B. OneofthesecapacitorscanbeeliminatedifthedivideranditscapacitorsareplacednearaDDR_VREFpin. C. Foralltheterminationrequirements,seeSection7.7.2.2.2.9. Figure7-39.16-BitDDR2InterfaceUsingOne16-BitDDR2Device Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 159 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com AM335x 8-Bit DDR2 Devices DDR_D0 DQ0 DDR_D7 DQ7 DDR_DQM0 DM DDR_DQS0 DQS DDR_DQSn0 DQS DDR_D8 DQ0 DDR_D15 DQ7 DDR_DQM1 DM DDR_DQS1 DQS DDR_DQSn1 DQS DDR_ODT T ODT ODT DDR_BA0 T BA0 BA0 DDR_BA1 T BA1 BA1 DDR_BA2 T BA2 BA2 DDR_A0 T A0 A0 DDR_A15 T A15 A15 DDR_CSn0 T CS CS DDR_CASn T CAS CAS (A) DDR_RASn T RAS RAS VDDS_DDR DDR_WEn T WE WE DDR_CKE T CKE CKE DDR_CK T CK CK DDR_CKn T CK CK 0.1µF 1 kΩ1% DDR_VREF VREF VREF DDR_VREF (B) (B) (B) 0.1µF 0.1µF 0.1µF 0.1µF 1 kΩ1% DDR_RESETn NC DDR_VTP 49.9Ω (±1%, 20 mW) Copyright © 2016,Texas Instruments Incorporated A. VDDS_DDRisthepowersupplyfortheDDR2memoriesandtheAM335xDDR2interface. B. OneofthesecapacitorscanbeeliminatedifthedivideranditscapacitorsareplacednearaDDR_VREFpin. C. Foralltheterminationrequirements,seeSection7.7.2.2.2.9. Figure7-40.16-BitDDR2InterfaceUsingTwo8-BitDDR2Devices 160 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.2.2.2 CompatibleJEDECDDR2Devices Table 7-46 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface. Generally,theDDR2interfaceiscompatiblewithx16orx8DDR2-533speedgradeDDR2devices. Table7-46.CompatibleJEDECDDR2Devices(PerInterface)(1) NO. PARAMETER MIN MAX UNIT 1 JEDECDDR2devicespeedgrade(2) DDR2-533 2 JEDECDDR2devicebitwidth x8 x16 bits 3 JEDECDDR2devicecount 1 2 devices 4 JEDECDDR2deviceterminalcount(3) 60 84 terminals (1) IftheDDR2interfaceisoperatedwithaclockfrequencylessthan266MHz,lower-speedgradeDDR2devicesmaybeusedifthe minimumclockperiodspecifiedfortheDDR2deviceislessthanorequaltotheminimumclockperiodselectedfortheAM335xDDR2 interface. (2) HigherDDR2speedgradesaresupportedduetoinherentJEDECDDR2backwardcompatibility. (3) 92-terminaldevicesarealsosupportedforlegacyreasons.Newdesignswillmigrateto84-terminalDDR2devices.Electrically,the92- and84-terminalDDR2devicesarethesame. 7.7.2.2.2.3 PCBStackup The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7- 47. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrityandelectromagneticinterferenceperformance,ortoreducethesizeofthePCBfootprint. Table7-47.MinimumPCBStackup(1) LAYER TYPE DESCRIPTION 1 Signal Topsignalrouting 2 Plane Ground 3 Plane Splitpowerplane 4 Signal Bottomsignalrouting (1) Allsignalsthathavecriticalsignalintegrityrequirementsshouldberoutedfirstonlayer1.Itmaynotbepossibletorouteallofthese signalsonlayer1,thereforerequiringroutingofsomesignalsonlayer4.Whenthisisdone,thesignalroutesonlayer4mustnotcross splitsinthepowerplane. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 161 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com CompletestackupspecificationsareprovidedinTable7-48. Table7-48.PCBStackupSpecifications(1) NO. PARAMETER MIN TYP MAX UNIT 1 PCBroutingandplanelayers 4 2 Signalroutinglayers 2 3 FullgroundlayersunderDDR2routingregion 1 4 NumberofgroundplanecutsallowedwithinDDR2routingregion 0 5 FullVDDS_DDRpowerreferencelayersunderDDR2routingregion 1 6 NumberoflayersbetweenDDR2routinglayerandreferencegroundplane 0 7 PCBroutingfeaturesize 4 mils 8 PCBtracewidth,w 4 mils 9 PCBBGAescapeviapadsize(2) 18 20 mils 10 PCBBGAescapeviaholesize(2) 10 mils 11 Single-endedimpedance,Zo(3) 50 75 Ω 12 Impedancecontrol(4)(5) Zo-5 Zo Zo+5 Ω (1) FortheDDR2deviceBGApadsize,seetheDDR2devicemanufacturerdocumentation. (2) A20-10viamaybeusedifenoughpowerroutingresourcesareavailable.An18-10viaallowsformoreflexiblepowerroutingtothe AM335xdevice. (3) Zoisthenominalsingled-endedimpedanceselectedforthePCB. (4) ThisparameterspecifiestheACcharacteristicimpedancetoleranceforeachsegmentofaPCBsignaltracerelativetothechosenZo definedbythesingle-endedimpedanceparameter. (5) Tighterimpedancecontrolisrequiredtoensureflighttimeskewisminimal. 162 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.2.2.4 Placement Figure 7-41 shows the required placement for the DDR2 devices. The dimensions for this figure are defined in Table 7-49. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement. X A1 Y OFFSET e Y DDeDvRic2e DR2rfac Y DInte OFFSET AM335x A1 Recommended DDR2 Device Orientation Figure7-41.AM335xDeviceandDDR2DevicePlacement Table7-49.PlacementSpecifications(1) NO. PARAMETER MIN MAX UNIT 1 X(2)(3) 1750 mils 2 Y(2)(3) 1280 mils 3 YOffset(2)(3)(4) 650 mils 4 Clearancefromnon-DDR2signaltoDDR2keepoutregion(5)(6) 4 w (1) DDR2keepoutregiontoencompassentireDDR2routingarea. (2) Fordimensiondefinitions,seeFigure7-41. (3) MeasurementsfromcenteroftheAM335xdevicetocenteroftheDDR2device. (4) Forsingle-memorysystems,itisrecommendedthatYoffsetbeassmallaspossible. (5) wisdefinedasthesignaltracewidth. (6) Non-DDR2signalsallowedwithinDDR2keepoutregionprovidedtheyareseparatedfromDDR2routinglayersbyagroundplane. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 163 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.2.2.5 DDR2KeepoutRegion The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keepout region is defined for this purpose and is shown in Figure 7-42. This region should encompass all DDR2 circuitry and the region size varies with component placement and DDR2 routing. Additional clearances required for the keepout region are shown in Table 7-49. Non-DDR2 signals must not be routed on the same signal layer as DDR2 signals within the DDR2 keepout region. Non-DDR2 signals may be routed in the region provided they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region.Inaddition,theVDDS_DDRpowerplaneshouldcovertheentirekeepoutregion. A1 e DDR2 R2ac Device Drf Dnte I A1 Figure7-42.DDR2KeepoutRegion 7.7.2.2.2.6 BulkBypassCapacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. Table 7-50 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x DDR2 interface and DDR2 devices. Additional bulkbypasscapacitancemaybeneededforothercircuitry. Table7-50.BulkBypassCapacitors(1) NO. PARAMETER MIN MAX UNIT 1 AM335xVDDS_DDRbulkbypasscapacitorcount 1 devices 2 AM335xVDDS_DDRbulkbypasstotalcapacitance 10 μF 3 DDR2number1bulkbypasscapacitorcount 1 devices 4 DDR2number1bulkbypasstotalcapacitance 10 μF 5 DDR2number2bulkbypasscapacitorcount(2) 1 devices 6 DDR2number2bulkbypasstotalcapacitance(2) 10 μF (1) Thesedevicesshouldbeplacednearthedevicetheyarebypassing,butpreferenceshouldbegiventotheplacementofthehigh-speed (HS)bypasscapacitors. (2) OnlyusedwhentwoDDR2devicesareused. 164 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.2.2.7 High-Speed(HS)BypassCapacitors HS bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device DDR2 power, and the AM335x device DDR2 ground connections. Table 7-51 contains the specification for the HS bypasscapacitorsaswellasforthepowerconnectionsonthePCB. Table7-51.HSBypassCapacitors NO. PARAMETER MIN MAX UNIT 1 HSbypasscapacitorpackagesize(1) 0402 10mils 2 DistancefromHSbypasscapacitortodevicebeingbypassed 250 mils 3 NumberofconnectionviasforeachHSbypasscapacitor(2) 2 vias 4 Tracelengthfrombypasscapacitorcontacttoconnectionvia 30 mils 5 NumberofconnectionviasforeachAM335xVDDS_DDRandVSSterminal 1 vias 6 TracelengthfromAM335xVDDS_DDRandVSSterminaltoconnectionvia 35 mils 7 NumberofconnectionviasforeachDDR2devicepowerandgroundterminal 1 vias 8 TracelengthfromDDR2devicepowerandgroundterminaltoconnectionvia 35 mils 9 AM335xVDDS_DDRHSbypasscapacitorcount(3) 10 devices 10 AM335xVDDS_DDRHSbypasscapacitortotalcapacitance 0.6 μF 11 DDR2deviceHSbypasscapacitorcount(3)(4) 8 devices 12 DDR2deviceHSbypasscapacitortotalcapacitance(4) 0.4 μF (1) LxW,10-milunits;forexample,a0402isa40x20-milsurface-mountcapacitor. (2) AnadditionalHSbypasscapacitorcansharetheconnectionviasonlyifitismountedontheoppositesideoftheboard. (3) Thesedevicesshouldbeplacedascloseaspossibletothedevicebeingbypassed. (4) PerDDR2device. 7.7.2.2.2.8 NetClasses Table 7-52 lists the clock net classes for the DDR2 interface. Table 7-53 lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the terminationandroutingrulesthatfollow. Table7-52.ClockNetClassDefinitions CLOCKNETCLASS AM335xPINNAMES CK DDR_CKandDDR_CKn DQS0 DDR_DQS0andDDR_DQSn0 DQS1 DDR_DQS1andDDR_DQSn1 Table7-53.SignalNetClassDefinitions ASSOCIATEDCLOCK SIGNALNETCLASS AM335xPINNAMES NETCLASS DDR_BA[2:0],DDR_A[15:0],DDR_CSn0,DDR_CASn,DDR_RASn, ADDR_CTRL CK DDR_WEn,DDR_CKE,DDR_ODT DQ0 DQS0 DDR_D[7:0],DDR_DQM0 DQ1 DQS1 DDR_D[15:8],DDR_DQM1 Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 165 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.2.2.9 DDR2SignalTermination Signal terminations are required on the CK and ADDR_CTRL net class signals. Serial terminations should be used on the CK and ADDR_CTRL lines and is the preferred termination scheme. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. They should be enabled to ensure signal integrity. Table 7-54 shows the specifications for the series terminators. Placement of serial terminationsforADDR_CTRLnetclasssignalsshouldbeclosetotheAM335xdevice. Table7-54.DDR2SignalTerminations NO. PARAMETER MIN TYP MAX UNIT 1 CKnetclass(1) 0 10 Ω 2 ADDR_CTRLnetclass(1)(2)(3) 0 22 Zo(4) Ω 3 DQS0,DQS1,DQ0,andDQ1netclasses(5) N/A N/A Ω (1) Onlyseriesterminationispermitted. (2) SeriesterminationvalueslargerthantypicalonlyrecommendedtoaddressEMIissues. (3) Seriesterminationvaluesshouldbeuniformacrossnetclass. (4) ZoistheDDR2PCBtracecharacteristicimpedance. (5) NoexternalterminationresistorsareallowedandODTmustbeusedforthesenetclasses. If the DDR2 interface is operated at a lower frequency (<200-MHz clock rate), on-device terminations are not specifically required for the DQS[x] and DQ[x] net class signals and serial terminations for the CK and ADDR_CTRL net class signals are not mandatory. System designers may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis. Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device. Table 7-55 shows the specificationsfortheserialterminatorsinsuchcases. Table7-55.Lower-FrequencyDDR2SignalTerminations NO. PARAMETER MIN TYP MAX UNIT 1 CKnetclass(1) 0 22 Zo(2) Ω 2 ADDR_CTRLnetclass(1)(3)(4) 0 22 Zo(2) Ω 3 DQS0,DQS1,DQ0,andDQ1netclasses 0 22 Zo(2) Ω (1) Onlyseriesterminationispermitted. (2) ZoistheDDR2PCBtracecharacteristicimpedance. (3) SeriesterminationvalueslargerthantypicalonlyrecommendedtoaddressEMIissues. (4) Seriesterminationvaluesshouldbeuniformacrossnetclass. 166 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.2.2.10 DDR_VREFRouting DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x device. DDR_VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 7-39 and Figure 7-40. TI does not recommend other methods of creatingDDR_VREF.Figure7-43showsthelayoutguidelinesforDDR_VREF. DDR_VREF Bypass Capacitor DDR2 Device A1 DDR_VREF Nominal Minimum Trace Width is 20 Mils AM335x A1 Neck down to minimum in BGAescape regions is acceptable. Narrowing to accommodate via congestion for short distances is also acceptable. Best performance is obtained if the width of DDR_VREF is maximized. Figure7-43.DDR_VREFRoutingandTopology Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 167 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.2.3 DDR2CKandADDR_CTRLRouting Figure 7-44 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length AisthemajorityofthetotallengthofsignalpathABandAC. A1 B T 2ce A DRrfa Dnte C I AM335x A1 Figure7-44.CKandADDR_CTRLRoutingandTopology Table7-56.CKandADDR_CTRLRoutingSpecification(1)(2) NO. PARAMETER MIN TYP MAX UNIT 1 Center-to-centerCKspacing 2w 2 CKdifferentialpairskewlengthmismatch(2)(3) 25 mils 3 CKB-to-CKCskewlengthmismatch 25 mils 4 Center-to-centerCKtootherDDR2tracespacing(4) 4w 5 CKandADDR_CTRLnominaltracelength(5) CACLM-50 CACLM CACLM+50 mils 6 ADDR_CTRL-to-CKskewlengthmismatch 100 mils 7 ADDR_CTRL-to-ADDR_CTRLskewlengthmismatch 100 mils 8 Center-to-centerADDR_CTRLtootherDDR2tracespacing(4) 4w 9 Center-to-centerADDR_CTRLtootherADDR_CTRLtracespacing(4) 3w 10 ADDR_CTRLA-to-BandADDR_CTRLA-to-Cskewlengthmismatch(2) 100 mils 11 ADDR_CTRLB-to-Cskewlengthmismatch 100 mils (1) CKrepresentstheclocknetclass,andADDR_CTRLrepresentstheaddressandcontrolsignalnetclass. (2) Seriesterminator,ifused,shouldbelocatedclosesttotheAM335xdevice. (3) DifferentialimpedanceshouldbeZox2,whereZoisthesingle-endedimpedancedefinedinTable7-48. (4) Center-to-centerspacingisallowedtofalltominimum(w)forupto500milsofroutedlengthtoaccommodateBGAescapeandrouting congestion. (5) CACLMisthelongestManhattandistanceoftheCKandADDR_CTRLnetclasses. Figure 7-45 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to point.Skewmatchingacrossbytesisnotneedednorrecommended. e A1 DQ[0] DR2rfac DQ[1] Dnte I AM335x Figure7-45.DQS[x]andDQ[x]RoutingandTopology 168 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-57.DQS[x]andDQ[x]RoutingSpecification(1) NO. PARAMETER MIN TYP MAX UNIT 1 Center-to-centerDQS[x]spacing 2w 2 DQS[x]differentialpairskewlengthmismatch(2) 25 mils 3 Center-to-centerDDR_DQS[x]tootherDDR2tracespacing(3) 4w 4 DQS[x]andDQ[x]nominaltracelength(4) DQLM-50 DQLM DQLM+50 mils 5 DQ[x]-to-DQS[x]skewlengthmismatch(4) 100 mils 6 DQ[x]-to-DQ[x]skewlengthmismatch(4) 100 mils 7 Center-to-centerDQ[x]tootherDDR2tracespacing(3)(5) 4w 8 Center-to-centerDQ[x]tootherDQ[x]tracespacing(3)(6) 3w (1) DQS[x]representstheDQS0andDQS1clocknetclasses,andDQ[x]representstheDQ0andDQ1signalnetclasses. (2) DifferentialimpedanceshouldbeZox2,whereZoisthesingle-endedimpedancedefinedinTable7-48. (3) Center-to-centerspacingisallowedtofalltominimum(w)forupto500milsofroutedlengthtoaccommodateBGAescapeandrouting congestion. (4) Thereisnorequirementforskewmatchingbetweendatabytes;thatis,fromnetclassesDQS0andDQ0tonetclassesDQS1andDQ1. (5) SignalsfromoneDQnetclassshouldbeconsideredotherDDR2tracestoanotherDQnetclass. (6) DQLMisthelongestManhattandistanceofeachoftheDQS[x]andDQ[x]netclasses. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 169 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.3 DDR3andDDR3LRoutingGuidelines NOTE All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise noted. 7.7.2.3.1 BoardDesigns TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 7-58 and Figure7-46. Table7-58.SwitchingCharacteristicsforDDR3MemoryInterface NO. PARAMETER MIN MAX UNIT 1 tc(DDR_CK) Cycletime,DDR_CKandDDR_CKn 2.5 3.3(1) ns t c(DDR_CKn) (1) TheJEDECJESD79-3FStandarddefinesthemaximumclockperiodof3.3nsforallstandard-speedbinDDR3andDDR3Lmemory devices.Therefore,allstandard-speedbinDDR3andDDR3Lmemorydevicesarerequiredtooperateat303MHz. 1 DDR_CK DDR_CKn Figure7-46.DDR3MemoryInterfaceClockTiming 7.7.2.3.1.1 DDR3versusDDR2 This specification only covers AM335x PCB designs that use DDR3 memory. Designs using DDR2 memory should use the DDR2 routing guidleines described in Section 7.7.2.2. While similar, the two memory systems have different requirements. It is currently not possible to design one PCB that meets therequirementsofbothDDR2andDDR3. 7.7.2.3.2 DDR3DeviceCombinations Because there are several possible combinations of device counts and single-side or dual-side mounting, Table7-59summarizesthesupporteddeviceconfigurations. Table7-59.SupportedDDR3DeviceCombinations NUMBEROFDDR3DEVICES DDR3DEVICEWIDTH(BITS) MIRRORED? DDR3EMIFWIDTH(BITS) 1 16 N 16 2 8 Y(1) 16 (1) TwoDDR3devicesaremirroredwhenonedeviceisplacedonthetopoftheboardandtheseconddeviceisplacedonthebottomof theboard. 7.7.2.3.3 DDR3Interface This section provides the timing specification for the DDR3 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR3 memory system without the need for a complex timing closure process. For more information regarding the guidelines for using this DDR3 specification, see Understanding TI's PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedenceoverthegenericguidelinesandmustbeadheredtoforareliableDDR3interfaceoperation. 170 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.3.3.1 DDR3InterfaceSchematic The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 7-47 shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR3 device and Figure 7-49 shows the schematic connections for 16-bit interface on the AM335x device using two x8 DDR3 devices. The AM335x DDR3 memory interface only supports 16-bit wide mode of operation. The AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads connected to the CK and ADDR_CTRL net class signals. For more information related to net classes,seeSection7.7.2.3.3.8. 16-Bit DDR3 16-Bit DDR3 Interface Device DDR_D15 DQU7 8 DDR_D8 DQU0 DDR_DQM1 DMU DDR_DQS1 DQSU DDR_DQSn1 DQSU# DDR_D7 DQL7 8 DDR_D0 DQL0 DDR_DQM0 DML DDR_DQS0 DQSL DDR_DQSn0 DQSL# Zo 0.1µF DDR_CK CK VDDS_DDR DDR_CKn CK# Zo DDR_ODT ODT DDR_CSn0 CS# DDR_BA0 BA0 DDR_BA1 BA1 DDR_VTT DDR_BA2 BA2 DDR_A0 A0 Zo 15 DDR_A15 A15 Zo DDR_CASn CAS# DDR_RASn RAS# DDR_WEn WE# DDR_CKE CKE DDR_RESETn RESET# DDR_VREF ZQ ZQ VREFDQ DDR_VREF VREFCA 0.1µF 0.1µF 0.1µF DDR_VTP 49.9Ω (±1%, 20 mW) Zo Termination is required. See terminator comments. ZQ Value determined according to the DDR3 memory device data sheet. Copyright © 2016,Texas Instruments Incorporated Figure7-47.16-BitDDR3InterfaceUsingOne16-BitDDR3DevicewithV Termination TT Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 171 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 16-Bit DDR3 16-Bit DDR3 Interface Device DDR_D15 DQU7 8 DDR_D8 DQU0 DDR_DQM1 DMU DDR_DQS1 DQSU DDR_DQSn1 DQSU# DDR_D7 DQL7 8 DDR_D0 DQL0 DDR_DQM0 DML DDR_DQS0 DQSL DDR_DQSn0 DQSL# DDR_CK CK DDR_CKn CK# DDR_ODT ODT DDR_CSn0 CS# DDR_BA0 BA0 DDR_BA1 BA1 DDR_BA2 BA2 DDR_A0 A0 15 DDR_A15 A15 DDR_CASn CAS# (A) VDDS_DDR DDR_RASn RAS# DDR_WEn WE# DDR_CKE CKE DDR_RESETn RESET# ZQ 0.1µF 1 kΩ1% ZQ VREFDQ DDR_VREF VREFCA DDR_VREF 0.1µF 0.1µF 0.1µF 1 kΩ1% DDR_VTP 49.9Ω (±1%, 20 mW) ZQ Value determined according to the DDR3 memory device data sheet. Copyright © 2016,Texas Instruments Incorporated A. VDDS_DDRisthepowersupplyfortheDDR3memoriesandtheAM335xDDR3interface. Figure7-48.16-BitDDR3InterfaceUsingOne16-BitDDR3DevicewithoutV Termination TT 172 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 16-Bit DDR3 8-Bit DDR3 Interface Devices DDR_D15 DQ7 8 DDR_D8 DQ0 DDR_DQM1 DM/TDQS NC TDQS# DDR_DQS1 DQS DDR_DQSn1 DQS# DDR_D7 DQ7 8 DDR_D0 DQ0 DDR_DQM0 DM/TDQS NC TDQS# DDR_DQS0 DQS DDR_DQSn0 DQS# Zo 0.1µF DDR_CK CK CK VDDS_DDR DDR_CKn CK# CK# Zo DDR_ODT ODT ODT DDR_CSn0 CS# CS# DDR_BA0 BA0 BA0 DDR_BA1 BA1 BA1 DDR_VTT DDR_BA2 BA2 BA2 DDR_A0 A0 A0 Zo 15 DDR_A15 A15 A15 Zo DDR_CASn CAS# CAS# DDR_RASn RAS# RAS# DDR_WEn WE# WE# DDR_CKE CKE CKE DDR_RESETn RESET# RESET# DDR_VREF ZQ ZQ ZQ VREFDQ VREFDQ ZQ DDR_VREF VREFCA VREFCA 0.1µF 0.1µF 0.1µF 0.1µF DDR_VTP 49.9Ω (±1%, 20 mW) Zo Termination is required. See terminator comments. ZQ Value determined according to the DDR3 memory device data sheet. Copyright © 2016,Texas Instruments Incorporated Figure7-49.16-BitDDR3InterfaceUsingTwo8-BitDDR3Devices Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 173 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.3.3.2 CompatibleJEDECDDR3Devices Table7-60showstheparametersoftheJEDECDDR3devicesthatarecompatiblewiththisinterface. Table7-60.CompatibleJEDECDDR3Devices(PerInterface) NO. PARAMETER TESTCONDITIONS MIN MAX UNIT t andt C(DDR_CK) C(DDR_CKn) DDR3-800 =3.3ns 1 JEDECDDR3devicespeedgrade t andt C(DDR_CK) C(DDR_CKn) DDR3-1600 =2.5ns 2 JEDECDDR3devicebitwidth x8 x16 bits 3 JEDECDDR3devicecount(1) 1 2 devices (1) ForvalidDDR3deviceconfigurationsanddevicecounts,seeSection7.7.2.3.3.1,Figure7-47,andFigure7-49. 7.7.2.3.3.3 PCBStackup The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 7-61. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrityandelectromagneticinterferenceperformance,ortoreducethesizeofthePCBfootprint. Table7-61.MinimumPCBStackup(1) LAYER TYPE DESCRIPTION 1 Signal Topsignalrouting 2 Plane Ground 3 Plane SplitPowerPlane 4 Signal Bottomsignalrouting (1) Allsignalsthathavecriticalsignalintegrityrequirementsshouldberoutedfirstonlayer1.Itmaynotbepossibletorouteallofthese signalsonlayer1,thereforerequiringroutingofsomesignalsonlayer4.Whenthisisdone,thesignalroutesonlayer4mustnotcross splitsinthepowerplane. 174 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-62.PCBStackupSpecifications(1) NO. PARAMETER MIN TYP MAX UNIT 1 PCBroutingandplanelayers 4 2 Signalroutinglayers 2 3 FullgroundreferencelayersunderDDR3routingregion(2) 1 4 FullVDDS_DDRpowerreferencelayersundertheDDR3routingregion(2) 1 5 NumberofreferenceplanecutsallowedwithinDDR3routingregion(3) 0 6 NumberoflayersbetweenDDR3routinglayerandreferenceplane(4) 0 7 PCBroutingfeaturesize 4 mils 8 PCBtracewidth,w 4 mils 9 PCBBGAescapeviapadsize(5) 18 20 mils 10 PCBBGAescapeviaholesize 10 mils 11 Single-endedimpedance,Zo(6) 50 75 Ω 12 Impedancecontrol(7)(8) Zo-5 Zo Zo+5 Ω (1) FortheDDR3deviceBGApadsize,seetheDDR3devicemanufacturerdocumentation. (2) Groundreferencelayersarepreferredoverpowerreferencelayers.Besuretoincludebypasscapacitorstoaccommodatereference layerreturncurrentasthetraceroutesswitchroutinglayers. (3) NotracesshouldcrossreferenceplanecutswithintheDDR3routingregion.High-speedsignaltracescrossingreferenceplanecuts createlargereturncurrentpathswhichcanleadtoexcessivecrosstalkandEMIradiation. (4) Referenceplanesaretobedirectlyadjacenttothesignalplanetominimizethesizeofthereturncurrentloop. (5) An18-milpadassumesViaChannelisthemosteconomicalBGAescape.A20-milpadmaybeusedifadditionallayersareavailable forpowerrouting.An18-milpadisrequiredforminimumlayercountescape. (6) Zoisthenominalsingled-endedimpedanceselectedforthePCB. (7) ThisparameterspecifiestheACcharacteristicimpedancetoleranceforeachsegmentofaPCBsignaltracerelativetothechosenZo definedbythesingle-endedimpedanceparameter. (8) Tighterimpedancecontrolisrequiredtoensureflighttimeskewisminimal. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 175 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.3.3.4 Placement Figure 7-50 shows the required placement for the AM335x device as well as the DDR3 devices. The dimensions for this figure are defined in Table 7-63. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengthsandallowforproperroutingspace. X1 X2 DDR3 Interface Y Figure7-50.PlacementSpecifications Table7-63.PlacementSpecifications(1) NO. PARAMETER MIN MAX UNIT 1 X1(2)(3)(4) 1000 mils 2 X2(2)(3) 600 mils 3 YOffset(2)(3)(4) 1500 mils 4 Clearancefromnon-DDR3signaltoDDR3keepoutregion(5)(6) 4 w (1) DDR3keepoutregiontoencompassentireDDR3routingarea. (2) Fordimensiondefinitions,seeFigure7-50. (3) MeasurementsfromcenteroftheAM335xdevicetocenteroftheDDR3device. (4) MinimizingX1andYimprovestimingmargins. (5) wisdefinedasthesignaltracewidth. (6) Non-DDR3signalsallowedwithinDDR3keepoutregionprovidedtheyareseparatedfromDDR3routinglayersbyagroundplane. 176 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.3.3.5 DDR3KeepoutRegion The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout region is defined for this purpose and is shown in Figure 7-51. This region should encompass all DDR3 circuitry and the region size varies with component placement and DDR3 routing. Additional clearances required for the keepout region are shown in Table 7-63. Non-DDR3 signals must not be routed on the same signal layer as DDR3 signals within the DDR3 keepout region. Non-DDR3 signals may be routed in the region provided they are routed on layers separated from DDR3 signal layers by a ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition, theVDDS_DDRpowerplaneshouldcovertheentirekeepoutregion. DDR3 Interface DDR3 Keepout Region Encompasses Entire DDR3 RoutingArea Figure7-51.DDR3KeepoutRegion 7.7.2.3.3.6 BulkBypassCapacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. Table 7-64 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM335x DDR3 interface and DDR3 devices. Additional bulkbypasscapacitancemaybeneededforothercircuitry. Table7-64.BulkBypassCapacitors(1) NO. PARAMETER MIN MAX UNIT 1 AM335xVDDS_DDRbulkbypasscapacitorcount 2 devices 2 AM335xVDDS_DDRbulkbypasstotalcapacitance 20 μF 3 DDR3number1bulkbypasscapacitorcount 2 devices 4 DDR3number1bulkbypasstotalcapacitance 20 μF 5 DDR3number2bulkbypasscapacitorcount(2) 2 devices 6 DDR3number2bulkbypasstotalcapacitance(2) 20 μF (1) Thesedevicesshouldbeplacednearthedevicestheyarebypassing,butpreferenceshouldbegiventotheplacementofthehigh- speed(HS)bypasscapacitorsandDDR3signalrouting. (2) OnlyusedwhentwoDDR3devicesareused. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 177 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.3.3.7 High-SpeedBypassCapacitors High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device DDR3power,and the AM335x device DDR3 ground connections. Table 7-65 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to: • FitasmanyHSbypasscapacitorsaspossible. • Minimizethedistancefromthebypasscapacitortothepowerterminalsbeingbypassed. • Usethesmallestphysicalsizedcapacitorspossiblewiththehighestcapacitancereadilyavailable. • Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest holesizeviapossible. • Minimizeviasharing.NotethelimitsonviasharingshowninTable7-65. Table7-65.High-SpeedBypassCapacitors NO. PARAMETER MIN TYP MAX UNIT 1 HSbypasscapacitorpackagesize(1) 0201 0402 10mils Distance,HSbypasscapacitortoAM335xVDDS_DDRandVSSterminal 2 beingbypassed(2)(3)(4) 400 mils 3 AM335xVDDS_DDRHSbypasscapacitorcount 20 devices 4 AM335xVDDS_DDRHSbypasscapacitortotalcapacitance 1 μF TracelengthfromAM335xVDDS_DDRandVSSterminaltoconnection 5 via(2) 35 70 mils 6 Distance,HSbypasscapacitortoDDR3devicebeingbypassed(5) 150 mils 7 DDR3deviceHSbypasscapacitorcount(6) 12 devices 8 DDR3deviceHSbypasscapacitortotalcapacitance(6) 0.85 μF 9 NumberofconnectionviasforeachHSbypasscapacitor(7)(8) 2 vias 10 Tracelengthfrombypasscapacitorconnecttoconnectionvia(2)(8) 35 100 mils NumberofconnectionviasforeachDDR3devicepowerandground 11 terminal(9) 1 vias TracelengthfromDDR3devicepowerandgroundterminaltoconnection 12 via(2)(7) 35 60 mils (1) LxW,10-milunits;forexample,a0402isa40x20-milsurface-mountcapacitor. (2) Closerandshorterisbetter. (3) MeasuredfromthenearestAM335xVDDS_DDRandgroundterminaltothecenterofthecapacitorpackage. (4) ThreeofthesecapacitorsshouldbelocatedunderneaththeAM335xdevice,betweentheclusterofVDDS_DDRandgroundterminals, betweentheDDR3interfacesonthepackage. (5) MeasuredfromtheDDR3devicepowerandgroundterminaltothecenterofthecapacitorpackage. (6) PerDDR3device. (7) AnadditionalHSbypasscapacitorcansharetheconnectionviasonlyifitismountedontheoppositesideoftheboard.Nosharingof viasispermittedonthesamesideoftheboard. (8) AnHSbypasscapacitormayshareaviawithaDDR3devicemountedonthesamesideofthePCB.Awidetraceshouldbeusedfor theconnectionandthelengthfromthecapacitorpadtotheDDR3devicepadshouldbelessthan150mils. (9) UptotwopairsofDDR3powerandgroundterminalsmayshareavia. 7.7.2.3.3.7.1 ReturnCurrentBypassCapacitors Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals hopping from one signal layer to another. The bypass capacitor here provides a path for the return current to hop planes along with the signal. As many of these return current bypass capacitors should be used as possible. Because these are returns for signal current, the signal via size may be used for these capacitors. 178 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.3.3.8 NetClasses Table 7-66 lists the clock net classes for the DDR3 interface. Table 7-67 lists the signal net classes, and associated clock net classes, for signals in the DDR3 interface. These net classes are used for the terminationandroutingrulesthatfollow. Table7-66.ClockNetClassDefinitions CLOCKNETCLASS AM335xPINNAMES CK DDR_CKandDDR_CKn DQS0 DDR_DQS0andDDR_DQSn0 DQS1 DDR_DQS1andDDR_DQSn1 Table7-67.SignalNetClassDefinitions ASSOCIATEDCLOCKNET SIGNALNETCLASS AM335xPINNAMES CLASS DDR_BA[2:0],DDR_A[15:0],DDR_CSn0,DDR_CASn,DDR_RASn, ADDR_CTRL CK DDR_WEn,DDR_CKE,DDR_ODT DQ0 DQS0 DDR_D[7:0],DDR_DQM0 DQ1 DQS1 DDR_D[15:8],DDR_DQM1 7.7.2.3.3.9 DDR3SignalTermination Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are coveredintheroutingrulesinthefollowingsections. Figure 7-48 provides an example DDR3 schematic with a single 16-bit DDR3 memory device that does not have V termination on the address and control signals. A typical DDR3 point-to-point topology may TT provide acceptable signal integrity without V termination. System performance should be verified by TT performingsignalintegrityanalysisusingspecificPCBdesigndetailsbeforeimplementingthistopology. 7.7.2.3.3.10 DDR_VREFRouting DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x device. DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with avoltagedividerconnectedtotheVDDS_DDRpowersupply.Itshouldberoutedasanominal20-milwide trace with 0.1 µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to accommodateroutingcongestion. 7.7.2.3.3.11 VTT Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should beroutedasapowersub-plane.VTTshouldbebypassedneartheterminatorresistors. 7.7.2.3.4 DDR3CKandADDR_CTRLTopologiesandRoutingDefinition The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew between them. CK is a bit more complicated because it runs at a higher transition rate and is differential. The following subsections show the topology and routing for various DDR3 configurations for CK and ADDR_CTRL. The figures in the following subsections define the terms for the routing specification detailedinTable7-68. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 179 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.3.4.1 TwoDDR3Devices Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a pairtosaveboardspaceatacostofincreasedroutingcomplexityandpartsonthebacksideofthePCB. 7.7.2.3.4.1.1 CKandADDR_CTRLTopologies,TwoDDR3Devices Figure 7-52 shows the topology of the CK net classes and Figure 7-53 shows the topology for the correspondingADDR_CTRLnetclasses. DDR3 Differential CK Input Buffers + – + – S+S- S+S- AA AA Clock Parallel Terminator VDDS_DDR Rcp A1 A2 A3 AT Cac AM335x + Differential Clock Output Buffer – 0.1 µF Rcp A1 A2 A3 AT Routed as Differential Pair Figure7-52.CKTopologyforTwoDDR3Devices DDR3Address and Control Input Buffers S S A A Address and Control Terminator AM335x Rtt Address and Control A1 A2 A3 AT Vtt Output Buffer Figure7-53.ADDR_CTRLTopologyforTwoDDR3Devices 7.7.2.3.4.1.2 CKandADDR_CTRLRouting,TwoDDR3Devices Figure 7-54 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 7-55 showsthecorrespondingADDR_CTRLrouting. 180 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 11 AA VDDS_DDR Rcp Cac A2 A3 AT A2 A3 AT Rcp 0.1 µF = S+S- AA Figure7-54.CKRoutingforTwoSingle-SidedDDR3Devices 1 A Rtt A2 A3 AT Vtt = S A Figure7-55.ADDR_CTRLRoutingforTwoSingle-SidedDDR3Devices Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 181 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased routing and assembly complexity. Figure 7-56 and Figure 7-57 show the routing for CK and ADDR_CTRL, respectively,fortwoDDR3devicesmirroredinasingle-pairconfiguration. 11 AA VDDS_DDR Rcp Cac A2 A3 AT A2 A3 AT Rcp 0.1 µF = S+S- AA Figure7-56.CKRoutingforTwoMirroredDDR3Devices 1 A Rtt A2 A3 AT Vtt = S A Figure7-57.ADDR_CTRLRoutingforTwoMirroredDDR3Devices 182 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.7.2.3.4.2 OneDDR3Device One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as one16-bitbank. 7.7.2.3.4.2.1 CKandADDR_CTRLTopologies,OneDDR3Device Figure 7-58 shows the topology of the CK net classes and Figure 7-59 shows the topology for the correspondingADDR_CTRLnetclasses. DDR3 Differential CK Input Buffer + – S+S- AA Clock Parallel Terminator VDDS_DDR Rcp A1 A2 AT Cac AM335x + Differential Clock Output Buffer – 0.1 µF Rcp A1 A2 AT Routed as Differential Pair Figure7-58.CKTopologyforOneDDR3Device DDR3Address and Control Input Buffers S A Address and Control Terminator AM335x Rtt Address and Control A1 A2 AT Vtt Output Buffer Figure7-59.ADDR_CTRLTopologyforOneDDR3Device Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 183 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.3.4.2.2 CKandADDR_CTRLRouting,OneDDR3Device Figure 7-60 shows the CK routing for one DDR3 device. Figure 7-61 shows the corresponding ADDR_CTRLrouting. 11 AA VDDS_DDR Rcp Cac A2 AT A2 AT Rcp 0.1 µF = S+S- AA Figure7-60.CKRoutingforOneDDR3Device 1 A Rtt A2 AT Vtt = S A Figure7-61.ADDR_CTRLRoutingforOneDDR3Device 7.7.2.3.5 DataTopologiesandRoutingDefinition No matter the number of DDR3 devices used, the data line topology is always point to point, so its definitionissimple. 7.7.2.3.5.1 DQS[x]andDQ[x]Topologies,AnyNumberofAllowedDDR3Devices DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point single-ended. Figure 7-62 andFigure7-63showthesetopologies. 184 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Am335x DQS[x]+ DDR3 DQS[x] DQS[x] DQS[x]- I/O Buffer I/O Buffer Routed Differentially x=0,1 Figure7-62.DQS[x]Topology AM335x DDR3 DQ[x] DQ[x] DQ[x] I/O Buffer I/O Buffer x=0,1 Figure7-63.DQ[x]Topology 7.7.2.3.5.2 DQS[x]andDQ[x]Routing,AnyNumberofAllowedDDR3Devices Figure7-64andFigure7-65showtheDQS[x]andDQ[x]routing. DQS[x] DQS[x]+ DQS[x]- Routed Differentially x=0,1 Figure7-64.DQS[x]RoutingWithAnyNumberofAllowedDDR3Devices DQ[x] x=0,1 Figure7-65.DQ[x]RoutingWithAnyNumberofAllowedDDR3Devices Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 185 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.7.2.3.6 RoutingSpecification 7.7.2.3.6.1 CKandADDR_CTRLRoutingSpecification Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable traceroutelengthistowithina percentage of its Manhattan distance. CACLM is defined as Clock Address ControlLongestManhattandistance. Given the clock and address pin locations on the AM335x device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-66 shows this distance for two loads. The specifications on the lengths of the transmission lines for the address bus are determined from this distance. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specificationsarecontainedinTable7-68. A8(A) A1 CACLMY CACLMX A8(A) A8(A) Rtt A2 A3 AT Vtt = S A A. It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net classthatsatisfiesthiscriteriaanduseasthebaselineforCKandADDR_CTRLskewmatchingandlengthcontrol. ThelengthofshorterCKandADDR_CTRLstubsaswellasthelengthoftheterminatorstubarenotincludedinthis lengthcalculation.Nonincludedlengthsaregrayedoutinthefigure. AssumingA8isthelongest,CALM=CACLMY+CACLMX+300mils. Theextra300milsallowsforroutingdownlowerthantheDDR3memoriesandreturninguptoreachA8. Figure7-66.CACLMforTwoAddressLoadsonOneSideofPCB Table7-68.CKandADDR_CTRLRoutingSpecification(1)(2)(3) NO. PARAMETER MIN TYP MAX UNIT 1 A1+A2length 2500 mils 2 A1+A2skew 25 mils 3 A3length 660 mils 4 A3skew(4) 25 mils 5 A3skew(5) 125 mils 6 ASlength 100 mils 186 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-68.CKandADDR_CTRLRoutingSpecification(1)(2)(3)(continued) NO. PARAMETER MIN TYP MAX UNIT 7 ASskew 25 mils 8 AS+andAS–length 70 mils 9 AS+andAS–skew 5 mils 10 ATlength(6) 500 mils 11 ATskew(7) 100 mils 12 ATskew(8) 5 mils 13 CKandADDR_CTRLnominaltracelength(9) CACLM-50 CACLM CACLM+50 mils 14 Center-to-centerCKtootherDDR3tracespacing(10) 4w 15 Center-to-centerADDR_CTRLtootherDDR3tracespacing(10)(11) 4w 16 Center-to-centerADDR_CTRLtootherADDR_CTRLtracespacing(10) 3w 17 CKcenter-to-centerspacing(12) 18 CKspacingtoothernet(10) 4w 19 Rcp(13) Zo-1 Zo Zo+1 Ω 20 Rtt(13)(14) Zo-5 Zo Zo+5 Ω (1) CKrepresentstheclocknetclass,andADDR_CTRLrepresentstheaddressandcontrolsignalnetclass. (2) Theuseofviasshouldbeminimized. (3) AdditionalbypasscapacitorsarerequiredwhenusingtheVDDS_DDRplaneasthereferenceplanetoallowthereturncurrenttojump betweentheVDDS_DDRplaneandthegroundplanewhenthenetclassswitcheslayersatavia. (4) Mirroredconfiguration(oneDDR3deviceontopoftheboardandoneDDR3deviceonthebottom). (5) Nonmirroredconfiguration(allDDR3memoriesonsamesideofPCB). (6) Whilethislengthcanbeincreasedforconvenience,itslengthshouldbeminimized. (7) ADDR_CTRLnetclassonly(notCKnetclass).Minimizingthisskewisrecommended,butnotrequired. (8) CKnetclassonly. (9) CACLMisthelongestManhattandistanceoftheCKandADDR_CTRLnetclasses+300mils.Fordefinition,seeSection7.7.2.3.6.1 andFigure7-66. (10) Center-to-centerspacingisallowedtofalltominimum(w)forupto1250milsofroutedlength. (11) SignalsfromoneDQnetclassshouldbeconsideredotherDDR3tracestoanotherDQnetclass. (12) CKspacingsettoensureproperdifferentialimpedance.DifferentialimpedanceshouldbeZ x2,whereZ isthesingle-ended o o impedancedefinedinTable7-62. (13) Sourcetermination(seriesresistoratdriver)isspecificallynotallowed. (14) Terminationvaluesshouldbeuniformacrossthenetclass. 7.7.2.3.6.2 DQS[x]andDQ[x]RoutingSpecification SkewwithintheDQS[x]andDQ[x]netclassesdirectlyreducessetupandholdmarginand,thus,thisskew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs, DQLM0-DQLM1. NOTE Matching the lengths across all bytes is not required, nor is it recommended. Length matchingisonlyrequiredwithineachbyte. Given the DQS[x] and DQ[x] pin locations on the AM335x device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-67 shows this distance for a two-load case. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 7- 69. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 187 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com DQLMX0 DQ[0:7], DM0, DQS0 DQ0 DQ[8:15], DM1, DQS1 DQ1 DQLMX1 DQLMY0 DQLMY1 1 0 DQ0 - DQ1 represent data bytes 0 - 1. TherearetwoDQLMs,oneforeachbyte(16-bitinterface).EachDQLMisthelongestManhattandistanceofthebyte; therefore: DQLM0=DQLMX0+DQLMY0 DQLM1=DQLMX1+DQLMY1 Figure7-67.DQLMforAnyNumberofAllowedDDR3Devices Table7-69.DQS[x]andDQ[x]RoutingSpecification(1)(2) NO. PARAMETER MIN TYP MAX UNIT 1 DQ0nominallength(3)(4) DQLM0 mils 2 DQ1nominallength(3)(5) DQLM1 mils 3 DQ[x]skew(6) 25 mils 4 DQS[x]skew 5 mils 5 DQS[x]-to-DQ[x]skew(6)(7) 25 mils 6 Center-to-centerDQ[x]tootherDDR3tracespacing(8)(9) 4w 7 Center-to-centerDQ[x]tootherDQ[x]tracespacing(8)(10) 3w 8 DQS[x]center-to-centerspacing(11) 9 DQS[x]center-to-centerspacingtoothernet(8) 4w (1) DQS[x]representstheDQS0andDQS1clocknetclasses,andDQ[x]representstheDQ0andDQ1signalnetclasses. (2) Externalterminationdisallowed.Dataterminationshouldusebuilt-inODTfunctionality. (3) DQLMnisthelongestManhattandistanceofabyte.Fordefinition,seeSection7.7.2.3.6.2andFigure7-67. (4) DQLM0isthelongestManhattanlengthfortheDQ0netclass. (5) DQLM1isthelongestManhattanlengthfortheDQ1netclass. (6) Lengthmatchingisonlydonewithinabyte.Lengthmatchingacrossbytesisnotrequired. (7) EachDQSclocknetclassislengthmatchedtoitsassociatedDQsignalnetclass. (8) Center-to-centerspacingisallowedtofalltominimumforupto1250milsofroutedlength. (9) OtherDDR3tracespacingmeanssignalsthatarenotpartofthesameDQ[x]signalnetclass. (10) ThisappliestospacingwithinsameDQ[x]signalnetclass. (11) DQS[x]pairspacingissettoensureproperdifferentialimpedance.DifferentialimpedanceshouldbeZ x2,whereZ isthesingle- o o endedimpedancedefinedinTable7-62. 188 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.8 I2C For more information, see the Inter-Integrated Circuit (I2C) section of the AM335x and AMIC110 Sitara ProcessorsTechnicalReferenceManual. 7.8.1 I2C Electrical Data and Timing Table7-70.I2CTimingConditions –SlaveMode STANDARDMODE FASTMODE PARAMETER UNIT MIN MAX MIN MAX OutputCondition C Capacitiveloadforeachbusline 400 400 pF b Table7-71. TimingRequirementsforI2CInputTimings (seeFigure7-68) STANDARDMODE FASTMODE NO. UNIT MIN MAX MIN MAX 1 t Cycletime,SCL 10 2.5 µs c(SCL) Setuptime,SCLhighbeforeSDAlow(forarepeated 2 t 4.7 0.6 µs su(SCLH-SDAL) STARTcondition) Holdtime,SCLlowafterSDAlow(foraSTARTanda 3 t 4 0.6 µs h(SDAL-SCLL) repeatedSTARTcondition) 4 t Pulseduration,SCLlow 4.7 1.3 µs w(SCLL) 5 t Pulseduration,SCLhigh 4 0.6 µs w(SCLH) 6 t Setuptime,SDAvalidbeforeSCLhigh 250 100(1) ns su(SDAV-SCLH) 7 t Holdtime,SDAvalidafterSCLlow 0(2) 3.45(3) 0(2) 0.9(3) µs h(SCLL-SDAV) Pulseduration,SDAhighbetweenSTOPandSTART 8 t 4.7 1.3 µs w(SDAH) conditions 9 t Risetime,SDA 1000 300 ns r(SDA) 10 t Risetime,SCL 1000 300 ns r(SCL) 11 t Falltime,SDA 300 300 ns f(SDA) 12 t Falltime,SCL 300 300 ns f(SCL) 13 t Setuptime,highbeforeSDAhigh(forSTOPcondition) 4 0.6 µs su(SCLH-SDAH) 14 t Pulseduration,spike(mustbesuppressed) 0 50 0 50 ns w(SP) (1) Afast-modeI2C-busdevicecanbeusedinastandard-modeI2C-bussystem,buttherequirementt ≥250nsmustthenbe su(SDA-SCLH) met.ThisisautomaticallythecaseifthedevicedoesnotstretchtheLOWperiodoftheSCLsignal.IfsuchadevicestretchestheLOW periodoftheSCLsignal,itmustoutputthenextdatabittotheSDAlinet +t =1000+250=1250ns(accordingtothe rmax su(SDA-SCLH) standard-modeI2C-BusSpecification)beforetheSCLlineisreleased. (2) Adevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignal(referredtotheV oftheSCLsignal)tobridgethe IHmin undefinedregionofthefallingedgeofSCL. (3) Themaximumt hasonlytobemetifthedevicedoesnotstretchthelowperiod[t ]oftheSCLsignal. h(SDA-SCLL) w(SCLL) Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 189 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 11 9 I2C[x]_SDA 8 6 14 4 13 10 5 I2C[x]_SCL 1 12 3 7 2 3 Stop Start Repeated Stop Start Figure7-68.I2CReceiveTiming Table7-72.SwitchingCharacteristicsforI2COutputTimings (seeFigure7-69) STANDARDMODE FASTMODE NO. PARAMETER UNIT MIN MAX MIN MAX 15 t Cycletime,SCL 10 2.5 µs c(SCL) Setuptime,SCLhighbeforeSDAlow(forarepeated 16 t 4.7 0.6 µs su(SCLH-SDAL) STARTcondition) Holdtime,SCLlowafterSDAlow(foraSTARTanda 17 t 4 0.6 µs h(SDAL-SCLL) repeatedSTARTcondition) 18 t Pulseduration,SCLlow 4.7 1.3 µs w(SCLL) 19 t Pulseduration,SCLhigh 4 0.6 µs w(SCLH) 20 t Setuptime,SDAvalidbeforeSCLhigh 250 100 ns su(SDAV-SCLH) 21 t Holdtime,SDAvalidafterSCLlow 0 3.45 0 0.9 µs h(SCLL-SDAV) Pulseduration,SDAhighbetweenSTOPandSTART 22 t 4.7 1.3 µs w(SDAH) conditions 27 t Setuptime,highbeforeSDAhigh(forSTOPcondition) 4 0.6 µs su(SCLH-SDAH) I2C[x]_SDA 22 20 18 27 19 I2C[x]_SCL 15 17 21 16 17 Stop Start Repeated Stop Start Figure7-69.I2CTransmitTiming 7.9 JTAG Electrical Data and Timing Table7-73.JTAGTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions 190 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-73.JTAGTimingConditions(continued) PARAMETER MIN TYP MAX UNIT t Inputsignalrisetime 5 ns R t Inputsignalfalltime 5 ns F OutputConditions C Outputloadcapacitance 5 15 pF LOAD Table7-74.TimingRequirementsforJTAG (seeFigure7-70) OPP100 OPP50 NO. UNIT MIN MAX MIN MAX 1 t Cycletime,TCK 81.5 104.5 ns c(TCK) 1a t Pulseduration,TCKhigh(40%oft ) 32.6 41.8 ns w(TCKH) c 1b t Pulseduration,TCKlow(40%oft ) 32.6 41.8 ns w(TCKL) c t Inputsetuptime,TDIvalidtoTCKhigh 3 3 ns su(TDI-TCKH) 3 t Inputsetuptime,TMSvalidtoTCKhigh 3 3 ns su(TMS-TCKH) t Inputholdtime,TDIvalidfromTCKhigh 8.05 8.05 ns h(TCKH-TDI) 4 t Inputholdtime,TMSvalidfromTCKhigh 8.05 8.05 ns h(TCKH-TMS) Table7-75.SwitchingCharacteristicsforJTAG (seeFigure7-70) OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX 2 t Delaytime,TCKlowtoTDOvalid 3 27.6 4 36.8 ns d(TCKL-TDO) 1 1a 1b TCK 2 TDO 3 4 TDI/TMS Figure7-70.JTAGTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 191 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.10 LCD Controller (LCDC) The LCDC consists of two independent controllers, the raster controller and the LCD interface display driver (LIDD) controller. Each controller operates independently from the other and only one of them is activeatanygiventime. • The raster controller handles the synchronous LCD interface. It provides timing and data for constant graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale and serializer. Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block in the system. A built-in DMA engine supplies the graphics data to the raster engine which,inturn,outputstotheexternalLCDdevice. • TheLIDDcontrollersupportstheasynchronousLCD interface. It provides full-timing programmability of controlsignals(CS,WE,OE,ALE)andoutputdata. The maximum resolution for the LCD controller is 2048 × 2048 pixels. The maximum frame rate is determinedbytheimagesizeincombinationwiththepixelclockrate. Table7-76.LCDControllerTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions T Inputsignalfalltime 1 5 ns R T Inputsignalfalltime 1 5 ns F OutputCondition LIDDmode 5 60 C Outputloadcapacitance pF LOAD Rastermode 3 30 7.10.1 LCD Interface Display Driver (LIDD Mode) Table7-77.TimingRequirementsforLCDLIDDMode (seeFigure7-72throughFigure7-80) OPP100 NO. UNIT MIN MAX Setuptime,LCD_DATA[15:0]validbefore 16 t 18 ns su(LCD_DATA-LCD_MEMORY_CLK) LCD_MEMORY_CLKhigh Holdtime,LCD_DATA[15:0]validafter 17 t 0 ns h(LCD_MEMORY_CLK-LCD_DATA) LCD_MEMORY_CLKhigh 18 t Transitiontime,LCD_DATA[15:0] 1 3 ns t(LCD_DATA) Table7-78.SwitchingCharacteristicsforLCDLIDDMode (seeFigure7-72throughFigure7-80) OPP100 NO. PARAMETER UNIT MIN MAX 1 t Cycletime,LCD_MEMORY_CLK 23.7 ns c(LCD_MEMORY_CLK) 2 t Pulseduration,LCD_MEMORY_CLKhigh 0.45t 0.55t ns w(LCD_MEMORY_CLKH) c c 3 t Pulseduration,LCD_MEMORY_CLKlow 0.45t 0.55t ns w(LCD_MEMORY_CLKL) c c Delaytime,LCD_MEMORY_CLKhighto 4 t 7 ns d(LCD_MEMORY_CLK-LCD_DATAV) LCD_DATA[15:0]valid(write) Delaytime,LCD_MEMORY_CLKhighto 5 t 0 ns d(LCD_MEMORY_CLK-LCD_DATAI) LCD_DATA[15:0]invalid(write) Delaytime,LCD_MEMORY_CLKhighto 6 t 0 6.8 ns d(LCD_MEMORY_CLK-LCD_AC_BIAS_EN) LCD_AC_BIAS_EN Delaytime,LCD_MEMORY_CLKhighto 8 t 0 7 ns d(LCD_MEMORY_CLK-LCD_VSYNC) LCD_VSYNC 192 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-78.SwitchingCharacteristicsforLCDLIDDMode(continued) (seeFigure7-72throughFigure7-80) OPP100 NO. PARAMETER UNIT MIN MAX Delaytime,LCD_MEMORY_CLKhighto 10 t 0 7 ns d(LCD_MEMORY_CLK-LCD_HYSNC) LCD_HSYNC 12 t Delaytime,LCD_MEMORY_CLKhightoLCD_PCLK 0 7 ns d(LCD_MEMORY_CLK-LCD_PCLK) Delaytime,LCD_MEMORY_CLKhighto 14 t 0 7 ns d(LCD_MEMORY_CLK-LCD_DATAZ) LCD_DATA[15:0]high-Z Delaytime,LCD_MEMORY_CLKhighto 15 t 0 7 ns d(LCD_MEMORY_CLK-LCD_DATA) LCD_DATA[15:0]driven CS_DELAY W_SU (0 to 3) (0 to 31) W_STROBE (1 to 63) W_HOLD (1 to 15) LCD_MEMORY_CLK 6 6 LCD_MEMORY_CLK (E1) 4 5 LCD_DATA[7:0] Write Instruction 8 8 LCD_VSYNC (RS) 10 10 LCD_HSYNC (R/W) 6 6 LCD_AC_BIAS_EN (E0) A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first LCD_MEMORY_CLKwaveformis onlyshownas a referenceoftheinternalclockthat sequences theothersignals. The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to implementtheE1functioninHitachimode. Figure7-71.CommandWriteinHitachiMode Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 193 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com CS_DELAY W_SU (0 to 3) (0 to 31) W_STROBE (1 to 63) W_HOLD (1 to 15) LCD_MEMORY_CLK 6 6 LCD_MEMORY_CLK (E1) 4 5 LCD_DATA[15:0] Write Data LCD_VSYNC (RS) 10 10 LCD_HSYNC (R/W) 6 6 LCD_AC_BIAS_EN (E0) A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first LCD_MEMORY_CLKwaveformis onlyshownas a referenceoftheinternalclockthat sequences theothersignals. The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to implementtheE1functioninHitachimode. Figure7-72.DataWriteinHitachiMode R_SU R_HOLD (0 to 31) (1 to 15) CS_DELAY R_STROBE (0 to 3) (1 to 63) LCD_MEMORY_CLK 6 6 LCD_MEMORY_CLK (E1) 17 14 16 15 LCD_DATA[15:0] Read Command 8 18 8 LCD_VSYNC (RS) LCD_HSYNC (R/W) 6 6 LCD_AC_BIAS_EN (E0) A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first LCD_MEMORY_CLKwaveformis onlyshownas a referenceoftheinternalclockthat sequences theothersignals. The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to implementtheE1functioninHitachimode. Figure7-73.CommandReadinHitachiMode 194 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 R_SU R_HOLD (0 to 31) (1 to 15) CS_DELAY R_STROBE (0 to 3) (1 to 63) LCD_MEMORY_CLK 6 6 LCD_MEMORY_CLK (E1) 17 14 16 15 LCD_DATA[15:0] Read Data 18 LCD_VSYNC (RS) LCD_HSYNC (R/W) 6 6 LCD_AC_BIAS_EN (E0) A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first LCD_MEMORY_CLKwaveformis onlyshownas a referenceoftheinternalclockthat sequences theothersignals. The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to implementtheE1functioninHitachimode. Figure7-74.DataReadinHitachiMode Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 195 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com W_HOLD W_HOLD (1−15) (1−15) 1 W_SU W_SU (0−31) W_STROBE (0−31) W_STROBE 2 (1−63) CS_DELAY (1−63) CS_DELAY 3 (0−3) (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 6 6 6 6 LCD_MEMORY_CLK (CS1) Async Mode 4 5 4 5 LCD_DATA[15:0] WriteAddress Write Data 6 6 6 6 LCD_AC_BIAS_EN (CS0) 8 8 LCD_VSYNC (ALE) 9 10 10 10 10 LCD_HSYNC (DIR) 12 12 12 12 LCD_PCLK (EN) A. Motorolamodecanbeconfiguredtoperformasynchronousoperationsorsynchronousoperations.When configured in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a referenceoftheinternalclockthatsequencestheothersignals. Figure7-75.Micro-InterfaceGraphicDisplayMotorolaWrite 196 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 W_HOLD R_SU (1−15) (0−31) 1 W_SU R_HOLD (0−31) W_STROBE R_STROBE (1−15) 2 (1−63) CS_DELAY (1−63) CS_DELAY 3 (0−3) (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 6 6 6 6 LCD_MEMORY_CLK (CS1) Async Mode 16 4 5 14 15 17 LCD_DATA[15:0] WriteAddress 18 Read Data 6 6 6 6 LCD_AC_BIAS_EN (CS0) 8 8 LCD_VSYNC (ALE) 9 10 10 LCD_HSYNC (DIR) 12 12 12 12 LCD_PCLK (EN) A. Motorolamodecanbeconfiguredtoperformasynchronousoperationsorsynchronousoperations.When configured in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a referenceoftheinternalclockthatsequencestheothersignals. Figure7-76.Micro-InterfaceGraphicDisplayMotorolaRead Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 197 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com R_SU (0−31) 1 R_HOLD 2 R_STROBE (1−15) (1−63) CS_DELAY 3 (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 6 6 LCD_MEMORY_CLK (CS1) Async Mode 16 14 15 17 LCD_DATA[15:0] 18 Read Status 6 6 LCD_AC_BIAS_EN (CS0) 8 8 LCD_VSYNC (ALE) LCD_HSYNC (DIR) 12 12 LCD_PCLK (EN) A. Motorolamodecanbeconfiguredtoperformasynchronousoperationsorsynchronousoperations.When configured in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a referenceoftheinternalclockthatsequencestheothersignals. Figure7-77.Micro-InterfaceGraphicDisplayMotorolaStatus 198 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 W_HOLD W_HOLD (1−15) (1−15) 1 W_SU W_SU (0−31) W_STROBE (0−31) W_STROBE 2 (1−63) CS_DELAY (1−63) CS_DELAY 3 (0−3) (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 6 6 6 6 LCD_MEMORY_CLK (CS1) Async Mode 4 5 4 5 LCD_DATA[15:0] WriteAddress Write Data 6 6 6 6 LCD_AC_BIAS_EN (CS0) 8 8 LCD_VSYNC (ALE) 10 10 10 10 LCD_HSYNC (WS) LCD_PCLK (RS) A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a referenceoftheinternalclockthatsequencestheothersignals. Figure7-78.Micro-InterfaceGraphicDisplayIntelWrite Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 199 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com W_HOLD R_SU (1−15) (0−31) 1 W_SU R_HOLD (0−31) W_STROBE R_STROBE (1−15) 2 (1−63) CS_DELAY (1−63) CS_DELAY 3 (0−3) (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 6 6 6 6 LCD_MEMORY_CLK (CS1) Async Mode 16 4 5 14 15 17 LCD_DATA[15:0] WriteAddress 18 Read Data 6 6 6 6 LCD_AC_BIAS_EN (CS0) 8 8 LCD_VSYNC (ALE) 10 10 LCD_HSYNC (WS) 12 12 LCD_PCLK (RS) A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a referenceoftheinternalclockthatsequencestheothersignals. Figure7-79.Micro-InterfaceGraphicDisplayIntelRead 200 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 R_SU (0−31) 1 R_HOLD 2 R_STROBE (1−15) (1−63) CS_DELAY 3 (0−3) LCD_MEMORY_CLK (MCLK) Sync Mode 19 6 6 LCD_MEMORY_CLK (CS1) Async Mode 16 14 15 17 LCD_DATA[15:0] 18 Read Status 6 6 LCD_AC_BIAS_EN (CS0) 8 8 LCD_VSYNC (ALE) LCD_HSYNC (WS) 12 12 LCD_PCLK (RS) A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a referenceoftheinternalclockthatsequencestheothersignals. Figure7-80.Micro-InterfaceGraphicDisplayIntelStatus Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 201 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.10.2 LCD Raster Mode Table7-79.SwitchingCharacteristicsforLCDRasterMode (seeFigure7-82throughFigure7-85) OPP50 OPP100 NO. PARAMETER UNIT MIN MAX MIN MAX 1 t Cycletime,pixelclock 15.8 7.9 ns c(LCD_PCLK) 2 t Pulseduration,pixelclockhigh 0.45t 0.55t 0.45t 0.55t ns w(LCD_PCLKH) c c c c 3 t Pulseduration,pixelclocklow 0.45t 0.55t 0.45t 0.55t ns w(LCD_PCLKL) c c c c Delaytime,LCD_PCLKtoLCD_DATA[23:0]valid 4 t 3.0 1.9 ns d(LCD_PCLK-LCD_DATAV) (write) Delaytime,LCD_PCLKtoLCD_DATA[23:0]invalid 5 t –3.0 –1.7 ns d(LCD_PCLK-LCD_DATAI) (write) 6 t Delaytime,LCD_PCLKtoLCD_AC_BIAS_EN –3.0 3.0 –1.7 1.9 ns d(LCD_PCLK-LCD_AC_BIAS_EN) 8 t Delaytime,LCD_PCLKtoLCD_VSYNC –3.0 3.0 –1.7 1.9 ns d(LCD_PCLK-LCD_VSYNC) 10 t Delaytime,LCD_PCLKtoLCD_HSYNC –3.0 3.0 –1.7 1.9 ns d(LCD_PCLK-LCD_HSYNC) Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1) register: • Verticalfrontporch(VFP) • Verticalsyncpulsewidth(VSW) • Verticalbackporch(VBP) • Linesperpanel(LPP_B10+LPP) Line-to-linetimingisderivedthroughthefollowingparametersintheLCD(RASTER_TIMING_0)register: • Horizontalfrontporch(HFP) • Horizontalsyncpulsewidth(HSW) • Horizontalbackporch(HBP) • Pixelsperpanel(PPLMSB+PPLLSB) LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2) register: • ACbiasfrequency(ACB) The display format produced in raster mode is shown in Figure 7-81. An entire frame is delivered one line at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the activationofI/OsignalLCD_HSYNC. 202 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Data Pixels (From 1 to P) P−2, P−1, 1, 1 2, 1 3, 1 P, 1 1 1 P−1, 1, 2 2, 2 P, 2 2 1, 3 P, 3 L) o 1 t m o Fr LCD s ( e n Li a at D 1, P, L−2 L−2 1, 2, P−1, P, L−1 L−1 L−1 L−1 P−2, P−1, 1, L 2, L 3, L P, L L L Figure7-81.LCDRaster-ModeDisplayFormat Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 203 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com FrameTime VSW VBP LPP_B10 + LPP VFP VSW (1 to 64) (0 to 255) (1 to 2048) (0 to 255) (1 to 64) Line Time LCD_HSYNC LCD_VSYNC LCD_DATA[23:0] 1, 1 1, 2 1, L-1 1, L P, 1 P, 2 P, L-1 P, L LCD_AC_BIAS_EN (ACTVID) 10 10 LCD_HSYNC LCD_PCLK LCD_DATA[23:0] 1, 1 2, 1 P, 1 1, 2 2, 2 P, 2 LCD_AC_BIAS_EN (ACTVID) PPLMSB + PPLLSB HFP HSW HBP PPLMSB + PPLLSB 16 × (1 to 2048) (1 to 256) (1 to 64) (1 to 256) 16 × (1 to 2048) Line 1 Line 2 Figure7-82.LCDRaster-ModeActive 204 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 FrameTime VBP= 0 VFP= 0 LPP_B10 + LPP VSW = 1 (1 to 2048) Line Time LCD_HSYNC LCD_VSYNC 1, L Data 1, L: 1, 1: 1, 2: 1, 3: 1, 4: 1, 5: 1, 6: 1, L 1, 1 1, 2 LCD_DATA[7:0] P, L P, 1 P, 2 P, 3 P, 4 P, 5 P, 6 P, L P, 1 P, 2 1, L−1 1, L−4 1, L−3 1, L−2 1, L−1 P, L−1 P, L−4 P, L−3 P, L−2 P, L−1 LCD_AC_BIAS_EN ACB ACB (0 to 255) (0 to 255) 10 10 LCD_HSYNC LCD_PCLK LCD_DATA[7:0] 1, 5 2, 5 P, 5 1, 6 2, 6 P, 6 PPLMSB + PPLLSB HFP HSW HBP PPLMSB + PPLLSB 16 x (1 to 2048) (1 to 256) (1 to 64) (1 to 256) 16 x (1 to 2048) Line 5 Line 6 A. ThedashedportionofLCD_PCLKisonlyshownasareferenceoftheinternalclockthatsequencestheothersignals. Figure7-83.LCDRaster-ModePassive Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 205 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 6 LCD_AC_BIAS_EN 8 LCD_VSYNC 10 10 LCD_HSYNC 1 2 3 LCD_PCLK (passive mode) 4 5 LCD_DATA[7:0] 1, L 2, L P, L 1, 1 2, 1 P, 1 (passive mode) 1 2 3 LCD_PCLK (active mode) 4 5 LCD_DATA[23:0] 1, L 2, L P, L (active mode) VBP= 0 VFP= 0 VWS = 1 PPLMSB + PPLLSB HFP HSW HBP PPLMSB + PPLLSB 16 x (1 to 2048) (1 to 256) (1 to 64) (1 to 256) 16 x (1 to 2048) Line L Line 1 (Passive Only) A. ThedashedportionofLCD_PCLKisonlyshownasareferenceoftheinternalclockthatsequencestheothersignals. Figure7-84.LCDRaster-ModeControlSignalActivation 206 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 6 LCD_AC_BIAS_EN 8 LCD_VSYNC 10 10 LCD_HSYNC 1 2 3 LCD_PCLK (passive mode) 4 5 LCD_D[7:0] 1, 1 2, 1 P, 1 1, 2 2, 2 P, 2 (passive mode) 1 2 3 LCD_PCLK (active mode) 4 5 LCD_DATA[23:0] 1, 1 2, 1 P, 1 (active mode) VBP= 0 VFP= 0 VWS = 1 PPLMSB + PPLLSB HFP HSW HBP PPLMSB + PPLLSB 16 x (1 to 2048) (1 to 256) (1 to 64) (1 to 256) 16 x (1 to 2048) Line 1 Line 1 for active Line 2 for passive A. ThedashedportionofLCD_PCLKisonlyshownasareferenceoftheinternalclockthatsequencestheothersignals. Figure7-85.LCDRaster-ModeControlSignalDeactivation Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 207 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.11 Multichannel Audio Serial Port (McASP) The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission (DIT). 7.11.1 McASP Device-Specific Information The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and McASP1). The McASP module consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or, alternatively, the transmit and receive sections may be synchronized. The McASP module also includesshiftregistersthatmaybeconfiguredtooperateaseithertransmitdataorreceivedata. The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for SPDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports theTDMsynchronousserialformat. The McASP module can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format; however, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode, which is useful for nonaudio data (for example, passingcontrolinformationbetweentwodevices). The McASP peripheral has additional capability for flexible clock generation and error detection/handling, aswellaserrormanagement. The device McASP0 and McASP1 modules have up to four serial data pins each. The McASP FIFO size is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used transparently to bettermanageDMA,whichcanbeleveragedtomanagedataflowmoreefficiently. For more detailed information on and the functionality of the McASP peripheral, see the Multichannel Audio Serial Port (McASP) section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual. 208 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.11.2 McASP Electrical Data and Timing Table7-80.McASPTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 1(1) 4(1) ns R t Inputsignalfalltime 1(1) 4(1) ns F OutputCondition C Outputloadcapacitance 15 30 pF LOAD (1) Exceptwhenspecifiedotherwise. Table7-81.TimingRequirementsforMcASP(1) (seeFigure7-86) OPP100 OPP50 NO. UNIT MIN MAX MIN MAX Cycletime,McASP[x]_AHCLKRand 1 t 20 40 ns c(AHCLKRX) McASP[x]_AHCLKX 2 t Pulseduration,McASP[x]_AHCLKRand 0.5P-2.5(2) 0.5P-2.5(2) ns w(AHCLKRX) McASP[x]_AHCLKXhighorlow Cycletime,McASP[x]_ACLKRand 3 t 20 40 ns c(ACLKRX) McASP[x]_ACLKX 4 t Pulseduration,McASP[x]_ACLKRand 0.5R-2.5(3) 0.5R-2.5(3) ns w(ACLKRX) McASP[x]_ACLKXhighorlow ACLKRand 11.5 15.5 ACLKXint Setuptime,McASP[x]_AFSRand t McASP[x]_AFSXinputvalidbefore ACLKRand 5 su(AFSRX- 4 6 ns McASP[x]_ACLKRand ACLKXextin ACLKRX) McASP[x]_ACLKX ACLKRand 4 6 ACLKXextout ACLKRand -1 -1 ACLKXint Holdtime,McASP[x]_AFSRand t McASP[x]_AFSXinputvalidafter ACLKRand 6 h(ACLKRX- 0.4 0.4 ns McASP[x]_ACLKRand ACLKXextin AFSRX) McASP[x]_ACLKX ACLKRand 0.4 0.4 ACLKXextout ACLKRand 11.5 15.5 ACLKXint Setuptime,McASP[x]_AXRinput ACLKRand 7 t validbeforeMcASP[x]_ACLKRand 4 6 ns su(AXR-ACLKRX) ACLKXextin McASP[x]_ACLKX ACLKRand 4 6 ACLKXextout ACLKRand -1 -1 ACLKXint Holdtime,McASP[x]_AXRinput ACLKRand 8 t validafterMcASP[x]_ACLKRand 0.4 0.4 ns h(ACLKRX-AXR) ACLKXextin McASP[x]_ACLKX ACLKRand 0.4 0.4 ACLKXextout (1) ACLKRinternal:ACLKRCTL.CLKRM=1,PDIR.ACLKR=1 ACLKRexternalinput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=0 ACLKRexternaloutput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=1 ACLKXinternal:ACLKXCTL.CLKXM=1,PDIR.ACLKX=1 ACLKXexternalinput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=0 ACLKXexternaloutput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=1 (2) P=McASP[x]_AHCLKRandMcASP[x]_AHCLKXperiodinnanoseconds(ns). (3) R=McASP[x]_ACLKRandMcASP[x]_ACLKXperiodinns. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 209 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 2 1 2 McASP[x]_ACLKR/X (Falling Edge Polarity) McASP[x]_AHCLKR/X (Rising Edge Polarity) 4 3 4 McASP[x]_ACLKR/X (CLKRP= CLKXP= 0)(A) McASP[x]_ACLKR/X (CLKRP= CLKXP= 1)(B) 6 5 McASP[x]_AFSR/X (Bit Width, 0 Bit Delay) McASP[x]_AFSR/X (Bit Width, 1 Bit Delay) McASP[x]_AFSR/X (Bit Width, 2 Bit Delay) McASP[x]_AFSR/X (Slot Width, 0 Bit Delay) McASP[x]_AFSR/X (Slot Width, 1 Bit Delay) McASP[x]_AFSR/X (Slot Width, 2 Bit Delay) 8 7 McASP[x]_AXR[x] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiverisconfiguredforfallingedge(toshiftdatain). B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiverisconfiguredforrisingedge(toshiftdatain). Figure7-86.McASPInputTiming 210 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-82.SwitchingCharacteristicsforMcASP(1) (seeFigure7-87) OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX 9 t Cycletime,McASP[x]_AHCLKRand 20(2) 40 ns c(AHCLKRX) McASP[x]_AHCLKX 10 t Pulseduration,McASP[x]_AHCLKRand 0.5P–2.5(3) 0.5P–2.5(3) ns w(AHCLKRX) McASP[x]_AHCLKXhighorlow Cycletime,McASP[x]_ACLKRand 11 t 20 40 ns c(ACLKRX) McASP[x]_ACLKX 12 t Pulseduration,McASP[x]_ACLKRand 0.5P–2.5(3) 0.5P–2.5(3) ns w(ACLKRX) McASP[x]_ACLKXhighorlow Delaytime,McASP[x]_ACLKRand ACLKRand 0 6 0 6 McASP[x]_ACLKXtransmitedgeto ACLKXint McASP[x]_AFSRand ACLKRand McASP[x]_AFSXoutputvalid ACLKXextin 2 13.5 2 18 13 t ns d(ACLKRX-AFSRX) Delaytime,McASP[x]_ACLKRand McASP[x]_ACLKXtransmitedgeto ACLKRand McASP[x]_AFSRand ACLKXext 2 13.5 2 18 McASP[x]_AFSXoutputvalidwith out PadLoopback Delaytime,McASP[x]_ACLKX ACLKXint 0 6 0 6 transmitedgetoMcASP[x]_AXR outputvalid ACLKXextin 2 13.5 2 18 14 t ns d(ACLKX-AXR) Delaytime,McASP[x]_ACLKX ACLKXext transmitedgetoMcASP[x]_AXR 2 13.5 2 18 out outputvalidwithPadLoopback Disabletime,McASP[x]_ACLKX ACLKXint 0 6 0 6 transmitedgetoMcASP[x]_AXR outputhighimpedance ACLKXextin 2 13.5 2 18 15 tdis(ACLKX-AXR) Disabletime,McASP[x]_ACLKX ns transmitedgetoMcASP[x]_AXR ACLKXext 2 13.5 2 18 outputhighimpedancewithpad out loopback (1) ACLKRinternal:ACLKRCTL.CLKRM=1,PDIR.ACLKR=1 ACLKRexternalinput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=0 ACLKRexternaloutput:ACLKRCTL.CLKRM=0,PDIR.ACLKR=1 ACLKXinternal:ACLKXCTL.CLKXM=1,PDIR.ACLKX=1 ACLKXexternalinput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=0 ACLKXexternaloutput:ACLKXCTL.CLKXM=0,PDIR.ACLKX=1 (2) 50MHz (3) P=AHCLKRandAHCLKXperiod. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 211 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 10 10 9 McASP[x]_ACLKR/X (Falling Edge Polarity) McASP[x]_AHCLKR/X (Rising Edge Polarity) 12 11 12 McASP[x]_ACLKR/X (CLKRP= CLKXP= 1)(A) McASP[x]_ACLKR/X (CLKRP= CLKXP= 0)(B) 13 13 13 13 McASP[x]_AFSR/X (Bit Width, 0 Bit Delay) McASP[x]_AFSR/X (Bit Width, 1 Bit Delay) McASP[x]_AFSR/X (Bit Width, 2 Bit Delay) McASP[x]_AFSR/X (Slot Width, 0 Bit Delay) 13 13 13 McASP[x]_AFSR/X (Slot Width, 1 Bit Delay) McASP[x]_AFSR/X (Slot Width, 2 Bit Delay) McASP[x]_AXR[x] (Data Out/Transmit) 14 15 A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiverisconfiguredforrisingedge(toshiftdatain). B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiverisconfiguredforfallingedge(toshiftdatain). Figure7-87.McASPOutputTiming 212 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.12 Multichannel Serial Port Interface (McSPI) For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x and AMIC110SitaraProcessorsTechnicalReferenceManual. 7.12.1 McSPI Electrical Data and Timing The following timings are applicable to the different configurations of McSPI in master or slave mode for anyMcSPIandanychannel(n). 7.12.1.1 McSPI—SlaveMode Table7-83.McSPITimingConditions –SlaveMode PARAMETER MIN MAX UNIT InputConditions t Inputsignalrisetime 5 ns r t Inputsignalfalltime 5 ns f OutputCondition C Outputloadcapacitance 20 pF load Table7-84.TimingRequirementsforMcSPIInputTimings—SlaveMode (seeFigure7-88) OPP100 OPP50 NO. UNIT MIN MAX MIN MAX 1 t Cycletime,SPI_CLK 62.5 124.8 ns c(SPICLK) 0.5P– 0.5P+ 0.5P– 0.5P+ 2 tw(SPICLKL) Typicalpulseduration,SPI_CLKlow 3.12(1) 3.12(1) 3.12(1) 3.12(1) ns 0.5P– 0.5P+ 0.5P– 0.5P+ 3 tw(SPICLKH) Typicalpulseduration,SPI_CLKhigh 3.12(1) 3.12(1) 3.12(1) 3.12(1) ns Setuptime,SPI_D[x](SIMO)validbeforeSPI_CLK 4 tsu(SIMO-SPICLK) activeedge(2)(3) 12.92 12.92 ns Holdtime,SPI_D[x](SIMO)validafterSPI_CLK 5 th(SPICLK-SIMO) activeedge(2)(3) 12.92 12.92 ns Setuptime,SPI_CSvalidbeforeSPI_CLKfirst 8 tsu(CS-SPICLK) edge(2) 12.92 12.92 ns 9 t Holdtime,SPI_CSvalidafterSPI_CLKlastedge(2) 12.92 12.92 ns h(SPICLK-CS) (1) P=SPI_CLKperiod. (2) ThistimingappliestoallconfigurationsregardlessofMCSPIX_CLKpolarityandwhichclockedgesareusedtodriveoutputdataand captureinputdata. (3) PinsSPIx_D0andSPIx_D1canfunctionasSIMOorSOMI. Table7-85.SwitchingCharacteristicsforMcSPIOutputTimings—SlaveMode (seeFigure7-89) OPP100 OPP50 NO. PARAMETER UNIT MIN MAX MIN MAX Delaytime,SPI_CLKactiveedgeto 6 td(SPICLK-SOMI) SPI_D[x](SOMI)transition(1)(2) –4.00 17.12 –4.00 17.12 ns Delaytime,SPI_CSactiveedgeto 7 td(CS-SOMI) SPI_D[x](SOMI)transition(1)(2) 17.12 17.12 ns (1) ThistimingappliestoallconfigurationsregardlessofMCSPIX_CLKpolarityandwhichclockedgesareusedtodriveoutputdataand captureinputdata. (2) PinsSPIx_D0andSPIx_D1canfunctionasSIMOorSOMI. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 213 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com PHA=0 EPOL=1 SPI_CS[x] (In) 1 3 8 2 9 SPI_SCLK (In) POL=0 1 3 2 POL=1 SPI_SCLK (In) 4 4 5 5 SPI_D[x] (SIMO, In) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 PHA=1 EPOL=1 SPI_CS[x] (In) 1 3 8 2 9 SPI_SCLK (In) POL=0 1 2 3 POL=1 SPI_SCLK (In) 4 4 5 5 SPI_D[x] (SIMO, In) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure7-88.SPISlaveModeReceiveTiming 214 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 PHA=0 EPOL=1 SPI_CS[x] (In) 1 3 8 2 9 SPI_SCLK (In) POL=0 1 3 2 POL=1 SPI_SCLK (In) 6 7 6 SPI_D[x] (SOMI, Out) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 PHA=1 EPOL=1 SPI_CS[x] (In) 1 3 8 2 9 SPI_SCLK (In) POL=0 1 2 3 POL=1 SPI_SCLK (In) 6 6 6 6 SPI_D[x] (SOMI, Out) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure7-89.SPISlaveModeTransmitTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 215 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.12.1.2 McSPI—MasterMode Table7-86.McSPITimingConditions –MasterMode LOWLOAD HIGHLOAD PARAMETER UNIT MIN MAX MIN MAX InputConditions t Inputsignalrisetime 8 8 ns r t Inputsignalfalltime 8 8 ns f OutputCondition C Outputloadcapacitance 5 25 pF load Table7-87.TimingRequirementsforMcSPIInputTimings – MasterMode (seeFigure7-90) OPP100 OPP50 NO. LOWLOAD HIGHLOAD LOWLOAD HIGHLOAD UNIT MIN MAX MIN MAX MIN MAX MIN MAX 4 tSsPuI(CSLOKMHI)- SSePtIu_pCLtimKea,cStivPeI_eDd[gxe]((1S)OMI)validbefore 2.29 3.02 2.29 3.02 ns Industrialextended Holdtime,SPI_D[x] temperature 7.1 7.1 7.1 7.1 5 th(SPICLKH- (SOMI)validafter (-40°Cto125°C) ns SOMI) SPI_CLKactiveedge(1) Allother 4.7 4.7 4.7 4.7 temperatureranges (1) PinsSPIx_D0andSPIx_D1canfunctionasSIMOorSOMI. Table7-88.SwitchingCharacteristicsforMcSPIOutputTimings – MasterMode (seeFigure7-91) OPP100 OPP50 NO. PARAMETER LOWLOAD HIGHLOAD LOWLOAD HIGHLOAD UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1 tc(SPICLK) Cycletime,SPI_CLK 20.8 20.8 41.6 41.6 ns Typicalpulseduration, 0.5P– 0.5P+ 0.5P– 0.5P+ 0.5P– 0.5P+ 0.5P– 0.5P+ 2 tw(SPICLKL) SPI_CLKlow 1.04(1) 1.04(1) 2.08(1) 2.08(1) 1.04(1) 1.04(1) 2.08(1) 2.08(1) ns Typicalpulseduration, 0.5P– 0.5P+ 0.5P– 0.5P+ 0.5P– 0.5P+ 0.5P– 0.5P+ 3 tw(SPICLKH) SPI_CLKhigh 1.04(1) 1.04(1) 2.08(1) 2.08(1) 1.04(1) 1.04(1) 2.08(1) 2.08(1) ns Delaytime,SPI_CLK 6 td(SPICLK-SIMO) activeedgetoSPI_D[x] –3.57 3.57 –4.62 4.62 –3.57 3.57 –4.62 4.62 ns (SIMO)transition(2) Delaytime,SPI_CSactive 7 td(CS-SIMO) edgetoSPI_D[x](SIMO) 3.57 4.62 3.57 4.62 ns transition(2) DSPelIa_yCtSimaec,tive Manodde3(31) A–4.2(4) A–2.54(4) A–4.2(4) A–2.54(4) ns 8 td(CS-SPICLK) tfoirsStPedI_gCeLK Manodde2(30) B–4.2(5) B–2.54(5) B–4.2(5) B–2.54(5) ns DSPelIa_yCtLimKela,st Manodde3(31) B–4.2(5) B–2.54(5) B–4.2(5) B–2.54(5) ns 9 td(SPICLK-CS) edgeto SinPaIc_tiCveS Manodde2(30) A–4.2(4) A–2.54(4) A–4.2(4) A–2.54(4) ns (1) P=SPI_CLKperiod. (2) PinsSPIx_D0andSPIx_D1canfunctionasSIMOorSOMI. (3) ThepolarityofSPIx_CLKandtheactiveedge(risingorfalling)onwhichmcspix_simoisdrivenandmcspix_somiislatchedisall softwareconfigurable: – SPIx_CLK(1)phaseprogrammablewiththebitPHAofMCSPI_CH(i)CONFregister:PHA=1(Modes1and3). – SPIx_CLK(1)phaseprogrammablewiththebitPHAofMCSPI_CH(i)CONFregister:PHA=0(Modes0and2). (4) CaseP=20.8ns,A=(TCS+1)×TSPICLKREF(TCSisabitfieldofMCSPI_CH(i)CONFregister). CaseP>20.8ns,A=(TCS+0.5)×Fratio×TSPICLKREF(TCSisabitfieldofMCSPI_CH(i)CONFregister). Note:P=SPI_CLKclockperiod. 216 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 (5) B=(TCS+0.5)×TSPICLKREF×Fratio(TCSisabitfieldofMCSPI_CH(i)CONFregister,Fratio:Even≥2). PHA=0 EPOL=1 SPI_CS[x] (Out) 1 3 8 2 9 SPI_SCLK (Out) POL=0 1 2 3 POL=1 SPI_SCLK (Out) 4 4 5 5 SPI_D[x] (SOMI, In) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 PHA=1 EPOL=1 SPI_CS[x] (Out) 1 3 8 2 9 SPI_SCLK (Out) POL=0 1 2 3 POL=1 SPI_SCLK (Out) 4 4 5 5 SPI_D[x] (SOMI, In) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure7-90.SPIMasterModeReceiveTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 217 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com PHA=0 EPOL=1 SPI_CS[x](Out) 1 3 8 2 9 SPI_SCLK (Out) POL=0 1 2 3 POL=1 SPI_SCLK (Out) 6 7 6 SPI_D[x] (SIMO, Out) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 PHA=1 EPOL=1 SPI_CS[x] (Out) 1 3 8 2 9 SPI_SCLK (Out) POL=0 1 2 3 POL=1 SPI_SCLK (Out) 6 6 6 6 SPI_D[x] (SIMO, Out) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 Figure7-91.SPIMasterModeTransmitTiming 218 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.13 Multimedia Card (MMC) Interface For more information, see the Multimedia Card (MMC) section of the AM335x and AMIC110 Sitara ProcessorsTechnicalReferenceManual. 7.13.1 MMC Electrical Data and Timing Table7-89.MMCTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 1 5 ns r t Inputsignalfalltime 1 5 ns f OutputCondition C Outputloadcapacitance 3 30 pF load Table7-90.TimingRequirementsforMMC[x]_CMDandMMC[x]_DAT[7:0] (seeFigure7-92) 1.8-VMODE 3.3-VMODE NO. UNIT MIN TYP MAX MIN TYP MAX 1 tsu(CMDV-CLKH) Setuptime,MMC_CMDvalidbeforeMMC_CLKrisingclockedge 4.1 4.1 ns Industrialextended temperature MMC0-2 3.76 3.76 (–40°Cto125°C) Holdtime,MMC_CMDvalidafter 2 th(CLKH-CMDV) MMC_CLKrisingclockedge MMC0 3.76 2.52 ns Allother MMC1 3.76 3.03 temperatureranges MMC2 3.76 3.0 3 tsu(DATV-CLKH) Setuptime,MMC_DATxvalidbeforeMMC_CLKrisingclockedge 4.1 4.1 ns Industrialextended temperature MMC0-2 3.76 3.76 (–40°Cto125°C) Holdtime,MMC_DATxvalidafter 4 th(CLKH-DATV) MMC_CLKrisingclockedge MMC0 3.76 2.52 ns Allother MMC1 3.76 3.03 temperatureranges MMC2 3.76 3.0 1 2 MMC[x]_CLK (Output) MMC[x]_CMD (Input) MMC[x]_DAT[7:0] (Inputs) 3 4 Figure7-92.MMC[x]_CMDandMMC[x]_DAT[7:0]InputTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 219 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table7-91.SwitchingCharacteristicsforMMC[x]_CLK (seeFigure7-93) STANDARDMODE HIGH-SPEEDMODE NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX ƒ Operatingfrequency,MMC_CLK 24 48 MHz op(CLK) t Operatingperiod:MMC_CLK 41.7 20.8 ns cop(CLK) 5 f Identificationmodefrequency,MMC_CLK 400 400 kHz id(CLK) t Identificationmodeperiod:MMC_CLK 2500 2500 ns cid(CLK) (0.5×P)– (0.5×P)– 6 tw(CLKL) Pulseduration,MMC_CLKlow t (1) t (1) ns f(CLK) f(CLK) (0.5×P)– (0.5×P)– 7 tw(CLKH) Pulseduration,MMC_CLKhigh t (1) t (1) ns r(CLK) r(CLK) (1) P=MMC_CLKperiod 5 6 7 MMC[x]_CLK (Output) Figure7-93.MMC[x]_CLK(Output) Table7-92.SwitchingCharacteristicsforMMC[x]_CMDandMMC[x]_DAT[7:0]—StandardMode (seeFigure7-94) OPP100 OPP50 NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX Delaytime,MMC_CLKfallingclock 10 t –4 14 –4 17.5 ns d(CLKL-CMD) edgetoMMC_CMDtransition Delaytime,MMC_CLKfallingclock 11 t –4 14 –4 17.5 ns d(CLKL-DAT) edgetoMMC_DATxtransition 10 MMC[x]_CLK (Output) MMC[x]_CMD (Output) MMC[x]_DAT[7:0] (Outputs) 11 Figure7-94.MMC[x]_CMDandMMC[x]_DAT[7:0]OutputTiming—StandardMode 220 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-93.SwitchingCharacteristicsforMMC[x]_CMDandMMC[x]_DAT[7:0]—High-SpeedMode (seeFigure7-95) OPP100 OPP50 NO. PARAMETER UNIT MIN TYP MAX MIN TYP MAX t Delaytime,MMC_CLKrisingclockedgeto 12 d(CLKL- 3 14 3 17.5 ns MMC_CMDtransition CMD) Delaytime,MMC_CLKrisingclockedgeto 13 t 3 14 3 17.5 ns d(CLKL-DAT) MMC_DATxtransition 12 MMC[x]_CLK (Output) MMC[x]_CMD (Output) MMC[x]_DAT[7:0] (Outputs) 13 Figure7-95.MMC[x]_CMDandMMC[x]_DAT[7:0]OutputTiming—High-SpeedMode Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 221 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS) For more information, see the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem Interface (PRU-ICSS) section of the AM335x and AMIC110 Sitara Processors Technical ReferenceManual. 7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU) Table7-94.PRU-ICSSPRUTimingConditions PARAMETER MIN MAX UNIT OutputCondition C Capacitiveloadforeachbusline 30 pF load 7.14.1.1 PRU-ICSSPRUDirectInput/OutputModeElectricalDataandTiming Table7-95.PRU-ICSSPRUTimingRequirements-DirectInputMode (seeFigure7-96) NO. MIN MAX UNIT 1 t Pulsewidth,GPI 2×P(1) ns w(GPI) t Risetime,GPI 1.00 3.00 ns r(GPI) 2 t Falltime,GPI 1.00 3.00 ns f(GPI) PRU0 1.00 3 t InternalskewbetweenGPI[n:0]signals(2) ns sk(GPI) PRU1 3.00 (1) P=L3_CLK(PRU-ICSSocpclock)period. (2) n=16 2 1 GPI[m:0] 3 Figure7-96.PRU-ICSSPRUDirectInputTiming Table7-96.PRU-ICSSPRUSwitchingRequirements –DirectOutputMode (seeFigure7-69) NO. PARAMETER MIN MAX UNIT 1 t Pulsewidth,GPO 2×P(1) ns w(GPO) PRU0 1.00 3 t InternalskewbetweenGPO[n:0]signals(2) ns sk(GPO) PRU1 5.00 (1) P=L3_CLK(PRU-ICSSocpclock)period (2) n=15 1 GPO[n:0] 3 Figure7-97.PRU-ICSSPRUDirectOutputTiming 222 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.14.1.2 PRU-ICSSPRUParallelCaptureModeElectricalDataandTiming Table7-97.PRU-ICSSPRUTimingRequirements-ParallelCaptureMode (seeFigure7-98andFigure7-99) NO. MIN MAX UNIT 1 t Cycletime,CLOCKIN 20.00 ns c(CLOCKIN) 2 t Pulseduration,CLOCKINlow 10.00 ns w(CLOCKIN_L) 3 t Pulseduration,CLOCKINhigh 10.00 ns w(CLOCKIN_H) 4 t Risingtime,CLOCKIN 1.00 3.00 ns r(CLOCKIN) 5 t Fallingtime,CLOCKIN 1.00 3.00 ns f(CLOCKIN) 6 t Setuptime,DATAINvalidbeforeCLOCKIN 5.00 ns su(DATAIN-CLOCKIN) 7 t Holdtime,DATAINvalidafterCLOCKIN 0.00 ns h(CLOCKIN-DATAIN) t Risingtime,DATAIN 1.00 3.00 ns r(DATAIN) 8 t Fallingtime,DATAIN 1.00 3.00 ns f(DATAIN) 1 3 5 4 2 CLOCKIN DATAIN 7 6 8 Figure7-98.PRU-ICSSPRUParallelCaptureTiming-RisingEdgeMode 1 3 4 5 2 CLOCKIN DATAIN 7 6 8 Figure7-99.PRU-ICSSPRUParallelCaptureTiming-FallingEdgeMode 7.14.1.3 PRU-ICSSPRUShiftModeElectricalDataandTiming Table7-98.PRU-ICSSPRUTimingRequirements – ShiftInMode (seeFigure7-100) NO. MIN MAX UNIT 1 t Cycletime,DATAIN 10.00 ns c(DATAIN) 2 t Pulsewidth,DATAIN 0.45×P(1) 0.55×P(1) ns w(DATAIN) 3 t Risingtime,DATAIN 1.00 3.00 ns r(DATAIN) 4 t Fallingtime,DATAIN 1.00 3.00 ns f(DATAIN) (1) P=L3_CLK(PRU-ICSSocpclock)period. Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 223 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 1 2 4 3 DATAIN Figure7-100.PRU-ICSSPRUShiftInTiming Table7-99.PRU-ICSSPRUSwitchingRequirements-ShiftOutMode (seeFigure7-101) NO. MIN MAX UNIT 1 t Cycletime,CLOCKOUT 10.00 ns c(CLOCKOUT) 2 t Pulsewidth,CLOCKOUT 0.45×P(1) 0.55×P(1) ns w(CLOCKOUT) 5 t Delaytime,CLOCKOUTtoDATAOUTvalid 0.00 3.00 ns d(CLOCKOUT-DATAOUT) (1) P=L3_CLK(PRU-ICSSocpclock)period. 1 2 CLOCKOUT DATAOUT 5 6 Figure7-101.PRU-ICSSPRUShiftOutTiming 7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT) Table7-100.PRU-ICSSECATTimingConditions PARAMETER MIN MAX UNIT OutputCondition C Capacitiveloadforeachbusline 30 pF load 7.14.2.1 PRU-ICSSECATElectricalDataandTiming Table7-101.PRU-ICSSECATTimingRequirements –InputValidatedWithLATCH_IN (seeFigure7-102) NO. MIN MAX UNIT 1 t Pulsewidth,EDIO_LATCH_IN 100.00 ns w(EDIO_LATCH_IN) 2 t Risingtime,EDIO_LATCH_IN 1.00 3.00 ns r(EDIO_LATCH_IN) 3 t Fallingtime,EDIO_LATCH_IN 1.00 3.00 ns f(EDIO_LATCH_IN) t Setuptime,EDIO_DATA_INvalidbeforeEDIO_LATCH_IN 4 su(EDIO_DATA_IN- 20.00 ns activeedge EDIO_LATCH_IN) t Holdtime,EDIO_DATA_INvalidafterEDIO_LATCH_INactive 5 h(EDIO_LATCH_IN- 20.00 ns edge EDIO_DATA_IN) t Risingtime,EDIO_DATA_IN 1.00 3.00 ns r(EDIO_DATA_IN) 6 t Fallingtime,EDIO_DATA_IN 1.00 3.00 ns f(EDIO_DATA_IN) 224 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 2 3 EDIO_LATCH_IN 1 4 5 EDIO_DATA_IN[7:0] 6 Figure7-102.PRU-ICSSECATInputValidatedWithLATCH_INTiming Table7-102.PRU-ICSSECATTimingRequirements –InputValidatedWithSYNCx (seeFigure7-103) NO. MIN MAX UNIT 1 t Pulsewidth,EDC_SYNCx_OUT 100.00 ns w(EDC_SYNCx_OUT) 2 t Risingtime,EDC_SYNCx_OUT 1.00 3.00 ns r(EDC_SYNCx_OUT) 3 t Fallingtime,EDC_SYNCx_OUT 1.00 3.00 ns f(EDC_SYNCx_OUT) t Setuptime,EDIO_DATA_INvalidbefore 4 su(EDIO_DATA_IN- 20.00 ns EDC_SYNCx_OUTactiveedge EDC_SYNCx_OUT) t Holdtime,EDIO_DATA_INvalidafterEDC_SYNCx_OUT 5 h(EDC_SYNCx_OUT- 20.00 ns activeedge EDIO_DATA_IN) t Risingtime,EDIO_DATA_IN 1.00 3.00 ns r(EDIO_DATA_IN) 6 t Fallingtime,EDIO_DATA_IN 1.00 3.00 ns f(EDIO_DATA_IN) 2 3 EDC_SYNCx_OUT 1 4 5 EDIO_DATA_IN[7:0] 6 Figure7-103.PRU-ICSSECATInputValidatedWithSYNCxTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 225 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table7-103. PRU-ICSSECATTimingRequirements –InputValidatedWithStartofFrame(SOF) (seeFigure7-104) NO. MIN MAX UNIT 1 t Pulseduration,EDIO_SOF 4×P(1) 5×P(1) ns w(EDIO_SOF) 2 t Risingtime,EDIO_SOF 1.00 3.00 ns r(EDIO_SOF) 3 t Fallingtime,EDIO_SOF 1.00 3.00 ns f(EDIO_SOF) t Setuptime,EDIO_DATA_INvalidbeforeEDIO_SOF 4 su(EDIO_DATA_IN- 20.00 ns activeedge EDIO_SOF) Holdtime,EDIO_DATA_INvalidafterEDIO_SOFactive 5 t 20.00 ns h(EDIO_SOF-EDIO_DATA_IN) edge t Risingtime,EDIO_DATA_IN 1.00 3.00 ns r(EDIO_DATA_IN) 6 t Fallingtime,EDIO_DATA_IN 1.00 3.00 ns f(EDIO_DATA_IN) (1) P=PRU-ICSSIEPclocksourceperiod. 2 3 EDIO_SOF 1 4 5 EDIO_DATA_IN[7:0] 6 Figure7-104.PRU-ICSSECATInputValidatedWithSOF Table7-104.PRU-ICSSECATTimingRequirements-LATCHx_IN (seeFigure7-105) NO. MIN MAX UNIT 1 t Pulseduration,EDC_LATCHx_IN 3×P(1) ns w(EDC_LATCHx_IN) 2 t Risingtime,EDC_LATCHx_IN 1.00 3.00 ns r(EDC_LATCHx_IN) 3 t Fallingtime,EDC_LATCHx_IN 1.00 3.00 ns f(EDC_LATCHx_IN) (1) P=PRU-ICSSIEPclocksourceperiod. 2 3 EDC_LATCHx_IN 1 Figure7-105.PRU-ICSSECATLATCHx_INTiming 226 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-105.PRU-ICSSECATSwitchingRequirements-DigitalI/Os NO. PARAMETER MIN MAX UNIT 1 t Pulseduration,EDIO_OUTVALID 14×P(1) 32×P(1) ns w(EDIO_OUTVALID) 4 td(EDIO_OUTVALID- Delaytime,EDIO_OUTVALIDtoEDIO_DATA_OUT 0.00 18×P(1) ns EDIO_DATA_OUT) 7 t EDIO_DATA_OUTskew 8.00 ns sk(EDIO_DATA_OUT) (1) P=PRU-ICSSIEPclocksourceperiod. 7.14.3 PRU-ICSS MII_RT and Switch Table7-106.PRU-ICSSMII_RTSwitchTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 1(1) 3(1) ns R t Inputsignalfalltime 1(1) 3(1) ns F OutputCondition C Outputloadcapacitance 3 20 pF LOAD (1) Exceptwhenspecifiedotherwise. 7.14.3.1 PRU-ICSSMDIOElectricalDataandTiming Table7-107.PRU-ICSSMDIOTimingRequirements –MDIO_DATA (seeFigure7-106) NO. MIN TYP MAX UNIT 1 t Setuptime,MDIOvalidbeforeMDChigh 90 ns su(MDIO-MDC) 2 t Holdtime,MDIOvalidfromMDChigh 0 ns h(MDIO-MDC) 1 2 MDIO_CLK (Output) MDIO_DATA(Input) Figure7-106.PRU-ICSSMDIO_DATATiming-InputMode Table7-108.PRU-ICSSMDIOSwitchingCharacteristics-MDIO_CLK (seeFigure7-107) NO. PARAMETER MIN TYP MAX UNIT 1 t Cycletime,MDC 400 ns c(MDC) 2 t Pulseduration,MDChigh 160 ns w(MDCH) 3 t Pulseduration,MDClow 160 ns w(MDCL) 1 2 3 MDIO_CLK Figure7-107.PRU-ICSSMDIO_CLKTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 227 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table7-109.PRU-ICSSMDIOSwitchingCharacteristics – MDIO_DATA (seeFigure7-108) NO. MIN TYP MAX UNIT 1 t Delaytime,MDChightoMDIOvalid -150 150 ns d(MDC-MDIO) 1 MDIO_CLK (Output) MDIO_DATA(Output) Figure7-108.PRU-ICSSMDIO_DATATiming –OutputMode 7.14.3.2 PRU-ICSSMII_RTElectricalDataandTiming NOTE In order to guarantee the MII_RT I/O timing values published in the device data manual, the PRUocp_clkclockmustbeconfiguredfor200MHz(defaultvalue)andtheTX_CLK_DELAY bitfieldinthePRUSS_MII_RT_TXCFG0/1registermustbeconfiguredasfollows: • 100Mbpsmode:6h(non-defaultvalue) • 10Mbpsmode:0h(value) Table7-110.PRU-ICSSMII_RTTimingRequirements – MII_RXCLK (seeFigure7-109) 10Mbps 100Mbps NO. UNIT MIN TYP MAX MIN TYP MAX 1 t Cycletime,RX_CLK 399.96 400.04 39.996 40.004 ns c(RX_CLK) 2 t Pulseduration,RX_CLKhigh 140 260 14 26 ns w(RX_CLKH) 3 t Pulseduration,RX_CLKlow 140 260 14 26 ns w(RX_CLKL) 4 t Transitiontime,RX_CLK 3 3 ns t(RX_CLK) 1 4 2 3 MII_RXCLK 4 Figure7-109.PRU-ICSSMII_RXCLKTiming 228 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-111.PRU-ICSSMII_RTTimingRequirements-MII[x]_TXCLK (seeFigure7-110) 10Mbps 100Mbps NO. UNIT MIN TYP MAX MIN TYP MAX 1 t Cycletime,TX_CLK 399.96 400.04 39.996 40.004 ns c(TX_CLK) 2 t Pulseduration,TX_CLKhigh 140 260 14 26 ns w(TX_CLKH) 3 t Pulseduration,TX_CLKlow 140 260 14 26 ns w(TX_CLKL) 4 t Transitiontime,TX_CLK 3 3 ns t(TX_CLK) 1 4 2 3 MII_TXCLK 4 Figure7-110.PRU-ICSSMII_TXCLKTiming Table7-112.PRU-ICSSMII_RTTimingRequirements-MII_RXD[3:0],MII_RXDV,andMII_RXER (seeFigure7-111) 10Mbps 100Mbps NO. UNIT MIN TYP MAX MIN TYP MAX t Setuptime,RXD[3:0]validbeforeRX_CLK su(RXD-RX_CLK) 1 t Setuptime,RX_DVvalidbeforeRX_CLK 8 8 ns su(RX_DV-RX_CLK) t Setuptime,RX_ERvalidbeforeRX_CLK su(RX_ER-RX_CLK) t HoldtimeRXD[3:0]validafterRX_CLK h(RX_CLK-RXD) 2 t HoldtimeRX_DVvalidafterRX_CLK 8 8 ns h(RX_CLK-RX_DV) t HoldtimeRX_ERvalidafterRX_CLK h(RX_CLK-RX_ER) 1 2 MII_MRCLK (Input) MII_RXD[3:0], MII_RXDV, MII_RXER (Inputs) Figure7-111.PRU-ICSSMII_RXD[3:0],MII_RXDV,andMII_RXERTiming Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 229 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com Table7-113.PRU-ICSSMII_RTSwitchingCharacteristics-MII_TXD[3:0]andMII_TXEN (seeFigure7-112) NO 10Mbps 100Mbps UNIT . MIN TYP MAX MIN TYP MAX t Delaytime,TX_CLKhightoTXD[3:0]valid d(TX_CLK-TXD) 1 5 25 5 25 ns t Delaytime,TX_CLKtoTX_ENvalid d(TX_CLK-TX_EN) 1 MII_TXCLK (input) MII_TXD[3:0], MII_TXEN (outputs) Figure7-112.PRU-ICSSMII_TXD[3:0],MII_TXENTiming 7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART) Table7-114.UARTTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 10 ns R t Inputsignalfalltime 10 ns F OutputConditions C Outputloadcapacitance 25 pF LOAD Table7-115.TimingRequirementsforPRU-ICSSUARTReceive (seeFigure7-113) NO. MIN MAX UNIT 3 t Pulseduration,receivestart,stop,databit 0.96U(1) 1.05U(1) ns w(RX) (1) U=UARTbaudtime=1/programmedbaudrate. Table7-116.SwitchingCharacteristicsOverRecommendedOperatingConditionsforPRU-ICSSUART Transmit (seeFigure7-113) NO. PARAMETER MIN MAX UNIT 1 ƒ Maximumprogrammablebaudrate 0 12 MHz baud(baud) 2 t Pulseduration,transmitstart,stop,databit U–2(1) U+2(1) ns w(TX) (1) U=UARTbaudtime=1/programmedbaudrate. 3 2 Start UART_TXD Bit Data Bits 5 4 Start UART_RXD Bit Data Bits Figure7-113.PRU-ICSSUARTTiming 230 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 7.15 Universal Asynchronous Receiver Transmitter (UART) For more information, see the Universal Asynchronous Receiver Transmitter (UART) section of the AM335xandAMIC110SitaraProcessorsTechnicalReferenceManual. 7.15.1 UART Electrical Data and Timing Table7-117.UARTTimingConditions PARAMETER MIN TYP MAX UNIT InputConditions t Inputsignalrisetime 10 ns R t Inputsignalfalltime 10 ns F OutputConditions C Outputloadcapacitance 25 pF LOAD Table7-118.TimingRequirementsforUARTxReceive (seeFigure7-114) NO. MIN MAX UNIT 3 t Pulseduration,receivestart,stop,databit 0.96U(1) 1.05U(1) ns w(RX) (1) U=UARTbaudtime=1/programmedbaudrate. Table7-119. SwitchingCharacteristicsforUARTxTransmit (seeFigure7-114) NO. PARAMETER MIN MAX UNIT 1 ƒ Maximumprogrammablebaudrate 3.6864 MHz baud(baud) 2 t Pulseduration,transmitstart,stop,databit U–2(1) U+2(1) ns w(TX) (1) U=UARTbaudtime=1/programmedbaudrate 2 2 2 Start UARTx_TXD Bit Stop Bit Data Bits 3 3 3 Start UARTx_RXD Bit Stop Bit Data Bits Figure7-114.UARTTimings Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 231 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 7.15.2 UART IrDA Interface TheIrDAmoduleoperatesinthreedifferentmodes: • Slowinfrared(SIR)(≤115.2kbps) • Mediuminfrared(MIR)(0.576Mbpsand1.152Mbps) • Fastinfrared(FIR)(4Mbps). Figure 7-115 shows the UART IrDA pulse parameters. Table 7-120 and Table 7-121 list the signaling ratesandpulsedurationsforUARTIrDAreceiveandtransmitmodes. Pulse Duration Pulse Duration 50% 50% 50% Figure7-115.UARTIrDAPulseParameters Table7-120.UARTIrDA—SignalingRateandPulseDuration—ReceiveMode ELECTRICALPULSEDURATION SIGNALINGRATE UNIT MIN MAX SIR 2.4kbps 1.41 88.55 µs 9.6kbps 1.41 22.13 µs 19.2kbps 1.41 11.07 µs 38.4kbps 1.41 5.96 µs 57.6kbps 1.41 4.34 µs 115.2kbps 1.41 2.23 µs MIR 0.576Mbps 297.2 518.8 ns 1.152Mbps 149.6 258.4 ns FIR 4Mbps(singlepulse) 67 164 ns 4Mbps(doublepulse) 190 289 ns 232 PeripheralInformationandTimings Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Table7-121.UARTIrDA—SignalingRateandPulseDuration—TransmitMode ELECTRICALPULSEDURATION SIGNALINGRATE UNIT MIN MAX SIR 2.4kbps 78.1 78.1 µs 9.6kbps 19.5 19.5 µs 19.2kbps 9.75 9.75 µs 38.4kbps 4.87 4.87 µs 57.6kbps 3.25 3.25 µs 115.2kbps 1.62 1.62 µs MIR 0.576Mbps 414 419 ns 1.152Mbps 206 211 ns FIR 4Mbps(singlepulse) 123 128 ns 4Mbps(doublepulse) 248 253 ns Copyright©2011–2020,TexasInstrumentsIncorporated PeripheralInformationandTimings 233 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 8 Device and Documentation Support 8.1 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, XAM3358AZCE). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). Devicedevelopmentevolutionaryflow: X Experimental device that is not necessarily representative of the final device's electrical specificationsandmaynotuseproductionassemblyflow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet finalelectricalspecifications. null Productionversionofthesilicondiethatisfullyqualified. Supporttooldevelopmentevolutionaryflow: TMDX Development-support product that has not yet completed Texas Instruments internal qualificationtesting. TMDS Fully-qualifieddevelopment-supportproduct. XandPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." Production devices and TMDS development-support tools have been characterized fully, and the quality andreliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZCE), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, 27 is 275 MHz). Figure 8-1 providesalegendforreadingthecompletedevicenameforanyAM335xdevice. For orderable part numbers of AM335x devices in the ZCE and ZCZ package types, see the Package OptionAddendumofthisdocument, ti.com,orcontactyourTIsalesrepresentative. For additional description of the device nomenclature markings on the die, see the AM335x Sitara ProcessorsSiliconErrata. 234 DeviceandDocumentationSupport Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 X AM3358 B ZCZ ( ) ( ) ( ) PREFIX CARRIER TYPE X = Experimental device Blank =Tray Blank = Qualified device R =Tape and Reel DEVICE(A) DEVICE SPEED RANGE ARM Cortex-A8 MPU: 27 = 275-MHz Cortex-A8 AM3351 30 = 300-MHz Cortex-A8 AM3352 50 =500-MHzCortex-A8 AM3354 60= 600-MHzCortex-A8 AM3356 72= 720-MHzCortex-A8 AM3357 80 = 800-MHz Cortex-A8 AM3358 100 = 1-GHz Cortex-A8 AM3359 TEMPERATURE RANGE DEVICE REVISION CODE Blank = 0°C to 90°C (commercial junction temperature) Blank = silicon revision 1.0 A= -40°C to 105°C (extended junction temperature) A= silicon revision 2.0 D = -40°C to 90°C (industrial junction temperature) B = silicon revision 2.1 T= -40°C to 125°C (industrial extended junction temperature) PACKAGE TYPE(B) ZCE = 298-pin plastic BGA, with Pb-Free solder balls ZCZ = 324-pin plastic BGA, with Pb-Free solder balls A. TheAM3358deviceshowninthisdevicenomenclatureexampleisoneofseveralvalidpartnumbersfortheAM335x familyofdevices.Fororderabledevicepartnumbers,seethePackageOptionAddendumofthisdocument. B. BGA=Ballgridarray Figure8-1.AM335xDeviceNomenclature 8.2 Tools and Software TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,generatecode,anddevelopsolutionsarelistedbelow. DesignKitsandEvaluationModules AM335xEvaluationModule Enables developers to immediately start evaluating the AM335x processor family (AM3351, AM3352, AM3354, AM3356, AM3358) and begin building applications such asportablenavigation,portablegaming,home/buildingautomationandothers. AM335xStarterKit Provides a stable and affordable platform to quickly start evaluation of Sitara ARM Cortex-A8 AM335x Processors (AM3351, AM3352, AM3354, AM3356, AM3358) and accelerate development for smart appliance, industrial and networking applications. It is a low-cost development platform based on the ARM Cortex-A8 processor that is integrated withoptionssuchasDualGigabitEthernet,DDR3andLCDtouchscreen. BeagleBoneBlackDevelopmentBoard Low-cost, open source, community-supported development platform for ARM Cortex-A8 processor developers and hobbyists. Boot Linux in under 10- seconds and get started on Sitara AM335x ARM Cortex-A8 processor development in less than5minuteswithjustasingleUSBcable. BeagleBoneDevelopmentBoard Low-cost, community-supported development platform for ARM Cortex-A8 processor developers. Boot Linux in under 10-seconds and get started on Sitara AM335x ARM Cortex-A8 processor development in less than 5 minutes with just a single USB cable. For TI-supported hardware platforms, consider the Sitara ARM AM335x Starter KitorAM335xEvaluationModule. DataConcentratorEvaluationModule Based on AM3359 as the main processor and has Power Line Communication (PLC) Module to support various OFDM PLC communication standards. TMDSDC3359 also has capability to support multiple interfaces, sub-1GHz and 2.4GHz RF, Ethernet, RS-232, and RS-485. This evaluation module is ideal development platform for smart grid infrastructure applications including data concentrator, convergent node of grid sensornetwork,andcontrolequipmentofpowerautomation. WiLink™8DualBand2.4 &5GHzWi-Fi®+Bluetooth® COM8EvaluationModule Enables customers to add both Wi-Fi and Bluetooth to home and building automation, smart energy, gateways, wireless audio, enterprise, wearables and many more industrial and Internet of Things (IoT) applications. TI’s WiLink 8 modules are certified and offer high throughput and extended range along with Wi-Fi and Bluetooth coexistence in a power-optimized design. Drivers for the Linux and Android high-level operating systems (HLOSs) are available free of charge Copyright©2011–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 235 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com fromTIfortheSitaraAM335xmicroprocessor(LinuxandAndroidversionrestrictionsapply). WiLink8Module2.4GHzWiFi+BluetoothCOM8EvaluationModule Enables customers to add Wi-Fi and Bluetooth (WL183x module only) to embedded applications based on TI's Sitara microprocessors. TI’s WiLink 8 Wi-Fi + Bluetooth modules are pre-certified and offer high throughput and extended range along with Wi-Fi and Bluetooth coexistence (WL183x modules only) in a power-optimized design. Drivers for the Linux and Android high-level operating systems (HLOSs) are available free of charge from TI for the Sitara AM335x microprocessor(LinuxandAndroidversionrestrictionsapply). TIDesigns EtherCATCommunicationsDevelopmentPlatform Allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance. PROFIBUSCommunicationsDevelopmentPlatform Allows designers to implement PROFIBUS communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance. Ethernet/IPCommunicationsDevelopmentPlatform Allows designers to mplement Ethernet/IP communications standards in a broad range of industrial automation equipment. It enables low foot print designs in applications such as industrial automation, factory automation or industrial communication with minimal external components and with best in class low power performance. AcontisEtherCATMasterStackReferenceDesign Highly portable software stack that can be used on various embedded platforms. The EC-Master supports the high performane TI Sitara MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to implement EtherCAT communication interface boards, EtherCAT based PLC or motion control applications. The EC-Master architectural design does not require additional tasks to be scheduled, thus the full stack functionality is available even on an OS less platform such as TI Starterware suported on AM335x. Due to this architecture combined with the high speed Ethernet driver it is possible to implement EtherCAT master based applications on the Sitara platformwithshortcycletimesof100microsecondsorevenbelow. SolarInverterGatewayDevelopmentPlatformReferenceDesign Adds communication functions to solar energy generation systems to enable system monitoring, real-time feedback, system updates, and more. The TIDEP0044 reference design describes the implementation of a solar inverter gateway using display, Ethernet, USB, and CAN on the TMDXEVM3358 featuringTI'sAM335xprocessor. G3PowerLineCommunicationsDataConcentratoronBeagleBoneBlackPlatform Offers a simplifiedapproachforevaluatingG3-PLCutilizingBeagleBoneBlackpoweredbytheSitara AM335x processor. Users can establish a G3-PLC network with one service node. Single phasecouplingissupported. IEC61850DemonstrationofSubstationBayControlleronBeagleboneCapeandStarterKit Low- cost, simplified implementation of an IEC 61850 Substation Bay Controller is demonstrated by running the Triangle MicroWorks IEC 61850 stack efficiently on the TI AM335X platform with a Linux target layer definition. Many different substation automation applications can be builtontopoftheAM335Xplatformand61850stackdemonstration. 236 DeviceandDocumentationSupport Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 PRUReal-TimeI/OEvaluationReferenceDesign BeagleBone Black add-on board that allows users get to know TI’s powerful Programmable Real-Time Unit (PRU) core and basic functionality. The PRU is a low-latency microcontroller subsystem integrated in the Sitara AM335x and AM437x family of devices. The PRU core is optimized for deterministic, real-time processing, direct access to I/Os and ultra-low-latency requirements. With LEDs and push buttons for GPIO,audio,atempsensor,optionalcharacterdisplayandmore,this add-on board includes schematics, bill of materials (BOM), design files, and design guide to teach the basics of the PRU. SmartHomeandEnergyGatewayReferenceDesign Provides example implementation for measurement, management and communication of energy systems for smart homes and buildings. This example design is a bridge between different communication interfaces, such as WiFi, Ethernet, ZigBee or Bluetooth, that are commonly found in residential and commercial buildings. Since objects in the house and buildings are becoming more and more connected, the gateway design needs to be flexible to accommodate different RF standard, since no single RF standard is dominating the market. This example gateway addresses this problem by supporting existing legacy RF standards (WiFi, Bluetooth) and newerRFstandards(ZigBee,BLE). StreamingAudioReferenceDesign Minimizes design time for customers by offering small form factor hardware and major software components, including streaming protocols and internet radio services. With this reference design, TI offers a quick and easy transition path to the AM335x and WiLink8 platform solution. This proven combo solution provides key advantagesinthismarketcategorythathelpsbringyourproductstothenextlevel. Software ProcessorSDKforAM335XSitaraProcessors-LinuxandTI-RTOSSupport Unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and migrate software across devices. Developing scalable platform solutions has never been easier than with the Processor SDK andTI’sembeddedprocessorsolutions. G3DataConcentratorPower-LineCommunicationModem G3-PLC standard for narrowband OFDM Power Line Communications. The data concentrator solution is designed for the head-end systems which communicate with the end meters (“service node”) in the neighborhood area network. PRIMEDataConcentratorPower-LineCommunicationModem PRIME standard for narrowband OFDM Power Line Communications. The data concentrator solution is designed for the head-end systems which communicate with the end meters (“service node”) in the neighborhoodareanetwork. TIDual-ModeBluetoothStack Comprised of Single-Mode and Dual-Mode offerings implementing the Bluetooth 4.0 specification. The Bluetooth stack is fully Bluetooth Special Interest Group (SIG) qualified, certified and royalty-free, provides simple command line sample applications tospeeddevelopment,anduponrequesthasMFIcapability. CryptographyforTIDevices Enables encryption, crypto for TI devices. These files contain only cryptographic modules that were part of a TI software release. For the complete software release please search ti.com for your device part number, and download the Software DevelopmentKit(SDK). Copyright©2011–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 237 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com DevelopmentTools ClockTreeToolforSitaraARM Processors Interactive clock tree configuration software that provides informationabouttheclocksandmodulesinSitaradevices. Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM Processors Integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich developmentenvironmentforembeddeddevelopers. PinMuxTool Provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDK) or used to configure customer's custom software. Version 3 of the Pin Mux utility adds the capability of automaticallyselectingamuxconfigurationthatsatisfiestheenteredrequirements. PowerEstimationTool(PET) Provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniquescanbeappliedtofurtherreduceoverallpowerconsumption. Uniflash Standalone Flash Tool for TI Microcontrollers (MCU), Sitara Processors and SimpleLink devices Programs on-chip flash memory on TI MCUs and onboard flash memory for Sitara processors. Uniflash has a GUI, command line, and scripting interface. CCS Uniflash is availablefreeofcharge. XDS200USBDebugProbe Connects to the target board via a TI 20-pin connector (with multiple adapters for TI 14-pin, ARM 10-pin and ARM 20-pin) and to the host PC via USB2.0 High Speed (480Mbps). It also requires a license of Code Composer Studio IDE running on the hostPC. XDS560v2SystemTraceUSBandEthernetDebugProbe Adds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an EmbeddedTraceBuffer(ETB). XDS560v2SystemTraceUSBDebugProbe Adds system pin trace in its large external memory buffer. Available for selected TI devices, this external memory buffer captures device-level information that allows obtaining accurate bus performance activity and throughput, as well as power management of core and peripherals. Also, all XDS debug probes support Core and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer (ETB). 238 DeviceandDocumentationSupport Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Models AM335xZCEIBISModel ZCEpackageIBISmodel AM335xZCZIBISModel ZCZpackageIBISmodel AM335xZCERev.2.1BSDLModel ZCE package BSDL model for the revision 2.1 TI F781962A Fixed- andFloating-PointDSPwithBoundaryScan AM335xZCZRev.2.1BSDLModel ZCZ package BSDL model for the revision 2.1 TI F781962A Fixed- andFloating-PointDSPwithBoundaryScan 8.3 Documentation Support To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperrightcorner,click on Alert me to register and receive a weekly digest of any product information that haschanged.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. The current documentation that describes the processor, related peripherals, and other technical collateral islistedbelow. Errata AM335xSitaraProcessorsSiliconErrata Describes the known exceptions to the functional specifications for the AM335x Sitara Processors. ApplicationReports Processor SDK RTOS Customization: Modifying Board Library to Change UART Instance on AM335x Describes the procedure to modify the default UART0 example in the AM335x Processor SDK RTOS package to enable UART1. On the BeagleBone Black (BBB) P9 header, pins 24(TX) and 26(RX) are connected to UART1. This procedure shows a test to verify that UART1isenabledontheBBB. High-SpeedLayoutGuidelinesAs modern bus interface frequencies scale higher, care must be taken in theprintedcircuitboard(PCB)layoutphaseofadesigntoensurearobustsolution. AM335xReliabilityConsiderationsinPLCApplicationsProgrammable Logic Controllers (PLC) are used as the main control in an automation system with high- reliability expectations and long life in harsh environments. Processors used in these applications require an assessment of performance verses expected power on hours to achieve the optimal performance for the application. AM335xThermalConsiderationsDiscusses the thermal considerations of the AM335x devices. It offers guidance on analysis of the processor's thermal performance, suggests improvements for an end system to aid in overcoming some of the existing challenges of producing a good thermal design, and provides real power/thermal data measured with AM335x EVMs for user evaluation. User'sGuides TPS65910AxUser'sGuideforAM335xProcessorsUser'sGuide A reference for connectivity between theTPS65910Axpower-managementintegratedcircuit(PMIC)andtheAM335xprocessor. AM335xandAMIC110SitaraProcessorsTechnicalReferenceManual Details the integration, the environment, the functional description, and the programming modelsforeachperipheralandsubsysteminthedevice. G3PowerLineCommunicationsDataConcentratoronBeagleBoneBlackPlatformDesignGuide Provide the foundation that you need including methodology, testing, and design files to quickly evaluate and customize the system. TI Designs help you accelerate your time to market. PoweringtheAM335xwiththeTPS65217x A reference for connectivity between the TPS65217 power managementICandtheAM335xprocessor. PoweringtheAM335xWiththeTPS650250 Details a power solution for the AM335x application processor with a TPS650250 Power Management Unit (PMU) or Power Management IC (PMIC). Copyright©2011–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 239 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com SelectionandSolutionGuides ConnectedSensorsBuildingAutomationSystemsGuide The use of connected sensors has a wide range of uses in building automation applications, from monitoring human safety and security, controlling the environment and ambience specified by the comfort preferences of the end user, or either periodic or continuous data logging of environmental and system data todetectirregularsystemconditions. WhitePapers BuildingAutomationforEnhancedEnergyAndOperationalEfficiency Discusses building automation solutions, focusing on aspects of the Building Control System. TI’s Sitara processors facilitate intelligent automation of the control systems. The scalable Sitara processor portfolio offers an opportunity to build a platform solution that also spans beyond Building Control Systems. POWERLINKonTISitaraProcessors Supports Ethernet standard features such as cross-traffic, hot- plugging and different types of network configurations such as star, ring and mixed topologies. EtherNet/IPonTI'sSitaraAM335xProcessors EtherNet/IP™ (EtherNet/Industrial Protocol) is an industrial automation networking protocol based on the IEEE 802.3 Ethernet standard that hasdominatedtheworldofITnetworkingforthepastthreedecades. PROFINETonTI’sSitaraAM335xProcessors To integrate PROFINET into the Sitara AM335x processor, TI has built upon its programmable realtime unit (PRU) technology to create an industrialcommunicationsub-system(ICSS). ProfibusonAM335xandAM1810SitaraARMMicroprocessor PROFIBUS, one of the most used communication technologies, is installed in more than 35 million industrial nodes worldwide andisgrowingatarateofapproximately10percenteachyear. EtherCATonSitaraAM335xARMCortex-A8Microprocessors Emerging real-time industrial Ethernet standard for industrial automation applications, such as input/output (I/O) devices, sensors andprogrammablelogiccontrollers(PLCs). MainlineLinuxEnsuresStabilityandInnovation Enabling and empowering the rapid development of new functionality starts at the foundational level of the system’s software environment – that is,attheleveloftheLinuxkernel– andbuildsupwardfromthere. CompleteSolutionsforNext-GenerationWirelessConnectedAudio Robust, feature-rich and high- performanceconnectivitytechnologyforWi-FiandBluetooth. DataConcentrators:TheCoreofEnergyandDataManagement With a large install base, it is essential to establish an automated metering infrastructure (AMI). With automated meter reading (AMR) measurement, the communication of meter data to the central billing station willbeseamless. LinaroSpeedsDevelopmentinTILinuxSDKs Linaro’s software is not a Linux distribution; in fact, it is distribution neutral. The focus of the organization’s 120 engineers is on optimizing base-level open-source software in areas that interact directly with the silicon such as multimedia, graphics,powermanagement,theLinuxkernelandbootingprocesses. GettingStartedonTIARMEmbeddedProcessorDevelopment Beginning with an overview of ARM technology and available processor platforms, this paper will then explore the fundamentals of embedded design that influence a system’s architecture and, consequently, impact processorselection. PowerOptimizationTechniquesforEnergy-EfficientSystems The TI Sitara processor solutions offer the flexibility to design application-specific systems. The latest Sitara AM335x processors provideascalablearchitecturewithspeedrangingfrom300MHzto1GHz. TheYoctoProject:ChangingtheWayEmbeddedLinuxSoftwareSolutionsareDeveloped Enabling complex silicon devices such as SoC with operating firmware and application software can be a challenge for equipment manufacturers who often are more comfortable with hardware thansoftwareissues. SmartThermostatsareaCoolAdditiontotheConnectedHome Because of the pervasiveness of residential broadband connectivity and the explosion in options, the key to the connected homeis–connectivity. BeagleBoneLow-CostDevelopmentBoardProvidesaClearPathtoOpen-sourceResources 240 DeviceandDocumentationSupport Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 Ready-to-use open-source hardware platform for rapid prototyping and firmware and softwaredevelopment. EnableSecurityandAmpUpChipPerformanceWithHardware-AcceleratedCryptography Cryptography is one of several techniques or methodologies that are typically implemented in contemporary electronic systems to construct a secure perimeter around a device where informationordigitalcontentisbeingprotected. GestureRecognition:EnablingNaturalInteractionsWithElectronics Enabling humans and machines tointerfacemoreeasilyinthehome,theautomobile,andatwork. DevelopingAndroidApplicationsforARMCortex-A8Cores The flexibility, power, versatility and ubiquity of the Android operating system (OS) and associated ecosystem have been a boon todevelopersofapplicationsforARMprocessorcores. OtherDocuments IndustrialCommunicationwithSitaraAM335xARMCortex-A8Microprocessors The industry’s first low- power ARM Cortex-A8 devices to incorporate multiple industrial communication protocols on a single chip. The six pin-to-pin and software-compatible devices in this generation of processors, along with industrial hardware development tools, software and analogcomplements,provideatotalindustrialsystemsolution. SitaraProcessors Using the ARM Cortex-A series of cores, are optimized system solutions that go beyond the core, delivering products that support rich graphics capabilities, LCD displays andmultipleindustrialprotocols. IndustrialCommunicationwithSitaraAM335xARMCortex-A8Microprocessors Describes the key features and benefits of multiple, on-chip, production-ready industrial Ethernet and field bus communicationprotocolswithmasterandslavefunctionality. Copyright©2011–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 241 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 8.4 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstoordernow. Table8-1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY AM3359 Clickhere Clickhere Clickhere Clickhere Clickhere AM3358 Clickhere Clickhere Clickhere Clickhere Clickhere AM3357 Clickhere Clickhere Clickhere Clickhere Clickhere AM3356 Clickhere Clickhere Clickhere Clickhere Clickhere AM3354 Clickhere Clickhere Clickhere Clickhere Clickhere AM3352 Clickhere Clickhere Clickhere Clickhere Clickhere AM3351 Clickhere Clickhere Clickhere Clickhere Clickhere 8.5 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help youneed. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications anddonotnecessarilyreflectTI'sviews;seeTI's TermsofUse. 242 DeviceandDocumentationSupport Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 www.ti.com SPRS717L–OCTOBER2011–REVISEDMARCH2020 8.6 Trademarks Sitara,SmartReflex,WiLink,E2EaretrademarksofTexasInstruments. NEONisatrademarkofARMLtdoritssubsidiaries. ARM,CortexareregisteredtrademarksofARMLtdoritssubsidiaries. BluetoothisaregisteredtrademarkofBluetoothSIG. EtherCATisaregisteredtrademarkofEtherCATTechnologyGroup. PowerVRSGXisatrademarkofImaginationTechnologiesLimited. LinuxisaregisteredtrademarkofLinusTorvalds. Wi-FiisaregisteredtrademarkofWi-FiAlliance. Allothertrademarksarethepropertyoftheirrespectiveowners. 8.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 8.8 Glossary TIGlossary Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2011–2020,TexasInstrumentsIncorporated DeviceandDocumentationSupport 243 SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

AM3359,AM3358,AM3357,AM3356,AM3354,AM3352,AM3351 SPRS717L–OCTOBER2011–REVISEDMARCH2020 www.ti.com 9 Mechanical, Packaging, and Orderable Information 9.1 Via Channel The ZCE package has been specially engineered with Via Channel technology. This allows larger than normal PCB via and trace sizes and reduced PCB signal layers to be used in a PCB design with the 0.65- mm pitch package, and substantially reduces PCB costs. It allows PCB routing in only two signal layers (fourlayerstotal)duetotheincreasedlayerefficiencyoftheViaChannelBGAtechnology. Via Channel technology implemented on the ZCE package makes it possible to build an AM335x-based product with a 4-layer PCB, but a 4-layer PCB may not meet system performance goals. Therefore, systemperformanceusinga4-layerPCBdesignmustbeevaluatedduringproductdesign. 9.2 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 244 Mechanical,Packaging,andOrderableInformation Copyright©2011–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351

PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2019 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) AM3351BZCE30 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3351BZCE30 & no Sb/Br) AM3351BZCE30R ACTIVE NFBGA ZCE 298 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3351BZCE30 & no Sb/Br) AM3351BZCE60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3351BZCE60 & no Sb/Br) AM3351BZCE60R ACTIVE NFBGA ZCE 298 1000 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3351BZCE60 & no Sb/Br) AM3351BZCEA30 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3351BZCEA30 & no Sb/Br) AM3351BZCEA30R ACTIVE NFBGA ZCE 298 1000 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3351BZCEA30 & no Sb/Br) AM3351BZCEA60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3351BZCEA60 & no Sb/Br) AM3352BZCE30 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3352BZCE30 & no Sb/Br) AM3352BZCE30R ACTIVE NFBGA ZCE 298 1000 Green (RoHS SNAGCU Level-3-260C-168 HR AM3352BZCE30 & no Sb/Br) AM3352BZCE60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3352BZCE60 & no Sb/Br) AM3352BZCEA30 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCEA30 & no Sb/Br) AM3352BZCEA30R ACTIVE NFBGA ZCE 298 1000 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCEA30 & no Sb/Br) AM3352BZCEA60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCEA60 & no Sb/Br) AM3352BZCEA60R ACTIVE NFBGA ZCE 298 1000 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCEA60 & no Sb/Br) AM3352BZCED30 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3352BZCED30 & no Sb/Br) AM3352BZCED60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3352BZCED60 & no Sb/Br) AM3352BZCZ100 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3352BZCZ100 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2019 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) AM3352BZCZ30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3352BZCZ30 & no Sb/Br) AM3352BZCZ60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3352BZCZ60 & no Sb/Br) AM3352BZCZ80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3352BZCZ80 & no Sb/Br) AM3352BZCZA100 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCZA100 & no Sb/Br) AM3352BZCZA30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCZA30 & no Sb/Br) AM3352BZCZA60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCZA60 & no Sb/Br) AM3352BZCZA80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3352BZCZA80 & no Sb/Br) AM3352BZCZD30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3352BZCZD30 & no Sb/Br) AM3352BZCZD60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3352BZCZD60 & no Sb/Br) AM3352BZCZD80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3352BZCZD80 & no Sb/Br) AM3352BZCZT60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 AM3352BZCZT60 & no Sb/Br) AM3352BZCZT60R ACTIVE NFBGA ZCZ 324 1000 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 AM3352BZCZT60 & no Sb/Br) AM3354BZCE60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3354BZCE60 & no Sb/Br) AM3354BZCEA60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3354BZCEA60 & no Sb/Br) AM3354BZCED60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3354BZCED60 & no Sb/Br) AM3354BZCZ100 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3354BZCZ100 & no Sb/Br) AM3354BZCZ30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3354BZCZ30 & no Sb/Br) AM3354BZCZ60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3354BZCZ60 & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2019 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) AM3354BZCZ80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3354BZCZ80 & no Sb/Br) AM3354BZCZA100 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3354BZCZA100 & no Sb/Br) AM3354BZCZA60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3354BZCZA60 & no Sb/Br) AM3354BZCZA80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3354BZCZA80 & no Sb/Br) AM3354BZCZA80R ACTIVE NFBGA ZCZ 324 1000 Green (RoHS SNAGCU Level-3-260C-168 HR AM3354BZCZA80 & no Sb/Br) AM3354BZCZD60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3354BZCZD60 & no Sb/Br) AM3354BZCZD80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3354BZCZD80 & no Sb/Br) AM3356BZCEA60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR AM3356BZCEA60 & no Sb/Br) AM3356BZCZ30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3356BZCZ30 & no Sb/Br) AM3356BZCZ60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3356BZCZ60 & no Sb/Br) AM3356BZCZ80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3356BZCZ80 & no Sb/Br) AM3356BZCZA30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3356BZCZA30 & no Sb/Br) AM3356BZCZA60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3356BZCZA60 & no Sb/Br) AM3356BZCZA80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3356BZCZA80 & no Sb/Br) AM3356BZCZD30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3356BZCZD30 & no Sb/Br) AM3356BZCZD60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3356BZCZD60 & no Sb/Br) AM3357BZCZA30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3357BZCZA30 & no Sb/Br) AM3357BZCZA60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3357BZCZA60 & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2019 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) AM3357BZCZA80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3357BZCZA80 & no Sb/Br) AM3357BZCZD30 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3357BZCZD30 & no Sb/Br) AM3357BZCZD60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 90 AM3357BZCZD60 & no Sb/Br) AM3358BZCE60 ACTIVE NFBGA ZCE 298 160 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3358BZCE60 & no Sb/Br) AM3358BZCZ100 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3358BZCZ100 & no Sb/Br) AM3358BZCZ60 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3358BZCZ60 & no Sb/Br) AM3358BZCZ80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR 0 to 90 AM3358BZCZ80 & no Sb/Br) AM3358BZCZA100 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3358BZCZA100 & no Sb/Br) AM3358BZCZA80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3358BZCZA80 & no Sb/Br) AM3359BZCZA80 ACTIVE NFBGA ZCZ 324 126 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 AM3359BZCZA80 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2019 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF AM3358 : •Enhanced Product: AM3358-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 5

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