DATASHEET X9252 FN8167 Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface Quad Rev 3.00 Digitally-Controlled (XDCP™) Potentiometer July 24, 2014 The X9252 integrates 4 digitally controlled potentiometers Features (XDCP) on a monolithic CMOS integrated circuit. • Quad Solid State Potentiometer The digitally controlled potentiometers are implemented • 256 Wiper Tap Points-0.4% Resolution using 255 resistive elements in a series array. Between each pair of elements are tap points connected to wiper terminals • 2-Wire Serial Interface for Write, Read, and Transfer through switches. The position of each wiper on the array is Operations of the Potentiometer controlled by the user through the Up/Down (U/D) or 2-wire • Up/Down Interface for Individual Potentiometers bus interface. The wiper of each potentiometer has an associated volatile Wiper Counter Register (WCR) and four • Wiper Resistance: 40 Typical nonvolatile Data Registers (DRs) that can be directly written • NonVolatile Storage of Wiper Positions to and read by the user. The contents of the WCR controls • Power On Recall. Loads Saved Wiper Position on the position of the wiper on the resistor array through the Power-Up. switches. At power-up, the device recalls the contents of the default data registers DR00, DR10, DR20, DR30, to the • Standby Current < 100µA Max corresponding WCR. • Maximum Wiper Current: 3mA Each DCP can be used as a three-terminal potentiometer or • VCC: 2.7V to 5.5V Operation as a two terminal variable resistor in a wide variety of • 2.8k and 10k Version of Total Pot Resistance applications including the programming of bias voltages, the implementation of ladder networks, and three resistor • Endurance: 100,000 Data Changes per Bit per Register programmable networks. • 100 yr. Data Retention • 24 Ld TSSOP • Pb-Free (RoHS Compliant) Pinout X9252 (24 LD TSSOP) TOP VIEW DS0 1 24 DS1 A0 2 23 SCL RW3 3 22 RL2 RH3 4 21 RH2 RL3 5 20 RW2 U/D 6 19 CS VCC 7 18 VSS RL0 8 17 RW1 RH0 9 16 RH1 RW0 10 15 RL1 A2 11 14 A1 WP 12 13 SDA FN8167 Rev 3.00 Page 1 of 19 July 24, 2014

X9252 Ordering Information PART NUMBER PART RTOTAL TEMP RANGE PACKAGE PKG. (Notes1, 2) MARKING (k) (°C) (Pb-free) DWG. # X9252YV24IZ-2.7 X9252YV ZG 2.8 -40 to +85 24 Ld TSSOP (4.4mm) M24.173 X9252WV24IZ-2.7 X9252WV ZG 10 -40 to +85 24 Ld TSSOP (4.4mm) M24.173 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for X9252. For more information on MSL please see tech brief TB363 Functional Diagram VCC RH0 RH1 RH2 RH3 A2 2-Wire A1 Interface WCR0 DCP0 WCR1 DCP1 WCR2 DCP2 WCR3 DCP3 A0 DR00 DR10 DR20 DR30 DR01 DR11 DR21 DR31 SDA POWER-UP, DR02 DR12 DR22 DR32 INTERFACE DR03 DR13 DR23 DR33 SCL CONTROL AND Up-Down STATUS Interface DS0 DS1 CS U/D VSS WP RW0 RL0 RW1 RL1 RW2 RL2 RW3 RL3 Pin Descriptions PIN # SYMBOL DESCRIPTION 1, 24 DS0, DS1 DCP select for Up/Down interface. 2, 14, 11 A0, A1, A2 Device address for 2-wire bus. 3 RW3 Wiper terminal of DCP3. 4 RH3 High terminal of DCP3. 5 RL3 Low terminal of DCP3. 6 U/D Increment/decrement for up/down interface. 7 VCC System supply voltage 8 RL0 Low terminal of DCP0. 9 RH0 High terminal of DCP0. 10 RW0 Wiper terminal of DCP0. 12 WP Hardware write protect 13 SDA Serial data input/output for 2-wire bus. 15 RL1 Low terminal of DCP1. 16 RH1 High terminal of DCP1. 17 RW1 Wiper terminal DCP1. 18 VSS System ground FN8167 Rev 3.00 Page 2 of 19 July 24, 2014

X9252 Pin Descriptions (Continued) PIN # SYMBOL DESCRIPTION 19 CS Chip select for Up/Down interface. 20 RW2 Wiper terminal of DCP2. 21 RH2 High terminal of DCP2. 22 RL2 Low terminal of DCP2. 23 SCL Serial clock for 2-wire bus. Pin Descriptions DCP Select (DS1 and DS0) The DS1 and DS0 select one of the four DCPs for an Up/Down Bus Interface Pins interface operation. Serial Data Input/Output (SDA) Hardware Write Protect Input (WP) The SDA is a bidirectional serial data input/output pin for the 2- When the WP pin is set low, “write” operations to nonvolatile wire interface. It receives device address, operation code, wiper DCP Data Registers are disabled. This includes both 2-wire register address and data from a 2-wire external master device interface nonvolatile “Write”, and Up/Down interface “Store” at the rising edge of the serial clock SCL, and it shifts out data operations. after each falling edge of the serial clock SCL. DCP Pins SDA requires an external pull-up resistor, since it’s an open drain output. RH0, RL0, RH1, RL1, RH2, RL2, RH3, and RL3 Serial Clock (SCL) These pins are equivalent to the terminal connections on mechanical potentiometers. Since there are 4 DCPs, there is This input is the serial clock of the 2-wire and Up/Down interface. one set of RH and RL for each DCP. Device Address (A0, A1, A2) RW0, RW1, RW2, and RW3 The wiper pins are equivalent to the wiper terminal of The Address inputs are used to set the least significant 3 bits of mechanical potentiometers. Since there are four DCPs, there the 8-bit 2-wire interface slave address. A match in the slave address serial data stream must be made with the Address input are 4 RW pins. pins in order to initiate communication with the X9252. A maximum of 8 devices may occupy the 2-wire serial bus. Chip Select (CS) When the CS pin is low, increment or decrement operations are possible using the SCL and U/D pins. The 2-wire interface is disabled at this time. When CS is high, the 2-wire interface is enabled. Up or Down Control (U/D) The U/D input pin is held HIGH during increment operations and held LOW during decrement operations. FN8167 Rev 3.00 Page 3 of 19 July 24, 2014

X9252 Absolute Maximum Ratings Recommended Operating Conditions Junction Temperature Under Bias . . . . . . . . . . . . . .-65C to +135C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Supply Voltage (VCC) (Note6) Limits . . . . . . . . . . . . . .2.7V to 5.5V Voltage at any Digital Interface Pin with Respect to VSS, Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage at any DCP Pin with Respect to VSS . . . . . . . . .-1V to VCC Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . .300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications Across recommended operating conditions unless otherwise stated. Boldface limits apply across the operating temperature range, -40°C to +85°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note12) (Note6) (Note12) UNIT RTOTAL End-to-End Resistance Y, W versions respectively 2.8, 10 k End-to-End Resistance Tolerance -20 +20 % Power Rating +25°C, each DCP 50 mW RTOTAL DCP to DCP Resistance Matching 0.75 2.0 % Matching IW Wiper Current (Note7) See “Test Circuit” on page8 -3.0 +3.0 mA RW Wiper Resistance Wiper current = VCC 50 150  RTOTAL VTERM Voltage on any DCP Pin VSS VCC V Noise (Note7) Ref: 1kHz -120 dBV Resolution 0.4 % Absolute Linearity (Note3) V(RH0) = V(RH1) = V(RH2) = V(RH3) = VCC -1 +1 MI V(RL0) = V(RL1) = V(RL2) = V(RL3) = VSS (Note5) Relative linearity (Note4) -0.3 +0.3 MI (Note5) Temperature coefficient of resistance 300 ppm/C (Note7) Ratiometric Temperature (Note7) -20 +20 ppm/°C Coefficient CH/CL/CW Potentiometer Capacitance (Note7) See “Equivalent Circuit” on page8 10/10/25 pF IOL Leakage on DCP Pins Voltage at pin from VSS to VCC 0.1 10 µA DC Electrical Specifications Across the recommended operating conditions unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C. MIN MAX SYMBOL PARAMETER TEST CONDITIONS (Note12) (Note12) UNITS ICC1 VCC Supply Current (Volatile Write/Read) fSCL = 400kHz; SDA = open; (for 2-wire, active, read 3 mA and volatile write states only) ICC2 VCC Supply Current (Active) fSCL = 200kHz; 3 mA (for U/D interface, increment, decrement) ICC3 VCC Supply Current (Nonvolatile Write) fSCL = 400kHz; SDA = Open; 5 mA (for 2-wire, active, nonvolatile write state only) ISB VCC Current (Standby) VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; 100 µA (for 2-Wire, standby state only) IL Leakage Current, Bus Interface Pins Voltage at pin from VSS to VCC -10 10 µA VIH Input HIGH Voltage VCC x 0.7 VCC + 1 V VIL Input LOW Voltage -1 VCC x 0.3 V VOL SDA Pin Output LOW Voltage IOL = 3mA 0.4 V FN8167 Rev 3.00 Page 4 of 19 July 24, 2014

X9252 Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit Data Retention 100 Years Capacitance Symbol Test Test Conditions Max UNITS CIN/OUT (Note7) Input/Output Capacitance (SDA) VOUT = 0V 8 pF CIN (Note7) Input Capacitance (SCL, WP, DS0, DS1, CS, U/D, A2, A1 and VIN = 0V 6 pF A0) Power-Up Timing SYMBOL PARAMETER MAX UNITS tD (Notes7, 11) Power-Up Delay from VCC Power-Up (VCC above 2.7V) to Wiper Position Recall 2 ms Completed, and Communication Interfaces Ready for Operation. A.C. Test Conditions Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Threshold Level VCC x 0.5 External Load at Pin SDA 2.3k to VCC and 100pF to VSS 2-Wire Interface Timing (s) SYMBOL PARAMETER MIN MAX UNITS fSCL Clock Frequency 400 kHz tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Condition Setup Time 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:STO Stop Condition Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR (Note7) SCL and SDA Rise Time 300 ns tF (Note7) SCL and SDA Fall Time 300 ns tAA (Note7) SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns tIN (Note7) Pulse Width Suppression Time at SCL and SDA inputs 50 ns tBUF (Note7) Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA A0, A1, A2 and WP Setup Time 600 ns (Note7) tHD:WPA A0, A1, A2 and WP Hold Time 600 ns (Note7) FN8167 Rev 3.00 Page 5 of 19 July 24, 2014

X9252 SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) WP, A0, A1, and A2 Pin Timing START STOP SCL Clk 1 SDA IN tSU:WP tHD:WP WP, A0, A1, or A2 Increment/Decrement Timing SYMBOL PARAMETER MIN TYP (Note6) MAX UNITS tCI CS to SCL Setup 600 ns tID (Note7) SCL HIGH to U/D, DS0 or DS1 Change 600 ns tDI (Note7) U/D, DS0 or DS1 to SCL Setup 600 ns tIL SCL LOW Period 2.5 µs tIH SCL HIGH Period 2.5 µs tIC SCL Inactive to CS Inactive (Nonvolatile Store Setup Time) 1 µs tCPHS CS Deselect Time (Store) 10 ms tCPHNS CS Deselect Time (No Store) 1 µs (Note7) tIW (Note7) SCL to RW Change 100 500 µs tCYC SCL Cycle Time 5 µs tR, tF (Note7) SCL Input Rise and Fall Time 500 µs FN8167 Rev 3.00 Page 6 of 19 July 24, 2014

X9252 Increment/Decrement Timing CS tCYC tCI tIL tIH tIC tCPHS tCPHNS 90% 90% SCL 10% tID tDI tF tR U/D DS0, DS1 tIW (3) RW MI High-Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWC Non-Volatile Write Cycle Time 5 10 ms (Notes7, 10) XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRL (Note7) SCL Rising Edge To Wiper Code Changed, Wiper Response Time After Instruction 5 20 µs Issued (All Load Instructions) NOTES: 3. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI V(RW(n)(expected)) = n(V(RH)-V(RL))/255 + V(RL), with n from 0 to 255. 4. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) + MI)]/MI, with n from 0 to 254 5. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/255. 6. Typical values are for TA = +25°C and nominal supply voltage. 7. This parameter is not 100% tested. 8. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2)] x 106, with T1 and T2 being 2 temperatures, and n from 0 to 255. 9. Measured with wiper at tap position 255, RL grounded, using test circuit. 10. tWC is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS of a valid “Store” operation of the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle. 11. The recommended power up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power-up, the data sheet parameters for the DCP do not fully apply until tD after VCC reaches its final value. In order to prevent unwanted tap position changes, or an inadvertant store, bring the CS pin high before or concurrently with the VCC pin on power-up. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN8167 Rev 3.00 Page 7 of 19 July 24, 2014

X9252 Test Circuit Equivalent Circuit RTOTAL TEST POINT RH RL CH CW CL RW FORCE CURRENT RW Principles of Operation Within each individual array only one switch may be turned on at a time. The X9252 is an integrated circuit incorporating four resistor arrays, their associated registers and counters, and the serial These switches are controlled by a Wiper Counter Register interface logic providing direct communication between the (WCR). The 8 bits of the WCR (WCR[7:0]) are decoded to host and the digitally controlled potentiometers. This section select and enable one of 256 switches (see Table1). Note that provides detail description of the following: each wiper has a dedicated WCR. When all bits of a WCR are - Resistor Array zeroes, the switch closest to the corresponding RL pin is selected. When all bits of a WCR are ones, the switch closest - Up/Down Interface to the corresponding RH pin is selected. - 2-wire Interface The WCR is volatile and may be written directly. There are four Resistor Array Description non-volatile Data Registers (DR) associated with each WCR. The X9252 is comprised of four resistor arrays. Each array Each DR can be loaded into WCR. All DRs and WCRs can be contains 255 discrete resistive segments that are connected in read or written. series. The physical ends of each array are equivalent to the Power-Up and Down Requirements fixed terminals of a mechanical potentiometer (RHi and RLi inputs) (see Figure1). During power-up, CS must be high, to avoid inadvertant “store” operations. At power-up, the contents of Data Registers DR00, At both ends of each array and between each resistor segment DR10, DR20, and DR30, are loaded into the corresponding is a switch connected to the wiper (RWi) pin. wiper counter register. i = 0, 1, 2, AND 3 WCR[7:0] 255 FOUR = FF hex RHi VOLATILE NON-VOLATILE 8-BIT 254 DATA WIPER REGISTERS COUNTER DRi0, DRi1, REGISTER 253 DRi2, and WCRi DRi3 252 ONE OF 256 DECODER WP SCL SDA INTERFACE CONTROL AND VOLATILE STATUS REGISTER (SR) A2, A1, A0 2 (SHARED BY THE FOUR DCPs) CS U/D 1 DS1, DS0 WCR[7:0] 0 = 00 hex RLi RWi FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP FN8167 Rev 3.00 Page 8 of 19 July 24, 2014

X9252 Up/Down Interface Operation Mode Selection for Up/Down Control The SCL, U/D, CS, DS0 and DS1 inputs control the movement CS SCL U/D MODE of the wiper along the resistor array. With CS set LOW the L H Wiper Up device is selected and enabled to respond to the U/D and SCL inputs. HIGH-to-LOW transitions on SCL will increment or L L Wiper Down decrement (depending on the state of the U/D input) a wiper H X Store Wiper Position to nonvolatile counter register selected by DS0 and DS1. The output of this memory if WP pin is high. No store, counter is decoded to select one of 256 wiper positions along return to standby, if WP pin is low. the resistor array. H X X Standby The value of the counter is stored in nonvolatile Data Registers L X No Store, Return to Standby DRi0 whenever CS transitions HIGH while the SCL and WP inputs are HIGH. “i” indicates the DCP number selected with L H Wiper Up (not recommended) pins DS1 and DS0. During a “Store” operation bits DRSel1 and L L Wiper Down (not recommended) DRSel0 in the Status Register must be both “0”, which is their power up default value. Other combinations are reserved and must not be used. 2-Wire Serial Interface The system may select the X9252, move the wiper, and Protocol Overview deselect the device without having to store the latest wiper The device supports a bidirectional bus oriented protocol. The position in nonvolatile memory. After the wiper movement is protocol defines any device that sends data onto the bus as a performed as described above and once the new position is transmitter, and the receiving device as the receiver. The reached, the system must keep SCL LOW while taking CS device controlling the transfer is called the master and the HIGH. The new wiper position will be maintained until changed device being controlled is called the slave. The master always by the system or until a power-down/up cycle recalled the initiates data transfers, and provides the clock for both transmit previously stored data. and receive operations. The X9252 operates as a slave in all applications. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system All 2-wire interface operations must begin with a START, operation minor adjustments could be made. The adjustments followed by a Slave Address byte. The Slave Address selects might be based on user preference, system parameter the X9252, and specifies if a Read or Write operation is to be changes due to temperature drift, etc. performed. The state of U/D may be changed while CS remains LOW. This All Communication over the 2-wire interface is conducted by allows the host system to enable the device and then move the sending the MSB of each byte of data first. wiper up and down until the proper trim is attained. The 2-wire Serial Clock and Data interface is disabled while CS remains LOW. Data states on the SDA line can change only while SCL is TABLE 1. DCP SELECTION FOR UP/DOWN CONTROL LOW. The SDA state changes while SCL is HIGH are reserved DS1 DS0 SELECTED DCP for indicating START and STOP conditions 0 0 DCP0 (see Figure2). On power-up of the X9252, the SDA pin is in the input mode. 0 1 DCP1 1 0 DCP2 Serial Start Condition 1 1 DCP3 All commands are preceded by the START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met (see Figure2). Serial Stop Condition All communications must be terminated by a STOP condition, which is a LOW-to-HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus (see Figure2). FN8167 Rev 3.00 Page 9 of 19 July 24, 2014

X9252 SCL SDA START DATA DATA DATA STOP STABLE CHANGE STABLE FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START ACK FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER Serial Acknowledge Slave Address Byte An ACK (Acknowledge), is a software convention used to Following a START condition, the master must output a Slave indicate a successful data transfer. The transmitting device, Address Byte (Figure4). This byte includes three parts: either master or slave, releases the bus after transmitting eight - The four MSBs (SA7-SA4) are the Device Type Identifier, bits. During the ninth clock cycle, the receiver pulls the SDA which must always be set to 0101 in order to select the line LOW to acknowledge the reception of the eight bits of data X9252. (see Figure3). - The next three bits (SA3-SA1) are the Device Address bits The device responds with an ACK after recognition of a START (AS2-AS0). To access any part of the X9252’s memory, the condition followed by a valid Slave Address byte. A valid Slave value of bits AS2, AS1, and AS0 must correspond to the logic levels at pins A2, A1, and A0 respectively. Address byte must contain the Device Type Identifier 0101, and the Device Address bits matching the logic state of pins - The LSB (SA0) is the R/W bit. This bit defines the operation to be performed on the device being addressed. A2, A1, and A0 (see Figure4). When the R/W bit is “1”, then a Read operation is If a write operation is selected, the device responds with an selected. A “0” selects a Write operation. ACK after the receipt of each subsequent eight-bit word. SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. 0 1 0 1 AS2 AS1 AS0 R/W The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to Device Type Device Read or Identifier Address Write place the device into a known state. SLAVE ADDRESS BIT(S) DESCRIPTION SA7-SA4 Device Type Identifier SA3-SA1 Device Address SA0 Read or Write Operation Select FIGURE 4. SLAVE ADDRESS (SA) FORMAT FN8167 Rev 3.00 Page 10 of 19 July 24, 2014

X9252 Nonvolatile Write Acknowledge Polling 2-Wire Serial Interface Operation After a nonvolatile write command sequence is correctly issued X9252 Digital Potentiometer Register Organization (including the final STOP condition), the X9252 initiates an Refer to the “Functional Diagram” on page2. There are four internal high voltage write cycle. This cycle typically requires Digitally Controlled Potentiometers, referred to as DCPi, 5ms. During this time, any Read or Write command is ignored i = 0, 1, 2, 3. Each potentiometer has one volatile Wiper by the X9252. Write Acknowledge Polling is used to determine Control Register (WCR) with the corresponding number, whether a high voltage write cycle is completed. WCRi, i = 0, 1, 2, 3. Each potentiometer also has four During acknowledge polling, the master first issues a START nonvolatile registers to store wiper position or general data, condition followed by a Slave Address Byte. The Slave these are numbered DRi0, DRi1, DRi2 and DRi3, Address Byte contains the X9252’s Device Type Identifier and i = 0, 1, 2, 3. Device Address. The LSB of the Slave Address (R/W) can be The registers are organized in five pages of four, with one page set to either 1 or 0 in this case. If the device is busy within the consisting of the WCRi (i = 0 to 3), a second page containing high voltage cycle, then no ACK is returned. If the high voltage the DRi0 (i = 0 to 3), a third page containing the DRi1, and so cycle is completed, an ACK is returned and the master can forth. These pages can be written to four bytes at time. In this then proceed with a new Read or Write operation (see manner all four potentiometer WCRs can be updated in a Figure5). single serial write (see “Page Write Operation” on page14), as well as all four registers of a given page in the DR array. BYTE LOAD COMPLETED BY ISSUING STOP. ENTER ACK POLLING The unique feature of the X9252 device is that writing or reading to a Data Register of a given DCP automatically updates/moves the WCR of that DCP with the content of the DR. In this manner data can be moved from a particular DCP ISSUE START register to that DCP’s WCR just by performing a 2-wire read operation. Simultaneously, that data byte can be utilized by the host. ISSUE SLAVE ISSUE STOP ADDRESS BYTE Status Register Organization (READ OR WRITE) The Status Register (SR) is used in read and write operations to select the appropriate DCP register. Before any DCP register can be accessed, the SR must be set to the correct NO ACK RETURNED? value. It is accessed by setting the Address Byte to 07h (see Table3). Do this by Writing the Slave Address followed by a Byte Address of 07h. The SR is volatile and defaults to 00h on YES power-up. It is an 8-bit register containing three control bits in the 3 LSBs as follows: HIGH VOLTAGE NO COMPLETE. CONTINUE COMMAND 7 6 5 4 3 2 1 0 SEQUENCE. Reserved DRSel1 DRSel0 NVEnable YES Bits DRSel1 and DRSel0 determine which Data Register of a ISSUE STOP DCP is selected for a given operation. NVEnable is used to CONTINUE NORMAL READ OR WRITE COMMAND SEQUENCE select the volatile WCR if “0”, and one of the nonvolatile DCP registers if “1”. Table2 shows this register organization. “Store” operations using the Up/Down interface require that bits DRSel1 and DRSel0 are set to “0”. PROCEED FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE FN8167 Rev 3.00 Page 11 of 19 July 24, 2014

X9252 TABLE 2. REGISTER NUMBERING STATUS REG (Note13) (Addr: 07H) REGISTERED SELECTED (Note14) DCP0 DCP1 DCP2 DCP3 RESERVED DRSel1 DRSel0 NVEnable BITS 7-3 BIT-2 BIT-1 BIT-0 (ADDR: 00h) (ADDR: 01h) (ADDR: 02h) (ADDR: 03h) Reserved X X 0 WCR0 WCR1 WCR2 WCR3 0 0 1 DR00 DR10 DR20 DR30 0 1 1 DR01 DR11 DR21 DR31 1 0 1 DR02 DR12 DR22 DR32 1 1 1 DR03 DR13 DR23 DR33 To read or write the contents of a single Data Register or Wiper Register: 13. Load the status register (using a write command) to select the row (see Figure6) Writing a 1, 3, 5, or 7 to the Status Register specifies that the subsequent read or write command will access a Data Register. This status register operation also initiates a transfer of the contents of the selected data register to its associated WCR for all DCPs. So, for example, writing ‘03h’ to the status register causes the value in DR01 to move to WCR0, DR11 to move to WCR1, DR21 to move to WCR2, and DR31 to move to WCR3. Writing a 0 to bit ‘0’ of the status register specifies that the subsequent read or write command will access a wiper counter register. Each WCR can be written to individually, without affecting the contents of any other. 14. Access the desired DR or WCR using a new write or read command (see Figure7 for write and Figure9 for read.) Specify the desired column (DCP number) by sending the DCP address as part of this read or write command. If Bit-0 of data byte = 1, DR contents move to WCR during this ACK period S SIGTNHAEL MSA FSRTOEMR ART ADSDLARVEES S STATAUDSD RREEGSISSTER DR DSAETLAECT OST T P SIGNAL AT SDA 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 x x 1 SIGNALS FROM A A A THE SLAVE C C C K K K FIGURE 6. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER) FN8167 Rev 3.00 Page 12 of 19 July 24, 2014

X9252 DCP Addressing for 2-Wire Interface The SR bits and WP pin determine the register being accessed Once the register number has been selected by a 2-wire through the 2-wire interface (see Table2). instruction, then the DCP number is determined by the As noted before, any write operation to a Data Register (DR), Address Byte of the following instruction. Note again that this also transfers the contents of all the data registers in that row enables a complete page write of the DRs of all four to their corresponding WCR. potentiometers at once. The register addresses accessible in the X9252 include: For example, to write 3Ahex to the Data Register 1 of DCP2 the following sequence is required: TABLE 3. 2-WIRE INTERFACE ADDRESS BYTE START ADDRESS (HEX) CONTENTS Slave Address 0101 0000 (Hardware Address = 000, 0 DCP 0 ACK and a Write Command) 1 DCP 1 Address Byte 0000 0111 (Indicates Status Register ACK Address) 2 DCP 2 Data Byte 0000 0011 (Data Register 1 and 3 DCP 3 ACK NVEnable Selected) 4 Not Used Note: at this ACK, the WCRs are all updated with their respective DR. STOP 5 Not Used START 6 Not Used Slave Address 0101 0000 (Hardware Address = 000, 7 Status Register Write Command) ACK Address Byte 0000 0010 (Access DCP2) All other address bits in the Address Byte must be set to “0” ACK during 2-wire write operations and their value should be Data Byte 0011 1010 (Write Data Byte 3Ah) ignored when read. ACK Byte Write Operation STOP For any Byte Write operation, the X9252 requires the Slave Address byte, an Address Byte, and a Data Byte During the sequence of this example, WP pin must be high, (see Figure7). After each of them, the X9252 responds with an and A0, A1, and A2 pins must be low. When completed, the ACK. The master then terminates the transfer by generating a DR21 register and the WCR2 will be set to 3Ah and the other STOP condition. At this time, if the write operation is to a Data Register in Row 1 will transfer their other contents to the volatile register (WCR, or SR), the X9252 is ready for the next respective WCR’s read or write operation. If the write operation is to a nonvolatile register (DR), and the WP pin is high, the X9252 begins the internal write cycle to the nonvolatile memory. During the internal nonvolatile write cycle, the X9252 does not respond to any requests from the master. The SDA output is at high impedance. WRITE S SIGNALS FROM T S THE MASTER A SLAVE ADDRESS DATA T R ADDRESS BYTE BYTE O T P SIGNAL AT SDA 0 1 0 1 0 SIGNALS FROM A A A THE SLAVE C C C K K K FIGURE 7. BYTE WRITE SEQUENCE FN8167 Rev 3.00 Page 13 of 19 July 24, 2014

X9252 Page Write Operation (DR3i, 03hex), it “rolls over” and goes back to the first byte of the same page (DR0i, 00hex). As stated previously, the memory is organized as a single Status Register (SR), and four pages of four registers each. For example, if the master writes 3 bytes to a page starting at Each page contains one Data Register for each DCP. The location DR22, the first 2 bytes are written to locations DR22 order of the bytes within a page is DR0i, followed by DR1i, and DR32, while the last byte is written to locations DR02. followed by DR2i, and then DR3i, with i being the Data Afterwards, the DCP counter would point to location DR12. If Register number (0, 1, 2, or 3). Normally a page write the master supplies more than 4 bytes of data, then new data operation will be used to efficiently update all four data overwrites the previous data, one byte at a time. registers and WCR in a single write command, starting at The master terminates the loading of Data Bytes by issuing a DCP0 and finishing with DCP3. STOP condition, which initiates the nonvolatile write cycle. As In order to perform a Page Write operation to the memory with the Byte Write operation, all inputs are disabled until array, the NVEnable bit in the SR must first be set to “1”. completion of the internal write cycle. If the WP pin is low, the A Page Write operation is initiated in the same manner as the nonvolatile write cycle doesn’t start and the bytes are byte write operation; but instead of terminating the write cycle discarded. after the first data byte is transferred, the master can transmit Notice that the Data Bytes are also written to the WCR of the up to 4 bytes (see Figure8). After the receipt of each byte, the corresponding DCPs, therefore in the above example, WCR2, X9252 responds with an ACK, and the internal DCP address WCR3, and WCR0 are also written and WCR1 is updated with counter is incremented by one. The page address remains the contents of DR12. constant. When the counter reaches the end of the page WRITE S 2 < n < 4 SIGNALS FROM T S THE MASTER A SLAVE ADDRESS T R ADDRESS BYTE DATA BYTE (1) DATA BYTE (n) O T P SIGNAL AT SDA 0 1 0 1 0 SIGNALS FROM A A A A THE SLAVE C C C C K K K K FIGURE 8. PAGE WRITE OPERATION FN8167 Rev 3.00 Page 14 of 19 July 24, 2014

X9252 Move/Read Operation as long as the master responds with an ACK during the SCL The Move/Read operation simultaneously reads the contents cycle following the eight bit of each byte. The master terminates the Move/Read operation (issuing a STOP of a Data Register (DR) and moves the contents into the corresponding DCP’s WCR and the WCRs of all DCPs are condition) following the last bit of the last Data Byte. updated with the content of their corresponding DR. The first byte being read is determined by the current DCP Move/Read operation consists of a one byte, or three byte address and by the Status Register bits, according to Table 2. If instruction followed by one or more Data Bytes more than one byte is read, the DCP address is incremented (see Figure9). To read an arbitrary byte, the master initiates by one after each byte, in the same way as during a Page the operation issuing the following sequence: a START, the Write operation. After reaching DCP3, the DCP address “rolls Slave Address byte with the R/W bit set to “0”, an Address over” to DCP0. Byte, a second START, and a second Slave Address byte with On power-up, the Address pointer is set to the Data Register 0 the R/W bit set to “1”. After each of the three bytes, the X9252 of DCP0. responds with an ACK. Then the X9252 transmits Data Bytes ONE OR MORE DATA BYTES S SLAVE S SLAVE SIGNALS T ADDRESS WITH T ADDRESS WITH S FROM THE A A T MASTER R R/W = 0 ADDRESS R R/W = 1 A A O T BYTE T C C P K K SIGNAL AT SDA 0 1 0 1 0 0 1 0 1 1 A A A SIGNALS FROM C C C THE SLAVE K K K FIRST READ LAST READ DATA BYTE DATA BYTE SETTING THE CURRENT ADDRESS CURRENT ADDRESS READ RANDOM ADDRESS READ FIGURE 9. MOVE/READ SEQUENCE FN8167 Rev 3.00 Page 15 of 19 July 24, 2014

X9252 Applications Information Basic Configurations of Electronic Potentiometers VR +VR RW I FIGURE 10. THREE TERMINAL POTENTIOMETER; VARIABLE FIGURE 11. TWO TERMINAL VARIABLE RESISTOR; VOLTAGE DIVIDER VARIABLE CURRENT Application Circuits VS + VIN 317 VO (REG) VO - R1 Iadj R2 R2 R1 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1) + Iadj R2 FIGURE 13. VOLTAGE REGULATOR FIGURE 12. NONINVERTING AMPLIFIER R1 R2 VS +5V VS - 100k VO - + VO + TL072 10k } } R1 R2 10k 10k +5V VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) FIGURE 14. OFFSET VOLTAGE ADJUSTMENT FIGURE 15. COMPARATOR WITH HYSTERISIS FN8167 Rev 3.00 Page 16 of 19 July 24, 2014

X9252 Application Circuits (Continued) C VS + VO R1 R2 - - R VO VS + R3 R2 R4 R1 = R2 = R3 = R4 = 10k R1 GO = 1 + R2/R1 VO = G VS fc = 1/(2RC) -1/2  G  +1/2 FIGURE 17. FILTER FIGURE 16. ATTENUATOR R1 R2 VS } } C1 R2 VS + - - VO + R1 ZIN VO = G VS R3 G = - R2/R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FIGURE 18. INVERTING AMPLIFIER FIGURE 19. EQUIVALENT L-R CIRCUIT C - R2 R1 - + } RA + } RB FREQUENCY R1, R2, C AMPLITUDE  RA, RB FIGURE 20. FUNCTION GENERATOR FN8167 Rev 3.00 Page 17 of 19 July 24, 2014

X9252 Application Circuits (Continued) V+ mR nR pR VUL + VS } } } VO - VS + V+ VR - VO + + - VLL FIGURE 21. WINDOW COMPARATOR FIGURE 22. SHUNT LIMITER C mR nR pR } } } - VO + - + FIGURE 23. FUNCTION GENERATOR © Copyright Intersil Americas LLC 2005-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8167 Rev 3.00 Page 18 of 19 July 24, 2014

X9252 Package Outline Drawing M24.173 24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 7.80 ±0.10 24 13 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 C B A 1 12 +0.05 0.65 B 0.15 -0.06 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90+0.15 -0.10 1.20 MAX GAUGE SEATING PLANE PLANE 0.25 0.25+0.05 5 -0.06 0°-8° 0.10C 0.10MCBA 0.05 MIN 0.15 MAX 0.60± 0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN8167 Rev 3.00 Page 19 of 19 July 24, 2014