VND1NV04 VNN1NV04 - VNS1NV04 OMNIFET II fully autoprotected Power MOSFET Features 3 Parameter Symbol Value 1 Max on-state resistance (per ch.) RON 250mΩ TO-252 (DPAK) Current limitation (typ) I 1.7A LIMH 2 Drain-source clamp voltage V 40V CLAMP 3 2 1 ■ Linear current limitation SOT-223 SO-8 ■ Thermal shutdown ■ Short circuit protection ■ Integrated clamp Description ■ Low current drawn from input pin ■ Diagnostic feedback through input pin The VND1NV04, VNN1NV04, VNS1NV04 are ■ ESD protection monolithic devices designed in STMicroelectronics® VIPower® M0-3 Technology, ■ Direct access to the gate of the Power intended for replacement of standard Power MOSFET (analog driving) MOSFETs from DC up to 50KHz applications. ■ Compatible with standard Power MOSFET Built in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments. Fault feedback can be detected by monitoring the voltage at the input pin. Table 1. Device summary Order codes Package Tube Tube (lead free) Tape and reel Tape and reel (lead free) TO-252 (DPAK) VND1NV04 VND1NV04-E VND1NV0413TR VND1NV04TR-E SOT-223 VNN1NV04 - VNN1NV0413TR - SO-8 VNS1NV04 - VNS1NV0413TR - September 2013 Doc ID 7381 Rev 4 1/33 www.st.com 1

Contents VND1NV04 - VNN1NV04 - VNS1NV04 Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 DPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 DPAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 SO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 DPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 SO8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DPAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. SOT-223 thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. SO-8 thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. DPAK mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 7381 Rev 4 3/33

List of figures VND1NV04 - VNN1NV04 - VNS1NV04 List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Test circuit for diode recovery times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 10. Static drain-source on resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. Static drain-source on resistance vs. input voltage (part 1/2). . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13. Static drain-source on resistance vs. input voltage (part 2/2). . . . . . . . . . . . . . . . . . . . . . . 12 Figure 14. Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15. Static drain-source on resistance vs. Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 16. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17. Turn-on current slope (part1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 18. Turn-on current slope (part2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 19. Input voltage vs. input charge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 20. Turn-off drain source voltage slope (part1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 21. Turn-off drain-source voltage slope (part2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 22. Capacitance variations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 23. Switching time resistive load (part1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 24. Switching time resistive load (part2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 25. Output characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 26. Normalized on resistance vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 27. Normalized input threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 28. Normalized current limit vs. junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 29. Step response current limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 30. DPAK PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 31. DPAK Rthj-amb vs. PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . 17 Figure 32. DPAK thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 33. DPAK thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 34. SOT-223 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 35. SOT-223 Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . 20 Figure 36. SOT-223 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 37. SOT-223 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 38. SO-8 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 39. SO-8 Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . 22 Figure 40. SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 41. SO-8 thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 42. DPAK package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 43. SOT-223 mechanical data & package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 44. SO-8 package dimension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 45. SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 46. SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 47. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram DRAIN 2 Overvoltage Clamp INPUT Gate 1 Control Linear Current Over Limiter Temperature 3 SOURCE Figure 2. Configuration diagram (top view) SOURCE 1 8 DRAIN SOURCE DRAIN SOURCE DRAIN INPUT 4 5 DRAIN 1. For the pins configuration related to SOT-223 and DPAK see outline at page 1. Doc ID 7381 Rev 4 5/33

Electrical specifications VND1NV04 - VNN1NV04 - VNS1NV04 2 Electrical specifications Figure 3. Current and voltage conventions I D V DS DRAIN IIN RIN INPUT SOURCE V IN 2.1 Absolute maximum ratings The rating listed in Table2: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. T able 2. Absolute maximum ratings Value Symbol Parameter Unit SOT-223 SO-8 DPAK V Drain-source voltage (V =0V) Internally clamped V DSn INn V Input voltage Internally clamped V INn I Input current +/-20 mA INn R Minimum input series impedance 330 Ω IN MINn I Drain current Internally limited A Dn I Reverse DC output current -3 A Rn V Electrostatic discharge (R=1.5KΩ, C=100pF) 4000 V ESD1 Electrostatic discharge on output pins only V 16500 V ESD2 (R=330Ω, C=150pF) P Total dissipation at T=25°C 7 8.3 35 W tot c T Operating junction temperature Internally limited °C j T Case operating temperature Internally limited °C c T Storage temperature -55 to 150 °C stg 6/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Electrical specifications 2.2 Thermal data T able 3. Thermal data Maximum value Symbol Parameter Unit SOT-223 SO-8 DPAK R Thermal resistance junction-case 18 3.5 °C/W thj-case R Thermal resistance junction-lead 15 °C/W thj-lead R Thermal resistance junction-ambient 70(1) 65(1) 54(1) °C/W thj-amb 1. When mounted on a standard single-sided FR4 board with 50mm2 of Cu (at least 35μm thick) connected to all DRAIN pins 2.3 Electrical characteristics T able 4. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Off (-40°C<Tj<150°C, unless otherwise specified) Drain-source clamp V V =0V; I =0.5A 40 45 55 V CLAMP voltage IN D Drain-source clamp V V =0V; I =2mA 36 V CLTH threshold voltage IN D Input threshold V V =V ; I =1mA 0.5 2.5 V INTH voltage DS IN D Supply current from I V =0V; V =5V 100 150 µA ISS input pin DS IN Input-source clamp IIN=1mA 6 6.8 8 V V INCL voltage I =-1mA -1.0 -0.3 IN Zero input voltage V =13V; V =0V; T=25°C 30 µA DS IN j I drain current DSS (VIN=0V) VDS=25V; VIN=0V 75 On (-40°C<Tj<150°C, unless otherwise specified) Static drain-source on VIN=5V; ID=0.5A; Tj=25°C 250 mΩ R DS(on) resistance V =5V; I =0.5A 500 IN D Dynamic (T=25°C, unless otherwise specified) j Forward g (1) V =13V; I =0.5A 2 S fs transconductance DD D C Output capacitance V =13V; f=1MHz; V =0V 90 pF OSS DS IN Doc ID 7381 Rev 4 7/33

Electrical specifications VND1NV04 - VNN1NV04 - VNS1NV04 Table 4. Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Switching (T=25°C, unless otherwise specified) j t Turn-on delay time 70 200 ns d(on) V =15V; I =0.5A t Rise time DD D 170 500 ns r V =5V; R =R =330Ω gen gen IN MIN t Turn-off delay time 350 1000 ns d(off) (see Figure4) t Fall time 200 600 ns f t Turn-on delay time 0.25 1.0 µs d(on) V =15V; I =0.5A t Rise time DD D 1.3 4.0 µs r V =5V; R =2.2KΩ gen gen t Turn-off delay time 1.8 5.5 µs d(off) (see Figure4) t Fall time 1.2 4.0 µs f V =15V; I =1.5A (dI/dt) Turn-on current slope DD D 5 A/µs on V =5V; R =R =330Ω gen gen IN MIN V =12V; I =0.5A; V =5V Q Total input charge DD D IN 5 nC i I =2.13mA (see Figure7) gen Source drain diode (T=25°C, unless otherwise specified) j V (1) Forward on voltage I =0.5A; V =0V 0.8 V SD SD IN Reverse recovery t 205 ns rr time I =0.5A; dI/dt=6A/µs SD Reverse recovery Q V =30V; L=200µH 100 nC rr charge DD (see Figure5) Reverse recovery I 0.7 A RRM current Protections (-40°C<T<150°C, unless otherwise specified) j I Drain current limit V =5V; V =13V 1.7 3.5 A lim IN DS Step response t V =5V; V =13V 2.0 µs dlim current limit IN DS Overtemperature T 150 175 200 °C jsh shutdown Overtemperature T 135 °C jrs reset I Fault sink current V =5V; V =13V; T=T 10 15 20 mA gf IN DS j jsh Starting T=25°C; V =24V j DD Single pulse V =5V R =R =330Ω; E IN gen IN MIN 55 mJ as avalanche energy L=50mH (see Figure6 and Figure8) 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% 8/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Electrical specifications Figure 4. Switching time test circuit for resistive load VD Rgen Vgen I D 90% tr 10% tf t V td(on) td(off) gen t Doc ID 7381 Rev 4 9/33

Electrical specifications VND1NV04 - VNN1NV04 - VNS1NV04 Figure 5. Test circuit for diode recovery times A A D I FAST L=100uH OMNIFET DIODE S B B 330Ω D V R DD gen I OMNIFET V gen S 8.5 Ω Figure 6. Unclamped inductive load test circuits R GEN V IN P W 10/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Electrical specifications Figure 7. Input charge test circuit VIN GEN ND8003 Figure 8. Unclamped inductive waveforms Doc ID 7381 Rev 4 11/33

Electrical specifications VND1NV04 - VNN1NV04 - VNS1NV04 2.4 Electrical characteristics curves Figure 9. Source-drain diode forward Figure 10. Static drain-source on resistance characteristics Vsd (mV) Rds(on) (ohms) 1000 4.5 Tj=-40ºC 4 950 Vin=2.5V 3.5 Vin=0V 900 3 2.5 850 2 800 1.5 Tj=25ºC 1 750 Tj=150ºC 0.5 700 0 0 2 4 6 8 10 12 14 0 0.05 0.1 0.15 0.2 0.25 0.3 Id (A) Id(A) Figure 11. Derating curve Figure 12. Static drain-source on resistance vs. input voltage (part 1/2) Rds(on) (mohms) 500 450 Id=0.5A 400 Tj=150ºC 350 300 250 200 Tj=25ºC 150 Tj=-40ºC 100 50 0 3 3.5 4 4.5 5 5.5 6 6.5 7 Vin(V) Figure 13. Static drain-source on resistance Figure 14. Transconductance vs. input voltage (part 2/2) Rds(on) (mohms) Gfs (S) 500 6 Tj=150ºC 450 5.5 Vds=13V Tj=-40ºC 400 5 Id=1.5A Tj=25ºC 350 Id=1A 4.5 4 Tj=150ºC 300 3.5 250 Tj=25ºC 3 200 2.5 Id=1.5A Tj=-40ºC Id=1A 2 150 Id=1.5A 1.5 100 Id=1A 1 50 0.5 0 0 3 3.5 4 4.5 5 5.5 6 6.5 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Vin(V) Id(A) 12/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Electrical specifications Figure 15. Static drain-source on resistance Figure 16. Transfer characteristics vs. Id Rds(on) (mohms) Idon(A) 500 2.25 450 Vin=3.5V 2 Tj=25ºC 400 Tj=150ºC Vds=13.5V Vin=5V 1.75 350 1.5 300 1.25 250 Vin=3.5V 1 125000 Tj=25ºC VVinin==35.5VV 0.75 Tj=150ºC Tj=-40ºC Tj=-40ºC Vin=5V 0.5 100 0.25 50 0 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1.5 2 2.5 3 3.5 4 4.5 5 1.75 2.25 2.75 3.25 3.75 4.25 4.75 Id(A) Vin(V) Figure 17. Turn-on current slope (part1/2) Figure 18. Turn-on current slope (part2/2) di/dt(A/us) di/dt(A/us) 6 1.4 5 Vin=5V 1.2 Vin=3.5V Vdd=15V Vdd=15V 4 Id=1.5A 1 Id=1.5A 3 0.8 2 0.6 1 0.4 0 0.2 0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500 Rg(ohm) Rg(ohm) Figure 19. Input voltage vs. input charge Figure 20. Turn-off drain source voltage slope (part1/2) Vin (V) dv/dt(V/us) 6 350 300 5 Vds=12V Vin=5V Id=0.5A 250 Vdd=15V 4 Id=0.5A 200 3 150 2 100 1 50 0 0 0 1 2 3 4 5 6 0 500 1000 1500 2000 2500 Qg (nC) Rg(ohm) Doc ID 7381 Rev 4 13/33

Electrical specifications VND1NV04 - VNN1NV04 - VNS1NV04 Figure 21. Turn-off drain-source voltage slope Figure 22. Capacitance variations (part2/2) dv/dt(V/us) C(pF) 350 225 300 200 f=1MHz Vin=3.5V Vin=0V 250 Vdd=15V 175 Id=0.5A 200 150 150 125 100 100 50 75 0 50 0 500 1000 1500 2000 2500 0 5 10 15 20 25 30 35 Rg(ohm) Vds(V) Figure 23. Switching time resistive load Figure 24. Switching time resistive load (part1/2) (part2/2) t(ns) t(us) 550 2 500 1.75 td(off) 450 tr VIdd=d0=.155AV Vdd=15V Rg=330ohm 1.5 Id=0.5A 400 Vin=5V tr 350 1.25 td(off) 300 tf 1 250 tf 0.75 200 0.5 150 td(on) td(on) 100 0.25 50 0 0 0 250 500 750 100012501500 175020002250 2500 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 Rg(ohm) Vin(V) Figure 25. Output characteristics Figure 26. Normalized on resistance vs. temperature ID(A) Rds(on) (mOhm) 2.4 2.25 2.2 Vin=5.5V 2 2 Vin=4.5V Vin=5V 1.8 Vin=3.5V 1.75 Id=0.5A 1.6 1.4 1.5 1.2 1.25 1 0.8 1 0.6 0.4 Vin=3V 0.75 0.2 0 0.5 0 1 2 3 4 5 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 150 175 VDS(V) Tc (ºC) 14/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Electrical specifications Figure 27. Normalized input threshold voltage Figure 28. Normalized current limit vs. vs. temperature junction temperature Vinth (V) Ilim (A) 2 5 1.8 4.5 Vds=Vin 1.6 Vin=5V Id=1mA 4 Vds=13V 1.4 3.5 1.2 3 1 2.5 0.8 2 0.6 1.5 0.4 1 0.2 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Figure 29. Step response current limit Tdlim(us) 2.4 2.3 Vin=5V Rg=330ohm 2.2 2.1 2 1.9 5 10 15 20 25 30 35 Vdd(V) Doc ID 7381 Rev 4 15/33

Protection features VND1NV04 - VNN1NV04 - VNS1NV04 3 Protection features During normal operation, the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path. The device behaves like a standard Power MOSFET and it can be used as a switch from DC up to 50KHz. The only difference from the user’s point of view is that a small DC current I ISS (typ. 100µA) flows into the input pin in order to supply the internal circuitry. The device integrates: ● Overvoltage clamp protection gives – Internally set at 45V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. ● Linear current limiter circuit – Limits the drain current I to I whatever the input pin voltages. When the current D lim limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh. ● Overtemperature and short circuit protection – These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout ranges is from 150 to 190°C, a typical value is 170°C. The device is automatically restarted when the chip temperature falls of about 15°C below shutdown temperature. ● Status feedback – In the case of an overtemperature fault condition (T > T ), the device tries to sink j jsh a diagnostic current I through the input pin in order to indicate fault condition. If gf driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the input pin driver is not able to supply the current I , the input pin falls to 0V. gf This does not however affect the device operation: no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current I . Additional features of this device are ESD protection ISS according to the Human Body model and the ability to be driven from a TTL logic circuit. 16/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and PCB thermal data 4 Package and PCB thermal data 4.1 DPAK thermal data Figure 30. DPAK PC board 1. Layout condition of R and Z measurements (PCB FR4 area = 58mm x 58mm,PCB thickness = 2mm, Cu thickness=35µm t,h Coppetrh areas: from minimum pad layout to 16cm2). Figure 31. DPAK R vs. PCB copper area in open box free air condition thj-amb 90 footprint 80 70 60 50 40 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) - (refer to PCB layout) Doc ID 7381 Rev 4 17/33

Package and PCB thermal data VND1NV04 - VNN1NV04 - VNS1NV04 Figure 32. DPAK thermal impedance junction ambient single pulse ZTH (°C/W) 100 Footprint 6 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 10 100 1000 Time (s) Equation 1: Pulse calculation formula ZTHδ = RTH⋅δ+ZTHtp(1–δ) where δ = t /T P Figure 33. DPAK thermal fitting model of a single channel 18/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and PCB thermal data Table 5. DPAK thermal parameter Area/island (cm2) 0.25 6 R1 (°C/W) 0.8 R2 (°C/W) 1.6 R3 (°C/W) 0.8 R4 (°C/W) 2 R5 (°C/W) 15 R6 (°C/W) 61 24 C1 (W·s/°C) 0.00006 C2 (W·s/°C) 0.0005 C3 (W·s/°C) 0.01 C4 (W·s/°C) 0.3 C5 (W·s/°C) 0.45 C6 (W·s/°C) 0.8 5 4.2 SOT-223 thermal data Figure 34. SOT-223 PC board . 1. Layout condition of R and Z measurements (PCB FR4 area = 58mm x 58mm,PCB thickness = 2mm, Cu thickness=35µm t,h Coppetrh areas: from minimum pad layout to 0.8cm2). Doc ID 7381 Rev 4 19/33

Package and PCB thermal data VND1NV04 - VNN1NV04 - VNS1NV04 Figure 35. SOT-223 R vs. PCB copper area in open box free air condition thj-amb 140 footprint 130 120 110 100 90 80 70 60 0 0,5 1 1,5 2 2,5 PCB Cu heatsink area (cm^2) - (refer to PCB layout) Figure 36. SOT-223 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Footprint 100 2 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 10 100 1000 Time (s) 20/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and PCB thermal data Equation 2: Pulse calculation formula ZTHδ = RTH⋅δ+ZTHtp(1–δ) where δ = t /T P Figure 37. SOT-223 thermal fitting model of a single channel Table 6. SOT-223 thermal parameter Area/island (cm2) FP 2 R1 (°C/W) 0.8 R2 (°C/W) 1.6 R3 (°C/W) 4.5 R4 (°C/W) 24 R5 (°C/W) 0.1 R6 (°C/W) 100 45 C1 (W·s/°C) 0.00006 C2 (W·s/°C) 0.0005 C3 (W·s/°C) 0.03 C4 (W·s/°C) 0.16 C5 (W·s/°C) 1000 C6 (W·s/°C) 0.5 2 Doc ID 7381 Rev 4 21/33

Package and PCB thermal data VND1NV04 - VNN1NV04 - VNS1NV04 4.3 SO-8 thermal data Figure 38. SO-8 PC board . 1. Layout condition of R and Z measurements (PCB FR4 area = 58mm x 58mm,PCB thickness = 2mm, Cu thickness=35µm t,h Coppetrh areas: from minimum pad layout to 2cm2). Figure 39. SO-8 R vs. PCB copper area in open box free air condition thj-amb 105 footprint 95 85 75 65 0 0,5 1 1,5 2 2,5 PCB Cu heatsink area (cm^2) - (refer to PCB layout) 22/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and PCB thermal data Figure 40. SO-8 thermal impedance junction ambient single pulse ZTH (°C/ W) 1000 Footprint 100 2 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 10 100 1000 Time (s) Equation 3: Pulse calculation formula ZTHδ = RTH⋅δ+ZTHtp(1–δ) where δ = t /T P Figure 41. SO-8 thermal fitting model of a single channel Doc ID 7381 Rev 4 23/33

Package and PCB thermal data VND1NV04 - VNN1NV04 - VNS1NV04 Table 7. SO-8 thermal parameter Area/island (cm2) FP 2 R1 (°C/W) 0.8 R2 (°C/W) 2.6 R3 (°C/W) 3.5 R4 (°C/W) 21 R5 (°C/W) 16 R6 (°C/W) 58 28 C1 (W·s/°C) 0.00006 C2 (W·s/°C) 0.0005 C3 (W·s/°C) 0.0075 C4 (W·s/°C) 0.045 C5 (W·s/°C) 0.35 C6 (W·s/°C) 1.05 2 24/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and packing information 5 Package and packing information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.1 DPAK mechanical data Figure 42. DPAK package dimensions P 0 3 2 P Doc ID 7381 Rev 4 25/33

Package and packing information VND1NV04 - VNN1NV04 - VNS1NV04 T able 8. DPAK mechanical data mm. Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 B 0.64 0.90 B2 5.20 5.40 C 0.45 0.60 C2 0.48 0.60 D 6.00 6.20 D1 5.1 E 6.40 6.60 E1 4.7 e 2.28 G 4.40 4.60 H 9.35 10.10 L2 0.8 L4 0.60 1.00 R 0.2 V2 0° 8° Package weight Gr. 0.29 26/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and packing information 5.2 SOT-223 mechanical data Figure 43. SOT-223 mechanical data & package outline 5.3 SO8 mechanical data T able 9. SO-8 mechanical data mm Dim. Min. Typ. Max. A 1.75 A1 0.10 0.25 A2 1.25 Doc ID 7381 Rev 4 27/33

Package and packing information VND1NV04 - VNN1NV04 - VNS1NV04 Table 9. SO-8 mechanical data (continued) mm Dim. Min. Typ. Max. b 0.28 0.48 c 0.17 0.23 D(1) 4.80 4.90 5.00 E 5.80 6.00 6.20 E1(2) 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 L1 1.04 k 0° 8° ccc 0.10 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. Figure 44. SO-8 package dimension 0016023 D 28/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and packing information 5.4 DPAK packing information The devices can be packed in tube or tape and reel shipments (see the Table1: Device summary ). DPAK FOOTPRINT TUBE SHIPMENT (no suffix) A C Base Q.ty 75 Bulk Q.ty 3000 Tube length (± 0.5) 532 A 6 B B 21.3 C (± 0.1) 0.6 All dimensions are in mm. TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 16.4 N (min) 60 T (max) 22.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width W 16 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 7.5 Compartment Depth K (max) 6.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape. User direction of feed Doc ID 7381 Rev 4 29/33

Package and packing information VND1NV04 - VNN1NV04 - VNS1NV04 5.5 SOT-223 packing information Figure 45. SOT-223 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty 1000 Bulk Q.ty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (+ 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape. User direction of feed 30/33 Doc ID 7381 Rev 4

VND1NV04 - VNN1NV04 - VNS1NV04 Package and packing information 5.6 SO8 packing information Figure 46. SO-8 tube shipment (no suffix) B C Base Q.ty 100 Bulk Q.ty 2000 Tube length (± 0.5) 532 A A 3.2 B 6 C (± 0.1) 0.6 All dimensions are in mm. Figure 47. SO-8 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (+ 0.1/-0) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.05) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape. User direction of feed Doc ID 7381 Rev 4 31/33

Revision history VND1NV04 - VNN1NV04 - VNS1NV04 6 Revision history T able 10. Document revision history Date Revision Changes Feb-2003 1 Initial release. Added Table1: Device summary and Section4: Package and PCB 16-Apr-2009 2 thermal data Updated Section5: Package and packing information on page25 Upadate Table1: Device summary. 01-Dic-2011 3 Update the entire document using the new coorporate template. 20-Sep-2013 4 Updated Disclaimer. 32/33 Doc ID 7381 Rev 4

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