VND5E160AJ-E Double channel high side driver with analog current sense for automotive applications Features Max transient supply voltage V 41 V CC Operating voltage range V 4.5 to 28V CC PowerSSO-12 Max On-state resistance (per ch.) R 160 m ON Current limitation (typ.) I 10 A – Reverse battery protected (see Application LIMH schematic) Off state supply current I 2 µA(1) S – Electrostatic discharge protection 1. Typical value with all loads connected. Application ■ General ■ All types of resistive, inductive and capacitive – Inrush current active management by loads power limitation – Very low stand-by current ■ Suitable as LED driver – 3.0 V CMOS compatible inputs Description – Optimized electromagnetic emissions – Very low electromagnetic susceptibility The VND5E160AJ-E is a single channel high-side – In compliance with the 2002/95/EC driver manufactured in the ST proprietary european directive VIPower M0-5 technology and housed in the tiny – Very low current sense leakage PowerSSO-12 package. The VND5E160AJ-E is designed to drive 12V automotive grounded loads ■ Diagnostic functions delivering protection, diagnostics and easy 3V – Proportional load current sense and 5V CMOS compatible interface with any – High current sense precision for wide microcontroller. currents range The device integrates advanced protective – Current sense disable functions such as load current limitation, inrush – Off state openload detection and overload active management by power – Output short to V detection CC limitation, over-temperature shut-off with – Overload and short to ground (power auto-restart and over-voltage active clamp. A limitation) indication dedicated analog current sense pin is associated – Thermal shutdown indication with every output channel in order to provide ■ Protections Ehnanced diagnostic functions including fast detection of overload and short-circuit to ground – Undervoltage shutdown through power limitation indication, over- – Overvoltage clamp temperature indication, short-circuit to Vcc – Load current limitation diagnosis and ON & OFF state open load – Self limiting of fast thermal transients detection. The current sensing and diagnostic – Protection against loss of ground and loss feedback of the whole device can be disabled by of V pulling the CS_DIS pin high to allow sharing of CC – Over-temperature shutdown with the external sense resistor with other similar autorestart (thermal shutdown) devices. September 2013 Rev 3 1/37 www.st.com 37

Contents VND5E160AJ-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24 3.1.1 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 24 3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 25 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.1 Short to VCC and OFF state open load detection . . . . . . . . . . . . . . . . . 27 3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28 4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/37

VND5E160AJ-E List of tables List of tables Table 1. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 8. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9. Current sense (8V<VCC<18V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 10. Openload detection (8V<V <18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CC Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 13. Thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3/37

List of figures VND5E160AJ-E List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Openload Off-state delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. Iout/ Isense vs. Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14. OFF-State Open Load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 15. Short to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CC Figure 16. T evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 J Figure 17. Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 18. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 20. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 21. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 22. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 23. On state resistance vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 case Figure 24. On state resistance vs. V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CC Figure 25. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 27. I vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 LIMH case Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 29. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 30. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 31. CS_DIS low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 32. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 33. Current sense and diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 34. Maximum turn-Off current versus inductance (for each channel). . . . . . . . . . . . . . . . . . . . 28 Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 36. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 29 Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 30 Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 30 Figure 39. PowerSSO-12 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 40. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4/37

VND5E160AJ-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC Signal Clamp Undervoltage Control & Diagnostic 1 Power Clamp C IN1 DRIVER TI S IN2 LimVitOaNtion CH 1 NO G2 tOemvepr. LCimuirtraetinotn DIAnels OOFpeFn S lotaatde OL & Chan CH 2 CS_ R DIS T VSENSEH ON C CS1 Current Sense OUT2 CS2 OUT1 OVERLOAD PROTECTION LOGIC (ACTIVE POWER LIMITATION) GND T able 1. Pin function Name Function V Battery connection. CC OUTPUT Power output. n Ground connection. Must be reverse battery protected by an external GND diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls INPUT n output switch state. CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current. n CS_DIS Active high CMOS compatible pin, to disable the current sense pin. 5/37

Block diagram and pin description VND5E160AJ-E Figure 2. Configuration diagram (top view) TAB = V cc GND 1 12 N.C. INPUT2 2 11 OUTPUT2 INPUT1 3 10 OUTPUT2 CURRENT SENSE1 4 9 OUTPUT1 CURRENT SENSE2 5 8 OUTPUT1 CS_DIS 6 7 N.C. PowerSSO-12 Table 2. Suggested connections for unused and not connected pins Connection / pin Current sense N.C. Output Input CS_DIS Floating Not allowed X X X X Through 1k Through 22k Through 10k Through 10k To ground X resistor resistor resistor resistor 6/37

VND5E160AJ-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions I S V CC V CC V Fn ICSD OUTPUT1 IOUT1 CS_DIS V V OUT1 CSD I CURRENT ISENSE1 IN1 SENSE1 V INPUT1 VSENSE1 IN1 I I OUT2 IN2 OUTPUT2 INPUT2 VOUT2 VIN2 CURRENT ISENSE2 SENSE2 GND V SENSE2 I GND Note: V = V - V during reverse battery condition. Fn OUTn CC 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. T able 3. Absolute maximum ratings Symbol Parameter Value Unit V DC supply voltage 41 V CC -V Reverse DC supply voltage 0.3 V CC - I DC reverse ground pin current 200 mA GND I DC output current Internally limited A OUT - I Reverse DC output current 6 A OUT I DC input current -1 to 10 mA IN I DC current sense disable input current -1 to 10 mA CSD -I DC reverse CS pin current 200 mA CSENSE V -41 V V Current sense maximum voltage CC CSENSE +V V CC 7/37

Electrical specifications VND5E160AJ-E Table 3. Absolute maximum ratings (continued) Symbol Parameter Value Unit Maximum switching energy (single pulse) E 34 mJ MAX (L=12mH; R =0; V =13.5V; T =150ºC; I = I (Typ.) ) L bat jstart OUT limL Electrostatic discharge (Human Body Model: R=1.5K C=100pF) - INPUT 4000 V V - CURRENT SENSE 2000 V ESD - CS_DIS 4000 V - OUTPUT 5000 V - VCC 5000 V V Charge device model (CDM-AEC-Q100-011) 750 V ESD T Junction operating temperature -40 to 150 °C j T Storage temperature -55 to 150 °C stg 2.2 Thermal data T able 4. Thermal data Symbol Parameter Max. value Unit R Thermal resistance junction-case (With one channel ON) 8 °C/W thj-case R Thermal resistance junction-ambient See Figure36 °C/W thj-amb 8/37

VND5E160AJ-E Electrical specifications 2.3 Electrical characteristics Values specified in this section are for 8V<V <28V; -40°C<T<150°C, unless otherwise CC j stated. T able 5. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit V Operating supply voltage 4.5 13 28 V CC V Undervoltage shutdown 3.5 4.5 V USD Undervoltage shutdown V 0.5 V USDhyst hysteresis I = 1A; T= 25°C 160 m OUT j R On state resistance (1) I = 1A; T= 150°C 320 m ON OUT j I = 1A; V = 5V; T= 25°C 210 m OUT CC j V Clamp voltage I = 20 mA 41 46 52 V clamp S Off State; V = 13V; T= 25°C; CC j IS Supply current VIN=VOUT=VSENSE=VCSD=0V 2(2) 5(2) µA On State; VCC=13V; VIN=5V; IOUT=0A 3 6 mA I Off state output VIN=VOUT=0V; VCC=13V; Tj=25°C 0 0.01 3 µA L(off1) current(1) V =V =0V; V =13V; T=125°C 0 5 IN OUT CC j Output - V diode V CC -I = 0.6A; T=150°C 0.7 V F voltage(1) OUT j 1. For each channel. 2. PowerMOS leakage included. Table 6. Switching (V =13V, T=25°C) CC j Symbol Parameter Test conditions Min. Typ. Max. Unit t Turn- On delay time R = 13 (see Figure 6.) 10 µs d(on) L t Turn- Off delay time R = 13 (see Figure 6.) 15 µs d(off) L Turn- On voltage See (dV /dt) R = 13 V/µs OUT on slope L Figure 26. Turn- Off voltage See (dV /dt) R = 13 V/µs OUT off slope L Figure 28. Switching energy W R = 13 (see Figure 6.) 0.03 mJ ON losses during twon L Switching energy W R = 13 (see Figure 6.) 0.02 mJ OFF losses during twoff L 9/37

Electrical specifications VND5E160AJ-E T able 7. Logic inputs Symbol Parameter Test conditions Min. Typ. Max. Unit V Input low level voltage 0.9 V IL I Low level input current V = 0.9V 1 µA IL IN V Input high level voltage 2.1 V IH I High level input current V = 2.1V 10 µA IH IN V Input hysteresis voltage 0.25 V I(hyst) I = 1mA 5.5 7 V V Input clamp voltage IN ICL I = -1mA -0.7 V IN V CS_DIS low level voltage 0.9 V CSDL I Low level CS_DIS current V = 0.9V 1 µA CSDL CSD V CS_DIS high level voltage 2.1 V CSDH I High level CS_DIS current V = 2.1V 10 µA CSDH CSD V CS_DIS hysteresis voltage 0.25 V CSD(hyst) I = 1mA 5.5 7 V V CS_DIS clamp voltage CSD CSCL I = -1mA -0.7 V CSD Table 8. Protections and diagnostics (1) Symbol Parameter Test conditions Min. Typ. Max. Unit V = 13V 7 10 14 A I DC short circuit current CC limH 5V<V <28V 14 A CC I Short circuit current VCC= 13V; 2.5 A limL during thermal cycling T <T<T R j TSD T Shutdown temperature 150 175 200 °C TSD T Reset temperature T + 1 T + 5 °C R RS RS T Thermal reset of STATUS 135 °C RS Thermal hysteresis T 7 °C HYST (T -T ) TSD R Turn-Off output voltage V I = 1A; V = 0; L= 20mH V -41 V -46 V -52 V DEMAG clamp OUT IN CC CC CC I = 0.03A; Output voltage drop OUT V T= -40°C...150°C 25 mV ON limitation j (see Figure 8.) 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. 10/37

VND5E160AJ-E Electrical specifications T able 9. Current sense (8V<VCC<18V) Symbol Parameter Test conditions Min. Typ. Max. Unit I = 0.025A; V = 0.5V; V =0V; K I /I OUT SENSE CSD 0 OUT SENSE T= -40°C...150°C 270 520 730 j I = 0.35A; V =0.5V; V =0V; OUT SENSE CSD T= -40°C...150°C 345 470 610 K I /I j 1 OUT SENSE I =0.35A; V =0.5V; V =0V; OUT SENSE CSD T= 25°C...150°C 370 470 540 j I = 0.35A; V = 0.5V; OUT SENSE Current sense ratio dK /K (1) V =0V; -13 13 % 1 1 drift CSD T = -40 °C to 150 °C J I = 0.5A; V = 4V; V = 0V; OUT SENSE CSD T= -40°C...150°C 370 460 550 K I /I j 2 OUT SENSE I = 0.5A; V = 4V; V = 0V; OUT SENSE CSD T= 25°C...150°C 390 460 510 j I = 0.5 A; V = 4 V; OUT SENSE Current sense ratio dK /K (1) V = 0V; -8 8 % 2 2 drift CSD T = -40 °C to 150 °C J I = 1.5A; V =4V; V =0V; OUT SENSE CSD T= -40°C...150°C 400 430 470 K I /I j 3 OUT SENSE I =1.5A; V =4V; V =0V; OUT SENSE CSD T= 25°C...150°C 410 430 460 j I = 1.5 A; V = 4 V; OUT SENSE Current sense ratio dK /K (1) V =0V; -4 4 % 3 3 drift CSD T = -40 °C to 150 °C J I =0A; V =0V; OUT SENSE V =5V; V =0V; T=-40°C...150°C 0 1 µA CSD IN j I Analog sense VCSD=0V; VIN=5V; Tj=-40°C...150°C 0 2 µA SENSE0 leakage current I =0.6A; V =0V; OUT SENSE V =5V; V =5V; T= -40°C...150°C 0 1 µA CSD IN j Openload ON state V = 5V, 8V<V <18V I current detection IN CC 1 5 mA OL I = 5 µA threshold SENSE Max analog V senseoutput I =1.5A; V =0V; 5 V SENSE OUT CSD voltage Analog sense V (2) output voltage in V =13V; R = 3.9K 8 V SENSEH CC SENSE fault condition Analog sense I (2) output current in V =13V; V = 5V; 9 mA SENSEH CC SENSE fault condition 11/37

Electrical specifications VND5E160AJ-E Table 9. Current sense (8V<VCC<18V) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Delay response V <4V, 0.08A<Iout<1.5A SENSE time from falling t I =90% of I 40 100 µs DSENSE1H edge of CS_DIS SENSE SENSEmax (see Figure 4.) pin Delay response V <4V, 0.08A<Iout<1.5A SENSE time from rising t I =10% of I 5 20 µs DSENSE1L edge of CS_DIS SENSE SENSEmax (see Figure 4.) pin Delay response VSENSE<4V, 0.08A<Iout<1.5A tDSENSE2H time from rising ISENSE=90% of ISENSE max 30 150 µs edge of INPUT pin (see Figure 4.) Delay response time between rising VSENSE<4V, t edge of output ISENSE =90% of ISENSEMAX, 110 (cid:0)(cid:0)µ DSENSE2H current and rising I =90% of I s OUT OUTMAX edge of current I = 1.5A (see Figure7) OUTMAX sense Delay response VSENSE<4V, 0.08A<Iout<1.5A t time from falling I =10% of I 80 250 µs DSENSE2L SENSE SENSEmax edge of INPUT pin (see Figure 4.) 1. Parameter guaranteed by design; it is not tested. 2. Fault condition includes: power limitation, overtemperature and open load OFF state detection. T able 10. Openload detection (8V<V <18V) CC Symbol Parameter Test conditions Min. Typ. Max. Unit Openload Off state See V voltage detection V = 0 V 2 4 V OL IN Figure5 threshold Output short circuit to t V detection delay at See Figure5 180 1200 µs DSTKON CC turn Off I Off state output current VIN=0V; VSENSE=0V -120 0 µA L(off2)r at VOUT = 4V VOUT rising from 0V to 4V I Off state output current VIN=0V; VSENSE=VSENSEH -50 90 µA L(off2)f at VOUT = 2V VOUT falling from VCC to 2V Delay response from td_vol output rising edge to VOUT= 4 V; VIN= 0V 20 µs VSENSE rising edge in VSENSE= 90% of VSENSEH open-load 12/37

VND5E160AJ-E Electrical specifications Figure 4. Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L Figure 5. Openload Off-state delay timing OUTPUT STUCK TO V CC V IN V > V OUT OL V SENSEH V CS t DSTKON Figure 6. Switching characteristics V OUT t t Won Woff 90% 80% dVOUT/dt(on) dVOUT/dt(off) tr 10% tf t INPUT td(on) td(off) t 13/37

Electrical specifications VND5E160AJ-E Figure 7. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) V IN t DSENSE2H t I OUT I OUTMAX 90% I OUTMAX t I SENSE I SENSEMAX 90% I SENSEMAX t Figure 8. Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Iout Von/Ron(T) 14/37

VND5E160AJ-E Electrical specifications Figure 9. I / I vs. I out sense out I / I out sense 700 650 max Tj = -40 °C to 150 °C 600 max Tj = 25 °C to 150 °C 550 500 typical value 450 min Tj = 25 °C to 150 °C 400 350 min Tj = -40 °C to 150 °C 300 250 200 0,35 0,58 0,81 1,04 1,27 1,5 I (A) OUT Figure 10. Maximum current sense ratio drift vs load current dk/k(%) 15 10 5 0 -5 -10 -15 0,35 0,58 0,81 1,04 1,27 1,5 IOUT (A) Note: Parameter guaranteed by design; it is not tested. 15/37

Electrical specifications VND5E160AJ-E Table 11. Truth table Conditions Input Output Sense (V =0V)(1) CSD L L 0 Normal operation H H Nominal L L 0 Overtemperature H L V SENSEH L L 0 Undervoltage H L 0 H X Nominal (no power limitation) Overload H Cycling V SENSEH (power limitation) Short circuit to GND L L 0 (Power limitation) H L V SENSEH Open load OFF State L H V (with external pull up) SENSEH Short circuit to V CC L H V SENSEH (external pull up H H < Nominal disconnected) Negative output voltage L L 0 clamp 1. If the V is high, the SENSE output is at a high impedance, its potential depends on leakage currents CSD and external circuit. 16/37

VND5E160AJ-E Electrical specifications T able 12. Electrical transient requirements Burst cycle/pulse ISO 7637-2: Test levels(1) Number of repetition time Delays and 2004(E) pulses or Impedance Test pulse test times III IV Min. Max. 1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10 2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2 3a -100V -150V 1h 90ms 100ms 0.1µs, 50 3b +75V +100V 1h 90ms 100ms 0.1µs, 50 4 -6V -7V 1 pulse 100ms, 0.01 5b(2) +65V +87V 1 pulse 400ms, 2 ISO 7637-2: Test level results 2004E Test pulse III VI 1 C C 2a C C 3a C C 3b C C 4 C C 5b(2) C C Class Contents C All functions of the device performed as designed after exposure to disturbance. One or more functions of the device did not perform as designed after exposure to E disturbance and cannot be returned to proper operation without replacing the device. 1. The above test levels must be considered referred to V =13.5V except for pulse 5b. CC 2. Valid in case of external load dump clamp: 40V maximum referred to ground. 17/37

Electrical specifications VND5E160AJ-E 2.4 Waveforms Figure 11. Normal operation Normal operation INPUT Nominal load Nominal load I OUT V SENSE V CS_DIS Figure 12. Overload or Short to GND Overload or Short to GND INPUT Power Limitation ILimH > Thermal cycling I > LimL I OUT V SENSE V CS_DIS 18/37

VND5E160AJ-E Electrical specifications Figure 13. Intermittent Overload Intermittent Overload INPUT Overload I > LimH Nominal load I > LimL I OUT V > SENSEH V SENSE V CS_DIS Figure 14. OFF-State Open Load with external circuitry OFF-State Open Load with external circutry INPUT V > V OUT OL V V OL OUT I OUT V > SENSEH t DSTK(on) V SENSE V CS_DIS 19/37

Electrical specifications VND5E160AJ-E Figure 15. Short to V CC Short to V CC Resistive Hard Short to V Short to V CC CC V > V OUT OL V V OL OUT I OUT tDSTK(on) tDSTK(on) V CS_DIS Figure 16. T evolution in Overload or Short to GND J T evolution in J Overload or Short to GND INPUT Self-limitation of fast thermal transients T TSD T HYST T R T J_START T J Power Limitation I > LimH < I LimL I OUT 20/37

VND5E160AJ-E Electrical specifications 2.5 Electrical characteristics curves Figure 17. Off state output current Figure 18. High level input current Iloff (nA) Iih (µA) 300 5 4,5 250 Off State 4 Vin=2.1V Vcc=13V Vin=Vout=0V 3,5 200 3 150 2,5 2 100 1,5 1 50 0,5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 19. Input clamp voltage Figure 20. Input low level Vicl (V) Vil (V) 7 2 6,8 1,8 lin=1mA 6,6 1,6 6,4 1,4 6,2 1,2 6 1 5,8 0,8 5,6 0,6 5,4 0,4 5,2 0,2 5 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 21. Input high level Figure 22. Input hysteresis voltage Vih (V) Vihyst (V) 4 1 0,9 3,5 0,8 3 0,7 2,5 0,6 2 0,5 0,4 1,5 0,3 1 0,2 0,5 0,1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) 21/37

Electrical specifications VND5E160AJ-E Figure 23. On state resistance vs. T Figure 24. On state resistance vs. V case CC Ron (mOhm) Ron (mOhm) 300 300 Iout= 1A Tc=150°C 250 Vcc=13V 250 Tc=125°C 200 200 150 150 Tc=25°C 100 100 Tc=-40°C 50 50 -50 -25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40 Tc (°C) Vcc (V) Figure 25. Undervoltage shutdown Figure 26. Turn-On voltage slope Vusd (V) (dVout/dt )On (V/ms) 16 1000 900 14 Vcc=13V 800 12 RI=13 Ohm 700 10 600 8 500 400 6 300 4 200 2 100 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 27. I vs. T Figure 28. Turn-Off voltage slope LIMH case Ilimh (A) (dVout/dt )Off (V/ms) 20 1400 1300 Vcc=13V Vcc=13V 15 1200 RI= 13 Ohm 1100 1000 10 900 800 5 700 600 0 500 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) 22/37

VND5E160AJ-E Electrical specifications Figure 29. CS_DIS high level voltage Figure 30. CS_DIS clamp voltage Vcsdh (V) Vcsdcl(V) 4 10 9 3,5 8 Iin = 1 mA 3 7 2,5 6 2 5 4 1,5 3 1 2 0,5 1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 31. CS_DIS low level voltage Vcsdl (V) 3 2,5 2 1,5 1 0,5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 23/37

Application information VND5E160AJ-E 3 Application information Figure 32. Application schematic +5V VCC Rprot CS_DIS Dld CU Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE RGND CEXT VGND DGND Note: Channel 2 has the same internal circuit as channel 1. 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1 : resistor in the ground line (R only) GND This can be used with any type of load. The following is an indication on how to dimension the R resistor. GND 1. R  600mV / (I ) GND S(on)max 2. R V ) / (-I ) GND CC GND where -I is the DC reverse ground pin current and can be found in the absolute GND maximum rating section of the device datasheet. Power dissipation in R (when V <0: during reverse battery situations) is: GND CC P = (-V )2/R D CC GND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I becomes the sum of the S(on)max maximum On-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the R will produce a shift (I * R ) in the input thresholds and the status output GND S(on)max GND values. This shift will vary depending on how many devices are On in the case of several high side drivers sharing the same R . GND 24/37

VND5E160AJ-E Application information If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 3.1.2 Solution 2 : diode (D ) in the ground line GND A resistor (R =1kshould be inserted in parallel to D if the device drives an GND GND inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the ld V max DC rating. The same applies if the device is subject to transients on the V line CC CC that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient are present on the V line, CC the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to prot prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os: -V /I  R  (V -V -V ) / I CCpeak latchup prot OHC IH GND IHmax Calculation example: For V = - 100V and I  20mA; V  4.5V CCpeak latchup OHµC 5k  R  180k prot Recommended values: R =10k, C =10nF. prot EXT 25/37

Application information VND5E160AJ-E 3.4 Current sense and diagnostic The current sense pin performs a double function (see Figure33: Current sense and diagnostic): ● Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a know ratio K . X The current I can be easily converted to a voltage V by means of an SENSE SENSE external resistor R . Linearity between I and V is ensured up to 5V SENSE OUT SENSE minimum (see parameter V in Table9: Current sense (8V<VCC<18V)). The SENSE current sense accuracy depends on the output current (refer to current sense electrical characteristics Table9: Current sense (8V<VCC<18V)). ● Diagnostic flag in fault conditions, delivering a fixed voltage V up to a SENSEH maximum current I in case of the following fault conditions (refer to Truth table): SENSEH – Power limitation activation – Over-temperature – Short to V in OFF state CC – Open load in OFF state with additional external components. A logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices. Figure 33. Current sense and diagnostic VBAT VPU VCC Main MOSn 41V PU_CMD Overtemperature IOUT/KX + RPU OL OFF - ISENSEH VOL ILoff2r Pwr_Lim CS_DIS OUTn ILoff2f INPUTn VSENSEH CURRENT SENSEn GND Load RPROT RPD To uC ADC RSENSE VSENSE 26/37

VND5E160AJ-E Application information 3.4.1 Short to V and OFF state open load detection CC Short to V CC A short circuit between V and output is indicated by the relevant current sense pin set to CC V during the device off state. Small or no current is delivered by the current sense SENSEH during the on state depending on the nature of the short circuit. OFF state open load with external circuitry Detection of an open load in off mode requires an external pull-up resistor R connecting PU the output to a positive supply voltage V . PU It is preferable V to be switched off during the module stand-by mode in order to avoid the PU overall stand-by current consumption to increase in normal conditions, i.e. when load is connected. An external pull down resistor R connected between output and GND is mandatory to PD avoid misdetection in case of floating outputs in off state (see Figure33: Current sense and diagnostic). R must be selected in order to ensure V <V unless pulled up by the external PD OUT OLmin circuitry: V  R I V  2V OUT Pullup_OFF PD L(off2)f OLmin R 22Kis recommended. PD For proper open load detection in off state, the external pull-up resistor must be selected according to the following formula: R V R R I PD PU PU PD L(off2)r V  V 4V OUT Pullup_ON R R OLmax PU PD For the values of V ,V ,I and I see Table10: Openload detection OLmin OLmax L(off2)r L(off2)f (8V<V <18V). CC 27/37

Application information VND5E160AJ-E 3.5 Maximum demagnetization energy (V = 13.5V) CC Figure 34. Maximum turn-Off current versus inductance (for each channel) 100 10 A B C 1 A) I ( 0,1 0,1 1 L (mH) 10 100 A: T =150°C single pulse jstart B: T =100°C repetitive pulse jstart C: T =125°C repetitive pulse jstart V , I IN L Demagnetization Demagnetization Demagnetization t Note: Values are generated with R =0  L In case of repetitive pulses, T (at beginning of each demagnetization) of every pulse jstart must not exceed the temperature specified above for curves A and B. 28/37

VND5E160AJ-E Package and PC board thermal data 4 Package and PC board thermal data 4.1 PowerSSO-12 thermal data Figure 35. PowerSSO-12 PC board Note: Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 th th area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 36. R vs. PCB copper area in open box free air condition (one channel ON) thj-amb RTHj_amb(°C/W) 70 65 60 55 50 45 40 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 29/37

Package and PC board thermal data VND5E160AJ-E Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON) ZTH (°C/W) 100 Footprint 2 cm2 8 cm2 10 1 0,001 0,01 0,1 1 10 100 1000 Time (s) Equation 1: pulse calculation formula Z = R +Z 1– TH TH THtp where  = t /T P Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 (a) a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 30/37

VND5E160AJ-E Package and PC board thermal data T able 13. Thermal parameters Area/island (cm2) Footprint 2 8 R1= R7 (°C/W) 1.2 R2= R8 (°C/W) 6 R3 (°C/W) 3 R4 (°C/W) 8 8 7 R5 (°C/W) 22 15 10 R6 (°C/W) 26 20 15 C1= C7 (W.s/°C) 0.0008 C2= C8 (W.s/°C) 0.0016 C3 (W.s/°C) 0.0166 C4 (W.s/°C) 0.2 0.1 0.1 C5 (W.s/°C) 0.27 0.8 1 C6 (W.s/°C) 3 6 9 31/37

Package and packing information VND5E160AJ-E 5 Package and packing information ® 5.1 ECOPACK packages In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.2 Package mechanical data Figure 39. PowerSSO-12 package dimensions 32/37

VND5E160AJ-E Package and packing information T able 14. PowerSSO-12 mechanical data Millimeters Symbol Min. Typ. Max. A 1.250 1.620 A1 0.000 0.100 A2 1.100 1.650 B 0.230 0.410 C 0.190 0.250 D 4.800 5.000 E 3.800 4.000 e 0.800 H 5.800 6.200 h 0.250 0.500 L 0.400 1.270 k 0° 8° X 2.200 2.800 Y 2.900 3.500 ddd 0.100 33/37

Package and packing information VND5E160AJ-E 5.3 Packing information Figure 40. PowerSSO-12 tube shipment (no suffix) B Base Q.ty 100 C Bulk Q.ty 2000 Tube length (± 0.5) 532 A 1.85 A B 6.75 C (± 0.1) 0.6 All dimensions are in mm. Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.05) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2 End All dimensions are in mm. Start Top No components Components No components cover tape 500mm min 500mm min Empty components pockets saled with cover tape. User direction of feed 34/37

VND5E160AJ-E Order codes 6 Order codes T able 15. Device summary Order codes Package Tube Tape and reel PowerSSO-12 VND5E160AJ-E VND5E160AJTR-E 35/37

Revision history VND5E160AJ-E 7 Revision history T able 16. Document revision history Date Revision Changes 13-Sep-2004 1 Initial release. Document reformatted and restructured. Updated Figure2: Configuration diagram (top view) : pins 7-12 left unconnected (N.C) . Updated Table9: Current sense (8V<VCC<18V): – added k, dk/k, t ,t ,t , t , DSENSE1H DSENSE1L DSENSE2H DSENSE2H t values DSENSE2L Updated Table10: Openload detection (8V<V <18V): CC – added I , I and td_vol parameters L(off2)r L(off2)f Added Figure7: Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled). Added Figure9: Iout/ Isense vs. Iout. Added Figure10: Maximum current sense ratio drift vs load current. Table12: Electrical transient requirements : updated test level values III and IV for test pulse 5b and notes. 14-Mar-2008 2 Added Section2.4: Waveforms. Added Section2.5: Electrical characteristics curves. Updated Section3: Application information: – added Section3.4: Current sense and diagnostic Updated Section4.1: PowerSSO-12 thermal data: – changed Figure36: Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). – added Figure37: PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). – Figure38: Thermal fitting model of a double channel HSD in PowerSSO-12 : added note. – updated Table13: Thermal parameters: R3 value changed from 7 to 3 °C/W. R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W. C3 value changed from 0.05 to 0.0166 W.s/°C. 24-Sep-2013 3 Updated disclaimer. 36/37

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