VND5050AJ-E VND5050AK-E Double channel high side driver with analog current sense for automotive applications Features Max transient supply voltage V 41V CC PowerSSO-12 PowerSSO-24 Operating voltage range V 4.5 to 36V CC Max on-state resistance (per ch.) RON 50mΩ Applications Current limitation (typ) I 18A LIMH ■ All types of resistive, inductive and capacitive Off-state supply current I 2µA(1) S loads 1. Typical value with all loads connected ■ Suitable as LED driver ■ Main – Inrush current active management by Description power limitation – Very low standby current The VND5050AJ-E, VND5050AK-E is a – 3.0V CMOS compatible input monolithic device made using STMicroelectronics – Optimized electromagnetic emission VIPower M0-5 technology. It is intended for driving – Very low electromagnetic susceptibility resistive or inductive loads with one side connected to ground. Active V pin voltage – In compliance with the 2002/95/ec CC clamp protects the device against low energy european directive spikes (see ISO7637 transient compatibility ■ Diagnostic functions table). – Proportional load current sense This device integrates an analog current sense – High current sense precision for wide range which delivers a current proportional to the load currents current (according to a known ratio) when – Current sense disable CS_DIS is driven low or left open. When CS_DIS – Thermal shutdown indication is driven high, the current sense pin is in a high – Very low current sense leakage impedance condition. ■ Protections Output current limitation protects the device in – Undervoltage shutdown overload condition. In case of long overload – Overvoltage clamp duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. – Load current limitation Thermal shutdown with automatic restart allows – Self limiting of fast thermal transients the device to recover normal operation as soon as – Protection against loss of ground and loss fault condition disappears. of V CC – Thermal shutdown T able 1. Device summary – Reverse battery protection (see Application Order codes schematic on page21) Package – Electrostatic discharge protection Tube Tape and reel PowerSSO-12 VND5050AJ-E VND5050AJTR-E PowerSSO-24 VND5050AK-E VND5050AKTR-E September 2013 Doc ID 12272 Rev 10 1/37 www.st.com 1

Contents VND5050AJ-E / VND5050AK-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 PowerSSO-24™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 7. Switching (VCC=13V; Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10. Current sense (8V<V <16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CC Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 12. Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 13. Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 14. Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 15. PowerSSO-12™ thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 16. PowerSSO-24™ thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 17. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 12272 Rev 10 3/37

List of figures VND5050AJ-E / VND5050AK-E List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Delay response time between rising edge of output current and rising edge of current sense (CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. I /I vs I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OUT SENSE OUT Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 17. On-state resistance vs T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 case Figure 18. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CC Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 20. I vs T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LIMH case Figure 21. Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 22. Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 23. STAT_DIS clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 24. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25. High level STAT_DIS voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 Figure 28. PowerSSO-12™ PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24 Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on). . . . 25 Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25 Figure 32. PowerSSO-24™ PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 33. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 27 Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one channel on). . . 28 Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28 Figure 36. PowerSSO-12™ package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 37. PowerSSO-24™ package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 38. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 40. PowerSS0-24TM tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 41. PowerSSO-24TM tape and reel shipment (suffix “TR”). . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC VCC UNDERVOLTAGE CLAMP OUTPUT1 GND DRIVER 1 PwCLAMP 1 CURRENT SENSE1 INPUT1 ILIM 1 PwCLAMP 2 DRIVER 2 LOGIC PwrLIM 1 VDSLIM 1 OUTPUT2 OVERTEMP. 1 ILIM 2 CURRENT INPUT2 IOUT1 VDSLIM 2 SENSE2 K 1 OVERTEMP. 2 IOUT2 K 2 PwrLIM 2 CS_DIS T a ble 2. Pin function Name Function V Battery connection. CC OUTPUT Power output. 1,2 Ground connection. Must be reverse battery protected by an external diode/resistor GND network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output INPUT 1,2 switch state. CURRENT Analog current sense pin, delivers a current proportional to the load current SENSE 1,2 CS_DIS Active high CMOS compatible pin, to disable the current sense pin. Doc ID 12272 Rev 10 5/37

Block diagram and pin description VND5050AJ-E / VND5050AK-E Figure 2. Configuration diagram (top view) TAB = V cc VCC OUTPUT2 GND OUTPUT2 ININPPGUUNTTD12 123 111120 VOOcUUc TTPPUUTT22 IINNPPNNUU..TTCC12.. OOOOUUUUTTTTPPPPUUUUTTTT2222 CURRENT SENSE1 4 9 OUTPUT1 N.C. OUTPUT1 CURRENT SENSE2 5 8 OUTPUT1 CURRENT SENSE1 OUTPUT1 CS_DIS 6 7 Vcc CURRENT SENNS.EC2. OOUUTTPPUUTT11 CS_DIS. OUTPUT1 VCC OUTPUT1 TAB = VCC PowerSSO-12 PowerSSO-24 T a ble 3. Suggested connections for unused and not connected pins Connection/pin Current sense N.C. Output Input CS_DIS Floating N.R.(1) X X X X Through 1KΩ Through 10KΩ Through To ground X N.R.(1) resistor resistor 10KΩ resistor 1. Not recommended. 6/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions I S V CC V CC V Fn ICSD OUTPUT1 IOUT1 CS_DIS V V OUT1 CSD I CURRENT ISENSE1 IN1 SENSE1 V INPUT1 VSENSE1 IN1 I IIN2 OUTPUT2 OUT2 INPUT2 VOUT2 VIN2 CURRENT ISENSE2 SENSE2 GND V SENSE2 I GND Note: V = V - V during reverse battery condition. Fn OUTn CC 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. T able 4. Absolute maximum ratings Symbol Parameter Value Unit V DC supply voltage 41 V CC -V Reverse DC supply voltage 0.3 V CC -I DC reverse ground pin current 200 mA GND I DC output current Internally limited A OUT -I Reverse DC output current 12 A OUT I DC input current -1 to 10 mA IN I DC current sense disable input current -1 to 10 mA CSD -I DC reverse CS pin current 200 mA CSENSE V -41 V VCSENSE Current sense maximum voltage +CVC V CC Maximum switching energy E 104 mJ MAX (L= 3mH; R =0Ω; V =13.5V; T =150°C; I = I (Typ.)) L bat jstart OUT limL Doc ID 12272 Rev 10 7/37

Electrical specifications VND5050AJ-E / VND5050AK-E Table 4. Absolute maximum ratings (continued) Symbol Parameter Value Unit Electrostatic discharge (Human Body Model: R=1.5KΩ; C=100pF) 4000 V – Input 2000 V V – Current sense ESD 4000 V – CS_DIS 5000 V – Output 5000 V – V CC V Charge device model (CDM-AEC-Q100-011) 750 V ESD T Junction operating temperature -40 to 150 °C j T Storage temperature -55 to 150 °C stg 2.2 Thermal data T able 5. Thermal data Value Symbol Parameter Unit PowerSSO-12 PowerSSO-24 Thermal resistance junction case (max) R 2.7 2.7 °C/W thj-case (with one channel on) Thermal resistance junction ambient R See Figure29 See Figure33 °C/W thj-amb (max) 2.3 Electrical characteristics 8V<V <36V; -40°C<T<150°C, unless otherwise specified. CC j T a ble 6. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit V Operating supply voltage 4.5 13 36 V CC V Undervoltage shutdown 3.5 4.5 V USD Undervoltage shutdown V 0.5 V USDhyst hysteresis I = 2A; T= 25°C 50 mΩ OUT j R On-state resistance(1) I = 2A; T= 150°C 100 mΩ ON OUT j I = 2A; V = 5V; T= 25°C 65 mΩ OUT CC j V Clamp voltage I = 20mA 41 46 52 V clamp S Off-state; V =13V; T=25°C; CC j V =V =V =V =0V 2(2) 5(2) µA I Supply current IN OUT SENSE CSD S On-state; V =13V; V =5V; CC IN I = 0A 3 6 mA OUT 8/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Electrical specifications Table 6. Power section (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit V =V =0V; V =13V; IN OUT CC I Off-state output Tj= 25°C 0 0.01 3 µA L(off) current(1) V =V =0V; V =13V; IN OUT CC T= 125°C 0 5 j Output - V diode V CC -I =4A; T=150°C 0.7 V F voltage (1) OUT j 1. For each channel. 2. PowerMOS leakage included. T able 7. Switching (V =13V; T =25°C) CC j Symbol Parameter Test conditions Min. Typ. Max. Unit t Turn-on delay time R = 6.5Ω (see Figure8) 25 µs d(on) L t Turn-off delay time R = 6.5Ω (see Figure8) 35 µs d(off) L dV /dt Turn-on voltage slope R = 6.5Ω See Figure21 V/µs OUT (on) L dV /dt Turn-off voltage slope R = 6.5Ω See Figure22 V/µs OUT (off) L Switching energy losses W R = 6.5Ω (see Figure8) 0.24 mJ ON during t L won Switching energy losses W R = 6.5Ω (see Figure8) 0.2 mJ OFF during t L woff T able 8. Logic input Symbol Parameter Test conditions Min. Typ. Max. Unit V Input low level voltage 0.9 V IL I Low level input current V = 0.9V 1 µA IL IN V Input high level voltage 2.1 V IH I High level input current V = 2.1V 10 µA IH IN V Input hysteresis voltage 0.25 V I(hyst) I = 1mA 5.5 7 V V Input clamp voltage IN ICL I = -1mA -0.7 V IN V CS_DIS low level voltage 0.9 V CSDL Low level CS_DIS I V = 0.9V 1 µA CSDL current CSD CS_DIS high level V 2.1 V CSDH voltage High level CS_DIS ICSDH current VCSD= 2.1V 10 µA Doc ID 12272 Rev 10 9/37

Electrical specifications VND5050AJ-E / VND5050AK-E Table 8. Logic input (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit CS_DIS hysteresis V 0.25 V CSD(hyst) voltage I = 1mA 5.5 7 V V CS_DIS clamp voltage CSD CSCL I = -1mA -0.7 V CSD T able 9. Protections and diagnostics (1) Symbol Parameter Test conditions Min. Typ. Max. Unit V = 13V 12 18 24 A I DC short circuit current CC limH 5V<V <36V 24 A CC Short circuit current I V =13V; T <T<T 7 A limL during thermal cycling CC R j TSD T Shutdown temperature 150 175 200 °C TSD T Reset temperature T + 1 T + 5 °C R RS RS Thermal reset of T 135 °C RS STATUS Thermal hysteresis T 7 °C HYST (T -T ) TSD R Turn-off output voltage V I =2A; V =0; L=6mH V -41 V -46 V -52 V DEMAG clamp OUT IN CC CC CC I =0.1A; Output voltage drop OUT V T= -40°C...+150°C 25 mV ON limitation j (see Figure9) 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. T able 10. Current sense (8V<V <16V) CC Symbol Parameter Test conditions Min. Typ. Max. Unit I =0.05A; OUT K0 IOUT/ISENSE VSENSE=0.5V;VCSD=0V; 1270 2360 3450 T= -40°C...150°C j I =1A; V =0.5V;V =0V; OUT SENSE CSD K I /I T= -40°C 1470 2020 2610 1 OUT SENSE j T= 25°C...150°C 1570 2020 2470 j I =1A; V = 0.5V; OUT SENSE Current sense ratio dK /K (1) V =0V; -7 +7 % 1 1 drift CSD T =-40 °C to 150 °C J I =2A; V =4V;V =0V; OUT SENSE CSD K I /I T= -40°C 1740 2020 2320 2 OUT SENSE j T= 25°C...150°C 1790 2020 2250 j 10/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Electrical specifications Table 10. Current sense (8V<V <16V) (continued) CC Symbol Parameter Test conditions Min. Typ. Max. Unit I =2 A; V = 4 V; OUT SENSE Current sense ratio dK /K (1) V =0V; -4 +4 % 2 2 drift CSD T =-40 °C to 150 °C J I =4A; V =4V;V =0V; OUT SENSE CSD K I /I T=-40°C 1880 2010 2160 3 OUT SENSE j T=25°C...150°C 1900 2010 2120 j I =4 A; V = 4 V; OUT SENSE Current sense ratio dK /K (1) V =0V; -2 +2 % 3 3 drift CSD T =-40 °C to 150 °C J I =0A; V =0V; OUT SENSE V =5V; V =0V; CSD IN T=-40°C...150°C 0 1 µA j I Analog sense VCSD=0V; VIN=5V; SENSE0 leakage current T=-40°C...150°C 0 2 µA j I =2A; V =0V; OUT SENSE V =5V; V =5V; CSD IN T=-40°C...150°C 0 1 µA j Openload on-state I current detection V = 5V, I = 5 µA 4 20 mA OL IN SENSE threshold Max analog sense V I =4A; V =0V 5 V SENSE output voltage OUT CSD Analog sense output voltage in V V =13V; R =10KΩ 9 V SENSEH over temperature CC SENSE condition Analog sense output current in I V =13V; V =5V 8 mA SENSEH over temperature CC SENSE condition Delay response V <4V, 0.5A<Iout<4A SENSE time from falling t I =90% of I 50 100 µs DSENSE1H edge of CS_DIS SENSE SENSEmax (see Figure4) pin Delay response V <4V, 0.5A<Iout<4A SENSE time from rising t I =10% of I 5 20 µs DSENSE1L edge of CS_DIS SENSE SENSEmax (see Figure4) pin Delay response VSENSE<4V, 0.5A<Iout<4A t time from rising I =90% of I 80 250 µs DSENSE2H SENSE SENSEmax edge of INPUT pin (see Figure4) Doc ID 12272 Rev 10 11/37

Electrical specifications VND5050AJ-E / VND5050AK-E Table 10. Current sense (8V<V <16V) (continued) CC Symbol Parameter Test conditions Min. Typ. Max. Unit Delay response time between rising VSENSE<4V, Δt edge of output ISENSE =90% of ISENSEMAX, 65 µs DSENSE2H current and rising I =90% of I OUT OUTMAX edge of current I =2A (see Figure5) OUTMAX sense Delay response VSENSE<4V, 0.5A<Iout<4A t time from falling I =10% of I 100 250 µs DSENSE2L SENSE SENSEmax edge of INPUT pin (see Figure4) 1. Parameter guaranteed by design; it is not tested. Figure 4. Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L 12/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Electrical specifications Figure 5. Delay response time between rising edge of output current and rising edge of current sense (CS enabled) V IN Δt DSENSE2H t I OUT I OUTMAX 90% I OUTMAX t I SENSE I SENSEMAX 90% I SENSEMAX t Doc ID 12272 Rev 10 13/37

Electrical specifications VND5050AJ-E / VND5050AK-E Figure 6. I /I vs I OUT SENSE OUT IOUT/ISENSE 3000 2500 Max -40°C to 150°C Max 25°C to 150°C 2000 Typ 25°C Min 25°C to 150°C Min -40°C to 150°C 1500 1000 500 1 2 3 4 5 IOUT (A) Figure 7. Maximum current sense ratio drift vs load current dk/k(%) 10 5 0 -5 -10 1 2 3 4 IOUT (A) Note: Parameter guaranteed by design; it is not tested. 14/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Electrical specifications T able 11. Truth table Conditions Input Output Sense (V =0V)(1) CSD L L 0 Normal operation H H Nominal L L 0 Over temperature H L V SENSEH L L 0 Undervoltage H L 0 L L 0 Short circuit to GND H L 0 if T < T (Rsc ≤ 10 mΩ) H L V j if T T>S DT SENSEH j TSD L H 0 Short circuit to V CC H H < Nominal Negative output voltage L L 0 clamp 1. If the V is high, the SENSE output is at a high impedance, its potential depends on leakage currents CSD and external circuit. Figure 8. Switching characteristics VOUT tWon tWoff 90% 80% dVOUT/dt(on) dVOUT/dt(off) tr 10% tf t INPUT td(on) td(off) t Figure 9. Output voltage drop limitation V -V cc out Tj=150oC Tj=25oC Tj=-40oC V on I out V /R on on(T) Doc ID 12272 Rev 10 15/37

Electrical specifications VND5050AJ-E / VND5050AK-E T able 12. Electrical transient requirements (part 1/3) ISO 7637-2: Test levels(1) Number of Burst cycle/pulse Delays and 2004(E) pulses or repetition time impedance test pulse III IV test times 5000 1 -75V -100V 0.5 s 5 s 2 ms, 10 Ω pulses 5000 2a +37V +50V 0.2 s 5 s 50 µs, 2 Ω pulses 3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω 3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω 100 ms, 0.01 4 -6V -7V 1 pulse Ω 5b (2) +65V +87V 1 pulse 400 ms, 2 Ω 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. Table 13. Electrical transient requirements (part 2/3) ISO 7637-2: Test level results(1) 2004(E) test pulse III IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b(2) C C 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Table 14. Electrical transient requirements (part 3/3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to E disturbance and cannot be returned to proper operation without replacing the device. 16/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Electrical specifications Figure 10. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst V CC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO V CC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERLOAD OPERATION Tj TR TTSD TRS INPUT CS_DIS ILIMH LOAD CURRENT ILIML VSENSEH SENSE CURRENT current power thermal cycling limitation limitation SHORTED LOAD NORMAL LOAD Doc ID 12272 Rev 10 17/37

Electrical specifications VND5050AJ-E / VND5050AK-E 2.4 Electrical characteristics curves Figure 11. Off-state output current Figure 12. High level input current Iloff (uA) Iih (uA) 1 5 4.5 0.875 Vin=2.1V Off State 4 0.75 Vcc=13V Vin=Vout=0V 3.5 0.625 3 0.5 2.5 2 0.375 1.5 0.25 1 0.125 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 13. Input clamp voltage Figure 14. Input high level Vicl (V) Vih (V) 7 4 6.8 3.5 Iin=1mA 6.6 3 6.4 2.5 6.2 6 2 5.8 1.5 5.6 1 5.4 0.5 5.2 5 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 15. Input low level Figure 16. Input hysteresis voltage Vil (V) Vhyst (V) 2 1 1.8 0.9 1.6 0.8 1.4 0.7 1.2 0.6 1 0.5 0.8 0.4 0.6 0.3 0.4 0.2 0.2 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) 18/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Electrical specifications Figure 17. On-state resistance vs T Figure 18. On-state resistance vs V case CC Ron (mOhm) Ron (mOhm) 100 100 90 90 80 Iout=2A 80 Tc= 150°C Vcc=13V 70 70 Tc= 125°C 60 60 50 50 Tc= 25°C 40 40 30 30 Tc= - 40°C 20 20 10 10 0 0 -50 -25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40 Tc (°C) Vcc (V) Figure 19. Undervoltage shutdown Figure 20. I vs T LIMH case Vusd (V) Ilimh (A) 16 25 14 22.5 Vcc=13V 12 20 10 17.5 8 15 6 12.5 4 10 2 7.5 0 5 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope (dVout/dt)on (V/ms) (dVout/dt)off (V/ms) 1000 1000 900 900 Vcc=13V Vcc=13V 800 800 RI=6.5Ohm RI=6.5Ohm 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Doc ID 12272 Rev 10 19/37

Electrical specifications VND5050AJ-E / VND5050AK-E Figure 23. STAT_DIS clamp voltage Figure 24. Low level STAT_DIS voltage Vsdcl(V) Vsdl(V) 8 14 7 12 Isd=1mA 6 10 5 8 4 6 3 4 2 2 1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 25. High level STAT_DIS voltage Vsdh(V) 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 20/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Application information 3 Application information Figure 26. Application schematic +5V VCC Rprot CS_DIS Dld μC Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE RGND CEXT VGND DGND Note: Channel 2 has the same internal circuit as channel 1. 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (R only) GND This can be used with any type of load. The following is an indication on how to dimension the R resistor. GND 1. R ≤ 600mV / (I ). GND S(on)max 2. R ≥ (−V ) / (-I ) GND CC GND where -I is the DC reverse ground pin current and can be found in the absolute GND maximum rating section of the device datasheet. Power Dissipation in R (when V <0: during reverse battery situations) is: GND CC P = (-V )2/R D CC GND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I becomes the sum of the S(on)max maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R . GND Doc ID 12272 Rev 10 21/37

Application information VND5050AJ-E / VND5050AK-E If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 3.1.2 Solution 2: diode (D ) in the ground line GND A resistor (R =1kΩ) should be inserted in parallel to D if the device drives an GND GND inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the ld V max DC rating. The same applies if the device is subject to transients on the V line CC CC that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 Microcontroller I/Os protection If a ground protection network is used and negative transient are present on the V line, CC the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to prot prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Calculation example: For V = - 100V and I ≥ 20mA; V ≥ 4.5V CCpeak latchup OHµC 5kΩ ≤ R ≤ 180kΩ. prot Recommended values: R =10kΩ, C =10nF. prot EXT 22/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Application information 3.4 Maximum demagnetization energy (V = 13.5V) CC Figure 27. Maximum turn-off current versus inductance (for each channel) 100 A B C 10 ) A I ( 1 0,1 1 10 100 L (mH) A: T =150°C single pulse jstart B: T =100°C repetitive pulse jstart C: T =125°C repetitive pulse jstart V , I IN L Demagnetization Demagnetization Demagnetization t Note: Values are generated with R =0 Ω.In case of repetitive pulses, T (at beginning of each L jstart demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. Doc ID 12272 Rev 10 23/37

Package and PCB thermal data VND5050AJ-E / VND5050AK-E 4 Package and PCB thermal data 4.1 PowerSSO-12™ thermal data Figure 28. PowerSSO-12™ PC board Note: Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 th th area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70μm (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. R vs PCB copper area in open box free air condition (one channel thj-amb on) RTHj_amb(°C/W) 70 65 60 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 24/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Package and PCB thermal data Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on) ZTH (°C/W) 100 Footprint 2 cm2 8 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 10 100 1000 Time (s) Equation 1: pulse calculation formula ZTHδ = RTH⋅δ+ZTHtp(1–δ) where δ = t /T P Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ (a) a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Doc ID 12272 Rev 10 25/37

Package and PCB thermal data VND5050AJ-E / VND5050AK-E T able 15. PowerSSO-12™ thermal parameter Area/island (cm2) Footprint 2 8 R1= R7 (°C/W) 0.7 R2= R8 (°C/W) 2.8 R3 (°C/W) 4 R4 (°C/W) 8 8 7 R5 (°C/W) 22 15 10 R6 (°C/W) 26 20 15 C1= C7 (W.s/°C) 0.001 C2= C8 (W.s/°C) 0.0025 C3 (W.s/°C) 0.05 C4 (W.s/°C) 0.2 0.1 0.1 C5 (W.s/°C) 0.27 0.8 1 C6 (W.s/°C) 3 6 9 26/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Package and PCB thermal data 4.2 PowerSSO-24™ thermal data Figure 32. PowerSSO-24™ PC board Note: Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 th th area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 33. R vs PCB copper area in open box free air condition (one channel thj-amb on) RTHj_amb(°C/W) 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) Doc ID 12272 Rev 10 27/37

Package and PCB thermal data VND5050AJ-E / VND5050AK-E Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one channel on) Equation 2: pulse calculation formula ZTHδ = RTH⋅δ+ZTHtp(1–δ) where δ = t /T P Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™(b) b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 28/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Package and PCB thermal data T able 16. PowerSSO-24™ thermal parameter Area/island (cm2) Footprint 2 8 R1=R7 (°C/W) 0.4 R2=R8 (°C/W) 2 R3 (°C/W) 6 R4 (°C/W) 7.7 R5 (°C/W) 9 9 8 R6 (°C/W) 28 17 10 C1=C7 (W.s/°C) 0.001 C2=C8 (W.s/°C) 0.0022 C3 (W.s/°C) 0.025 C4 (W.s/°C) 0.75 C5 (W.s/°C) 1 4 9 C6 (W.s/°C) 2.2 5 17 Doc ID 12272 Rev 10 29/37

Package and packing information VND5050AJ-E / VND5050AK-E 5 Package and packing information ® 5.1 ECOPACK packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 PowerSSO-12™package information Figure 36. PowerSSO-12™ package dimensions 30/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Package and packing information Table 17. PowerSSO-12™ mechanical data Millimeters Symbol Min. Typ. Max. A 1.25 1.62 A1 0 0.1 A2 1.10 1.65 B 0.23 0.41 C 0.19 0.25 D 4.8 5.0 E 3.8 4.0 e 0.8 H 5.8 6.2 h 0.25 0.5 L 0.4 1.27 k 0° 8° X 1.9 2.5 Y 3.6 4.2 ddd 0.1 Doc ID 12272 Rev 10 31/37

Package and packing information VND5050AJ-E / VND5050AK-E 5.3 PowerSSO-24™ package information Figure 37. PowerSSO-24™ package dimensions T able 18. PowerSSO-24™ mechanical data Millimeters Symbol Min. Typ. Max. A - 2.45 A2 2.15 2.35 a1 0 0.1 b 0.33 0.51 c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.8 e3 8.8 F 2.3 G 0.1 H 10.1 10.5 32/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Package and packing information Table 18. PowerSSO-24™ mechanical data (continued) Millimeters Symbol Min. Typ. Max. h 0.4 k 0° 8° L 0.55 0.85 O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 N 10° X 4.1 4.7 Y 6.5 7.1 Doc ID 12272 Rev 10 33/37

Package and packing information VND5050AJ-E / VND5050AK-E 5.4 PowerSSO-12™ packing information Figure 38. PowerSSO-12™ tube shipment (no suffix) B Base Q.ty 100 C Bulk Q.ty 2000 Tube length (± 0.5) 532 A 1.85 A B 6.75 C (± 0.1) 0.6 All dimensions are in mm. Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.05) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape. User direction of feed 34/37 Doc ID 12272 Rev 10

VND5050AJ-E / VND5050AK-E Package and packing information 5.5 PowerSSO-24™ packing information Figure 40. PowerSS0-24TM tube shipment (no suffix) Base Qty 49 Bulk Qty 1225 C Tube length (±0.5) 532 B A 3.5 B 13.8 C (±0.1) 0.6 All dimensions are in mm. A Figure 41. PowerSSO-24TM tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Qty 1000 Bulk Qty 1000 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+2 / -0) 24.4 N (min) 100 T (max) 30.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 24 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 12 Hole Diameter D (± 0.05) 1.55 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 11.5 Compartment Depth K (max) 2.85 Hole Spacing P1 (± 0.1) 2 End All dimensions are in mm. Start Top No components Components No components cover tape 500mm min 500mm min Empty components pockets sealed with cover tape. User direction of feed Doc ID 12272 Rev 10 35/37

Revision history VND5050AJ-E / VND5050AK-E 6 Revision history T able 19. Document revision history Date Revision Changes 30-Mar-2006 1 Initial release. 14-Apr-2006 2 PowerSSO-24 dimensions table update. Reformatted 26-Apr-2007 3 Figure31 title corrected Table4: corrected E value. MAX Table10: added dk1/k1, dk2/k2, dk3/k3, Δt . DSENSE2H Added Figure5. Updated Figure6. 14-May-2007 4 Added Figure7. Table12: Updated test level values III and IV for test pulse 5b and notes. Added Section3.4: Maximum demagnetization energy (VCC = 13.5V). Figure31: Thermal fitting model of a double channel HSD in 01-Jun-2007 5 PowerSSO-12™, Figure35: Thermal fitting model of a double channel HSD in PowerSSO-24™: added notes. Updated Table10: Current sense (8V<V <16V): CC – changed t max value from 300 µs to 250µs. DSENSE2H – added I parameter. OL Updated Section4.1: PowerSSO-12™ thermal data: – Changed Figure29: Rthj-amb vs PCB copper area in open box free 04-Dec-2007 6 air condition (one channel on). – Changed Figure30: PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on). – Updated Table : : R3 value changed from 7 to 4 °C/W. R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W. Corrected typing error in Table10: Current sense (8V<V <16V): 12-Feb-2008 7 CC changed I test condition from V = 0V to V = 5V. OL IN IN Table18: PowerSSO-24™ mechanical data: – Deleted A (min) value – Changed A (max) value from 2.47 to 2.45 16-Jun-2009 8 – Changed A2 (max) value from 2.40 to 2.35 – Changed a1 (max) value from 0.075 to 0.1 – Added F and k rows Updated Figure37: PowerSSO-24™ package dimensions. Updated Table18: PowerSSO-24™ mechanical data: 21-Jul-2009 9 – Deleted G1 row – Added O, Q, S, T, and U rows 23-Sep-2013 10 Updated Disclaimer. 36/37 Doc ID 12272 Rev 10

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