VN5016AJ-E Single channel high side driver with analog current sense for automotive applications Features Max supply voltage V 41V CC Operating voltage range V 4.5 to 36V CC Max On-State resistance (per ch.) R 16 m PowerSSO-12 ON Current limitation (typ) I 65A LIMH Off state supply current IS 2 µA Application ■ Main features ■ All types of resistive, inductive and capacitive – Inrush current active management by loads power limitation – Very low stand-by current Description – 3.0V CMOS compatible input The VN5016AJ-E is a monolithic device made – Optimized electromagnetic emission using STMicroelectronics VIPower M0-5 – Very low electromagnetic susceptibility technology. It is intended for driving resistive or – In compliance with the 2002/95/EC inductive loads with one side connected to european directive ground. Active V pin voltage clamp protects the CC ■ Diagnostic functions device against low energy spikes (see ISO7637 – Proportional load current sense transient compatibility table). This device integrates an analog current sense which delivers – High current sense precision for wide range a current proportional to the load current currents (according to a known ratio) when CS_DIS is – Current sense disable driven low or left open. – Thermal shutdown indication When CS_DIS is driven high, the CURRENT – Very low current sense leakage SENSE pin is in a high impedance condition. ■ Protection Output current limitation protects the device in – Undervoltage shut-down overload condition. In case of long overload – Overvoltage clamp duration, the device limits the dissipated power to – Load current limitation safe level up to thermal shut-down intervention. – Self limiting of fast thermal transients Thermal shut-down with automatic restart allows – Protection against loss of ground and loss the device to recover normal operation as soon as of V fault condition disappears. CC – Thermal shut down – Reverse battery protection – Electrostatic discharge protection Table 1. Device summary Order codes Package Tube Tape & Reel PowerSSO-12 VN5016AJ-E VN5016AJTR-E September 2013 Rev 8 1/32 www.st.com 32

Contents VN5016AJ-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22 3.1.1 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 22 3.1.2 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 23 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 Maximum demagnetization energy (V = 13.5V) . . . . . . . . . . . . . . . . . . 24 CC 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32

VN5016AJ-E List of tables List of tables Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. Switching (V =13V, T=25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CC j Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10. Current sense (8V<V <16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CC Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 13. Thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3/32

List of figures VN5016AJ-E List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 6. IOUT/ISENSE Vs. IOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11. Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17. On state resistance vs. Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18. On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 20. Turn - On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 21. ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22. Turn - Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 25. CS_DIS low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 27. Maximum turn Off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 28. PowerSSO-12™ PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 29. Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 25 Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 26 Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 26 Figure 32. PowerSSO-12™ package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 33. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4/32

VN5016AJ-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram V CC V CC CLAMP UNDERVOLTAGE PwCLAMP DRIVER OUTPUT GND I LIM V LOGIC DSLIM Pwr INPUT LIM OVERTEMP. I OUT K CURRENT SENSE CS_DIS Table 2. Pin function Name Function V Battery connection. CC OUTPUT Power output. Ground connection. Must be reverse battery protected by an external GND diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output INPUT switch state. CURRENT Analog current sense pin, delivers a current proportional to the load current. SENSE CS_DIS Active high CMOS compatible pin, to disable the current sense pin. 5/32

Block diagram and pin description VN5016AJ-E Figure 2. Configuration diagram (top view) TAB = V cc V OUTPUT CC 1 12 GND 2 11 OUTPUT INPUT 3 10 OUTPUT CURRENT SENSE 4 9 OUTPUT CS_DIS 5 8 OUTPUT VCC 6 7 OUTPUT Table 3. Suggested connections for unused and N.C. pins Connection / Pin Current Sense N.C. Output Input CS_DIS Floating N.R.(1) X X X X Through 1K Through 10K Through 10K To ground X N.R.(1) resistor resistor resistor (1) Not recommended. 6/32

VN5016AJ-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions I S V CC V F V CC ICSD IOUT CS_DIS OUTPUT V OUT V CSD I IN INPUT I SENSE CURRENT SENSE V V SENSE IN GND I GND Note: V = V - V during reverse battery condition. Fn OUTn CC 2.1 Absolute maximum ratings Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. T able 4. Absolute maximum ratings Symbol Parameter Value Unit V DC supply voltage 41 V CC -V Reverse DC supply voltage 0.3 V CC -I DC reverse ground pin current 200 mA GND I DC output current Internally limited A OUT -I Reverse DC output current 30 A OUT I DC input current -1 to 10 mA IN I DC current sense disable input current -1 to 10 mA CSD -I DC reverse CS pin current 200 mA CSENSE V -41 V V Current sense maximum voltage CC CSENSE +V V CC Maximum switching energy E (L=0.75mH; R =0; V =13.5V; T =150ºC; 304 mJ MAX L bat jstart I = I (Typ.) ) OUT limL 7/32

Electrical specifications VN5016AJ-E Table 4. Absolute maximum ratings (continued) Symbol Parameter Value Unit Electrostatic discharge (Human Body Model: R=1.5K C=100pF) V - INPUT 4000 V V - CURRENT SENSE 2000 ESD V - CS_DIS 4000 V - OUTPUT 5000 V - VCC 5000 V Charge device model (CDM-AEC-Q100-011) 750 V ESD T Junction operating temperature -40 to 150 °C j T Storage temperature -55 to 150 °C stg 2.2 Thermal data Table 5. Thermal data Symbol Parameter Max value Unit R Thermal resistance junction-case 0.5 °C/W thj-case R Thermal resistance junction-ambient See Figure29 °C/W thj-amb 8/32

VN5016AJ-E Electrical specifications 2.3 Electrical characteristics 8V<V <36V; -40°C<T<150°C, unless otherwise specified. CC j . Table 6. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit V Operating supply voltage 4.5 13 36 V CC V Undervoltage shutdown 3.5 4.5 V USD Undervoltage Shut-down V 0.5 V USDhyst hysteresis I = 5A; T= 25°C 16 m OUT j R On state resistance I = 5A; T= 150°C 32 m ON OUT j I = 5A; V = 5V; T= 25°C 20 m OUT CC j V Clamp voltage I = 20mA 41 46 52 V clamp S Off State; V =13V; T=25°C; CC j V =V =V =V =0V 2(1) 5(1) µA IN OUT SENSE CSD I Supply current S On State; V =13V; V =5V; 1.5 3 mA CC IN I =0A OUT V =V =0V; V =13V; IN OUT CC 0 0.01 3 T=25°C I Off state output current j µA L(off) V =V =0V; V =13V; IN OUT CC 0 5 T=125°C j Output - V diode V CC I = 6A; T= 150°C 0.7 V F voltage OUT j (1) PowerMOS leakage included. T able 7. Switching (V =13V, T=25°C) CC j Symbol Parameter Test conditions Min. Typ. Max. Unit t Turn-On delay time R = 2.6 (see Figure8) 35 µs d(on) L t Turn-Off delay time R = 2.6(see Figure8) 50 µs d(off) L (dV /dt) Turn-On voltage slope R = 2.6(see Figure8) See Figure20 Vµs OUT on L (dV /dt) Turn-Off voltage slope R = 2.6(see Figure8) See Figure22 Vµs OUT off L Switching energy losses W R = 2.6(see Figure8) 1.1 mJ ON during t L won Switching energy losses W R = 2.6(see Figure8) 0.8 mJ OFF during t L woff 9/32

Electrical specifications VN5016AJ-E Table 8. Logic input Symbol Parameter Test conditions Min. Typ. Max. Unit V Input low level voltage 0.9 V IL I Low level input current V =0.9V 1 µA IL IN V Input high level voltage 2.1 V IH I High level input current V =2.1V 10 µA IH IN V Input hysteresis voltage 0.25 V I(hyst) I =1mA 5.5 7 V V Input clamp voltage IN ICL I =-1mA -0.7 V IN V CS_DIS low level voltage 0.9 V CSDL Low level CS_DIS I V =0.9V 1 µA CSDL current CSD CS_DIS high level V 2.1 V CSDH voltage High level CS_DIS I V =2.1V 10 µA CSDH current CSD CS_DIS hysteresis V 0.25 V CSD(hyst) voltage I =1mA 5.5 7 V V CS_DIS clamp voltage CSD CSCL I =-1mA -0.7 V CSD T able 9. Protections and diagnostics (1) Symbol Parameter Test conditions Min. Typ. Max. Unit V =13V 46 65 91 A I DC short circuit current CC limH 5V<V <36V 91 A CC Short circuit current I V =13V T <T<T 24 A limL during thermal cycling CC R j TSD T Shutdown temperature 150 175 200 °C TSD T Reset temperature T +1 T +5 °C R RS RS Thermal reset of T 135 °C RS STATUS Thermal hysteresis T 7 °C HYST (T -T ) TSD R Turn-Off output voltage V I =2A; V =0; L=6mH V -41 V -46 V -52 V DEMAG clamp OUT IN CC CC CC I =0.3A; Output voltage drop OUT V T= -40°C...+150°C 25 mV ON limitation j (see Figure9) (1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. 10/32

VN5016AJ-E Electrical specifications T able 10. Current sense (8V<V <16V) CC Symbol Parameter Test conditions Min. Typ. Max. Unit I =0.25A; OUT K0 IOUT/ISENSE VSENSE=0.5V;VCSD=0V; 2760 5010 7240 T= -40°C...150°C j I =4A; V =0.5V; OUT SENSE V =0V; CSD T= -40°C...150°C 3510 4560 5690 K I /I j 1 OUT SENSE I =4A; V =0.5V; OUT SENSE V =0V; CSD Tj= 25°C...150°C 3770 4560 5350 I =4A; V = 0.5V; OUT SENSE dK /K (1) Current sense ratio drift V =0V; -8 +8 % 1 1 CSD T =-40 °C to 150 °C J I =10A; V =4V; OUT SENSE V =0V; CSD T=-40°C...150°C 4180 4570 5060 K I /I j 2 OUT SENSE I =10A; V =4V; OUT SENSE V =0V; CSD Tj=25°C...150°C 4250 4570 4890 I =10A; V = 4V; OUT SENSE dK /K (1) Current sense ratio drift V =0V; -4 +4 % 2 2 CSD T =-40 °C to 150 °C J I =25A; V =4V; OUT SENSE V =0V; CSD T= -40°C...150°C 4360 4500 4700 K I /I j 3 OUT SENSE I =25A; V =4V; OUT SENSE V =0V; CSD Tj= 25°C...150°C 4380 4500 4620 I =25A; V = 4V; OUT SENSE dK /K (1) Current sense ratio drift V =0V; -3 +3 % 3 3 CSD T =-40 °C to 150 °C J I =0A; V =0V; OUT SENSE V =5V; V =0V; CSD IN T=-40°C...150°C 0 1 µA j V =0V; V =5V; CSD IN Analog sense leakage I T=-40°C...150°C 0 2 µA SENSE0 current j I =2A; V =0V; OUT SENSE V =5V; V =5V; CSD IN T=-40°C...150°C 0 1 µA j Openload ON state I current detection V = 5V, I = 5 µA 10 45 mA OL IN SENSE threshold 11/32

Electrical specifications VN5016AJ-E Table 10. Current sense (8V<V <16V) (continued) CC Symbol Parameter Test conditions Min. Typ. Max. Unit Max analog sense V I =15A; V =0V; 5 V SENSE output voltage OUT CSD Analog sense output voltage in V V =13V; R =3.9K 9 V SENSEH overtemperature CC SENSE condition Analog sense output current in I V =13V; V =5V 8 mA SENSEH overtemperature CC SENSE condition Delay response time VSENSE<4V, 1.5A<Iout<25A t from falling edge of I = 90% of I 50 100 µs DSENSE1H SENSE SENSEmax CS_DIS pin (see Figure4) Delay response time VSENSE<4V, 1.5A<Iout<25A t from rising edge of I = 10% of I 5 20 µs DSENSE1L SENSE SENSEmax CS_DIS pin (see Figure4) Delay response time VSENSE<4V, 1.5A<Iout<25A t from rising edge of I = 90% of I 270 400 µs DSENSE2H SENSE SENSEmax INPUT pin (see Figure4) Delay response time VSENSE<4V, t between rising edge of ISENSE =90% of ISENSEMAX, 280 (cid:0)(cid:0)µs DSENSE2H output current and rising I =90% of I OUT OUTMAX edge of current sense I =15A (see Figure5) OUTMAX Delay response time VSENSE<4V, 1.5A<Iout<25A t from falling edge of I =10% of I 100 250 µs DSENSE2L SENSE SENSEmax INPUT pin (see Figure4) (1) Parameter guaranteed by design; it is not tested. 12/32

VN5016AJ-E Electrical specifications Figure 4. Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L Figure 5. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) V IN t DSENSE2H t I OUT I OUTMAX 90% I OUTMAX t I SENSE I SENSEMAX 90% I SENSEMAX t 13/32

Electrical specifications VN5016AJ-E Figure 6. I /I Vs. I (see Table10 for details) OUT SENSE OUT I / I out sense 6000 max Tj = -40 °C to 150 °C 5500 5000 max Tj = 25 °C to 150 °C typical value 4500 min Tj = 25 °C to 150 °C 4000 min Tj = -40 °C to 150 °C 3500 3000 4 8 12 16 20 24 I (A) OUT Figure 7. Maximum current sense ratio drift vs load current dk/k(%) 15 10 5 0 -5 -10 -15 4 7 10 13 16 19 22 25 I (A) OUT Note: Parameter guaranteed by design; it is not tested. 14/32

VN5016AJ-E Electrical specifications Figure 8. Switching characteristics VOUT tWon tWoff 90% 80% dVOUT/dt(on) dVOUT/dt(off) tr 10% tf t INPUT td(on) td(off) t Figure 9. Output voltage drop limitation V -V cc out Tj=150oC T=25oC j T=-40oC j V on I out V /R on on(T) 15/32

Electrical specifications VN5016AJ-E T able 11. Truth table Conditions Input Output Sense (V =0V) (1) CSD L L 0 Normal operation H H Nominal L L 0 Overtemperature H L V SENSEH L L 0 Undervoltage H L 0 L L 0 Short circuit to GND H L 0 if T < T (Rsc  10 m) j TSD H L V if T > T SENSEH j TSD L H 0 Short circuit to V CC H H < Nominal Negative output voltage clamp L L 0 (1) If the V is high, the SENSE output is at a high impedance, its potential depends on leakage currents CSD and external circuit. 16/32

VN5016AJ-E Electrical specifications Table 12. Electrical transient requirements ISO 7637-2: Test levels (1) Number of Burst cycle/pulse Delays and 2004(E) pulses or repetition time Impedance Test pulse III IV test times 1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10  2a +37V +50V 5000 pulses 0.2 s 5 s 50 µs, 2  3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50  3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50  4 -6V -7V 1 pulse 100 ms, 0.01 5b (2) +65V +87V 1 pulse 400 ms, 2  ISO 7637-2: Test level results (1) 2004(E) Test pulse III IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b (2) C C (1) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. (2) Valid in case of external load dump clamp: 40V maximum referred to ground. Class Contents C All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to E disturbance and cannot be returned to proper operation without replacing the device. 17/32

Electrical specifications VN5016AJ-E Figure 10. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst VCC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERLOAD OPERATION Tj TR TTSD TRS INPUT CS_DIS ILIMH LOAD CURRENT ILIML VSENSEH SENSE CURRENT current power thermal cycling limitation limitation SHORTED LOAD NORMAL LOAD 18/32

VN5016AJ-E Electrical specifications 2.4 Electrical characteristics curves Figure 11. Off state output current Figure 12. High level input current Iloff (uA) Iih (uA) 2 5 4.5 1.75 Vin=2.1V Off State 4 1.5 Vcc=13V Vin=Vout=0V 3.5 1.25 3 1 2.5 0.75 2 1.5 0.5 1 0.25 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 13. Input clamp voltage Figure 14. Input low level Vicl (V) Vil (V) 7 4 6.75 3.5 Iin=1mA 6.5 3 6.25 2.5 6 2 5.75 1.5 5.5 1 5.25 0.5 5 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 15. Input high level Figure 16. Input hysteresis voltage Vih (V) Vhyst (V) 4 1 0.9 3.5 0.8 3 0.7 2.5 0.6 2 0.5 0.4 1.5 0.3 1 0.2 0.5 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) 19/32

Electrical specifications VN5016AJ-E Figure 17. On state resistance vs. T Figure 18. On state resistance vs. V case CC Ron (mOhm) Ron (mOhm) 50 40 45 35 Iout=5A 40 Vcc=13V 30 35 Tc= 150°C 25 30 25 20 Tc= 125°C 20 15 Tc= 25°C 15 10 10 Tc= -40°Cv 5 5 0 0 -50 -25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 40 Tc (°C) Vcc (V) Figure 19. Undervoltage shutdown Figure 20. Turn - On voltage slope Vusd (V) dVout/dt(on) (V/ms) 16 1000 900 14 Vcc=13V 800 12 RI=2.6Ohm 700 10 600 8 500 400 6 300 4 200 2 100 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 21. I vs. T Figure 22. Turn - Off voltage slope LIMH case Ilimh (A) (dVout/dt)off (V/ms) 80 1000 900 75 Vcc=13V 800 Vcc=13V Rl=2.6Ohm 70 700 65 600 60 500 400 55 300 50 200 45 100 40 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) 20/32

VN5016AJ-E Electrical specifications Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage Vcsdh (V) Vcsdcl (V) 4 8 3.5 7.5 Icsd=1mA 3 7 2.5 6.5 2 6 1.5 5.5 1 5 0.5 4.5 0 4 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 25. CS_DIS low level voltage Vcsdl (V) 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 21/32

Application Information VN5016AJ-E 3 Application Information Figure 26. Application schematic +5V VCC Rprot CS_DIS Dld µC Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE RGND Cext VGND DGND 3.1 GND protection network against reverse battery 3.1.1 Solution 1 : resistor in the ground line (R only) GND This can be used with any type of load. The following is an indication on how to dimension the R resistor. GND 1. R  600mV / (I ). GND S(on)max 2. R V ) / (-I ) GND CC GND where -I is the DC reverse ground pin current and can be found in the absolute GND maximum rating section of the device datasheet. Power Dissipation in R (when V <0: during reverse battery situations) is: GND CC P = (-V )2/R D CC GND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I becomes the sum of the S(on)max maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the R will produce a shift (I * R ) in the input thresholds and the status output GND S(on)max GND values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R . GND 22/32

VN5016AJ-E Application Information If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 3.1.2 Solution 2 : diode (D ) in the ground line GND A resistor (R =1kshould be inserted in parallel to D if the device drives an GND GND inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the ld V max DC rating. The same applies if the device is subject to transients on the V line CC CC that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient are present on the V line, CC the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to prot prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -V /I  R  (V -V -V ) / I CCpeak latchup prot OHµC IH GND IHmax Calculation example: For V = - 100V and I  20mA; V  4.5V CCpeak latchup OHµC 5k  R  180k. prot Recommended values: Rprot =10kCEXT=10nF. 23/32

Application Information VN5016AJ-E 3.4 Maximum demagnetization energy (V = 13.5V) CC Figure 27. Maximum turn Off current versus load inductance 100 A B C 10 A) I ( 1 0,1 1 L (mH) 10 100 A: T =150°C single pulse jstart B: T =100°C repetitive pulse jstart C: T =125°C repetitive pulse jstart V , I IN L Demagnetization Demagnetization Demagnetization t Note: Values are generated with R =0  L In case of repetitive pulses, T (at beginning of each demagnetization) of every pulse jstart must not exceed the temperature specified above for curves B and C. 24/32

VN5016AJ-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 PowerSSO-12™ thermal data Figure 28. PowerSSO-12™ PC board Note: Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 th th area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. R vs. PCB copper area in open box free air condition thj-amb RTHj_amb(°C/W) 65 60 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 25/32

Package and PCB thermal data VN5016AJ-E Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse 100 2 cm2 W) Footprint C/ ° H ( 8 cm2 T Z 10 1 0,1 0,0001 0,001 0,01 0,1 Time (s) 1 10 100 1000 Equation 1: pulse calculation formula Z = R +Z 1– TH TH THtp where  = t /T P Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ (a) (a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 26/32

VN5016AJ-E Package and PCB thermal data T able 13. Thermal parameter Area/island (cm2) Footprint 2 8 R1 (°C/W) 0.1 R2 (°C/W) 0.2 R3 (°C/W) 4 R4 (°C/W) 8 8 7 R5 (°C/W) 22 15 10 R6 (°C/W) 26 20 15 C1 (W.s/°C) 0.0001 C2 (W.s/°C) 0.002 C3 (W.s/°C) 0.05 C4 (W.s/°C) 0.2 0.1 0.1 C5 (W.s/°C) 0.27 0.8 1 C6 (W.s/°C) 3 6 9 27/32

Package information VN5016AJ-E 5 Package information ® 5.1 ECOPACK packages In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.2 PowerSSO-12™package information Figure 32. PowerSSO-12™ package dimensions 28/32

VN5016AJ-E Package information T a ble 14. PowerSSO-12™ mechanical data Millimeters Symbol Min. Typ. Max. A 1.250 1.620 A1 0.000 0.100 A2 1.100 1.650 B 0.230 0.410 C 0.190 0.250 D 4.800 5.000 E 3.800 4.000 e 0.800 H 5.800 6.200 h 0.250 0.500 L 0.400 1.270 k 0° 8° X 1.900 2.500 Y 3.600 4.200 ddd 0.100 29/32

Package information VN5016AJ-E 5.3 PowerSSO-12™ packing information Figure 33. PowerSSO-12™ tube shipment (no suffix) B Base Q.ty 100 C Bulk Q.ty 2000 Tube length (± 0.5) 532 A 1.85 A B 6.75 C (± 0.1) 0.6 All dimensions are in mm. Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.05) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape. User direction of feed 30/32

VN5016AJ-E Revision history 6 Revision history T able 15. Document revision history Date Revision Changes 30-Oct-2004 1 Initial release. 15-Jan-2005 2 Minor text changes. 11-May-2006 3 Document changed from Advance Data to maturity. Changes minor formatting. Added Figure27: Maximum turn Off current versus load 02-Feb-2007 4 inductance. Added new disclaimer. Table4 : updated E entries. MAX Table10 : added dk1/k1, dk2/k2, dk3/k3, t . DSENSE2H Added Figure5. Updated Figure6. Added Figure7. 02-Jul-2007 5 Table12 : updated test level values III and IV for test pulse 5b and notes. Added Section3.4: Maximum demagnetization energy (V = CC 13.5V). Figure31: Thermal fitting model of a single channel HSD in PowerSSO-12™: added notes. Updated Table10: Current sense (8V<V <16V) : CC – Changed dK /K values from ± 2 to ± 3 %. 3 3 – Added I parameter. OL – Changed t max value from 120 to 280 µs. DSENSE2H Updated Figure7: Maximum current sense ratio drift vs load current with new dK/K values. Updated Section4.1: PowerSSO-12™ thermal data: 09-Jan-2007 6 – Changed Figure29: Rthj-amb vs. PCB copper area in open box free air condition. – Changed Figure30: PowerSSO-12™ thermal impedance junction ambient single pulse. – Updated Table13: Thermal parameter: R3 value changed from 7 to 4 °C/W. R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W. Corrected typing error in Table10: Current sense (8V<V <16V) : 12-Feb-2008 7 CC changed I test condition from V = 0V to V = 5V. OL IN IN 25-Sep-2013 8 Updated disclaimer. 31/32

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