VIPer100/SP VIPer100A/ASP SMPS PRIMARY I.C. Table 1. General Features Figure 2. Package Type VDSS In RDS(on) VIPer100/SP 620V 3 A 2.5 Ω VIPer100A/ASP 700V 3 A 2.8 Ω ■ ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz PENTAWATT HV PENTAWATT HV (022Y) ■ CURRENT MODE CONTROL ) s ■ SOFT START AND SHUTDOWN CONTROL ( t c ■ AUTOMATIC BURST MODE OPERATION IN DESCRIPTION u STAND-BY CONDITION ABLE TO MEET d “BLUE ANGEL” NORM (<1w TOTAL POWER VIPer100™/100A, made o using VIPower M0 Technology, combines orn the same silicon chip a CONSUMPTION) P state-of-the-art PWM circuit together with an ■ INTERNALLY TRIMMED ZENER optimized, high veo ltage, Vertical Power MOSFET REFERENCE t (620V or 70e0V / 3A). ■ UNDERVOLTAGE LOCK-OUT WITH ol Typical applications cover offline power supplies HYSTERESIS s wbith a secondary power capability of 50 W in wide ■ INTEGRATED START-UP SUPPLY O range condition and 100W in single range or with ■ OVER-TEMPERATURE PROTECTION doubler configuration. It is compatible from both - primary or secondary regulation loop despite ■ LOW STAND-BY CURRENT ) s using around 50% less components when ■ ADJUSTABLE CURRENT LIMITAtTI(ON compared with a discrete solution. Burst mode c u operation is an additional feature of this device, d offering the ability to operate in stand-by mode Figure 1. Block Diagramo without extra components. r P OSC DRAIN e t e ON/OFF l OSCILLATOR o s SECURITY PWM b LATCH LATCH O VDD LUOVGLOIC R/SFFQ R1FSF Q S R2R3 OVERTEMP. DETECTOR 0.5V 0.5 V + 1.7 μ s 250 ns + + _ 1 V/A _ DELAY BLANKING _ _ AEMRPRLOIFRIER ACMUPRLRIEFINETR 13 V + 4.5 V 00231C F COMP SOURCE Rev 2 June 2005 1/24 www.st.com 24

VIPer100/SP - VIPer100A/ASP Table 2. Absolute Maximum Rating Symbol Parameter Value Unit Continuous Drain-Source Voltage (TJ = 25 to 125°C) V VDS for VIPer100/SP –0.3 to 620 V for VIPer100A/ASP –0.3 to 700 ID Maximum Current Internally limited A VDD Supply Voltage 0 to 15 V VOSC Voltage Range Input 0 to VDD V VCOMP Voltage Range Inpu 0 to 5 V ICOMP Maximum Continuous Current ±2 mA VESD Electrostatic Discharge (R =1.5kΩ; C=100pF) 4000 V Avalanche Drain-Source Current, Repetitive or Not Repetitive (Tc=100°C; Pulse width limited by TJ max; δ < 1%) I ) D(AR) s for VIPer100/SP 2 A ( for VIPer100A/ASP 1.4 ct A u Ptot Power Dissipation at Tc=25ºC 82d W o Tj Junction Operating Temperature Intrernally limited °C P Tstg Storage Temperature -65 to 150 °C e t e Table 3. Thermal data l o Symbol Parameter s PENTAWATT HV Unit b Rthj-case Thermal Resistance Junction-case O Max 1.4 °C/W Rthj-amb Thermal Resistance Ambient-case - Max 60 °C/W ) s ( Figure 3. Connection Diagrams (tTop View) c u d o PENTAWATT HV PENTAWATT HV (022Y) r P e t e l o s Tabble 4. Current and Voltage Convention O IDD ID VDD DRAIN IOSC - OSC 13V + VDD COMP SOURCE VDS ICOMP VOSC VCOMP FC00020 2/24

VIPer100/SP - VIPer100A/ASP Table 5. Ordering Numbers PENTAWATT HV PENTAWATT HV (022Y) VIPer100 VIPer100 (022Y) VIPer100A VIPer100A (022Y) Pins Functional Description Drain Pin (Integrated Power MOSFET Drain): Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. Suorce Pin: Power MOSFET source pin. Primary side circuit common ground connection. ) s V Pin (Power Supply): ( DD t c This pin provides two functions : u d ■ It corresponds to the low voltage supply of the control part of the circuit. If V gooes below 8V, the start- DD r up current source is activated and the output power MOSFET is switchedP off until the VDD voltage reaches 11V. During this phase, the internal current consumption is re duced, the V pin is sourcing e DD a current of about 2mA and the COMP pin is shorted to ground. Atfter that, the current source is shut e down, and the device tries to start up by switching again. l o ■ This pin is also connected to the error amplifier, in orders to allow primary as well as secondary regulation configurations. In case of primary regulatiobn, an internal 13V trimmed reference voltage is O used to maintain V at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put DD on V pin by transformer design, in order to- stuck the output of the transconductance amplifier to the DD ) high state. The COMP pin behaves as sa constant current source, and can easily be connected to the output of an optocoupler. Note that a(ny overvoltage due to regulation loop failure is still detected by the t c error amplifier through the V voltage, which cannot overpass 13V. The output voltage will be DDu somewhat higher than the dnominal one, but still under control. o Compensation Pin r P This pin providese two functions : t ■ It is the oeutput of the error transconductance amplifier, and allows for the connection of a compensation l netwoork to provide the desired transfer function of the regulation loop. Its bandwidth can be easily asdjusted to the needed value with usual components value. As stated above, secondary regulation b configurations are also implemented through the COMP pin. O ■ When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (no matter what the configuration is) to provide a burst mode operation in case of negligible output power or open load condition. OSC Pin (Oscillator Frequency): An R-C network must be connected on that to define the switching frequency. Note that despite the t t connection of R to V , no significant frequency change occurs for V varying from 8V to 15V. It t DD DD provides also a synchronisation capability, when connected to an external frequency source. 3/24

VIPer100/SP - VIPer100A/ASP Table 6. Avalance Characteristics Symbol Parameter Max Value Unit Avalanche Current, Repetitive or Not Repetitive (pulse width limited by TJ max; δ < 1%) I D(AR) for VIPer100/SP (see Figure 15) 2 A for VIPer100A/ASP (*) (see Figure 15) 1.4 A Single Pulse Avalanche Energy E (AR) (starting TJ = 25ºC, ID = ID(ar)) (*) 60 mJ Electrical Chracteristics (TJ = 25°C; V = 13V, unless otherwise specified) DD Table 7. Power Section Symbol Parameter Test Conditions Min Typ Max Unit I = 1mA; V = 0V ) D COMP s BVDS Drain-Source Voltage for VIPer100/SP 620 ( V t for VIPer100A/ASP (see Figure 8) 700 c V u V = 0V; T = 125°C d COMP j Off-State Drain o IDSS Current VDS = 620V for VIPer100/SP P r 1 mA V = 700Vfor VIPer100A/ASP 1 mA DS e ID = 2A t e for VIPer100/SP l 2.5 Ω o Static Drain-Source for VIPer100A/ASP s 2.0 2.8 Ω R DS(on) On Resistance I = 2A; T = 100°C b 2.3 D j O for VIPer100/SP 4.5 Ω for VIPer100A-/ASP 5.0 Ω ) tf Fall Time ID = 0(.2As; VIN =300V (1)Figure6 100 ns t tr Rise Time u IDc = 0.4A; VIN = 300V (1)Figure6 50 ns Coss Output Capacitancde VDS = 25V 150 pF o r P (1) On Inductive Load, Clamped. e t e l o s b O 4/24

VIPer100/SP - VIPer100A/ASP Table 8. Supply Section Symbol Parameter Test Conditions‘ Min Typ Max Unit IDDch Start-Up Charging Current VDD = 5V; VDS = 35V -2 mA (see Figure 5)(see Figure 18) V = 12V; F = 0kHz IDD0 Operating Supply Current DD SW 12 16 mA (see Figure 5) IDD1 VDD = 12V; Fsw = 100kHz 15.5 mA Operating Supply Current VDD = 12V; Fsw = 200kHz 19 mA VDDoff Undervoltage Shutdown (see Figure 5) 7.5 8 9 V VDDon Undervoltage Reset (see Figure 5) 11 12 V VDDhyst Hysteresis Start-up (see Figure 5) 2.4 3 V Table 9. Oscillator Section ) s Symbol Parameter Test Conditions‘ Min Typ Max( Unit t c R =8.2KΩ; C =2.4nF u T T d FSW OVasrciailltaiotonr Frequency Total VwDithD =R9T ±to 1 1%5;V C; T± 5% 90 P r 1o00 110 KHz (see Figure 9)(see Figure 12) e VOSCIH Oscillator Peak Voltage e t 7.1 V l VOSCIL Oscillator Valley Voltage o 3.7 V s b Table 10. Error Amplifier Section O Symbol Parameter T-est Conditions‘ Min Typ Max Unit ) s VDDREG VDD Regulation Point (ICOMP=0mA (see Figure 4) 12.6 13 13.4 V t ΔVDDreg Total Variation u c Tj=0 to 100°C 2 % d From Input =V to o DD r Output = V GBW Unity Gain BP andwidth COMP 150 KHz COMP pin is open e (see Figure 13) t e l COMP pin is open AVOL o Open Loop Voltage Gain 45 52 dB s (see Figure 13) b O Gm DC Transconductance VCOMP=2.5V(see Figure 4) 1.1 1.5 1.9 mA/V VCOMPLO Output Low Level ICOMP=-400µA; VDD=14V 0.2 V VCOMPHI Output High Level ICOMP=400µA; VDD=12V 4.5 V ICOMPLO Output Low Current Capability VCOMP=2.5V; VDD=14V -600 µA Output High Current ICOMPHI Capability VCOMP=2.5V; VDD=12V 600 µA 5/24

VIPer100/SP - VIPer100A/ASP Table 11. PWM Comparator Section Symbol Parameter Test Conditions‘ Min Typ Max Unit HID ΔVCOMP / ΔIDPEAK VCOMP = 1 to 3 V 0.7 1 1.3 V/A VCOMPoff VCOMP Offset IDPEAK = 10mA 0.5 V IDpeak Peak Current Limitation VDD = 12V; COMP pin open 3 4 5.3 A Current Sense Delay to Turn- td Off ID = 1A 250 ns tb Blanking Time 250 360 ns ton(min) Minimum On Time 350 1200 ns Table 12. Shutdown and Overtemperature Section Symbol Parameter Test Conditions‘ Min Typ Max Unit ) VCOMPth Restart Threshold (see Figure 7) 0.5 s V ( tDISsu Disable Set Up Time (see Figure 7) 1.7 c5t µs u Ttsd TTehmerpmearal tSuhreutdown (see Figure 7) 140 1o70d °C r Thyst Thermal Shutdown Hysteresis (see Figure 7) P 40 °C e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 6/24

VIPer100/SP - VIPer100A/ASP Figure 4. V Regulation Point Figure 5. Undervoltage Lockout DD I COMP I Slope = DD I Gm in mA/V COMPHI IDD0 V DD 0 VDDhyst VDS= 35 V Fsw = 0 V I VDDoff VDDon DD COMPLO IDDch V DDreg FC00150 FC00170 Figure 6. Transition Time Figure 7. Shutdown Action ) VOSC s ( t c ID u t d VCOMP o tDISsu 10% Ipeak r t P VDS VCOMPth e t 90% VD t e ID l 10% VD o t s tf tr b t FC00160 O ENABLE ENABLE - DISABLE ) FC00060 Figure 8. Breakdown Voltage vs. Temsperature Figure 9. Typical Frequency Variation ( t c FC00180 FC00190 1.15 u 1 (%) BVDSS d (Normalized) o 0 1.1 r P -1 e 1.0t5 -2 e ol -3 s 1 b -4 O -5 0.95 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) 7/24

VIPer100/SP - VIPer100A/ASP Figure 10. Start-Up Waveforms ) s ( t c u d o r P e t e l o Figure 11. Over-temperature Protection s b O T T J - tsc T -T ) tsd hyst s ( t c t u d V dd o V r ddon P V ddoff e t t e I l d o s b O t V comp t SC10191 8/24

VIPer100/SP - VIPer100A/ASP Figure 12. Oscillator VDD For R >1.2KΩ Rt t and OSC C ≥ 15nF if F ≤ 40KHz t SW F = --2---.--3----⋅⎛1–------5---5---0--------⎞ CLK SW RC ⎝ R –150⎠ t t t Ω Ct 0 6 3 ~ FC00050 Ct ) s ( t c u Forbidden area d o r P 880 Ct(nF) = Fsw(kHze) 22nF t e 15nF ol s b O Forbidden area - ) s ( t 40kHz Fsw c u d Oscillator frequency vs Rt and Ct o FFCC0000003300 r1,000 P Ct = 1.5 nF e t 500 e Ct = 2.7 nF l o 300 s Hz) Ct = 4.7 nF b k 200 O y ( c n e Ct = 10 nF u 100 q e Fr 50 30 1 2 3 5 10 20 30 50 Rt (kΩ) 9/24

VIPer100/SP - VIPer100A/ASP Figure 13. Error Amplifier frequency Response FC00200 60 RCOMP = +∞ RCOMP = 270k ) 40 B RCOMP = 82k d ( n RCOMP = 27k i a G 20 RCOMP = 12k e g a t l o V 0 ) s ( (20) t c 0.001 0.01 0.1 1 10 100 1,000 u Frequency (kHz) d o r P e t e l Figure 14. Error Amplifier Phase Response o s b O FC00210 200 - ) s ( RCOMP = +∞ t 150 c RCOMP = 270k u d RCOMP = 82k o °) 10P 0r RCOMP = 27k ( RCOMP = 12k e es t a e h 50 P l o s b O 0 (50) 0.001 0.01 0.1 1 10 100 1,000 Frequency (kHz) 10/24

VIPer100/SP - VIPer100A/ASP Figure 15. Avalanche Test Circuit L1 1mH 2 3 VDD DRAIN Q1 - 2 x STHV102FI in parallel 1 OSC R1 13V + BT1 0 to 20V COMP SOURCE 47 GENERATOR INPUT 5 4 500us PULSE C1 U1 BT2 47uF VIPer100 12V 16V ) R2 R3 s 1k 100 ( t c u d oFC00195 r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 11/24

VIPer100/SP - VIPer100A/ASP Figure 16. Offline Power Supply With Auxiliary Supply Feedback F1 BR1 TR2 C1 TR1 AC IN D2 L2 +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN - U1 ) OSC s 13V + VIPer100 ( t c COMP SOURCE C5 u d C6 C11 o r R3 P FC00081 e t e l o s Figure 17. Offline Power Supply With Optocoupler Fbeedback O F1 - TR2 BR1 AC IN C1 s ) TR1 D2 L2 R9 ( D1 +Vcc ct C2 C7 C9 u R1 d C3 GND D3 o C10 r R7 P C4 e t R2 e VDD DRAIN s ol OSC 13V -+ VIUP1er100 b C5 COMP SOURCE O C6 C11 R6 R3 ISO1 R4 C8 U2 R5 FC00091 12/24

VIPer100/SP - VIPer100A/ASP Operation Description: Current Mode Topology: The current mode control method, like the one integrated in the VIPer100/100A, uses two control loops - an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage V proportional to this current. When V reaches V (the S S COMP amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in case there is a short circuit. During the first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on V is no lo nger DD ) correct. For specific applications the maximum peak current internally set can be overridden by exsternally ( limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWMt comparator c output for a short time after the integrated Power MOSFET is switched on. This fuunction prevents anomalous or premature termination of the switching pulse in case there are currendt spikes caused by o primary side capacitance or secondary side rectifier reverse recovery time. r P Stand-by Mode e t Stand-by operation in nearly open load conditions automatically leaeds to a burst mode operation allowing voltage regulation on the secondary side. The transition from onlormal operation to burst mode operation happens for a power P given by : s STBY b 1 2 F P = ---L I STBY SW Where: O STBY 2 P L is the primary inductance of the transformer.- F is the normal switching frequency. P SW ) I is the minimum controllable current,s corresponding to the minimum on time that the device is able STBY ( to provide in normal operation. This ccturrent can be computed as : (tb+td)VIN I = ----------------------------- u STBY L p d t + t is the sum of the bolanking time and of the propagation time of the internal current sense and b d r comparator, and reprPesents roughly the minimum on time of the device. Note: that PSTBY may be affected by the eff iciency of the converter at low load, and must include the power drawn on the primary e auxiliary voltage. t e As soon las the power goes below this limit, the auxiliary secondary voltage starts to increase above the o 13V sregulation level, forcing the output voltage of the transconductance amplifier to low state (VCOMP < Vb ). This situation leads to the shutdown mode where the power switch is maintained in the Off COMPth O state, resulting in missing cycles and zero duty cycle. As soon as V gets back to the regulation level DD and the V threshold is reached, the device operates again. The above cycle repeats indefinitely, COMPth providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input main supply lines. This mode of operation allows the VIPer100/100A to meet the new German "Blue Angel" Norm with less than 1W total power consumption for the system when working in stand-by mode. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and low output current drawn in such conditions.The normal operation resumes automatically when the power gets back to higher levels than P . STBY 13/24

VIPer100/SP - VIPer100A/ASP High Voltage Start-up Current Suorce An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the V pin. As soon DD as the voltage on this pin reaches the high voltage threshold V of the UVLO logic, the device DDon becomes active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the V pin through the auxiliary winding of the DD transformer, as shown on (see Figure 18). In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage supply current to the V pin (i.e. short circuit on the output of the converter), the external capacitor DD discharges to the low threshold voltage V of the UVLO logic, and the device goes back to the inactive DDoff state where the internal circuits are in standby mode and the start-up current source is activated. The converter enters a endless start-up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPer100/100A tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage. ) This low value start-up duty cycle prevents the application of stress to the output rectifiers as wesll as the ( transformer when a short circuit occurs. t c u The external capacitor C on the V pin must be sized according to the time needed by the converter VDD DD d to start up, when the device starts switching. This time tSS depends on many paroameters, among which transformer design, output capacitors, soft start feature, and compensation nertwork implemented on the P COMP pin. The following formula can be used for defining the minimum capacitor needed: I where: t e CVDD>V-----D----D---t-S---S---- e DDhyst IDD is the consumption current on the VDD pin when switching.o Rlefer to specified IDD1 and IDD2 values. s tSS is the start up time of the converter when the deviceb begins to switch. Worst case is generally at full load. O V is the voltage hysteresis of the UVLO lo-gic (refer to the minimum specified value). DDhyst ) The soft start feature can be implemented son the COMP pin through a simple capacitor which will be also ( used as the compensation network. Int this case, the regulation loop bandwidth is rather low, because of c the large value of this capacitor. Iun case a large regulation loop bandwidth is mandatory, the schematics of (see Figure 19) can be usded. It mixes a high performance compensation network together with a separate high value soft sotart capacitor. Both soft start time and regulation loop bandwidth can be r adjusted separately. P If the device is inetentionally shut down by tying the COMP pin to ground, the device is also performing start-up cycleets, and the VDD voltage is oscillating between VDDon and VDDoff. l This vooltage can be used for supplying external functions, provided that their consumption does not s exceed 0.5mA. (see Figure 20) page 17 shows a typical application of this function, with a latched b O shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the input voltage is removed. 14/24

VIPer100/SP - VIPer100A/ASP Figure 18. Behaviour of the high voltage current source at start-up VDD 2 mA 3 mA DRAIN VDD VDDon 15 mA 1 mA 15 mA VDDoff CVDD Ref. t UNDERVOLTAGE Auxiliary primary LOCK OUT LOGIC winding VIPer100 SOURCE Start up duty cycle ~ 12% FC00100 ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 15/24

VIPer100/SP - VIPer100A/ASP Transconductance Error Amplifier The VIPer100/100A includes a transconductance error amplifier. Transconductance Gm is the change in output current (I ) versus change in input voltage (V ). Thus: COMP DD ∂I COMP G = ------------------------ m ∂V DD The output impedance Z at the output of this amplifier (COMP pin) can be defined as: COMP ∂V ∂V COMP 1 COMP Z = -------------------------- = ---------×-------------------------- COMP ∂I G ∂V COMP m DD This last equation shows that the open loop gain A can be related to G and Z : VOL m COMP A = G x Z VOL m COMP where G value for VIPer100/100A is 1.5 mA/V typically. m G is defined by specification, but Z and therefore A are subject to large tolerances. An m COMP VOL impedance Z can be connected between the COMP pin and ground in order to define the tr)ansfer s function F of the error amplifier more accurately, according to the following equation (very sim(ilar to the t one above): c u F = Gm x Z(S) d (S) o The error amplifier frequency response is reported in figure 10 page 8 for dirfferent values of a simple P resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal Z of about 330KΩ. More complex impedance can be conneected on the COMP pin to achieve COMP t different compensation level. A capacitor will provide an integrator feunction, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher froelquency, insuring a correct phase margin. This configuration is illustrated in (see Figure 21) page 17.s b As shown in (see Figure 21) an additional noise filterOing capacitor of 2.2nF is generally needed to avoid any high frequency interference. - Is also possible to implement a slope comp)ensation when working in continuous mode with duty cycle s higher than 50%. (see Figure 22) sho(ws such a configuration. Note: R1 and C2 build the classical t compensation network, and Q1 is cinjecting the slope compensation with the correct polarity from the u oscillator sawtooth. d o External Clock Syncrhronization: P The OSC pin prov ides a synchronisation capability when connected to an external frequency source. e (see Figure 23) page17 shows one possible schematic to be adapted, depending the specific needs. If t e the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for l minimizoing consumption. The optocoupler must be able to provide 20mA through the optotransistor. s b O Primary Peak Current Limitation The primary I current and, consequently, the output power can be limited using the simple circuit DPEAK shown in (see Figure 24) page 18. The circuit based on Q1, R and R clamps the voltage on the COMP 1 2 pin in order to limit the primary peak current of the device to a value: V –0.5 COMP I = ------------------------------------ where: DPEAK H ID R1+R2 V = 0.6×-------------------- COMP R 2 The suggested value for R +R is in the range of 220KΩ. 1 2 16/24

VIPer100/SP - VIPer100A/ASP Over-Temperature Protection Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is 170ºC. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 11) page 8.. Figure 19. Mixed Soft Start and Compensation Figure 20. Latched Shut Down D2 U1 UVI1PER100 D3 R1 VIPER100 VDD DRAIN VDD DRAIN - Q2 - OSC R3 OSC 13V + 13V + COMP SOURCE COMP SOURCE D1 AUXILIARY R3 R2 WINDING C4 R1 R4 R2 Shutdown Q1 D1 +C3 C1 +C2 ) s ( t FcC00110 FC00131 u d o Figure 21. Typical Compensation Network Figure 22. Slope Comprensation P U1 e VIPER100 t VDD DRAIN R2 e R1 U1 - l VIPER100 OSC o 13V + s VDD - DRAIN COMP SOURCE b OSC 13V + O COMP SOURCE C2 R1 - C2 ) Q1 C3 C1 s ( t C1 R3 c u d oFC00121 FC00141 r P Figure 23. Exteer nal Clock Sinchronisation Figure 24. Current Limitation Circuit Example t e l U1 o VIPER100 s VDD DRAIN b - O U1 OSC VIPER100 13V + VDD DRAIN COMP SOURCE - OSC 13V + COMP SOURCE R1 10 kΩ Q1 R2 FC00220 FC00240 17/24

VIPer100/SP - VIPer100A/ASP Figure 25. Input Voltage Surges Protection D1 R1 (Optional) R2 39R Auxilliary winding VDD DRAIN C2 C1 - Bulk capacitor 22nF OSC 13V + VIPerXX0 COMPSOURCE ) s ( t c u Electrical Over Stress Ruggedness d o The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or lightning. r Following the Layout Considerations is sufficient to prevent catastrophic dP amages most of the time. However in some cases, the voltage surges coupled through the tra nsformer auxiliary winding can e exceed the VDD pin absolute maximum rating voltage value. Suche tevents may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the V bulk capacitor. l DD o The simple RC filter shown in (see Figure 25) page 17 can be implemented to improve the application s immunity to such surges. b O - ) s ( t c u d o r P e t e l o s b O 18/24

VIPer100/SP - VIPer100A/ASP Figure 26. Recommended Layout T1 D1 To secondary D2 C7 filtering and load R1 VDD DRAIN C1 - From input OSC 13V + C5 diodes bridge COMP SOURCE U1 VIPerXX0 R2 C6 C2 C3 ISO1 C4 ) s FC00500 ( t c u d o r P Layout Considerations e t Some simple rules insure a correct running of switching power supeplies. They may be classified into two categories: ol s - Minimizing power loops: The switched power current mbust be carefully analysed and the corresponding paths must be as small an inner loop area as possibleO. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, - especially on secondary side. ) s - Using different tracks for low level an(d power signals: Interference due to mixing of signal and power t may result in instabilities and/or anocmalous behaviour of the device in case of violent power surge (Input u overvoltages, output short circuits...). d In case of VIPer, these ruleos apply as shown on (see Figure 26). r P (cid:129) Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized. e (cid:129) C6 must be as close as possible to T1. t e (cid:129) Signal clomponents C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power o sourcse of the device. b O 19/24

VIPer100/SP - VIPer100A/ASP Pentawatt HV Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. Max. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.11 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 ) s H2 10.40 (0.409 t c H3 10.05 10.40 0.396 0.409 u L 15.60 17.30 6.14 d 0.681 o L1 14.60 15.22 0.575 r 0.599 P L2 21.20 21.85 0.835 0.860 e L3 22.20 22.82 0e.8t74 0.898 l L5 2.60 3 o 0.102 0.118 s L6 15.10 15.80 b 0.594 0.622 O L7 6 6.60 0.236 0.260 - M 2.50 3.10 0.098 0.122 ) s M1 4.50 ( 5.60 0.177 0.220 t c R 0.50 0.02 u V4 d 90° o Diam 3.65r 3.85 0.144 0.152 P e t e l o s b O P023H3 20/24

VIPer100/SP - VIPer100A/ASP Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. Max. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.110 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 ) s H2 10.40 (0.409 t c H3 10.05 10.40 0.396 0.409 u L 16.42 17.42 0.646 d 0.686 o L1 14.60 15.22 0.575 r 0.599 P L3 20.52 21.52 0.808 0.847 e L5 2.60 3.00 0e.1t02 0.118 l L6 15.10 15.80 o 0.594 0.622 s L7 6.00 6.60 b 0.236 0.260 O M 2.50 3.10 0.098 0.122 - M1 5.00 5.70 0.197 0.224 ) s R 0.50( 0.02 0.020 t c V4 90° 90° u d Diam 3.65 3.85 0.144 0.154 o r P e t e l L o L1 s E b O M1 M A R D C leadsResin between L6 L7 V4 G2 G1 H1 H3 H2 F L3 L5 DIA 21/24

VIPer100/SP - VIPer100A/ASP Figure 27. Pentawatt HV Tube Shipment ( no suffix ) Base Q.ty 50 Bulk Q.ty 1000 Tube length ( ± 0.5 ) 532 A 18 B 33.1 C ( ± 0.1) 1 All dimensions are in mm. ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 22/24

VIPer100/SP - VIPer100A/ASP Table 13. Revision history Date Revision Changes 02-May-2005 1 Initial release. 08-JUn-2005 2 Update without PowerSO-10TM ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 23/24

VIPer100/SP - VIPer100A/ASP ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences t of use of such ineformation nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implicatioln or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject o to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not s authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. b O The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 24/24