USBLC6-4SC6Y Automotive very low capacitance ESD protection Datasheet  production data Features ■ 4 data-line protection ■ Protects V BUS ■ Very low capacitance: 3 pF SOT23-6L ■ Very low leakage current: 10 nA USBLC6-4SC6Y(JEDEC MO178AB) ■ SOT23-6L package ■ RoHS compliant ■ AEC Q101 qualified Figure 1. Functional diagram Benefits ■ Very low capacitance between lines to GND for I/O1 11 6 I/O4 optimized data integrity and speed ■ Low PCB space consumption, 9 mm² maximum foot print GND 2 5 VBUS ■ Enhanced ESD protection: ISO10605 up to 25kV guaranteed at device level I/O2 3 4 I/O3 ■ ESD protection of V BUS ■ High reliability offered by monolithic integration ■ Fast response time Applications ■ Consistent D+ / D- signal balance: – Very low capacitance matching tolerance ■ USB 2.0 ports up to 480 Mb/s (high speed) I/O to GND = 0.015 pF ■ Compatible with USB 1.1 low and full speed – Compliant with USB 2.0 requirements ■ High-speed data lines in smart junction boxes Complies with the following standards ■ Ethernet port: 10/100 Mb/s ■ ISO10605, C = 150 pF, R = 330  ■ Video line protection – 25 kV (air discharge) Description – 15 kV (contact discharge) ■ ISO10605, C = 330 pF, R = 330  The USBLC6-4SC6Y is a monolithic device – 15 kV (air discharge) dedicated to ESD protection of high speed – 15 kV (contact discharge) interfaces, such as USB 2.0, Ethernet links and video lines. ■ ISO 7637-3 – Pulse 3a: Vs = -150 V Its very low line capacitance secures a high level – Pulse 3b: Vs = +100 V of signal integrity without compromising in protecting sensitive chips against the most TM: Transil is a trademark of STMicroelectronics stringent characterized ESD strikes. September 2012 Doc ID 023199 Rev 2 1/10 This is information on a product in full production. www.st.com 10

Characteristics USBLC6-4SC6Y 1 Characteristics T able 1. Absolute maximum ratings (t = 25 °C) - Generic parameters amb Symbol Parameter Value Unit ISO10605 (C = 330 pF, R = 330 ): air discharge 15 contact discharge 15 V Peak pulse voltage kV PP ISO10605 (C = 150 pF, R = 330 : air discharge 25 contact discharge 15 T Storage temperature range -55 to +150 °C stg T Operating junction temperature range -40 to +150 °C j T Lead solder temperature (10 seconds duration) 260 °C L Note: 1 For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) I I F Symbol Parameter VBR = Breakdown voltage VF I = Leakage current @V VRM = Stand-off voltage RM VCLVBR VRM V RM IRM I = Peak pulse current I PP R C = Line capacitance line Slope:1/R d I PP 2/10 Doc ID 023199 Rev 2

USBLC6-4SC6Y Characteristics Table 2. E lectrical characteristics (T = 25 °C) amb Value Symbol Parameter Test Conditions Unit Min. Typ. Max. I Leakage current V = 5.25 V 10 150 nA RM RM Breakdown voltage between V and V BUS I = 1 mA 6 V BR GND R V Forward voltage I = 10 mA 0.86 V F F I = 1 A, 8/20 µs PP 12 V Any I/O pin to GND V Clamping voltage CL I = 5 A, 8/20 µs PP 17 V Any I/O pin to GND C Capacitance between I/O and GND V = 1.65 V 3 4 i/o-GND R pF C 0.015 i/o-GND C Capacitance between I/O V = 1.65 V 1.85 2.7 i/o-i/o R pF C 0.04 i/o-i/o Figure 3. Capacitance versus voltage Figure 4. Line capacitance versus frequency (typical values) (typical values) C(pF) C(pF) 5.0 5.0 VOSC=30mVRMS 4.5 F=1MHz 4.5 Tj=25°C 4.0 VOSCT=j=3205m°CVRMS 4.0 VCC=0V 3.5 3.5 CO=I/O-GND VCC=1.65V 3.0 3.0 2.5 2.5 Cj=I/O-I/O 2.0 2.0 1.5 1.5 1.0 1.0 0.5 Data line voltage (V) 0.5 F(MHz) 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 1000 Figure 5. Relative variation of leakage Figure 6. Frequency response current versus junction temperature (typical values) IRM[Tj] /IRM[Tj=25°C] S21(dB) 100 0.00 VBUS=5V -5.00 10 -10.00 -15.00 F(Hz) Tj(°C) 1 -20.00 25 50 75 100 125 100.0k 1.0M 10.0M 100.0M 1.0G Doc ID 023199 Rev 2 3/10

Application and design guidelines USBLC6-4SC6Y Figure 7. E SD response to ISO10605, Figure 8. ESD response to ISO10605, C=150pF, R = 330 (+15 kV air C=150pF, R=330(-15 kV air discharge) discharge) Figure 9. Analog crosstalk results 00..0000 ddBB --3300..0000 --6600..0000 --9900..0000 F (Hz) --112200..0000 110000..00kk 11..00MM 1100..00MM 110000..00MM 11..00GG f/Hz 2 Application and design guidelines More information is available in the STMicroelectronics Application note AN2689, “Protection of automotive electronics from electrical hazards, guidelines for design and component selection”. 4/10 Doc ID 023199 Rev 2

USBLC6-4SC6Y Ordering information scheme 3 Ordering information scheme Figure 10. Ordering information scheme USB LC 6 - 4 SC6 Y Product designation Low capacitance Breakdown voltage 6 = 6.1V Number of lines protected 4 = 4 lines Package SC6 = SOT23-6L Automotive grade Doc ID 023199 Rev 2 5/10

Package information USBLC6-4SC6Y 4 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at:www.st.com. ECOPACK® is an ST trademark. T able 3. SOT23-6L dimensions Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.90 1.45 0.035 0.057 c A1 θ L A1 0 0.15 0 0.006 A H E A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.02 C 0.09 0.20 0.004 0.008 e D 2.80 3.05 0.110 0.120 D b e E 1.50 1.75 0.059 0.069 e 0.95 0.037 A2 H 2.60 3.00 0.102 0.118 L 0.30 0.60 0.012 0.024  0° 10° 0° 10° F igure 11. SOT23-6L footprint (mm) 0.60 1.20 3.50 2.30 0.95 1.10 6/10 Doc ID 023199 Rev 2

USBLC6-4SC6Y Recommendation on PCB assembly 5 Recommendation on PCB assembly 5.1 Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. 5.2 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of  0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 5.3 PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Doc ID 023199 Rev 2 7/10

Recommendation on PCB assembly USBLC6-4SC6Y 5.4 Reflow profile Figure 12. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) -2°C/s 250 2 - 3 °C/s 200 60sec (90max) -3°C/s 150 -6°C/s 100 0.9 °C/s 50 Time (s) 0 30 60 90 120 150 180 210 240 270 300 Note: Minimize air convection currents in the reflow oven to avoid component movement. 8/10 Doc ID 023199 Rev 2

USBLC6-4SC6Y Ordering information 6 Ordering information T able 4. Ordering information Order code Marking Package Weight Base qty Delivery mode USBLC6-4SC6Y UL4Y SOT23-6L 16.7 mg 3000 Tape and reel 7 Revision history T able 5. Document revision history Date Revision Changes 14-May-2012 1 First issue. 06-Sep-2012 2 Updated dimensions A1 max, b min., and L min. in Table3. Doc ID 023199 Rev 2 9/10

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