USBLC6-2SC6Y Automotive very low capacitance ESD protection Datasheet  production data Features ■ 2 data lines protected ■ Protects V BUS ■ Very low capacitance: 2.5 pF ■ Very low leakage current: 10 nA SOT23-6L USBLC6-2SC6Y(JEDEC MO178AB) ■ SOT23-6L package ■ RoHS compliant Figure 1. Functional diagram ■ AEC-Q101 qualified Benefits I/O1 11 6 I/O1 ■ Very low capacitance between lines to GND for optimized data integrity and speed GND 2 5 VBUS ■ Low PCB space consumption I/O2 3 4 I/O2 ■ Enhanced ESD protection. ISO10605 up to 25kV guaranteed at device level ■ ESD protection of V Applications BUS ■ High reliability offered by monolithic integration ■ USB 2.0 ports up to 480 Mb/s (high speed) ■ Fast response time ■ Compatible with USB 1.1 low and full speed ■ Consistent D+ / D- signal balance: ■ High-speed datalines in smart junction boxes – Very low capacitance matching tolerance ■ Ethernet port: 10/100 Mb/s I/O to GND = 0.015 pF ■ Video line protection – Compliant with USB 2.0 requirements Complies with the following standards Description ■ ISO10605: C = 150 pF, R = 330  The USBLC6-2SC6Y is a monolithic device – 25 kV (air discharge) dedicated to ESD protection of high speed – 15 kV (contact discharge) interfaces, such as USB 2.0, Ethernet links and video lines. ■ ISO10605: C = 330 pF, R = 330  – 15 kV (air discharge) The very low line capacitance secures a high level – 15 kV (contact discharge) of signal integrity without compromising in protecting sensitive chips against the most ■ ISO7637-3 stringent characterized ESD strikes. – Pulse 3a: Vs = -150 V – Pulse 3b: Vs = +100 V TM: Transil is a trademark of STMicroelectronics September 2012 Doc ID 023201 Rev 2 1/9 This is information on a product in full production. www.st.com 9

Characteristics USBLC6-2SC6Y 1 Characteristics T able 1. Absolute ratings Symbol Parameter Value Unit ISO 10605 (C = 150 pF, R = 330 ): Air discharge 25 Contact discharge 15 V (1) Peak pulse voltage kV PP ISO 10605 (C = 300 pF, R = 330 ): Air discharge 15 Contact discharge 15 T Storage temperature range -55 to +150 °C stg T Operating junction temperature range -40 to +150 °C j T Lead solder temperature (10 seconds duration) 260 °C L 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) I IF Symbol Parameter V = Breakdown voltage BR IRM = Leakage current @VRM VF VIPRPM == SPetaankd p-ouflfs veo cltuargreent VCLVBR VRM IRM V CLINE= Line capacitance Slope:1/Rd IPP T able 2. Electrical characteristics (T = 25 °C) amb Symbol Parameter Test conditions Min. Typ. Max. Unit I Leakage current V = 5.25 V 10 150 nA RM RM Breakdown voltage between V V BUS I = 1 mA 6 V BR and GND R V Forward voltage I = 10 mA 1.1 V F F I = 1 A, 8/20 µs PP 12 V Any I/O pin to GND V Clamping voltage CL I = 5 A, 8/20 µs PP 17 V Any I/O pin to GND C Capacitance between I/O and GND 2.5 3.5 i/o-GND Interline capacitance matching VR = 1.65 V pF C 0.015 i/o-GND between I/O and GND C Capacitance between I/O 1.2 1.7 i/o-i/o Interline capacitance matching VR = 1.65 V pF C 0.04 i/o-i/o between I/O 2/9 Doc ID 023201 Rev 2

USBLC6-2SC6Y Characteristics F igure 3. Capacitance versus voltage Figure 4. Line capacitance versus frequency (typical values) (typical values) C(pF) C(pF) 3.0 2.8 2.6 CO= I/O - GND 2.4 2.5 2.2 VOSC= 30mVRMS F = 1MHz 2.0 Tj= 25°C 2.0 VOSC= 30mVRMS 1.8 VLINE= 0V to 3.3V Tj= 25°C 1.6 1.5 1.4 Cj= I/O - I/O 1.2 1.0 1.0 0.8 0.6 0.5 0.4 Data line voltage (V) 0.2 F(MHz) 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 1000 Figure 5. Relative variation of leakage Figure 6. Frequency response current versus junction temperature (typical values) IRM[Tj] /IRM[Tj=25°C] 0.00 100 S21(dB) VBUS=5V -5.00 -10.00 10 -15.00 Tj(°C) F(Hz) 1 -20.00 25 50 75 100 125 100.0k 1.0M 10.0M 100.0M 1.0G Figure 7. ESD response to ISO10605, Figure 8. ESD response to ISO10605, C=150pF, R = 330 (+15 kV air C=150pF, R=330(-15 kV air discharge) discharge) Vin Vin Vout Vout ESDSURGE ESDSURGE INTEST BOAORUDT INTEST BOAORUDT USBLC6-2SC6 +5V USBLC6-2SC6 +5V Doc ID 023201 Rev 2 3/9

Application and design guidelines USBLC6-2SC6Y Figure 9. Analog crosstalk results dB 0.00 -30.00 -60.00 -90.00 F (Hz) -120.00 100.0k 1.0M 10.0M 100.0M 1.0G 2 Application and design guidelines More information is available in the STMicroelectronics Application note AN2689, “Protection of automotive electronics from electrical hazards, guidelines for design and component selection”. 3 Ordering information scheme Figure 10. Ordering information scheme USB LC 6 - 2 SC6 Y Product designation Low capacitance Breakdown voltage 6 = 6.1V Number of lines protected 2 = 2 lines Package SC6 = SOT23-6L Automotive grade 4/9 Doc ID 023201 Rev 2

USBLC6-2SC6Y Package information 4 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. T able 3. SOT23-6L dimensions Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.90 1.45 0.035 0.057 c A1 θ L A1 0 0.15 0 0.006 A H E A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.012 0.020 c 0.09 0.20 0.004 0.008 e D 2.80 3.05 0.11 0.118 D b e E 1.50 1.75 0.059 0.069 e 0.95 0.037 A2 H 2.60 3.00 0.102 0.118 L 0.30 0.60 0.012 0.024  0° 10° 0° 10° F igure 11. SOT23-6L footprint 0.60 1.20 3.50 2.30 0.95 1.10 Doc ID 023201 Rev 2 5/9

Recommendation on PCB assembly USBLC6-2SC6Y 5 Recommendation on PCB assembly 5.1 Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. 5.2 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of  0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 5.3 PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 6/9 Doc ID 023201 Rev 2

USBLC6-2SC6Y Recommendation on PCB assembly 5.4 Reflow profile Figure 12. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) -2°C/s 250 2 - 3 °C/s 200 60sec (90max) -3°C/s 150 -6°C/s 100 0.9 °C/s 50 Time (s) 0 30 60 90 120 150 180 210 240 270 300 Note: Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 023201 Rev 2 7/9

Ordering information USBLC6-2SC6Y 6 Ordering information T able 4. Ordering information Order code Marking Package Weight Base qty Delivery mode USBLC6-2SC6Y UL2Y SOT23-6L 16.7 mg 3000 Tape and reel 7 Revision history T able 5. Document revision history Date Revision Changes 16-May-2012 1 First issue. 06-Sep-2012 2 Updated dimensions A max., b min. and L min. in Table3. 8/9 Doc ID 023201 Rev 2

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