USBDFxxW5 EMI filter and line termination for USB downstream ports Applications EMI Filter and line termination for USB downstream ports on: ■ Desktop computer SOT323-5L ■ Notebooks ■ Workstations Functional diagram ■ USB Hubs Features Rt D+ In D+ Out ■ Monolithic device with recommended line termination for USB downstream ports Ct Rd ■ Integrated Rt series termination and Ct Gnd bypassing capacitors. ■ Integrated ESD protection Ct Rd ■ Small package size D- In D- Out Rt Description R R C t d t The USB specification requires USB downstream USBDF01W5 33 Ω 15 kΩ 47 pF ports to be terminated with pull-down resistors from the D+ and D- lines to ground. On the USBDF02W5 15 Ω 15 kΩ 47 pF implementation of USB systems, the radiated and Tolerance ±10% ±10% ±20% conducted EMI should be kept within the required levels as stated by the FCC regulations. In Order codes addition to the requirements of termination and EMC compatibility, the computing devices are required to be tested for ESD susceptibility. Part number Marking The USBDFxxW5 provides the recommended line USBDF01W5 UD1 termination while implementing a low pass filter to USBDF02W5 UD2 limit EMI levels and providing ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device is packaged in a SOT323-5L, which is Benefits a very small (50% smaller than the standard ■ EMI / RFI noise suppression SOT23). ■ Required line termination for USB downstream Complies with the following standards ports ■ ESD protection exceeding IEC 61000-4-2, level 4±15 kV (air discharge) IEC61000-4-2 level 4 ±8 kV (contact discharge) ■ IPAD™ technology provides high flexibility in the design of high density boards MIL STD 883C, Method 3015-6 ■ Tailored to meet USB 1.1 standard Class 3 C = 100 pF R = 1500 W 3 positive strikes and 3 negative strikes (F = 1 Hz) TM: IPAD is a trademark of STMicroelectronics September 2006 Rev 3 1/11 www.st.com 11

Characteristics USBDFxxW5 1 Characteristics T able 1. Absolute maximum ratings (T = 25° C) amb Symbol Parameter Value Unit ESD discharge IEC 61000-4-2, contact discharge ±15 V kV PP ESD discharge - MIL STD 883 - Method 3015-6 ±25 T Operating junction temperature range -40 to 150 °C j T Storage temperature range - 55 to +150 °C stg T Lead solder temperature (10 second duration) 260 °C L P Power rating per resistor 100 mW r T able 2. Electrical characteristics (T = 25° C) amb Symbol Parameters Test conditions Min Typ Max Unit V Diode breakdown voltage I = 1 mA 6 V BR R V Diode forward voltage drop I = 50 mA 0.9 V F F 2 Application information Figure 1. USB Standard requirements +Vbus 1.5k Rt D+ D+ Rt Full-speed or Low-speed USB Ct Twisted pair shielded Ct Full-speed USB Transceiver Rt Rt Transceiver D- Zo = 90ohms D- Host or Ct 15k 15k 5m max Ct Hub 0 or Hub port Full-speed function FULL SPEED CONNECTION +Vbus 1.5k Rt D+ D+ Rt Full-speed or LTroawn-sscpeeiveedr USB Ct Rt Untwisted unshielded Rt Ct LTroawn-sscpeeiveedr USB D- 3m max D- Host or Ct 15k 15k Ct Hub 0 or Hub port Low-speed function LOW SPEED CONNECTION 2/11

USBDFxxW5 Application information Figure 2. Application example Downstream port Upstream port D+ (1) D+ CABLE D- (2) +Vbus USBDF USBUF xxW5 xxW6 D- D- (1) D+ (2) Host/Hub USB Peripheral port transceiver transceiver (1) for a low-speed port (2) for a full-speed port 2.1 EMI filtering Current FCC regulations requires that class B computing devices meet specified maximum levels for both radiated and conducted EMI. ● Radiated EMI covers the frequency range from 30 MHz to 1 GHz. ● Conducted EMI covers the 450 kHz to 30 MHz range. For the types of devices utilizing the USB the most difficult test to pass is usually the radiated EMI test. For this reason the USBDF device aims to minimize radiated EMI. The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted EMI because the magnetic field of the two conductors exactly cancels each other. The inside of the PC environment is very noisy and designers must minimise noise coupling from the different sources. D+ and D- must not be routed near high speed lines (clocks...). Induced common mode noise can be minimised by running pairs of USB signals parallel to each other and running grounded guard trace on each side of the signal pair from the USB controller to the USBDF device. If possible, locate the USBDF device physically near the USB connectors. Distance between the USB controller and the USB connector must be minimized. The 47 pF (C) capacitors are used to divert high frequency energy to ground and for edge t control, and must be placed between the USB Controller and the series termination resistors (R). Both C and R should be placed as close to the mSB Controller as t t t practicable. The USBDFxxW5 ensure a filtering protection against electroMagnetic and radio-frequency Interference thanks to its low-pass filter structure. This filter is characterized by the following parameters : ● cut-off frequency ● Insertion loss ● high frequency rejection Figure 4. shows the attenuation curve for frequencies up to 3 GHz. 3/11

Application information USBDFxxW5 F igure 3. Measurement configuration Figure 4. USBDFxxW5 attenuation curve Insertion loss (dB) 0 50Ω TG OUT TEST BOARD RF IN UD1 -10 Vg 50Ω -20 -30 1 10 100 1000 3000 F (MHz) 2.2 ESD protection In addition to the requirements of termination and EMC compatibility, computing devices are required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe. This test requires that a device tolerates ESD events and remain operational without user intervention. The USBDFxxW5 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at : VINPUT=VBR+ Rd.Ipp This protection function is split in 2 stages. As shown in Figure 5., the ESD strikes are clamped by the first stage S1 and then the remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the V level. out Figure 5. USBDFxxW5 ESD clamping behavior Rg S1 R S2 Rd Rd Vinput Rload V PP V Voutput V BR BR Device to be ESD Surge USBDFxxW5 protected 4/11

USBDFxxW5 Application information To have a good approximation of the remaining voltages at both V and V stages, we give in out the typical dynamical resistance value R . Taking into account the following hypothesis: d R > R , R > R and R > R , gives these formulas:: t d g load d Rg.VBR+ Rd.Vg Vinput= Rg Rt.VBR+ Rd.Vinput Voutput= Rt The results of the calculation done for V = 8 kV, R = 330 W (IEC61000-4-2 standard), PP g V = 7 V (typ.) and R = 1 Ω (typ.) give: BR d V = 31.2 V input V = 7.95 V output This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the V side. This parasitic effect in is not present at the V side due the low current involved after the resistance R. out The measurements results shown below show very clearly (Figure 7.) the high efficiency of the ESD protection : ● no influence of the parasitic inductances on Vout stage ● output clamping voltage very close to V (positive strike) and -V (negative strike) BR F Figure 6. Measurement board ESD TEST BOARD SURGE 15 kV Air U Vin D Vout Discharge 1 5/11

Application information USBDFxxW5 Figure 7. Remaining voltage at both stages S1 (V ) and S2 (V ) during ESD input output surge A.Positive surge B.Negative surge Note that the USBDFxxW5 is not only acting for positive ESD surges but also for negative ones. Negative disturbances are clamped close to ground voltage as shown in Figure 7.b. 2.3 Latch-up phenomena The early ageing and destruction of IC’s is often due to latch-up phenomena which is mainly induced by dV/dt. Thanks to its structure, the USBDFxxW5 provides a high immunity to latch-up phenomena by smoothing very fast edges. 2.4 Crosstalk behaviour Figure 8. Crosstalk phenomena R G1 Line 1 VG1 RL1 α1VG1+β1 2VG2 R G2 Line 2 VG2 RL2 α2VG2+β2 1VG1 DRIVERS RECEIVERS The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor ( β12 or β21 ) increases when the gap across lines decreases, this is the reason why we provide crosstalk measurements for a monolithic device to guarantee negligeable crosstalk between the lines. In the example above, the expected signal on load R is α V , in fact the real L2 2 G2 voltage at this point has got an extra value β21V . This part of the V signal represents G1 G1 the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). 6/11

USBDFxxW5 Application information Figure 9. A nalog crosstalk measurements Figure 10. Typical analog crosstalk results Analog crosstalk (dB) 0 -20 TEST BOARD 50Ω TG OUT RF IN UD1 -40 Vg 50Ω -60 -80 -100 1 10 100 1,000 frequency (MHz) Figure 8. gives the measurement circuit for the analog crosstalk application. In Figure 10., the curve shows the effect of the D+ cell on the D- cell. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -46 dB. Figure 11. D igital crosstalk measurements Figure 12. Digital crosstalk results configuration +5V +5V 74HC04 74HC04 Line 1 Square +5V VG1 UxSxBWD5F Pulse Generator Line 2 5KHz b21VG1 Figure 11. shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure 12. shows that in such a condition signal, from 0 to 5 V and rise time of few ns, the impact on the other line is less than 100 mV peak to peak (below the logic high voltage threshold). The measurements performed with falling edges give the same results. 7/11

Application information USBDFxxW5 2.5 Transition times This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the signal edges are maintained within the 4 ns-20 ns stipulated USB specification limits. Figure 13. Typical rise and fall times: measurements configuration +5V +5V 74HC04 74HC04 D+ USBDF +5V xxW5 Square Pulse D- Generator Figure 14. Typical rise and fall times A.Rise time B.Fall time 8/11

USBDFxxW5 Package information 3 Package information T able 3. SOT323-5L dimensions Dimensions A Ref. Millimeters Inches E Min. Max. Min. Max. A 0.8 1.1 0.031 0.043 e A1 0 0.1 0 0.004 b D A2 0.8 1 0.031 0.039 e b 0.15 0.3 0.006 0.012 A1 c 0.1 0.18 0.004 0.007 A2 D 1.8 2.2 0.071 0.086 Q1 E 1.15 1.35 0.045 0.053 e 0.65 Typ. 0.025 Typ. c L H 1.8 2.4 0.071 0.094 HE Q1 0.1 0.4 0.004 0.016 Figure 15. Recommended footprint (dimensions in mm) 0.3 1.0 2.9 1.0 0.35 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 9/11

Ordering information USBDFxxW5 4 Ordering information Type Order Code Weight Marking Package Base Qty USBDF01W5 USBDF01W5 UD1 5.4 mg SOT323-5L 3000 USBDF02W5 USBDF02W5 UD2 5 Revision history Date Revision Changes May-2000 1C Initial release. Reformatted to current standard. Modified Operating junction 7-Sep-2006 2 temperature range in Table 1. 15-Sep-2006 3 Corrected units of R to kΩ instead of Ω. on page 1 d 10/11

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