USB334x Enhanced Single Supply Hi-Speed USB ULPI Transceiver PRODUCT FEATURES Datasheet  USB-IF Battery Charging 1.2 Specification Compliant  External Reference Clock operation available  Link Power Management (LPM) Specification — ULPI Clock Input Mode (60MHz sourced by Link) Compliant — 0 to 3.6V input drive tolerant  Integrated ESD protection circuits — Able to accept “noisy” clock sources as reference to internal, low-jitter PLL — Up to ±25kV IEC Air Discharge without external — Crystal support available (USB3343) devices  Over-Voltage Protection circuit (OVP) protects the  Smart detection circuits allow identification of USB charger, headset, or data cable insertion VBUS pin from continuous DC voltages up to 30V  Integrated USB Switch (USB3341, USB3346, and  Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go USB3347) Supplement Revision 2.0 specification — Allows single USB port of connection by providing switching function for:  Supports the OTG Host Negotiation Protocol (HNP) – Battery charging and Session Request Protocol (SRP) – Stereo and mono/mic audio  UART mode for non-USB serial data transfers – USB Full-Speed/Low-Speed data  Internal 5V cable short-circuit protection of ID, DP  SMSC RapidCharge Anywhere™ Provides: and DM lines to VBUS or ground — 3-times the charging current through a USB port  Industrial Operating Temperature -40°C to +85°C over traditional solutions  24 pin, QFN lead-free RoHS Compliant package — USB-IF Battery Charging 1.2 compliance to any (4 x 4 x 0.90 mm height) portable device — Charging current up to 1.5Amps via compatible Applications USB host or dedicated charger — Dedicated Charging Port (DCP), Charging (CDP) The USB334x is the solution of choice for any & Standard (SDP) Downstream Port support application where a Hi-Speed USB connection is desired  flexPWR® Technology and when board space, power, and interface pins must — Extremely low current design ideal for battery be minimized. powered applications  Cell Phones — “Sleep” mode tri-states all ULPI pins and places  PDAs the part in a low current state — 1.8V to 3.3V IO Voltage (USB3343)  MP3 Players  Single Power Supply Operation  GPS Personal Navigation — Integrated 1.8V regulator  Scanners — Integrated 3.3V regulator  External Hard Drives – 100mV dropout voltage  Digital Still and Video Cameras  PHYBoost  Portable Media Players — Programmable USB transceiver drive strength for  Entertainment Devices recovering signal integrity  Printers  VariSenseTM  Set Top Boxes — Programmable USB receiver sensitivity  Video Record/Playback Systems  “Wrapper-less” design for optimal timing performance and design ease  IP and Video Phones — Low Latency Hi-Speed Receiver (43 Hi-Speed  Gaming Consoles clocks Max) allows use of legacy UTMI Links with a ULPI bridge SMSC USB334x Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Order Number(s): REFCLK FREQUENCY ORDER NUMBER (Note0.1) PACKAGE TYPE REEL SIZE USB3341-CP-TR 26MHz (oscillator only) USB3343-CP-TR 26MHz (oscillator or crystal) 24 Pin, QFN Lead-Free RoHS 4,000 pieces Compliant Package (tape and reel) USB3346-CP-TR 19.2MHz (oscillator only) USB3347-CP-TR 27MHz (oscillator only) Note0.1 All versions support ULPI Clock In Mode (60MHz input at REFCLK) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs Please contact your SMSC sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. Copyright © 2013 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.2 (02-08-13) 2 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 0.1 Reference Documents UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 Universal Serial Bus Specification, Revision 2.0 On-The-Go Supplement to the USB2.0 Specification, Revision 1.3 On-The-Go Supplement to the USB2.0 Specification, Revision 2.0 USB Battery Charging Specification, Revision 1.2 SMSC USB334x 3 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table of Contents 0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter2 USB334x Pin Locations and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 USB334x Pin Locations and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 USB3341, USB3346, and USB3347 Pin Diagram and Pin Definitions . . . . . . . . . . . . . . 11 2.1.2 USB3343 Diagram and Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter3 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Operating Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 ULPI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 Digital IO Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 DC Characteristics: Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 Dynamic Characteristics: Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 VBUS Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 ID Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.9 USB Audio Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.10 USB Charger Detection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11 Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.12 Piezoelectric Resonator for Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.13 ESD and Latch-Up Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter5 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 ULPI Digital Operation and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 USB 2.0 Hi-Speed Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.1 USB Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 Crystal Reference Support (USB3343 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5 Integrated Low Jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.1 REFCLK Frequency Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.2 REFCLK Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5.3 REFCLK Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5.4 REFCLK Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.1 Integrated Low Dropout Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.2 Power On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.3 Recommended Power Supply Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6.4 Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7 USB On-The-Go (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.7.1 ID Resistor Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.7.2 VBUS Monitoring and VBUS Pulsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.7.3 Driving External VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.8 USB UART Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.9 USB Charger Detection Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.9.1 Active Analog Charger Detection (USB-IF Battery Charging 1.2). . . . . . . . . . . . . . . . . . 45 Revision 1.2 (02-08-13) 4 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 5.9.2 Resistive Charger Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.10 USB Audio Support (USB3341 and USB3346) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter6 ULPI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1 ULPI Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.1 ULPI Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.2 ULPI Interface Timing in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 ULPI Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2.1 Transmit Command Byte (TX CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.2 ULPI Register Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.3 ULPI Register Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3 USB334x Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.1 ULPI Receive Command (RX CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.2 USB Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4 USB334x Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.4.1 USB334x Host Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.4.2 Typical USB Transmit with ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.5 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.5.1 Entering Low Power/Suspend Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.5.2 Exiting Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5.3 Link Power Management (LPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5.4 Interface Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.5.5 Minimizing Current in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.6 Full Speed/Low Speed Serial Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.7 Carkit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.7.1 Entering USB UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.7.2 USB Audio Mode (USB3341 and USB3346). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.8 RID Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.8.1 Headset Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Chapter7 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.1 ULPI Register Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.1.1 ULPI Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.1.2 Carkit Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.1.3 Vendor Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Chapter8 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2 USB Charger Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.3 Reference Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.4 ESD Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.4.1 Human Body Model (HBM) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4.2 EN/IEC 61000-4-2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Chapter9 Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Chapter10 Datasheet Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SMSC USB334x 5 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet List of Figures Figure1.1 Block Diagram (USB3341, USB3346, and USB3347). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure1.2 Block Diagram (USB3343). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure2.1 USB3341, USB3346, and USB3347 Pin Locations - Top View. . . . . . . . . . . . . . . . . . . . . . . 11 Figure2.2 USB3343 Pin Locations - Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure5.1 USB334x System Diagram (USB3341, USB3346, and USB3347) . . . . . . . . . . . . . . . . . . . . 29 Figure5.2 USB334x System Diagram (USB3343) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure5.1 Configuring the USB334x for ULPI Clock Input Mode (60 MHz) . . . . . . . . . . . . . . . . . . . . . . 34 Figure5.2 Configuring the USB334x for ULPI Clock Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure5.3 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level. . . . . . . 35 Figure5.4 ULPI Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure5.5 USB334x ID Resistor Detection Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure5.6 USB334x OTG VBUS Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure5.7 USB Charger Detection Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure6.1 ULPI Digital Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure6.2 ULPI Single Data Rate Timing Diagram in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . 50 Figure6.3 ULPI Register Write in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure6.4 ULPI Extended Register Write in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure6.5 ULPI Register Read in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure6.6 ULPI Extended Register Read in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure6.7 ULPI RXCMD Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure6.8 ULPI Receive in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure6.9 ULPI Transmit in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure6.10 LPM Token Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure6.11 Entering Low Power Mode from Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure6.12 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure8.1 USB3341, USB3346, and USB3347 Application Diagram (Device configured for ULPI Clock Output Mode) 84 Figure8.2 USB3343 Application Diagram (Device configured for ULPI Clock Output Mode) . . . . . . . . 85 Figure8.3 USB3341, USB3346, and USB3347 Application Diagram (Host or OTG configured for ULPI Clock Input mode) 86 Figure9.1 24-pin QFN, 4x4mm Body, 0.5mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure9.2 24QFN, 4x4 Tape and Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure9.3 24QFN, 4x4 Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure9.4 24QFN, 4x4 Package Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Revision 1.2 (02-08-13) 6 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet List of Tables Table2.1 USB3341, USB3346, and USB3347 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table2.2 USB3343 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table3.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table4.1 Operating Current (USB3341, USB3346, and USB3347) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table4.2 Operating Current (USB3343) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table4.3 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table4.4 ULPI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table4.5 Digital IO Characteristics: RESETB, STP, DIR, NXT, DATA[7:0], and REFCLK Pins . . . . . . . . . . . . . . . 21 Table4.6 DC Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table4.7 Dynamic Characteristics: Analog I/O Pins (DP/DM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table4.8 VBUS Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table4.9 ID Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table4.10 USB Audio Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table4.11 USB Charger Detection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table4.12 Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table4.13 USB334x Quartz Crystal Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table4.14 ESD and Latch-Up Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table5.1 DP/DM Termination vs. Signaling Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table5.2 Operating Mode vs. Power Supply Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table5.3 Valid Values of ID Resistance to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table5.4 IdGnd and IdFloat vs. ID Resistance to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table5.5 External VBUS Indicator Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table5.6 Required RVBUS Resistor Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table5.7 USB Charger Setting vs. Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table5.8 USB Weak Pull-up Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table6.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table6.2 ULPI TX CMD Byte Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table6.3 ULPI RX CMD Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table6.4 USB Linestate Decoding in FS and LS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table6.5 USB Linestate Decoding in HS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table6.6 USB Linestate Decoding in HS Chirp Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table6.7 Interface Signal Mapping During Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table6.8 Pin Definitions in 3 pin Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table6.9 Pin Definitions in 6 pin Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table6.10 Pin Definitions in Carkit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table6.11 ULPI Register Programming Example to Enter UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table6.12 ULPI Register Programming Example to Enter Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table6.13 Pin Definitions in Headset Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table7.1 ULPI Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table8.1 Component Values in Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table8.2 Capacitance Values at VBUS of USB Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table10.1 Customer Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SMSC USB334x 7 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 1 General Description SMSC’s USB334x is a family of Hi-Speed USB 2.0 Transceivers that provide a physical layer (PHY) solution well-suited for portable electronic devices. Both commercial and industrial temperature applications are supported. Each model in the USB334x family may use a 60MHz reference clock or the model-number specific reference clock shown on page 2. Several advanced features make the USB334x the transceiver of choice by reducing both eBOM part count and printed circuit board (PCB) area. Outstanding ESD robustness eliminates the need for external ESD protection devices in typical applications. The internal Over-Voltage Protection circuit (OVP) protects the USB334x from voltages up to 30V on the VBUS pin. By using a reference clock from the Link, the USB334x removes the cost of a dedicated crystal reference from the design. The USB334x includes integrated 3.3V and 1.8V regulators, making it possible to operate the device from a single power supply. The USB334x is optimized for use in portable applications where a low operating current and standby currents are essential. The USB334x operates from a single supply and includes integrated regulators for its supplies. The USB334x also supports the USB Link Power Management protocol (LPM) to further reduce USB operating currents. The USB334x family is enabled with SMSC's RapidCharge AnywhereTM which supports USB-IF Battery Charging 1.2 for any portable device. RapidCharge AnywhereTM provides three times the charging current through a USB port over traditional solutions which translate up to 1.5Amps via compatible USB host or dedicated charger. In addition, this provides a complete USB charging ecosystem between device and host ports such as Dedicated Charging Port (DCP), Charging (CDP) and Standard (SDP) Downstream Ports. Section5.9 describes this is further detail. The USB334x meets all of the electrical requirements for a Hi-Speed USB Host, Device, or an On-the- Go (OTG) transceiver. In addition to the supporting USB signaling, the USB334x also provides USB UART mode and, in versions with the integrated USB switch, USB Audio mode. USB334x uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB transceiver to the Link. ULPI uses a method of in-band signaling and status byte transfers between the Link and PHY to facilitate a USB session with only twelve pins. The USB334x uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapper- less” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused. Versions of the USB334x with the integrated USB switch enable a single USB port of connection. Revision 1.2 (02-08-13) 8 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet REFCLK VBUS OVP Low Jitter BIAS RBIAS n OTG Integrated o ID cti PLL e ot Pr Integrated RESETB D Power VBAT DP S Hi-Speed VDD33 E BC 1.1 Management USB VDD18 DM ULPI Transceiver Registers and State STP Machine ULPI NXT USB Interface DIR DP/DM CLKOUT Switch _L _R DATA[7:0] K K P P S S Figure1.1 Block Diagram (USB3341, USB3346, and USB3347) In USB audio mode, a switch connects the DP pin to the SPK_R pin, and another switch connects he DM pin to the SPK_L pin. These switches are shown in the lower left-hand corner of .The USB334x can be configured to enter USB audio mode as described in Section6.7.2. In addition, these switches are on when the RESETB pin of the USB334x is asserted. The USB audio mode enables audio signaling from a single USB port of connection, and the switches may also be used to connect Full Speed USB from another transceiver to the USB connector. SMSC USB334x 9 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet XI K / L C F E O R X VBUS OVP Low Jitter BIAS RBIAS n OTG Integrated o ID cti PLL e ot Pr Integrated RESETB D Power VBAT DP S Hi-Speed VDD33 E Management USB VDD18 DM ULPI Transceiver Registers VDDIO and State STP Machine ULPI NXT Interface DIR CLKOUT DATA[7:0] Figure1.2 Block Diagram (USB3343) The USB334x includes an integrated 3.3V LDO regulator that is used to generate 3.3V from power applied to the VBAT pin. The voltage on the VBAT pin can range from 3.0 to 5.5V. The regulator dropout voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on VBAT drops to 3.0V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the USB specifications. The VBAT and VDD33 pins should never be connected together. In USB UART mode, the USB334x DP and DM pins are redefined to enable pass-through of asynchronous serial data. The USB334x will enter UART mode when programmed, as described in Section6.7.1. Revision 1.2 (02-08-13) 10 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 2 USB334x Pin Locations and Definitions 2.1 USB334x Pin Locations and Descriptions 2.1.1 USB3341, USB3346, and USB3347 Pin Diagram and Pin Definitions The illustration below is viewed from the top of the package. B K DIR STP VDD18 RESET REFCL RBIAS 4 3 2 1 0 9 2 2 2 2 2 1 CLKOUT 1 18 ID NXT 2 17 VBUS DATA0 3 24Pin QFN 16 VBAT 4x4mm DATA1 4 15 VDD33 DATA2 5 14 DM DATA3 6 13 DP 0 1 2 7 8 9 1 1 1 4 5 6 7 L R A A A A _ _ T T T T K K A A A A P P D D D D S S Figure2.1 USB3341, USB3346, and USB3347 Pin Locations - Top View The following table details the pin definitions for the figure above. Table2.1 USB3341, USB3346, and USB3347 Pin Descriptions DIRECTION/ ACTIVE DESCRIPTION PIN NAME TYPE LEVEL 1 CLKOUT Output, N/A ULPI Clock Output Mode: CMOS 60MHz ULPI Clock Outputput. All ULPI signals are driven synchronous to the rising edge of this clock. ULPI Clock Input Mode: Connect this pin to VDD18 to configure 60MHz ULPI Clock Input mode as described in Section5.5.1. 2 NXT Output, High The PHY asserts NXT to throttle the data. When the CMOS Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. 3 DATA[0] I/O, N/A ULPI bi-directional data bus. DATA[0] is the LSB. CMOS SMSC USB334x 11 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table2.1 USB3341, USB3346, and USB3347 Pin Descriptions (continued) DIRECTION/ ACTIVE DESCRIPTION PIN NAME TYPE LEVEL 4 DATA[1] I/O, N/A ULPI bi-directional data bus. CMOS 5 DATA[2] I/O, N/A ULPI bi-directional data bus. CMOS 6 DATA[3] I/O, N/A ULPI bi-directional data bus. CMOS 7 DATA[4] I/O, N/A ULPI bi-directional data bus. CMOS 8 DATA[5] I/O, N/A ULPI bi-directional data bus. CMOS 9 DATA[6] I/O, N/A ULPI bi-directional data bus. CMOS 10 DATA[7] I/O, N/A ULPI bi-directional data bus. DATA[7] is the MSB. CMOS 11 SPK_L I/O, N/A USB switch in/out for DM signals. Analog 12 SPK_R I/O, N/A USB switch in/out for DP signals. Analog 13 DP I/O, N/A D+ pin of the USB cable. Analog 14 DM I/O, N/A D- pin of the USB cable. Analog 15 VDD33 Power N/A 3.3V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 16 VBAT Power N/A Regulator input. The regulator supply can be from 5.5V to 3.0V. 17 VBUS I/O, N/A This pin is used for the VBUS comparator inputs and Analog for VBUS pulsing during session request protocol. An external resistor, R , is required between this VBUS pin and the USB connector. 18 ID Input, N/A For device applications the ID pin is connected to Analog VDD33. For Host applications ID is grounded. For OTG applications the ID pin is connected to the USB connector. 19 RBIAS Analog, N/A Bias Resistor pin. This pin requires an 8.06kΩ (±1%) CMOS resistor to ground, placed as close as possible to the USB334x. Nominal voltage during ULPI operation is 0.8V. 20 REFCLK Input, N/A ULPI Clock Output Mode: CMOS Model-specific reference clock pin. See on page 2. ULPI Clock Input Mode: 60MHz ULPI Clock Input. Revision 1.2 (02-08-13) 12 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table2.1 USB3341, USB3346, and USB3347 Pin Descriptions (continued) DIRECTION/ ACTIVE DESCRIPTION PIN NAME TYPE LEVEL 21 RESETB Input, Low When low, the part is suspended and the 3.3V and CMOS, 1.8V regulators are disabled. When high, the USB334x will operate as a normal ULPI device, as described in Section5.6.2. The state of this pin may be changed asynchronously to the clock signals. When asserted for a minimum of 1 microsecond and then de-asserted, the ULPI registers are reset to their default state and all internal state machines are reset. 22 VDD18 Power N/A 1.8V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 23 STP Input, High The Link asserts STP for one clock cycle to stop the CMOS data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. 24 DIR Output, N/A Controls the direction of the data bus. When the PHY CMOS has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. FLAG GND Ground N/A Ground. SMSC USB334x 13 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 2.1.2 USB3343 Diagram and Pin Definitions The illustration below is viewed from the top of the package. XI B K / TP DD18 ESET EFCL O BIAS S V R R X R 4 3 2 1 0 9 2 2 2 2 2 1 DIR 1 18 ID CLKOUT 2 17 VBUS NXT 3 24Pin QFN 16 VBAT 4x4mm DATA0 4 15 VDD33 DATA1 5 14 DM DATA2 6 13 DP 0 1 2 7 8 9 1 1 1 3 4 O 5 6 7 TA TA DI TA TA TA A A D A A A D D V D D D Figure2.2 USB3343 Pin Locations - Top View The following table details the pin definitions for the figure above. Table2.2 USB3343 Pin Descriptions DIRECTION/ ACTIVE DESCRIPTION PIN NAME TYPE LEVEL 1 DIR Output, N/A Controls the direction of the data bus. When the PHY CMOS has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. 2 CLKOUT Output, N/A ULPI Clock Out Mode: CMOS 60MHz ULPI clock output. All ULPI signals are driven synchronous to the rising edge of this clock. ULPI Clock In Mode: Connect this pin to VDDIO to configure 60MHz ULPI Clock IN mode as described in Section5.5.1. 3 NXT Output, High The PHY asserts NXT to throttle the data. When the CMOS Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. 4 DATA[0] I/O, N/A ULPI bi-directional data bus. DATA[0] is the LSB. CMOS 5 DATA[1] I/O, N/A ULPI bi-directional data bus. CMOS Revision 1.2 (02-08-13) 14 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table2.2 USB3343 Pin Descriptions (continued) DIRECTION/ ACTIVE DESCRIPTION PIN NAME TYPE LEVEL 6 DATA[2] I/O, N/A ULPI bi-directional data bus. CMOS 7 DATA[3] I/O, N/A ULPI bi-directional data bus. CMOS 8 DATA[4] I/O, N/A ULPI bi-directional data bus. CMOS 9 Power N/A ULPI interface supply voltage. When RESETB is low VDDIO and VDDIO is powered on, ULPI pins will tri-state. 10 DATA[5] I/O, N/A ULPI bi-directional data bus. CMOS 11 DATA[6] I/O, N/A ULPI bi-directional data bus. CMOS 12 DATA[7] I/O, N/A ULPI bi-directional data bus. DATA[7] is the MSB. CMOS 13 DP I/O, N/A D+ pin of the USB cable. Analog 14 DM I/O, N/A D- pin of the USB cable. Analog 15 VDD33 Power N/A 3.3V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 16 VBAT Power N/A Regulator input. The regulator supply can be from 5.5V to 3.0V. 17 VBUS I/O, N/A This pin is used for the VBUS comparator inputs and Analog for VBUS pulsing during session request protocol. An external resistor, R , is required between this VBUS pin and the USB connector. 18 ID Input, N/A For device applications the ID pin is connected to Analog VDD33. For Host applications ID is grounded. For OTG applications the ID pin is connected to the USB connector. 19 RBIAS Analog, N/A Bias Resistor pin. This pin requires an 8.06kΩ (±1%) CMOS resistor to ground, placed as close as possible to the USB334x. Nominal voltage during ULPI operation is 0.8V. 20 XO Output, N/A Crystal pin. If using an external clock on REFCLK / CMOS XI, this pin should be floated. 21 REFCLK/XI Input, N/A ULPI Clock Out Mode: CMOS Model-specific reference clock or XI (crystal in) pin. See on page 2. ULPI Clock In Mode: 60MHz ULPI clock input. SMSC USB334x 15 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table2.2 USB3343 Pin Descriptions (continued) DIRECTION/ ACTIVE DESCRIPTION PIN NAME TYPE LEVEL 22 RESETB Input, Low When low, the part is suspended and the 3.3V and CMOS, 1.8V regulators are disabled. When high, the USB334x will operate as a normal ULPI device, as described in Section5.6.2. The state of this pin may be changed asynchronously to the clock signals. When asserted for a minimum of 1 microsecond and then de-asserted, the ULPI registers are reset to their default state and all internal state machines are reset. 23 VDD18 Power N/A 1.8V Regulator Output. A 1.0uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB334x. 24 STP Input, High The Link asserts STP for one clock cycle to stop the CMOS data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. FLAG GND Ground N/A Ground. Revision 1.2 (02-08-13) 16 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 3 Limiting Values 3.1 Absolute Maximum Ratings Table3.1 Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBUS, VBAT, ID, DP, DM, V Voltage measured at pin. -0.5 +6.0 V MAX_5V SPK_L, and SPK_R VBUS tolerant to 30V with voltage to GND external R . VBUS Maximum VDD18 voltage V -0.5 2.5 V MAX_18V to Ground Maximum VDD33 voltage V -0.5 4.0 V MAX_33V to Ground Maximum VDDIO voltage V -0.5 4.0 V MAX_IOV to Ground (USB3343) Maximum I/O voltage to V -0.5 2.5 V MAX_IN Ground (USB3341, USB3346, and USB3347) Maximum I/O voltage to V -0.5 V + 0.7 MAX_IN DDIO Ground (USB3343) Operating Temperature T -40 85 C MAX_OP Storage Temperature T -55 150 C MAX_STG Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3.2 Recommended Operating Conditions Table3.2 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBAT to GND V 3.0 5.5 V BAT VDD33 to GND V 3.0 3.3 3.6 V DD33 VDD18 to GND V 1.6 1.8 2.0 V DD18 VDDIO to GND V 1.6 1.8-3.3 3.6 V DDIO Input Voltage on Digital V 0.0 V V I DD18 Pins (RESETB, STP, DIR, NXT, DATA[7:0]) (USB3341, USB3346, and USB3347) SMSC USB334x 17 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table3.2 Recommended Operating Conditions (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Voltage on Digital V 0.0 V V I DDIO Pins (RESETB, STP, DIR, NXT, DATA[7:0]) (USB3343) Voltage on Analog I/O V 0.0 V V I(I/O) DD33 Pins (DP, DM, ID, SPK_L, SPK_R) VBUS to GND V 0.0 5.5 V VMAX Ambient Temperature T -40 85 C A Revision 1.2 (02-08-13) 18 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 4 Electrical Characteristics The following conditions are assumed unless otherwise specified: V = 3.0 to 3.6V; VDD18 = 1.6 to 2.0V; V = 0V; T = -40C to +85C DD33 SS A 4.1 Operating Current Table4.1 Operating Current (USB3341, USB3346, and USB3347) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Synchronous Mode Current I USB Idle 22 23 25 mA VBAT(SYNC) (Default Configuration) Synchronous Mode Current I Active USB Transfer 38 40 52 mA VBAT(HS) (HS USB operation) Synchronous Mode Current I Active USB Transfer 29 34 43 mA VBAT(FS) (FS/LS USB operation) Serial Mode Current I 6 8 9 mA VBAT(FS_S) (FS/LS USB) Note4.1 USB UART Current I 6 8 9 mA VBAT(UART) Note4.1 USB Audio Mode I V = 4.2V 63 71 117 uA VBAT(AUDIO) VBAT Note4.2 Low Power Mode I V = 4.2V 29 36 81 uA VBAT(SUSPEND) VBAT Note4.2 RESET Mode I RESETB = 0 0 1 11 uA VBAT(RSTB) V = 4.2V VBAT Table4.2 Operating Current (USB3343) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Synchronous Mode Current I USB Idle 18 22 24 mA VBAT(SYNC) (Default Configuration) I 1 2 5 mA VIO(SYNC) Synchronous Mode Current I Active USB Transfer 33 35 37 mA VBAT(HS) (HS USB operation) I 5 6 14 mA VIO(HS) Synchronous Mode Current I Active USB Transfer 25 28.5 30 mA VBAT(FS) (FS/LS USB operation) I 4 5 13 mA VIO(FS) Serial Mode Current I 7 8 9 mA VBAT(FS_S) (FS/LS USB) Note4.1 I 0 0.1 0.7 mA VIO(FS_S) USB UART Current I 7 8 9 mA VBAT(UART) Note4.1 I 0 0.1 0.7 mA VIO(UART) SMSC USB334x 19 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table4.2 Operating Current (USB3343) (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low Power Mode I V = 4.2V 29 32 83 uA VBAT(SUSPEND) VBAT Note4.2 V 1.8V VDDIO = Note4.3 I 0 0 2 uA VIO(SUSPEND) RESET Mode I RESETB = 0 0.1 1 12 uA VBAT(RSTB) Note4.3 V = 4.2V VBAT IVIO(RSTB) VVDDIO = 1.8V 0 0 7 uA Note4.1 ClockSuspendM bit = 0. Note4.2 SessEnd, VbusVld, and IdFloat comparators disabled. STP Interface protection disabled. Note4.3 REFCLK is OFF 4.2 Clock Specifications The model number for each frequency of REFCLK is provided in on page 2. Table4.3 Clock Specifications PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Suspend Recovery Time T LPM Enable = 0 1.0 1.1 1.2 ms START T LPM Enable = 1 125 150 uS START_LPM PHY Preparation Time T LPM Enable = 0 1.0 1.1 1.2 ms PREP 60MHz REFCLK T LPM Enable = 1 125 150 uS PREP_LPM CLKOUT Duty Cycle DC ULPI Clock Input Mode 45 55 % CLKOUT REFCLK Duty Cycle DC 20 80 % REFCLK REFCLK Frequency Accuracy F -500 +500 PPM REFCLK Note: T and T are measured from the time when REFCLK and RESETB are both valid to START PREP when the USB334x de-asserts DIR. Note: The USB334x uses the AutoResume feature, Section6.4.1.4, to allow a host start-up time of less than 1ms. 4.3 ULPI Interface Timing Table4.4 ULPI Interface Timing PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 60MHz ULPI Output Clock Note4.4 Setup time (STP, data in) T , T Model-specific REFCLK 5.0 ns SC SD Hold time (STP, data in) T , T Model-specific REFCLK 0.0 ns HC HD Output delay (control out, 8-bit data out) T , T Model-specific REFCLK 1.5 6 ns DC DD 60MHz ULPI Input Clock Revision 1.2 (02-08-13) 20 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table4.4 ULPI Interface Timing (continued) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Setup time (STP, data in) T , T 60MHz REFCLK 3 ns SC SD Hold time (STP, data in) T , T 60MHz REFCLK 0 ns HC HD Output delay (control out, 8-bit data out) T , T 60Mhz REFCLK 0.5 6.0 ns DC DD Note: C = 10pF. Load Note4.4 REFCLK does not need to be aligned in any way to the ULPI signals. 4.4 Digital IO Pins Table4.5 Digital IO Characteristics: RESETB, STP, DIR, NXT, DATA[7:0], and REFCLK Pins PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low-Level Input Voltage V V 0.4 * V IL SS (USB3341, USB3346, and V DD18 USB3347) Low-Level Input Voltage V V 0.8 V IL SS (USB3343) High-Level Input Voltage V 0.68 * V V IH DD18 (USB3341, USB3346, and V DD18 USB3347) High-Level Input Voltage V 0.68 * V V IH DDIO (USB3343) V DDIO High-Level Input Voltage V 0.68 * V V IH_REF DD33 REFCLK and RESETB V DD18 (USB3341, USB3346, and USB3347) High-Level Input Voltage V 0.68 * V V IH_REF DD33 REFCLK and RESETB V DDIO (USB3343) Low-Level Output Voltage V I = 8mA 0.4 V OL OL High-Level Output Voltage V I = -8mA V V OH OH DD18 (USB3341, USB3346, and - 0.4 USB3347) High-Level Output Voltage V I = -8mA V - V OH OH DDIO (USB3343) 0.4 Output rise time T C = 10pF 1.19 nS IORISE LOAD Output fall time T C = 10pF 1.56 nS IOFALL LOAD Input Leakage Current I ±10 uA LI Pin Capacitance Cpin 4 pF STP pull-up resistance R InterfaceProtectDisable = 55 67 80 kΩ STP 0 DATA[7:0] pull-down R ULPI Synchronous Mode 55 67 77 kΩ DATA_PD resistance SMSC USB334x 21 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table4.5 Digital IO Characteristics: RESETB, STP, DIR, NXT, DATA[7:0], and REFCLK Pins (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLKOUT External Drive VIH_ED At start-up or following 0.4 * V reset V (USB3341, USB3346, and DD18 USB3347) CLKOUT External Drive VIH_ED At start-up or following 0.4 * V reset V (USB3343) DDIO 4.5 DC Characteristics: Analog I/O Pins Table4.6 DC Characteristics: Analog I/O Pins (DP/DM) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LS/FS FUNCTIONALITY Input levels Differential Receiver Input V | V(DP) - V(DM) | 0.2 V DIFS Sensitivity Differential Receiver V 0.8 2.5 V CMFS Common-Mode Voltage Single-Ended Receiver Low V Note4.6 0.8 V ILSE Level Input Voltage Single-Ended Receiver High V Note4.6 2.0 V IHSE Level Input Voltage Single-Ended Receiver V 0.050 0.150 V HYSSE Hysteresis Output Levels Low Level Output Voltage V Pull-up resistor on DP; 0.3 V FSOL R = 1.5kΩ to V L DD33 High Level Output Voltage V Pull-down resistor on DP, 2.8 3.6 V FSOH DM; Note4.6 R = 15kΩ to GND L Termination Driver Output Impedance for Z Steady state drive 40.5 45 49.5 Ω HSDRV HS Input Impedance Z RX, RPU, RPD disabled 1.0 MΩ INP Pull-up Resistor Impedance R Bus Idle, Note4.5 0.900 1.24 1.575 kΩ PU Pull-up Resistor Impedance R Device Receiving, 1.425 2.26 3.09 kΩ PU Note4.5 Pull-dn Resistor Impedance R Note4.5 14.25 16.9 20 kΩ PD HS FUNCTIONALITY Input levels HS Differential Input V | V(DP) - V(DM) | 100 mV DIHS Sensitivity Revision 1.2 (02-08-13) 22 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table4.6 DC Characteristics: Analog I/O Pins (DP/DM) (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HS Data Signaling Common V -50 500 mV CMHS Mode Voltage Range HS Squelch Detection V VariSense[1:0] = 00b 100 150 mV HSSQ Threshold (Differential) Note4.7 HS Disconnect Threshold V 525 625 mV HSDSC Output Levels High Speed Low Level V 45Ω load -10 10 mV HSOL Output Voltage (DP/DM referenced to GND) High Speed High Level V 45Ω load 360 440 mV HSOH Output Voltage (DP/DM referenced to GND) High Speed IDLE Level V 45Ω load -10 10 mV OLHS Output Voltage (DP/DM referenced to GND) Chirp-J Output Voltage V HS termination resistor 700 1100 mV CHIRPJ (Differential) disabled, pull-up resistor connected. 45Ω load. Chirp-K Output Voltage V HS termination resistor -900 -500 mV CHIRPK (Differential) disabled, pull-up resistor connected. 45Ω load. Leakage Current OFF-State Leakage Current I ±10 uA LZ Port Capacitance Transceiver Input C Pin to GND 5 10 pF IN Capacitance Note4.5 The resistor value follows the 27% Resistor ECN published by the USB-IF. Note4.6 The values shown are valid when the USB RegOutput bits in the USB IO & Power Management register are set to the default value. Note4.7 An automatic waiver up to 200mV is granted to accommodate system-level elements such as measurement/test fixtures, captive cables, EMI components, and ESD suppression. This parameter can be tuned using VariSense technology, as defined in Section7.1.3.1of Chapter 7. SMSC USB334x 23 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 4.6 Dynamic Characteristics: Analog I/O Pins Table4.7 Dynamic Characteristics: Analog I/O Pins (DP/DM) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FS Output Driver Timing FS Rise Time T C = 50pF; 10 to 90% of 4 20 ns FR L |V - V | OH OL FS Fall Time T C = 50pF; 10 to 90% of 4 20 ns FF L |V - V | OH OL Output Signal Crossover V Excluding the first 1.3 2.0 V CRS Voltage transition from IDLE state Differential Rise/Fall Time T Excluding the first 90 111.1 % FRFM Matching transition from IDLE state LS Output Driver Timing LS Rise Time T C = 50-600pF; 75 300 ns LR L 10 to 90% of |V - V | OH OL LS Fall Time T C = 50-600pF; 75 300 ns LF L 10 to 90% of |V - V | OH OL Differential Rise/Fall Time T Excluding the first 80 125 % LRFM Matching transition from IDLE state HS Output Driver Timing Differential Rise Time T 500 ps HSR Differential Fall Time T 500 ps HSF Driver Waveform Eye pattern of Template 1 Requirements in USB 2.0 specification High Speed Mode Timing Receiver Waveform Eye pattern of Template 4 Requirements in USB 2.0 specification Data Source Jitter and Eye pattern of Template 4 Receiver Jitter Tolerance in USB 2.0 specification 4.7 VBUS Electrical Characteristics Table4.8 VBUS Electrical Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SessEnd trip point V 0.2 0.5 0.8 V SessEnd SessVld trip point V 0.8 1.4 2.0 V SessVld VbusVld trip point V 4.4 4.58 4.75 V VbusVld VBUS Pull-Up R VBUS to VDD33 Note4.8 1.29 1.34 1.45 kΩ VPU (ChargeVbus = 1) Revision 1.2 (02-08-13) 24 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table4.8 VBUS Electrical Characteristics (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBUS Pull-down R VBUS to GND Note4.8 1.55 1.7 1.85 kΩ VPD (DisChargeVbus = 1) VBUS Impedance R VBUS to GND 40 75 100 kΩ VB A-Device Impedance to R Maximum Impedance to 100 kΩ IdGnd ground ground on ID pin Note4.8 The R and R values include the required 1kΩ external R resistor. VPD VPU VBUS 4.8 ID Electrical Characteristics Table4.9 ID Electrical Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ID Ground Trip Point V 0.4 0.7 0.9 V IdGnd ID Float Trip Point V 1.6 2.2 2.5 V IdFloat ID pull-up resistance R IdPullup = 1 80 100 120 kΩ ID ID weak pull-up resistance R IdPullup = 0 1 MΩ IDW ID pull-dn resistance R IdGndDrv = 1 1000 Ω IDPD 4.9 USB Audio Switch Characteristics Table4.10 USB Audio Switch Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Minimum “ON” Resistance R 0 < V < V 2.7 5 5.8 Ω ON_Min switch DD33 Maximum “ON” Resistance R 0 < V < V 4.5 7 13 Ω ON_Max switch DD33 Minimum “OFF” R 0 < V < V 1 MΩ OFF_Min switch DD33 Resistance 4.10 USB Charger Detection Characteristics Table4.11 USB Charger Detection Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data Source Voltage V I < 250uA 0.5 0.7 V DAT_SRC DAT_SRC Data Detect Voltage V 0.25 0.4 V DAT_REF Data Source Current I 250 uA DAT_SRC Data Sink Current I 50 150 uA DAT_SINK SMSC USB334x 25 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table4.11 USB Charger Detection Characteristics (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data Connect Current I 7 13 uA DP_SRC Weak Pull-up Resistor R Configured by bits 4 and 5 128 170 212 kΩ CD Impedance in USB IO & Power Management register. 4.11 Regulator Output Voltages and Capacitor Requirement Table4.12 Regulator Output Voltages and Capacitor Requirement PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Regulator Output Voltage V 5.5V > VBAT > 3.0V 2.8 3.3 3.6 V DD33 USB UART Mode & UART 2.7 3.0 3.3 V RegOutput[1:0] = 01 6V > VBAT > 3.0V USB UART Mode & UART 2.47 2.75 3.03 V RegOutput[1:0] = 10 6V > VBAT > 3.0V USB UART Mode & UART 2.25 2.5 2.75 V RegOutput[1:0] = 11 6V > VBAT > 3.0V Regulator Bypass Capacitor C 1.0 uF OUT33 Bypass Capacitor ESR C 1 Ω ESR33 Regulator Output Voltage V 3.6V > VDD33 > 2.25V 1.6 1.8 2.0 V DD18 Regulator Bypass Capacitor C 1.0 uF OUT18 Bypass Capacitor ESR C 1 Ω ESR18 Revision 1.2 (02-08-13) 26 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 4.12 Piezoelectric Resonator for Internal Oscillator The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section5.4. See Table4.13 for the recommended crystal specifications. Table4.13 USB334x Quartz Crystal Specifications PARAMETER SYMBOL MIN NOM MAX UNITS NOTES Crystal Cut AT, typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency F - See on - MHz fund page 2 Total Allowable PPM Budget - - ±500 PPM Note4.9 Shunt Capacitance C - 7 typ - pF O Load Capacitance C - 20 typ - pF L Drive Level P 0.1 - - mW W Equivalent Series Resistance R - - 30 Ohm 1 USB334x REFCLK Pin - 3 typ - pF Note4.10 Capacitance USB334x XO Pin Capacitance - 3 typ - pF Note4.10 Note4.9 The required bit rate accuracy for Hi-Speed USB applications is ±500 ppm as provided in the USB 2.0 Specification. This takes into account the effect of voltage, temperature, aging, etc. Note4.10 This number includes the pad, the bond wire and the lead frame. Printed Circuit Board (PCB) capacitance is not included in this value. The PCB capacitance value and the capacitance value of the XO and REFCLK pins are required to accurately calculate the value of the two external load capacitors. 4.13 ESD and Latch-Up Performance Table4.14 ESD and Latch-Up Performance PARAMETER CONDITIONS MIN TYP MAX UNITS COMMENTS ESD PERFORMANCE Note4.11 Human Body Model ±8 kV Device System EN/IEC 61000-4-2 Contact ±25 kV 3rd party system test Discharge System EN/IEC 61000-4-2 Air-gap ±25 kV 3rd party system test Discharge LATCH-UP PERFORMANCE All Pins EIA/JESD 78, Class II 150 mA SMSC USB334x 27 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Note4.11 REFCLK, XO(USB3343 only), ID, RESETB, SPK_L(USB3341, USB3346, and USB3347 only) and SPK_R (USB3341, USB3346, and USB3347 only) pins: ±5kV Human Body Model. Revision 1.2 (02-08-13) 28 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 5 Architecture Overview The USB334x consists of the blocks shown in the diagrams below. VDD18 VDD33 IdGnd DATA7 RIDW RID IdFloat DDAATTAA65 ID e DATA4 Rid Value ul O DATA3 VDD33 Mod ULPI Digitial al I DDAATTAA21 VBUS OVP RVPU SessEnd TG Digit SDTAPTA0 VBAT SessValid O NXT DIR VDD33 LDO RVB RVPD VbusValid CRELKSOETUBT n a a o at at cti LDO X D X D e Charger T R VDD18 ot Pr Detection D VDD33 VDD33 S E RCD RCD RPU RPU Integrated HS/FS/LS TX Low Jitter REFCLK DP TX Encoding PLL DM HS/FS/LS RX BIAS RBIAS SPK_L RPD RPD RX Decoding SPK_R Figure5.1 USB334x System Diagram (USB3341, USB3346, and USB3347) SMSC USB334x 29 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet VDDIO VDD33 DATA7 IdGnd RIDW RID DDAATTAA65 IdFloat DATA4 ID e Rid Value ul O DATA3 VDD33 Mod ULPI Digitial al I DDAATTAA21 VBUS OVP RVPU SessEnd TG Digit SDTAPTA0 O NXT VBAT SessValid DIR LDO CLKOUT VDD33 n RVB RVPD VbusValid RESETB o cti ata ata rote LDO Charger TX D RX D VDD18 P D Detection S VDD33 VDD33 E RCD RCD RPU RPU Integrated REFCLK / XI HS/FS/LS TX Low Jitter DP TX Encoding XO PLL DM HS/FS/LS RX BIAS RBIAS RPD RPD RX Decoding Figure5.2 USB334x System Diagram (USB3343) 5.1 ULPI Digital Operation and Interface This section of the USB334x is covered in detail in Chapter6, ULPI Operation. 5.2 USB 2.0 Hi-Speed Transceiver The blocks in the lower left-hand corner of interface to the DP/DM pins. 5.2.1 USB Transceiver The USB334x transceiver includes a Universal Serial Bus Specification Rev 2.0 compliant receiver and transmitter. The DP/DM signals in the USB cable connect directly to the receivers and transmitters. The receiver consists of receivers for HS and FS/LS mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. For HS mode support, the HS RX block contains a squelch circuit to insure that noise is not interpreted as data. The RX block also includes a single-ended receiver on each of the data lines to determine the correct FS linestate. Data from the Link is encoded, bit stuffed, serialized and transmitted onto the USB cable by the transmitter. Separate differential FS/LS and HS transmitters are included to support all modes. The USB334x TX block meets the HS signalling level requirements in the USB 2.0 Specification when the PCB traces from the DP and DM pins to the USB connector are correctly designed. In some systems the proper 90 ohm differential impedance can not be maintained and it may be desirable to compensate for loss by adjusting the HS transmitter amplitude and this HS squelch threshold. The Revision 1.2 (02-08-13) 30 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet PHYBoost bits in the HS Compensation Register may be configured to adjust the HS transmitter amplitude at the DP and DM pins. The VariSense bits in the HS Compensation Register can also be used to lower the squelch threshold to compensate for losses on the PCB. To ensure proper operation of the USB transceiver the settings of Table5.1 must be followed. 5.2.2 Termination Resistors The USB334x transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω High Speed termination resistors. These resistors require no tuning or trimming by the Link. The state of the resistors is determined by the operating mode of the transceiver when operating in synchronous mode. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration of the termination resistors. All possible valid resistor combinations are shown in Table5.1, and operation is guaranteed in only the configurations shown. If a ULPI Register Setting is configured that does not match a setting in the table, the transceiver operation is not guaranteed and the settings in the last row of Table5.1 will be used.  RPU_DP_EN activates the 1.5kΩ DP pull-up resistor  RPU_DM_EN activates the 1.5kΩ DM pull-up resistor  RPD_DP_EN activates the 15kΩ DP pull-down resistor  RPD_DM_EN activates the 15kΩ DM pull-down resistor  HSTERM_EN activates the 45Ω DP and DM High Speed termination resistors Table5.1 DP/DM Termination vs. Signaling Mode USB334X TERMINATION ULPI REGISTER SETTINGS RESISTOR SETTINGS SIGNALING MODE cvrSelect[1:0] TermSelect OpMode[1:0] DpPulldown DmPulldown RPU_DP_EN RPU_DM_EN RPD_DP_EN RPD_DM_EN HSTERM_EN X General Settings Tri-State Drivers, Note5.1 XXb Xb 01b Xb Xb 0b 0b 0b 0b 0b Power-up or VBUS < V 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b SESSEND Host Settings Host Chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Host High Speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b Host Full Speed X1b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Low Speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b SMSC USB334x 31 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table5.1 DP/DM Termination vs. Signaling Mode (continued) USB334X TERMINATION ULPI REGISTER SETTINGS RESISTOR SETTINGS SIGNALING MODE cvrSelect[1:0] TermSelect OpMode[1:0] DpPulldown DmPulldown RPU_DP_EN RPU_DM_EN RPD_DP_EN RPD_DM_EN HSTERM_EN X Host LS Resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Test J/Test_K 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Peripheral Settings Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b Peripheral FS 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral LS 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b OTG device, Peripheral Chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b OTG device, Peripheral FS 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral Test J/Test K 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b Charger Detection Connect Detect 01b 0b 00b 0b 1b 0b 0b 0b 1b 0b Any combination not defined above, 0b 0b 1b 1b 0b Note5.2 Note: This is equivalent to Table 40, Section 4.4 of the ULPI 1.1 specification. Note: USB334x does not support operation as an upstream hub port. See Chapter 6.4.1.3. Note5.1 When RESETB = 0 The HS termination will tri-state the USB drivers Note5.2 The transceiver operation is not guaranteed in a combination that is not defined. The USB334x uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table4.6. Revision 1.2 (02-08-13) 32 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 5.3 Bias Generator This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06KΩ, 1% tolerance, reference resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the USB334x to minimize the trace length. The nominal voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80μW of power. 5.4 Crystal Reference Support (USB3343 only) The USB3343 provide support for a 26MHz crystal to provide the reference frequency required by the device in place of a clock oscillator. The crystal should be connected to the REFCLK/XI and XO pins as shown in Figure8.2. If a 26MHz clock oscillator is used in place of a crystal, it should be driven into the REFCLK/XI pin, and the XO pin should be left floating. Proper care should be taken to ensure that a crystal is selected with appropriate power dissipation characteristics. 5.5 Integrated Low Jitter PLL The USB334x uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS USB signal quality. This clock is used by the PHY during both transmit and receive. The USB334x PLL requires an accurate frequency reference to be driven on the REFCLK pin. 5.5.1 REFCLK Frequency Selection The USB334x PLL is designed to operate in one of two reference clock modes. In the first mode, the 60MHz ULPI clock is driven on the REFCLK pin. In the second mode a reference clock is driven on the REFCLK pin. The Link is driving the ULPI clock, in the first mode, and this is referred to as ULPI Clock Input Mode. In the second mode, the USB334x generates the ULPI clock, and this is referred to as ULPI Clock Output Mode. During start-up, the USB334x monitors the CLKOUT pin. If a connection to VDD18 (USB3341, USB3346, and USB3347) or VDDIO (USB3343) is detected, the USB334x is configured for a 60MHz ULPI reference clock driven on the REFCLK pin. Section5.5.1.1 and Section5.5.1.2 describe how to configure the USB334x for either ULPI Clock Input Mode or ULPI Clock Output Mode. 5.5.1.1 ULPI Clock Input Mode (60MHz REFCLK Mode) When using ULPI Clock Input Mode, the Link must supply the 60MHz ULPI clock to the USB334x. In this mode the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDD18 (USB3341, USB3346, and USB3347) or VDDIO(USB3343). After the PLL has locked to the correct frequency, the USB334x will de-assert DIR and the Link can begin using the ULPI interface. The USB334x is guaranteed to start the clock within the time specified in Table4.3. For Host applications, the ULPI AutoResume bit should be enabled. This is described in Section6.4.1.4. SMSC USB334x 33 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet VDD18/ ~~ VDDIO CLKOUT ULPI Clk Out REFCLK To PLL Link Reference Clk In ~~ SMSC PHY Clock Source Figure5.1 Configuring the USB334x for ULPI Clock Input Mode (60 MHz) 5.5.1.2 ULPI Clock Output Mode When using ULPI Clock Output Mode, the USB334x generates the 60MHz ULPI clock used by the Link. In this mode, the REFCLK pin must be driven with the model-specific frequency, and the CLKOUT pin sources the 60MHz ULPI clock to the Link. When using ULPI Clock Output Mode, the system must not drive the CLKOUT pin following POR or hardware reset with a voltage that exceeds the value of V provided in Table4.4. An example of ULPI Clock Output Mode is shown in IH_ED Figure8.1 After the PLL has locked to the correct frequency, the USB334x generates the 60MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB334x is guaranteed to start the clock within the time specified in Table4.3, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be enabled. This is described in Section6.4.1.4. When using ULPI Clock Output Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI interface signals. There is no need to align the phase of the REFCLK and the CLKOUT. For the USB3341, USB3343, USB3346, and USB3347, the reference clock frequency required is shown on page 2. Revision 1.2 (02-08-13) 34 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet ~~ ULPI Clk In CLKOUT From PLL Link Clock REFCLK Source To PLL ~~ SMSC PHY Figure5.2 Configuring the USB334x for ULPI Clock Output Mode 5.5.2 REFCLK Amplitude The reference clock should be connected to the REFCLK pin as shown in the application diagrams, . The REFCLK pin is designed to be driven with a square wave from 0V to VDD18 (USB3341, USB3346, and USB3347) or VDDIO (USB3343), but can be driven with a square wave from 0V to as high as 3.6V. The USB334x uses only the positive edge of the REFCLK. If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the REFCLK pin. If using an analog clock the DC bias should be set at the mid-point of the VDD18 supply using a bias circuit as shown in Figure5.3. The amplitude must be greater than 300mV peak to peak. The component values provided in Figure5.3 are for example only. The actual values should be selected to satisfy system requirements. The REFCLK amplitude must comply with the signal amplitudes shown in Table4.5 and the duty cycle in Table4.3. 1.8V Supply k 7 4 To REFCLK pin Clock 0.1uF k 7 4 Figure5.3 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level SMSC USB334x 35 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 5.5.3 REFCLK Jitter The USB334x is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Clock Input Mode or ULPI Clock Output Mode, the USB334x High Speed eye diagram may be degraded. The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table4.3. 5.5.4 REFCLK Enable/Disable The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start running after the time specified in Table4.3. If the reference clock enable is delayed relative to the RESETB pin, the ULPI interface will start operation delayed by the same amount. The reference clock can be run at anytime the RESETB pin is low without causing the USB334x to start-up or draw current. When the USB334x is placed in Low Power Mode or Carkit Mode, the reference clock can be stopped after the final ULPI register write is complete. The STP pin is asserted to bring the USB334x out of Low Power Mode. The reference clock should be started at the same time STP is asserted to minimize the USB334x start-up time. If the reference clock is stopped while in ULPI Synchronous mode the PLL will come out of lock and the frequency of oscillation will decrease to the minimum allowed by the PLL design. If the reference clock is stopped during a USB session, the session may drop. 5.6 Internal Regulators and POR The USB334x includes integrated power management functions, including a Low-Dropout regulator that can be used to generate the 3.3V USB supply, an integrated 1.8V regulator, and a POR generator described in Section5.6.2. 5.6.1 Integrated Low Dropout Regulators The USB334x includes two integrated linear regulators. Power sourced at the VBAT pin is regulated to 3.3V and 1.8V output on the VDD33 and VDD18 pins. To ensure stability, both regulators require an external bypass capacitor as specified in Table4.12 placed as close to the pin as possible. The USB334x regulators are designed to generate the 3.3 Volt and 1.8 Volt supplies for the USB334x only. Using the regulators to provide current for other circuits is not recommended and SMSC does not guarantee USB performance or regulator stability. During USB UART mode the 3.3V regulator output voltage can be changed to allow the USB334x to work with UARTs operating at different operating voltages. The 3.3V regulator output is configured to the voltages shown in Table4.12 with the UART RegOutput[1:0] bits in the USB IO & Power Management register. The regulators are enabled by the RESETB pin. When RESETB pin is low both regulators are disabled and the regulator outputs are pulled low by weak pull-down. The RESETB pin must be brought high to enable the regulators. For peripheral-only or host-only bus-powered applications, the input to VBAT may be derived from the VBUS pin of the USB connector. In this configuration, the supply must be capable of withstanding any transient voltage present at the VBUS pin of the USB connector. SMSC does not recommend connecting the VBAT pin to the VBUS terminal of the USB connector. 5.6.2 Power On Reset (POR) The USB334x provides a POR circuit that generates an internal reset pulse after the VDD18 supply is stable. After the internal POR goes high the USB334x will release from reset and begin normal ULPI operation as described in Section5.3. Revision 1.2 (02-08-13) 36 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet The ULPI registers will power up in their default state summarized in Table7.1 when the 1.8V supply comes up. Cycling the RESETB pin can also be used to reset the ULPI registers to their default state (and reset all internal state machines) by bringing the pin low for a minimum of 1 microsecond and then high. It is not necessary to wait for the VDD33 and VDD18 pins to discharge to 0 volts to reset the part. The RESETB pin must be pulled high to enable the 3.3V and 1.8V regulators. A pull-down resistor is not present on the RESETB pin and therefore the system should drive the RESETB pin to the desired state at all times. If the system does not need to place the USB334x into reset mode the RESETB pin can be connected to a supply between 1.8V and 3.3V. 5.6.3 Recommended Power Supply Sequence For USB operation, the USB334x requires a valid voltage on the VBAT and VDDIO pins. The VDD33 and VDD18 regulators are automatically enabled when the RESETB pin is brought high. Table5.2 presents the power supply configurations in more detail. The RESETB pin can be held low until the VBAT supply is stable. If the Link is not ready to interface the USB334x, the Link may choose to hold the RESETB pin low until it is ready to control the ULPI interface. Table5.2 Operating Mode vs. Power Supply Configuration VDDIO VBAT (Note5.4) RESETB OPERATING MODES AVAILABLE 0 0 0 Powered Off 1 X 0 RESET Mode. (Note5.3) 1 1 1 Full USB operation as described in Chapter 6. Note5.3 VDDIO must be present for ULPI pins to tri-state. Note5.4 USB3343 only. 5.6.4 Start-Up The power on default state of the USB334x is ULPI Synchronous mode. The USB334x requires the following conditions to begin operation: the power supplies must be stable, the REFCLK must be present and the RESETB pin must be high. After these conditions are met, the USB334x will begin ULPI operation that is described in Chapter 6. Figure5.4 below shows a timing diagram to illustrate the start-up of the USB334x. At T0, the supplies are stable and the USB334x is held in reset mode. At T1, the Link drives RESETB high after the REFCLK has started. The RESETB pin may be brought high asynchronously to REFCLK. Once, the 3.3V and 1.8V internal supplies become stable the USB334x will apply the 15Kohm pull downs to the data bus and assert DIR until the internal PLL has locked. After the PLL has locked, the USB334x will check that the Link has de-asserted STP and at T2 it will de-assert DIR and begin ULPI operation. The ULPI bus will be available as shown in Figure5.4 in the time defined as T given in Table4.3. START If the REFCLK signal starts after the RESETB pin is brought high, then time T0 will begin when REFCLK starts. T also assumes that the Link has de-asserted STP. If the Link has held STP START high the USB334x will hold DIR high until STP is de-asserted. When the LINK de-asserts STP, it must be ready drive the ULPI data bus to idle (00h) for a minimum of one clock cycle after DIR de-asserts. SMSC USB334x 37 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet T0 T1 T2 SUPPLIES STABLE REFCLK REFCLK valid RESETB DATA[7:0] PHY Tri-States PHY Drives Idle IDLE RXCMD IDLE DIR PHY Tri-States PHY Drives High STP LINK Drives Low T START Figure5.4 ULPI Start-up Timing 5.7 USB On-The-Go (OTG) The USB334x provides support for the USB OTG protocol. OTG allows the USB334x to be dynamically configured as a host or peripheral depending on the type of cable inserted into the Micro-AB receptacle. When the Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB device becomes the A-device. When a Micro-B plug is inserted, the device becomes the B-device. The OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral. The differences are covered in the “On-The-Go Supplement to the USB 2.0 Specification”. In applications where only USB Host or USB Peripheral is required, the OTG Module is unused. 5.7.1 ID Resistor Detection The ID pin of the USB connector is monitored by the ID pin of the USB334x to detect the attachment of different types of USB devices and cables. For device only applications that do not use the ID signal the ID pin should be connected to VDD33. The block diagram of the ID detection circuitry is shown in Figure5.5 and the related parameters are given in Table4.9. Revision 1.2 (02-08-13) 38 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet ~~ VDD33 IdPullup M K >1W =100 ID RID RID To USB Con. IdGnd V IdGnd ref en IdGnd Rise or IdGnd Fall IdGndDrv IdFloat V IdFloat ref en IdFloatRise or IdFloatFall RidValue Rid ADC OTG Module ~~ Figure5.5 USB334x ID Resistor Detection Circuitry 5.7.1.1 USB OTG Operation The USB334x can detect ID grounded and ID floating to determine if an A or B cable has been inserted. The A plug will ground the ID pin while the B plug will float the ID pin. These are the only two valid states allowed in the OTG Protocol. To monitor the status of the ID pin, the Link activates the IdPullup bit in the OTG Control register, waits 50mS and then reads the status of the IdGnd bit in the USB Interrupt Status register. If an A cable has been inserted the IdGnd bit will read 0. If a B cable is inserted, the ID pin is floating and the IdGnd bit will read 1. The USB334x provides an integrated weak pull-up resistor on the ID pin, R . This resistor is present IDW to keep the ID pin in a known state when the IdPullup bit is disabled and the ID pin is floated. In addition to keeping the ID pin in a known state, it enables the USB334x to generate an interrupt to inform the link when a cable with a resistor to ground has been attached to the ID pin. The weak pull- up is small enough that the largest valid RID resistor pulls the ID pin low and causes the IdGnd comparator to go low. After the link has detected an ID pin state change, the RID converter can be used to determine the resistor value as described in Section5.7.1.2. 5.7.1.2 Measuring ID Resistance to Ground The Link can use the integrated resistance measurement capabilities of the USB334x to determine the value of an ID resistance to ground. The following table details the valid values of resistance to ground that the USB334x can detect. SMSC USB334x 39 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table5.3 Valid Values of ID Resistance to Ground ID RESISTANCE TO GROUND RID VALUE Ground 000 75Ω +/-1% 001 102kΩ +/-1% 010 200kΩ+/-1% 011 Floating 101 Note: IdPullUp = 0 The ID resistance to ground can be read while the USB334x is in Synchronous Mode. When a resistor to ground is attached to the ID pin, the state of the IdGnd comparator will change. After the Link has detected ID transition to ground, it can use the methods described in Section6.8 to operate the Rid converter. 5.7.1.3 Using IdFloat Comparator (not recommended) Note: The ULPI specification details a method to detect a 102kΩ resistance to ground using the IdFloat comparator. This method can only detect 0ohms, 102kΩ, and floating terminations of the ID pin. Due to this limitation it is recommended to use the RID Converter as described in Section5.7.1.2. The ID pin can be either grounded, floated, or connected to ground with a 102kΩ external resistor. To detect the 102K resistor, set the idPullup bit in the OTG Control register, causing the USB334x to apply the 100K internal pull-up connected between the ID pin and VDD33. Set the idFloatRise and idFloatFall bits in the Carkit Interrupt Enable register to enable the IdFloat comparator to generate an RXCMD to the Link when the state of the IdFloat changes. As described in Figure6.3, the alt_int bit of the RXCMD will be set. The values of IdGnd and IdFloat are shown for the three types cables that can attach to the USB Connector in Table5.4. Table5.4 IdGnd and IdFloat vs. ID Resistance to Ground ID RESISTANCE IDGND IDFLOAT Float 1 1 102K 1 0 GND 0 0 Note: The ULPI register bits IdPullUp, IdFloatRise, and IdFloatFall should be enabled. To save current when an A Plug is inserted, the internal 102kΩ pull-up resistor can be disabled by clearing the IdPullUp bit in the OTG Control register and the IdFloatRise and IdFloatFall bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. If the cable is removed the weak R will pull the ID pin high. IDW The IdGnd value can be read using the ULPI USB Interrupt Status register, bit 4. In host mode, it can be set to generate an interrupt when IdGnd changes by setting the appropriate bits in the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. The IdFloat value can be read by reading the ULPI Carkit Interrupt Status register bit 0. Revision 1.2 (02-08-13) 40 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Note: The IdGnd switch has been provided to ground the ID pin for future applications. 5.7.2 VBUS Monitoring and VBUS Pulsing The USB334x includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and SessEnd comparators shown in Figure5.6 are fully integrated into the USB334x. These comparators are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from the USB Interrupt Status register. The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the VBUS voltage on the cable is valid. The SessVld comparator is used by the Link when configured as both an A or B device to indicate a session is requested or valid. Finally the SessEnd comparator is used by the B-device to indicate a USB session has ended. Also included in the VBUS Monitor and Pulsing block are the resistors used for VBUS pulsing in SRP. The resistors used for VBUS pulsing include a pull-down to ground and a pull-up to VDD33. In some applications, voltages much greater than 5.5V may be present at the VBUS pin of the USB connector. The USB334x includes an over voltage protection circuit that protects the VBUS pin of the USB334x from excessive voltages as shown in Figure5.6. ~~ VDD33 ChrgVbus 0.5V SessEnd en SessEnd Rise or SessEnd Fall U P V R SessValid VBUS VBUS 1.4V Overvoltage To USB Con. RVBUS Protection RVB RVPD VbusValid 4.575V en DischrgVbus VbusValid Rise or VbusValid Fall [0, X] [1, 0] RXCMD VbusValid EXTVBUS (logic 1) [1, 1] IndicatorComplement [UseExternalVbusindicator, IndicatorPassThru] SMSC PHY ~~ Figure5.6 USB334x OTG VBUS Block 5.7.2.1 SessEnd Comparator The SessEnd comparator is used during the Session Request Protocol (SRP). The comparator is used by the B-device to detect when a USB session has ended and it is safe to start Vbus Pulsing to request a USB session from the A-device. When VBUS goes below the threshold in Table4.8, the USB session is considered to be ended, and SessEnd will transition from 0 to 1. The SessEnd comparator can be SMSC USB334x 41 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, the SessEnd bit in the USB Interrupt Status register will read 0. The SessEnd Comparator is only used when configured as an OTG device. If the USB334x is used as a Host or Device only the SessEnd Comparator should be disabled, using the method described above. 5.7.2.2 SessVld Comparator The SessVld comparator is used when the PHY is configured as both an A and B device. When configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When configured as a B device, SessVld is used to detect the presence of VBUS. The SessVld comparator output can also be read from the USB Interrupt Status register. The SessVld comparator will also generate an RX CMD, as detailed in Section6.3.1, anytime the comparator changes state. The SessVld interrupts can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When the interrupts are disabled, the SessVld comparator is still operational and will generate RX CMD’s. The SessVld comparator trip point is detailed in Table4.9. Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device Session Valid comparator. The USB334x PHY combines the two comparators into one and uses the narrower threshold range. 5.7.2.3 VbusVld Comparator The VbusVld comparator is only used when the USB334x is configured as a host that can supply less than 100mA VBUS current. In the USB protocol, the A-device supplies the VBUS voltage and is responsible to ensure it remains within a specified voltage range. The VbusVld comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, bit 1 of the USB Interrupt Status register will return a 0. The VbusVld comparator threshold values are detailed in Table4.9. If the USB334x is used as a Device only the VbusValid Comparator should be disabled, using the method described above. The USB334x includes the external VbusVld indicator logic as detailed in the ULPI Specification. The external VbusVld indicator is tied to a logic one. The decoding of this logic is shown in Table5.5 below. By default this logic is disabled. Table5.5 External VBUS Indicator Logic USE EXTERNAL TYPICAL VBUS INDICATOR INDICATOR RXCMD VBUS VALID APPLICATION INDICATOR PASS THRU COMPLEMENT ENCODING SOURCE OTG Device 0 X X Internal VbusVld comparator (Default) 1 1 0 Fixed 1 1 1 1 Fixed 0 1 0 0 Internal VbusVld comparator. 1 0 1 Fixed 0 Standard Host 1 1 0 Fixed 1 1 1 1 Fixed 0 Standard 0 X X Internal VbusVld comparator. This Peripheral information should not be used by the Link. (Note5.5) Revision 1.2 (02-08-13) 42 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Note5.5 A peripheral should not use VbusVld to begin operation. The peripheral should use SessVld to detect the presence of VBUS on the USB connector. VbusVld should only be used for USB Host and OTG A-device applications. 5.7.2.4 VBUS Pulsing with Pull-up and Pull-down Resistors In addition to the internal VBUS comparators, the USB334x also includes the integrated VBUS pull-up and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge the VBUS voltage so that a Session Request can begin, the USB334x provides a pull-down resistor from VBUS to GND. This resistor is controlled by the DischargeVbus bit 3 of the OTG Control register. The pull-up resistor is connected between VBUS and VDD33. This resistor is used to pull VBUS above 2.1 volts so that the A-Device knows that a USB session has been requested. The state of the pull- up resistor is controlled by the bit 4 ChargeVbus of the OTG Control register. The Pull-Up and Pull- Down resistor values are detailed in Table4.9. The internal VBUS Pull-up and Pull-down resistors are designed to include the R external resistor VBUS in series. This external resistor is used by the VBUS Over voltage protection described below. 5.7.2.5 VBUS Input Impedance The OTG Supplement requires an A-Device that supports Session Request Protocol to have a VBUS input impedance less than 100kΩ and greater the 40kΩ to ground. The USB334x provides a 75kΩ resistance to ground, R . The R resistor tolerance is detailed in Table4.9. VB VB 5.7.2.6 VBUS Over Voltage Protection (OVP) The USB334x provides an integrated over voltage protection circuit to protect the VBUS pin from excessive voltages that may be present at the USB connector. The over voltage protection circuit works with an external resistor (R ) by drawing current across the resistor to reduce the voltage at the VBUS VBUS pin. When voltage at the VBUS pin exceeds 5.5V, the Over voltage Protection block will sink current to ground until VBUS is below 5.5V. The current drops the excess voltage across R and protects the VBUS USB334x VBUS pin. The required R value is dependent on the operating mode of the USB334x VBUS as shown in Table5.6. Table5.6 Required R Resistor Value VBUS OPERATING MODE R VBUS Device only 20kΩ ±5% OTG Host Capable of less than 100mA 1kΩ ±5% of current on VBUS Host or OTG Host capable of >100mA 20kΩ ±5% UseExternalVbusIndicator = 1 The Over voltage Protection circuit is designed to protect the USB334x from continuous voltages up to 30V on the R resistor. VBUS SMSC USB334x 43 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet The R resistor must be sized to handle the power dissipated across the resistor. The resistor VBUS power can be found using the equation below: (Vprotect–5.0)2 P = -------------------------------------------- RVBUS R VBUS Where:  Vprotect is the VBUS protection required.  RVBUS is the resistor value, 1kΩ or 20kΩ.  PRVBUS is the required power rating of RVBUS. For example, protecting a peripheral or device only application to 15V would require a 20kΩ R VBUS resistor with a power rating of 0.05W. To protect an OTG product to 15V would require a 1kΩ R VBUS resistor with a power rating of 0.1W. 5.7.3 Driving External VBUS The USB334x monitors VBUS as described in VBUS Monitoring and VBUS Pulsing. The USB334x does not provide an external output for the DrvVbusExternal ULPI register. For OTG and Host applications, the external VBUS supply or power switch must be controlled by the Link. 5.8 USB UART Support The USB334x provides support for the USB UART interface as detailed in the ULPI specification and the former CEA-936A specification. The USB334x can be placed in UART Mode using the method described in Section6.7, and the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register. While in UART mode, the Linestate signals cannot be monitored on the DATA[0] and DATA[1] pins. 5.9 USB Charger Detection Support The following blocks allow the USB334x to detect when a Battery Charger, Charging Host Port, or a USB Host is attached to the USB connector. The USB334x can also be configured to appear as a Charging Host Port, all according to the USB-IF Battery Charging 1.2 specification. The charger detection circuitry should be disabled during USB operation. Revision 1.2 (02-08-13) 44 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet ~~ VDD33 ChargerPullupEnDP ChargerPullupEnDM en ContactDetectEn D D C C R R I DP_SRC DP To USB Con. VDAT_SRC VDatSrcEn HostChrgEn DM VdatDet To USB Con. VDAT_REF en en IDatSinkEn D D P P R R I DAT_SINK DpPulldown DmPulldown SMSC PHY ~~ Figure5.7 USB Charger Detection Block Diagram Note: The italic names in the Figure5.7 correspond to bits in the ULPI register set. The charger detection circuitry runs from the VDD33 supply and requires that the VDD33 supply to be present to run the charger detection circuitry. The VDD33 supply is present anytime the RESETB pin is pulled high and VBAT is present. The charger detection circuits are fully functional while in Low Power Mode (Suspendm = 0). The status of the VdatDet can be relayed back to the Link through the ULPI interrupts in both Synchronous mode and Low Power Mode. 5.9.1 Active Analog Charger Detection (USB-IF Battery Charging 1.2) The USB334x includes the active analog charger detection specified in the USB-IF Battery Charging Specification. The additional analog circuitry will allow the USB334x to: 1. Detect a Dedicated Charging Port (DCP) with the DP and DM pins shorted together. 2. Detect a Standard Downstream Port (SDP) which has no battery charging circuitry. 3. Detect a Charging Downstream Port (CDP) which activly supplies voltage to the DM pin when connected to a USB-IF BC 1.2 compatible device. 4. Behave as a Charging Downstream Port by enabling the voltage source on the DM pin. SMSC USB334x 45 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet The charger detection circuitry is shown in Figure5.7. The VdatDet output is qualified with the Linestate[1:0] value. If the Linestate is not equal to 00 the VdatDet signal will not assert. The proper detection process flows through different modes of detection and uses the linestate and VdatDet signals values to determine the connection. Table5.7 describes the bit values that need to be set to enter each mode. Table5.7 USB Charger Setting vs. Modes N N N ETE EN WN WN E E D G O O C K T R D D R N C H L L TS SI TA TC UL UL A T N S P P CHARGER DETECTION MODES VD DA CO HO DP DM I Device Connect Detect 0 0 1 0 0 1 (The Connect Detect setting in Table5.1 must be followed) Device Charger Detection 1 1 0 0 0 0 Device Enhanced Charger Detection 1 1 0 1 0 0 Device USB Operation 0 0 0 0 0 0 Charging Host Port, no charging device attached and SE0 0 1 0 1 1 1 (VdatDet = 0) Charging Host Port, charging device attached (VdatDet = 1) 1 1 0 1 1 1 Charging Host Port USB Operation 0 0 0 1 1 1 5.9.1.1 Example Charger Detection Flow - Dedicated Charging Port The USB-IF Battery Charging 1.2 specification describes in detail the flow for each charger type, but below is an example of the flow used to detect a Dedicated Charger (DCP). 1. Device detects Vbus voltage is present from RXCMD, (SESS_VLD is 1) 2. Device enters the Device Connect Detect mode. If the linestate still equals 10 after a specified timeout, the charger is an unknown charger and there will be no attempted USB enumeration. If the linestate equals 00 or 11, the device will go to the next mode: 3. Device enters Device Charger Detection mode. If the VdatDet bit is 0 then the host is a Standard Downstream Port (SDP) and the device will draw the standard 500mA of current and enter the Device USB Operation mode. If the VdatDet bit is 1 then the host is a charger that can supply at least 1.5A of current, the device will go to the next mode. 4. Device enters Device Enhanced Charger Detection mode. If the VdatDet bit is 0 then the device is connected to a Charging Downstream Port (CDP) and the device will enter the Device USB Operation mode. If the VdatDet bit is 1 then the device is connected to a Dedicated Charding Port (DCP) and the device will not try to enumerate. 5. The charger detection is complete. Revision 1.2 (02-08-13) 46 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 5.9.2 Resistive Charger Detection Note: The Resistive Charger Detection has been superseded by the Active Analog Charger Detection (USB-IF Battery Charging 1.2) detailed above. It is recommended that new designs use the Active Analog Charger Detection (USB-IF Battery Charging 1.2). To support the detection and identification of different types of USB chargers the USB334x provides integrated pull-up resistors, R , on both DP and DM. These pull-up resistors along with the single CD ended receivers can be used to determine the type of USB charger attached. Reference information on implementing charger detection is provided in Section8.2. Table5.8 USB Weak Pull-up Enable RESETB DP PULLUP ENABLE DM PULLUP ENABLE 0 0 0 1 ChargerPullupEnableDP ChargerPullupEnableDM Note: ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power Management register. 5.10 USB Audio Support (USB3341 and USB3346) Note: The USB334x supports “USB Digital Audio” through the USB protocol in ULPI and USB Serial modes described in Section6. The USB334x provides two low resistance analog switches that allow analog audio to be multiplexed over the DP and DM terminals of the USB connector. The audio switches are shown in . The electrical characteristics of the USB Audio Switches are provided in Table4.11. During normal USB operation the switches are off. When USB Audio is desired the switches can be turned “on” by enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as described in Section6.7.2. These bits are disabled by default. The RESETB pin must be high when using the analog switches so that the VDD33 supply is present. If the VDD33 supply is applied externally and RESETB is held low the switches will be off. In addition to USB Audio support the switches could also be used to multiplex a second Full Speed USB transceiver to the USB connector. The signal quality will be degraded slightly due to the “on” resistance of the switches. The USB334x single-ended receivers described in Section5.2.1 are enabled while in synchronous mode and are disabled when Carkit Mode is entered. The USB334x does not provide the DC bias for the audio signals. The SPK_R and SPK_L pins should be biased to 1.65V when audio signals are routed through the USB334x. This DC bias is necessary to prevent the audio signal from swinging below ground and being clipped by ESD Diodes. When the system is not using the USB Audio switches, the SPK_R and SPK_L switches should be disabled. SMSC USB334x 47 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 6 ULPI Operation 6.1 ULPI Introduction The USB334x uses the industry standard ULPI digital interface for communication between the transceiver and Link (device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals. The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1”. The following sections describe the operating modes of the USB334x digital interface. Figure6.1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB334x does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies. USB Transmit and Receive Logic Tx Data HS Tx Data Data[7:0] High Speed TX To TX Full Speed TX FS/LS Tx Data Analog Low Speed TX DIR ULPI Protocol NOTE: NXT The ULPI interface Block is a wrapperless STP Rx Data design. High Speed Data HS RX Data Recovery To RX Full / Low Speed FS/LS Data Analog Data Recovery ol ntr To To USB o er C OTG Audio eiv Analog Analog er Access Transc RMida cShtiantee ULPI RegistULPI InteruptXcvrSelect[1:0]TermSelectOpMode[1:0]ResetDpPulldownDmPulldownSwapDP/DMRegOutput[1:0]TxdEnRxdEn SuspendM6pinSerial Mode3pinSerial ModeClockSuspendMAutoResumeCarkitMode Linestates[1:0]HostDisconnect VbusValidSessionValidSessionEndIdGndIdFloat RidCon...Done RidValue[2:0]RidCon...Start Interface Protect DisableUseExternal Vbus IndicatorIndicator ComplementIndicator Pass ThruDischrgVbusChrgVbusIdGndDrvIdPullUpSpkLeftEnSpkRightEn/MicEnChargerPullupEnDPChargerPullupEnDM Interrupt Control RESETB ULPI Register Array POR Figure6.1 ULPI Digital Block Diagram Revision 1.2 (02-08-13) 48 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet The advantage of a “wrapper-less” architecture is that the USB334x has a lower USB latency than a design which must first register signals into the PHY’s wrapper before the transfer to the transceiver core. A low latency PHY allows a wrapper around a UTMI Link to be used and still make the required USB turn-around timing required by the USB 2.0 specification. RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 Hi-Speed clocks. USB334x uses a low latency Hi-Speed receiver path to lower the RxEndDelay to 43 Hi-Speed clocks. This low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This is the result of the “wrapper less” architecture of the USB334x. This low RxEndDelay should allow legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface. In Figure6.1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The USB334x is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array. 6.1.1 ULPI Interface Signals The UTMI+ Low Pin Interface (ULPI) uses a 12-pin interface to connect a USB Transceiver to an external Link. The reduction of external pins, relative to UTMI+, is accomplished implementing the relatively static configuration pins (i.e. xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown DmPulldown) as an internal register array. An 8-bit bi-directional data bus clocked at 60MHz allows the Link to access this internal register array and transfer USB packets to and from the PHY. The remaining 3 pins function to control the data flow and arbitrate the data bus. Direction of the 8-bit data bus is controlled by the DIR output from the PHY. Another output, NXT, is used to control data flow into and out of the device. Finally, STP, which is in input to the PHY, terminates transfers and is used to start up and resume from Low Power Mode. The ULPI Interface signals are described below in Table6.1. Table6.1 ULPI Interface Signals SIGNAL DIRECTION DESCRIPTION CLK I/O 60MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of this clock. This clock can be either driven by the PHY or the Link as described in Section5.5.1 DATA[7:0] I/O 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of the ULPI clock. DIR OUT Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The PHY will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start-up. STP IN The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. NXT OUT The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. USB334x implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on the rising edge of the 60MHz ULPI Clock while operating in Synchronous Mode. The direction of the SMSC USB334x 49 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet data bus is determined by the state of DIR. When DIR is high, the PHY is driving DATA[7:0]. When DIR is low, the Link is driving DATA[7:0]. Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor PHY drive the data bus for one clock cycle. During the “turn-around“cycle, the state of DATA[7:0] is unknown and the PHY will not read the data bus. Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USB transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the data bus by the Link. The ULPI interface supports the two basic modes of operation: Synchronous Mode and Asynchronous Mode. Asynchronous Mode includes Low Power Mode, the Serial Modes, and Carkit Mode. In Synchronous Mode, all signals change synchronously with the 60MHz ULPI clock. In asynchronous modes the clock is off and the ULPI bus is redefined to bring out the signals required for that particular mode of operations. The description of synchronous Mode is described in the following sections while the descriptions of the asynchronous modes are described in Section6.5, Section6.6, and Section6.7. 6.1.2 ULPI Interface Timing in Synchronous Mode The control and data timing relationships are given in Figure6.2 and Table4.4. All timing is relative to the rising clock edge of the 60MHz ULPI Clock. 60MHz ULPI - CLK T T SC HC Control In - STP T T SD HD Data In - DATA[7:0] T T DC DC Control Out - DIR, NXT T DD Data Out - DATA[7:0] Figure6.2 ULPI Single Data Rate Timing Diagram in Synchronous Mode 6.2 ULPI Register Access The following section details the steps required to access registers through the ULPI interface. At any time DIR is low the Link may access the ULPI registers set using the Transmit Command byte. The ULPI registers retain their contents when the PHY is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode. Revision 1.2 (02-08-13) 50 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 6.2.1 Transmit Command Byte (TX CMD) A command from the Link begins a ULPI transfer from the Link to the USB334x. Before reading a ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TX CMD) byte. The TX CMD byte informs the USB334x of the type of data being sent. The TX CMD is followed by a data transfer to or from the USB334x. Table6.2 gives the TX command byte (TX CMD) encoding for the USB334x. The upper two bits of the TX CMD instruct the PHY as to what type of packet the Link is transmitting. Table6.2 ULPI TX CMD Byte Encoding CMD COMMAND NAME BITS[7:6] CMD BITS[5:0] COMMAND DESCRIPTION Idle 00b 000000b ULPI Idle Transmit 01b 000000b USB Transmit Packet with No Packet Identifier (NOPID) 00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P P P P where P is the 3 2 1 0 3 MSB. Register Write 10b XXXXXXb Immediate Register Write Command where: DATA[5:0] = 6-bit register address 101111b Extended Register Write Command where the 8-bit register address is available on the next cycle. Register Read 11b XXXXXXb Immediate Register Read Command where: DATA[5:0] = 6-bit register address 101111b Extended Register Read Command where the 8-bit register address is available on the next cycle. 6.2.2 ULPI Register Write A ULPI register write operation is given in Figure6.3. The TX command with a register write DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TX CMD byte. SMSC USB334x 51 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD Reg Data[n] Idle (reg write) DIR STP NXT ULPI Register Reg Data [n-1] Reg Data [n] Figure6.3 ULPI Register Write in Synchronous Mode To write a register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the register data. At T4, the PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into the register and the Link will pull STP low. NXT is used to throttle when the Link drives the register data on the bus. DIR is low throughout this transaction since the PHY is receiving data from the Link. STP is used to end the transaction and data is registered after the de-assertion of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus. If the databus is not driven to idle the USB334x may decode the non- zero bus value as an RX Command. A ULPI extended register write operation is shown in Figure6.4. To write an extended register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT high. On the next clock T3 the Link will drive the extended address. On the next rising clock edge, T4, the Link will write the register data. At T5, the PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. At T5, the PHY will latch the data into the register. Finally, at T6, the Link will drive STP low. Revision 1.2 (02-08-13) 52 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] Idle TXD CMD Extended Reg Data[n] Idle (extended reg write) address DIR STP NXT ULPI Register Reg Data [n-1] Reg Data [n] Figure6.4 ULPI Extended Register Write in Synchronous Mode 6.2.3 ULPI Register Read A ULPI register read operation is given in Figure6.5. The Link drives a TX CMD byte with DATA[7:6] = 11h for a register read. DATA[5:0] of the ULPI TX command bye contain the register address. T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD Turn around Reg Data Turn around Idle reg read DIR STP NXT Figure6.5 ULPI Register Read in Synchronous Mode At T0, the Link will place the TX CMD on the data bus. At T2, the PHY will bring NXT high, signaling the Link it is ready to accept the data transfer. At T3, the PHY reads the TX CMD, determines it is a SMSC USB334x 53 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet register read, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T4, the bus ownership has transferred back to the PHY and the PHY drives the requested register onto the data bus. At T5, the Link will read the data bus and the PHY will drop DIR low returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. A ULPI extended register read operation is shown in Figure6.6.To read an extended register, the Link writes the TX CMD with the address set to 2Fh. At T2, the PHY will assert NXT, signaling the Link it is ready to accept the extended address. At T3, the Link places the extended register address on the bus. At T4, the PHY reads the extended address, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T5, the bus ownership has transferred back to the PHY and the PHY drives the requested register onto the data bus. At T6, the Link will read the data bus and the PHY will de- assert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] Idle TXD CMD Extended Turn around Reg Data Turn around Idle extended reg read address DIR STP NXT Figure6.6 ULPI Extended Register Read in Synchronous Mode 6.3 USB334x Receiver The following section describes how the USB334x uses the ULPI interface to receive USB signaling and transfer status information to the Link. This information is communicated to the Link using RX Commands to relay bus status and received USB packets. 6.3.1 ULPI Receive Command (RX CMD) The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0], rxactive, rxvalid, rxerror, and VbusValid. When implementing the OTG functions, the VBUS and ID pin states must also be transferred to the Link. ULPI defines a Receive Command Byte (RXCMD) that contains this information. An RXCMD can be sent a any time the bus is idle. The RXCMD is initiated when the USB334x asserts DIR to take control of the bus. The timing of RXCMD is shown in the figure below. The USB334x can send single or back to back RXCMD’s as required. The Encoding of the RXCMD byte is given in the Table6.3. Revision 1.2 (02-08-13) 54 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DATA[7:0] Idle Turn around RXCMD Turn around Idle Turn around RXCMD RXCMD Turn around Idle DIR STP NXT Figure6.7 ULPI RXCMD Timing Transfer of the RXCMD byte occurs in Synchronous Mode when the PHY has control of the bus. The ULPI Protocol Block shown in Figure6.1 determines when to send an RXCMD. A RXCMD will occur:  When a linestate change occurs.  When VBUS or ID comparators change state.  During a USB receive when NXT is low.  After the USB334x deasserts DIR and STP is low during start-up  After the USB334x exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the Link has de-asserted STP, and DIR is low. When a USB Receive is occurring, RXCMD’s are sent whenever NXT = 0 and DIR = 1. During a USB Transmit, the RXCMD’s are returned to the Link after STP is asserted. If an RXCMD event occurs during a Hi-Speed USB transmit, the RXCMD is blocked until STP de- asserts at the end of the transmit. The RXCMD contains the status that is current at the time the RXCMD is sent. SMSC USB334x 55 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table6.3 ULPI RX CMD Encoding DATA[7:0] NAME DESCRIPTION AND VALUE [1:0] Linestate UTMI Linestate Signals. See Section6.3.1.1 [3:2] Encoded ENCODED VBUS VOLTAGE STATES VBUS State VALUE VBUS VOLTAGE SESSEND SESSVLD VBUSVLD 2 00 V < V 1 0 0 VBUS SESS_END 01 V < V < 0 0 0 SESS_END VBUS V SESS_VLD 10 V < V < X 1 0 SESS_VLD VBUS V VBUS_VLD 11 V < V X X 1 VBUS_VLD VBUS [5:4] Rx Event ENCODED UTMI EVENT SIGNALS Encoding VALUE RXACTIVE RXERROR HOSTDISCONNECT 00 0 0 0 01 1 0 0 11 1 1 0 10 X X 1 [6] State of Set to the logic state of the ID pin. A logic low indicates an A device. A logic high ID pin indicates a B device. [7] alt_int Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit Interrupt Latch register to determine the source of the interrupt. Section6.8 describes how an interrupt can be generated when the RidConversionDone bit is set. Notes: 1. An ‘X’ is a do not care and can be either a logic 0 or 1. 2. The value of VbusValid is defined in Table5.5. 6.3.1.1 Definition of Linestate The Linestate information is used to relay information back to the Link on the current status of the USB data lines, DP and DM. The definition of Linestate changes as the USB334x transitions between LS/FS mode, HS mode, and HS Chirp. 6.3.1.1.1 LS/FS LINESTATE DEFINITIONS In LS and FS operating modes the Linestate is defined by the outputs of the LS/FS Single Ended Receivers (SE RX). The logic thresholds for single ended receivers, V and V are shown in ILSE ILSE Table4.6. Revision 1.2 (02-08-13) 56 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table6.4 USB Linestate Decoding in FS and LS Mode LINESTATE[1:0] DP SE RX DM SE RX STATE 00 SE0 0 0 USB Reset 01 J (FS idle) 1 0 J State 10 K (LS Idle) 0 1 K State 11 SE1 1 1 SE1 Low Speed uses the same Linestate decoding threshold as Full Speed. Low Speed re-defines the Idle state as an inversion of the Full Speed idle to account for the inversion which occurs in the hub repeater path. Linestates are decoded exactly as in Table6.4 with the idle as a K state. 6.3.1.1.2 HS LINESTATE DEFINITION In HS mode the data transmission is too fast for Linestate to be transmitted with each transition in the data packet. In HS operation the Linestate is redefined to indicate activity on the USB interface. The Linestate will signal the assertion and de-assertion of squelch in HS mode. Table6.5 USB Linestate Decoding in HS Mode LINESTATE[1:0] DP SE RX DM SE RX STATE 00 SE0 0 0 HS Squelch asserted 01 J 1 0 HS Squelch de-asserted 10 K 0 1 Invalid State 11 SE1 1 1 Invalid State 6.3.1.1.3 HS CHIRP LINESTATE DEFINITION There is also a third use of Linestate in HS Chirp where when the Host and Peripheral negotiate the from FS mode to HS mode. While the transitions from K to J or SE0 are communicated to the Link through the Linestate information. Table6.6 USB Linestate Decoding in HS Chirp Mode LINESTATE[1:0] DP SE RX DM SE RX STATE 00 SE0 0 0 HS Squelch asserted 01 J 1 0 HS Squelch de-asserted & HS differential Receiver = 1 10 K 0 1 HS Squelch de-asserted & HS differential Receiver = 0 11 SE1 1 1 Invalid State SMSC USB334x 57 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 6.3.2 USB Receiver The USB334x ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority and will immediately follow register reads and RXCMD transfers. Figure6.8 shows a basic USB packet received by the USB334x over the ULPI interface. CLK DATA[7:0] Idle Turn Rxd PID D1 Rxd D2 Turn around Cmd Cmd around DIR STP NXT Figure6.8 ULPI Receive in Synchronous Mode In Figure6.8 the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link. After the last byte of the USB receive packet is transferred to the PHY, the linestate will return to idle. The ULPI Full Speed receiver operates according to the UTMI / ULPI specification. In the Full Speed case, the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is low with DIR high, the RXCMD is driven on the data bus. In Full Speed, the USB334x will not issue a Rxactive de-assertion in the RXCMD until the DP/DM linestate transitions to idle. This prevents the Link from violating the two Full Speed bit times minimum turn around time. 6.3.2.1 Disconnect Detection A Hi-Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP transmitted during a SOF packet. The USB334x only looks for a Hi-Speed disconnect during the long EOP where the period is long enough for the disconnect reflection to return to the host PHY. When a Hi-Speed disconnect occurs, the USB334x will return a RXCMD and set the host disconnect bit in the USB Interrupt Status register. When in FS or LS modes, the Link is expected to handle all disconnect detection. 6.3.2.2 Link Power Management (LPM) Token Receive The USB334x is fully capable of receiving the Extended PID in the LPM token. When the LPM 0000b PID is received, this information is passed to the Link as a normal receive packet. If the Link chooses to enter LPM suspend, the procedure detailed in 6.5.3 can be followed. Revision 1.2 (02-08-13) 58 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 6.4 USB334x Transmitter The USB334x ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure6.1 shows the Hi-Speed, Full Speed, and Low Speed transmitter block controlled by ULPI Protocol Block. Encoding of the USB packet follows the bit-stuffing and NRZI outlined in the USB 2.0 specification. Many of these functions are reused between the HS and FS/LS transmitters. When using the USB334x, Table5.1 should always be used as a guideline on how to configure for various modes of operation. The transmitter decodes the inputs of XcvrSelect[1:0], TermSelect, OpMode[1:0], DpPulldown, and DmPulldown to determine what operation is expected. Users must strictly adhere to the modes of operation given in Table5.1. Several important functions for a device and host are designed into the transmitter blocks. The USB334x transmitter will transmit a 32-bit long Hi-Speed sync before every Hi-Speed packet. In Full and Low Speed modes a 8-bit sync is transmitted. When the device or host needs to chirp for Hi-Speed port negotiation, the OpMode = 10 setting will turn off the bit-stuffing and NRZI encoding in the transmitter. At the end of a chirp, the USB334x OpMode register bits should be changed only after the RXCMD linestate encoding indicates that the transmitter has completed transmitting. Should the opmode be switched to normal bit-stuffing and NRZI encoding before the transmit pipeline is empty, the remaining data in the pipeline may be transmitted in an bit-stuff encoding format. Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp. 6.4.1 USB334x Host Features The USB334x can also support USB Host operation and includes the following features that are required for Host operation. 6.4.1.1 Hi-Speed Long EOP When operating as a Hi-Speed host, the USB334x will automatically generate a 40 bit long End of Packet (EOP) after a SOF PID (A5h). The USB334x determines when to send the 40-bit long EOP by decoding the ULPI TX CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the DpPulldown and DmPulldown bits in the OTG Control register are asserted. The Hi-Speed 40-bit long EOP is used to detect a disconnect in mode. In device mode, the USB334x will not send a long EOP after a SOF PID. 6.4.1.2 Low Speed Keep-Alive Low Speed keep alive is supported by the USB334x. When in Low Speed mode, the USB334x will send out two Low Speed bit times of SE0 when a SOF PID is received. 6.4.1.3 UTMI+ Level 3 Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect is set to (11b) in host mode, (DpPulldown and DmPulldown both asserted) the USB334x will pre-pend a Full Speed pre-amble before the Low Speed packet. Full Speed rise and fall times are used in this mode. The pre-amble consists of the following: Full Speed sync, the encoded pre-PID (C3h) and then Full Speed idle (DP=1 and DM = 0). A Low Speed packet follows with a sync, data and a LS EOP. The USB334x will only support UTMI+ Level 3 as a host. The USB334x does not support UTMI+ Level 3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB334x will not decode a pre-amble packet intended for a LS device when the USB334x is configured as the upstream port of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b. SMSC USB334x 59 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 6.4.1.4 Host Resume K Resume K generation is supported by the USB334x. At the end of a USB Suspend the PHY will drive a K back to the downstream device. When the USB334x exits from Low Power Mode, when operating as a host, it will automatically transmit a Resume K on DP/DM. The transmitters will end the K with SE0 for two Low Speed bit times. If the USB334x was operating in Hi-Speed mode before the suspend, the host must change to Hi-Speed mode before the SE0 ends. SE0 is two Low Speed bit times which is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of the USB Specification. In device mode, the resume K will not append an SE0, but release the bus to the correct idle state, depending upon the operational mode as shown in Table5.1. The ULPI specification includes a detailed discussion of the resume sequence and the order of operations required. To support Host start-up of less than 1mS the USB334x implements the ULPI AutoResume bit in the Interface Control register. The default AutoResume state is 0 and this bit should be enabled for Host applications. 6.4.1.5 No SYNC and EOP Generation (OpMode = 11) UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This is an option to the ULPI specification and not implemented in the USB334x. 6.4.2 Typical USB Transmit with ULPI Figure6.9 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a TX CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID is followed by transmit data. CLK DATA[7:0] Idle T(XUDS BC MtxD) D0 D1 D2 D3 IDLE ATrouurnn d CRMXDD ATrouurnn d DIR NXT STP DP/DM SE0 !SQUELCH SE0 Figure6.9 ULPI Transmit in Synchronous Mode During transmit the PHY will use NXT to control the rate of data flow into the PHY. If the USB334x pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP while NXT is asserted. Note: The Link cannot assert STP with NXT de-asserted since the USB334x is expecting to fetch another byte from the Link. After the USB334x completes transmitting, the DP and DM lines return to idle and a RXCMD is returned to the Link so the inter-packet timers may be updated by linestate. While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for approximately two bit times, followed by J for one bit time. The transceiver drives a J state for one bit time following the SE0 to complete the EOP. The Link must wait for one bit time following line state Revision 1.2 (02-08-13) 60 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet indication of the SE0 to J transition to allow the transceiver to complete the one bit time J state. All bit times are relative to the speed of transmission. In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate a RXCMD since the bit times are relatively slow. 6.4.2.1 Link Power Management Token Transmit A Host Link can send a LPM command using the USB334x. When sending the LPM token the normal transmit method is not used. Sending a LPM token requires the USB334x to send a 0000b or ‘F0’ PID. When the ULPI specification was defined the ‘F0’ PID was not defined. The ULPI specification used the “Reserved” ‘F0’ PID to signal chirp and resume signaling while using OpMode 10b. While in OpMode 00b the USB334x is able to generate the ‘F0’ PID as shown below. CLK DATA[7:0] Idle (40hT XTDX CNMOPDI D ) (FP0IDh) D0 D1 ATrouurnn d IDLE ATrouurnn d CRMXDD IDLE DIR NXT STP DP/DM SE0 !SQUELCH SE0 Figure6.10 LPM Token Transmit To send the ‘F0’ PID, the link will be required to use the TX CMD with NOPID to initiate the transmit and then follow up the TX CMD with the ‘F0’ PID. The data bytes follow as in a normal transmit, in OpMode 00b. The key difference is in that the link will have to send the PID the same as it would send a data packet. The USB334x is able to recognize the LPM transmit and correctly send the PID information. 6.5 Low Power Mode Low Power Mode is a power down state to save current when the USB session is suspended. The Link controls when the PHY is placed into or out of Low Power Mode. In Low Power Mode all of the circuits are powered down except the interface pins, Full Speed receiver, VBUS comparators, and IdGnd comparator. The VBUS and ID comparators can optionally be powered down to save current as shown in Section6.5.5. Before entering Low Power Mode, the USB334x must be configured to set the desired state of the USB transceiver. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration as shown in Table5.1. The DP and DM pins are configured to a high impedance state by configuring OpMode[1:0] = 01 as shown in the programming example in Table6.8. Pull-down resistors with a value of approximately 2MΩ are present on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to float. SMSC USB334x 61 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 6.5.1 Entering Low Power/Suspend Mode To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control register. After this write is complete, the PHY will assert DIR high and after a minimum of five rising edges of CLKOUT, drive the clock low. After the clock is stopped, the PHY will enter a low power state to conserve current. Placing the PHY in Suspend Mode is not related to USB Suspend. To clarify this point, USB Suspend is initiated when a USB host stops data transmissions and enters Full-Speed mode with 15KΩ pull-down resistors on DP and DM. The suspended device goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one of them drives DM high (this is called a resume). T0 T1 T2 T3 T4 T5 T6 T10 ... CLK DATA[7:0] Idle TXD CMD Reg Data[n] Idle Turn Low Power Mode (reg write) Around DIR STP NXT SUSPENDM (ULPI Register Bit) Figure6.11 Entering Low Power Mode from Synchronous Mode While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table6.7. Linestate[1:0] is the combinational output of the Single-Ended Receivers. The “int” or interrupt signal indicates an unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the Link is notified and can determine if it should wake-up the PHY. Table6.7 Interface Signal Mapping During Low Power Mode SIGNAL MAPS TO DIRECTION DESCRIPTION linestate[0] DATA[0] OUT Combinatorial LineState[0] driven directly by the Full-Speed single ended receiver. Note6.1 linestate[1] DATA[1] OUT Combinatorial LineState[1] driven directly by the Full-Speed single ended receiver. Note6.1 reserved DATA[2] OUT Driven Low int DATA[3] OUT Active high interrupt indication. Must be asserted whenever any unmasked interrupt occurs. reserved DATA[7:4] OUT Driven Low Revision 1.2 (02-08-13) 62 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Note6.1 LineState: These signals reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1). An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld, SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3] will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts masked to lower the suspend current as described in Section6.5.5. While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks are stopped during Low Power Mode. 6.5.2 Exiting Low Power Mode To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB334x will begin its start-up procedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode. The PHY will automatically set the SuspendM bit to a 1 in the Function Control register. T0 T1 T2 T3 T4 T5 ... CLK DATA[7:0] LOW TURN DATA BUS IGNORED (SLOW LINK) IDLE POWER MODE AROUND IDLE (FAST LINK) Slow Link Drives Bus Fast Link Drives Bus Idle and STP low DIR Idle and STP low STP Note: Not to Scale T START Figure6.12 Exiting Low Power Mode The value for T is given in Table4.3. START Should the Link de-assert STP before DIR is de-asserted, the USB334x will detect this as a false resume request and return to Low Power Mode. This is detailed in Section 3.9.4 of the UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1. 6.5.3 Link Power Management (LPM) When the USB334x is operating with a Link capable of Link Power Management, the Link will place the USB334x in and out of suspend rapidly to conserve power. The USB334x provides a fast suspend recovery that allows the USB334x to meet the suspend recovery time detailed in the Link Power Management ECN to the USB 2.0 specification. SMSC USB334x 63 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet When the Link places the USB334x into suspend during Link Power Management, the LPM Enable bit of the HS Compensation Register must be set to 1. This allows the USB334x to start-up in the time specified in Table4.3. 6.5.4 Interface Protection ULPI protocol assumes that both the Link and PHY will keep the ULPI data bus driven by either the Link when DIR is low or the PHY when DIR is high. The only exception is when DIR has changed state and a turn around cycle occurs for 1 clock period. In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus to a known state while DIR is low. Two examples where this can happen is because of a slow Link start-up or a hardware reset. 6.5.4.1 Start up Protection Upon start-up, when the PHY de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STP before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up. If the Link doesn’t assert STP before it can receive commands, the PHY may interpret the data bus state as a TX CMD and transmit invalid data onto the USB bus, or make invalid register writes. When the USB334x sends a RXCMD the Link is required to drive the data bus back to idle at the end of the turn around cycle. If the Link does not drive the databus to idle the USB334x may take the information on the data bus as a TXCMD and transmit data on DP and DM until the Link asserts stop. If the ID pin is floated the last RXCMD from the USB334x will remain on the bus after DIR is de- asserted and the USB334x will take this in as a TXCMD. A Link should be designed to have the default POR state of the STP output high and the data bus tri- stated. The USB334x has weak pull-downs on the data bus to prevent these inputs from floating when not driven. These resistors are only used to prevent the ULPI interface from floating during events when the link ULPI pins may be tri-stated. The strength of the pull down resistors can be found in Table4.5. The pull downs are not strong enough to pull the data bus low after a ULPI RXCMD, the Link must drive the data bus to idle after DIR is de-asserted. In some cases, a Link may be software configured and not have control of its STP pin until after the PHY has started. In this case, the USB334x has in internal pull-up on the STP input pad which will pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register. The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP high. After the Link completes its start-up, STP can be synchronously driven low. A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtectDisable bit to 1. A motivation for this is to reduce the suspend current. In Low Power Mode, STP is held low, which would draw current through the pull-up resistor on STP. 6.5.4.2 Warm Reset Designers should also consider the case of a warm restart of a Link with a PHY in Low Power Mode. After the PHY enters Low Power Mode, DIR is asserted and the clock is stopped. The USB334x looks for STP to be asserted to re-start the clock and then resume normal synchronous operation. Should the USB334x be suspended in Low Power Mode, and the Link receives a hardware reset, the PHY must be able to recover from Low Power Mode and start its clock. If the Link asserts STP on reset, the PHY will exit Low Power Mode and start its clock. If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link is reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the PHY to restart its clock. Revision 1.2 (02-08-13) 64 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 6.5.5 Minimizing Current in Low Power Mode In order to minimize the suspend current in Low Power Mode, the VBUS and ID comparators can be disabled to reduce suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are not needed and can be disabled by clearing the associated bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. By disabling the interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and IdFloatFall bits in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG functionality is required. In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the Interface Protect Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register, the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled. 6.6 Full Speed/Low Speed Serial Modes The USB334x includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the Interface control register. Serial Mode may be used to conserve power when attached to a device that is not capable of operating in Hi-Speed. The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes the Interface Control register bit for the specific serial mode. The USB334x will assert DIR and shut off the clock after at least five clock cycles. Then the data bus goes to the format of the serial mode selected. Before entering Serial Mode the Link must set the ULPI transceiver to the appropriate mode as defined in Table5.1. In ULPI Clock Output Mode, the PHY will shut off the 60MHz clock to conserve power. Should the Link need the 60MHz clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface Control Register should be set before entering a serial mode. If set, the 60 MHz clock will be present during serial modes. In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal the PHY to exit serial mode. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB334x and return it to Synchronous Mode. 6.6.0.1 3-Pin FS/LS Serial Mode Three pin serial mode utilizes the data bus pins for the serial functions shown in Table6.8. Table6.8 Pin Definitions in 3 pin Serial Mode CONNECTED SIGNAL TO DIRECTION DESCRIPTION tx_enable DATA[0] IN Active High transmit enable. data DATA[1] I/O TX differential data on DP/DM when tx_enable is high. RX differential data from DP/DM when tx_enable is low. SE0 DATA[2] I/O TX SE0 on DP/DM when tx_enable is high. RX SE0_b from DP/DM when tx_enable is low. SMSC USB334x 65 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table6.8 Pin Definitions in 3 pin Serial Mode (continued) CONNECTED SIGNAL TO DIRECTION DESCRIPTION interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. Reserved DATA[7:4] OUT Driven Low. 6.6.0.2 6-Pin FS/LS Serial Mode Six pin serial mode utilizes the data bus pins for the serial functions shown in Table6.9. Table6.9 Pin Definitions in 6 pin Serial Mode CONNECTED SIGNAL TO DIRECTION DESCRIPTION tx_enable DATA[0] IN Active High transmit enable. tx_data DATA[1] IN Tx differential data on DP/DM when tx_enable is high. tx_se0 DATA[2] IN Tx SE0 on DP/DM when tx_enable is high. interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. rx_dp DATA[4] OUT Single ended receive data on DP. rx_dm DATA[5] OUT Single ended receive data on DM. rx_rcv DATA[6] OUT Differential receive data from DP and DM. Reserved DATA[7] OUT Driven Low. 6.7 Carkit Mode The USB334x includes Carkit Mode to support a USB UART and USB Audio Mode. By entering Carkit Mode, the USB334x current drain is minimized. The internal PLL is disabled and the 60MHz ULPI CLKOUT will be stopped to conserve power by default. The Link may configure the 60MHz clock to continue by setting the ClockSuspendM bit of the Interface Control register before entering Carkit Mode. If set, the 60 MHz clock will continue during the Carkit Mode of operation. In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. In Carkit Mode, the Linestate signals are not available per the ULPI specification. The ULPI interface is redefined to the following when Carkit Mode is entered. Table6.10 Pin Definitions in Carkit Mode CONNECTED SIGNAL TO DIRECTION DESCRIPTION txd DATA[0] IN UART TXD signal that is routed to the DM pin if the TxdEn is set in the Carkit Control register. rxd DATA[1] OUT UART RXD signal that is routed to the DP pin if the RxdEn bit is set in the Carkit Control register. Revision 1.2 (02-08-13) 66 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table6.10 Pin Definitions in Carkit Mode (continued) CONNECTED SIGNAL TO DIRECTION DESCRIPTION reserved DATA[2] OUT Driven Low (CarkitDataMC = 0, default) IN Tri-state (CarkitDataMC = 1) int DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. reserved DATA[4:7] OUT Driven Low. Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section6.5.2. The Link must assert STP to signal the PHY to exit serial mode. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB334x and return it to Synchronous Mode. 6.7.1 Entering USB UART Mode The USB334x can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn and RxdEn bits must be written before the CarkitMode bit. Table6.11 ULPI Register Programming Example to Enter UART Mode ADDRESS VALUE R/W (HEX) (HEX) DESCRIPTION RESULT W 04 49 Configure Non-Driving mode OpMode=01 Select FS transmit edge rates XcvrSelect=01 W 39 00 Set regulator to 3.3V UART RegOutput=00 W 19 0C Enable UART connections RxdEn=1 TxdEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table6.10, and the USB334x will transmit data through the DATA[0] to DM of the USB connector and receive data on DP and pass the information the Link on DATA[1]. When entering UART mode, the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register and the R pull-up resistors CD will be applied internally to DP and DM. This will hold the UART in its default operating state. While in UART mode, the transmit edge rates can be set to either the Full Speed USB or Low Speed USB edge rates by using the XcvrSelect[1:0] bits in the Function Control register. 6.7.2 USB Audio Mode (USB3341 and USB3346) When the USB334x is powered in Synchronous Mode, the Audio switches can be enabled by asserting the SpkLeftEn, or SpkRightEn bits in the Carkit Control register. After the register write is complete, the USB334x will immediately enable or disable the audio switch. Then the Link can set the CarkitMode bit in the Interface Control register. The SpkLeftEn, or SpkRightEn bits must be written before the CarkitMode bit. SMSC USB334x 67 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table6.12 ULPI Register Programming Example to Enter Audio Mode ADDRESS VALUE R/W (HEX) (HEX) DESCRIPTION RESULT W 04 48 Configure Non-Driving mode OpMode=01 W 19 30 Enable Audio connections SpkrRightEn=1, SpkrLeftEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table6.10. 6.8 RID Converter Operation The RID converter is designed to read the value of the ID resistance to ground and report back its value through the ULPI interface. When a resistor to ground is applied to the ID pin the state of the IdGnd comparator will change from a 1 to a 0 as described in Section5.7.1. If the USB334x is in ULPI mode, an RXCMD will be generated with bit 6 low. If the USB334x is in Low Power Mode (or one of the other non-ULPI modes), the DATA[3] interrupt signal will go high. After the USB334x has detected the change of state on the ID pin, the RID converter can be used to determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart bit is set in the Vendor Rid Conversion register. The Link can use one of two methods to determine when the RID Conversion is complete. One method is polling the RidConversionStart bit as described in Section7.1.3.4. The preferred method is to set the RidIntEn bit in the Vendor Rid Conversion register. When RidIntEn is set, an RXCMD will be generated after the RID conversion is complete. As described in Table6.3, the alt_int bit of the RXCMD will be set. After the RID Conversion is complete, the Link can read RidValue from the Vendor Rid Conversion register. 6.8.1 Headset Audio Mode This mode is designed to allow a user to view the status of several signals while using an analog Audio headset with a USB connector. This mode is provided as an alternate mode to the CarKit Mode defined in Chapter 6.7. In the CarKit mode the Link is unable to view the source of the interrupt on ID. For the Link to view the interrupt on ID the PHY must be returned to synchronous mode so the interrupt can be read. This will force the audio switches to be deactivated during the PHY start-up which may glitch the audio signals. In addition the Link can not change the resistance on the ID pin without starting up the PHY to access the ULPI registers. The Headset Audio Mode is entered by writing to the Headset Audio Mode register, and allows the Link access to the state of the VBUS and ID pins during audio without having to break the audio connection. The Headset Audio mode also allows for the Link to change the resistance on the ID pin to change the audio device attached from mono to stereo. Revision 1.2 (02-08-13) 68 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table6.13 Pin Definitions in Headset Audio Mode CONNECTED SIGNAL TO DIRECTION DESCRIPTION SessVld DATA[0] OUT Output of SessVld comparator VbusVld DATA[1] OUT Output of VbusVld Comparator (interrupt must be enabled) IdGndDrv DATA[2] IN Drives ID pin to ground when asserted 0b: Not connected 1b: Connects ID to ground. DATA[3] OUT Driven low IdGround DATA[4] OUT Asserted when the ID pin is grounded. 0b: ID pin is grounded 1b: ID pin is floating IdFloat DATA[5] OUT Asserted when the ID pin is floating. IdPullup or Id_pullup330 must be enabled. IdFloatRise and IdFloatFall must be enabled. IdPullup330 DATA[6] IN When enabled a 330kΩ pullup is applied to the ID pin. This bit will also change the trip point of the IdGnd comparator to the value shown in Table4.9. 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor IdPullup DATA[7] IN Connects the 100kΩ pull-up resistor from the ID pin to VDD3.3 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor Exiting Headset Audio Mode is the same as exiting Low Power Mode as described in Section6.5.2. The RESETB pin can also be pulsed low to reset the USB334x and return to Synchronous Mode. SMSC USB334x 69 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 7 ULPI Register Map 7.1 ULPI Register Array The USB334x PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB334x ULPI register set is shown in Table7.1. All registers are 8 bits. This table also includes the default state of each register upon POR or de-assertion of RESETB, as described in Section5.6.2. The RESET bit in the Function Control Register does not reset the bits of the ULPI register array. The Link should not read or write to any registers not listed in this table. The USB334x supports extended register access. The immediate register set (00-3Fh) can be accessed through either a immediate address or an extended register address. Table7.1 ULPI Register Map ADDRESS (6BIT) DEFAULT REGISTER NAME STATE READ WRITE SET CLEAR Vendor ID Low 24h 00h - - - Vendor ID High 04h 01h - - - Product ID Low 09h 02h - - - Product ID High 00h 03h - - - Function Control 41h 04-06h 04h 05h 06h Interface Control 00h 07-09h 07h 08h 09h OTG Control 06h 0A-0Ch 0Ah 0Bh 0Ch USB Interrupt Enable Rising 1Fh 0D-0Fh 0Dh 0Eh 0Fh USB Interrupt Enable Falling 1Fh 10-12h 10h 11h 12h USB Interrupt Status (Note7.1) 00h 13h - - - USB Interrupt Latch 00h 14h - - - Debug 00h 15h - - - Scratch Register 00h 16-18h 16h 17h 18h Carkit Control 00h 19-1Bh 19h 1Ah 1Bh Reserved 00h 1Ch Carkit Interrupt Enable 00h 1D-1Fh 1Dh 1Eh 1Fh Carkit Interrupt Status 00h 20h - - - Carkit Interrupt Latch 00h 21h - - - Reserved 00h 22-30h HS Compensation Register 00h 31h 31h - - USB-IF Charger Detection 00h 32h 32h - - Headset Audio Mode 00 33 33 - - Revision 1.2 (02-08-13) 70 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Table7.1 ULPI Register Map (continued) ADDRESS (6BIT) DEFAULT REGISTER NAME STATE READ WRITE SET CLEAR Reserved 00h 34-35h Vendor Rid Conversion 00h 36-38h 36h 37h 38h USB IO & Power Management 04h 39-3Bh 39h 3Ah 3Bh Reserved 00h 3C-3Fh Note7.1 Dynamically updates to reflect current status of interrupt sources. 7.1.1 ULPI Register Set The following registers are used for the ULPI interface. 7.1.1.1 Vendor ID Low Address = 00h (read only) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION Vendor ID Low 7:0 rd 24h SMSC Vendor ID 7.1.1.2 Vendor ID High Address = 01h (read only) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION Vendor ID High 7:0 rd 04h SMSC Vendor ID 7.1.1.3 Product ID Low Address = 02h (read only) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION Product ID Low 7:0 rd 09h SMSC Product ID 7.1.1.4 Product ID High Address = 03h (read only) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION Product ID High 7:0 rd 00h SMSC Product ID SMSC USB334x 71 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 7.1.1.5 Function Control Address = 04-06h (read), 04h (write), 05h (set), 06h (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION XcvrSelect[1:0] 1:0 rd/w/s/c 01b Selects the required transceiver speed. 00b: Enables HS transceiver 01b: Enables FS transceiver 10b: Enables LS transceiver 11b: Enables FS transceiver for LS packets (FS preamble automatically pre-pended) TermSelect 2 rd/w/s/c 0b Controls the DP and DM termination depending on XcvrSelect, OpMode, DpPulldown, and DmPulldown. The DP and DM termination is detailed in Table5.1. OpMode 4:3 rd/w/s/c 00b Selects the required bit encoding style during transmit. 00b: Normal Operation 01b: Non-Driving 10b: Disable bit-stuff and NRZI encoding 11b: Reserved Reset 5 rd/w/s/c 0b Active high transceiver reset. This reset does not reset the ULPI interface or register set. Automatically clears after reset is complete. SuspendM 6 rd/w/s/c 1b Active low PHY suspend. When cleared the PHY will enter Low Power Mode as detailed in 6.5. Automatically set when exiting Low Power Mode. LPM Enable 7 rd/w/s/c 0b When enabled the PLL start-up time is shortened to allow fast start-up for LPM. The reduced PLL start-up time is achieved by bypassing the VCO process compensation which was done on initial start-up. 7.1.1.6 Interface Control Address = 07-09h (read), 07h (write), 08h (set), 09h (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION 6-pin FsLsSerialMode 0 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 6-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. 3-pin FsLsSerialMode 1 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 3-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. CarkitMode 2 rd/w/s/c 0b When asserted the ULPI interface is redefined to the Carkit interface. The PHY will automatically clear this bit when exiting Carkit Mode. Revision 1.2 (02-08-13) 72 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION ClockSuspendM 3 rd/w/s/c 0b Enables Link to turn on 60MHz CLKOUT in Serial Mode or Carkit Mode. 0b: Disable clock in serial or Carkit Mode. 1b: Enable clock in serial or Carkit Mode. AutoResume 4 rd/w/s/c 0b Only applicable in Host mode. Enables the PHY to automatically transmit resume signaling. This function is detailed in Section6.4.1.4. IndicatorComplement 5 rd/w/s/c 0b Inverts the EXTVBUS signal. This function is detailed in Section5.7.2. Note: The EXTVBUS signal is always high on the USB334x. IndicatorPassThru 6 rd/w/s/c 0b Disables and’ing the internal VBUS comparator with the EXTVBUS signal when asserted. This function is detailed in Section5.7.2. Note: The EXTVBUS signal is always high on the USB334x. InterfaceProtectDisable 7 rd/w/s/c 0b Used to disable the integrated STP pull-up resistor used for interface protection. This function is detailed in Section6.5.4. 7.1.1.7 OTG Control Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION IdPullup 0 rd/w/s/c 0b Connects a 100kΩ pull-up resistor from the ID pin to VDD33 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor DpPulldown 1 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DP. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected DmPulldown 2 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DM. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected DischrgVbus 3 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to ground to discharge VBUS. 0b: disconnect resistor from VBUS to ground 1b: connect resistor from VBUS to ground ChrgVbus 4 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to VDD33 to charge VBUS above the SessValid threshold. 0b: disconnect resistor from VBUS to VDD33 1b: connect resistor from VBUS to VDD33 DrvVbus 5 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbusExternal. 0b: Do not drive Vbus. 1b: Drive Vbus SMSC USB334x 73 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION DrvVbusExternal 6 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbus. 0b: Do not drive Vbus 1b: Drive Vbus UseExternalVbus 7 rd/w/s/c 0b Tells the PHY to use an external VBUS over-current Indicator or voltage indicator. This function is detailed in Section5.7.2. 0b: Use the internal VbusValid comparator 1b: Use the EXTVBUS input as for VbusValid signal. Note: The EXTVBUS signal is always high on the USB334x. 7.1.1.8 USB Interrupt Enable Rising Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION HostDisconnect Rise 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode. VbusValid Rise 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from low to high. SessValid Rise 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from low to high. SessEnd Rise 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from low to high. IdGnd Rise 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from low to high. Reserved 7:5 rd 0h Read only, 0. 7.1.1.9 USB Interrupt Enable Falling Address = 10-12h (read), 10h (write), 11h (set), 12h (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION HostDisconnect Fall 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode. VbusValid Fall 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from high to low. SessValid Fall 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from high to low. SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from high to low. Revision 1.2 (02-08-13) 74 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 rd 0h Read only, 0. 7.1.1.10 USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. FIELD NAME BIT ACCESS DEFAULT DESCRIPTION HostDisconnect 0 0b Current value of the UTMI+ HS Hostdisconnect output. Applicable only in host mode. VbusValid 1 0b Current value of the UTMI+ Vbusvalid output. If VbusValid Rise and VbusValid Fall are set this register will read 0. SessValid 2 0b Current value of the UTMI+ SessValid output. This rd register will always read the current status of the (read Session Valid comparator regardless of the only) SessValid Rise and SessValid Fall settings. SessEnd 3 0b Current value of the UTMI+ SessEnd output. If SessEnd Rise and SessEnd Fall are set this register will read 0. IdGnd 4 0b Current value of the UTMI+ IdGnd output. Reserved 7:5 0h Read only, 0. Note: The default value is only valid after POR. When the register is read it will match the current status of the comparators at the moment the register is read. 7.1.1.11 USB Interrupt Latch Address = 14h (read only with auto clear) SMSC USB334x 75 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION HostDisconnect Latch 0 0b Set to 1b by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode. VbusValid Latch 1 0b Set to 1b by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read. SessValid Latch 2 rd 0b Set to 1b by the PHY when an unmasked event (Note7.2) occurs on SessValid. Cleared when this register is read. SessEnd Latch 3 0b Set to 1b by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read. IdGnd Latch 4 0b Set to 1b by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read. Reserved 7:5 rd 0h Read only, 0. Note7.2 rd: Read Only with auto clear. 7.1.1.12 Debug Address = 15h (read only) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION Linestate[1:0] 1:0 rd 00b Contains the current value of Linestate[1:0]. Reserved 7:2 rd 000000b Read only, 0. 7.1.1.13 Scratch Register Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION Scratch 7:0 rd/w/s/c 00h Empty register byte for testing purposes. Software can read, write, set, and clear this register and the PHY functionality will not be affected. 7.1.2 Carkit Control Registers The following registers are used to set-up and enable the USB UART and USB Audio functions. 7.1.2.1 Carkit Control Address = 19-1Bh (read), 19h (write), 1Ah (set), 1Bh (clear) This register is used to program the USB334x into and out of the Carkit Mode. When entering the UART mode the Link must first set the desired TxdEn and the RxdEn bits and then transition to Carkit Revision 1.2 (02-08-13) 76 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Mode by setting the CarkitMode bit in the Interface Control Register. When RxdEn is not set then the DATA[1] pin is held to a logic high. FIELD NAME BIT ACCESS DEFAULT DESCRIPTION CarkitPwr 0 rd 0b Read only, 0. IdGndDrv 1 rd/w/s/c 0b Drives ID pin to ground TxdEn 2 rd/w/s/c 0b Connects UART TXD (DATA[0]) to DM RxdEn 3 rd/w/s/c 0b Connects UART RXD (DATA[1]) to DP SpkLeftEn 4 rd/w/s/c 0b Connects DM pin to SPK_L pin SpkRightEn 5 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. MicEn 6 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. CarkitDataMC 7 rd/w/s/c 0b When set the UPLI DATA[2] pin is changed from a driven 0 to tri-state, when carkit mode is entered. Note: If SpkRightEn or MicEn are asserted the DP pin will be connected to SPK_R. To disconnect the DP pin from the SPK_R pin both SpkrRightEn and MicEn must be set to de-asserted. If using USB UART mode, the UART data will appear at the SPK_L and SPK_R pins if the corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled. If using USB Audio the TxdEn and RxdEn bits should not be set when the SpkLeftEn, SpkRightEn, or MicEn switches are enabled. The USB single-ended receivers described in Section5.2.1 are disabled when either SpkLeftEn, SpkRightEn, or MicEn are set. 7.1.2.2 Carkit Interrupt Enable Address = 1D-1Fh (read), 1Dh (write), 1Eh (set), 1Fh (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION IdFloatRise 0 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from non-floating to floating. The IdPullup bit in the OTG Control register should be set. IdFloatFall 1 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from floating to non-floating. The IdPullup bit in the OTG Control register should be set. VdatDetIntEn 2 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the V DAT_DET Comparator changes state. CarDpRise 3 rd 0b Not Implemented. Reads as 0b. CarDpFall 4 rd 0b Not Implemented. Reads as 0b. SMSC USB334x 77 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION RidIntEn 5 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or’ed with the RidIntEn bit of the Vendor Rid Conversion register described in Section7.1.3.4. Reserved 6 rd/w/s/c 0b Read only, 0. Reserved 7 rd 0b Read only, 0. 7.1.2.3 Carkit Interrupt Status Address = 20h (read only) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION IdFloat 0 rd 0b Asserted when the ID pin is floating. IdPullup must be enabled. VdatDet 1 rd 0b V Comparator output DAT_DET 0b: No voltage is detected on DP 1b: Voltage detected on DP, IdatSinkEn must be set to 1. Note: VdatDet can also be read from the USB-IF Charger Detection register described in Section7.1.3.3. CarDp 2 rd 0b Not Implemented. Reads as 0b. RidValue 5:3 rd 000b Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 102K ohms 011: 200K ohms 100: Reserved 101: ID floating 111: Error Note: RidValue can also be read from the Vendor Rid Conversion register described in Section7.1.3.4. RidConversionDone 6 rd 0b Automatically asserted by the USB334x when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status register will not clear either RidConversionDone status bit. Note: RidConversionDone can also be read from the Vendor Rid Conversion register described in Section7.1.3.4. Reserved 7 rd 0b Read only, 0. Revision 1.2 (02-08-13) 78 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 7.1.2.4 Carkit Interrupt Latch Address = 21h (read only with auto-clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION IdFloat Latch 0 rd 0b Asserted if the state of the ID pin changes from non- (Note7.3) floating to floating while the IdFloatRise bit is enabled or if the state of the ID pin changes from floating to non-floating while the IdFloatFall bit is enabled. VdatDet Latch 1 rd 0b If VdatDetIntEn is set and the VdatDet bit changes state, this bit will be asserted. CarDp Latch 2 rd 0b Not Implemented. Reads as 0b. RidConversionLatch 3 rd 0b If RidIntEn is set and the state of the (Note7.3) RidConversionDone bit changes from a 0 to 1 this bit will be asserted. Reserved 7:4 rd 0000b Read only, 0. Note7.3 rd: Read Only with auto clear 7.1.3 Vendor Register Access The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write. 7.1.3.1 HS Compensation Register Address = 31h (read / write) The USB334x is designed to meet the USB specifications and requirements when the DP and DM signals are properly designed on the PCB. The DP and DM trace impedance should be 45ohm single ended and 90ohm differential. In cases where the DP and DM traces are not able to meet these requirements the HS Compensation register can be used to compensate for the losses in signal amplitude. FIELD NAME BIT ACCESS DEFAULT DESCRIPTION VariSense 1:0 rd/w 00b Used to lower the threshold of the squelch detector. 00: 100% (default) 01: 83% 10: 66.7% 11: 50% Reserved 2 rd 0b Read only, 0. Reserved 3 rd 0b Read only, 0. SMSC USB334x 79 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet FIELD NAME BIT ACCESS DEFAULT DESCRIPTION PHYBoost 6:4 rd/w 000b Used to change the output voltage of the Hi-Speed transmitter 000: Nominal 001: +3.7% 010: +7.4% 011: +11.0% 100: +14.7% 101: +18.3% 110: +22.0% 111: +25.7% Reserved 7 rd 0b Read only, 0. 7.1.3.2 USB-IF Charger Detection Address = 32h (read / write) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION VDatSrcEn 0 rd/w 0 V voltage enable DAT_SRC 0b: Disabled 1b: Enabled IDatSinkEn 1 rd/w 0 I current sink and V comparator DAT_SINK DAT_DET enable 0b: Disabled, V = 0. DAT_DET 1b: Enabled ContactDetectEn 2 rd/w 0 I Enable DP_SRC 0b: Disabled 1b: Enabled HostChrgEn 3 rd/w 0 Enable Charging Host Port Mode. 0b: Portable Device 1b: Charging Host Port. When the charging host port bit is set the connections of V , I , DAT_SRC DAT_SINK I , and V are reversed between DP DP_SRC DAT_DET and DM. VdatDet 4 rd 0 V Comparator output. IdatSinkEn must be set DAT_DET to 1 to enable the comparator. 0b: No voltage is detected on DP or Linestate[1:0] is not equal to 00b. 1b: Voltage detected on DP, and Linestate[1:0] = 00b. Note: VdatDet can also be read from the Carkit Interrupt Status register described in Section7.1.2.3. Reserved 5-7 rd Read only, 0. Note: The charger detection should be turned off before beginning USB operation. USB-IF Charger Detection Bits 2:0 should be set to 000b. Revision 1.2 (02-08-13) 80 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 7.1.3.3 Headset Audio Mode Address = 33h (read / write) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION HeadsetAudioEn 3:0 rd/w 0000b When this field is set to a value of ‘1010’, the Head- set Audio Mode is enabled as described in Section6.8.1. Reserved 7:4 rd 0h Read only, 0. 7.1.3.4 Vendor Rid Conversion Address = 36-38h (read), 36h (write), 37h (set), 38h (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION RidValue 2:0 rd/w 000b Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 100K ohms 011: 200K ohms 100: 440K ohms 101: ID floating 111: Error Note: RidValue can also be read from the Carkit Interrupt Status Register. RidConversionDone 3 rd 0b Automatically asserted by the USB334x when the Rid (Note7.4) Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status Register will not clear either RidConversionDone status bit. Note: RidConversionDone can also be read from the Carkit Interrupt Status Register. RidConversionStart 4 rd/w/s/c 0b When this bit is asserted either through a register write or set, the Rid converter will read the value of the ID resistor. When the conversion is complete this bit will auto clear. Reserved 5 rd/w/s/c 0b This bit must remain at 0. RidIntEn 6 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or’ed with the RidIntEn bit of the Carkit Interrupt Status register. Reserved 7 rd 0b Read only, 0. Note7.4 rd: Read Only with auto clear. SMSC USB334x 81 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 7.1.3.5 USB IO & Power Management Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear) FIELD NAME BIT ACCESS DEFAULT DESCRIPTION Reserved 0 rd/w/s/c 0b Read only, 0. SwapDP/DM 1 rd/w/s/c 0b When asserted, the DP and DM pins of the USB transceiver are swapped. This bit can be used to prevent crossing the DP/DM traces on the board. In UART mode, it swaps the routing to the DP and DM pins. In USB Audio Mode, it does not affect the SPK_L and SPK_R pins. UART RegOutput 3:2 rd/w/s/c 01b Controls the output voltage of the VBAT to VDD33 regulator in UART mode. When the PHY is switched from USB mode to UART mode regulator output will automatically change to the value specified in this register when TxdEn is asserted. 00: 3.3V 01: 3.0V (default) 10: 2.75V 11: 2.5V Note: When in USB Audio Mode the regulator will remain at 3.3V. When using this register it is recommended that the Link exit UART mode by using the RESETB pin. ChargerPullupEnDP 4 rd/w/s/c 0b Enables the R Pull-up resistor on the DP pin. (The CD pull-up is automatically enabled in UART mode) ChargerPullupEnDM 5 rd/w/s/c 0b Enables the R Pull-up resistor on the DM pin. (The CD pull-up is automatically enabled in UART mode) USB RegOutput 7:6 rd/w/s/c 00b Controls the output voltage of the VBAT to VDD33 regulator in USB mode. When the PHY is in Synchronous Mode, Serial Mode, or Low Power Mode, the regulator output will be the value specified in this register. 00: 3.3V (default) 01: 3.0V 10: 2.75V 11: 2.5V Revision 1.2 (02-08-13) 82 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 8 Application Notes 8.1 Application Diagram The USB334x requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this limit, so the USB334x provides an integrated over voltage protection circuit. The over voltage protection circuit works with an external resistor (R ) to lower the voltage at the VBUS VBUS pin. Table8.1 Component Values in Application Diagrams REFERENCE DESIGNATOR VALUE DESCRIPTION NOTES C See Table4.12 Bypass capacitor to ground (<1Ω ESR) Place as close as possible to the OUT for regulator stability. PHY. C See Table8.2 Capacitor to ground required by the USB Place near the USB connector. VBUS Specification. SMSC recommends <1Ω ESR. C System Bypass capacitor to ground. Typical Place as close as possible to the BYP dependent. values used are 0.1 or 0.01 μF. PHY. C System The USB connector housing may be AC- Industry convention is to ground DC_LOAD dependent. coupled to the device ground. only the host side of the cable shield. R 1kΩ or 20kΩ Series resistor to work with internal over See Section5.7.2.6 for VBUS voltage protection. information regarding power dissipation. R 8.06kΩ (±1%) Series resistor to establish reference See Section5.3 for information BIAS voltage. regarding power dissipation. Table8.2 Capacitance Values at VBUS of USB Connector MODE MIN VALUE MAX VALUE Host 120μF Device 1μF 10μF OTG 1μF 6.5μF SMSC USB334x 83 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet R must be installed to VBUS USB3341 / USB3346 enable overvoltage Link Controller protection of the VBUS pin. RESETB 21 RESETB RVBUS DATA7 10 DATA7 17 VBUS DATA6 9 DATA6 DATA5 8 DATA5 DATA4 7 DATA4 3.0-5.5V DATA3 6 DATA3 DATA2 5 DATA2 Supply DATA1 4 DATA1 The capacitor CVBUS 16 VBAT DATA0 3 DATA0 must be installed on STP 23 STP this side of RVBUS. CBYP NXT 2 NXT 15 VDD33 DIR 24 DIR CLKOUT 1 CLKIN C C OUT USB VBUS REFCLK 20 REFCLK Receptacle ULPI Output VBUS 18 ID Clock Mode DM 14 DM DP 13 DP VDD18 22 C SHIELD OUT 11 SPK_L RBIAS 19 GND CDC_BLOCK 12 SPK_R GND RBIAS 25 Optional Switched Signal to DP/DM Figure8.1 USB3341, USB3346, and USB3347 Application Diagram (Device configured for ULPI Clock Output Mode) Revision 1.2 (02-08-13) 84 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet R must be installed to VBUS USB3343 enable overvoltage Link Controller protection of the VBUS pin. RESETB 22 RESETB RVBUS DATA7 12 DATA7 17 VBUS DATA6 11 DATA6 DATA5 10 DATA5 DATA4 8 DATA4 3.0-5.5V DATA3 7 DATA3 DATA2 6 DATA2 Supply DATA1 5 DATA1 The capacitor CVBUS 16 VBAT DATA0 4 DATA0 must be installed on STP 24 STP this side of RVBUS. CBYP NXT 3 NXT 15 VDD33 DIR 1 DIR CLKOUT 2 CLKIN C COUT ULPI Output USB VBUS Clock Mode Receptacle VDD18 23 VBUS 18 ID C OUT DM 14 DM XO 20 DP 13 DP 1MΩ VDDIO Supply SHIELD Resonator 9 VDDIO 21 GND REFCLK/XI - or - CDC_BLOCK CBYP GND RBIAS 19 Crystal 25 CLOAD and Caps R BIAS Figure8.2 USB3343 Application Diagram (Device configured for ULPI Clock Output Mode) SMSC USB334x 85 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Link Controller CPEN R must be VBUS installed to enable VBUS overvoltage USB3341/USB3346 Switch protection of the RESETB 21 RESETB VBUS pin. EN 5V IN OUT RVBUS 17 VBUS DDAATTAA76 190 DDAATTAA76 DATA5 8 DATA5 DATA4 7 DATA4 3.0-5.5V DATA3 6 DATA3 The capacitor C DATA2 5 DATA2 must be installedVB oUnS Supply DATA1 4 DATA1 this side of R . 16 VBAT DATA0 3 DATA0 VBUS STP 23 STP CBYP NXT 2 NXT 15 VDD33 DIR 24 DIR USB CLKOUT 1 Receptacle CVBUS COUT VBUS REFCLK 20 CLKOUT ULPI Clock ID 18 ID In Mode DM 14 DM DP 13 DP VDD18 22 C SHIELD OUT 11 SPK_L VDDIO 8 VDDIO Suppl GND 12 SPK_R RBIAS 19 GND 25 CBYP Optional Switched Signal to DP/DM Figure8.3 USB3341, USB3346, and USB3347 Application Diagram (Host or OTG configured for ULPI Clock Input mode) 8.2 USB Charger Detection The USB334x provides the hardware described in the USB Battery Charging Specification. SMSC provides an Application Note which describes how to use the USB334x in a battery charging application. 8.3 Reference Designs SMSC has generated reference designs for connecting the USB334x to SoCs with a ULPI port. Please contact the SMSC sales office for more details. 8.4 ESD Performance The USB334x is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated into the USB334x protect the device whether or not it is powered up. Revision 1.2 (02-08-13) 86 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet 8.4.1 Human Body Model (HBM) Performance HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. The USB334x HBM performance is detailed in Table4.14. 8.4.2 EN/IEC 61000-4-2 Performance The EN/IEC 61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down. SMSC contracts with Independent laboratories to test the USB334x to EN/IEC 61000-4-2 in a working system. Reports are available upon request. Please contact your SMSC representative, and request information on 3rd party ESD test results. The reports show that systems designed with the USB334x can safely provide the ESD performance shown in Table4.14 without additional board level protection. In addition to defining the ESD tests, EN/IEC 61000-4-2 also categorizes the impact to equipment operation when the strike occurs (ESD Result Classification). The USB334x maintains an ESD Result Classification 1 or 2 when subjected to an EN/IEC 61000-4-2 (level 4) ESD strike. Both air discharge and contact discharge test techniques for applying stress conditions are defined by the EN/IEC 61000-4-2 ESD document. 8.4.2.1 Air Discharge To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and construction of the test equipment. 8.4.2.2 Contact Discharge The uncharged electrode first contacts the USB connector to prepare this test, and then the probe tip is energized. This yields more repeatable results, and is the preferred test method. The independent test laboratories contracted by SMSC provide test results for both types of discharge methods. SMSC USB334x 87 Revision 1.2 (02-08-13) DATASHEET

Chapter 9 Package Outline 3) 1 8- 0 2- 0 2 ( 1. n o si vi e R T E E 88 SH A T A D er v ei c s n a Tr PI L U B S U d e e p S Hi- y pl p u S gle 34x n 3 Si B ced heet C US Enhan Datas Figure9.1 24-pin QFN, 4x4mm Body, 0.5mm Pitch SMS

R e v is io n 1 .2 (0 2 -0 8 -1 3 ) D A T A S8 H9 E E T E n h a n c e d S in g le S u p p ly H i-S p e e d U S B S U M LP SC Figure9.2 24QFN, 4x4 Tape and Reel I T USB Datas ransc 3 h e 34 ee ive x t r

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Figure9.3 24QFN, 4x4 Reel Dimensions Revision 1.2 (02-08-13) 90 SMSC USB334x DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Figure9.4 24QFN, 4x4 Package Marking SMSC USB334x 91 Revision 1.2 (02-08-13) DATASHEET

Enhanced Single Supply Hi-Speed USB ULPI Transceiver Datasheet Chapter 10 Datasheet Revision History Table10.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 1.2 (02-08-13) Document co-branded: Microchip logo added; document disclaimer modified. Added to ordering information: “Please contact your SMSC sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines.” Rev. 1.2 (08-15-11) Product Features - cover The following text removed from package information bullet: “USB3341, USB3343, USB3346 and USB3347.” Rev 1.2 (08-10-11) Page 2 Added USB3347 product. Table3.1, Table3.2 Removed requirement that VDD18 be active while VDDIO is active. Table4.1, Table4.2 Updated power specifications Table2.2 Modified VDDIO Description Section7.1.3.1 Removed “and LPM” from section title. Throughout Document Updated support for Battery Charging v1.2. Throughout Document Various editorial improvements. Rev 1.1 (01-20-11) Chapter1, General Add Rapid Charge and BC 1.1 descriptions Description Paragraph 6 Figure 1.1 Block Diagram Added BC 1.1 Block Section 5.5.2, "REFCLK Correct REFCLK voltage reference Amplitude" Section 5.9, "USB Charger Added BC 1.1 Details Detection Support" Package Outline Changed format and figure titles Rev. 1.0 (08-25-10) Product Features Added SMSC RapidCharge Anywhere feature Rev. 0.9 (11-16-09) Initial datasheet release Revision 1.2 (02-08-13) 92 SMSC USB334x DATASHEET

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: USB3343-CP USB3347-CP USB3341-CP USB3341-CP-TR USB3346-CP-TR USB3347-CP-TR USB3346-CP