USB3320 Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver Features • Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Sup- • Integrated ESD protection circuits plement Revision 2.0 specification - Up to ±15kV IEC Air Discharge without exter- • Supports Headset Audio Mode nal devices • Supports the OTG Host Negotiation Protocol • Over-Voltage Protection circuit (OVP) protects the (HNP) and Session Request Protocol (SRP) VBUS pin from continuous DC voltages up to 30V • UART mode for non-USB serial data transfers • Integrated USB Switch • Internal 5V cable short-circuit protection of ID, DP - No degradation of Hi-Speed electrical char- and DM lines to VBUS or ground acteristics • Industrial Operating Temperature -40C to +85C - Allows single USB port of connection by pro- • 32-pin, QFN RoHS Compliant Package viding switching function for: (5 x 5 x 0.90 mm height) –Battery charging –Stereo and mono/mic audio Applications –USB Full-Speed/Low-Speed data • flexPWR® Technology The USB3320 is targeted for any application where a - Low current design ideal for battery powered Hi-Speed USB connection is desired and when board applications space, power, and interface pins must be minimized. - “Sleep” mode tri-states all ULPI pins and The USB3320 is well suited for: places the part in a low current state • Networking - 1.8V to 3.3V IO Voltage (±10%) • Audio Video • Integrated battery to 3.3V regulator • Medical - 2.2uF bypass capacitor • Industrial Computers - 100mV dropout voltage • Printers • “Wrapper-less” design for optimal timing perfor- • Repeaters mance and design ease • Communication - Low Latency Hi-Speed Receiver (43 Hi- Speed clocks Max) allows use of legacy UTMI Links with a ULPI bridge • Selectable Reference Clock Frequency - Frequencies: 12, 13, 19.2, 24, 26, 27, 38.4, 52 or 60MHz - pin selectable • External Reference Clock operation available - ULPI Input Clock Mode (60MHz sourced by Link) - 0 to 3.6V input drive tolerant - Able to accept “noisy” clock sources as refer- ence to internal, low-jitter PLL • Internal Oscillator operation available • This mode requires external Quartz Crystal or Ceramic Resonator • Smart detection circuits allow identification of USB charger, headset, or data cable insertion  2014-2016 Microchip Technology Inc. DS00001792E-page 1

USB3320 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00001792E-page 2  2014-2016 Microchip Technology Inc.

USB3320 Table of Contents 1.0 Introduction .....................................................................................................................................................................................4 2.0 USB3320 Pin Locations and Definitions .........................................................................................................................................6 3.0 Limiting Values ................................................................................................................................................................................9 4.0 Electrical Characteristics ...............................................................................................................................................................10 5.0 Architecture Overview ...................................................................................................................................................................17 6.0 ULPI Operation .............................................................................................................................................................................33 7.0 ULPI Register Map ........................................................................................................................................................................49 8.0 Application Notes ..........................................................................................................................................................................58 9.0 Package Information .....................................................................................................................................................................63 Appendix A: Data Sheet Revision History ...........................................................................................................................................67 The Microchip Web Site ......................................................................................................................................................................68 Customer Change Notification Service ...............................................................................................................................................68 Customer Support ...............................................................................................................................................................................68 Product Identification System .............................................................................................................................................................69  2014-2016 Microchip Technology Inc. DS00001792E-page 3

USB3320 1.0 INTRODUCTION 1.1 General Description The Microchip USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution and is an excellent match for a wide variety of products. The frequency of the reference clock is user selectable. The USB3320 includes an internal oscillator that may be used with either a quartz crystal or a ceramic resonator. Alternatively, the crystal input can be driven by an external clock oscil- lator. Another option is the use of a 60MHz external clock when using the ULPI Input Clock mode. Several advanced features make the USB3320 the transceiver of choice by reducing both electrical bill of material (eBOM) part count and printed circuit board (PCB) area. Outstanding ESD robustness eliminates the need for external ESD protection devices in typical applications. The internal Over-Voltage Protection circuit (OVP) protects the USB3320 from voltages up to 30V. By using a reference clock from the Link, the USB3320 removes the cost of a dedicated crystal reference from the design. And the integrated USB switch enables unique product features with a single USB port of connection. The USB3320 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device, or an On-the-Go (OTG) transceiver. In addition to the supporting USB signaling, the USB3320 also provides USB UART mode and USB Audio mode. USB3320 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB Transceiver to the Link. ULPI uses a method of in-band signaling and status byte transfers between the Link and transceiver to facilitate a USB ses- sion with only 12 pins. The USB3320 uses Microchip’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-less” tech- nology allows the transceiver to achieve a low latency transmit and receive time. Microchip’s low latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused. FIGURE 1-1: USB3320 BLOCK DIAGRAM REFCLK XO REFSEL[2:0] CPEN Crystal Oscillator and VBUS n OTG Low Jitter o ID cti Integrated BIAS RBIAS e ot PLL Pr D Integrated RESETB DP ES Hi-Speed Power VVBDADT33 USB Management VDD18 DM Transceiver ULPI Registers VDDIO and State STP USB Machine ULPI Interface NXT DP/DM DIR Switch CLKOUT K_L K_R DATA[7:0] P P S S DS00001792E-page 4  2014-2016 Microchip Technology Inc.

USB3320 The USB3320 includes an integrated 3.3V Low Drop Out (LDO) regulator that may optionally be used to generate 3.3V from power applied at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout voltage is less than 100mV which allows the transceiver to continue USB signaling when the voltage on VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the USB specifications. If the user would like to provide a 3.3V supply to the USB3320, the VBAT and VDD33 pins should be connected together as described in Section5.5.1. The USB3320 also includes integrated pull-up resistors that can be used for detecting the attachment of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3320 can charge its battery at more than the 500mA allowed when charging from a USB Host. Please see Microchip Application Note AN 19.7 - Battery Charging Using Microchip USB Transceivers for more information on battery charging. In USB UART mode, the USB3320 DP and DM pins are redefined to enable pass-through of asynchronous serial data. The USB3320 can only enter UART mode when the user programs the part into this mode, as described in Section6.5.1. In USB audio mode, a switch connects the DP pin to the SPK_R pin, and another switch connects he DM pin to the SPK_L pin. These switches are shown in the lower left-hand corner of Figure5.1. The USB3320 can be configured to enter USB audio mode as described in Section6.5.2. In addition, these switches are on when the RESETB pin of the USB3320 is asserted. The USB audio mode enables audio signaling from a single USB port of connection, and the switches may also be used to connect Full Speed USB from another transceiver onto the USB cable. 1.2 Reference Documents • Universal Serial Bus Specification, Revision 2.0, April 27, 2000 • On-The-Go Supplement to the USB 2.0 Specification, Revision 2.0, May 8, 2009 • USB Specification Revision 2.0 "Pull-up/pull-down resistors" ECN (27% Resistor ECN) • USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 • UTMI+ Specification, Revision 1.0, February 25, 2004 • UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20th, 2004 • Technical Requirements and Test Methods of Charger and Interface for Mobile Telecommunication Terminal Equipment (Chinese Charger Specification Approval Draft 11/29/2006)  2014-2016 Microchip Technology Inc. DS00001792E-page 5

USB3320 2.0 USB3320 PIN LOCATIONS AND DEFINITIONS 2.1 USB3320 Pin Locations and Descriptions 2.1.1 PACKAGE DIAGRAM WITH PIN LOCATIONS The illustration below is viewed from the top of the package. FIGURE 2-1: USB3320 PIN LOCATIONS - TOP VIEW B K VDDIO DIR VDD18 STP VDD18 RESET REFCL XO 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 CLKOUT 1 24 RBIAS NXT 2 23 ID DATA0 3 USB3300 22 VBUS Hi-Speed USB DATA1 4 Hi-Speed USB2 21 VBAT ULPI PHY DATA2 5 3U2L PPiIn P QHFYN 20 VDD33 32 Pin QFN DATA3 6 19 DM DATA4 7 18 DP GND FLAG REFSEL0 8 17 CPEN 0 1 2 3 4 5 6 9 1 1 1 1 1 1 1 DATA5 DATA6 EFSEL1 N/C DATA7 EFSEL2 SPK_L SPK_R R R 2.1.2 PIN DEFINITIONS The following table details the pin definitions for the figure above. TABLE 2-1: USB3320 PIN DESCRIPTION Direction/ Active Pin Name Description Type Level 1 CLKOUT Output, N/A ULPI Output Clock Mode: CMOS 60MHz ULPI clock output. All ULPI signals are driven synchronous to the rising edge of this clock. ULPI Input Clock Mode: This pin is connected to VDDIO to configure 60MHz ULPI Input Clock mode as described in Section5.4.1. Following POR or hardware reset, the voltage at CLKOUT must not exceed V as provided inTable4-4. IH_ED 2 NXT Output, High The transceiver asserts NXT to throttle the CMOS data. When the Link is sending data to the transceiver, NXT indicates when the current byte has been accepted by the transceiver. The Link places the next byte on the data bus in the following clock cycle. 3 DATA[0] I/O, N/A ULPI bi-directional data bus. CMOS DS00001792E-page 6  2014-2016 Microchip Technology Inc.

USB3320 TABLE 2-1: USB3320 PIN DESCRIPTION (CONTINUED) Direction/ Active Pin Name Description Type Level 4 DATA[1] I/O, N/A ULPI bi-directional data bus. CMOS 5 DATA[2] I/O, N/A ULPI bi-directional data bus. CMOS 6 DATA[3] I/O, N/A ULPI bi-directional data bus. CMOS 7 DATA[4] I/O, N/A ULPI bi-directional data bus. CMOS 8 REFSEL[0] Input, N/A This signal, along with REFSEL[1] and CMOS REFSEL[2] selects one of the available reference frequencies as defined in Table5-10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. 9 DATA[5] I/O, N/A ULPI bi-directional data bus. CMOS 10 DATA[6] I/O, N/A ULPI bi-directional data bus. CMOS 11 REFSEL[1] Input, N/A This signal, along with REFSEL[0] and CMOS REFSEL[2] selects one of the available reference frequencies as defined in Table5-10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. 12 N/C N/A This pin must not be connected. 13 DATA[7] I/O, N/A ULPI bi-directional data bus. CMOS 14 REFSEL[2] Input, N/A This signal, along with REFSEL[0] and CMOS REFSEL[1] selects one of the available reference frequencies as defined in Table5-10. Note: This signal must be tied to VDDIO when in ULPI 60MHz REFCLK IN mode. 15 SPK_L I/O, N/A USB switch in/out for DM signals Analog 16 SPK_R I/O, N/A USB switch in/out for DP signals Analog 17 CPEN Output, N/A External 5V supply enable. Controls the CMOS external V power switch. CPEN is low BUS on POR. 18 DP I/O, N/A D+ pin of the USB cable. Analog 19 DM I/O, N/A D- pin of the USB cable. Analog 20 VDD33 Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm ESR) bypass capacitor to ground is required for regulator stability. The bypass capacitor should be placed as close as possible to the USB3320. 21 VBAT Power N/A Regulator input.  2014-2016 Microchip Technology Inc. DS00001792E-page 7

USB3320 TABLE 2-1: USB3320 PIN DESCRIPTION (CONTINUED) Direction/ Active Pin Name Description Type Level 22 VBUS I/O, N/A This pin connects to an external resistor Analog (R ) connected to the VBUS pin of the VBUS USB cable. This pin is used for the VBUS comparator inputs and for VBUS pulsing during session request protocol. See Table5-7, "Required RVBUS Resistor Value". 23 ID Input, N/A ID pin of the USB cable. For applications Analog not using ID this pin can be connected to VDD33. For an A-Device ID is grounded. For a B-Device ID is floated. 24 RBIAS Analog, N/A Bias Resistor pin. This pin requires an CMOS 8.06kΩ (±1%) resistor to ground, placed as close as possible to the USB3320. Nominal voltage during ULPI operation is 0.8V. 25 XO Output, N/A External resonator pin. When using an CMOS external clock on REFCLK, this pin should be floated. 26 REFCLK Input, N/A ULPI Output Clock Mode: CMOS Reference frequency as defined in Table5- 10. ULPI Input Clock Mode: 60MHz ULPI clock input. 27 RESETB Input, Low When low, the part is suspended with all CMOS, ULPI outputs tri-stated. When high, the USB3320 will operate as a normal ULPI device, as described in Section5.5.2. The state of this pin may be changed asynchronously to the clock signals. When asserted for a minimum of 1 microsecond and then de-asserted, the ULPI registers are reset to their default state and all internal state machines are reset. 28 VDD18 Power N/A External 1.8V Supply input pin. This pad needs to be bypassed with a 0.1uF capacitor to ground, placed as close as possible to the USB3320. 29 STP Input, High The Link asserts STP for one clock cycle CMOS to stop the data stream currently on the bus. If the Link is sending data to the transceiver, STP indicates the last byte of data was on the bus in the previous cycle. 30 VDD18 Power N/A External 1.8V Supply input pin. This pad needs to be bypassed with a 0.1uF capacitor to ground, placed as close as possible to the USB3320. 31 DIR Output, N/A Controls the direction of the data bus. CMOS When the transceiver has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the transceiver has no data to transfer it drives DIR low and monitors the bus for commands from the Link. 32 VDDIO Power N/A External 1.8V to 3.3V ULPI supply input pin. This voltage sets the value of V for OH the ULPI signals. This pad needs to be bypassed with a 0.1uF capacitor to ground, placed as close as possible to the USB3320. FLAG GND Ground N/A Ground. DS00001792E-page 8  2014-2016 Microchip Technology Inc.

USB3320 3.0 LIMITING VALUES 3.1 Absolute Maximum Ratings TABLE 3-1: ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition MIN TYP MAX Units VBUS, VBAT, ID, CPEN, V Voltage measured at pin. -0.5 +6.0 V MAX_5V DP, DM, SPK_L, and VBUS tolerant to 30V with SPK_R voltage to GND external R . VBUS Maximum VDD18 voltage V -0.5 2.5 V MAX_18V to Ground Maximum VDDIO voltage V VDD18 = V -0.5 4.0 V MAX_IOV DD18 to Ground Maximum VDDIO voltage V VDD18 = 0V -0.5 0.7 V MAX_IOV to Ground Maximum VDD33 voltage V -0.5 4.0 V MAX_33V to Ground Maximum I/O voltage to V -0.5 V + 0.7 V MAX_IN DDIO Ground Operating Temperature T -40 85 C MAX_OP Storage Temperature T -55 150 C MAX_STG Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3.2 Recommended Operating Conditions TABLE 3-2: RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition MIN TYP MAX Units VBAT to GND V 3.1 5.5 V VBAT VDD33 to GND V 3.0 3.3 3.6 V DD33 VDDIO to GND V 1.6 1.8-3.3 3.6 V DDIO VDDIOVDD18min VDD18 to GND V 1.6 1.8 2.0 V DD18 Input Voltage on Digital V 0.0 V V I DDIO Pins (RESETB, STP, DIR, NXT, DATA[7:0]) Voltage on Analog I/O V 0.0 V V I(I/O) DD33 Pins (DP, DM, ID, CPEN, SPK_L, SPK_R) VBUS to GND V 0.0 5.5 V VMAX Ambient Temperature T -40 85 C A  2014-2016 Microchip Technology Inc. DS00001792E-page 9

USB3320 4.0 ELECTRICAL CHARACTERISTICS The following conditions are assumed unless otherwise specified: V = 3.1 to 5.5V; V = 1.6 to 2.0V; V = 1.6 to 2.0V; V = 0V; T = -40C to +85C VBAT DD18 DDIO SS A The current for 3.3V circuits is sourced at the VBAT pin, except when using an external 3.3V supply as shown in Figure5-7. 4.1 Operating Current TABLE 4-1: ELECTRICAL CHARACTERISTICS: OPERATING CURRENT Parameter Symbol Condition MIN TYP MAX Units Synchronous Mode Current I Start-up sequence defined in 7.5 mA 33AVG(SYNC) (Default Configuration) Section5.5.4 has I 28.0 mA 18AVG(SYNC) completed. I 4.1 mA IOAVG(SYNC) Synchronous Mode Current I Active USB Transfer 11.1 mA 33AVG(HS) (HS USB operation) I 29.4 mA 18AVG(HS) I 5.9 mA IOAVG(HS) Synchronous Mode Current I Active USB Transfer 6.3 mA 33AVG(FS) (FS/LS USB operation) I 22.5 mA 18AVG(FS) I 5.0 mA IOAVG(FS) Serial Mode Current I 5.6 mA 33AVG(FS_S) (FS/LS USB) I 2.4 mA 18AVG(FS_S) Note 4-1 I 86 uA IOAVG(FS_S) USB UART Current I 5.6 mA 33AVG(UART) I 2.4 mA Note 4-1 18AVG(UART) I 58 uA IOAVG(UART) Low Power Mode I V = 4.2V 18.8 uA DD33(LPM) VBAT V = 1.8V I DD18 0.7 uA Note 4-2 DD18(LPM) V = 1.8V DDIO I 30 uA DDIO(LPM) Standby Mode I RESETB = 0 18 uA DD33(RSTB) V = 4.2V I VBAT 0.6 uA DD18(RSTB) V = 1.8V DD18 IDDIO(RSTB) VDDIO = 1.8V 0.1 uA Note 4-1 ClockSuspendM bit = 0. Note 4-2 SessEnd, VbusVld, and IdFloat comparators disabled. STP Interface protection disabled. DS00001792E-page 10  2014-2016 Microchip Technology Inc.

USB3320 4.2 Clock Specifications TABLE 4-2: ULPI CLOCK SPECIFICATIONS Parameter Symbol Condition MIN TYP MAX Units Suspend Recovery Time T 26MHz REFCLK 1.03 2.28 ms START Note 4-3 12MHz REFCLK 2.24 3.49 ms 52MHz REFCLK 0.52 1.77 ms 24MHz REFCLK 1.12 2.37 ms 19.2MHz REFCLK 1.40 2.65 ms 27MHz REFCLK 1.00 2.25 ms 38.4MHz REFCLK 0.70 1.95 ms 13MHz REFCLK 2.07 3.32 ms PHY Preparation Time T 60MHz REFCLK 0.4 0.45 0.5 ms PREP ULPI Input Clock Mode CLKOUT Duty Cycle DC ULPI Input Clock Mode 45 55 % CLKOUT REFCLK Duty Cycle DC 20 80 % REFCLK REFCLK Frequency Accuracy F -500 +500 PPM REFCLK Note 4-3 The Suspend Recovery Time is measured from the start of the REFCLK to when the USB3320 de- asserts DIR. Note: The USB3320 uses the AutoResume feature, Section6.2.4.4, to allow a host start-up time of less than 1ms. 4.3 ULPI Interface Timing TABLE 4-3: ULPI INTERFACE TIMING Parameter Symbol Condition MIN MAX Units 60MHz ULPI Output Clock Note 4-4 Setup time (STP, data in) T , T Model-specific REFCLK 5.0 ns SC SD Hold time (STP, data in) T , T Model-specific REFCLK 0.0 ns HC HD Output delay (control out, 8-bit data out) T , T Model-specific REFCLK 1.0 3.5 ns DC DD 60MHz ULPI Input Clock Setup time (STP, data in) T , T 60MHz REFCLK 1.5 ns SC SD Hold time (STP, data in) T , T 60MHz REFCLK -0.5 ns HC HD Output delay (control out, 8-bit data out) T , T 60Mhz REFCLK 1.5 6.0 ns DC DD Note: V = 1.6 to 2.0V; V = 0V; T = -40C to +85C. DD18 SS A Note 4-4 REFCLK does not need to be aligned in any way to the ULPI signals.  2014-2016 Microchip Technology Inc. DS00001792E-page 11

USB3320 4.4 Digital IO Pins TABLE 4-4: DIGITAL IO CHARACTERISTICS: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK PINS Parameter Symbol Condition MIN TYP MAX Units Low-Level Input Voltage V V 0.4 * V IL SS V DDIO High-Level Input Voltage V 0.68 * V V IH DDIO V DDIO High-Level Input Voltage V 0.68 * V V IH DD33 REFCLK only V DD18 Low-Level Output Voltage V I = 8mA 0.4 V OL OL High-Level Output Voltage V I = -8mA V - V OH OH DDIO 0.4 High-Level Output Voltage V I = -8mA V - V OH OH DD33 CPEN Only 0.4 Input Leakage Current I V - ±10 uA LI DD33 0.4 Pin Capacitance Cpin 4 pF STP pull-up resistance R InterfaceProtectDisable = 0 55 67 77 kΩ STP DATA[7:0] pull-dn resistance R ULPI Synchronous Mode 55 67 77 kΩ DATA_PD CLKOUT External Drive V At start-up or following reset 0.4 * V IH_ED V DDIO 4.5 DC Characteristics: Analog I/O Pins TABLE 4-5: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) Parameter Symbol Condition MIN TYP MAX Units LS/FS FUNCTIONALITY Input levels Differential Receiver Input V | V(DP) - V(DM) | 0.2 V DIFS Sensitivity Differential Receiver V 0.8 2.5 V CMFS Common-Mode Voltage Single-Ended Receiver Low V Note 4-6 0.8 V ILSE Level Input Voltage Single-Ended Receiver High V Note 4-6 2.0 V IHSE Level Input Voltage Single-Ended Receiver V 0.050 0.150 V HYSSE Hysteresis Output Levels Low Level Output Voltage V Pull-up resistor on DP; 0.3 V FSOL R = 1.5kΩ to V L DD33 High Level Output Voltage V Pull-down resistor on DP, 2.8 3.6 V FSOH DM; Note 4-6 R = 15kΩ to GND L Termination Driver Output Impedance for Z Steady state drive 40.5 45 49.5 Ω HSDRV HS and FS Input Impedance Z RX, RPU, RPD disabled 1.0 MΩ INP Pull-up Resistor Impedance R Bus Idle, Note 4-5 0.900 1.24 1.575 kΩ PU Pull-up Resistor Impedance R Device Receiving, Note 4-5 1.425 2.26 3.09 kΩ PU DS00001792E-page 12  2014-2016 Microchip Technology Inc.

USB3320 TABLE 4-5: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (CONTINUED) Parameter Symbol Condition MIN TYP MAX Units Pull-dn Resistor Impedance R Note 4-5 14.25 16.9 20 kΩ PD Weak Pull-up Resistor R Configured by bits 4 and 5 128 170 212 kΩ CD Impedance in USB IO & Power Management register. HS FUNCTIONALITY Input levels HS Differential Input Sensitivity V | V(DP) - V(DM) | 100 mV DIHS HS Data Signaling Common V -50 500 mV CMHS Mode Voltage Range High-Speed Squelch Detection Note 4-7 100 150 mV Threshold (Differential Signal V HSSQ Amplitude) Output Levels Hi-Speed Low Level V 45Ω load -10 10 mV HSOL Output Voltage (DP/DM referenced to GND) Hi-Speed High Level V 45Ω load 360 440 mV HSOH Output Voltage (DP/DM referenced to GND) Hi-Speed IDLE Level V 45Ω load -10 10 mV OLHS Output Voltage (DP/DM referenced to GND) Chirp-J Output Voltage V HS termination resistor 700 1100 mV CHIRPJ (Differential) disabled, pull-up resistor connected. 45Ω load. Chirp-K Output Voltage V HS termination resistor -900 -500 mV CHIRPK (Differential) disabled, pull-up resistor connected. 45Ω load. Leakage Current OFF-State Leakage Current I ±10 uA LZ Port Capacitance Transceiver Input Capacitance C Pin to GND 5 10 pF IN Note 4-5 The resistor value follows the 27% Resistor ECN published by the USB-IF. Note 4-6 The values shown are valid when the USB RegOutput bits in the USB IO & Power Management register are set to the default value. Note 4-7 An automatic waiver up to 200mV is granted to accommodate system-level elements such as measurement/test fixtures, captive cables, EMI components, and ESD suppression.  2014-2016 Microchip Technology Inc. DS00001792E-page 13

USB3320 4.6 Dynamic Characteristics: Analog I/O Pins TABLE 4-6: DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) Parameter Symbol Condition MIN TYP MAX Units FS Output Driver Timing FS Rise Time T C = 50pF; 10 to 90% of 4 20 ns FR L |V - V | OH OL FS Fall Time T C = 50pF; 10 to 90% of 4 20 ns FF L |V - V | OH OL Output Signal Crossover V Excluding the first transition 1.3 2.0 V CRS Voltage from IDLE state Differential Rise/Fall Time T Excluding the first transition 90 111.1 % FRFM Matching from IDLE state LS Output Driver Timing LS Rise Time T C = 50-600pF; 75 300 ns LR L 10 to 90% of |V - V | OH OL LS Fall Time T C = 50-600pF; 75 300 ns LF L 10 to 90% of |V - V | OH OL Differential Rise/Fall Time T Excluding the first transition 80 125 % LRFM Matching from IDLE state HS Output Driver Timing Differential Rise Time T 500 ps HSR Differential Fall Time T 500 ps HSF Driver Waveform Eye pattern of Template 1 Requirements in USB 2.0 specification Hi-Speed Mode Timing Receiver Waveform Eye pattern of Template 4 Requirements in USB 2.0 specification Data Source Jitter and Eye pattern of Template 4 Receiver Jitter Tolerance in USB 2.0 specification 4.7 OTG Electrical Characteristics TABLE 4-7: OTG ELECTRICAL CHARACTERISTICS Parameter Symbol Condition MIN TYP MAX Units SessEnd trip point V 0.2 0.5 0.8 V SessEnd SessVld trip point V 0.8 1.4 2.0 V SessVld VbusVld trip point V 4.4 4.58 4.75 V VbusVld A-Device Impedance R Maximum A device 100 kΩ IdGnd Impedance to ground on ID pin ID Float trip point V 1.9 2.2 2.5 V IdFloat VBUS Pull-Up R VBUS to VDD33 Note 4-8 1.29 1.34 1.45 kΩ VPU (ChargeVbus = 1) VBUS Pull-down R VBUS to GND Note 4-8 1.55 1.7 1.85 kΩ VPD (DisChargeVbus = 1) VBUS Impedance R VBUS to GND 40 75 100 kΩ VB ID pull-up resistance R IdPullup = 1 80 100 120 kΩ ID ID weak pull-up resistance R IdPullup = 0 1 MΩ IDW ID pull-dn resistance R IdGndDrv = 1 1000 Ω IDPD DS00001792E-page 14  2014-2016 Microchip Technology Inc.

USB3320 Note 4-8 The R and R values include the required 1kΩ external R resistor. VPD VPU VBUS 4.8 USB Audio Switch Characteristics TABLE 4-8: USB AUDIO SWITCH CHARACTERISTICS Parameter Symbol Condition MIN TYP MAX Units Minimum “ON” Resistance R 0 < V < V 2.7 5 5.8 Ω ON_Min switch DD33 Maximum “ON” Resistance R 0 < V < V 4.5 7 10 Ω ON_Max switch DD33 Minimum “OFF” Resistance R 0 < V < V 1 MΩ OFF_Min switch DD33 4.9 Regulator Output Voltages and Capacitor Requirement TABLE 4-9: REGULATOR OUTPUT VOLTAGES AND CAPACITOR REQUIREMENT Parameter Symbol Condition MIN TYP MAX Units Regulator Output Voltage V 6V > VBAT > 3.1V 3.0 3.3 3.6 V DD33 Regulator Output Voltage V USB UART Mode & UART 2.7 3.0 3.3 V DD33 RegOutput[1:0] = 01 6V > VBAT > 3.1V Regulator Output Voltage V USB UART Mode & UART 2.47 2.75 3.03 V DD33 RegOutput[1:0] = 10 6V > VBAT > 3.1V Regulator Output Voltage V USB UART Mode & UART 2.25 2.5 2.75 V DD33 RegOutput[1:0] = 11 6V > VBAT > 3.1V Regulator Bypass Capacitor C 2.2 uF OUT Bypass Capacitor ESR C 1 Ω ESR TABLE 4-10: ESD AND LATCH-UP PERFORMANCE Parameter Conditions MIN TYP MAX Units Comments ESD PERFORMANCE Note 4-9 Human Body Model ±8 kV Device System EN/IEC 61000-4-2 Contact ±8 kV 3rd party system test Discharge System EN/IEC 61000-4-2 Air-gap ±15 kV 3rd party system test Discharge LATCH-UP PERFORMANCE All Pins EIA/JESD 78, Class II 150 mA Note 4-9 REFCLK, XO, SPK_L and SPK_R pins: ±5kV Human Body Model.  2014-2016 Microchip Technology Inc. DS00001792E-page 15

USB3320 4.10 Piezoelectric Resonator for Internal Oscillator The internal oscillator may be used with an external quartz crystal or ceramic resonator as described in Section5.4.1.2. See Table4-11 for the recommended crystal specifications. TABLE 4-11: USB3320 QUARTZ CRYSTAL SPECIFICATIONS Parameter Symbol MIN TYP MAX Units Notes Crystal Cut AT, typ Crystal Oscillation Mode Fundamental Mode Crystal Calibration Mode Parallel Resonant Mode Frequency F - Table5-10 - MHz fund Total Allowable PPM Budget - - ±500 PPM Note 4-10 Shunt Capacitance C - 7 typ - pF O Load Capacitance C - 20 typ - pF L Drive Level P 0.5 - - mW W Equivalent Series Resistance R - - 30 Ohm 1 Operating Temperature Range -40 - +85 oC USB3320 REFCLK Pin - 3 typ - pF Note 4-11 Capacitance USB3320 XO Pin Capacitance - 3 typ - pF Note 4-11 Note 4-10 The required bit rate accuracy for Hi-Speed USB applications is ±500 ppm as provided in the USB 2.0 Specification. This takes into account the effect of voltage, temperature, aging, etc. Note 4-11 This number includes the pad, the bond wire and the lead frame. Printed Circuit Board (PCB) capacitance is not included in this value. The PCB capacitance value and the capacitance value of the XO and REFCLK pins are required to accurately calculate the value of the two external load capacitors. DS00001792E-page 16  2014-2016 Microchip Technology Inc.

USB3320 5.0 ARCHITECTURE OVERVIEW The USB3320 consists of the blocks shown in the diagram below. All pull-up resistors shown in this diagram are con- nected internally to the VDD33 pin. FIGURE 5-1: USB3320 INTERNAL BLOCK DIAGRAM DrvVbus or’d with DrvVbusExternal DATA7 VDD33 DATA6 CPEN IdGnd DATA5 RIDW RID IdFloat O DDAATTAA43 VBUIDS OVP VDRDVPU33 RSieds VsEalnude OTG Module DUigLiPtiaI l Digital I DNSDDDTIXAAARPTTTTAAA201 VBAT n SessValid CLKOUT o RESETB VDD33 D Protecti LDOVDD33 RVB RVPD VbusValid TX Data RX Data VVDDDDI1O8 S REFCLK E RCD RCD RPU RPU HS/FS/LS ILnotewg Jraittteedr XROEFSEL0 TX PLL REFSEL1 DP TX Encoding REFSEL2 DM HS/FS/LS RX BIAS RBIAS SPK_L RPD RPD RX Decoding SPK_R 5.1 ULPI Digital Operation and Interface This section of the USB3320 is covered in detail in Section 6.0, "ULPI Operation". 5.2 USB 2.0 Hi-Speed Transceiver The blocks in the lower left-hand corner of Figure5.1 interface to the DP/DM pins. 5.2.1 USB TRANSCEIVER The USB3320 includes the receivers and transmitters that are compliant to the Universal Serial Bus Specification Rev 2.0. The DP/DM signals in the USB cable connect directly to the receivers and transmitters. The RX block consists of a differential receiver for HS and separate receivers for FS/LS mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. For HS mode sup- port, the HS RX block contains a squelch circuit to insure that noise is not interpreted as data. The RX block also includes a single-ended receiver on each of the data lines to determine the correct FS linestate. Data from the TX Logic block is encoded, bit stuffed, serialized and transmitted onto the USB cable by the TX block. Separate differential FS/LS and HS transmitters are included to support all modes. The USB3320 TX block meets the HS signaling level requirements in the USB 2.0 Specification when the PCB traces from the DP and DM pins to the USB connector have very little loss. In some systems, it may be desirable to compensate for loss by adjusting the HS transmitter amplitude. The Boost bits in the HS TX Boost register may be configured to adjust the HS transmitter amplitude at the DP and DM pins.  2014-2016 Microchip Technology Inc. DS00001792E-page 17

USB3320 5.2.2 TERMINATION RESISTORS The USB3320 transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω high speed termination resistors. These resistors require no tun- ing or trimming by the Link. The state of the resistors is determined by the operating mode of the transceiver when oper- ating in synchronous mode. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration. The possible valid resistor combinations are shown in Table5-1, and operation is maintained in only the configurations shown. If a ULPI Register Setting is config- ured that does not match a setting in the table, the transceiver operation is not ensured and the settings in the last row of Table5-1 will be used. • RPU_DP_EN activates the 1.5kΩ DP pull-up resistor • RPU_DM_EN activates the 1.5kΩ DM pull-up resistor • RPD_DP_EN activates the 15kΩ DP pull-down resistor • RPD_DM_EN activates the 15kΩ DM pull-down resistor • HSTERM_EN activates the 45Ω DP and DM high speed termination resistors The USB3320 also includes two DP and DM pull-up resistors described in Section5.8. TABLE 5-1: DP/DM TERMINATION VS. SIGNALING MODE USB3320 Termination Resistor ULPI Register Settings Settings 0] Signaling Mode CVRSELECT[1: TERMSELECT OPMODE[1:0] DPPULLDOWN DMPULLDOWN RPU_DP_EN RPU_DM_EN RPD_DP_EN RPD_DM_EN HSTERM_EN X General Settings Tri-State Drivers XXb Xb 01b Xb Xb 0b 0b 0b 0b 0b Power-up or VBUS < V 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b SESSEND Host Settings Host Chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Host Hi-Speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b Host Full Speed X1b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host low Speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Test J/Test_K 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Peripheral Settings Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b Peripheral FS 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral LS 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b DS00001792E-page 18  2014-2016 Microchip Technology Inc.

USB3320 TABLE 5-1: DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED) USB3320 Termination Resistor ULPI Register Settings Settings 0] Signaling Mode CVRSELECT[1: TERMSELECT OPMODE[1:0] DPPULLDOWN DMPULLDOWN RPU_DP_EN RPU_DM_EN RPD_DP_EN RPD_DM_EN HSTERM_EN X Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b OTG device, Peripheral Chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b OTG device, Peripheral FS 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral Test J/Test K 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b Any combination not defined above Note 5- 0b 0b 0b 0b 0b 1 Note1: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification. 2: USB3320 does not support operation as an upstream hub port. See Section 6.2.4.3, "UTMI+ Level 3". Note 5-1 The transceiver operation is not ensured in a combination that is not defined. The USB3320 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table4-5. 5.3 Bias Generator This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06K, 1% tolerance, reference resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the USB3320 to minimize the trace length. The nominal voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80W of power. 5.4 Integrated Low Jitter PLL The USB3320 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS USB signal quality. This clock is used by the transceiver during both transmit and receive. The USB3320 PLL requires an accurate frequency reference to be driven on the REFCLK pin. 5.4.1 REFCLK MODE SELECTION The USB3320 is designed to operate in one of two available modes as shown in Table5-2. In the first mode, a 60MHz ULPI clock is driven on the REFCLK pin as described in Section5.4.1.1. In the second mode, the USB3320 generates the ULPI clock as described in Section5.4.1.2. When using the second mode, the frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Section5.10. TABLE 5-2: REFCLK MODES REFCLK Mode ULPI Clock Description Frequency ULPI Input Clock Mode 60Mhz Sourced by Link, driven on the REFCLK pin ULPI Output Clock Table5-10 Sourced by USB3320 at the CLKOUT pin Mode During start-up, the USB3320 monitors the CLKOUT pin to determine which mode has been configured as described in Section5.4.1.1.  2014-2016 Microchip Technology Inc. DS00001792E-page 19

USB3320 The system must not drive voltage on the CLKOUT pin following POR or hardware reset that exceeds the value of V provided in Table4-4. IH_ED 5.4.1.1 ULPI Input Clock Mode (60MHz REFCLK Mode) When using ULPI Input Clock Mode, the Link must supply the 60MHz ULPI clock to the USB3320. As shown in Figure5- 2, the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDDIO. A simplified schematic using the ULPI Input Clock Mode is shown in Figure8-2. After the PLL has locked to the correct frequency, the USB3320 will de-assert DIR and the Link can begin using the ULPI interface. The USB3320 is ensured to start the clock within the time specified in Table4-2. For Host applications, the ULPI AutoResume bit should be enabled. This is described in Section6.2.4.4. REFSEL[2], REFSEL[1] and REFSEL[0] should all be tied to VDDIO for ULPI Input Clock Mode. FIGURE 5-2: CONFIGURING THE USB332X FOR ULPI INPUT CLOCK MODE (60 MHZ) ~~ VDDIO CLKOUT ULPI Clk Out REFCLK To PLL Link Reference Clk In ~~ PHY Clock Source 5.4.1.2 ULPI Output Clock When using ULPI Output Clock Mode, the USB3320 generates the 60MHz ULPI clock used by the Link. The frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Table5-10. As shown in Figure5-3, the CLKOUT pin sources the 60MHz ULPI clock to the Link. FIGURE 5-3: CONFIGURING THE USB332X FOR ULPI OUTPUT CLOCK MODE ~~ ULPI Clk In CLKOUT From PLL Link Clock REFCLK Source To PLL ~~ PHY DS00001792E-page 20  2014-2016 Microchip Technology Inc.

USB3320 In this mode, the REFCLK pin may be driven at the reference clock frequency. Alternatively, the internal oscillator may be used with an external crystal or resonator as shown in Figure5-4. An example of ULPI Output Clock Mode is shown in Figure8-1. FIGURE 5-4: ULPI OUTPUT CLOCK MODE ~~ ULPI Clk In CLKOUT Link From PLL REFCLK Internal Oscillator To PLL Resonator XO - or - Crystal ~~ and Caps PHY CLOAD After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB3320 is ensured to start the clock within the time specified in Table4-2, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be enabled. This is described in Section6.2.4.4. When using ULPI Output Clock Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI interface signals; in other words, there is no need to align the phase of the REFCLK and the CLKOUT. 5.4.2 REFCLK AMPLITUDE The reference clock is connected to the REFCLK pin as shown in the application diagrams, Figure8-1, Figure8-2 and Figure8-3. The REFCLK pin is designed to be driven with a square wave from 0V to V , but can be driven with a DD18 square wave from 0V to as high as 3.6V. The USB3320 uses only the positive edge of the REFCLK. If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the REFCLK pin. If using an analog clock, the DC bias should be set at the mid-point of the VDD18 supply using a bias circuit as shown in Figure5-5. The amplitude must be greater than 300mV peak to peak. The component values pro- vided in Figure5-5 are for example only. The actual values should be selected to satisfy system requirements. The REFCLK amplitude must comply with the signal amplitudes shown in Table4-4 and the duty cycle in Table4-2. FIGURE 5-5: EXAMPLE OF CIRCUIT USED TO SHIFT A REFERENCE CLOCK COMMON- MODE VOLTAGE LEVEL VDD18 k 7 4 To REFCLK pin Clock 0.1uF k 7 4  2014-2016 Microchip Technology Inc. DS00001792E-page 21

USB3320 5.4.3 REFCLK JITTER The USB3320 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Input Clock Mode or ULPI Output Clock Mode, the USB3320 Hi-Speed eye diagram may be degraded. The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table4-2. 5.4.4 REFCLK ENABLE/DISABLE The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start running after the time specified in Table4-2. If the REFCLK enable is delayed relative to the RESETB pin, the ULPI interface will start operation delayed by the same amount. The REFCLK can be run at anytime the RESETB pin is low without causing the USB3320 to start-up or draw current. When the USB3320 is placed in Low Power Mode or Carkit Mode, the REFCLK can be stopped after the final ULPI register write is complete. The STP pin is asserted to bring the USB3320 out of Low Power Mode. The REFCLK should be started at the same time STP is asserted to minimize the USB3320 start-up time. If the REFCLK is stopped while CLKOUT is running, the PLL will come out of lock and the frequency of the CLKOUT signal will decrease to the minimum allowed by the PLL design. If the REFCLK is stopped during a USB session, the session may drop. 5.5 Internal Regulators and POR The USB3320 includes integrated power management functions, including a Low-Dropout regulator that can be used to generate the 3.3V USB supply, and a POR generator described in Section5.5.2. 5.5.1 INTEGRATED LOW DROPOUT REGULATOR The USB3320 has an integrated linear regulator. Power sourced at the VBAT pin is regulated to 3.3V and the regulator output is on the VDD33 pin. To ensure stability, the regulator requires an external bypass capacitor (C as specified OUT) in Table4-9 placed as close to the pin as possible. The USB3320 regulator is designed to generate a 3.3 volt supply for the USB3320 only. Using the regulator to provide current for other circuits is not recommended and Microchip does not support USB performance or regulator stability. During USB UART mode the regulator output voltage can be changed to allow the USB3320 to work with UARTs oper- ating at different operating voltages. The regulator output is configured to the voltages shown in Table4-9 with the UART RegOutput[1:0] bits in the USB IO & Power Management register. The USB3320 regulator can be powered in the three methods as shown below. For USB Peripheral, Host, and OTG operations the regulator can be connected as shown in Figure5-6 or Figure5-7 below. For OTG operation, the VDD33 supply on the USB3320 must be powered to detect devices attaching to the USB connector and detect a SRP during an OTG session. When using a battery to supply the USB3320, the battery voltage must be within the range of 3.1V to 5.5V. DS00001792E-page 22  2014-2016 Microchip Technology Inc.

USB3320 FIGURE 5-6: POWERING THE USB3320 FROM A BATTERY ~~ R VBUS VBUS VBUS To USB Con. To OTG VBAT VDD33 LDO C OUT GND PHY ~~ The USB3320 can be powered from an external 3.3V supply as shown below in Figure5-7. When using the external supply, both the VBAT and VDD33 pins are connected together. The bypass capacitor, C , is recommended when BYP using the external supply. FIGURE 5-7: POWERING THE USB3320 FROM A 3.3V SUPPLY ~~ R VBUS VBUS VBUS To USB Con. To OTG VBAT VDD33 LDO Vdd 3.3V C BYP GND PHY ~~ For peripheral only or host only operation, the VBAT supply shown below in Figure5-8 may be connected to the VBUS pin of the USB connector for bus powered applications. In this configuration, external overvoltage protection is required to protect the VBAT supply from any transient voltage present at the VBUS pin of the USB connector.  2014-2016 Microchip Technology Inc. DS00001792E-page 23

USB3320 The VBAT input must never be exposed to a voltage that exceeds V . (See Table3-2) VBAT FIGURE 5-8: POWERING THE USB3320 FROM VBUS ~~ R VBUS VBUS VBUS To USB Con. To OTG VBAT OVP VDD33 LDO C OUT GND PHY ~~ 5.5.2 POWER ON RESET (POR) The USB3320 provides a POR circuit that generates an internal reset pulse after the VDD18 supply is stable. After the internal POR goes high and the RESETB pin is high, the USB3320 will release from reset and begin normal ULPI oper- ation as described in Section5.5.4. The ULPI registers will power up in their default state summarized in Table7-1 when the 1.8V supply is brought up. Cycling the 1.8 volt power supply will reset the ULPI registers to their default states. The RESETB pin can also be used to reset the ULPI registers to their default state (and reset all internal state machines) by bringing the pin low for a min- imum of 1 microsecond and then high. The Link is not required to assert the RESETB pin. A pull-down resistor is not present on the RESETB pin and therefore the Link must drive the RESETB pin to the desired state at all times (including system start-up) or connect the RESETB pin to VDDIO. 5.5.3 RECOMMENDED POWER SUPPLY SEQUENCE For USB operation the USB3320 requires the VBAT, VDD33, VDDIO and VDD18 supples. VBAT, VDD33, and VDD18 can be applied in any order. The VDD18 supply must be turned on and stable before the VDDIO supply is applied. This does not apply in cases where the VDD18 and VDDIO supply pins are tied together. When the VBAT supply is applied, the integrated regulator will automatically start-up and regulate VBAT to VDD33. If the VDD33 supply is powered and the VDD18 supply is not powered, the 3.3V circuits are powered off and the VDD33 current will be limited as shown in Table4-1. The ULPI interface will start operating after the VDD18 and VDDIO supplies are applied and the RESETB pin is brought high. The RESETB pin must be held low until the VDD18 and VDDIO supplies are stable. If the Link is not ready to interface the USB3320, the Link may choose to hold the RESETB pin low until it is ready to control the ULPI interface. TABLE 5-3: OPERATING MODE VS. POWER SUPPLY CONFIGURATION VDD33 VDD18 RESETB Operating Modes Available 0 0 0 Powered Off 0 1 0 RESET Mode. 0 1 1 In this configuration the ULPI interface is available and can be programed into all operating modes described in Section 6.0, "ULPI Operation". All USB signals will read 0. 1 0 X In this mode the ULPI interface is not active and the circuits powered from the VDD33 supply are turned off and the current will be limited to the RESET Mode current. (Note 5-2) DS00001792E-page 24  2014-2016 Microchip Technology Inc.

USB3320 TABLE 5-3: OPERATING MODE VS. POWER SUPPLY CONFIGURATION (CONTINUED) VDD33 VDD18 RESETB Operating Modes Available 1 1 0 RESET Mode 1 1 1 Full USB operation as described in Section 6.0, "ULPI Operation". Note: Anytime VBAT is powered per Table3-2, the VDD33 pin will be powered up. Note 5-2 VDDIO must be powered to tri-state the ULPI interface in this configuration. 5.5.4 START-UP The power on default state of the USB3320 is ULPI Synchronous mode. The USB3320 requires the following conditions to begin operation: the power supplies must be stable, the REFCLK must be present and the RESETB pin must be high. After these conditions are met, the USB3320 will begin ULPI operation that is described in Section 6.0, "ULPI Opera- tion". Figure5-9 below shows a timing diagram to illustrate the start-up of the USB3320. At T0, the supplies are stable and the USB3320 is held in reset mode. At T1, the Link drives RESETB high after the REFCLK has started. The RESETB pin may be brought high asynchronously to REFCLK. At this point the USB3320 will drive idle on the data bus and assert DIR until the internal PLL has locked. After the PLL has locked, the USB3320 will check that the Link has de-asserted STP and at T2 it will de-assert DIR and begin ULPI operation. The ULPI bus will be available as shown in Figure5-9 in the time defined as T given in Table4-2. If the REFCLK START signal starts after the RESETB pin is brought high, then time T0 will begin when REFCLK starts. T also assumes START that the Link has de-asserted STP. If the Link has held STP high the USB3320 will hold DIR high until STP is de- asserted. When the LINK de-asserts STP, it must drive a ULPI IDLE one cycle after DIR de-asserts. FIGURE 5-9: ULPI START-UP TIMING T0 T1 T2 SUPPLIES STABLE REFCLK REFCLK valid RESETB DATA[7:0] PHY Tri-States PHY Drives Idle IDLE RXCMD IDLE DIR PHY Tri-States PHY Drives High STP LINK Drives Low T START  2014-2016 Microchip Technology Inc. DS00001792E-page 25

USB3320 5.6 USB On-The-Go (OTG) The USB3320 provides full support for USB OTG protocol. OTG allows the USB3320 to be dynamically configured as a host or device depending on the type of cable inserted into the receptacle. When the Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB device becomes the A-device. When a Micro-B plug is inserted, the device becomes the B-device. The OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral. The differences are covered in the “On-The-Go Supplement to the USB 2.0 Specification”. In applications where only Host or Device is required, the OTG Module is unused. 5.6.1 ID RESISTOR DETECTION The ID pin of the USB connector is monitored by the ID pin of the USB3320 to detect the attachment of different types of USB devices and cables. For device only applications that do not use the ID signal the ID pin should be connected to VDD33. The block diagram of the ID detection circuitry is shown in Figure5-10 and the related parameters are given in Table4-7. FIGURE 5-10: USB3320 ID RESISTOR DETECTION CIRCUITRY ~~ VDD33 IdPullup M K >1W =100 ID RID RID To USB Con. IdGnd V IdGnd ref en IdGnd Rise or IdGnd Fall IdGndDrv IdFloat V IdFloat ref en IdFloatRise or IdFloatFall RidValue Rid ADC OTG Module ~~ 5.6.1.1 USB OTG Operation The USB3320 can detect ID grounded and ID floating to determine if an A or B cable has been inserted. The A plug will ground the ID pin while the B plug will float the ID pin. These are the only two valid states allowed in the OTG Protocol. To monitor the status of the ID pin, the Link activates the IdPullup bit in the OTG Control register, waits 50mS and then reads the status of the IdGnd bit in the USB Interrupt Status register. If an A cable has been inserted the IdGnd bit will read 0. If a B cable is inserted, the ID pin is floating and the IdGnd bit will read 1. The USB3320 provides an integrated weak pull-up resistor on the ID pin, R . This resistor is present to keep the ID IDW pin in a known state when the IdPullup bit is disabled and the ID pin is floated. In addition to keeping the ID pin in a known state, it enables the USB3320 to generate an interrupt to inform the link when a cable with a resistor to ground has been attached to the ID pin. The weak pull-up is small enough that the largest valid Rid resistor pulls the ID pin low and causes the IdGnd comparator to go low. After the link has detected an ID pin state change, the RID converter can be used to determine the resistor value as described in Section5.6.1.2. DS00001792E-page 26  2014-2016 Microchip Technology Inc.

USB3320 5.6.1.2 Measuring ID Resistance to Ground The Link can used the integrated resistance measurement capabilities to determine the value of an ID resistance to ground. Table5-4 lists the valid values of resistance, to ground, that the USB3320 can detect. TABLE 5-4: VALID VALUES OF ID RESISTANCE TO GROUND ID Resistance to Ground RID Value Ground 000 75Ω +/-1% 001 102kΩ +/-1% 010 200kΩ+/-1% 011 440kΩ +/-1% 100 Floating 101 Note: IdPullUp = 0 The Rid resistance can be read while the USB3320 is in Synchronous Mode. When a resistor to ground is attached to the ID pin, the state of the IdGnd comparator will change. After the Link has detected ID transition to ground, it can use the methods described in Section6.6 to operate the Rid converter. 5.6.1.3 Using IdFloat Comparator Note: The ULPI specification details a method to detect a 102kΩ resistance to ground using the IdFloat compar- ator. This method can only detect 0ohms, 102kΩ, and floating terminations of the ID pin. Due to this limita- tion it is recommended to use the RID Converter as described in Section5.6.1.2. The ID pin can be either grounded, floated, or connected to ground with a 102kΩ external resistor. To detect the 102K resistor, set the idPullup bit in the OTG Control register, causing the USB3320 to apply the 100K internal pull-up con- nected between the ID pin and VDD33. Set the idFloatRise and idFloatFall bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers to enable the IdFloat comparator to generate an RXCMD to the Link when the state of the IdFloat changes. As described in Figure6-3, the alt_int bit of the RXCMD will be set. The values of IdGnd and IdFloat are shown for the three types cables that can attach to the USB Connector in Table5-5. TABLE 5-5: IDGND AND IDFLOAT VS. ID RESISTANCE TO GROUND ID Resistance IDGND IDFLOAT Float 1 1 102K 1 0 GND 0 0 Note: The ULPI register bits IdPullUp, IdFloatRise, and IdFloatFall should be enabled. To save current when an A Plug is inserted, the internal 102kΩ pull-up resistor can be disabled by clearing the IdPullUp bit in the OTG Control register and the IdFloatRise and IdFloatFall bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. If the cable is removed the weak R will pull the ID pin high. IDW The IdGnd value can be read using the ULPI USB Interrupt Status register, bit 4. In host mode, it can be set to generate an interrupt when IdGnd changes by setting the appropriate bits in the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. The IdFloat value can be read by reading the ULPI Carkit Interrupt Status register bit 0. Note: The IdGnd switch has been provided to ground the ID pin for future applications.  2014-2016 Microchip Technology Inc. DS00001792E-page 27

USB3320 5.6.2 VBUS MONITOR AND PULSING The USB3320 includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and SessEnd compar- ators shown in Figure5-11 are fully integrated into the USB3320. These comparators are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from the USB Interrupt Status register. The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the VBUS voltage on the cable is valid. The SessVld comparator is used by the Link when configured as both an A or B device to indicate a ses- sion is requested or valid. Finally the SessEnd comparator is used by the B-device to indicate a USB session has ended. Also included in the VBUS Monitor and Pulsing block are the resistors used for VBUS pulsing in SRP. The resistors used for VBUS pulsing include a pull-down to ground and a pull-up to VDD33. In some applications, voltages much greater than 5.5V may be present at the VBUS pin of the USB connector. The USB3320 includes an overvoltage protection circuit that protects the VBUS pin of the USB3320 from excessive voltages as described in Section5.6.2.6, and shown in Figure5-11. FIGURE 5-11: USB3320 OTG VBUS BLOCK ~~ VDD33 ChrgVbus 0.5V SessEnd en SessEnd Rise or SessEnd Fall U P V R SessValid VBUS VBUS 1.4V Overvoltage To USB Con. RVBUS Protection RVB RVPD VbusValid 4.575V en DischrgVbus VbusValid Rise or VbusValid Fall [0, X] [1, 0] RXCMD VbusValid EXTVBUS (logic 1) [1, 1] IndicatorComplement [UseExternalVbusindicator, IndicatorPassThru] PHY ~~ 5.6.2.1 SessEnd Comparator The SessEnd comparator is designed to trip when VBUS is less than 0.5 volts. When VBUS goes below 0.5 volts the USB session is considered to be ended, and SessEnd will transition from 0 to 1. The SessEnd comparator can be dis- abled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When dis- abled, the SessEnd bit in the USB Interrupt Status register will read 0. The SessEnd comparator trip points are detailed in Table4-7. 5.6.2.2 SessVld Comparator The SessVld comparator is used when the transceiver is configured as both an A and B device. When configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When configured as a B device, SessVld is used to detect the presence of VBUS. The SessVld interrupts can be disabled by clearing this bit in both the USB Inter- DS00001792E-page 28  2014-2016 Microchip Technology Inc.

USB3320 rupt Enable Rising and USB Interrupt Enable Falling registers. When the interrupts are disabled, the SessVld compar- ator is not disabled and its state can be read in the USB Interrupt Status register. The SessVld comparator trip point is detailed in Table4-7. Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device Session Valid comparator. The USB3320 transceiver combines the two comparators into one and uses the narrower threshold range. 5.6.2.3 VbusVld Comparator The final VBUS comparator is the VbusVld comparator. This comparator is only used when the USB3320 is configured as an A-device. In the USB protocol the A-device supplies the VBUS voltage and is responsible to ensure it remains within a specified voltage range. The VbusVld comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, bit 1 of the USB Interrupt Status register will return a 0. The VbusVld comparator trip points are detailed in Table4-7. The internal VbusValid comparator is designed to ensure the VBUS voltage remains above 4.4V. The USB3320 includes the external vbus valid indicator logic as detail in the ULPI Specification. The external vbus valid indicator is tied to a logic one. The decoding of this logic is shown in Table5-6 below. By default this logic is disabled. TABLE 5-6: EXTERNAL VBUS INDICATOR LOGIC Typical Use External Indicator Pass Indicator RXCMD VBUS Valid Application VBus Indicator Thru Complement Encoding Source OTG Device 0 X X Internal VbusVld comparator (Default) 1 1 0 Fixed 1 1 1 1 Fixed 0 1 0 0 Internal VbusVld comparator. 1 0 1 Fixed 0 Standard Host 1 1 0 Fixed 1 1 1 1 Fixed 0 Standard 0 X X Internal VbusVld comparator. This Peripheral information should not be used by the Link. (Note 5-3) Note 5-3 A peripheral should not use VbusVld to begin operation. The peripheral should use SessVld because the internal VbusVld threshold can be above the VBUS voltage required for USB peripheral operation. 5.6.2.4 VBUS Pulsing with Pull-up and Pull-down Resistors In addition to the internal VBUS comparators, the USB3320 also includes the integrated VBUS pull-up and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge the VBUS voltage so that a Ses- sion Request can begin, the USB3320 provides a pull-down resistor from VBUS to Ground. This resistor is controlled by the DischargeVbus bit 3 of the OTG Control register. The pull-up resistor is connected between VBUS and VDD33. This resistor is used to pull VBUS above 2.1 volts so that the A-Device knows that a USB session has been requested. The state of the pull-up resistor is controlled by the bit 4 ChargeVbus of the OTG Control register. The Pull-Up and Pull- Down resistor values are detailed in Table4-7. The internal VBUS Pull-up and Pull-down resistors are designed to include the R external resistor in series. This VBUS external resistor is used by the VBUS Overvoltage protection described below. 5.6.2.5 VBUS Input Impedance The OTG Supplement requires an A-Device that supports Session Request Protocol to have a VBUS input impedance less than 100kΩ and greater the 40kΩ to ground. The USB3320 provides a 75kΩ resistance to ground, R . The R VB VB resistor tolerance is detailed in Table4-7.  2014-2016 Microchip Technology Inc. DS00001792E-page 29

USB3320 5.6.2.6 VBUS Overvoltage Protection The USB3320 provides an integrated overvoltage protection circuit to protect the VBUS pin from excessive voltages that may be present at the USB connector. The overvoltage protection circuit works with an external resistor (R ) by VBUS drawing current across the resistor to reduce the voltage at the VBUS pin. When voltage at the VBUS pin exceeds 5.5V, the Overvoltage Protection block will sink current to ground until VBUS is below 5.5V. The current drops the excess voltage across R and protects the USB3320 VBUS pin. The required VBUS R value is dependent on the operating mode of the USB3320 as shown in Table5-7. VBUS TABLE 5-7: REQUIRED R RESISTOR VALUE VBUS Operating Mode R VBUS Device only 10kΩ ±5% OTG Capable 1kΩ ±5% Host 10kΩ ±5% UseExternalVbusIndicator = 1 The Overvoltage Protection circuit is designed to protect the USB3320 from continuous voltages up to 30V on the R VBUS resistor. The R resistor must be sized to handle the power dissipated across the resistor. The resistor power can be found VBUS using the equation below: 2 Vprotect–5.0 P = -------------------------------------------- RVBUS R VBUS Where: • Vprotect is the VBUS protection required • R is the resistor value, 1kΩ or 10kΩ. VBUS • P is the required power rating of R RVBUS VBUS For example, protecting a peripheral or device only application to 15V would require a 10kΩ R resistor with a power VBUS rating of 0.01W. To protect an OTG product to 15V would require a 1kΩ R resistor with a power rating of 0.1W. VBUS 5.6.3 DRIVING EXTERNAL VBUS The USB3320 monitors VBUS as described in VBUS Monitor and Pulsing. For OTG and Host applications, the system is required to source 5 volts on VBUS. The USB3320 fully supports VBUS power control using an external VBUS switch as shown in Figure8-3. The USB3320 provides an active high control signal, CPEN, that is dedicated to controlling the Vbus supply when configured as an A-Device. CPEN is asserted by setting the DrvVbus or DrvVbusExternal bit of the OTG Control register. To be compatible with Link designs that support both internal and external Vbus supplies the DrvVbus and DrvVbusExternal bits in the OTG Control Register are or’d together. This enables the Link to set either bit to access the external Vbus enable (CPEN). This logic is shown in Figure5-12. DrvVbus and DrvVbusExternal are set to 0 on Power On Reset (POR) as shown in Section7.1.1.7. DS00001792E-page 30  2014-2016 Microchip Technology Inc.

USB3320 FIGURE 5-12: USB3320 DRIVES CONTROL SIGNAL (CPEN) TO EXTERNAL VBUS SWITCH USB Transceiver CPEN VBUS Link Switch DrvVbus Controller DrvVbusExternal +5V EN VBUS 5V RVBUS VBUS IN OUT Supply ULPI CPEN Logic USB Connector VBUS DM DM DP DP 5.7 USB UART Support The USB3320 provides support for the USB UART interface as detailed in the ULPI specification and the former CEA- 936A specification. The USB3320 can be placed in UART Mode using the method described in Section6.5, and the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register. While in UART mode, the Linestate signals cannot be monitored on the DATA[0] and DATA[1] pins. 5.8 USB Charger Detection Support To support the detection and identification of different types of USB chargers the USB3320 provides integrated pull-up resistors, R , on both DP and DM. These pull-up resistors along with the single ended receivers can be used to help CD determine the type of USB charger attached. Reference information on implementing charger detection is provided in Microchip Application Note AN 19.7 - Battery Charging Using Microchip USB Transceivers. TABLE 5-8: USB WEAK PULL-UP ENABLE RESETB DP Pullup Enable DM Pullup Enable 0 0 0 1 ChargerPullupEnableDP ChargerPullupEnableDM Note: ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power Management register. 5.9 USB Audio Support Note: The USB3320 supports “USB Digital Audio” through the USB protocol in ULPI and USB Serial modes described in Section6.0. The USB3320 provides two low resistance analog switches that allow analog audio to be multiplexed over the DP and DM terminals of the USB connector. The audio switches are shown in Figure5.1. The electrical characteristics of the USB Audio Switches are provided in Table4-8.  2014-2016 Microchip Technology Inc. DS00001792E-page 31

USB3320 During normal USB operation the switches are off. When USB Audio is desired the switches can be turned “on” by enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as described in Section6.5.2. These bits are disabled by default. The USB Audio Switches can also be enabled by asserting the RESETB pin or removing the voltage at VDD18 as shown in Table5-9. While using the USB switches, VDD18 is not required, but 3.3V must be present at VDD33. The integrated 3.3V LDO regulator may be used to generate VDD33 from power applied at the VBAT pin. TABLE 5-9: USB AUDIO SWITCH ENABLE RESETB VDD18 DP Switch Enable DM Switch Enable X 0 1 1 0 1 1 1 1 1 SpkLeftEn SpkRightEn or MicEn Note: SpkLeftEn, SpkRightEn, and MicEn are enabled in the Carkit Control register. In addition to USB Audio support the switches can also be used to multiplexed a second FS USB transceiver to the USB connector. The signal quality will be degraded slightly due to the “on” resistance of the switches. The USB3320 single- ended receivers described in Section5.2.1 are disabled when either USB Audio switch is enabled. The USB3320 does not provide the DC bias for the audio signals. The SPK_R and SPK_L pins should be biased to 1.65V when audio signals are routed through the USB3320. This DC bias is necessary to prevent the audio signal from swinging below ground and being clipped by ESD Diodes. When the system is not using the USB Audio switches, the SPK_R and SPK_L pins should not be connected. 5.10 Reference Frequency Selection The USB3320 is configured for the desired reference frequency by the REFSEL[2], REFSEL[1] and REFSEL[0] pins. If a pin is connected to VDDIO, the value of “1” is assigned. Connect the pin to ground to assign a “0.” When using the ULPI Input Clock Mode (60MHz REFCLK Mode), the reference frequency is always fixed at 60 MHz. Eight reference clock frequencies are available as described in Table5-10. TABLE 5-10: CONFIGURATION TO SELECT REFERENCE CLOCK FREQUENCY Configuration Pins Description REFSEL[2] REFSEL[1] REFSEL[0] Reference Frequency 0 0 0 52 MHz 0 0 1 38.4 MHz 0 1 0 12 MHz 0 1 1 27 MHz 1 0 0 13 MHz 1 0 1 19.2 MHz 1 1 0 26 MHz 1 1 1 24 MHz DS00001792E-page 32  2014-2016 Microchip Technology Inc.

USB3320 6.0 ULPI OPERATION 6.1 Overview The USB3320 uses the industry standard ULPI digital interface to facilitate communication between the USB Trans- ceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the number of pins required to con- nect a discrete USB Transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals. The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1”. The following sections describe the operating modes of the USB3320 digital interface. Figure6-1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB3320 does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies. FIGURE 6-1: ULPI DIGITAL BLOCK DIAGRAM USB Transmit and Receive Logic Tx Data HS Tx Data Data[7:0] High Speed TX To TX Full Speed TX FS/LS Tx Data Analog Low Speed TX DIR ULPI Protocol NOTE: NXT The ULPI interface Block is a wrapperless STP Rx Data design. High Speed Data HS RX Data Recovery To RX Full / Low Speed FS/LS Data Analog Data Recovery ol ntr To To USB o er C OTG Audio eiv Analog Analog er Access Transc RMida cShtiantee ULPI RegistULPI InteruptXcvrSelect[1:0]TermSelectOpMode[1:0]ResetDpPulldownDmPulldownSwapDP/DMRegOutput[1:0]TxdEnRxdEn SuspendM6pinSerial Mode3pinSerial ModeClockSuspendMAutoResumeCarkitMode Linestates[1:0]HostDisconnect VbusValidSessionValidSessionEndIdGndIdFloat RidCon...Done RidValue[2:0]RidCon...Start Interface Protect DisableUseExternal Vbus IndicatorIndicator ComplementIndicator Pass ThruDischrgVbusChrgVbusIdGndDrvIdPullUpSpkLeftEnSpkRightEn/MicEnChargerPullupEnDPChargerPullupEnDM Interrupt Control RESETB ULPI Register Array POR The advantage of a “wrapper less” architecture is that the USB3320 has a lower USB latency than a design which must first register signals into the PHY’s wrapper before the transfer to the PHY core. A low latency PHY allows a Link to use a wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification.  2014-2016 Microchip Technology Inc. DS00001792E-page 33

USB3320 RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3320 uses a low latency high speed receiver path to lower the RxEndDelay to 43 high speed clocks. This low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This is the result of the “wrapper less” architecture of the USB3320. This low RxEndDelay should allow legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface. In Figure6-1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The USB3320 is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array. 6.1.1 ULPI INTERFACE SIGNALS The UTIM+ Low Pin Interface (ULPI) uses twelve pins to connect a full OTG Host / Device USB Transceiver to an SOC. A reduction of external pins on the transceiver is accomplished by realizing that many of the relatively static configura- tion pins (xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown DmPulldown to list a few,) can be implemented by having an internal static register array. An 8-bit bi-directional data bus clocked at 60MHz allows the Link to access this internal register array and transfer USB packets to and from the transceiver. The remaining 3 pins function to control the data flow and arbitrate the data bus. Direction of the 8-bit data bus is controlled by the DIR output from the transceiver. Another output, NXT, is used to control data flow into and out of the device. Finally, STP, which is in input to the transceiver, terminates transfers and is used to start up and resume from Low Power Mode. The twelve signals are described below in Table6-1. TABLE 6-1: ULPI INTERFACE SIGNALS Signal Direction Description CLK I/O 60MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of this clock. This clock can be either driven by the transceiver or the Link as described in Section5.4.1 DATA[7:0] I/O 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and transceiver initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of the ULPI clock. DIR OUT Controls the direction of the data bus. When the transceiver has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the transceiver has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The transceiver will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start-up. STP IN The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the transceiver, STP indicates the last byte of data was on the bus in the previous cycle. NXT OUT The transceiver asserts NXT to throttle the data. When the Link is sending data to the transceiver, NXT indicates when the current byte has been accepted by the transceiver. The Link places the next byte on the data bus in the following clock cycle. USB3320 implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on the rising edge of the 60MHz ULPI Clock while operating in Synchronous Mode. The direction of the data bus is determined by the state of DIR. When DIR is high, the transceiver is driving DATA[7:0]. When DIR is low, the Link is driving DATA[7:0]. Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor transceiver drive the data bus for one clock cycle. During the “turn–around“cycle, the state of DATA[7:0] is unknown and the transceiver will not read the data bus. Because USB uses a bit-stuffing encoding, some means of allowing the transceiver to throttle the USB transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the data bus by the Link layer. The ULPI interface supports the two basic modes of operation: Synchronous Mode and asynchronous modes that include Low Power Mode, Serial Modes, and Carkit Mode. In Synchronous Mode, all signals change synchronously with the 60MHz ULPI clock. In asynchronous modes the clock is off and the ULPI bus is redefined to bring out the signals required for that particular mode of operations. The description of synchronous Mode is described in the following sec- tions while the descriptions of the asynchronous modes are described in Section6.3, Section6.4, and Section6.5. DS00001792E-page 34  2014-2016 Microchip Technology Inc.

USB3320 6.1.2 ULPI INTERFACE TIMING IN SYNCHRONOUS MODE The control and data timing relationships are given in Figure6-2 and Table4-3. All timing is relative to the rising clock edge of the 60MHz ULPI Clock. FIGURE 6-2: ULPI SINGLE DATA RATE TIMING DIAGRAM IN SYNCHRONOUS MODE 60MHz ULPI - CLK T T SC HC Control In - STP T T SD HD Data In - DATA[7:0] T T DC DC Control Out - DIR, NXT T DD Data Out - DATA[7:0] 6.2 ULPI Register Access A command from the Link begins a ULPI transfer from the Link to the USB3320. Before reading a ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TXD CMD) byte. The TXD CMD byte informs the USB3320 of the type of data being sent. The TXD CMD is followed by a data transfer to or from the USB3320. Table6- 2 gives the TXD command byte (TXD CMD) encoding for the USB3320. The upper two bits of the TX CMD instruct the transceiver as to what type of packet the Link is transmitting. The ULPI registers retain their contents when the trans- ceiver is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode. TABLE 6-2: ULPI TXD CMD BYTE ENCODING Command Name CMD Bits[7:6] CMD Bits[5:0] Command Description Idle 00b 000000b ULPI Idle Transmit 01b 000000b USB Transmit Packet with No Packet Identifier (NOPID) 00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P P P P where P is the 3 2 1 0 3 MSB. Register Write 10b XXXXXXb Immediate Register Write Command where: DATA[5:0] = 6-bit register address 101111b Extended Register Write Command where the 8-bit register address is available on the next cycle. Register Read 11b XXXXXXb Immediate Register Read Command where: DATA[5:0] = 6-bit register address 101111b Extended Register Read Command where the 8-bit register address is available on the next cycle.  2014-2016 Microchip Technology Inc. DS00001792E-page 35

USB3320 6.2.1 ULPI REGISTER WRITE A ULPI register write operation is given in Figure6-3. The TXD command with a register write DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TXD CMD byte. FIGURE 6-3: ULPI REGISTER WRITE IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD Reg Data[n] Idle (reg write) DIR STP NXT ULPI Register Reg Data [n-1] Reg Data [n] To write a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the data bus. At T2 the transceiver will drive NXT high. On the next rising clock edge, T3, the Link will write the register data. At T4, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the transceiver will latch the data into the register and the Link will pull STP low. NXT is used to control when the Link drives the register data on the bus. DIR is low throughout this transaction since the transceiver is receiving data from the Link. STP is used to end the transaction and data is registered after the de- assertion of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus or the USB3320 may decode the bus value as a ULPI command. A ULPI extended register write operation is shown in Figure6-4. To write an extended register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the data bus. At T2 the transceiver will drive NXT high. On the next clock T3 the Link will drive the extended address. On the next rising clock edge, T4, the Link will write the register data. At T5, the transceiver will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the transceiver will latch the data into the register. The Link will pull STP low. DS00001792E-page 36  2014-2016 Microchip Technology Inc.

USB3320 FIGURE 6-4: ULPI EXTENDED REGISTER WRITE IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] Idle TXD CMD Extended Reg Data[n] Idle (extended reg write) address DIR STP NXT ULPI Register Reg Data [n-1] Reg Data [n] 6.2.2 ULPI REGISTER READ A ULPI register read operation is given in Figure6-5. The Link drives a TXD CMD byte with DATA[7:6] = 11h for a reg- ister read. DATA[5:0] of the ULPI TXD command bye contain the register address. FIGURE 6-5: ULPI REGISTER READ IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD Turn around Reg Data Turn around Idle reg read DIR STP NXT  2014-2016 Microchip Technology Inc. DS00001792E-page 37

USB3320 At T0, the Link will place the TXD CMD on the data bus. At T2, the transceiver will bring NXT high, signaling the Link it is ready to accept the data transfer. At T3, the transceiver reads the TXD CMD, determines it is a register read, and asserts DIR to gain control of the bus. The transceiver will also de-assert NXT. At T4, the bus ownership has transferred back to the transceiver and the transceiver drives the requested register onto the data bus. At T5, the Link will read the data bus and the transceiver will drop DIR low returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. A ULPI extended register read operation is shown in Figure6-6.To read an extended register, the Link writes the TX CMD with the address set to 2Fh. At T2, the transceiver will assert NXT, signaling the Link it is ready to accept the extended address. At T3, the Link places the extended register address on the bus. At T4, the transceiver reads the extended address, and asserts DIR to gain control of the bus. The transceiver will also de-assert NXT. At T5, the bus ownership has transferred back to the transceiver and the transceiver drives the requested register onto the data bus. At T6, the Link will read the data bus and the transceiver will de-assert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. FIGURE 6-6: ULPI EXTENDED REGISTER READ IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] Idle TXD CMD Extended Turn around Reg Data Turn around Idle extended reg read address DIR STP NXT 6.2.3 ULPI RXCMD The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0], rxactive, rxvalid and rxerror. When implementing the OTG functions, the VBUS and ID pin states must also be trans- ferred to the Link. ULPI defines a Receive Command Byte (RXCMD) that contains this information. The Encoding of the RXCMD byte is given in the Table6-3. Transfer of the RXCMD byte occurs in Synchronous Mode when the transceiver has control of the bus. The ULPI Pro- tocol Block shown in Figure6-1 determines when to send an RXCMD. A RXCMD can occur: • When a linestate change occurs. • When VBUS or ID comparators change state. • During a USB receive when NXT is low. • After the USB3320 deasserts DIR and STP is low during start-up • After the USB3320 exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the Link has de- asserted STP, and DIR is low. When a USB Receive is occurring, RXCMD’s are sent whenever NXT = 0 and DIR = 1. During a USB Transmit, the RXCMD’s are returned to the Link after STP is asserted. DS00001792E-page 38  2014-2016 Microchip Technology Inc.

USB3320 If an RXCMD event occurs during a USB transmit, the RXCMD is blocked until STP de-asserts at the end of the transmit. The RXCMD contains the status that is current at the time the RXCMD is sent. TABLE 6-3: ULPI RX CMD ENCODING Data[7:0] Name Description and Value [1:0] Linestate UTMI Linestate Signals Note 6-1 [3:2] Encoded ENCODED VBUS VOLTAGE STATES VBUS State VALUE VBUS VOLTAGE SESSEND SESSVLD VBUSVLD 2 00 V < V 1 0 0 VBUS SESS_END 01 V < V < 0 0 0 SESS_END VBUS V SESS_VLD 10 V < V < X 1 0 SESS_VLD VBUS V VBUS_VLD 11 V < V X X 1 VBUS_VLD VBUS [5:4] Rx Event ENCODED UTMI EVENT SIGNALS Encoding VALUE RXACTIVE RXERROR HOSTDISCONNECT 00 0 0 0 01 1 0 0 11 1 1 0 10 X X 1 [6] State of ID Set to the logic state of the ID pin. A logic low indicates an A device. A logic high pin indicates a B device. [7] alt_int Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit Interrupt Latch register to determine the source of the interrupt. Section5.6.1.3 describes how a change on the ID pin can generate an interrupt. Section6.6 describes how an interrupt can be generated when the RidConversionDone bit is set. Note1: An ‘X’ is a do not care and can be either a logic 0 or 1. 2: The value of VbusValid is defined in Table5-6. Note 6-1 LineState: These bits in the RXCMD byte reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1). 6.2.4 USB3320 TRANSMITTER The USB3320 ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure6-1 shows the high speed, full speed, and low speed transmitter block controlled by ULPI Protocol Block. Encoding of the USB packet follows the bit- stuffing and NRZI outlined in the USB 2.0 specification. Many of these functions are re-used between the HS and FS/LS transmitters. When using the USB3320, Table5-1 should always be used as a guideline on how to configure for various modes of operation. The transmitter decodes the inputs of XcvrSelect[1:0], TermSelect, OpMode[1:0], DpPulldown, and DmPulldown to determine what operation is expected. Users must strictly adhere to the modes of operation given in Table5-1. Several important functions for a device and host are designed into the transmitter blocks. The USB3320 transmitter will transmit a 32-bit long high speed sync before every high speed packet. In full and low speed modes a 8-bit sync is transmitted. When the device or host needs to chirp for high speed port negotiation, the OpMode = 10b setting in the Function Con- trol register will turn off the bit-stuffing and NRZI encoding in the transmitter. At the end of a chirp, the USB3320 OpMode bits should be changed only after the RXCMD linestate encoding indicates that the transmitter has completed transmit- ting. Should the opmode be switched to normal bit-stuffing and NRZI encoding before the transmit pipeline is empty, the remaining data in the pipeline may be transmitted in an bit-stuff encoding format. Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp.  2014-2016 Microchip Technology Inc. DS00001792E-page 39

USB3320 6.2.4.1 High Speed Long EOP When operating as a Hi-Speed host, the USB3320 will automatically generate a 40 bit long End of Packet (EOP) after a SOF PID (A5h). The USB3320 determines when to send the 40-bit long EOP by decoding the ULPI TXD CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the DpPulldown and DmPulldown bits in the OTG Con- trol register are asserted. The Hi-Speed 40-bit long EOP is used to detect a disconnect in high speed mode. In device mode, the USB3320 will not send a long EOP after a SOF PID. 6.2.4.2 Low Speed Keep-Alive Low speed keep alive is supported by the USB3320. When in Low speed (XcvrSelect = 10b in the Function Control register), the USB3320 will send out two Low speed bit times of SE0 when a SOF PID is received. 6.2.4.3 UTMI+ Level 3 Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect = 11b in the Function Control register in host mode (DpPulldown and DmPulldown both asserted), the USB3320 will pre-pend a full speed pre-amble before the low speed packet. Full speed rise and fall times are used in this mode. The pre-amble consists of the following: Full speed sync, the encoded pre-PID (C3h) and then full speed idle (DP=1 and DM = 0). A low speed packet follows with a sync, data and a LS EOP. The USB3320 will only support UTMI+ Level 3 as a host. The USB3320 does not support UTMI+ Level 3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB3320 will not decode a pre-amble packet intended for a LS device when the USB3320 is configured as the upstream port of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b. 6.2.4.4 Host Resume K Resume K generation is supported by the USB3320. When the USB3320 exits the suspended (Low Power Mode), the USB3320, when operating as a host, will transmit a K on DP/DM. The transmitters will end the K with SE0 for two Low Speed bit times. If the USB3320 was operating in high speed mode before the suspend, the host must change to high speed mode before the SE0 ends. SE0 is two low speed bit times which is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of the USB Specification. In device mode, the resume K will not append an SE0, but release the bus to the correct idle state, depending upon the operational mode as shown in Table5-1. The ULPI specification includes a detailed discussion of the resume sequence and the order of operations required. To support Host start-up of less than 1mS the USB3320 implements the ULPI AutoResume bit in the Interface Control reg- ister. The default AutoResume state is 0 and this bit should be enabled for Host applications. 6.2.4.5 No SYNC and EOP Generation (OpMode = 11) UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This is an option to the ULPI specification and not implemented in the USB3320. 6.2.4.6 Typical USB Transmit with ULPI Figure6-7 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a TXD CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID is followed by transmit data. DS00001792E-page 40  2014-2016 Microchip Technology Inc.

USB3320 FIGURE 6-7: ULPI TRANSMIT IN SYNCHRONOUS MODE CLK DATA[7:0] Idle T(XUDS BC MtxD) D0 D1 D2 D3 IDLE ATrouurnn d CRMXDD ATrouurnn d DIR NXT STP DP/DM SE0 !SQUELCH SE0 During transmit the transceiver will use NXT to control the rate of data flow into the transceiver. If the USB3320 pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP while NXT is asserted. Note: The Link cannot assert STP with NXT de-asserted since the USB3320 is expecting to fetch another byte from the Link. After the USB3320 completes transmitting, the DP and DM lines return to idle and a RXCMD is returned to the Link so the inter-packet timers may be updated by linestate. While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for approximately two bit times, followed by J for one bit time. The transceiver drives a J state for one bit time following the SE0 to complete the EOP. The Link must wait for one bit time following line state indication of the SE0 to J transition to allow the transceiver to complete the one bit time J state. All bit times are relative to the speed of transmission. In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate a RXCMD since the bit times are relatively slow. 6.2.5 USB RECEIVER The USB3320 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority and will immediately follow register reads and RXCMD transfers. Figure6-8 shows a basic USB packet received by the USB3320 over the ULPI interface.  2014-2016 Microchip Technology Inc. DS00001792E-page 41

USB3320 FIGURE 6-8: ULPI RECEIVE IN SYNCHRONOUS MODE CLK DATA[7:0] Idle Turn Rxd PID D1 Rxd D2 Turn around Cmd Cmd around DIR STP NXT In Figure6-8 the transceiver asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link. After the last byte of the USB receive packet is transferred to the transceiver, the linestate will return to idle. The ULPI full speed receiver operates according to the UTMI / ULPI specification. In the full speed case, the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is low with DIR high, the RXCMD is driven on the data bus. In full speed, the USB3320 will not issue a Rxactive de-assertion in the RXCMD until the DP/DM linestate transitions to idle. This prevents the Link from violating the two full speed bit times minimum turn around time. 6.2.5.1 Disconnect Detection A High Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP transmitted during a SOF packet. The USB3320 only looks for a high speed disconnect during the long EOP where the period is long enough for the disconnect reflection to return to the host transceiver. When a high speed disconnect occurs, the USB3320 will return a RXCMD and set the host disconnect bit in the USB Interrupt Status register. When in FS or LS modes, the Link is expected to handle all disconnect detection. 6.3 Low Power Mode Low Power Mode is a power down state to save current when the USB session is suspended. The Link controls when the transceiver is placed into or out of Low Power Mode. In Low Power Mode all of the circuits are powered down except the interface pins, full speed receiver, VBUS comparators, and IdGnd comparator. Before entering Low Power Mode, the USB3320 must be configured to set the desired state of the USB transceiver. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPull- down bits in the OTG Control register control the configuration as shown in Table5-1. The DP and DM pins are config- ured to a high impedance state by configuring OpMode[1:0] = 01. Pull-down resistors with a value of approximately 2MΩ are present on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to float. 6.3.1 ENTERING LOW POWER/SUSPEND MODE To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control register. After this write is complete, the transceiver will assert DIR high and after a minimum of five rising edges of CLKOUT, drive the clock low. After the clock is stopped, the transceiver will enter a low power state to conserve current. Placing the trans- ceiver in Suspend Mode is not related to USB Suspend. To clarify this point, USB Suspend is initiated when a USB host DS00001792E-page 42  2014-2016 Microchip Technology Inc.

USB3320 stops data transmissions and enters Full-Speed mode with 15KΩ pull-down resistors on DP and DM. The suspended device goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one of them drives DM high (this is called a resume). FIGURE 6-9: ENTERING LOW POWER MODE FROM SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T10 ... CLK DATA[7:0] Idle TXD CMD Reg Data[n] Idle Turn Low Power Mode (reg write) Around DIR STP NXT SUSPENDM (ULPI Register Bit) While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table6-4. Linestate[1:0] is the combinational output of the Single-Ended Receivers. The “int” or interrupt signal indicates an unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the Link is notified and can determine if it should wake-up the transceiver. TABLE 6-4: INTERFACE SIGNAL MAPPING DURING LOW POWER MODE Signal Maps to Direction Description linestate[0] DATA[0] OUT Combinatorial LineState[0] driven directly by the Full-Speed single ended receiver. Note 6-2 linestate[1] DATA[1] OUT Combinatorial LineState[1] driven directly by the Full-Speed single ended receiver. Note 6-2 reserved DATA[2] OUT Driven Low int DATA[3] OUT Active high interrupt indication. Must be asserted whenever any unmasked interrupt occurs. reserved DATA[7:4] OUT Driven Low Note 6-2 LineState: These signals reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1). An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld, SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3] will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts masked to lower the suspend current as described in Section6.3.4. While in Low Power Mode, the Data bus is driven asynchronously because all of the transceiver clocks are stopped during Low Power Mode.  2014-2016 Microchip Technology Inc. DS00001792E-page 43

USB3320 6.3.2 EXITING LOW POWER MODE To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3320 will begin its start-up pro- cedure. After the transceiver start-up is complete, the transceiver will start the clock on CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode. The transceiver will automatically set the SuspendM bit to a 1 in the Function Control register. FIGURE 6-10: EXITING LOW POWER MODE T0 T1 T2 T3 T4 T5 ... CLK DATA[7:0] LOW TURN DATA BUS IGNORED (SLOW LINK) IDLE POWER MODE AROUND IDLE (FAST LINK) Slow Link Drives Bus Fast Link Drives Bus Idle and STP low DIR Idle and STP low STP Note: Not to Scale T START The value for T is given in Table4-2. START Should the Link de-assert STP before DIR is de-asserted, the USB3320 will detect this as a false resume request and return to Low Power Mode. This is detailed in section 3.9.4 of the ULPI 1.1 specification. 6.3.3 INTERFACE PROTECTION ULPI protocol assumes that both the Link and transceiver will keep the ULPI data bus driven by either the Link when DIR is low or the transceiver when DIR is high. The only exception is when DIR has changed state and a turn around cycle occurs for 1 clock period. In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus to a known state while DIR is low. Two examples where this can happen is because of a slow Link start-up or a hardware reset. 6.3.3.1 Start up Protection Upon start-up, when the transceiver de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STP before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up. If the Link doesn’t assert STP before it can receive com- mands, the transceiver may interpret the data bus state as a TX CMD and transmit invalid data onto the USB bus, or make invalid register writes. When the USB3320 sends a RXCMD the Link is required to drive the data bus back to idle at the end of the turn around cycle. If the Link does not drive the databus to idle the USB3320 may take the information on the data bus as a TXCMD and transmit data on DP and DM until the Link asserts stop. If the ID pin is floated the last RXCMD from the USB3320 will remain on the bus after DIR is de-asserted and the USB3320 will take this in as a TXCMD. A Link should be designed to have the default POR state of the STP output high and the data bus tri-stated. The USB3320 has weak pull-downs on the data bus to prevent these inputs from floating when not driven. These resistors are only used to prevent the ULPI interface from floating during events when the link ULPI pins may be tri-stated. The strength of the pull down resistors can be found in Table4-4. The pull downs are not strong enough to pull the data bus low after a ULPI RXCMD, the Link must drive the data bus to idle after DIR is de-asserted. DS00001792E-page 44  2014-2016 Microchip Technology Inc.

USB3320 In some cases, a Link may be software configured and not have control of its STP pin until after the transceiver has started. In this case, the USB3320 has in internal pull-up on the STP input pad which will pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfacePro- tectDisable bit 7 of the Interface Control register. The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP high. After the Link completes its start-up, STP can be synchronously driven low. A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtect- Disable bit to 1. A motivation for this is to reduce the suspend current. In Low Power Mode, STP is held low, which would draw current through the pull-up resistor on STP. 6.3.3.2 Warm Reset Designers should also consider the case of a warm restart of a Link with a transceiver in Low Power Mode. After the transceiver enters Low Power Mode, DIR is asserted and the clock is stopped. The USB3320 looks for STP to be asserted to re-start the clock and then resume normal synchronous operation. Should the USB3320 be suspended in Low Power Mode, and the Link receives a hardware reset, the transceiver must be able to recover from Low Power Mode and start its clock. If the Link asserts STP on reset, the transceiver will exit Low Power Mode and start its clock. If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link is reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the transceiver to restart its clock. 6.3.4 MINIMIZING CURRENT IN LOW POWER MODE In order to minimize the suspend current in Low Power Mode, the OTG comparators can be disabled to reduce suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are not needed and can be disabled by clearing the associated bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. By disabling the interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and IdFloatFall bits in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG functionality is required. In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the Interface Protect Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register, the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled. 6.4 Full Speed/Low Speed Serial Modes The USB3320 includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the Interface control register. Serial Mode may be used to conserve power when attached to a device that is not capable of operating in Hi-Speed. The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes the Interface Control register bit for the specific serial mode. The USB3320 will assert DIR and shut off the clock after at least five clock cycles. Then the data bus goes to the format of the serial mode selected. Before entering Serial Mode the Link must set the ULPI transceiver to the appropriate mode as defined in Table5-1. In ULPI Output Clock Mode, the transceiver will shut off the 60MHz clock to conserve power. Should the Link need the 60MHz clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface Control Register should be set before entering a serial mode. If set, the 60 MHz clock will be present during serial modes. In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal the transceiver to exit serial mode. When the transceiver can accept a command, DIR is de-asserted and the transceiver will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous Mode.  2014-2016 Microchip Technology Inc. DS00001792E-page 45

USB3320 6.4.1 3PIN FS/LS SERIAL MODE Three pin serial mode utilizes the data bus pins for the serial functions shown in Table6-5. TABLE 6-5: PIN DEFINITIONS IN 3 PIN SERIAL MODE Signal Connected To Direction Description tx_enable DATA[0] IN Active High transmit enable. data DATA[1] I/O TX differential data on DP/DM when tx_enable is high. RX differential data from DP/DM when tx_enable is low. SE0 DATA[2] I/O TX SE0 on DP/DM when tx_enable is high. RX SE0_b from DP/DM when tx_enable is low. interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. Reserved DATA[7:4] OUT Driven Low. 6.4.2 6PIN FS/LS SERIAL MODE Six pin serial mode utilizes the data bus pins for the serial functions shown in Table6-6. TABLE 6-6: PIN DEFINITIONS IN 6 PIN SERIAL MODE Signal Connected To Direction Description tx_enable DATA[0] IN Active High transmit enable. tx_data DATA[1] IN Tx differential data on DP/DM when tx_enable is high. tx_se0 DATA[2] IN Tx SE0 on DP/DM when tx_enable is high. interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. rx_dp DATA[4] OUT Single ended receive data on DP. rx_dm DATA[5] OUT Single ended receive data on DM. rx_rcv DATA[6] OUT Differential receive data from DP and DM. Reserved DATA[7] OUT Driven Low. 6.5 Carkit Mode The USB3320 includes Carkit Mode to support a USB UART and USB Audio Mode. By entering Carkit Mode, the USB3320 current drain is minimized. When operating in ULPI Input Clock Mode (60MHz REFCLK Mode), the CLKOUT is stopped to conserve power by default. The Link may configure the 60MHz clock to continue by setting the ClockSuspendM bit of the Interface Control register before entering Carkit Mode. If set, the 60 MHz clock will continue during the Carkit Mode of operation. In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. In Carkit Mode, the Linestate signals are not available per the ULPI specification. Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section6.3.2. The Link must assert STP to signal the transceiver to exit serial mode. When the transceiver can accept a command, DIR is de-asserted and the transceiver will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous Mode. 6.5.1 USB UART MODE The USB3320 can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn and RxdEn bits must be written before the CarkitMode bit. DS00001792E-page 46  2014-2016 Microchip Technology Inc.

USB3320 TABLE 6-7: ULPI REGISTER PROGRAMMING EXAMPLE TO ENTER UART MODE Address Value R/W Description Result (HEX) (HEX) W 04 49 Configure Non-Driving mode OpMode=01 Select FS transmit edge rates XcvrSelect=01 W 39 00 Set regulator to 3.3V UART RegOutput=00 W 19 0C Enable UART connections RxdEn=1 TxdEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table6-8, and the USB3320 will transmit data through the DATA[0] to DM of the USB connector and receive data on DP and pass the information the Link on DATA[1]. When entering UART mode, the regulator output will automatically switch to the value configured by the UART RegOut- put bits in the USB IO & Power Management register and a pull-up will be applied internally to DP and DM. This will hold the UART in its default operating state. While in UART mode, the transmit edge rates can be set to either the Full Speed USB or Low Speed USB edge rates by using the XcvrSelect[1:0] bits in the Function Control register. TABLE 6-8: PIN DEFINITIONS IN CARKIT MODE Signal Connected To Direction Description txd DATA[0] IN UART TXD signal that is routed to the DM pin if the TxdEn is set in the Carkit Control register. rxd DATA[1] OUT UART RXD signal that is routed to the DP pin if the RxdEn bit is set in the Carkit Control register. reserved DATA[2] OUT Driven Low. int DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. reserved DATA[4:7] OUT Driven Low. 6.5.2 USB AUDIO MODE When the USB3320 is powered in Synchronous Mode, the Audio switches can be enabled by asserting the SpkLeftEn, or SpkRightEn bits in the Carkit Control register. After the register write is complete, the USB3320 will immediately enable or disable the audio switch. Then the Link can set the CarkitMode bit in the Interface Control register. The SpkLeftEn, or SpkRightEn bits must be written before the CarkitMode bit. TABLE 6-9: ULPI REGISTER PROGRAMMING EXAMPLE TO ENTER AUDIO MODE Address Value R/W Description Result (HEX) (HEX) W 04 48 Configure Non-Driving mode OpMode=01 W 19 30 Enable Audio connections SpkrRightEn=1, SpkrLeftEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table6-8. 6.6 RID Converter Operation The RID converter is designed to read the value of the ID resistance to ground and report back its value through the ULPI interface. When a resistor to ground is applied to the ID pin the state of the IdGnd comparator will change from a 1 to a 0 as described in Section5.6.1. If the USB3320 is in ULPI mode, an RXCMD will be generated with bit 6 low. If the USB3320 is in Low Power Mode (or one of the other non-ULPI modes), the DATA[3] interrupt signal will go high.  2014-2016 Microchip Technology Inc. DS00001792E-page 47

USB3320 After the USB3320 has detected the change of state on the ID pin, the RID converter can be used to determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart bit is set in the Vendor Rid Conversion register. The Link can use one of two methods to determine when the RID Conversion is complete. One method is polling the RidConversionStart bit as described in Section7.1.3.3. The preferred method is to set the RidIntEn bit in the Vendor Rid Conversion register. When RidIntEn is set, an RXCMD will be generated after the RID conversion is complete. As described in Table6-3, the alt_int bit of the RXCMD will be set. After the RID Conversion is complete, the Link can read RidValue from the Vendor Rid Conversion register. 6.7 Headset Audio Mode This mode is designed to allow a user to view the status of several signals while using an analog audio headset with a USB connector. This feature, exclusive to Microchip, is provided as an alternate mode to the CarKit Mode defined in Section6.5. In the CarKit Mode, the Link is unable to view the source of the interrupt on ID, except by returning to syn- chronous mode to read the ULPI registers. This forces the audio switches to be deactivated, and may glitch the audio signals. In addition, the Link cannot change the resistance on the ID pin without starting up the PHY to access the ULPI registers. The Headset Audio Mode is entered by writing to the Headset Audio Mode register, and allows the Link access to the state of the VBUS and ID pins during audio without glitching the audio connection. The Headset Audio mode also enables the Link to change the resistance on the ID pin and to change the audio headset attached from mono to stereo. The ULPI interface is redefined as shown in Table6-10 when Headset Audio Mode is entered. TABLE 6-10: PIN DEFINITIONS IN HEADSET AUDIO MODE Signal Connected To Direction Description SessVld DATA[0] OUT Output of SessVld comparator VbusVld DATA[1] OUT Output of VbusVld Comparator (interrupt must be enabled) IdGndDrv DATA[2] IN Drives ID pin to ground when asserted 0b: Not connected 1b: Connects ID to ground. DATA[3] OUT Driven low IdGround DATA[4] OUT Asserted when the ID pin is grounded. 0b: ID pin is grounded 1b: ID pin is floating IdFloat DATA[5] OUT Asserted when the ID pin is floating. IdPullup or d_pullup330 must be enabled as shown below. IdPullup330 DATA[6] IN When enabled a 330kΩpullup is applied to the ID pin. This bit will also change the trip point of the IdGnd comparator to the value shown in Table4-7. 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor IdPullup DATA[7] IN Connects the 100kΩ pull-up resistor from the ID pin to VDD3.3 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor Exiting Headset Audio Mode is the same as exiting Low Power Mode as described in Section6.3.2. The Link must assert STP to signal the PHY to exit. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous Mode. DS00001792E-page 48  2014-2016 Microchip Technology Inc.

USB3320 7.0 ULPI REGISTER MAP 7.1 ULPI Register Array The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The com- plete USB3320 ULPI register set is shown in Table7-1. All registers are 8 bits. This table also includes the default state of each register upon POR or de-assertion of RESETB, as described in Section5.5.2. The RESET bit in the Function Control Register does not reset the bits of the ULPI register array. The Link should not read or write to any registers not listed in this table. The USB3320 supports extended register access. The immediate register set (00-3Fh) can be accessed through either a immediate address or an extended register address. TABLE 7-1: ULPI REGISTER MAP Address (6bit) Default Register Name State Read Write Set Clear Vendor ID Low 24h 00h - - - Vendor ID High 04h 01h - - - Product ID Low 07h 02h - - - Product ID High 00h 03h - - - Function Control 41h 04-06h 04h 05h 06h Interface Control 00h 07-09h 07h 08h 09h OTG Control 06h 0A-0Ch 0Ah 0Bh 0Ch USB Interrupt Enable Rising 1Fh 0D-0Fh 0Dh 0Eh 0Fh USB Interrupt Enable Falling 1Fh 10-12h 10h 11h 12h USB Interrupt Status (Note 7-1) 00h 13h - - - USB Interrupt Latch 00h 14h - - - Debug 00h 15h - - - Scratch Register 00h 16-18h 16h 17h 18h Carkit Control 00h 19-1Bh 19h 1Ah 1Bh Reserved 00h 1Ch Carkit Interrupt Enable 00h 1D-1Fh 1Dh 1Eh 1Fh Carkit Interrupt Status 00h 20h - - - Carkit Interrupt Latch 00h 21h - - - Reserved 00h 22-30h HS TX Boost 00h 31h 31h - - Reserved 00h 32h 32h - - Headset Audio Mode 00h 33h 33h - - Reserved 00h 34-35h Vendor Rid Conversion 00h 36-38h 36h 37h 38h USB IO & Power Management 04h 39-3Bh 39h 3Ah 3Bh Reserved 00h 3C-3Fh Note 7-1 Dynamically updates to reflect current status of interrupt sources.  2014-2016 Microchip Technology Inc. DS00001792E-page 49

USB3320 7.1.1 ULPI REGISTER SET The following registers are used for the ULPI interface. 7.1.1.1 Vendor ID Low Address = 00h (read only) Field Name Bit Access Default Description Vendor ID Low 7:0 rd 24h Microchip Vendor ID 7.1.1.2 Vendor ID High Address = 01h (read only) Field Name Bit Access Default Description Vendor ID High 7:0 rd 04h Microchip Vendor ID 7.1.1.3 Product ID Low Address = 02h (read only) Field Name Bit Access Default Description Product ID Low 7:0 rd 07h Microchip Product ID 7.1.1.4 Product ID High Address = 03h (read only) Field Name Bit Access Default Description Product ID High 7:0 rd 00h Microchip Product ID 7.1.1.5 Function Control Address = 04-06h (read), 04h (write), 05h (set), 06h (clear) Field Name Bit Access Default Description XcvrSelect[1:0] 1:0 rd/w/s/c 01b Selects the required transceiver speed. 00b: Enables HS transceiver 01b: Enables FS transceiver 10b: Enables LS transceiver 11b: Enables FS transceiver for LS packets (FS preamble automatically pre-pended) TermSelect 2 rd/w/s/c 0b Controls the DP and DM termination depending on XcvrSelect, OpMode, DpPulldown, and DmPulldown. The DP and DM termination is detailed in Table5-1. OpMode 4:3 rd/w/s/c 00b Selects the required bit encoding style during transmit. 00b: Normal Operation 01b: Non-Driving 10b: Disable bit-stuff and NRZI encoding 11b: Reserved Reset 5 rd/w/s/c 0b Active high transceiver reset. This reset does not reset the ULPI interface or register set. Automatically clears after reset is complete. DS00001792E-page 50  2014-2016 Microchip Technology Inc.

USB3320 Field Name Bit Access Default Description SuspendM 6 rd/w/s/c 1b Active low PHY suspend. When cleared the transceiver will enter Low Power Mode as detailed in Section6.3. Automatically set when exiting Low Power Mode. Reserved 7 rd 0b Read only, 0. 7.1.1.6 Interface Control Address = 07-09h (read), 07h (write), 08h (set), 09h (clear) Field Name Bit Access Default Description 6-pin FsLsSerialMode 0 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 6-pin Serial Mode. The transceiver will automatically clear this bit when exiting serial mode. 3-pin FsLsSerialMode 1 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 3-pin Serial Mode. The transceiver will automatically clear this bit when exiting serial mode. CarkitMode 2 rd/w/s/c 0b When asserted the ULPI interface is redefined to the Carkit interface. The transceiver will automatically clear this bit when exiting Carkit Mode. ClockSuspendM 3 rd/w/s/c 0b Enables Link to turn on 60MHz CLKOUT in Serial Mode or Carkit Mode. 0b: Disable clock in serial or Carkit Mode. 1b: Enable clock in serial or Carkit Mode. AutoResume 4 rd/w/s/c 0b Only applicable in Host mode. Enables the transceiver to automatically transmit resume signaling. This function is detailed in Section6.2.4.4. IndicatorComplement 5 rd/w/s/c 0b Inverts the EXTVBUS signal. This function is detailed in Section5.6.2. Note: The EXTVBUS signal is always high on the USB3320. IndicatorPassThru 6 rd/w/s/c 0b Disables and’ing the internal VBUS comparator with the EXTVBUS signal when asserted. This function is detailed in Section5.6.2. Note: The EXTVBUS signal is always high on the USB3320. InterfaceProtectDisable 7 rd/w/s/c 0b Used to disable the integrated STP pull-up resistor used for interface protection. This function is detailed in Section6.3.3. 7.1.1.7 OTG Control Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear) Field Name Bit Access Default Description IdPullup 0 rd/w/s/c 0b Connects a 100kΩ pull-up resistor from the ID pin to VDD33 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor DpPulldown 1 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DP. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected DmPulldown 2 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DM. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected  2014-2016 Microchip Technology Inc. DS00001792E-page 51

USB3320 Field Name Bit Access Default Description DischrgVbus 3 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to ground to discharge VBUS. 0b: disconnect resistor from VBUS to ground 1b: connect resistor from VBUS to ground ChrgVbus 4 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to VDD33 to charge VBUS above the SessValid threshold. 0b: disconnect resistor from VBUS to VDD33 1b: connect resistor from VBUS to VDD33 DrvVbus 5 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbusExternal. 0b: Do not drive Vbus, CPEN driven low. 1b: Drive Vbus, CPEN driven high. DrvVbusExternal 6 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbus. 0b: Do not drive Vbus, CPEN driven low. 1b: Drive Vbus, CPEN driven high. UseExternalVbus 7 rd/w/s/c 0b Tells the transceiver to use an external VBUS over- Indicator current or voltage indicator. This function is detailed in Section5.6.2. 0b: Use the internal VbusValid comparator 1b: Use the EXTVBUS input as for VbusValid signal. Note: The EXTVBUS signal is always high on the USB3320. 7.1.1.8 USB Interrupt Enable Rising Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear) Field Name Bit Access Default Description HostDisconnect Rise 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode. VbusValid Rise 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from low to high. SessValid Rise 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from low to high. SessEnd Rise 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from low to high. IdGnd Rise 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from low to high. Reserved 7:5 rd 000b Read only, 0. 7.1.1.9 USB Interrupt Enable Falling Address = 10-12h (read), 10h (write), 11h (set), 12h (clear) Field Name Bit Access Default Description HostDisconnect Fall 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode. VbusValid Fall 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from high to low. SessValid Fall 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from high to low. DS00001792E-page 52  2014-2016 Microchip Technology Inc.

USB3320 Field Name Bit Access Default Description SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from high to low. IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 rd 000b Read only, 0. 7.1.1.10 USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. Field Name Bit Access Default Description HostDisconnect 0 0b Current value of the UTMI+ Hi-Speed Hostdisconnect rd output. Applicable only in host mode. VbusValid 1 rd 0b Current value of the UTMI+ Vbusvalid output. SessValid 2 rd 0b Current value of the UTMI+ SessValid output. SessEnd 3 rd 0b Current value of the UTMI+ SessEnd output. IdGnd 4 rd 0b Current value of the UTMI+ IdGnd output. Reserved 7:5 rd 000b Read only, 0. Note: The default conditions will match the current status of the comparators. The values shown are for an unat- tached OTG device. 7.1.1.11 USB Interrupt Latch Address = 14h (read only with auto clear) Field Name Bit Access Default Description HostDisconnect Latch 0 0b Set to 1b by the transceiver when an unmasked event rd occurs on Hostdisconnect. Cleared when this register (Note 7-2) is read. Applicable only in host mode. VbusValid Latch 1 0b Set to 1b by the transceiver when an unmasked event rd occurs on VbusValid. Cleared when this register is (Note 7-2) read. SessValid Latch 2 0b Set to 1b by the transceiver when an unmasked event rd occurs on SessValid. Cleared when this register is (Note 7-2) read. SessEnd Latch 3 rd 0b Set to 1b by the transceiver when an unmasked event (Note 7-2) occurs on SessEnd. Cleared when this register is read. IdGnd Latch 4 rd 0b Set to 1b by the transceiver when an unmasked event (Note 7-2) occurs on IdGnd. Cleared when this register is read. Reserved 7:5 rd 000b Read only, 0. Note 7-2 rd: Read Only with auto clear. 7.1.1.12 Debug Address = 15h (read only) Field Name Bit Access Default Description Linestate0 0 rd 0b Contains the current value of Linestate[0]. Linestate1 1 rd 0b Contains the current value of Linestate[1]. Reserved 7:2 rd 000000b Read only, 0.  2014-2016 Microchip Technology Inc. DS00001792E-page 53

USB3320 7.1.1.13 Scratch Register Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) Field Name Bit Access Default Description Scratch 7:0 rd/w/s/c 00h Empty register byte for testing purposes. Software can read, write, set, and clear this register and the transceiver functionality will not be affected. 7.1.2 CARKIT CONTROL REGISTERS The following registers are used to set-up and enable the USB UART and USB Audio functions. 7.1.2.1 Carkit Control Address = 19-1Bh (read), 19h (write), 1Ah (set), 1Bh (clear) This register is used to program the USB3320 into and out of the Carkit Mode. When entering the UART mode the Link must first set the desired TxdEn and the RxdEn bits and then transition to Carkit Mode by setting the CarkitMode bit in the Interface Control Register. When RxdEn is not set then the DATA[1] pin is held to a logic high. Field Name Bit Access Default Description CarkitPwr 0 rd 0b Read only, 0. IdGndDrv 1 rd/w/s/c 0b Drives ID pin to ground TxdEn 2 rd/w/s/c 0b Connects UART TXD (DATA[0]) to DM RxdEn 3 rd/w/s/c 0b Connects UART RXD (DATA[1]) to DP SpkLeftEn 4 rd/w/s/c 0b Connects DM pin to SPK_L pin SpkRightEn 5 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. MicEn 6 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. Reserved 7 rd 0b Read only, 0. Note: If SpkRightEn or MicEn are asserted the DP pin will be connected to SPK_R. To disconnect the DP pin from the SPK_R pin both SpkrRightEn and MicEn must be set to de-asserted. If using USB UART mode the UART data will appear at the SPK_L and SPK_R pins if the corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled. If using USB Audio the TxdEn and RxdEn bits should not be set when the SpkLeftEn, SpkRightEn, or MicEn switches are enabled. The USB single-ended receivers described in Section5.2.1 are disabled when either SpkLeftEn, SpkRightEn, or MicEn are set. 7.1.2.2 Carkit Interrupt Enable Address = 1D-1Fh (read), 1Dh (write), 1Eh (set), 1Fh (clear) Field Name Bit Access Default Description IdFloatRise 0 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from non-floating to floating. The IdPullup bit in the OTG Control register should be set. IdFloatFall 1 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from floating to non-floating. The IdPullup bit in the OTG Control register should be set. CarIntDet 2 rd 0b Not Implemented. Reads as 0b. CarDpRise 3 rd 0b Not Implemented. Reads as 0b. CarDpFall 4 rd 0b Not Implemented. Reads as 0b. DS00001792E-page 54  2014-2016 Microchip Technology Inc.

USB3320 Field Name Bit Access Default Description RidIntEn 5 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or’ed with the RidIntEn bit of the Vendor Rid Conversion register described in Section7.1.3.3. Reserved 7:6 rd 00b Read only, 0. 7.1.2.3 Carkit Interrupt Status Address = 20h (read only) Field Name Bit Access Default Description IdFloat 0 rd 0b Asserted when the ID pin is floating. IdPullup must be enabled. CarIntDet 1 rd 0b Not Implemented. Reads as 0b. CarDp 2 rd 0b Not Implemented. Reads as 0b. RidValue 5:3 rd 000b Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 102K ohms 011: 200K ohms 100: 440K ohms 101: ID floating 111: Error Note: RidValue can also be read from the Vendor Rid Conversion register described in Section7.1.3.3. RidConversionDone 6 rd 0b Automatically asserted by the USB3320 when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status register will not clear either RidConversionDone status bit. Note: RidConversionDone can also be read from the Vendor Rid Conversion register described in Section7.1.3.3. Reserved 7 rd 0b Read only, 0. 7.1.2.4 Carkit Interrupt Latch Address = 21h (read only with auto-clear) Field Name Bit Access Default Description IdFloat Latch 0 rd (Note 7- 0b Asserted if the state of the ID pin changes from non- 3) floating to floating while the IdFloatRise bit is enabled or if the state of the ID pin changes from floating to non-floating while the IdFloatFall bit is enabled. CarIntDet Latch 1 rd 0b Not Implemented. Reads as 0b. CarDp Latch 2 rd 0b Not Implemented. Reads as 0b. RidConversionLatch 3 rd 0b If RidIntEn is set and the state of the (Note 7-3) RidConversionDone bit changes from a 0 to 1 this bit will be asserted. Reserved 7:4 rd 0000b Read only, 0. Note 7-3 rd: Read Only with auto clear.  2014-2016 Microchip Technology Inc. DS00001792E-page 55

USB3320 7.1.3 VENDOR REGISTER ACCESS The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write. 7.1.3.1 HS TX Boost Address = 31h (read / write) Field Name Bit Access Default Description Reserved 4:0 rd 00000b Read only, 0. Boost 6:5 rd/w 00b Sets the HS transmitter amplitude as described in Section5.2.1. 00b: Nominal 01b: Enables 11.1% increased drive strength 10b: Enables 7.4% increased drive strength 11b: Enables 3.7% increased drive strength Reserved 7 rd 0b Read only, 0. 7.1.3.2 Headset Audio Mode Address = 33h (read / write) Field Name Bit Access Default Description HeadsetAudioEn 3:0 rd/w 0000b When this field is set to a value of 1010, the Headset Audio Mode is enabled as described in Section6.7. Reserved 7:4 rd 0h Read only, 0. 7.1.3.3 Vendor Rid Conversion Address = 36-38h (read), 36h (write), 37h (set), 38h (clear) Field Name Bit Access Default Description RidValue 2:0 rd/w 000b Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 100K ohms 011: 200K ohms 100: 440K ohms 101: ID floating 111: Error Note: RidValue can also be read from the Carkit Interrupt Status Register. RidConversionDone 3 rd (Note 7- 0b Automatically asserted by the USB3320 when the Rid 4) Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status Register will not clear either RidConversionDone status bit. Note: RidConversionDone can also be read from the Carkit Interrupt Status Register. RidConversionStart 4 rd/w/s/c 0b When this bit is asserted either through a register write or set, the Rid converter will read the value of the ID resistor. When the conversion is complete this bit will auto clear. Reserved 5 rd/w/s/c 0b This bit must remain at 0. DS00001792E-page 56  2014-2016 Microchip Technology Inc.

USB3320 Field Name Bit Access Default Description RidIntEn 6 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or’ed with the RidIntEn bit of the Carkit Interrupt Status register. Reserved 7 rd 0b Read only, 0. Note 7-4 rd: Read Only with auto clear. 7.1.3.4 USB IO & Power Management Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear) Field Name Bit Access Default Description Reserved 0 rd/w/s/c 0b Read only, 0. SwapDP/DM 1 rd/w/s/c 0b When asserted, the DP and DM pins of the USB transceiver are swapped. This bit can be used to prevent crossing the DP/DM traces on the board. In UART mode, it swaps the routing to the DP and DM pins. In USB Audio Mode, it does not affect the SPK_L and SPK_R pins. UART RegOutput 3:2 rd/w/s/c 01b Controls the output voltage of the VBAT to VDD33 regulator in UART mode. When the transceiver is switched from USB mode to UART mode regulator output will automatically change to the value specified in this register when TxdEn is asserted. 00: 3.3V 01: 3.0V (default) 10: 2.75V 11: 2.5V Note: When in USB Audio Mode the regulator will remain at 3.3V. When using this register it is recommended that the Link exit UART mode by using the RESETB pin. ChargerPullupEnDP 4 rd/w/s/c 0b Enables a Pull-up for USB Charger Detection when set on the DP pin. (The pull-up is automatically enabled in UART mode) ChargerPullupEnDM 5 rd/w/s/c 0b Enables a Pull-up for USB Charger Detection when set on the DM pin. (The pull-up is automatically enabled in UART mode) USB RegOutput 7:6 rd/w/s/c 00b Controls the output voltage of the VBAT to VDD33 regulator in USB mode. When the transceiver is in Synchronous Mode, Serial Mode, or Low Power Mode, the regulator output will be the value specified in this register. 00: 3.3V (default) 01: 3.0V 10: 2.75V 11: 2.5V  2014-2016 Microchip Technology Inc. DS00001792E-page 57

USB3320 8.0 APPLICATION NOTES 8.1 Application Diagram The USB3320 requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this voltage, and the USB3320 provides an integrated overvoltage protection circuit. The overvoltage protection circuit works with an external resistor (R ) to lower the voltage at the VBUS pin, as described in Section5.6.2.6. VBUS Following POR or hardware reset, the voltage at CLKOUT must not exceed V as provided in Table4-4. IH_ED TABLE 8-1: COMPONENT VALUES IN APPLICATION DIAGRAMS Reference Value Description Notes Designator C 2.2F Bypass capacitor to ground (<1ESR) for Place as close as possible to the OUT regulator stability. transceiver. C See Table8-2 Capacitor to ground required by the USB Place near the USB connector. VBUS Specification. Microchip recommends <1 ESR. C System Bypass capacitor to ground. Typical Place as close as possible to the BYP dependent. values used are 0.1 or 0.01 F. transceiver. C System The USB connector housing may be AC- Industry convention is to ground DC_LOAD dependent. coupled to the device ground. only the host side of the cable shield. R 1k or 10k Series resistor to work with internal See Section5.6.2.6 for information VBUS overvoltage protection. regarding power dissipation. 10k in device applications. See Table5-7 for required values in Host or OTG applications. R 8.06k (±1%) Series resistor to establish reference See Section5.3 for information BIAS voltage. regarding power dissipation. TABLE 8-2: CAPACITANCE VALUES AT VBUS OF USB CONNECTOR Mode MIN Value MAX Value Host 120F Device 1F 10F OTG 1F 6.5F DS00001792E-page 58  2014-2016 Microchip Technology Inc.

USB3320 FIGURE 8-1: USB3320 APPLICATION DIAGRAM (DEVICE, ULPI OUTPUT CLOCK MODE, 24MHZ) VDDIO Supply RenVaBUbSle m ouvset rbveo litnasgtea lled to 14 REFSEL2 Link Controller protection of the VBUS pin. 11 REFSEL1 8 REFSEL0 RESETB 27 RESETB RVBUS DATA7 13 DATA7 22 VBUS DATA6 10 DATA6 DATA5 9 DATA5 3S.1u-p5p.5lyV 1275 CXOPEN DDDDAAAATTTTAAAA4321 7654 DDDDAAAATTTTAAAA4321 The capacitor CVBUS 21 VBAT DATA0 3 DATA0 must be installed on STP 29 STP this side of RVBUS. CBYP NXT 2 NXT 20 VDD33 DIR 31 DIR CLKOUT 1 CLKIN USB CVBUS COUT REFCLK 26 REFCLK Receptacle Signal at REFCLK VBUS 23 ID must comply with DM 19 DM VIH and VIL VDDIO Supply VDDIO 32 DP 18 DP 1.8V Supply SHIELD VDD18 28, 30 CBYP GND CDC_BLOCK 1165 SSPPKK__LR RBIAS 24 CBYP GND RBIAS Optional Switched Signal to DP/DM  2014-2016 Microchip Technology Inc. DS00001792E-page 59

USB3320 FIGURE 8-2: USB3320 APPLICATION DIAGRAM (DEVICE, ULPI INPUT CLOCK MODE, 60MHZ) VDDIO Supply RenVaBUbSle m ouvset rbveo ltinasgtea lled to 14 REFSEL2 Link Controller protection of the VBUS pin. 11 REFSEL1 8 REFSEL0 RESETB 27 RESETB RVBUS DATA7 13 DATA7 22 VBUS DATA6 10 DATA6 DATA5 9 DATA5 3S.1u-p5p.5lyV 1275 CXOPEN DDDDAAAATTTTAAAA4321 7654 DDDDAAAATTTTAAAA4321 The capacitor CVBUS 21 VBAT DATA0 3 DATA0 must be installed on STP 29 STP this side of RVBUS. CBYP 20 VDD33 NDXIRT 231 DNXIRT USB CVBUS COUT REFCLK 26 CLKOUT Receptacle VBUS 23 ID ULPI Clock In Mode VDDIO Supply DM 19 DM CLKOUT 1 VDDIO 32 DP 18 DP 1.8V Supply SHIELD VDD18 28, 30 CBYP GND CDC_BLOCK 1165 SSPPKK__LR RBIAS 24 CBYP GND RBIAS Optional Switched Signal to DP/DM DS00001792E-page 60  2014-2016 Microchip Technology Inc.

USB3320 FIGURE 8-3: USB3320 APPLICATION DIAGRAM (HOST OR OTG, ULPI OUTPUT CLOCK MODE, 24MHZ) VDDIO Supply Link Controller 14 REFSEL2 11 REFSEL1 RESETB 27 RESETB 8 REFSEL0 DATA7 13 DATA7 17 CPEN DATA6 10 DATA6 DATA5 9 DATA5 DATA4 7 DATA4 RVBUS must be DATA3 6 DATA3 installed to enable DATA2 5 DATA2 VBUS overvoltage DATA1 4 DATA1 Switch protection of the DATA0 3 DATA0 EN VBUS pin. STP 29 STP 5V IN OUT RVBUS 22 VBUS NDXIRT 231 DNIXRT CLKOUT 1 CLKIN 3.1-5.5V The capacitor C XO 25 Resonator VBUS Supply must be installed on this side of RVBUS. 21 VBAT 1M C BYP - or - 20 VDD33 REFCLK 26 USB Receptacle CVBUS COUT Crystal VBUS C and Caps LOAD ID 23 ID VDDIO Supply DM 19 DM VDDIO 32 1.8V Supply DP 18 DP VDD18 28, 30 CBYP SHIELD 15 SPK_L CBYP GND RBIAS 24 16 SPK_R GND R BIAS For Host applications (non-OTG), the Optional ID pin should be connected to GND. Switched Signal to DP/DM  2014-2016 Microchip Technology Inc. DS00001792E-page 61

USB3320 8.2 Reference Designs Microchip has generated reference designs for connecting the USB3320 to SOCs with a ULPI port. Please contact the Microchip sales office for more details. 8.3 ESD Performance The USB3320 is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated into the USB3320 protect the device whether or not it is powered up. 8.3.1 HUMAN BODY MODEL (HBM) PERFORMANCE HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing, and is done without power applied to the IC. To pass the test, the device must have no change in operation or perfor- mance due to the event. All pins on the USB3320 except the REFCLK, SPK_L, and SPK_R pins provide ±8kV HBM protection, as shown in Table4-10. 8.3.2 EN/IEC 61000-4-2 PERFORMANCE The EN/IEC 61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device powered down. Microchip contracts with Independent laboratories to test the USB3320 to EN/IEC 61000-4-2 in a working system. Reports are available upon request. Please contact your Microchip representative, and request information on 3rd party ESD test results. The reports show that systems designed with the USB3320 can safely provide the ESD performance shown in Table4-10 without additional board level protection. In addition to defining the ESD tests, EN/IEC 61000-4-2 also categorizes the impact to equipment operation when the strike occurs (ESD Result Classification). The USB3320 maintains an ESD Result Classification 1 or 2 when subjected to an EN/IEC 61000-4-2 (level 4) ESD strike. Both air discharge and contact discharge test techniques for applying stress conditions are defined by the EN/IEC 61000-4-2 ESD document. 8.3.3 AIR DISCHARGE To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and construction of the test equipment. 8.3.4 CONTACT DISCHARGE The uncharged electrode first contacts the USB connector to prepare this test, and then the probe tip is energized. This yields more repeatable results, and is the preferred test method. The independent test laboratories contracted by Micro- chip provide test results for both types of discharge methods. DS00001792E-page 62  2014-2016 Microchip Technology Inc.

USB3320 9.0 PACKAGE INFORMATION 9.1 Package Marking Information 32-Lead QFN (5x5x0.85 mm) Example USB3320C USB3320C RYYWWXXXX A15410000 YYWWNNNA 1541000A VCOO ASETW e3 e3 PIN 1 PIN 1 Legend: USB3320C Product part number R Major product revision YYWW Year and workweek of assembly XXXX Internal engineering code YYWWNNNA Traceability code V Plant of assembly COO Country of origin e3 Pb-free JEDEC® designator for Matte Tin (Sn)  2014-2016 Microchip Technology Inc. DS00001792E-page 63

USB3320 9.2 Package Details The USB3320 is offered in a compact 32 pin QFN package. FIGURE 9-1: 32-PIN QFN, 5X5MM BODY, 0.5MM PITCH wings, on at Note: For the most current package drasee the Microchip Packaging Specificatihttp://www.microchip.com/packaging DS00001792E-page 64  2014-2016 Microchip Technology Inc.

USB3320 FIGURE 9-1: 32-PIN QFN, 5X5MM BODY, 0.5MM PITCH (CONTINUED) gs, at winon nt package draging Specificatim/packaging For the most curree Microchip Packawww.microchip.co Note: see thhttp://  2014-2016 Microchip Technology Inc. DS00001792E-page 65

USB3320 FIGURE 9-2: QFN, 5X5 TAPING DIMENSIONS AND PART ORIENTATION 4.00 Ø1.50 A 0.30 2.00 Ø1.50 1.75 R0.3 MAX 5.50 12.00 B0 K0 A0 8.00 A 0.25 SECTION A — A 10 mm R0.25 DIRECTION OF UNREELING A0 5.25 B0 5.25 K0 1.10 DS00001792E-page 66  2014-2016 Microchip Technology Inc.

USB3320 APPENDIX A: DATA SHEET REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Level & Date Section/Figure/Entry Correction DS00001793E (05-31-16) Table4-11, "USB3320 Quartz Column headings modified. Crystal Specifications" DS00001792D (04-13-16) Table4-3, "ULPI Interface Table heading corrected: “TYP” changed to “MAX” Timing" DS00001792C (03-28-16) Table4-3, "ULPI Interface Table heading corrected: “MAX” changed to “Units” Timing" Section 9.1, "Package Mark- Added package marking information. ing Information," on page63 Trademark and Sales Listing pages updated DS00001792B (04-30-15) Updated temperature range offering throughout the document to reflect a single -40 to +85C option and adjusted product ordering codes accordingly DS00001792A (08-14-14) Replaces previous SMSC version Rev. 1.0 (07-14-09) Rev. 1.0 (07-14-09) Initial Release  2014-2016 Microchip Technology Inc. DS00001792E-page 67

USB3320 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con- tains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi- nars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi- cation” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu- ment. Technical support is available through the web site at: http://www.microchip.com/support DS00001792E-page 68  2014-2016 Microchip Technology Inc.

USB3320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. - XXX - [X](1) Examples: a) USB3320C-EZK Device Package Tape and Reel Option b) USB3320C-EZK-TR Device: USB3320C Temperature -40C to+85C Range: Package: EZK = 32-pin QFN RoHS Compliant package Tape and Reel Blank = Standard packaging (tray) Option: TR = Tape and Reel(1) Note1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2014-2016 Microchip Technology Inc. DS00001792E-page 69

USB3320 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be super- seded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REP- RESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro- chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781522406501 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California CERTIFIED BY DNV and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping == ISO/TS 16949 == devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS00001792E-page 70  2014-2016 Microchip Technology Inc.

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