UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 DIGITAL PWM SYSTEM CONTROLLER WITH 4-BIT, 6-BIT, OR 8-BIT VID SUPPORT CheckforSamples:UCD9222-EP FEATURES 1 • FullyConfigurableTwo-OutputNon-Isolated • OverandUnder-VoltageFaultProtection 2 DC/DCPWMControllerwithsupportfor • Over-TemperatureFaultProtection TMS320C6670™andTMS320C6678™DSPVID • EnhancedNonvolatileMemoryWithError interface CorrectionCode(ECC) • SupportsSwitchingFrequenciesUpto2MHz • DeviceOperatesFromaSingleSupplyWithan With250psDuty-CycleResolution InternalRegulatorControllerThatAllows • UpTo1mVClosedLoopResolution OperationOveraWideSupplyVoltageRange • Hardware-Accelerated,3-Pole/3-Zero • SupportedbyFusionDigitalPower™ CompensatorwithNon-LinearGainfor Designer,aFullFeaturedPCBasedDesign ImprovedTransientPerformance TooltoSimulate,Configure,andMonitor • SupportsMultipleSoft-StartandSoft-Stop PowerSupplyPerformance. ConfigurationsIncludingPrebiasStart-up APPLICATIONS • SupportsVoltageMarginingandSequencing • SyncIn/OutPinsAlignDPWMClocksBetween • NetworkingEquipment MultipleUCD92xxDevices • TelecommunicationsEquipment • 12-BitDigitalMonitoringofPowerSupply • FPGA,DSP,andMemoryPower ParametersIncluding: – InputCurrentandVoltage SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS – OutputCurrentandVoltage – TemperatureatEachPowerStage • ControlledBaseline – AuxiliaryADCInputs • OneAssemblyandTestSite • MultipleLevelsofOver-currentFault • OneFabricationSite Protection: • AvailableinExtended(–55°Cto115°C) – ExternalCurrentFaultInputs TemperatureRange – AnalogComparatorsMonitorCurrent • ExtendedProductLifeCycle SenseVoltage • ExtendedProduct-ChangeNotification – CurrentContinuallyDigitallyMonitored • ProductTraceability DESCRIPTION The UCD9222 is a two-rail synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with support for up to two VID interfaces. Additionally, the UCD9222 has flash memory and a serial interface to support configurability, monitoringandmanagement. Several Voltage Identification (VID) modes are supported, including a 4-bit parallel interface, a 6-bit interface and an8-bitserialinterface. The UCD9222 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining and tracking to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. TMS320C6670,TMS320C6678,FusionDigitalPower,Auto-IDaretrademarksofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memoryandobservebothfrequencydomainandtimedomainsimulationsforeachofthepowerstageoutputs. TI has also developed multiple complementary power stage solutions – from discrete drivers in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD92xxfamilyofsystempowercontrollers. 2 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION OPERATINGTEMPERATURE ORDERABLEPART PIN TOPSIDE SUPPLY PACKAGE VIDNUMBER RANGE,TJ NUMBER COUNT MARKING –55°Cto115°C UCD9222WRGZREP 48-pin Reelof2500 QFN UCD9222EP V62/13622-01XE ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT VoltageappliedatV toDGND –0.3to3.8 V 33D VoltageappliedatV toAGND –0.3to3.8 V 33A Voltageappliedtoanypin(2) –0.3to3.8 V Storagetemperature(T ) –55to150 °C STG (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoGND. RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Supplyvoltageduringoperation,V ,V ,V 3 3.3 3.6 V 33D 33DIO 33A T Operatingjunctiontemperaturerange –55 115 °C J Maximumjunctiontemperature 125 °C THERMAL INFORMATION UCD9222-EP THERMALMETRIC(1) RGZ UNITS 48PINS θ Junction-to-ambientthermalresistance(2) 27.1 JA θ Junction-to-case(top)thermalresistance(3) 12.9 JCtop θ Junction-to-boardthermalresistance(4) 4.3 JB °C/W ψ Junction-to-topcharacterizationparameter(5) 0.2 JT ψ Junction-to-boardcharacterizationparameter(6) 4.3 JB θ Junction-to-case(bottom)thermalresistance(7) 0.6 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,high-Kboard,as specifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a. (3) Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.NospecificJEDEC- standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. (4) Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCB temperature,asdescribedinJESD51-8. (5) Thejunction-to-topcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted JT fromthesimulationdataforobtainingθ ,usingaproceduredescribedinJESD51-2a(sections6and7). JA (6) Thejunction-to-boardcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted JB fromthesimulationdataforobtainingθ ,usingaproceduredescribedinJESD51-2a(sections6and7). JA (7) Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.Nospecific JEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. Spacer Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com ELECTRICAL CHARACTERISTICS overoperatingjunctiontemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN NOM MAX UNIT SUPPLYCURRENT I TotalV33supplycurrent, 54 80 mA V33 V =V =3.3V 33A 33DIO I V =3.3V 42 55 mA V33DIO 33DIO Supplycurrent I V =3.3V 8 15 mA V33A 33A I V =3.3Vstoringconfiguration 52 65 mA V33DIO 33DIO parametersinflashmemory INTERNALREGULATORCONTROLLERINPUTS/OUTPUTS V 3.3-Vlinearregulator EmitterofNPNtransistor 3.25 3.3 3.6 V 33 V 3.3-Vlinearregulatorfeedback 4 4.6 V 33FB I Seriespassbasedrive V =12V 0.2 0.4 8 mA V33FB IN Beta SeriesNPNpassdevice 40 100 EXTERNALLYSUPPLIED3.3VPOWER V ,V , Digital3.3-Vpower T =25°C 3.0 3.6 V 33D 33DIO1 J V 33DIO2 V33A Analog3.3-Vpower T =25°C 3.0 3.6 V J ERRORAMPLIFIERINPUTSEAPn,EANn V Commonmodevoltageeachpin 0 1.8 V CM V Internalerrorvoltagerange AFE_GAINfieldofCLA_GAINS=1X(1) –256 248 mV ERROR EAP-EAN Errorvoltagedigitalresolution AFE_GAINfieldofCLA_Gains=8X 1 mV R Inputimpedance Groundreference,T =25°C 1.5 MΩ EA J I Inputoffsetcurrent 1kΩsourceimpedance,T =25°C –5 5 µA OFFSET J Vref10-bitDAC V Referencevoltagesetpoint 0 1.7 V ref V Referencevoltageresolution 1.56 mV refres ANALOGINPUTSCS1A,CS2A,VinMon,IinMon,Vtrack,Temp1,Temp2,Addr0,Addr1 V Measurementrangeforvoltage Inputs:VinMon,IinMon,Vtrack,Temp1, 0 2.6 V ADC_RANGE monitoring Temp2,CS1A,CS2A Voffset inputoffsetvoltage –27 27 mV V Over-currentcomparatorthreshold Inputs:CS1A,CS2A 0.032 2 V OC_THRS voltagerange(2) V Over-currentcomparatorthreshold Inputs:CS1A,CS2A 31.25 mV OC_RES voltagerange Temp Internaltemperaturesense Overrangefrom0°Cto100°C –15 15 °C internal accuracy INL ADCintegralnonlinearity T =-40°Cto115°C –2.5 2.5 mV J I Inputleakagecurrent 3Vappliedtopin 100 nA lkg R Inputimpedance Groundreference 8 MΩ IN C Currentsenseinputcapacitance 10 pF IN (1) SeetheUCD92xxPMBusCommandReferenceforthedescriptionoftheAFE_GAINfieldofCLA_GAINScommand. (2) Canbedisabledbysettingto'0' 4 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 ELECTRICAL CHARACTERISTICS (Continued) overoperatingjunctiontemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN NOM MAX UNIT DIGITALINPUTS/OUTPUTS VOL Low-leveloutputvoltage IOL=6mA(1),V33DIO=3V D+g0n.3d V VOH High-leveloutputvoltage IOH=-6mA(2),V33DIO=3V V–303.D6IVO V VIH High-levelinputvoltage V33DIO=3V 2.1 3.6 V VIL Low-levelinputvoltage V33DIO=3.5V 1.4 V SYSTEMPERFORMANCE VRESET Voltagewheredevicecomesoutofreset V33DPin 2.3 2.4 V tRESET Pulsewidthneededforreset nRESETpin 2 µs Vrefcommandedtobe1V,at25°CAFEgain=4, Setpointreferenceaccuracy 1VinputtoEAP/Nmeasuredatoutputofthe –10 10 mV VRefAcc EADC(3) Setpointreferenceaccuracyover –55°Cto115°C –40 40 mV temperature AFEgain=4comparedto VDiffOffset Differentialoffsetbetweengainsettings AFEgain=1,2,or8 –4 4 mV 240+1 tDelay Digitalcompensatordelay 240 switching ns cycle FSW Switchingfrequency 15.260 2000 kHz Accuracy –5% 5% Duty Maximumandminimumdutycycle 0% 100% V33Slew MinimumV33slewrate Vto3131s5l°eCwratebetween2.3Vand2.9V,TJ=-40°C 0.25 V/ms tretention Retentionofconfigurationparameters(4) TJ=25°C 100 Years Write_Cycles Numberofnonvolatileerase/writecycles TJ=25°C 20 Kcycles Allrailsconfiguredtoaccept4-bitVIDmessages(5) 1 RateVID MaxVIDmessagerate Allrailsconfiguredtoaccept6-bitVIDmessages(5) 4 msg/msec Allrailsconfiguredtoaccept8-bitVIDmessages(6) 4 (1) ThemaximumI ,foralloutputscombined,shouldnotexceed12mAtoholdthemaximumvoltagedropspecified. OL (2) ThemaximumI ,foralloutputscombined,shouldnotexceed48mAtoholdthemaximumvoltagedropspecified. OH (3) Withdefaultdevicecalibration.PMBuscalibrationcanbeusedtoimprovetheregulationtolerance. (4) Thedataretentionspecificationisbasedonacceleratedstresstestingat170°Cfor420hoursandusinganArrheniusmodelwith activationenergyof0.6eV. (5) VIDmessagerateoneachinterface.Measuredovera1.0msecinterval (6) VIDmessagerateonPMBusinterface. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com ADC MONITORING INTERVALS AND RESPONSE TIMES The ADC operates in a continuous conversion sequence that measures each rail's output voltage and output current, plus six other variables (input voltage, input current, internal temperature, tracking source, and two external temperature sensors). The length of the sequence is determined by the number of output rails (NumRails) configured for use. The time to complete the monitoring sampling sequence is give by the formula: t =t ×(2 ×NumRAILS+6) ADC_SEQ ADC PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ADCsingle-sampletime 3.84 µs ADC t ADCsequencerinterval Min=2×1Rail+6=8samples 30.72 38.40 µs ADC_SEQ Max=2×2Rails+6=10samples The most recent ADC conversion results are periodically converted into the proper measurement units (volts, amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The monitoringoperatesasynchronouslytotheADC,atintervalsshowninthetablebelow. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Outputvoltagemonitoringinterval 200 µs Vout t Outputcurrentmonitoringinterval 200×N µs Iout Rails t Inputvoltagemonitoringinterval 1 ms Vin t Inputcurrentmonitoringinterval 1 ms Iin t Temperaturemonitoringinterval 100 ms TEMP t AuxiliaryADCmonitoringinterval 100 ms AUXADC Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC sequence interval. Once a fault condition is detected, some additional time is required to determine the correct action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following tableliststheworse-casefaultresponsetimes. MAX MAX PARAMETER TESTCONDITIONS TYP UNIT noVID /wVID(1) t , Over-/under-voltagefaultresponsetime Normalregulation,noPMBusactivity, 250 800 µs OVF tUVF duringnormaloperation 4stagesenabled t , Over-/under-voltagefaultresponsetime, Duringdataloggingtononvolatile 800 1000 µs OVF t duringdatalogging memory(2) UVF t , Over-/under-voltagefaultresponsetime, Duringtrackingandsoft-startramp. 400 µs OVF t whentrackingorsequencingenable UVF t , Over-/under-currentfaultresponsetime Normalregulation,noPMBusactivity, 100+ 5000 µs OCF tUCF duringnormaloperation 4stagesenabled75%to125%current (600×NRails) step(3) t , Over-/under-currentfaultresponsetime, Duringdataloggingtononvolatile 600+ 5000 µs OCF tUCF duringdatalogging memory75%to125%currentstep (600×NRails) t Over-temperaturefaultresponsetime Temperatureriseof10°C/sec,atOT 1.60 sec OTF threshold t TimetotristatethePWMoutputaftera DRIVER_CONFIG=0x01 5.5 µs 3-State shutdownisinitiated (1) ControllerreceivingVIDcommandsatarateof4000msg/sec. (2) DuringaSTORE_DEFAULT_ALLcommand,whichstorestheentireconfigurationtononvolatilememory,thefaultdetectionlatencycan beupto10ms. (3) Becausethecurrentmeasurementisaveragedwithasmoothingfilter,theresponsetimetoanover-currentconditiondependsona combinationofthetimeconstant(τ)fromTable3,therecentmeasurementhistory,andhowmuchthemeasuredvalueexceedsthe over-currentlimit. 6 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 HARDWARE FAULT DETECTION LATENCY ThecontrollercontainshardwarefaultdetectioncircuitsthatareindependentoftheADCmonitoringsequencer. PARAMETER TESTCONDITIONS MAXTIME UNIT TimetodisableDPWMoutputbaseonactiveFAULTpin t HighlevelonFAULTpin 18 µs FAULT signal TimetodisabletheDPWMAoutputbasedoninternal Switch t StepchangeinCSvoltagefrom0Vto2.5V 4 CLF analogcomparator Cycles PMBUS/SMBUS/I2C The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBusareshownbelow. Figure1. I2C/SMBus/PMBusTiminginExtendedModeDiagram I2C/SMBus/PMBus TIMING REQUIREMENTS T =–55°Cto115°C,3V<V <3.6V,typicalvaluesatT =25°C J 33 J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT f SMBus/PMBusoperatingfrequency Slavemode;SMBC50%dutycycle 10 1000 kHz SMB f ICoperatingfrequency Slavemode;SCL50%dutycycle 10 1000 kHz I2C t Busfreetimebetweenstartandstop 5 µs (BUF) t Holdtimeafter(repeated)start 0.3 µs (HD:STA) t Repeatedstartsetuptime 0.3 µs (SU:STA) t Stopsetuptime 0.3 µs (SU:STO) t Dataholdtime Receivemode 0 ns (HD:DAT) t Datasetuptime 55 ns (SU:DAT) t Errorsignal/detect See (1) 35 ms (TIMEOUT) t Clocklowperiod 0.55 µs (LOW) t Clockhighperiod See (2) 0.3 50 µs (HIGH) t Cumulativeclocklowslaveextendtime See (3) 25 ms (LOW:SEXT) t Clock/datafalltime Risetimet =V –0.15)to(V +0.15), 1000 ns FALL RISE ILMAX IHMIN T =-40°Cto115°C J (1) TheUCD9222timesoutwhenanyclocklowexceedst . (TIMEOUT) (2) t ,max,istheminimumbusidletime.SMBC=SMBD=1fort>50mscausesresetofanytransactioninvolvingUCD9222thatis (HIGH) inprogress. (3) t isthecumulativetimeaslavedeviceisallowedtoextendtheclockcyclesinonemessagefrominitialstarttothestop. (LOW:SEXT) Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com I2C/SMBus/PMBus TIMING REQUIREMENTS (continued) T =–55°Cto115°C,3V<V <3.6V,typicalvaluesatT =25°C J 33 J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Clock/datarisetime Falltimet =0.9V to(V –0.15),T =- 1000 ns RISE FALL 33 ILMAX J 40°Cto115°C C IN FUNCTIONAL BLOCK DIAGRAM Fusion Power Peripheral2 Digital EAp2 Analog Front End Compensator DPWM2A High Res EAn2 (AFE) 3P/3Z IIR PWM FLT2A Fusion Power Peripheral 1 Analog Front End Compensator EAp1 Diff Digital EAn1 Amp Ref AEmrrp A6DbCit 3PII/R3Z HiPgWh RMes DFLPTW1MA1A Coeff. Regs SyncIn/JTAG_TDI SyncOut/JTAG_TDO 5 V33x 3.3V reg. VID1A 6 controller Analog Comparators VID1B xGnd &1.8V VID1C BPCap regulator VID VID1S Ref1 OC 1-2 VID2A DPWM1 ARM-7core VID2B VID2C Addr0 Addr1 Ref2 OC VID2S DPWM2 CS1A Flash TCK CS2A 12-bit Memory with TDI ADC ECC JTAG TDO TMS 260ksps Osc RCK nTRST VinMon IinMon/AuxADC4 POR/BOR Vtrack/AuxADC3 PowerGood PG1 Temp2/AuxADC2 GPIO PG2 Temp1/AuxADC1 EN1 Internal EN2 Temp Sense PMBus_Clk nRESET PMBus PMBus_Data PMBus_Alert PMBus_Cntrl 8 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 1 3 C C D D 0 1 A A dr dr x x d d ef Au Au _A _A ADC_R AGND3 Temp1/ Vtrack/ PMBus PMBus CS1A V33FB EAN2 EAP2 EAN1 EAP1 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 IinMon/AuxADC4 1 36 AGND2 Temp2/AuxADC2 2 35 BPCap CS2A 3 34 V33A VinMon 4 33 V33DIO nRESET 5 32 DGND3 FLT1A 6 31 JTAG_nTRST VID1S 7 30 JTAG_TMS FLT2A 8 29 SyncIn/JTAG_TDI VID2S 9 28 SyncOut/JTAG_TDO PMBus_CLK 10 27 JTAG_TCK PMBus_Data 11 26 EN2 DPWM1A 12 25 EN1 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 PG1 DPWM2A PG2 VID1A owerGood VID1B Bus_Alert Bus_Cntrl VID1C VID2A VID2B VID2C P M M P P (1) IncaseofconflictbetweenFigure2andTable1thetableshalltakeprecedence (2) PreliminaryversionsofthisdatasheetpriortoJune14,2010hadadifferentdefinitionforpins17,18,and21.Board designsmadewiththatearlierpinoutshouldbeupdated. Figure2. PinAssignmentDiagram Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com Table1. PINFUNCTIONS PINNO. PINLABEL DESCRIPTION 1 IinMon/AuxADC4 Inputcurrentmonitor,orAuxiliaryADCinput4 2 Temp2/AuxADC2 TemperaturesenseinputforRail2,orAuxiliaryADCinput2 3 CS2A Powerstage2Acurrentsenseinputandinputtoanalogcomparator2 4 VinMon Inputvoltagemonitor 5 nRESET Activelowdeviceresetinput.Pullupto3.3Vwitha10kohmresistor 6 FLT1A Faultindicatorforstage1A 7 VID1S VIDSelectpinforRail1 8 FLT2A Faultindicatorforstage2A 9 VID2S VIDSelectpinforRail2 10 PMBus_Clk PMBusClock.Pullupto3.3Vwitha2kohmresistor 11 PMBus_Data PMBusData.Pullupto3.3Vwitha2kohmresistor 12 DPWM1A DigitalPulseWidthModulatoroutput1A 13 PG1 Rail1PowerGoodIndicator 14 DPWM2A DigitalPulseWidthModulatoroutput2A 15 PG2 Rail2PowerGoodIndicator 16 VID1A VIDinputpinforRail1–leastsignificantbit 17 PowerGood PowerGoodIndication 18 VID1B VIDinputpinforRail1 19 PMBus_Alert PMBusAlert.Pullupto3.3Vwitha10kohmresistor 20 PMBus_Cntrl PMBusControl.Pullupto3.3Vwitha10kohmresistor 21 VID1C VIDinputpinforRail1–mostsignificantbit 22 VID2A VIDinputpinforRail2–leastsignificantbit 23 VID2B VIDinputpinforRail2 24 VID2C VIDinputpinforRail2–mostsignificantbit 25 EN1 Rail1Enable 26 EN2 Rail2Enable 27 JTAG_TCK JTAGTestClock 28 SyncOut/JTAG_TDO Mux'edpinJTAGTestDataOutput,DPWMSyncOutput 29 SyncIn/JTAG_TDI Mux'edpin–JTAGTestDataIn,DPWMSyncInput 30 JTAG_TMS JTAGTestmodeselect.Pullupto3.3Vwitha10kohmresistor 31 (JTAG)nTRST JTAGTestReset–Tietogroundwitha10kohmresistor 32 Dgnd3 DigitalGround 33 V33DIO 3.3VsupplyforDigitalI/OandCore 34 V33A Analog3.3Vsupply 35 BPCap 1.8VBypassCapacitor–tie0.1µFcaptoanalogground 36 Agnd2 Analogground 37 EAp1 Erroranalog,differentialvoltage,Positivechannel1input 38 EAn1 Erroranalog,differentialvoltage,Negativechannel1input 39 EAp2 Erroranalog,differentialvoltage,Positivechannel2input 40 EAn2 Erroranalog,differentialvoltage,Negativechannel2input 41 V33FB Connectiontothebaseof3.3Vlinearregulatortransistor(noconnectifunused) 42 CS1A Powerstage1Acurrentsenseinputandinputtoanalogcomparator1 43 Addr1 PMBusAddresssense.Channel1. 44 Addr0 PMBusAddresssense.Channel0. 45 Vtrack/AuxADC3 Trackingvoltageinput,orAuxiliaryADCinput3 46 Temp1/AuxADC1 TemperaturesenseinputforRail1,orAuxiliaryADCinput1 47 Agnd3 Analogground 10 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 Table1. PINFUNCTIONS(continued) PINNO. PINLABEL DESCRIPTION 48 ADC_Ref ADCReference.Tietoanaloggroundthrough0.1µFcapacitor PowerPad Itisrecommendedthatthispadbeconnectedtoanalogground TYPICAL APPLICATION SCHEMATIC Figure 3 shows the UCD9222 power supply controller as part of a system that provides the regulation of two independentpowersupplies.Theloopforeachpowersupplyiscreatedbytherespectivevoltageoutputsfeeding into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate driversforeachpowerstage. The ±V rail signals must be routed to the EAp/EAn input that matches the DPWM number that controls the sense output power stage. For example, the power stage driven by DPWM1A must have its feedback routed to EAP1 andEAN1. UCD7242 UCD9222 Figure3. TypicalApplicationSchematic Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com FUNCTIONAL OVERVIEW TheUCD9222containstwoFusionPowerPeripherals(FPP).EachFPPconsistsof: • Adifferentialinputerrorvoltageamplifier. • A10-bitDACusedtosettheoutputregulationreferencevoltage. • AfastADCwithprogrammableinputgaintodigitallymeasuretheerrorvoltage. • Adedicated3-pole/3-zerodigitalfiltertocompensatetheerrorvoltage • AdigitalPWM(DPWM)enginethatgeneratesthePWMpulsewidthbasedonthecompensatoroutput. EachcontrollerisconfigurablethroughthePMBusserialinterface. PMBus Interface The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus interface that is built on the I2C physical specification. The UCD9222 supports revision 1.2 of the PMBus standard. Wherever possible, standard PMBus commands are used to support the function of the device. For uniquefeaturesoftheUCD9222,MFR_SPECIFICcommandsaredefinedtoconfigureoractivatethosefeatures. Thesecommandsaredefinedinthe UCD92xxPMBUSCommandReference. TheUCD9222isPMBuscompliant,inaccordancewiththe"Compliance"sectionofthePMBusspecification.The firmware is also compliant with the SMBus 2.0 specification, including support for the SMBus ALERT function. Thehardwarecansupport100kHz,400kHz,or1MHzPMBusoperation. Resistor Programmed PMBus Address Decode The PMBus Address is selected using resistors attached to the ADDR0 and ADDR1 pins. At power-up, the device applies a bias current to each address detect pin. The measured voltage on each pin determines the PMBus address as defined in Table 2. For example, a 133kΩ resistor on ADDR1 and a 75kΩ on ADDR0 will selectPMBusaddress=100.ResistorsarechosenfromthestandardEIA-E96series,andshouldhaveaccuracy of1%orbetter. V33 UCD9222 ADDR - 0, ADDR - 1 pins 10mA I BIAS Resistor to set PMBus To 12-bitADC Address Figure4. PMBusAddressDetectionMethod A short or open on either address pin causes the PMBus address to default to address 126. To avoid potential conflictsbetweenmultipledevices,itisbesttoavoidusingaddress126. Someaddressesshouldbeavoided;seeTable2fordetails. 12 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 Table2.PMBusAddressBins(1) ADDR0 (short) (open) 42.2k 48.7k 56.2k 64.9k 75k 86.6k 100k 115k 133k 154k 178k 205k <36.5k >237k <36.5k 126 126 126 126 126 126 126 126 126 126 126 126 126 126 (short) 42.2k 126 126(2) 1 2 3 4 5 6 7 8 9 10 11(3) 126 48.7k 126 126(2) 13 14 15 16 17 18 19 20 21 22 33 126 56.2k 126 24 25 26 27 28 29 30 31 32 33 34 35 126 64.9k 126 36 37 38 39 40 41 42 43 44 45 46 47 126 75k 126 48 49 50 51 52 53 54 55 56 57 58 59 126 1 86.6k 126 60 61 62 63 64 65 66 67 68 69 70 71 126 R DD 100k 126 72 73 74 75 76 77 78 79 80 81 82 83 126 A 115k 126 84 85 86 87 88 89 90 91 92 93 94 95 126 133k 126 96 97 98 99 100 101 102 103 104 105 106 107 126 154k 126 108 109 110 111 112 113 114 115 116 117 118 119 126 178k 126 120 121 122 123 124 125 126 126(2) 126 126 126 126 126 205k 126 126 126 126 126 126 126 126 126 126 126 126 126 126 >237k 126 126 126 126 126 126 126 126 126 126 126 126 126 126 (open) (1) Shadedaddressesarenotrecommendedastheywillcauseconflictwhenmultipledevicesareused. (2) Reserved.Donotuse. (3) ConflictswithROM.Donotuse. VID Interface The UCD9222 supports VID (Voltage Identification) inputs from up to two external VID enabled devices. The VID codes may be 4-, 6-, or 8-bit values; the format is selected using the VID_CONFIG PMBus command. In 4- and 6-bit mode, each host uses four VID input signals (VID_A, VID_B, VID_C, and VID_S) to send VID codes to the UCD9222. In 8-bit mode, the PMBus input is used to receive VID commands from the VID devices’ I2C interfaces. VID Device #1 UCD9222 VID Device #2 VCNTL[0] VID1A VID2A VCNTL[0] VCNTL[1] VID1B VID2B VCNTL[1] VCNTL[2] VID1C VID2C VCNTL[2] VCNTL[3] VID1S VID2S VCNTL[3] Figure5. OneUCD9222ControlledbyTwoDSP/ASICsUsing4-bitor6-bitVIDFormat RegardlessofwhichVIDmodeisused,thecommandedoutputvoltagereferenceissetaccordingtothisformula: Vref_cmd=(VID_CODE× VID_Slope)+VID_Offset, where VID_Slope=(VID_Vout_High– VID_Vout_Low)/((2^VID_Format)-1), and VID_Offset=VID_Vout_Low. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com The VID_Vout_High, VID_Vout_Low, and VID_Format values are set using the VID_CONFIG PMBus command. The same command is used to set the initial VID code that will be used at power-up. In addition, the VID_CONFIG command also sets the initial voltage that the device ramps to at the end of the soft start; and definesalockoutintervaloverwhichtheVIDisignoredduringthesoftstart. VID Lockout Interval: Because the VID signals may be originating from a device that is being powered by the UCD9222, the voltage levels on the VID signal may not be valid logic levels until the supply voltage at the powered device has stabilized. For this reason a configurable lockout interval is applied each time the regulated output voltage is turned on. The lockout interval timer starts when the output voltage reaches the top of the soft- start ramp. Positive values range from 1 to 32767 ms, with 1 ms resolution. A value of 0 will enable the VID inputs immediately at the top of the start ramp. Negative values disable the lockout, allowing the VID inputs to remainactiveallthetimeregardlessoftheoutputvoltagestate.Thedefaultvalueis0. 4-Bit VID Mode: In 4-bit VID mode, the four VID input signals are used to provide the four bits of VID data, as shown in the table below. The VID lines are level-sensitive, and are periodically polled every 400µs. When the VID lines are changed to command a new voltage, there may be a delay of 500 to 600µs while the UCD9222 confirms that the VID signal levels are stable. The output voltage will then slew to the new setpoint voltage at the ratespecifiedbythePMBusVOUT_TRANSITION_RATEcommand. PIN PURPOSE RAIL1 RAIL2 VID_A Databit0(leastsignificantbit) VID1A VID2A VID_B Databit1 VID1B VID2B VID_C Databit2 VID1C VID2C VID_S Databit3(mostsignificantbit) VID1S VID2S 6-Bit VID Mode: In 6-bit VID mode, the four VID input signals are used to provide the six bits of VID data, as shown in the table below. Each of the three data lines (VID_A, VID_B, and VID_C) carries two bits of data per VIDcode.ThebitsareclockedandselectedbytheVID_Sselectline. PIN PURPOSE RAIL1 RAIL2 VID_A Databit0whenVID_Sislow, VID1A VID2A Databit3whenVID_Sishigh VID_B Databit1whenVID_Sislow, VID1B VID2B Databit4whenVID_Sishigh VID_C Databit2whenVID_Sislow, VID1C VID2C Databit5whenVID_Sishigh VID_S SelectLine: VID1S VID2S Low=LSB,High=MSB 14 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 The falling edge of the VID_S line triggers the UCD9222 to read bits 2:0 on the three VID data lines. The rising edge of VID_S triggers the UCD9222 to read bits 5:3 on the three VID data lines and calculate a new VOUT setpoint. This calculation takes from 35 to 135µs. The output voltage will then slew to the new setpoint voltage at theratespecifiedbytheVOUT_TRANSITION_RATEPMBuscommand. VID_S Lower Half UpperHalf Lower Half Upper Half VID_A VID_A= bit 0 VID_A= bit 3 VID_A= bit 0 VID_A= bit 3 VID_B VID_B = bit 1 VID_B = bit 4 VID_B = bit 1 VID_B = bit 4 VID_C VID_C = bit 2 VID_C = bit 5 VID_C = bit 2 VID_C = bit 5 VOUT Figure6. 6-BitVIDDataTransfer The set-up time on the data lines is 0 µs. All four VID lines must hold at the same level for some time after a change in the VID_S line to allow the UCD9222 to read and validate the data signals and perform necessary voltage calculations. The UCD9222 can tolerate single hold times as short as 70µs, but does not have sufficient computation power to sustain continuous VID messaging that quickly. It is expected that the hold time will be at least 125µs for sustained operations. It is recommended that the DSP only send VID messages when the regulatedvoltageneedstochange;sendingthesameVIDcoderepeatedlyandcontinuouslyprovidesnobenefit. Figure7 andTable3illustratethecriticaltimingmeasurementsastheyapplytothe6-bitVIDinterface. Tsu Thd Tchi Tclo VID_S VID_A, VID_B, VID_C Tr Tf Tvo VOUT Figure7. 6-bitVIDTiming Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com Table3.6-bitVIDTiming SYMBO PARAMETER MIN TYP MAX UNITS L Tr Dataandclockrisetime – 2.5 µs Tf Dataandclockfalltime – 0.3 µs Tsu Datasetupbeforechangingclock 0 µs Thd Dataholduntilnextclockchange 70 µs Tchi Clockhightime 70 125 µs Tclo Clocklowtime 70 125 µs Tvo ResponsetimefromrisingedgeofVID_Stostartof 35 135 µs Voutslewingtonewsetpoint 8-Bit VID Mode: In 8-bit VID mode, the four VID input signals are not used. Instead, an 8-bit VID code is transmitted to the UCD9222 through the PMBus / I2C port using one of the VID_CODE_RAILn commands, wherenistherailnumberfrom1to2. NAME DESCRIPTION(1) CODE VID_CONFIG SelectstheVIDmode,setstheupperandlowervoltagelimits,andthestartingvoltagecodeatpower-up. 0xBB VID_CODE_RAIL1 SelectstheVIDcodeusedtosettheoutputvoltageforRail1. 0xBC VID_CODE_RAIL2 SelectstheVIDcodeusedtosettheoutputvoltageforRail2. 0xBD (1) ForacompletedescriptionoftheserialVIDcommands,seetheUCD92xxPMBusCommandReference(SLUU337) 16 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 V OUT T MSGVO T T MSG VO Addr Cmd Data PEC Start Stop PMBus Clock ACK ACK ACK ACK PMBus Data Figure8. PMBusTimingforVID_CODE_RAILnCommand Table4.TypicalPMBusTimingforVID_CODE_RAILnCommand@400kHz SYMBOL PARAMETER CONDITIONS TYP UNITS T MessageTransmitTime,withPEC 400kHzclock,PECenabled 162–256 msgPEC µs MessageTransmitTime,withoutPEC 400kHzclock,PECenabled 126–221 T EndofmessageuntilVoutstartschanging 28–140 µs vo T StartofmessageuntilVoutstartchanging 400kHzclock,PECdisabled 169–314 µs msgvo The total time to transmit the serial VID command will vary depending on the other tasks that the UCD92xx processor is performing. Typical packet times varied from 162 to 256µs when the PMBus is configured for a 400 kb/s transfer rate running and the optional PEC byte is enabled. Disabling the PEC byte saves about 35µs and the transfer times are from 126 to 221µs. Note that these are not specified best-case/worst-case timings, but indicatearangegiventhetypicalacknowledgeoverheadinthehostandcontroller. After the VID packet has been received by the controller there is a delay before the set-point reference DAC is updated. This delay time varies from ~28µs to 140µs (typical ) depending on the existing priority of updating set- pointreferenceDACwhenthecommandisreceived. Witha221µspackettransfertime,itwouldseempossibletosend4500VIDmessagespersecondtothedevice. Very short bursts at this rate might be acceptable, but doing so for sustained periods could overwhelm the available processing resources in the UCD92xx, causing it to be delayed in performing its other monitoring and fault response tasks. In addition, if multiple hosts are trying to talk on the PMBus at such high rates then bus contentionwilloccurwithgreatregularity. To prevent these issues, it is prudent to limit the total VID messaging rate to less than 4 messages per millisecond. In a system with four independent hosts, each host might need to be limited to less than 1 message per millisecond. Therefore, to minimize PMBus traffic, it is best to only issue the VID command when a voltage changeisrequired.ThereisnobenefittosendingthesameVIDcodecontinuouslyandrepeatedly. JTAG Interface The JTAG interface can provide an alternate interface for programming the device. Two of the JTAG pins (TDI and TDO) are shared with the SyncIn and SyncOut function. JTAG is disabled by default. There are three conditionsunderwhichtheJTAGinterfaceisenabled: 1. WhentheROM_MODEPMBuscommandisissued. 2. On power-up if the Data Flash is blank. This allows JTAG to be used for writing the configuration parameters toaprogrammeddevicewithnoPMBusinteraction. 3. When an invalid address is detected at power-up. By opening or shorting one of the address pins to ground, aninvalidaddresscanbegeneratedthatenablesJTAG. WhentheJTAGportisenabledthesharedpinsarenotavailableforuseasSyncpins. If JTAG is to be used, an external mechanism such as jumpers or a mux must be used to prevent conflict betweenJTAGandtheSyncpins. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com Bias Supply Generator (Shunt Regulator Controller) The I/O and analog circuits in the UCD9222 require 3.3V to operate. This can be provided using a stand-alone external 3.3V supply, or it can be generated from the main input supply using an internal shunt regulator and an externaltransistor.Regardlessofwhichmethodisusedtogeneratethe3.3Vsupply,bypasscapacitorsof0.1 µF and 4.7 µF should be connected from V33A and V33D to ground near the device. An additional bypass capacitor from 0.1 to 1 µF must be connected from the BPCap pin to ground for the internal 1.8V supply to the device’s logiccircuits. Figure9 showsatypicalapplicationusingtheexternaltransistor.Thebaseofthetransistorisdrivenbyaresistor R1 to Vin and a transconductance amplifier whose output is on the V33FB pin. The NPN emitter becomes the 3.3Vsupplyforthechip. Vin To Power Stage FCX491A +3.3V 4.7μ 0.1μ R1 +1.8V 0.1μ 0.1μ B ADp V33F V33V33BPCa UCD9222 Figure9. 3.3VShuntRegulatorControllerI/O Inordertogeneratethecorrectvoltageonthebaseoftheexternalpasstransistor,theinternaltransconductance amplifier sinks current into the V33FB pin and a voltage is produced across R1. This resistor value should be chosensothatISINKisintherangefrom0.2to0.4mA.R1isdefinedas V -3.3-V R = in be 1 I E +I (b+1) SINK (1) WhereI isthecurrentintotheV33FBpin;V isthepowersupplyinputvoltage,typically12V;I isthecurrent SINK in E draw of the device and any pull up resistors tied to the 3.3V supply; and β is the beta of the pass transistor. For I = 0.3 mA, V =12V, β=99, V = 0.7V and I =50mA, this formula selects R1 = 10kΩ. Weaker transistors or SINK in be E larger current loads will require less resistance to maintain the desired I current. For example, lowering β to SINK 40wouldrequireR1=5.23kΩ;likewise,aninputvoltageof5Vrequiresavalueof1.24kΩ forR1. Power-On Reset The UCD9222 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the POR circuit detects the V33D rise. When V33D is greater than V , the device initiates an internal startup RESET sequence. At the end of the startup sequence, the device begins normal operation, as defined by the downloadeddevicePMBusconfiguration. External Reset The device can be forced into the reset state by an external circuit connected to the nRESET pin. A logic low voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a 10kΩ pull up resistorto3.3Visrecommended. 18 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 ON_OFF_CONFIG TheON_OFF_CONFIGcommandisusedtoselectthemethodofturningrailsonandoff.Itcanbeconfiguredso thattherail: • staysoff, • turnsonautomatically, • respondstothePMBus_Cntrlpin, • respondstoOPERATIONcommand,or • respondstological-ANDofthePMBus_CntrlpinandtheOPERATIONcommand. TheON_OFF_CONFIGcommandalsosetstheactivepolarityofthePMBus_Cntrlpin. EN1/EN2 In addition to the PMBus_Cntrl pin supported by all UCD92xx products, the UCD9222 also supports separate Enable pins for each rail. The polarity of the EN1/EN2 pin is user-configurable, and will be the same as the polarity chosen for the PMBus_Cntrl pin by the ON_OFF_CONFIG command. When the ON_OFF_CONFIG setting is configured to respond the PMBus_Cntrl pin, the PMBus_Cntrl pin signal will be logically ANDed with therail’sENpinsignal. PG1/PG2 In addition to the PowerGood output signal supported by all UCD92xx products, the UCD9222 also supports separate PG indicators for each rail. The PowerGood signal is the logical-AND of all rails, while PG1 and PG2 indicate the status of a single rail. All three of these indicators are open-drain outputs, so they require pull-up resistors. When driving external circuits with logic voltages less than 3.3V, the pull-ups may be tied to that lower supplyvoltage,thusavoidingtheneedforlevel-shifters. Output Voltage Adjustment The output voltage may be set to maintain a steady voltage or it may be controlled dynamically by the VID interface, depending on the VID_CONFIG setting. When not being commanded by the VID interface, the nominal output voltage is programmed by a combination of PMBus settings: VOUT_COMMAND, VOUT_CAL_OFFSET, VOUT_SCALE_LOOP, and VOUT_MAX. Their relationship is shown in Figure 10. These PMBus parameters needtobesetsuchthattheresultingVrefDACvaluedoesnotexceedthemaximumvalueofV . ref Output voltage margining is configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands. The OPERATION command selects between the nominal output voltage and either of the margin voltages. The OPERATION command also includes an option to suppress certain voltage faults and warnings while operating atthemarginsettings. OPERATION Command V VOUT_CAL_OFFSET OUT VOUT_MARGIN_HIGH R1 V VOUT_COMMAND 3:1 VOUT_MAX Sense R2 Mux VOUT_MARGIN_LOW 3:1 + VOUT_ + VID_CODE_RAILx Limiter SCALE_ Vref DAC eADC Mux LOOP 4-wire VID interface VOUT_OV_FAULT_LIMIT VOUT_OV_WARN_LIMIT digital VID_CONFIG VOUT_UV_WARN_LIMIT compensator VOUT_UV_FAULT_LIMIT Figure10. PMBusVoltageAdjustmentMechanisms Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com For a complete description of the commands supported by the UCD9222 see the UCD92xx PMBUS Command Reference (SLUU337). Each of these commands can also be issued from the Texas Instruments Fusion Digital Power™ Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands toconfiguretheUCD9222device. Calibration To optimize the operation of the UCD9222, PMBus commands are supplied to enable fine calibration of output voltage, output current, and temperature measurements. The supported commands and related calibration formulasmaybefoundintheUCD92xxPMBUSCommandReference(SLUU337). Analog Front End (AFE) V G = 1, 2, 4, or 8 EAP V AFE 6-bit EA V Vead result EAN EADC G = 8mV/LSB eADC Vref DAC CPU Vref = 1.563 mV/LSB PMBus Figure11. AnalogFrontEndBlockDiagram The UCD9222 senses the power supply output voltage differentially through the EAP and EAN pins. The error amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage sensesignals.Thefullydifferentialnatureoftheerroramplifieralsoensureslowoffsetperformance. The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by the 10-bit Vref DAC as shown in Figure 11. The resulting error voltage is then amplified by a programmable gain circuit before the error voltage is converted to a digital value by the error ADC (EADC). This programmable gain is configured through the PMBus and affects the dynamic range and resolution of the sensed error voltage as shown in Table 5. The internal reference gains and offsets are factory-trimmed at the 4x gain setting, so it is recommendedthatthissettingbeusedwheneverpossible. Table5.AnalogFrontEndResolution AFE_GAINfor EFFECTIVEADC DIGITALERRORVOLTAGE AFEGain PMBusCommand RESOLUTION(mV) DYNAMICRANGE(mV) 0 1x 8 –256to248 1 2x 4 –128to124 2(Recommended) 4x 2 –64to62 3 8x 1 –32to31 The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This allowstheusertotrade-offresolutionanddynamicrangeforeachoperationalmode. The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time. However, its range is limited as shown in Table 5. If the output voltage is different from the reference by more than this, the EADC repoºrts a saturated value at –32 LSBs or 31 LSBs. The UCD9222 overcomes this limitation by adjusting the Vref DAC up or down in order to bring the error voltage out of saturation. In this way, the effective range of the ADC is extended. When the EADC saturates, the Vref DAC is slewed at a rate of 0.156 V/ms,referredtotheEAdifferentialinputs. 20 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 The differential feedback error voltage is defined as V = V – V . An attenuator network using resistors R1 EA EAP EAN and R2 (Figure 12) should be used to ensure that V does not exceed the maximum value of Vref when EA operating at the commanded voltage level. The commanded voltage level is determined by the PMBus settings describedintheOutputVoltageAdjustment section. R1 EAP +Vout R2 C2 Rin Ioff -Vout EAN Figure12. InputOffsetEquivalentCircuit Voltage Sense Filtering Conditioning should be provided on the EAP and EAN signals. Figure 12 shows a divider network between the output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the signalconditionedbythelow-passfilterformedbyR1andC2. As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly across an output capacitor as close to the load as possible. Route the positive and negative differential sense signalsasabalancedpairoftracesorasatwistedpaircablebacktothecontroller.Putthedividernetworkclose to the controller. This ensures that there is low impedance driving the differential voltage sense signal from the voltage rail output back to the controller. The resistance of the divider network is a trade-off between power loss and minimizing interference susceptibility. A parallel resistance (R ) of 1kΩ to 4kΩ is a good compromise. Once p RPischosen,R1andR2canbedeterminedfromthefollowingformulas. R R = P 1 K R R = P 2 1-K V where K = EA @ VOUT_SCALE_LOOP V OUT (2) It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter, thecornerfrequencyshouldbe35%to40%oftheswitchingfrequency.Thenthecapacitoriscalculatedas: 1 C2= 2p´0.35´F ´R SW P (3) To obtain the best possible accuracy, the input resistance and offset current on the device should be considered when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the UCD9222. The input resistance and input offset current are specified in the parametric tables in this datasheet. V =V –V intheequationbelow. EA EAP EAN R RR V = 2 V + 1 2 I EA æRR ö OUT æRR ö OFFSET R +R +ç 1 2 ÷ R +R +ç 1 2 ÷ 1 2 R 1 2 R è EA ø è EA ø (4) Theeffectoftheoffsetcurrentcanbereducedbymakingtheresistanceofthedividernetworklow. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com Digital Compensator Each voltage rail controller in the UCD9222 includes a digital compensator. The compensator consists of a nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter sectioncascadedwithafirstorderIIRfiltersection. The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the compensator coefficients. The design tool allows the compensator to be described in terms of the pole frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power™ Designercanbeusedtocharacterizethepowerstagesothatthecompensatorcoefficientscanbechosenbased on the total loop gain for each feedback system. The coefficients of the filter sections are generated through modelingthepowerstageandload. Additionally, the UCD9222 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is belowtheconfiguredlightloadthreshold. Figure13. DigitalCompensator To calculate the values of the digital compensation filter continuous-time design parameters K , F ands Q are DC Z Z entered into the Fusion Digital Power Designer software (or it calculates them automatically). Where the compensatingfiltertransferfunctionis S2 s + +1 w2 w Q H(s)=K Z Z Z DC æ s ö sç +1÷ w è ø P2 (5) There are approximate limits the design parameters K , F ands Q . Though design parameters beyond these DC Z Z upper a lower bounds can be used to calculate the discrete-time filter coefficients, there will be significant round- off error when the continuous-time floating-point design parameters are converted to the discrete-time fixed-point integercoefficientstobedownloadedtothecontroller. 22 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 APPROXIMATE DESIGNPARAMETER UNITS LOWERBOUND UPPERBOUND K 60 103 dB DC F 3kHz Fsw/5 kHz Z Q 0.1 5.0 n/a Z The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to be symmetrical. For example, the four limit registers could all be set to positive values causing the Gain 0 value tosetthegainforallnegativeerrorsandanonlineargainprofilewouldbeappliedtoonlypositiveerrorvoltages. Thecascaded1storderfiltersectionisusedtogeneratethethirdzeroandthirdpole. DPWM Engine The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty cycle as a digital number representing a percentage from 0 to 100%. The duty cycle value is multiplied by the configured period to generate a comparator threshold value. This threshold is compared against the high speed switchingperiodcountertogeneratethedesiredDPWMpulsewidth.ThisisshowninFigure14. Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the SyncIn and SyncOut pins. Configuration of the synchronization function is done through a MFR_SPECIFIC PMBus command.SeetheDPWMSynchronization sectionformoredetails. DPWM Engine (1 of 2) Clk SysClk highres ramp reset counter SyncIn S PWM gate drive output Switch period R Current balance adj Compensator output (Calculated duty cycle) EADC trigger EADC trigger SyncOut threshold Figure14. DPWMEngine Rail/Power Stage Configuration Unlike many other products in the UCD92xx family, the UCD9222 does not support assigning power stages to arbitrary rails, or combining multiple power stages on the same rail. The UCD9222 supports up to two single- phase rails, and the channel number of each rail’s DPWM output must match that of its EAP/EAN feedback inputs. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com DPWM Phase Synchronization DPWM synchronization provides a method to link the timing between voltage rails controlled by the UCD92xx device--either internally or between devices. The configuration of the synchronization between rails is performed by the issuing the SYNC_CONFIG command. For details of issuing this command, see the UCD92xx PMBUS Command Reference (SLUU337). The synchronization behavior can also be configured using the Fusion Digital PowerDesignersoftware.Belowisasummaryofthefunction. Each digital pulse width modulator (PWM) engine in the UCD92xx controller can accept a sync signal that resets the PWM ramp generator. The ramp generator can be set to free-run, accept a reset signal from another internal PWM engine, or accept a reset signal from the external SyncIn pin (UCD9222 only). In addition, each digital PWM engine can generate a phase delayed sync signal that can be directed to another PWM reset input or directed to the external SyncOut pin. In this way the PWM timers can be "daisy-chained" to set up the desired phaserelationshipbetweenpowerstages. ThePWMengineresetinputcanacceptthefollowinginputs Table6.SyncTriggerInputs None(freerun) DPWM1 DPWM2 SyncInPin When configuring a PWM engine to run synchronous to another internal PWM output, set the switching frequency of each PWM output to the same value using the FREQUENCY_SWITCH PMBus command. Set the time point where the controller samples the voltage to be regulated by setting the EADC_SAMPLE_TRIGGER valuetotheminimumvalue(228-240nsecbeforetheendoftheswitchingperiod). WhenconfiguringaPWMenginetorunsynchronoustorunanexternalsyncsignal,theswitchingperiodmustbe set to be longer than the period of the sync signal by setting the value of the FREQUENCY_SWITCH command to be lower than the frequency of the sync signal. This way the external sync signal will reset the PWM ramp counterbeforeitisinternallyreset.Inthisoperatingcondition,theerrorADCsampletriggertimemustbesetto: 1 0.95 EADC_SAMPLE_TRIGGER³ - +248ns F F SW sync (6) where F is the switching frequency set by FREQUENCY_SWITCH and F is the minimum synchronization SW sync frequency. The factor of 0.95 is due to the 5% tolerance on the internal clock in the controller. This will ensure that the regulation voltage is sampled "just in time" to calculate the appropriate control effort for each switching period.ThisisshowninFigure15. ADC sample=Period-EADC trigger Early sync Sync-in EADCThreshold ConvertADC sample and calculate insufficient time compensated to convertADC error sample Compensated error previous control PWM pulse effort Figure15. RelationshipofEADCTriggertoexternalSync 24 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 If two rails share a common sync source other than the SyncIn pin, they must have the same delay. When the SyncIn pin is used as a sync source, the delay is applied using a different register (EV1) than when using the other sources (which use the PhaseTrig registers). Using the EV1 register introduces delay in the control loop calculation that will introduce phase loss that must be taken into consideration when calculating the loop compensation. Therefore, under most conditions it will be desirable to set the delay to zero for the PWM signal synchronizedbytheSyncInpin. Output Current Measurement Pins CS1A and CS2A are used to measure either output current or inductor current in each of the controlled power stages. PMBus commands IOUT_CAL_GAIN and IOUT_CAL_OFFSET are used to calibrate each measurement. See the UCD92xx PMBus Command Reference (SLUU337) for specifics on configuring this voltagetocurrentconversion. When the measured current is outside the range of either the over-current or under-current fault threshold, a current limit fault is declared and the UCD9222 performs the PMBus configured fault recovery. ADC current measurements are digitally averaged before they are compared against the over-current and under-current warning and fault thresholds. The output current is measured at a rate of one output rail per t microseconds. Iout The current measurements are then passed through a digital smoothing filter to reduce noise on the signal and prevent false errors. The output of the smoothing filter asymptotically approaches the input value with a time constantthatisapproximately3.5timesthesamplinginterval. Table7.OutputCurrentFilterTimeConstants NUMBEROF OUTPUTCURRENT FILTER OUTPUTRAILS SAMPLINGINTERVALS(µs) TIMECONSTANTτ(ms) 1 200 0.7 2 400 1.4 This smoothed current measurement is used for output current fault detection; see the Over-current Detection section. The smoothed current measurement is also reported in response to a PMBus request for a current reading. Current Sense Input Filtering Each power stage current is monitored by the device at the CS pins. The device monitors the current with a 12- bit ADC and also monitors the current with a digitally programmable analog comparator. The comparator can be disabledbywritingazerototheFAST_OC_FAULT_LIMIT. Because the current sense signal is both digitally sampled and compared to the programmable over-current threshold, it should be conditioned with an RC network acting as an anti-alias filter. If the comparator is disabled, the CS input should be filtered at 35% of the sampling rate. An RC network with this characteristic can be calculatedas N T R =0.45 rails Iout C (7) where N is the number of rails configured and T is the sample period for the current sense inputs. rails Iout Therefore,whenthecomparatorisnotused,therecommendedcomponentvaluesfortheRCnetworkareC=10 nFandR=35.7kΩ. When the fast over-current comparator is used, the filter corner frequency based on the ADC sample rate may betooslowandacornerfrequencythatisacompromisebetweentherequirementsoffastover-currentdetection and attenuating aliased content in the sampled current must be sought. In this case, the filter corner frequency canbecalculatedbasedonthetimetocrosstheover-currentthreshold. V = V +DV (1-e-tt) OC_thres CS_nom Imon (8) where V is the programmed OC comparator threshold, V is the nominal CS voltage, ΔV is the OC_thres CS_nom Imon change in CS voltage due to an over-current fault and τ is the filter time constant. Using the equation for the comparatorvoltageabove,theRCnetworkvaluescanbecalculatedas Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com T 1 R = det ´ C ln(DV )-ln(DV -V +V ) Imon Imon OC_thres CS_nom (9) where T is the time to cross the over-current comparator threshold. For T = 10 µs, ΔV = 1.5V, V = det det Imon OC_thres 2.0V and V = 1.5V, the corner frequency is 6.4 kHz and the recommended RC network component values CS_nom areC=10nFandR=2.49kΩ. Over-Current Detection Several mechanisms are provided to sense output current fault conditions. This allows for the design of power systemswithmultiplelayersofprotection. 1. Integrated gate drivers such as the UCD72xx family can be used to generate the FLT signal. The driver monitors the voltage drop across the high side FET and if it exceeds a resistor/voltage programmed threshold, the driver activates its fault output. A logic high signal on the FLT input causes a hardware interrupt to the internal CPU, which then disables the DPWM output. This process takes about 14 microseconds. 2. Inputs CS1A and CS2A each drive an internal analog comparator. These comparators can be used to detect the voltage output of a current sense circuit. Each comparator has a separate threshold that can be set by the FAST_OC_FAULT_LIMIT PMBus command. Though the command is specified in amperes, the hardware threshold is programmed with a value between 31mV and 2V in 64 steps. The relationship between amperes to sensed volts is configured by the IOUT_CAL_GAIN command. When the current sense voltage exceeds the threshold, the corresponding DPWM output is driven low on the voltage rail with the fault. 3. Each Current Sense input to the UCD9222 is also monitored by the 12-bit ADC. Each measured value is scaled using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands and then passed through a digital smoothing filter. The smoothed current measurements are compared to fault and warning limits set by the IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT commands. The action taken when an OC fault is detectedisdefinedbytheIOUT_OC_FAULT_RESPONSEcommand. Because the current measurement is averaged with a smoothing filter, the response time to an over-current condition depends on a combination of the time constant (τ) from Table 7, the recent measurement history, and how much the measured value exceeds the over-current limit. When the current steps from a current (I ) that is 1 lessthanthelimittoahighercurrent(I )thatisgreaterthanthelimit,theoutputofthesmoothingfilteris 2 I (t)=I +(I -I )(1-e-tt) smoothed 1 2 1 (10) AtthepointwhenI exceedsthelimit,thesmoothingfilterlagstime,t is smoothed lag æ I -I ö t = tlnç 2 1 ÷ lag I -I è ø 2 limit (11) The worst case response time to an over-current condition is the sum of the sampling interval (Table 7) and the smoothingfilterlag,t fromEquation11. lag Current Foldback Mode When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the UCD9222 attempts to continue to operate by reducing the output voltage in order to maintain the output current at the value set by IOUT_OC_FAULT_LIMIT. This continues indefinitely as long as the output voltage remains above the minimum value specified by IOUT_OC_LV_FAULT_LIMIT. If the output voltage is pulled down to less thanthatvalue,thedevicerespondsasprogrammedbytheIOUT_OC_LV_FAULT_RESPONSEcommand. Input Voltage Monitoring The VinMon pin on the UCD9222 monitors the input voltage. The VinMon pin is monitored using the internal 12- bit ADC which has a dynamic range of 0 to 2.5V. The fault thresholds for the input voltage are set using the VIN_OV_FAULT_LIMIT and VIN_UV_FAULT_LIMIT commands. The scaling for Vin is set using the VIN_SCALE_MONITORcommand. 26 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 Input UV Lockout The input supply lock-out voltage thresholds are configured with the VIN_ON and VIN_OFF commands. When input supply voltage drops below the value set by VIN_OFF, the device starts a normal soft stop ramp. When the input supply voltage drops below the voltage set by VIN_UV_FAULT_LIMIT, the device performs as configured by the VIN_UV_FAULT_RESPONSE command. For example, when the bias supply for the controller is derived from another source, the response code can be set to "Continue" or "Continue with delay," and the controller attempts to finish the soft stop ramp. If the bias voltages for the controller and gate driver are uncertain below some voltage, the user can set the UV fault limit to that voltage and specify the response code to be "shut down immediately," disabling all DPWM outputs. VIN_OFF sets the voltage at which the output voltage soft-stop ramp isinitiated,andVIN_UV_FAULT_LIMITsetsthevoltagewherepowerconversionisstopped. Temperature Monitoring The UCD9222 monitors temperature using the 12-bit ADC. The ADC12 is read every 100us and combined into a running sum. At the end of each 100ms monitoring interval, the ~1000 sample in the running sum are averaged together and the running sum is restarted. These averaged values are used to calculate the temperature from external temperature sensors. These same values may be read directly using the READ_AUX_ADCS PMBus command. The averaged values are passed through an additional digital smoothing filter to further reduce the chance of reportingfalseover-temperatureevents.Thesmoothingfilterhasatimeconstantof1.55seconds. Auxiliary ADC Input Monitoring Unused external temperature sensor inputs may be used for general-purpose analog monitoring. The READ_AUX_ADCS PMBus command returns a block of four 16-bit values, each of which is the average of multiple raw measurements from the AuxADC inputs. These AuxADC inputs share usage with other signals such as Temp1, Temp2, Vtrack, and IinMon. A value of 0 corresponds to 0.00V and a value of 65535 corresponds to 2.50V. Unlike many other variables that can be monitored via PMBus, no mechanism is provided for adjusting thegainoroffsetoftheAuxADCmeasurements. When using the temperature sensor inputs as Auxiliary ADCs, the temperature warning and faults should be disabledtopreventshut-downsduetonon-existentover-temperatureconditions. Soft Start, Soft Stop Ramp Sequence TheUCD9222performssoftstartandsoftstoprampsunderclosed-loopcontrol. Performing a start or stop ramp or tracking is considered a separate operational mode. The other operational modes are normal regulation and light load regulation. Each operational mode can be configured to have an independent loop gain and compensation. Each set of loop gain coefficients is called a "bank" and is configured usingtheCLA_GAINSPMBuscommand. Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal reference toward the commanded reference voltage at the rate specified by the TON_RISE time and VOUT_COMMAND. The DPWM outputs are enabled when the internal ramp reference equals the preexisting voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width specified by DRIVER_MIN_PULSE. This ensures that a constant ramp rate is maintained, and that the ramp is completed at thesametimeitwouldbeiftherehadnotbeenapre-biascondition. Figure16showstheoperationofsoft-startrampsandsoft-stopramps. Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UCD9222-EP

UCD9222-EP SLVSBY1–OCTOBER2013 www.ti.com Figure16. StartandStopRamps When a voltage rail is in its idle state, the DPWM outputs are disabled, and the differential voltage on the EAP/EAN pins are monitored by the controller. During idle the Vref DAC is adjusted to match the feedback voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is required to match the measured voltage on the rail. Nominally this is calculated as Vout / Vin. If the pre-bias voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage hasincreasedtothepointwheretherequireddutycycleexceedsthespecifiedminimumduty. Once a soft start/stop ramp has begun, the output is controlled by adjusting the Vref DAC at a fixed rate and allowing the digital compensator control engine to generate a duty cycle based on the error. The Vref DAC adjustmentsaremadeatarateof10kHzandarebasedontheTON_RISEorTOFF_FALLPMBusconfiguration parameters. Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when the DPWM signals become active, the time from when the controller starts processing the turn-on command to the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or minimum duty cycle. During a normal ramp (i.e. no tracking, no current limiting events and no EADC saturation), the set point slews at a pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the compensatorfollowsthisrampuptotheregulationpoint. Because the EADC in the controller has a limited range, it may saturate due to a large transient during a start/stop ramp. If this occurs, the controller overrides the calculated set point ramp value, and adjusts the Vref DAC in the direction to minimize the error. It continues to step the Vref DAC in this direction until the EADC comesoutofsaturation.Onceitisoutofsaturation,thestartrampcontinues,butfromthisnewsetpointvoltage; andtherefore,hasanimpactontheramptime. Non-volatile Memory Error Correction Coding The UCD9222 uses Error Correcting Code (ECC) to improve data integrity and provide high reliability storage of Data Flash contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written into the Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array. These extra check bits, along with the hardware ECC algorithm, allow for any single bit error to be detected and correctedwhentheDataFlashisread. 28 SubmitDocumentationFeedback Copyright©2013,TexasInstrumentsIncorporated ProductFolderLinks:UCD9222-EP

UCD9222-EP www.ti.com SLVSBY1–OCTOBER2013 APPLICATION INFORMATION Automatic System Identification ( Auto-ID™) By using digital circuits to create the control function for a switch-mode power supply, additional features can be implemented. One of those features is the measurement of the open loop gain and stability margin of the power supply without the use of external test equipment. This capability is called automatic system identification or Auto-ID™. To identify the frequency response, the UCD9222 internally synthesizes a sine wave signal and injects it into the loop at the Vref DAC. This signal excites the system, and the closed-loop response to that excitation can be measured at another point in the loop. The UCD9222 measures the response to the excitation at the output of the digital compensator. From the closed-loop response, the open-loop transfer function is calculated.Theopen-looptransferfunctionmaybecalculatedfromtheclosed-loopresponse. Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be divided out of the measured open-loop gain. In this way the UCD9222 can accurately measure the power stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and send the measurement data back to a host through the PMBus interface without the need for external test equipment. Details of the Auto-ID™ PMBus measurement commands can be found in the UCD92xx PMBus CommandReference(SLUU337). Data Logging The UCD9222 maintains a data log in non-volatile memory. This log tracks the peak internal and external temperature sensor measurements, peak current measurements and fault history. The PMBus commands and dataformatfortheDataLoggingcanbefoundinthe UCD92xxPMBusCommandReference(SLUU337). Copyright©2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UCD9222-EP

PACKAGE OPTION ADDENDUM www.ti.com 3-Nov-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCD9222WRGZREP ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 115 UCD9222EP & no Sb/Br) V62/13622-01XE ACTIVE VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 115 UCD9222EP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 3-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCD9222-EP : •Catalog: UCD9222 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCD9222WRGZREP VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.1 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCD9222WRGZREP VQFN RGZ 48 2500 367.0 367.0 38.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 7.1 A B 6.9 7.1 PIN 1 INDEX AREA 6.9 1 MAX C SEATING PLANE 0.05 0.08 C 0.00 2X 5.5 5.15±0.1 (0.2) TYP 13 24 44X 0.5 12 25 SYMM 2X 5.5 1 36 0.30 PIN1 ID 48X 0.18 (OPTIONAL) 48 37 SYMM 0.1 C A B 0.5 48X 0.3 0.05 C 4219044A 052018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) ( 5.15) SYMM 48X (0.6) 48 35 48X (0.24) 44X (0.5) 1 34 2X SYMM 2X (5.5) (6.8) 2X (1.26) 2X (1.065) (R0.05) TYP 23 12 21X (Ø0.2) VIA TYP 13 22 2X (1.26) 2X (1.065) 2X (5.5) LAND PATTERN EXAMPLE SCALE: 15X 0.07 MAX 0.07 MIN SOLDER MASK ALL AROUND ALL AROUND OPENING EXPOSED METAL EXPOSED METAL METAL SOLDER MASK METAL UNDER OPENING NON SOLDER MASK SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4219044A 052018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.comlitslua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048A VQFN - 1 mm max height PLASTIC QUADFLAT PACK- NO LEAD 2X (6.8) SYMM ( 1.06) 48X (0.6) 48X (0.24) 44X (0.5) SYMM 2X 2X (5.5) (6.8) 2X (0.63) 2X (1.26) (R0.05) TYP 2X 2X (0.63) (1.26) 2X (5.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 67 PRINTED COVERAGE BY AREA SCALE: 15X 4219044A 052018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCE DESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES“ASIS” ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANY IMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRD PARTYINTELLECTUALPROPERTYRIGHTS. TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.Youaresolelyresponsiblefor(1)selectingtheappropriate TIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicable standards,andanyothersafety,security,orotherrequirements.Theseresourcesaresubjecttochangewithoutnotice.TIgrantsyou permissiontousetheseresourcesonlyfordevelopmentofanapplicationthatusestheTIproductsdescribedintheresource.Other reproductionanddisplayoftheseresourcesisprohibited.NolicenseisgrantedtoanyotherTIintellectualpropertyrightortoanythird partyintellectualpropertyright.TIdisclaimsresponsibilityfor,andyouwillfullyindemnifyTIanditsrepresentativesagainst,anyclaims, damages,costs,losses,andliabilitiesarisingoutofyouruseoftheseresources. TI’sproductsareprovidedsubjecttoTI’sTermsofSale(www.ti.com/legal/termsofsale.html)orotherapplicabletermsavailableeitheron ti.comorprovidedinconjunctionwithsuchTIproducts.TI’sprovisionoftheseresourcesdoesnotexpandorotherwisealterTI’sapplicable warrantiesorwarrantydisclaimersforTIproducts. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265 Copyright©2018,TexasInstrumentsIncorporated