Product Order Technical Tools & Support & Folder Now Documents Software Community UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 UCD3138 Highly Integrated Digital Controller for Isolated Power 1 Device Overview 1.1 Features 1 • DigitalControlofupto3IndependentFeedback – SynchronousRectifierSoftOn/Off Loops – LowICStandbyPower – DedicatedPID-Basedhardware • SoftStart/StopwithandwithoutPrebias – 2-Pole/2-ZeroConfigurable • FastInputVoltageFeedForwardHardware – NonlinearControl • PrimarySideVoltageSensing • Upto16MHzErrorAnalog-to-DigitalConverter • CopperTraceCurrentSensing (EADC) • FluxandPhaseCurrentBalancingforNonpeak – ConfigurableResolutionasSmallas1mV/LSB CurrentModeControlApplications – AutomaticResolutionSelection • CurrentShareBusSupport – Upto8xOversampling – AnalogAverage – Hardware-BasedAveraging(upto8x) – MasterandSlave – 14-BitEffectiveDigital-to-AnalogConverter • FeatureRichFaultProtectionOptions (DAC) – 7High-SpeedAnalogComparators – AdaptiveSampleTriggerPositioning – Cycle-by-CycleCurrentLimiting • Upto8HighResolutionDigitalPulseWidth – ProgrammableFaultCounting Modulated(DPWM)Outputs – ExternalFaultInputs – 250-psPulseWidthResolution – 10DigitalComparators – 4-nsFrequencyResolution – ProgrammableBlankingTime – 4-nsPhaseResolution • SynchronizationofDPWMWaveformsBetween – AdjustablePhaseShiftBetweenOutputs MultipleUCD3138devices – AdjustableDead-bandBetweenPairs • 14-Channel,12-Bit,267-kspsGeneral-Purpose – Cycle-by-CycleDutyCycleMatching ADCwithIntegrated – Upto2-MHzSwitchingFrequency – ProgrammableAveragingFilters • ConfigurablePWMEdgeMovement – DualSampleandHold – TrailingModulation • InternalTemperatureSensor – LeadingModulation • FullyProgrammableHigh-Performance31.25 – TriangularModulation MHz,32-BitARM7TDMI-S™Processor • ConfigurableFeedbackControl – 32KBofProgramFlash – VoltageMode – 2KBofDataFlashwithECC – AverageCurrentMode – 4KBofDataRAM – PeakCurrentModeControl – 4KBofBootROMEnablesFirmwareBoot-Load intheFieldviaI2CorUART – ConstantCurrent • CommunicationPeripherals – ConstantPower – I2C/PMBus • ConfigurableModulationMethods – 2UARTsonUCD3138RGC(64-PinQFN) – FrequencyModulation – 1UARTonUCD3138RHA/UCD3138RMH – PhaseShiftModulation (40-PinQFN)andUCD3138RJA(40-PinVQFN) – PulseWidthModulation • TimerCapturewithSelectableInputPins • Fast,Automatic,andSmoothModeSwitching • Upto5AdditionalGeneralPurposeTimers – FrequencyModulationandPWM • BuiltInWatchdog:BODandPOR – PhaseShiftModulationandPWM • 64-PinQFNand40-PinQFNPackages • HighEfficiencyandLightLoadManagement • OperatingTemperature: –40°Cto125°C – BurstMode • Fusion_Digital_Power_DesignerGUISupport – IdealDiodeEmulation 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 1.2 Applications • PowerSuppliesandTelecomRectifiers • IsolatedDC-DCModules • PowerFactorCorrection 1.3 Description The UCD3138 is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single-chip solution. The flexible nature of the UCD3138 makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC-DC and isolated DC-DC applicationsandreducethesolutioncomponentcountintheITandnetworkinfrastructurespace. The UCD3138 controller is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customers' development effort by offering best-in-class development tools, including application firmware, Code Composer Studio™ software development environment, and TI’s power developmentGUIwhichletscustomersconfigureandmonitorkeysystemparameters. At the core of the UCD3138 controller are the digital control loop peripherals, also known as Digital Power Peripherals (DPPs). Each DPP implements a high-speed digital control loop consisting of a dedicated Error Analog-to-Digital Converter (EADC), a PID-based 2-pole/2-zero digital compensator and DPWM outputs with 250-ps pulse width resolution. The device also contains a 12-bit, 267-ksps general-purpose ADC with up to 14 channels, timers, interrupt control, PMBus, and UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring, configures peripherals, and manages communications. The ARM microcontroller executes its program out ofprogrammableflashmemoryaswellason-chipRAMandROM. In addition to the FDPP, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. Such peripherals include: light load burst mode, synchronous rectification, LLC and phase- shifted full bridge mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high-resolution current sharing, hardware-configurable soft start with pre bias, as well as several other features. Topology support has been optimized for voltage mode and peak current mode controlled phase-shifted full bridge, single and dual phase PFC, bridgeless PFC, hard-switched full bridge and half bridge, and LLC half bridge and full bridge. DeviceInformation(1) PARTNUMBER PACKAGEDRAWING PACKAGETYPE BODYSIZE RGC VQFN(64) 9.00mm×9.00mm RHA VQFN(40) 6.00mm×6.00mm UCD3138 RMH WQFN(40) 6.00mm×6.00mm RJA VQFN(40) (2) 6.00mm×6.00mm (1) Formoreinformation,seeSection11,MechanicalPackagingandOrderableInformation. (2) Recommendedfornew40-pindesigns,optimizedforimprovedperformanceundertemperaturecyclingtestforboardlevelreliability (BLR). 2 DeviceOverview Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 1.4 Functional Block Diagram Figure1-1showsafunctionalblockdiagramofthedevice. Loop MUX EAP0 DPWM0A Front End0 PID Based DPWM0 Filter0 EAN0 DPWM0B EAP1 DPWM1A PID Based Front End1 DPWM1 EAN1 Filter1 DPWM1B Front End2 PID Based DPWM2 DPWM2A AFE Filter2 DPWM2B Constant Power Constant DPWM3A 23-AFE Current DPWM3 DPWM3B EEAAPN22 2AFE EADC X Avg() Front EndAveraging SYNC Digital Comparators SAR/Prebias DAC0 A0 Ramp Input Voltage Feed Forward Filter x CPCC Σ Value Dither Abs() Peak Current Mode Control Comparator Advanced Power Control Mode Switching,Burst Mode,IDE, Synchronous Rectification soft on&off ADC_EXT_TRIG ADC12Control PMBUS_ALERT Sequencing,Averaging, PMBUS_CTRL Digital Compare,Dual PMBus AD[13:0] ADC12 Sample and hold PMBUS_DATA AD00 PMBUS_CLK AD01 InternalTemperature Sensor PWM0 Timers 4–16bit(PWM) PWM1 AD02 1–24bit AGND Current Share Oscillator TCAP AD13 Analog,Average,Master/Slave SCI_TX0 ARM7TDMI-S UART0 SCI_RX0 Analog 32bit,31.25MHz Comparators SCI_TX1 AD02 UART1 A SCI_RX1 Memory AD03 PFLASH32kB EXT_INT B DFLASH2kB RAM4kB FAULT0 C ROM4kB GPIO FAULT1 Control AD04 Fault MUX& FAULT2 D Control Power On Reset V33D AD13 FAULT3 Cycle by Cycle E V33DIO Current Limit /RESET Brown Out Detection AD06 BP18 Power and Digital TCK F 1.8V Voltage Comparators DGND Regulator JTAG TDI AD07 V33A G TMS AGND TDO Figure1-1.FunctionalBlockDiagram NOTE Front-end2RecommendedforPeakCurrentModeControl Copyright©2012–2017,TexasInstrumentsIncorporated DeviceOverview 3 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com Table of Contents 1 DeviceOverview......................................... 1 6.2 ARM Processor..................................... 25 .............................................. .............................................. 1.1 Features 1 6.3 Memory 25 ........................................... ...................................... 1.2 Applications 2 6.4 SystemModule 27 ............................................ ................................. 1.3 Description 2 6.5 FeatureDescription 29 ............................ ........................... 1.4 FunctionalBlockDiagram 3 6.6 DeviceFunctionalModes 48 2 Revision History......................................... 4 7 ApplicationandImplementation.................... 55 3 DeviceComparisonTable.............................. 7 7.1 ApplicationInformation.............................. 55 .......................... .................................. 3.1 ProductFamilyComparison 7 7.2 TypicalApplication 56 3.2 ProductSelectionMatrix ............................. 7 8 PowerSupplyRecommendations.................. 67 4 PinConfigurationandFunctions..................... 8 8.1 PowerSupplyDecouplingandBulkCapacitors.... 67 4.1 UCD3138RGC64QFNPinAttributes.............. 10 9 Layout.................................................... 68 4.2 UCD3138RHA,UCD3138RMHandUCD3138RJA 9.1 Layout Guidelines................................... 68 ........................................ PinAttributes 12 ..................................... 9.2 Layout Example 69 5 Specifications........................................... 13 10 DeviceandDocumentationSupport............... 70 ......................... 5.1 AbsoluteMaximumRatings 13 ...................................... 10.1 DeviceSupport 70 ........................................ 5.2 ESDRatings 13 ............................. 10.2 DocumentationSupport 72 ............... 5.3 RecommendedOperatingConditions 13 .. 10.3 ReceivingNotificationofDocumentationUpdates 72 ................................. 5.4 Thermal Information 13 .............................. 10.4 CommunityResources 72 ............................ 5.5 ElectricalCharacteristics 14 .......................................... 10.5 Trademarks 72 ............... 5.6 TimingandSwitchingCharacteristics 16 ..................... 10.6 ElectrostaticDischargeCaution 72 .......................... 5.7 PowerSupplySequencing 18 ............................................. 10.7 Glossary 72 .......................................... 5.8 Peripherals 18 11 MechanicalPackagingandOrderable 5.9 TypicalTemperatureCharacteristics................ 24 Information.............................................. 72 6 DetailedDescription................................... 25 11.1 PackagingInformation .............................. 72 ............................................ 6.1 Overview 25 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionH(October2016)toRevisionI Page • AddedupdatedLayoutGuidelinessection....................................................................................... 68 • AddedLayoutExampleimages. .................................................................................................. 69 4 RevisionHistory Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 ChangesfromRevisionG(September2016)toRevisionH Page • AddedPACKAGEDRAWINGcolumntotheDeviceInformationtable. ...................................................... 2 • ChangedNote2from"Recommendedfornew40-pindesignswithadvanceBLRperformance"to "Recommendedfornew40-pindesigns,optimizedforimprovedperformanceundertemperaturecyclingtestfor boardlevelreliability(BLR)." ....................................................................................................... 2 • DeletedFigure4-3note,"Thesefeatureshelptoimprovesolder-jointreliability". .......................................... 9 ChangesfromRevisionF(November2013)toRevisionG Page • AddedDeviceandDocumentationSupportsectionandESDRatingstable.................................................. 2 • ChangeddocumentflowtomatchUCD3138A.................................................................................... 2 • AddedRJApackagetoFeaturesandtheDeviceInformationtable........................................................... 2 • AddedRJApackage. .............................................................................................................. 10 • AddedtheRJApackagetotheThermalInformationtable. ................................................................... 13 ChangesfromRevisionE(August2013)toRevisionF Page • ChangedTopSideMarkinginfofrom"3138"to"3138RMH"intheOrderingInformationtable. ....................... 2 ChangesfromRevisionD(August2013)toRevisionE Page • AddedUCD3138RMHtoFeaturebullet........................................................................................... 1 • AddedRMHpackagepinoutdrawing.............................................................................................. 9 • AddedRMHpackagethermalspecifications.................................................................................... 13 • ChangedGlobalI/Oregistersorderedlist,item5textfrom"Connectingpin/pinstohighrailthroughinternalpull upresistors."to"Configuringpin/pinsasopendrainorpush-pull(Normal)"................................................ 45 ChangesfromRevisionC(March2013)toRevisionD Page • ChangedT spectoT inAbsMaxtablewithMAXtempof150°C....................................................... 13 OPT J • AddedBP18VoltagevsTemperaturegraphic.................................................................................. 24 ChangesfromRevisionB(July2012)toRevisionC Page • Deleted"JTAGDebugPort"featurebullet........................................................................................ 1 • Deletedtextstring"JTAGdebug"fromDescriptionsection..................................................................... 2 • AddedNOTEunderFunctionalBlockDiagram................................................................................... 3 • Deleted"JTAG"optionfromProductSelectionMatrix........................................................................... 8 • AddedtexttoPin54description.................................................................................................. 11 • AddedtexttoPin35description.................................................................................................. 12 • AddedBP18spectoAbsMaxRatingsandRecommendedOperatingConditionsTables............................... 13 • DeletedV specificationfromSystemPerformancesectionofElectricalCharacteristics................................ 15 DD • AddedfootnotetoTable5-1....................................................................................................... 16 • Addedtextstringregardingfront-end2intheFrontEndsection ............................................................ 19 • Deletedtextstringreferenceto"JTAGport"inARMProcessorsection..................................................... 25 • ChangedillustrationinICGroundingandLayoutRecommendationssection.............................................. 68 • Changedtextstringsin ............................................................................................................ 70 • AddeddocumenttoReferenceslist............................................................................................... 72 ChangesfromRevisionA(March2012)toRevisionB Page • AddedFeaturebullets................................................................................................................ 1 • Changed"DualEdgeModulation"to"TriangularModulation"inFeaturessection.......................................... 1 • Changed"265ksps"to"267ksps"inFeaturessection......................................................................... 1 • ClarifiednumberofUARTsinFeaturesection ................................................................................... 1 Copyright©2012–2017,TexasInstrumentsIncorporated RevisionHistory 5 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com • Changed"FDPP"to"DDP"throughout. ........................................................................................... 2 • ChangedTotalGPIOpincountfortheUCD313840-pindevicefrom"17"to"18"intheProductSelectionMatrix table..................................................................................................................................... 8 • Changed"VREG"to"BP18"inconditionsstatementforElectricalCharacteristics........................................ 14 • ChangedEAP–EANErrorvoltagedigitalresolutionMINvaluesforAFE=3,AFE=2,AFE=1,AFE=0from 0.95,1.90,3.72,and7.3respectively;to,0.8,1.7,3.55,and6.90respectively............................................ 14 • ChangedconditionsforV andV specificationsinElectricalCharacteristics........................................... 15 OL OH • AddedTWDspecificationtoElectricalCharacteristics......................................................................... 15 • Changed"PWM"to"DPWM"in .................................................................................................. 20 • Changedwaveformsgraphicfor"PhaseShiftedFullBridgeExample"forclarification ................................... 30 • Addedtexttosection............................................................................................................... 31 • Changedtypicalconversionspeedfrom"268ksps"to"267ksps"intheGeneralPurposeADC12section............ 42 • AddedpackageIDinformationfortheUCD3138RGCandUCD3138RHAdevices........................................ 44 • Addedbullet"AD02hasaspecialESDprotectionmechanismthatpreventsthepinfrompullingdownthe current-sharebusifpowerismissingfromtheUCD3138"to................................................................. 46 • Changed"PWMA"and"PWMB"to"DPWMA"and"DPWMB"inSection6.6.1. ........................................... 50 • Addedsub-bullet"ThepowerpadofthedriverICshouldbetiedtoDGND"andchangedcapacitorvaluefrom "0.1µF"to"4.7µF"in .............................................................................................................. 68 • Changed"MechanicalData"sectionto"References"section................................................................ 72 ChangesfromOriginal(March2012)toRevisionA Page • AddedProductionDatastatementtofootnoteandremoved"ProductPreview"banner.................................... 1 • Deletedtable:SummaryofKeyDifferencesBetweenUCD3138xandUCD3138........................................... 7 6 RevisionHistory Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 3 Device Comparison Table 3.1 Product Family Comparison FEATURE UCD3138x80PINS ARM7TDMI-SCoreProcessor 31.25MHz HighResolutionDPWMOutputs(250-psresolution) 8 Numberofhighspeedindependentfeedbackloops(numberofregulatedoutputvoltages) 3 12-bit,267ksps,GeneralPurposeADCchannels 15 DigitalcomparatorsatADCoutputs 4 Flashmemory(program)(UCD3138A64) 64kB Flashmemory(program)(UCD3138128) 128kB Flashmemory(data) 2kB Flashsecurity √ RAM 8kB DPWMswitchingfrequency upto2MHz Programmablefaultinputs 4 Highspeedanalogcomparatorswithcycle-by-cyclecurrentlimiting 7 UART(SCI) 2 PMBus 1 I2C 1 SPI 1 Timers 4(16bit)and2(24bit) TimerPWMoutputs 4 Timercaptureinputs 2 Watchdog √ On-chiposcillator √ Power-onresetandbrown-outdetector √ SyncINandsyncOUTfunctions √ TotalGPIO(includesallpinswithmultiplexedfunctionssuchas,DPWM,FaultInputs,SCI,andso 43 forth) ExternalInterrupts 1 3.2 Product Selection Matrix UCD313864PIN UCD313840PIN FEATURE (RGC) (RHA/RMH/RJA) ARM7TDMI-Scoreprocessor 31.25MHz 31.25MHz HighresolutiondPWMoutputs(250-psresolution) 8 8 Numberofhighspeedindependentfeedbackloops(numberofregulatedoutput 3 3 voltages) 12-bit,267ksps,general-purposeADCchannels 14 7 DigitalcomparatorsatADCoutputs 4 4 Flashmemory(program) 32KB 32KB Flashmemory(data) 2KB 2KB Flashsecurity √ √ RAM 4KB 4KB DPWMswitchingfrequency upto2MHz upto2MHz Programmablefaultinputs 4 1+2(1) Highspeedanalogcomparatorswithcycle-by-cyclecurrentlimiting 7(2) 6(2) (1) Thisnumberrepresentsanalternatepinoutthatisprogrammableviafirmware.SeetheUCD3138DigitalPowerPeripherals Programmer’sManualfordetails. (2) TofacilitatesimpleOVPandUVPconnectionsbothcomparatorsBandCareconnectedtotheAD03pin. Copyright©2012–2017,TexasInstrumentsIncorporated DeviceComparisonTable 7 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com UCD313864PIN UCD313840PIN FEATURE (RGC) (RHA/RMH/RJA) UART(SCI) 2 1(1) PMBus √ √ Timers 4(16bit)and1(24bit) 4(16bit)and1(24bit) TimerPWMoutputs 2 1 Timercaptureinputs 1 1(1) Watchdog √ √ Onchiposcillator √ √ Power-onresetandbrown-outreset √ √ Packageoffering 64PinQFN(9mm×9mm) 40PinQFN(6mm×6mm) SyncINandsyncOUTfunctions √ √ TotalGPIO(includesallpinswithmultiplexedfunctionssuchas,DPWM,fault 30 18 inputs,SCI,andsoforth) Externalinterrupts 1 0 4 Pin Configuration and Functions 11D 90D 80D 50D 20D 10D 00D A33 DNG 2NA 2PA 1NA 1PA 0NA 0PA DNG A A A A A A A V A E E E E E E A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 48 AGND AD13 2 47 V33D AD12 3 46 BP18 AD10 4 45 V33DIO AD07 5 44 DGND AD06 6 UCD3138RGC 43 FAULT3 AD04 7 42 FAULT2 AD03 8 41 TCAP (64 QFN) V33DIO 9 40 TMS DGND 10 39 TDI/SCI_RX0/PMBUS_CTRL/FAULT1 /RESET 11 38 TDO/SCI_TX0/PMBUS_ALERT/FAULT0 ADC_EXT_TRIG/TCAP/SYNC/PWM0 12 37 TCK/TCAP/SYNC/PWM0 SCI_RX0 13 36 FAULT1 SCI_TX0 14 35 FAULT0 PMBUS_CLK/SCI_TX0 15 34 INT_EXT PMBUS_DATA/SCI_RX0 16 33 DGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A B A B A B A B D 0 T L T L 0 1 0 0 1 1 2 2 3 3 N M R R R R M M MWPD MWPD MWPD MWPD MWPD MWPD MWPD MWPD GD WP/GIRT_TXE ELA_SUBMP TC_SUBMP ELA_SUBMP/1 TC_SUBMP/1X WP WP _CDA/P XT_ICS R_ICS A C T /C N Y S Figure4-1.UCD3138RGC64QFNPinAttributes 8 PinConfigurationandFunctions Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 D02 D01 D00 33A GND AP2 AN1 AP1 AN0 AP0 A A A V A E E E E E 40 39 38 37 36 35 34 33 32 31 AGND 1 30 AGND UCD3138RHA AD13 2 29 AGND AD06 3 28 BP18 (40 QFN) AD04 4 27 V33D AD03 5 26 DGND DGND 6 25 FAULT2 /RESET 7 24 TMS ADC_EXT_TRIG/TCAP/SYNC/PWM0 8 23 TDI/SCI_RX0/PMBUS_CTRL/FAULT1 PMBUS_CLK/SCI_TX0 9 22 TDO/SCI_TX0/PMBUS_ALERT/FAULT0 PMBUS_DATA/SCI_RX0 10 21 TCK/TCAP/SYNC/PWM0 11 12 13 14 15 16 17 18 19 20 A B A B A B A B T L 0 0 1 1 2 2 3 3 R R M M M M M M M M E T W W W W W W W W L C A _ P P P P P P P P _ S D D D D D D D D S U U B B M M P P Figure4-2.UCD3138RHA40QFNPinAttributes D02 D01 D00 33A GND AP2 AN1 AP1 AN0 AP0 A A A V A E E E E E 40 39 38 37 36 35 34 33 32 31 AGND 1 30 AGND AD13 2 29 AGND UCD3138RMH AD06 3 28 BP18 AD04 4 27 V33D (40 QFN) AD03 5 26 DGND DGND 6 25 FAULT2 /RESET 7 24 TMS ADC_EXT_TRIG/TCAP/SYNC/PWM0 8 23 TDI/SCI_RX0/PMBUS_CTRL/FAULT1 PMBUS_CLK/SCI_TX0 9 22 TDO/SCI_TX0/PMBUS_ALERT/FAULT0 PMBUS_DATA/SCI_RX0 10 21 TCK/TCAP/SYNC/PWM0 11 12 13 14 15 16 17 18 19 20 A B A B A B A B T L 0 0 1 1 2 2 3 3 R R M M M M M M M M E T W W W W W W W W L C PD PD PD PD PD PD PD PD A_S _SU U B B M M P P NOTE:TheRMHpackagehasthinnerpackageheightcomparedtotheRHApackage.Therearealsofourcorner pinsontheRMHpackage.Thecorneranchorpinsandthermalpadshouldbesolderedforrobustmechanical performanceandshouldbetiedtotheappropriategroundsignal. Figure4-3.UCD3138RMH40QFNWithCornerAnchorsPinAttributes Copyright©2012–2017,TexasInstrumentsIncorporated PinConfigurationandFunctions 9 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com D02 D01 D00 33A GND AP2 AN1 AP1 AN0 AP0 A A A V A E E E E E 40 39 38 37 36 35 34 33 32 31 AGND 1 30 AGND AD13 2 29 AGND UCD3138RJA AD06 3 28 BP18 AD04 4 27 V33D (40 QFN) AD03 5 26 DGND DGND 6 25 FAULT2 /RESET 7 24 TMS ADC_EXT_TRIG/TCAP/SYNC/PWM0 8 23 TDI/SCI_RX0/PMBUS_CTRL/FAULT1 PMBUS_CLK/SCI_TX0 9 22 TDO/SCI_TX0/PMBUS_ALERT/FAULT0 PMBUS_DATA/SCI_RX0 10 21 TCK/TCAP/SYNC/PWM0 11 12 13 14 15 16 17 18 19 20 A B A B A B A B T L 0 0 1 1 2 2 3 3 R R M M M M M M M M E T W W W W W W W W L C PD PD PD PD PD PD PD PD A_S _SU U B B M M P P NOTE:TheRJApackagehasthickerpackageheightcomparedtotheRMHpackage.Therearealsofourcornerpins ontheRJApackage.Thesefeatureshelptoimprovesolder-jointreliability.Thecorneranchorpinsandthermalpad shouldbesolderedforrobustmechanicalperformanceandshouldbetiedtotheappropriategroundsignal. Figure4-4.UCD3138RJA40QFNWithCornerAnchorsPinAttributes 4.1 UCD3138RGC 64 QFN Pin Attributes Table4-1.UCD3138RGC64QFNPinAttributes ALTERNATEASSIGNMENT CONFIGURABLE PINNO. NAME PRIMARYASSIGNMENT NO.1 NO.2 NO.3 ASAGPIO? 1 AGND Analogground 2 AD13 12-bitADC,Ch13,comparatorE,I-share DACoutput 3 AD12 12-bitADC,Ch12 4 AD10 12-bitADC,Ch10 12-bitADC,Ch7,ConnectedtocomparatorFand 5 AD07 DACoutput referencetocomparatorG 6 AD06 12-bitADC,Ch6,ConnectedtocomparatorF DACoutput 7 AD04 12-bitADC,Ch4,ConnectedtocomparatorD DACoutput 8 AD03 12-bitADC,Ch3,ConnectedtocomparatorBandC 9 V33DIO DigitalI/O3.3Vcoresupply 10 DGND Digitalground 11 RESET DeviceResetInput,activelow 12 ADC_EXT_TRIG ADCconversionexternaltriggerinput TCAP SYNC PWM0 Yes 13 SCI_RX0 SCIRX0 Yes 14 SCI_TX0 SCITX0 Yes 15 PMBUS_CLK PMBUSClock(OpenDrain) SCITX0 Yes 16 PMBUS_DATA PMBusdata(OpenDrain) SCIRX0 Yes 17 DPWM0A DPWM0Aoutput Yes 18 DPWM0B DPWM0Boutput Yes 19 DPWM1A DPWM1Aoutput Yes 20 DPWM1B DPWM1Boutput Yes 21 DPWM2A DPWM2Aoutput Yes 22 DPWM2B DPWM2Boutput Yes 10 PinConfigurationandFunctions Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 Table4-1.UCD3138RGC64QFNPinAttributes(continued) ALTERNATEASSIGNMENT CONFIGURABLE PINNO. NAME PRIMARYASSIGNMENT NO.1 NO.2 NO.3 ASAGPIO? 23 DPWM3A DPWM3Aoutput Yes 24 DPWM3B DPWM3Boutput Yes 25 DGND Digitalground ADC_EXT_TRI 26 SYNC DPWMSynchronizepin TCAP PWM0 Yes G 27 PMBUS_ALERT PMBusAlert(OpenDrain) Yes 28 PMBUS_CTRL PMBusControl(OpenDrain) Yes PMBUS_ALER 29 SCI_TX1 SCITX1 Yes T 30 SCI_RX1 SCIRX1 PMBUS_CTRL Yes 31 PWM0 GeneralpurposePWM0 Yes 32 PWM1 GeneralpurposePWM1 Yes 33 DGND Digitalground 34 INT_EXT ExternalInterrupt Yes 35 FAULT0 Externalfaultinput0 Yes 36 FAULT1 Externalfaultinput1 Yes 37 TCK JTAGTCK(Formanufacturertestonly) TCAP SYNC PWM0 Yes PMBUS_ALER 38 TDO JTAGTDO(Formanufacturertestonly) SCI_TX0 FAULT0 Yes T 39 TDI JTAGTDI(Formanufacturertestonly) SCI_RX0 PMBUS_CTRL FAULT1 Yes 40 TMS JTAGTMS(Formanufacturertestonly) Yes 41 TCAP Timercaptureinput Yes 42 FAULT2 Externalfaultinput2 Yes 43 FAULT3 Externalfaultinput3 Yes 44 DGND Digitalground 45 V33DIO DigitalI/O3.3Vcoresupply 46 BP18 1.8VBypass 47 V33D Digital3.3Vcoresupply 48 AGND Substrateanalogground 49 AGND Analogground 50 EAP0 Channel0,differentialanalogvoltage,positiveinput 51 EAN0 Channel0,differentialanalogvoltage,negativeinput 52 EAP1 Channel1,differentialanalogvoltage,positiveinput 53 EAN1 Channel1,differentialanalogvoltage,negativeinput Channel2,differentialanalogvoltage,positiveinput 54 EAP2 (Recommendedforpeakcurrrentmodecontrol) 55 EAN2 Channel#2,differentialanalogvoltage,negativeinput 56 AGND Analogground 57 V33A Analog3.3-Vsupply 58 AD00 12-bitADC,Ch0,Connectedtocurrentsource 59 AD01 12-bitADC,Ch1,Connectedtocurrentsource 60 AD02 12-bitADC,Ch2,ConnectedtocomparatorA,I-share 61 AD05 12-bitADC,Ch5 62 AD08 12-bitADC,Ch8 63 AD09 12-bitADC,Ch9 64 AD11 12-bitADC,Ch11 Copyright©2012–2017,TexasInstrumentsIncorporated PinConfigurationandFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 4.2 UCD3138RHA, UCD3138RMH and UCD3138RJA Pin Attributes Table4-2.UCD3138RHA,UCD3138RMHandUCD3138RJAPinAttributes ALTERNATEASSIGNMENT CONFIGURABLE PINNO. NAME PRIMARYASSIGNMENT NO.1 NO.2 NO.3 ASAGPIO? 1 AGND Analogground 2 AD13 12-bitADC,Ch13,ConnectedtocomparatorE,I-share 3 AD06 12-bitADC,Ch6,ConnectedtocomparatorF 4 AD04 12-bitADC,Ch4,ConnectedtocomparatorD 5 AD03 12-bitADC,Ch3,ConnectedtocomparatorBandC 6 DGND Digitalground 7 RESET DeviceResetInput,activelow 8 ADC_EXT_TRIG ADCconversionexternaltriggerinput TCAP SYNC PWM0 Yes 9 PMBUS_CLK PMBUSClock(OpenDrain) SCI_TX0 Yes 10 PMBUS_DATA PMBusdata(OpenDrain) SCI_RX0 Yes 11 DPWM0A DPWM0Aoutput Yes 12 DPWM0B DPWM0Boutput Yes 13 DPWM1A DPWM1Aoutput Yes 14 DPWM1B DPWM1Boutput Yes 15 DPWM2A DPWM2Aoutput Yes 16 DPWM2B DPWM2Boutput Yes 17 DWPM3A DPWM3Aoutput Yes 18 DPWM3B DPWM3Boutput Yes 19 PMBUS_ALERT PMBusAlert(OpenDrain) Yes 20 PMBUS_CTRL PMBusControl(OpenDrain) Yes 21 TCK JTAGTCK(Formanufacturertestonly) TCAP SYNC PWM0 Yes 22 TDO JTAGTDO(Formanufacturertestonly) SCI_TX0 PMBUS_ALERT FAULT0 Yes 23 TDI JTAGTDI(Formanufacturertestonly) SCI_RX0 PMBUS_CTRL FAULT1 Yes 24 TMS JTAGTMS(Formanufacturertestonly) Yes 25 FAULT2 Externalfaultinput2 Yes 26 DGND Digitalground 27 V33D Digital3.3Vcoresupply 28 BP18 1.8VBypass 29 AGND Substrateanalogground 30 AGND Analogground 31 EAP0 Channel0,differentialanalogvoltage,positiveinput 32 EAN0 Channel0,differentialanalogvoltage,negativeinput 33 EAP1 Channel1,differentialanalogvoltage,positiveinput 34 EAN1 Channel1,differentialanalogvoltage,negativeinput 35 EAP2 Channel2,differentialanalogvoltage,positiveinput (Recommendedforpeakcurrrentmodecontrol) 36 AGND Analogground 37 V33A Analog3.3-Vsupply 38 AD00 12-bitADC,Ch0,Connectedtocurrentsource 39 AD01 12-bitADC,Ch1,Connectedtocurrentsource 40 AD02 12-bitADC,Ch2,ConnectedtocomparatorA,I-share Corner Corner AllfouranchorsshouldbesolderedandtiedtoGND NA anchorpin (RMHandRJA only) 12 PinConfigurationandFunctions Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 5 Specifications 5.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V33D V33DtoDGND –0.3 3.8 V V33DIO V33DIOtoDGND –0.3 3.8 V V33A V33AtoAGND –0.3 3.8 V BP18 BP18toDGND –0.3 2.5 V |DGND–AGND| Grounddifference 0.3 V Allpins,excluding AGND(2) Voltageappliedtoanypin –0.3 3.8 V T Junctiontemperature –40 150 °C J T Storagetemperature –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) ReferencedtoDGND 5.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 5.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V33D Digitalpower 3.0 3.3 3.6 V V33DIO DigitalI/Opower 3.0 3.3 3.6 V33A Analogpower 3.0 3.3 3.6 V T Junctiontemperature –40 125 °C J BP18 1.8-Vdigitalpower 1.6 1.8 2.0 V 5.4 Thermal Information UCD3138 UCD3138 UCD3138 UCD3138 THERMALMETRIC(1) 64PINQFN 40PINQFN 40PINQFN 40PINQFN UNIT (RGC) (RHA) (RMH) (RJA) R Junction-to-ambientthermalresistance 25.1 31.8 31.0 30.1 °C/W θJA R Junction-to-case(top)thermalresistance 10.5 18.5 16.5 13.5 °C/W θJC(top) R Junction-to-boardthermalresistance 4.6 6.8 6.3 4.9 °C/W θJB ψ Junction-to-topcharacterizationparameter 0.2 0.2 0.2 0.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 4.6 6.7 6.3 4.8 °C/W JB R Junction-to-case(bottom)thermalresistance 1.2 1.8 1.1 0.7 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seeSemiconductorandICPackageThermalMetricsapplicationreport. Copyright©2012–2017,TexasInstrumentsIncorporated Specifications 13 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 5.5 Electrical Characteristics V33A=V33D=V33DIO=3.3V;1μFfromBP18toDGND,T =–40°Cto125°C(unlessotherwisenoted) J PARAMETER TESTCONDITION MIN TYP MAX UNIT SUPPLYCURRENT MeasuredonV33A.Thedeviceis I33A poweredupbutallADC12andEADC 6.3 mA samplingisdisabled AllGPIOandcommunicationpinsare I33DIO 0.35 mA open I33D ROMprogramexecution 60 mA I33D FlashprogramminginROMmode 70 mA ThedeviceisinROMmodewithall I33 DPWMsenabledandswitchingat2 100 mA MHz.TheDPWMsareallunloaded. ERRORADCINPUTSEAP,EAN EAP–AGND –0.15 1.998 V EAP–EAN –0.256 1.848 V Typicalerrorrange AFE=0 –256 248 mV AFE=3 0.8 1 1.20 mV AFE=2 1.7 2 2.30 mV EAP–EANErrorvoltagedigitalresolution AFE=1 3.55 4 4.45 mV AFE=0 6.90 8 9.10 mV R Inputimpedance(SeeFigure5-4) AGNDreference 0.5 MΩ EA I Inputoffsetcurrent(SeeFigure5-4) –5 5 μA OFFSET Inputvoltage=0VatAFE=0 –2 2 LSB Inputvoltage=0VatAFE=1 –2.5 2.5 LSB EADCoffset Inputvoltage=0VatAFE=2 –3 -3 LSB Inputvoltage=0VatAFE=3 –4 4 LSB SampleRate 16 MHz AnalogFrontEndAmplifierBandwidth 100 MHz Gain SeeFigure5-5 1 V/V A 0 Minimumoutputvoltage 100 mV EADCDAC DACrange 0 1.6 V VREFDACreferenceresolution 10bit,Noditheringenabled 1.56 mV VREFDACreferenceresolution With4bitditheringenabled 97.6 μV INL –3.0 3.0 LSB DNL DoesnotincludeMSBtransition –2.1 1.6 LSB DNLatMSBtransition –1.4 LSB DACreferencevoltage 1.58 1.61 V τ SettlingTime From10%to90% 250 ns ADC12 I BiascurrentforPMBusaddresspins 9.5 10.5 μA BIAS Measurementrangeforvoltagemonitoring 0 2.5 V InternalADCreferencevoltage –40°Cto125°C 2.475 2.500 2.525 V –40°Cto25°C –0.4 ChangeinInternalADCreferencefrom 25°Creferencevoltage(1) 25°Cto85°C –1.8 mV 25°Cto125°C –4.2 (1) Asdesignedandcharacterized.Not100%testedinproduction. 14 Specifications Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 Electrical Characteristics (continued) V33A=V33D=V33DIO=3.3V;1μFfromBP18toDGND,T =–40°Cto125°C(unlessotherwisenoted) J PARAMETER TESTCONDITION MIN TYP MAX UNIT ADC12INLintegralnonlinearity(1) ±2.5 LSB ADC12DNLdifferentialnonlinearity(1) ADC_SAMPLINGSEL=6forallADC12 –0.7/+2.5 LSB ADCZeroScaleError data,25°Cto125°C –7 7 mV ADCFullScaleError –35 35 mV Inputbias 2.5Vappliedtopin 400 nA Inputleakageresistance(1) ADC_SAMPLINGSEL=6or0 1 MΩ InputCapacitance(1) 10 pF ADCsinglesampleconversiontime(1) ADC_SAMPLINGSEL=6or0 3.9 μs DIGITALINPUTS/OUTPUTS(2)(3) V Low-leveloutputvoltage(4) I =4mA,V33DIO=3V DGND V OL OH +0.25 V High-leveloutputvoltage (4) I =–4mA,V33DIO=3V V33DIO V OH OH –0.6 V High-levelinputvoltage V33DIO=3V 2.1 V IH V Low-levelinputvoltage V33DIO=3V 1.1 V IL I Outputsinkingcurrent 4 mA OH I Outputsourcingcurrent –4 mA OL SYSTEMPERFORMANCE Totaltimeis:TWD× TWD Watchdogtimeoutrange 14.6 17 20.5 ms (WDCTRL.PERIOD+1) TimetodisableDPWMoutputbasedon HighlevelonFAULTpin 70 ns activeFAULTpinsignal Processormasterclock(MCLK) 31.25 MHz t Digitalcompensatordelay(5) (1clock=32ns) 6 clocks Delay t Pulsewidthneededatreset(1) 10 µs (reset) Retentionperiodofflashcontent(data T =25°C 100 years retentionandprogram) J Programtimetoeraseonepageorblockin 20 ms dataflashorprogramflash Programtimetowriteonewordindata 20 µs flashorprogramflash f Internaloscillatorfrequency 240 250 260 MHz (PCLK) Sync-in/sync-outpulsewidth Syncpin 256 ns FlashRead 1 MCLKs FlashWrite 20 μs Currentsharecurrentsource(See I 238 259 μA SHARE Figure6-16) R Currentshareresistor(SeeFigure6-16) 9.75 10.3 kΩ SHARE POWERONRESETANDBROWNOUT(V33Dpin,SeeFigure5-3) VGH Voltagegoodhigh 2.7 V VGL Voltagegoodlow 2.5 V V VoltageatwhichIResetsignalisvalid 0.8 V res Timedelayafterpowerisgoodor T 1 ms POR RESET*relinquished (2) DPWMoutputsarelowafterreset.OtherGPIOpinsareconfiguredasinputsafterreset. (3) Onthe40-pinpackageV33DIOisconnectedtoV33Dinternally. (4) Themaximumtotalcurrent,IOHmaxandIOLmaxforalloutputscombined,shouldnotexceed12mAtoholdthemaximumvoltagedrop specified.Maximumsinkcurrentperpin=–6mAatV ;maximumsourcecurrentperpin=6mAatV . OL OH (5) TimefromcloseoferrorADCsamplewindowtotimewhendigitallycalculatedcontroleffort(dutycycle)isavailable.Thisdelay,which hasnovariationassociatedwithit,mustbeaccountedforwhencalculatingthesystemdynamicresponse. Copyright©2012–2017,TexasInstrumentsIncorporated Specifications 15 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com Electrical Characteristics (continued) V33A=V33D=V33DIO=3.3V;1μFfromBP18toDGND,T =–40°Cto125°C(unlessotherwisenoted) J PARAMETER TESTCONDITION MIN TYP MAX UNIT Internalsignalwarningofbrownout Brownout 2.9 V conditions TEMPERATURESENSOR(6) V Voltagerangeofsensor 1.46 2.44 V TEMP Voltageresolution V/°C 5.9 mV/ºC Temperatureresolution °Cperbit 0.1034 ºC/LSB Accuracy(6)(7) –40°Cto125°C –10 ±5 10 ºC Temperaturerange –40°Cto125°C –40 125 ºC I Currentdrawofsensorwhenactive 30 μA TEMP T Turnontime/settlingtimeofsensor 100 μs ON V Ambienttemperature Trimmed25°Creading 1.85 V AMB ANALOGCOMPARATOR DAC ReferenceDACRange 0 2.5 V ReferenceVoltage 2.478 2.5 2.513 V Bits 7 bits INL(6) –0.42 0.21 LSB DNL(6) 0.06 0.12 LSB Offset –5.5 19.5 mV TimetodisableDPWMoutputbasedon0 Vto2.5Vstepinputontheanalog 150 ns comparator.(1) ReferenceDACbufferedoutputload(8) 0.5 1 mA Bufferoffset(–0.5mA) 4.6 8.3 mV Bufferoffset(1.0mA) –0.05 17 mV (6) Characterizedbydesignandnotproductiontested. (7) AmbienttemperatureoffsetvalueshouldbeusedfromtheTEMPSENCTRLregistertomeetaccuracy. (8) AvailablefromreferenceDACsforcomparatorsD,E,F,andG. 5.6 Timing and Switching Characteristics The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Table 5-1, Figure 5-1, and Figure 5-2. The numbers in Table 5-1 arµe for 400 kHz operating frequency. However, the device supports all three speeds, standard (100kHz),fast(400kHz),andfastmodeplus(1MHz). Table5-1.PMBus/SMBus/I2CTiming PARAMETER TESTCONDITIONS MIN TYP MAX UNIT TypicalvaluesatT =25°CandVCC=3.3V(unlessotherwisenoted) A f SMBus/PMBusoperatingfrequency Slavemode,SMBC50%dutycycle 100 1000 kHz SMB f I2Coperatingfrequency Slavemode,SCL50%dutycycle 100 1000 kHz I2C Busfreetimebetweenstartand t(BUF) stop(1) 1.3 µs t Holdtimeafter(repeated)start(1) 0.6 µs (HD:STA) t Repeatedstartsetuptime(1) 0.6 µs (SU:STA) t Stopsetuptime(1) 0.6 µs (SU:STO) t Dataholdtime Receivemode 0 ns (HD:DAT) t Datasetuptime 100 ns (SU:DAT) t Errorsignal/detect(2) 35 ms (TIMEOUT) (1) Fastmode,400kHz (2) Thedevicetimesoutwhenanyclocklowexceedst . (TIMEOUT) 16 Specifications Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 Table5-1.PMBus/SMBus/I2CTiming(continued) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Clocklowperiod 1.3 µs (LOW) t Clockhighperiod(3) 0.6 µs (HIGH) Cumulativeclocklowslaveextend t(LOW:SEXT) time(4) 25 ms 20+0.1 tf Clock/datafalltime Risetimetr=(VILmax–0.15)to(VIHmin+0.15) Cb(5) 300 ns 20+0.1 tr Clock/datarisetime Falltimetf=0.9VDDto(VILmax–0.15) Cb(5) 300 ns C Totalcapacitanceofonebusline 400 pF b (3) t ,Max,istheminimumbusidletime.SMBC=SMBD=1fort>50mscausesresetofanytransactionthatisinprogress.This (HIGH) specificationisvalidwhentheNC_SMBcontrolbitremainsinthedefaultclearedstate(CLK[0]=0). (4) t isthecumulativetimeaslavedeviceisallowedtoextendtheclockcyclesinonemessagefrominitialstarttothestop. (LOW:SEXT) (5) C (pF) b Figure5-1.I2C/SMBus/PMBusTimingDiagram Figure5-2.BusTiminginExtendedMode 5.7 Power Supply Sequencing Copyright©2012–2017,TexasInstrumentsIncorporated Specifications 17 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com V33D 3.3 V Brown Out VGH VGL Vres t IReset TPOR TPOR t undefined Figure5-3.Power-OnReset(POR)andBrown-OutReset(BOR) Table5-2.Power-OnReset(POR)andBrown-OutReset(BOR)TermDefinitions TERM DEFINITION ThisistheV33Dthresholdwheretheinternalpowerisdeclaredgood.TheUCD3138comesoutofresetwhenabove VGH thisthreshold. ThisistheV33Dthresholdwheretheinternalpowerisdeclaredbad.Thedevicegoesintoresetwhenbelowthis VGL threshold. ThisistheV33Dthresholdwheretheinternalresetsignalisnolongervalid.Belowthisthresholdthedeviceisinan V res indeterminatestate. Thisistheinternalresetsignal.Whenlow,thedeviceisheldinreset.Thisisequivalenttoholdingtheresetpinon I Reset theIChigh. T ThetimedelayfromwhenVGHisexceededtowhenthedevicecomesoutofreset. POR ThisistheV33Dvoltagethresholdatwhichthedevicesetsthebrownoutstatusbit.Inadditionaninterruptcanbe Brownout triggeredifenabled. 5.8 Peripherals 5.8.1 Digital Power Peripherals (DPPs) At the core of the UCD3138 controller are three DDPs. Each DPP can be configured to drive from one to eightDPWMoutputs.EachDPPconsistsof: • DifferentialinputerrorADC(EADC)withsophisticatedcontrols • Hardwareaccelerateddigital2-pole/2-zeroPIDbasedcompensator • DigitalPWMmodulewithsupportforavarietyoftopologies These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of supporting functions like input voltage feed forward, current mode control, and constant current/constantpower,andsoforth.Thesimplestconfigurationisshowninthefollowingfigure: 18 Specifications Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 EAP DPWMA ErrorADC Digital Filter EAN (Front End) PWM DPWMB 5.8.1.1 FrontEnd Figure 5-4 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filtersandaprecisionhighresolutionsetpointDACreference.Theprogrammablegainamplifierinconcert withtheEADCandtheadjustabledigitalgainontheEADCoutputworktogethertoprovide9bitsofrange with 6 bits of resolution on the EADC output. The output of the Front End module is a 9-bit sign extended result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE value such that the minimum resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the digital compensator for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, and so forth. Some additional features include the ability to change the polarity of the error measurement and an absolute value mode which automaticallyaddstheDACvaluetotheerror. It is possible to operate the controller in a peak current mode control configuration; front-end 2 is recommended for implementing peak current mode control. In this mode topologies like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified inSection5.5. EAP Front End Differential Amplifier R I EA OFFSET AGND EAN R I EA OFFSET AGND Figure5-4.InputStageofEADCModule Copyright©2012–2017,TexasInstrumentsIncorporated Specifications 19 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com AFE_GAIN 3-AFE_GAIN 2 EAP0 6bitADC 8mV/LSB EAN0 2AFE_GAIN EADC X Averaging Signed9bit result (error)1mV/LSB SAR/Prebias Ramp A0 DAC0 Filter x CPCC 10bit DAC 1.5625mV/LSB S Value Dither 4bit dithering gives14bits of effective resolution 97.65625µV/LSB effective resolution Absolute Value 10bit result Calculation 1.5625mV/LSB Peak Current Detected Peak Current Mode Comparator Figure5-5.FrontEndModule (FrontEnd2RecommendedforPeakCurrentModeControl) 5.8.1.2 DPWMModule The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138 system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations. The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The compensator calculates the necessary duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time.TheresolutionoftheDPWMONtimeis250psec. Each DPWM module can be synchronized to another module or to an external sync signal. An input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of theDPWMoutputsformultiplepowerstagescanbetightlycontrolled. The DPWM logic is probably the most complex of the Digital Peripherals. It takes the output of the compensator and converts it into the correct DPWM output for several power supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers.FaulthandlingiscoveredintheFaultMuxsection. EachDPWMmodulesupportsthefollowingfeatures: • Dedicated14bittime-basewithperiodandfrequencycontrol • Shadowperiodregisterforendofperiodupdates. • Quad-eventcontrolregisters(AandB,risingandfalling)(Events1to4) – Usedforon/offDPWMdutyratioupdates. 20 Specifications Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 • PhasecontrolrelativetootherDPWMmodules • SampletriggerplacementforoutputvoltagesensingatanypointduringtheDPWMcycle. • SupportfortwoindependentedgeplacementDPWMoutputs(samefrequencyorperiodsetting) • Dead-timebetweenDPWMAandBoutputs • HighResolutioncapabilities– 250ps • Pulsecycleadjustmentofupto ±8.192 µs(32768 ×250ps) • Activehigh/activelowoutputpolarityselection • ProvideseventstotriggerbothCPUinterruptsandstartofADC12conversions. 5.8.1.3 DPWMEvents EachDPWMcancontrolthefollowingtimingevents: 1. SampleTriggerCount–ThisregisterdefineswheretheerrorvoltageissampledbytheEADCin relationshiptotheDPWMperiod.Theprogrammedvaluesetintheregistershouldbeonefourthofthe valuecalculatedbasedontheDPWMclock.AstheDCLK(DCLK=62.5MHzmax)controllingthe circuitryrunsatonefourthoftheDPWMclock(PCLK=250MHzmax).Whenthissampletrigger countisequaltotheDPWMCounter,itinitiatesafrontendcalculationbytriggeringtheEADC, resultinginaCLAcalculation,andaDPWMupdate.Oversamplingcanbesetfor2,4,or8timesthe samplingrate. 2. PhaseTriggerCount –countoffsetforslavinganotherDPWM(Multi-Phase/Interleavedoperation). 3. Period –lowresolutionswitchingperiodcount.(countofPCLKcycles) 4. Event1–countoffsetforrisingDPWMAevent.(PCLKcycles) 5. Event2–DPWMcountforfallingDPWMAeventthatsetsthedutyratio.Last4bitsoftheregisterare forhighresolutioncontrol.Upper14bitsarethenumberofPCLKcyclecounts. 6. Event3–DPWMcountforrisingDPWMBevent.Last4bitsoftheregisterareforhighresolution control.Upper14bitsarethenumberofPCLKcyclecounts. 7. Event4–DPWMcountforfallingDPWMBevent.Last4bitsoftheregisterareforhighresolution control.Upper14bitsarethenumberofPCLKcyclecounts. 8. CycleAdjust–ConstantoffsetforEvent2andEvent4adjustments. Basic comparisons between the programmed registers and the DPWM counter can create the desired edgeplacementsintheDPWM.HighresolutionedgecapabilityisavailableonEvents2,3,and4. Figure 5-6 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own registers,notbythefilteroutput.Inotherwords,thepowersupplycontrolloopisnotclosed. The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional DPWMmodesaredescribedbelow. Copyright©2012–2017,TexasInstrumentsIncorporated Specifications 21 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com Multi Mode Open Loop Start of Period Start of Period Period Period Counter DPWM OutputA Event1 Event2(High Resolution) CycleAdjustA (High Resolution) SampleTrigger 1 To Other BlankingABegin Modules BlankingAEnd DPWM Output B Event3(High Resolution) Event4(High Resolution) CycleAdjust B (High Resolution) SampleTrigger 2 Blanking B Begin To Other Blanking B End Modules PhaseTrigger Events which change with DPWM mode: DPWMARising Edge =Event1 DPWMAFalling Edge =Event2+CycleAdjustA DPWM B Rising Edge=Event3 DPWM B Falling Edge=Event4+CycleAdjust B PhaseTrigger =PhaseTrigger Register value Events always set by their registers,regardless of mode: SampleTrigger 1,SampleTrigger 2,BlankingABegin,BlankingAEnd,Blanking B Begin, Blanking B End Figure5-6.MultiModeOpenLoop 5.8.1.4 HighResolutionDPWM Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM edges, the UCD3138 DPWM can generate waveforms with resolutions as small as 250 ps. This is 16×theresolutionoftheclockdrivingtheDPWMmodule. 22 Specifications Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each.ThehighresolutionsectionofDPWMcanbeenabledordisabled,alsotheresolutioncanbedefined in several steps between 4ns to 250ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN, HIRES_SCALE, and ALL_PHASE_CLK_ENA inside the DPWM Control register 1. See the Power Peripheralsprogrammer’smanualfordetails. 5.8.1.5 Oversampling The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 timesperPWMperiod.Thusthetimetheoversamplehappensisatthedivideby2,4,or8timesetinthe sampling register. The 01 setting triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the11triggersoversamplingat8X. 5.8.1.6 DPWMInterruptGeneration The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 triggerforsequencesynchronization.Table5-3outlinesthedivideratiosthatcanbeprogrammed. 5.8.1.7 DPWMInterruptScaling/Range Table5-3.DPWMInterruptDivideRatio SwitchingPeriod InterruptDivide InterruptDivide InterruptDivide Numberof32-MHz Frames(Assume1-MHz Setting Count Count(hex) ProcessorCycles Loop) 1 0 00 1 32 2 1 01 2 64 3 3 03 4 128 4 7 07 8 256 5 15 0F 16 512 6 31 1F 32 1024 7 47 2F 48 1536 8 63 3F 64 2048 9 79 4F 80 2560 10 95 5F 96 3072 11 127 7F 128 4096 12 159 9F 160 5120 13 191 BF 192 6144 14 223 DF 224 7168 15 255 FF 256 8192 Copyright©2012–2017,TexasInstrumentsIncorporated Specifications 23 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 5.9 Typical Temperature Characteristics 2.1 1.81 2 1.79 V) m ze ( 1.9 V) 1.77 B Si ge ( S a C L 1.8 Volt1.75 D A E 1.7 1.73 Minimum Maximum Typical 1.6 1.71 −40 −20 0 20 40 60 80 100 120 -50 0 50 100 150 Temperature (°C) Figure5-7.EADCLSBSizeWith4XGain(mV)vsTemperGa00t5uare Temperature ((cid:131)C) C001 Figure5-8.BP18VoltagevsTemperature ADC12 Measurement Temperature Sensor Voltage ADC12 2.5-V Reference 2.6 2.515 2.510 2.4 2.505 age (V) 2.2 erence 2.500 Volt 2.0 Ref 2.495 or 12 ens 1.8 DC 2.490 S A 2.485 1.6 2.480 1.4 2.475 −60 −40 −20 0 20 40 60 80 100 120 140 160 −40 −20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure5-9.ADC12MeasurementTemperatureSensorVoltaG0g06eb vs Figure5-10.ADC122.5-VReferencevsTemperatureG003b Temperature ADC12 Temperature Sensor Measurement Error UCD3138 Oscillator Frequency 8 2.08 6 2.04 B) e S 4 c Error (L 2 Referen 2 2 Z 1 H ADC 0 2-M 1.96 −2 −4 1.92 −40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure5-11.ADC12TemperatureSensorMeasurementErGr0o02rbvs Figure5-12.UCD3138OscillatorFrequency(2-MHzRefereG0n04cbe, Temperature DividedDownfrom250MHz)vsTemperature 24 Specifications Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 6 Detailed Description 6.1 Overview The UCD3138 family is a digital power supply controller from Texas Instruments offering superior levels of integrationandperformanceinasinglechipsolution.TheUCD3138x,incomparisontoTexasInstruments UCD3138 digital power controller offers 32 kB of program Flash memory. The flexible nature of the UCD3138familymakesitsuitableforawidevarietyofpowerconversionapplications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network infrastructure space. The UCD3138 family is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customer’s development effort through offering best in class development tools, including application firmware, Code Composer StudioTM software development environment, and TI’s Fusion Power Development GUI which enables customers to configure and monitor keysystemparameters. 6.2 ARM Processor The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The Thumb instruction allows for higher code density equivalent to a 16-bit microprocessor, with the performanceofthe32-bitmicroprocessor. The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocksintheARMprocessorincludea32-bitALU,32x8multiplier,andabarrelshifter. 6.3 Memory The UCD3138 (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the memory modules. All of the memory module addresses are sequentially aligned along the same addressrange.Thisappliestoprogramflash,dataflash,ROMandallotherperipherals. Within the UCD3138 architecture, there is a Boot ROM that contains the initial firmware startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the ROM codebranchestothemainFLASH-programexecution. UCD3138 also supports customization of the boot program by allowing an alternative boot routine to be executed from program FLASH. This feature enables assignment of a unique address to each device; therefore, enabling firmware reprogramming even when several devices are connected on the same communicationbus. Two separate FLASH memory areas are present inside the device. The 32 kB Program FLASH is organized as an 8 k x 32 bit memory block and is intended to be for the firmware program. The block is configured with page erase capability for erasing blocks as small as 1kB per page, or with a mass erase for erasing the entire program FLASH array. The FLASH endurance is specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data FLASH array is organized as a 512 x 32 bit memory (32 byte page size). The Data FLASH is intended for firmware data value storage and data logging. Thus, the Data FLASH is specified as a high endurance memory of 20 k cycles with embedded errorcorrectioncode(ECC). Forruntimedatastorageandscratchpadmemory,a4kBRAMisavailable.TheRAMisorganizedasa1 kx32bitarray. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 25 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 6.3.1 CPU Memory Map and Interrupts When the device comes out of power-on-reset, the data memories are mapped to the processor as follows: Table6-1.MemoryMap(AfterResetOperation) Address Size Module 0x0000_0000–0x0000_FFFF 16X4K BootROM In16repeatedblocksof4Keach 0x0001_0000–0x0001_7FFF 32K Programflash 0x0001_8800–0x0001_8FFF 2K Dataflash 0x0001_9000–0x0001_9FFF 4K DataRAM Just before the boot ROM program gives control to FLASH program, the ROM configures the memory as follows: Table6-2.MemoryMap(NormalOperation) Address Size Module 0x0000_0000–0x0000_7FFF 32K Programflash 0x0001_0000–0x0001_AFFF 4K BootROM 0x0001_8800–0x0001_8FFF 2K Dataflash 0x0001_9000–0x0001_9FFF 4K DataRAM Table6-3.MemoryMap(SystemandPeripheralsBlocks) Address Size Module 0x0002_0000-0x0002_00FF 256 LoopMux 0x0003_0000-0x0003_00FF 256 FaultMux 0x0004_0000-0x0004_00FF 256 ADC 0x0005_0000-0x0005_00FF 256 DPWM3 0x0006_0000-0x0006_00FF 256 Filter2 0x0007_0000-0x0007_00FF 256 DPWM2 0x0008_0000-0x0008_00FF 256 FrontEnd/RampI/F2 0x0009_0000-0x0009_00FF 256 Filter1 0x000A_0000-0x000A_00FF 256 DPWM1 0x000B_0000–0x000B_00FF 256 FrontEnd/RampI/F1 0x000C_0000-0x000C_00FF 256 Filter0 0x000D_0000-0x000D_00FF 256 DPWM0 0x000E_0000-0x000E_00FF 256 FrontEnd/RampI/F0 0xFFF7_EC00-0xFFF7_ECFF 256 UART0 0xFFF7_ED00-0xFFF7_EDFF 256 UART1 0xFFF7_F000-0xFFF7_F0FF 256 MiscellaneousAnalogControl 0xFFF7_F600-0xFFF7_F6FF 256 PMBusInterface 0xFFF7_FA00-0xFFF7_FAFF 256 GIO 0xFFF7_FD00-0xFFF7_FDFF 256 Timer 0xFFFF_FD00-0xFFFF_FDFF 256 MMC 0xFFFF_FE00-0xFFFF_FEFF 256 DEC 0xFFFF_FF20-0xFFFF_FF37 23 CIM 0xFFFF_FF40-0xFFFF_FF50 16 PSA 0xFFFF_FFD0-0xFFFF_FFEC 28 SYS 26 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 The registers and bit definitions inside the system and peripheral blocks are detailed in the programmer’s guideforeachperipheral. 6.3.2 Boot ROM TheUCD3138incorporatesa4kbootROM.ThisbootROMincludessupportfor: • ProgramdownloadthroughthePMBus • Deviceinitialization • Examiningandmodifyingregistersandmemory • VerifyingandexecutingprogramFLASHautomatically • Jumpingtoacustomerdefinedbootprogram The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it also jumps to location 0 in the program flash. This permits full automated program memory checking, whenthereisnoneedforacustombootprogram. If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus interface These functions can be used to read and write to all memory locations in the UCD3138. Typically they are usedtodownloadaprogramtoProgramFlash,andtocommanditsexecution 6.3.3 Customer Boot Program As described above, it is possible to generate a user boot program using 2 kB or more of the program flash.ThiscansupportthingswhichtheBootROMdoesnotsupport,including: • Program download via UART – useful especially for applications where the UCD3138 is isolated from thehost(forexample,PFC) • Encrypteddownload–usefulforcodesecurityinfieldupdates. 6.3.4 Flash Management The UCD3138 offers a variety of features providing for easy prototyping and easy flash programming. At the same time, high levels of security are possible for production code, even with field updates. Standard firmware will be provided for storing multiple copies of system parameters in data flash. This is minimizes theriskoflosinginformationifprogrammingisinterrupted. 6.4 System Module The System Module contains the interface logic and configuration registers to control and configure all the memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder, memory management controller, system management unit, central interrupt unit, and clock controlunit. 6.4.1 Address Decoder (DEC) The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map addresses are selectable through configurable register settings. These memory selects can be configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode forusermodeprotection. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 27 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 6.4.2 Memory Management Controller (MMC) The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of addressspacedecoding. 6.4.3 System Management (SYS) The SYS unit contains the software access protection by configuring user privilege levels to memory or peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also available. 6.4.4 Central Interrupt Module (CIM) The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first action in the interrupt service routine. The requestchannelsaremaskable,allowingindividualchannelstobeselectivelydisabledorenabled. Table6-4.InterruptPriorityTable MODULECOMPONENTOR NAME DESCRIPTION PRIORITY REGISTER BRN_OUT_INT Brownout Brownoutinterrupt 0(lowest) EXT_INT Externalinterrupts Interruptonexternalinputpin 1 WDRST_INT Watchdogcontrol Interruptfromwatchdogexceeded(reset) 2 Wakeupinterruptwhenwatchdogequalshalfofset WDWAKE_INT Watchdogcontrol 3 watchtime SCI_ERR_INT UARTorSCIcontrol UARTorSCIerrorInterrupt.Frame,parityoroverrun 4 SCI_RX_0_INT UARTorSCIcontrol UART0RXbufferhasabyte 5 SCI_TX_0_INT UARTorSCIcontrol UART0TXbufferempty 6 SCI_RX_1_INT UARTorSCIcontrol UART1RXbufferhasabyte 7 SCI_TX_1_INT UARTorSCIcontrol UART1TXbufferempty 8 PMBUS_INT PMBusrelatedinterrupt 9 DIG_COMP_INT 12-bitADCcontrol Digitalcomparatorinterrupt 10 “Prebiascomplete”,“RampDelayComplete”,“Ramp FE0_INT FrontEnd0 Complete”,“LoadStepDetected”, 11 “Over-VoltageDetected”,“EADCsaturated” “Prebiascomplete”,“RampDelayComplete”,“Ramp FE1_INT FrontEnd1 Complete”,“LoadStepDetected”, 12 “Over-VoltageDetected”,“EADCsaturated” “Prebiascomplete”,“RampDelayComplete”,“Ramp FE2_INT FrontEnd2 Complete”,“LoadStepDetected”, 13 “Over-VoltageDetected”,“EADCsaturated” PWM3_INT 16-bittimerPWM3 16-bitTimerPWM3counteroverfloworcompareinterrupt 14 16-bitTimerPWM2counterOverfloworcompare PWM2_INT 16-bittimerPWM2 15 interrupt PWM1_INT 16-bittimerPWM1 16-bitTimerPWM1counteroverfloworcompareinterrupt 16 PWM0_INT 16-bittimerPWM0 16-bitTimerPWM1counteroverfloworcompareinterrupt 17 OVF24_INT 24-bittimercontrol 24-bitTimercounteroverflowinterrupt 18 CAPTURE_1_INT 24-bittimercontrol 24-bitTimercapture1interrupt 19 COMP_1_INT 24-bittimercontrol 24-bitTimercompare1interrupt 20 28 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 Table6-4.InterruptPriorityTable(continued) MODULECOMPONENTOR NAME DESCRIPTION PRIORITY REGISTER CAPTURE_0_INT 24-bittimercontrol 24-bitTimercapture0interrupt 21 COMP_0_INT 24-bittimercontrol 24-bitTimercompare0interrupt 22 ModeswitchedinCPCCmoduleFlagneedstoberead CPCC_INT Constantpowerconstantcurrent 23 fordetails ADC_CONV_INT 12-bitADCcontrol ADCendofconversioninterrupt 24 Analogcomparatorinterrupts,overvoltagedetection, FAULT_INT FaultMuxinterrupt 25 undervoltagedetection,LLMloadstepdetection DPWM3 DPWM3 SameasDPWM1 26 DPWM2 DPWM2 SameasDPWM1 27 1)Every(1to256)switchingcycles DPWM1 DPWM1 2)Faultdetection 28 3)Modeswitching DPWM0 DPWM0 SameasDPWM1 29 EXT_FAULT_INT ExternalFaults Faultpininterrupt 30 SYS_SSI_INT SystemSoftware Systemsoftwareinterrupt 31(highest) 6.5 Feature Description 6.5.1 Sync FET Ramp and IDE Calculation The UCD3138 has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This comesintwoforms: • SyncFETramp • IdealDiodeEmulation(IDE)calculation When starting up a power supply, sometimes there is already a voltage on the output – this is called prebias. It is very difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated correctly,itmaypulldowntheprebiasvoltage,causingthepowersupplytosinkcurrent. To avoid this, Sync FETs are not turned on until after the power supply has ramped up to the nominal voltage. The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET Ramplogiccanbeusedtoturnthemonataratebelowthebandwidthofthefilter. Indiscontinuousmode,theidealon-timefortheSyncFETsisafunctionofVin,Vout,andtheprimaryside duty cycle (D). The IDE logic in the UCD3138 takes Vin and Vout data from the firmware and combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the Sync FETs. 6.5.2 Automatic Mode Switching Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware intervention. This is useful to increase efficiency and power range. The following paragraphs describephase-shiftedfullbridgeandLLCexamples: 6.5.2.1 PhaseShiftedFullBridgeExample In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather thanphaseshift,atlightload.Thisisshownbelow: Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 29 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com DPWM3A (QB1) DPWM3B (QT1) DPWM2A (QT2) DPWM2B (QB2) VTrans DPWM1B (QSYN1,3) DPWM0B (QSYN2,4) IPRI Figure6-1.PhaseShiftedFullBridge 30 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 T1 L1 Q7 +12V Q6 VBUS I_pri C1 RL PRIM CURRENT ORING CTL T2 Q5 VOUT C2 QT1 D1 QT2 R2 VA Lr T1 Current Sensing QB1 D2 QB2 Vref Duty for mode DPWM0 DPWM0B switching Vout EADC0 CLA0 CPCC < DPWM1 DPWM1B Iout EADC1 CLA1 DPWM2A Load Current DPWM2 DPWM2B I_pri EADC2 PCM DPWM3 DDPPWWMM33AB ISOLATED AD00 FAULT0 ACFAIL_IN GATETransformer SYNCHRONOUS AD01 GATE DRIVE I_SHARE AD02/CMP0 FAULT FAULT1 ACFAIL_OUT DPWM3A DPWM3B DPWM2A DPWM2B DPWM0B DPWM1B VII_oopuurtti AD0AAA3DDD/C000456M///CCCP1MMM/CPPPM345P2 CBC FAGGUPPLIIOTO212 OOFNAR/IOILNUFGRF_ECRTL temp AD07/CMP6 Vin AD08 GPIO3 P_GOOD VA AD09 ARM7 WD PMBus RST OSC UART0 Primary UART1 Memory Figure6-2.Secondary-ReferencedPhase-ShiftedFullBridgeControl WithSynchronousRectification 6.5.2.2 LLCExample In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse widthofDPWMA.HerearethewaveformsfortheLLC: PWM Mode LLC Mode fr fs=fr_max fs>fr fs<fr y Q1T ar m Pri Q1B ET QSR1 Tr=1/fr F n SyQSR2 Tr=1/fr ISEC(t) Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 31 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com VBUS Q1T ILR(t) Transformer LRES LK QSR2 RLRES NS ISEC(t) Driver DPWM1B Oring Circuitry Q1B ILM(t) LM NP VOUT RF1 AD03 NS COUT1 COUT2 EAP0 VOUT(t) VBUS ESR1 ESR2 RF2 CF QSR1 CRES Rectifier and filter AD04 Driver DPWM1A RS EAN0 CS VCR(t) CRES RS1 RS2 ADC13 Driver DPWM0B EAP1 Driver DPWM0A Figure6-3.Secondary-ReferencedHalf-BridgeResonantLLCControl WithSynchronousRectification 32 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 6.5.2.3 MechanismforAutomaticModeSwitching The UCD3138 allows the customer to enable up to two distinct levels of automatic mode switching. These differentmodesareusedtoenhancelightloadoperation,shortcircuitoperationandsoftstart.Manyofthe configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, someoftheseparametersareduplicatedintheAutoConfigMidandAutoConfigHighregisters. If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is used. There are 4 registers which are used to select the points at which the mode switching takesplace.Theyareusedasshownbelow. Automatic Mode Switching With Hysteresis Filter Duty Full Range Auto Config High High–UpperThreshold High–LowerThreshold Auto Config Mid Low–UpperThreshold Low–LowerThreshold Control Register 1 0 Figure6-4.AutomaticModeSwitching As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modesifthefilterdutyisclosetoamodeswitchingpoint. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 33 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 6.5.3 DPWMC, Edge Generation, IntraMux The UCD3138 has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveformsalreadydiscussed– DPWMC,theEdgeGenerationModule,andtheIntraMux. DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the BlankingAendtime. The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM.Eachedge(risingandfallingforDPWMAandDPWMB)has8optionswhichcancauseit. Theoptionsare: 0=DPWM(n)ARisingedge 1=DPWM(n)AFallingedge 2=DPWM(n)BRisingedge 3=DPWM(n)BFallingedge 4=DPWM(n+1)ARisingedge 5=DPWM(n+1)AFallingedge 6=DPWM(n+1)BRisingedge 7=DPWM(n+1)BFallingedge Where“n"isthenumericalindexoftheDPWMmoduleofinterest.Forexamplen=1referstoDPWM1. TheEdgeGeniscontrolledbytheDPWMEDGEGENregister.Italsohasanenable/disablebit. The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are controlled with automatic mode switching. Of course, it can all be disabled, and DPWMA and DPWMB will be driven as described in the sections above. If the Intra Mux is enabled, high resolutionmustbedisabled,andDPWMedgeresolutiongoesdownto4ns. HereisadrawingoftheEdgeGen/IntraMux: A/B/C(N) A/B/C(N+1) C(N+2) INTRAMUX C(N+3) PWMA EDGE GEN PWM B A(N) EGENA B(N) EGEN B A(N+1) B(N+1) B SELECT ASELECT AON SELECT AOFF SELECT B ON SELECT B OFF SELECT Figure6-5.EdgeGen/IntraMux HereisalistoftheIntraMuxmodesforDPWMA: 0=DPWMA(n)passthrough(default) 1=Edge-genoutput,DPWMA(n) 2=DPWNC(n) 3=DPWMB(n)(Crossover) 34 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 4=DPWMA(n+1) 5=DPWMB(n+1) 6=DPWMC(n+1) 7=DPWMC(n+2) 8=DPWMC(n+3) andforDPWMB: 0=DPWMB(n)passthrough(default) 1=Edge-genoutput,DPWMB(n) 2=DPWNC(n) 3=DPWMA(n)(Crossover) 4=DPWMA(n+1) 5=DPWMB(n+1) 6=DPWMC(n+1) 7=DPWMC(n+2) 8=DPWMC(n+3) TheDPWMnumberwrapsaroundjustliketheEdgeGenunit.ForDPWM3thefollowingdefinitionsapply: DPWM(n) DPWM3 DPWM(n+1) DPWM0 DPWM(n+2) DPWM1 DPWM(n+3) DPWM2 6.5.4 Filter The UCD3138 filter is a PID filter with many enhancements for power supply control. Some of its features include: • TraditionalPIDArchitecture • Programmable non-linear limits for automated modification of filter coefficients based on received EADCerror • Multiplecoefficientsetsfullyconfigurablebyfirmware • Full24-bitprecisionthroughoutfiltercalculations • Programmableclampsonintegratorbranchandfilteroutput • Abilitytoloadvaluesintointernalfilterregisterswhilesystemisrunning • Abilitytostallcalculationsonanyoftheindividualfilterbranches • Abilitytoturnoffcalculationsonanyoftheindividualfilterbranches • Dutycycle,resonantperiod,orphaseshiftgenerationbasedonfilteroutput. • Fluxbalancing • Voltagefeedforward Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 35 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com HereisthefirstsectionoftheFilter: Limit Comparator Limit6 Limit5 ….. PID Filter Branch Stages Limit0 Kp Coef Coefficient select EADC_DATA <> Xn 16 9 24 24 X P Xn-1 Reg Ki Coef Ki_yn reg 9 9 Ki High Optional 16 24 Selbeycted 9 9 9 24 24 24 24 + X + Clamp I KI_ADDER_ 24 MODE 24 Ki Low Kd alpha 9 24 Kd coef X Kd yn_reg 32 24 9 Round 16 24 9 - Xn–Xn-1 9 X 24 + 24 Clamp 24 D Figure6-6.FirstSectionoftheFilter The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alphapole. The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errorstoimprovetransientresponse. Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits): FilterYn Yn Scale Clamp High 24 P 24 I + 26 24 24 24 FilterYn Saturate Yn Shifter Clamp 24 D S2.23 S0.23 S0.23 S0.23 All are S0.23 FilterYn Clamp Low Figure6-7.OutputSectionoftheFilter 36 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 ThissectioncombinestheP,I,andDsections,andprovidesforsaturation,scaling,andclamping. Thereisafinalsectionforthefilter,whichpermitsitsoutputtobematchedtotheDPWM: Round to FilterYN X 38 18bits, 18 Truncate 14 Filter Period 24 S0.23 S14.23 Clamp to 14.4 low 4bits Bits[17:4] 14.0 Positive KCompx 14.0 14 DPWMx Period 14.0 14.0 PERIOD_MULT_SEL Figure6-8.FinalSectionfortheFilter This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, toprovideforVoltageFeedForward,orforotherpurposes.Afterthis,thereisanotherclamp.Forresonant mode,thefiltercanbeusedtogeneratebothperiodanddutycycle. Filter Output Clamp High Round to FilterYN(Duty%) X 38 18bits, 18 18 Filter Duty Clamp 24 S0.23 S14.23 Clamp to 14.4 14.4 Positive KCompx 14.0 14 Filter Output DPWMx Period 14.0 Clamp Low Loop_VFF 14.0 14.0 Resonant Duty 14.0 OUTPUT_MULT_SEL Figure6-9.ResonantMode 6.5.4.1 LoopMultiplexer The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, andDPWMcanbecombinedwitheachotherinmanyconfigurations. Italsocontrolsthefollowingconnections: • DPWMtoFrontEnd • FrontEndDACcontrolfromFiltersorConstantCurrent/ConstantPowerModule • FilterSpecialCoefficientsandFeedForward • DPWMsynchronization • FiltertoDPWM ThefollowingcontrolmodulesareconfiguredintheLoopMux: • ConstantPower/ConstantCurrent Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 37 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com • CycleAdjustment(Currentandfluxbalancing) • GlobalPeriod • LightLoad(BurstMode) • AnalogPeakCurrentMode 6.5.4.2 FaultMultiplexer In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138providesanextensivearrayofmultiplexersthatareunitedunderthenameFaultMuxmodule. The Fault Mux Module supports the following types of mapping between all the sources of fault and all differentfaultresponsemechanisminsideeachDPWMmodule. • Many fault sources mapped to a single fault response mechanism. For instance an analog comparator in charge of over voltage protection, a digital comparator in charge of over current protection and an external digital fault pin can be all mapped to a fault-A signal connected to a single FAULT MODULE andshutdownDPWM1-A. • A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For instance an analog comparator in charge of over current protection can be mapped to DPWM-0throughDPWM-3bywayofseveralfaultmodules. • ManyfaultsourcescanbemappedtomanyfaultmodulesinsidemanyDPWMmodules. 38 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 FAULT MUX CBC_PWM_AB_EN DPWM Bit20in DPWMCTRL0 CYCLE BYCYCLE ANALOG PCM FAULT-CBC AB FLAG FAULTMODULE DISABLE PWMAAND B CBC_FAULT_EN Bit30in DPWMFLTCTRL FAULT-AB AB FLAG FAULTMODULE DISABLE PWMAAND B DCOMP–4X EXTGPIO–4X ACOMP–7X FAULT-A AFLAG FAULTMODULE DISABLE PWMAONLY FAULT-B FAULTMODULE B FLAG DISABLE PWM B ONLY ALL_FAULT_EN DPWM_EN Bit 31in DPWMFLTCTRL Bit0in DPWMCTRL0 The Fault Mux Module provides a multitude of fault protection functions within the UCD3138 high-speed loop (front end control, filter, DPWM and loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of thefaulteventsprovidedintheFaultMuxModule. Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB faultmodule,AfaultmoduleandBfaultmodule. The internal circuitry in all the four fault modules is identical, and the difference between the modules is limitedtothewaythemodulesareattachedtotheDPWMs. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 39 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com FAULTIN FAULTFLAG FAULT MODULE T N N N E E COU ULT WM AX FA DP M Figure6-10.FaultModule All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of the fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle faultscountexceedsmax_count. Once the fault flag is set DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags. NOTE All four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules)willbeclearedsimultaneously. All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module cannotbeenabled/disabledseparately. FAULT- CBC CLIM CYCLE BYCYCLE Figure6-11.CyclebyCycleBlock Unlikefaultmodules,onlyonecyclebycycleblockisavailableineachDPWMmodule. The cycle by cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to signalsarrivingfromanalogpeakcurrentmode(PCM)module. ThefaultMuxmodulesupportsthefollowingbasicfunctions: • 4digitalcomparatorswithprogrammablethresholdsandfaultgeneration • Configurationfor7high-speedanalogcomparatorswithprogrammablethresholdsandfaultgeneration • ExternalGPIOdetectioncontrolwithprogrammablefaultgeneration • Configurable DPWM fault generation for DPWM current limit fault, DPWM overvoltage detection fault, DPWMAexternalfault,DPWMBexternalfaultandDPWMIDEflag • Clockfailuredetectionforhighandlowfrequencyoscillatorblocks • Discontinuousconductionmodedetection 40 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 HFO/LFO DCM Detection Fail Detect Analog Comparator 0 Analog Control Comparator 0 Digital Comparator 0 Front End Control Control 0 Analog Comparator 1 Analog Control Comparator 1 Digital Comparator 1 Control Front End Control1 Analog Comparator 2 Analog Control Comparator 2 Digital Comparator 2 Control Analog Comparator 3 Analog Front End Control Comparator 3 Control2 Digital Comparator 3 Control Analog Comparator 4 Analog fault[2:0] ExternalGPIO Control Comparator 4 Detection Analog Comparator 5 Analog Control Comparator 5 DPWM 0 DPWM 1 DPWM 2 DPWM 3 Fault Control Fault Control Fault Control Fault Control Analog Comparator 6 Analog Control Comparator 6 DPWM 0 DPWM 1 DPWM 2 DPWM 3 Analog Comparator Automated Ramp Figure6-12.FaultMuxBlockDiagram 6.5.5 Communication Ports 6.5.5.1 SCI(UART)SerialCommunicationInterface A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous start- stop serial data communication (see the pin out sections for details) Each interface has a 24 bit for supporting programmable baud rates and has programmable data word and stop bit options. Half or full duplex operation is configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used. 6.5.5.2 PMBUS The PMBus Interface supports independent master and slave modes controlled directly by firmware through a processor bus interface. Individual control and status registers enable firmware to send or receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I2C Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol Specification. The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading andwritingofdataandactive-lowwriteandoutputenablecontrolsignals.Inaddition,thePMBusInterface connectsdirectlytotheI2C/SMBus/PMBusClock,Data,Alert,andControlsignals. Example:PMBusAddressDecodeviaADC12Reading The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding. At power-up the device applies I to each address detect pin and the voltage on that pin is BIAS capturedbytheinternal12-bitADC. Wherebin(V )istheaddressbinforoneof12addressasshowninFigure6-13. AD0x Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 41 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com Vdd AD00, AD01 pin On/Off Control IBIAS Resistor to set PMBus Address ToADC Mux Figure6-13.PMBusAddressDetectionMethod 6.5.5.3 GeneralPurposeADC12 TheADC12isa12bit,highspeedanalogtodigitalconverter,equippedwiththefollowingoptions: • Typicalconversionspeedof267ksps • Conversionscanconsistfrom1to16ADCchannelconversionsinanydesiredsequence • Postconversionaveragingcapability,rangingfrom4X,8X,16Xor32Xsamples • Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge, ADC_EXT_TRIGpinorAnalogComparatorresults • InterruptcapabilitytoembeddedprocessoratcompletionofADCconversion • Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data oraveragedADCdata • Two10µAcurrentsourcesforexcitationofPMBusaddressingresistors • Dualsampleandholdforaccuratepowermeasurement • Internaltemperaturesensorfortemperatureprotectionandmonitoring The control module ADC12 Contol Block Diagram contains the control and conversion logic for auto- sequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value is stored in the result register associated with the sequence number. Input channelscanbesampledinanydesiredorderorprogrammedtorepeatconversionsonthesamechannel multiple times during a conversion sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels convertedinasequencecanvaryfrom1to16. Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best suited for monitoring and detection of currents, voltages, temperatures and faults. PleaseseetheTypicalCharacteristicsplotsforthetemperaturevariationassociatedwiththisfunction. 42 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 ADC12 Block ADC12 Registers ADC Averaging 1122--bbiitt SSAARR S/H ADC AADDCC Channels ADC12 Control Digital Comparators ADC Channel ADC External Trigger (from pin) DPWM Analog Modules Comparators Figure6-14.ADC12ControlBlockDiagram 6.5.5.4 Timers External to the Digital Power Peripherals there are 3 different types of timers in UCD3138. They are the 24-bittimer,16-bittimerandtheWatchdogtimer 6.5.5.4.1 24-bitPWMTimer There is one 24 bit counter PWM timer which runs off the Interface Clock and can further be divided down by an 8-bit pre-scalar to generate a slower PWM time period. The timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, the timer has a shadow register (Data Buffer register) which can be used to store CPU updates of the compare events while still using the timer. Theselectedshadowregisterupdatemodehappensafterthecompareeventmatches. The two capture pins TCMP0 and TCMP1 are inputs for recording a capture event. A capture event can beseteithertorising,falling,orbothedgesofthecapturepin.Uponthisevent,thecountervalueisstored inthecorrespondingcapturedataregister. The counter reset can be configured to happen on a counter roll over, a compare equal event, or by software controlled register. Five Interrupts from the PWM timer can be set, which are the counter rollover event (overflow), either capture event 0 or 1, or the two comparison match events. Each interrupt can be disabledorenabled. Uponaneventcomparisonononlythesecondevent,theTCMPpincanbeconfiguredtoset,clear,toggle or have no action at the output. The value of PWM pin output can be read for status or simply configured as general purpose I/O for reading the value of the input at the pin. The first compare event can only be usedasaninterrupt. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 6.5.5.4.2 16-BitPWMTimers There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register) which can be used to store CPU updates of compare events while still using the timer.Theselectedshadowregisterupdatemodehappensafterthecompareeventmatches. The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or by the two comparison match events. Each comparison match and the overflow interrupts canbedisabledorenabled. Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O forreadingthevalueoftheinputatthepin. 6.5.5.4.3 WatchdogTimer A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine. On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled state.Ahalftimerflagisalsoprovidedforstatusmonitoringofthewatchdog. 6.5.6 Miscellaneous Analog The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a wide variety of functions. These functions include device supervisory features such as Brown-Out and power saving configuration, general purpose input/output configuration and interfacing, internal temperaturesensorcontrolandcurrentsharingcontrol. The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually usedatthetimeoftrimmingatmanufacturing;thereforethisdocumentwillnotcoverthesetrimcontrols. The MAC registers and peripherals are all available in the UCD3138 (64 pin version). Other UCD3138 devicesmayhavereducedresources.Seethedevicepinoutdescriptionfordetails. 6.5.7 Package ID Information Package ID register includes information regarding the package type of the device and can be read by firmwareforreportingthroughPMBusorforotherpackagesensitivedecisions. BITNUMBER 1:0 BitName PKG_ID Access R/W 0–UCD3138RGC, Default 1–UCD3138RHA 6.5.8 Brownout Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a conditionthatmaybeconsideredunsafeforproperoperationofthedevice. The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lowerthanbrownoutthreshold,itstilldoesnotnecessarilytriggeradevicereset. 44 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by aninterruptserviceroutine.PleaseseethePowerOnReset(POR)/BrownOutReset(BOR) section. 6.5.9 Global I/O Up to 30 pins in UCD3138 can be configured to serve as a general purpose input or output pin (GPIO). ThisincludesalldigitalinputoroutputpinsexceptfortheRESETpin. The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins,EADCanaloginputpinsandtheRESETpin. TherearetwowaystoconfigureandusethedigitalpinsasGPIOpins: 1. ThroughthecentralizedGlobalI/Ocontrolregisters. 2. Throughthedistributedcontrolregistersinthespecificperipheralthatsharesitpinswiththestandard GPIOfunctionality. TheGlobalI/Oregistersofferfullcontrolof: 1. ConfiguringeachpinasaGPIO. 2. Settingeachpinasinputoroutput. 3. Readingthepin’slogicstate,ifitisconfiguredasaninputpin. 4. Settingthelogicstateofthepin,ifitisconfiguredasanoutputpin. 5. Configuringpin/pinsasopendrainorpush-pull(Normal) The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain ControlRegister,GlobalI/OValueRegisterandGlobalI/OReadRegister. ThefollowingisshowingtheformatofGlobalI/OENRegister(GLBIOEN)asanexample: BITNUMBER 29:0 BitName GLOBAL_IO_EN Access R/W Default 00_0000_0000_0000_0000_0000_0000_0000 Bits29-0:GLOBAL_IO_EN –ThisregisterenablestheglobalcontrolofdigitalI/Opins 0=ControlofIOisdonebythefunctionalblockassignedtotheIO(Default) 1=ControlofIOisdonebyGlobalIOregisters. PINNUMBER BIT PIN_NAME UCD3138-64PIN UCD3138-40PIN 29 FAULT[3] 43 NA 28 ADC_EXT_TRIG 12,26 8 27 TCK 37 21 26 TDO 38 20 25 TMS 40 24 24 TDI 39 23 23 SCI_TX[1] 29 NA 22 SCI_TX[0] 14 22 21 SCI_RX[1] 30 NA 20 SCI_RX[0] 13 23 19 TMR_CAP 12,26,41 8,21 18 TMR_PWM[1] 32 NA 17 TMR_PWM[0] 12,26,31,37 21 16 PMBUS-CLK 15 9 15 PMBUS-DATA 16 10 Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com PINNUMBER BIT PIN_NAME UCD3138-64PIN UCD3138-40PIN 14 CONTROL 30 20 13 ALERT 29 19 12 EXT_INT 26,34 NA 11 FAULT[2] 42 25 10 FAULT[1] 36 23 9 FAULT[0] 35,39 22 8 SYNC 12,26,37 8,21 7 DPWM3B 24 18 6 DPWM3A 23 17 5 DPWM2B 22 16 4 DPWM2A 21 15 3 DPWM1B 20 14 2 DPWM1A 19 13 1 DPWM0B 18 12 0 DPWM0A 17 11 6.5.10 Temperature Sensor Control Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities.Theinternaltemperaturesensorisdisabledasdefault. Temp Cal Temperature ADC 12 Sensor Ch14 Figure6-15.InternalTempSensor Temperaturesensoriscalibratedatroomtemperature(25 °C)viaacalibrationregistervalue. The temperature sensor is measured using ADC12 (via Ch14). The temperature is then calculated using a mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement). Thetemperaturesensorcanbeenabledordisabled. 6.5.11 I/O Mux Control In different packages of UCD3138 several I/O functions are multiplexed and routed toward a single physical pin. I/O Mux Control register may be used in order to choose a single specific functionality that is desiredtobeassignedtoaphysicaldevicepinforyourapplication. 6.5.12 Current Sharing Control UCD3138providesthreeseparatemodesofcurrentsharingoperation. • Analogbuscurrentsharing 46 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 • PWMbuscurrentsharing • Master/Slavecurrentsharing • AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current- sharebusifpowerismissingfromtheUCD3138 Thesimplifiedcurrentsharingcircuitryisshowninthedrawingbelow: 3.3 V I SHARE SW3 Digital 3.3 V 3.3V ESD 400Ω 3.2kΩ 250Ω AD02 AD13 SW2 ESD SW1 ESD 250Ω EXTCAP R SHARE ADC12 and ADC12 and CMP CMP Figure6-16.SimplifiedCurrentSharingCircuitry FORTESTONLY, CURRENTSHARINGMODE CS_MODE EN_SW1 EN_SW2 DPWM ALWAYSKEEP00 OfforSlaveMode(3-state) 00 00(default) 0 0 0 PWMBus 00 01 1 0 ACTIVE OfforSlaveMode(3-state) 00 10 0 0 0 AnalogBusorMaster 00 11 0 1 0 The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be controlledthroughthecurrentsharingcontrolregister(CSCTRL). 6.5.13 Temperature Reference The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internaltemperaturesensor(channel14)duringthefactorytrimandcalibration. This information can be used by different periodic temperature compensation routines implemented in the firmware.Butitshouldnotbeoverwrittenbyfirmware,otherwisethisfactorywrittenvaluewillbelost. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 6.6 Device Functional Modes The DPWM is a complex logic system which is highly configurable to support several different power supply topologies. The discussion below will focus primarily on waveforms, timing and register settings, ratherthanonlogicdesign. The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts overagain. The DPWM logic causes transitions in many digital signals when the period counter hits the target value forthatsignal. 6.6.1 Normal Mode In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies,amongothers.HereisadrawingoftheNormalModewaveforms: 48 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 Normal Mode Closed Loop Start of Period Start of Period Period Period Counter Filter controlled edge DPWM OutputA Event1 Filter Duty(High Resolution) CycleAdjustA (High Resolution) Adaptive SampleTriggerA Adaptive SampleTrigger B SampleTrigger 1 BlankingABegin To Other Modules BlankingAEnd DPWM Output B Event3–Event2(High Res) Event4(High Res) SampleTrigger 2 Blanking B Begin To Other Blanking B End Modules PhaseTrigger Events which change with DPWM mode: DPWMARising Edge =Event1 DPWMAFalling Edge =Event1+Filter Duty+CycleAdjustA Adaptive SampleTriggerA =Event1+Filter Duty+Adaptive Sample Register or Adaptive SampleTrigger B =Event1+Filter Duty/2+Adaptive Sample Register DPWM B Rising Edge=Event1+Filter Duty+CycleAdjustA + (Event3–Event2) DPWM B Falling Edge=Event4 PhaseTrigger =PhaseTrigger Register value or Filter Duty Events always set by their registers,regardless of mode: SampleTrigger 1,SampleTrigger 2,BlankingABegin,BlankingAEnd,Blanking B Begin,Blanking B End Figure6-17.NormalModeClosedLoop Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for externaldelays,suchasMOSFETandgatedriverturnontimes. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. Theotheredgesaredynamic,soblankingismoredifficult. CycleAdjustBhasnoeffectinNormalMode. 6.6.2 Phase Shifting In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The phase shift signal has two possible sources. It can come from the Phase Shift register. This provides a fixedvalue,whichisusefulforaninterleavedPFC,forexample. The phase shift value can also come from the filter output. In this case, the changes in the filter output causes changes in the phase relationship of two DPWM modules. This is useful for phase shifted full bridgetopologies. Thefollowingfigureshowsthemechanismofphaseshift: Phase Shift DPWM0Start of Period DPWM0Start of Period Period Counter DPWM1Start of Period DPWM1Start of Period Period Counter PhaseTrigger=PhaseTrigger Register value or Filter Duty Figure6-18.PhaseShift 50 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 6.6.3 DPWM Multiple Output Mode Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and withdifferentcycleadjustsforeachphase. HereisadiagramforMulti-Mode: Multi Mode Closed Loop Start of Period Start of Period Period Period Counter Filter controlled edge DPWM OutputA Event1 Filter Duty(High Resolution) CycleAdjustA (High Resolution) Adaptive SampleTriggerA Adaptive SampleTrigger B SampleTrigger1 To Other BlankingABegin Modules BlankingAEnd DPWM Output B Event3(High Resolution) Filter Duty(High Resolution) CycleAdjust B(High Resolution) SampleTrigger2 Blanking B Begin To Other Blanking B End Modules PhaseTrigger Events which change with DPWM mode: DPWMARising Edge =Event1 DPWMAFalling Edge =Event1+Filter Duty+CycleAdjustA Adaptive SampleTriggerA =Event1+Filter Duty+Adaptive Sample Register or Adaptive SampleTrigger B=Event1+Filter Duty/2+Adaptive Sample Register DPWM B Rising Edge=Event3 DPWM B Falling Edge=Event3+Filter Duty+CycleAdjust B PhaseTrigger=PhaseTrigger Register value or Filter Duty Events always set by their registers,regardless of mode: SampleTrigger1,SampleTrigger2,BlankingABegin,BlankingAEnd,Blanking B Begin,Blanking B End Figure6-19.MultiModeClosedLoop Event2andEvent4arenotrelevantinMultimode. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulsewidthoperationispossible.DPWMAcannotcrossovertheperiodboundary. Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blankingthisrisingedge. And,ofcourse,CycleAdjustBisusableonDPWMB. 6.6.4 DPWM Resonant Mode This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As theswitchingfrequencychanges,thedeadtimesbetweenthepulsesremainthesame. The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as describedinSection6.5.2.2.Hereisadiagramofthismode: ResonantSymmetricalClosedLoop StartofPeriod StartofPeriod FilterPeriod PeriodCounter Filtercontrollededge DPWMOutputA Event1 FilterDuty–AverageDeadTime AdaptiveSampleTriggerA AdaptiveSampleTriggerB SampleTrigger1 BlankingABegin ToOther Modules BlankingAEnd DPWMOutputB Event3-Event2 PeriodRegister–Event4 SampleTrigger2 BlankingBBegin ToOther BlankingBEnd Modules PhaseTrigger EventswhichchangewithDPWMmode: DeadTime1=Event3–Event2 DeadTime2=Event1+PeriodRegister–Event4) AverageDeadTime=(DeadTime1+DeadTime2)/2 DPWMARisingEdge=Event1 DPWMAFallingEdge=Event1+FilterDuty–AverageDeadTime AdaptiveSampleTriggerA=Event1+FilterDuty+AdaptiveSampleRegister AdaptiveSampleTriggerB=Event1+FilterDuty/2+AdaptiveSampleRegister DPWMBRisingEdge=Event1+FilterDuty–AverageDeadTime+(Event3–Event2) DPWMBFallingEdge=FilterPeriod–(PeriodRegister–Event4) PhaseTrigger=PhaseTriggerRegistervalueorFilterDuty Eventsalwayssetbytheirregisters,regardlessofmode: SampleTrigger1,SampleTrigger2,BlankingABegin,BlankingAEnd,BlankingBBegin, BlankingBEnd Figure6-20.ResonantSymmetricalClosedLoop 52 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the Filter Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed regardlessoftheperiod.Theonlyedgewhichisfixedrelativetothestartoftheperiodistherisingedgeof DPWMA.Thisistheonlyedgeforwhichtheblankingsignalscanbeusedeasily. 6.6.5 Triangular Mode Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In TriangularMode,onlyDPWM-Bisavailable.HereisadiagramforTriangularMode: Triangular Mode Closed Loop Start of Period Start of Period Period Period Counter DPWM OutputA SampleTrigger1 To Other BlankingABegin Modules BlankingAEnd Filter controlled edge DPWM Output B CycleAdjustA(High Resolution) CycleAdjust B(High Resolution) Filter Duty/2(High Resolution) Period/2 SampleTrigger2 Blanking B Begin To Other Blanking B End Modules PhaseTrigger Events which change with DPWM mode: DPWMARising Edge=None DPWMAFalling Edge=None Adaptive SampleTrigger=None DPWM B Rising Edge=Period/2-Filter Duty/2+CycleAdjustA DPWM B Falling Edge=Period/2+Filter Duty/2+CycleAdjust B PhaseTrigger=PhaseTrigger Register value or Filter Duty Events always set by their registers,regardless of mode: SampleTrigger1,SampleTrigger2,BlankingABegin,BlankingAEnd,Blanking B Begin,Blanking B End Figure6-21.TriangularModeClosedLoop All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, becausethecenteroftheon-timedoesnotmoveinthismode. Copyright©2012–2017,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 6.6.6 Leading Edge Mode Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the LeadingEdgeMode: Leading Edge Closed Loop Start of Period Start of Period Period Period Counter DPWM OutputA Event1 Filter Duty(High Resolution) CycleAdjustA (High Resolution) Adaptive SampleTriggerA Adaptive SampleTrigger B SampleTrigger1 To Other BlankingABegin Modules BlankingAEnd DPWM Output B Event2-Event3(High Resolution) Event4(High Resolution) SampleTrigger2 Blanking B Begin To Other Blanking B End Modules PhaseTrigger Events which change with DPWM mode: DPWMAFalling Edge =Event1 DPWMARising Edge =Event1-Filter Duty+CycleAdjustA Adaptive SampleTriggerA =Event1-Filter Duty+Adaptive Sample Register or Adaptive SampleTrigger B=Event1-Filter Duty/2+Adaptive Sample Register DPWM B Rising Edge=Event4 DPWM B Falling Edge=Event1-Filter Duty+CycleAdjustA -(Event2–Event3) PhaseTrigger=PhaseTrigger Register value or Filter Duty Events always set by their registers,regardless of mode: SampleTrigger1,SampleTrigger2,BlankingABegin,BlankingAEnd,Blanking B Begin,Blanking B End Figure6-22.LeadingEdgeClosedLoop As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervalsaremainlyusefulfortheedgesatthebeginningandendoftheperiod. 54 DetailedDescription Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 7 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 7.1 Application Information The UCD3138x has an extensive set of fully-programmable, high-performance peripherals that make it suitable for a wide range of power supply applications. In order to make the part easier to use, TI has prepared an extensive set of materials to demonstrate the features of the device for several key applications.Ineachcasethefollowingitemsareavailable: 1. FullfeaturedEVMhardwarethatdemonstratesclassicpowersupplyfunctionality. 2. AnEVMuserguidethatcontainsschematics,bill-of-materials,layoutguidanceandtestdata showcasingtheperformanceandfeaturesofthedeviceandthehardware. 3. Afirmwareprogrammersmanualthatprovidesastep-by-stepwalkthroughofthecode. Table7-1.ApplicationInformation APPLICATION EVMDESCRIPTION ThisEVMdemonstratesaPSFBDC-DCpowerconverterwithdigitalcontrolusingtheUCD3138xdevice.Controlis implementedbyusingPCMCwithslopecompensation.Thissimplifiesthehardwaredesignbyeliminatingtheneed foraseriesblockingcapacitorsandprovidingtheinherentinputvoltagefeed-forwardthatcomesfromPCMC.The Phaseshiftedfull controllerislocatedonadaughtercardandrequiresfirmwareinordertooperate.Thisfirmware,alongwiththeentire bridge sourcecode,ismadeavailablethroughTI.Afree,customfunctionGUIisavailabletohelptheuserexperimentwith thedifferenthardwareandsoftwareenabledfeatures.TheEVMacceptsaDCinputfrom350VDCto400VDC,and outputsanominal12VDCwithfullloadoutputpowerof360W,orfulloutputcurrentof30A. This EVM demonstrates an LLC resonant half-bridge DC-DC power converter with digital control using the UCD3138x device. The controller is located on a daughter card and requires firmware in order to operate. This LLCresonant firmware,alongwiththeentiresourcecode,ismadeavailablethroughTI.Afree,customfunctionGUIisavailableto converter help the user experiment with the different hardware and software enabled features. The EVM accepts a DC input from350VDCto400VDC,andoutputsanominal12VDCwithfullloadoutputpowerof340W,orfulloutputcurrent of29A. Copyright©2012–2017,TexasInstrumentsIncorporated ApplicationandImplementation 55 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 7.2 Typical Application ThissectionsummarizesthePSFBEVMDC-DCpowerconverter. T1 L1 Q7 +12V Q6 VBUS C1 RL I_pri PRIM CURRENT ORING CTL Q5 T2 VOUT C2 QT1 D1 QT2 R2 VA Lr T1 Current Sensing QB1 D2 QB2 Vref Duty for mode DPWM0 DPWM0B switching Vout EADC0 CLA0 CPCC < DPWM1 DPWM1B Iout EADC1 CLA1 DPWM2 DPWM2A Load Current DPWM2B I_pri EADC2 PCM DPWM3 DPWM3A DPWM3B ISOLATED AD00 FAULT0 ACFAIL_IN GATE Transformer SYNCHRONOUS AD01 GATE DRIVE I_SHARE AD02/CMP0 FAULT FAULT1 ACFAIL_OUT A B A B Vout AD03/CMP1/CMP2 FAULT2 FAILURE M3 M3 M2 M2 0B 1B AD04/CMP3 UCD3138 PW PW PW PW WM WM Iout AD05/CMP4 GPIO1 ORING_CRTL D D D D DP DP I_pri AD06/CMP5 CBC GPIO2 ON/OFF temp AD07/CMP6 Vin AD08 GPIO3 P_GOOD VA AD09 ARM7 WD PMBus RST OSC UART0 Primary UART1 Memory Figure7-1.Phase-ShiftedFull-Bridge 56 ApplicationandImplementation Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 7.2.1 Design Requirements Table7-2.InputCharacteristics PARAMETER CONDITIONS MIN TYP MAX UNIT ALLSPECIFICATIONSatVin=400Vand25°CAMBIENTUNLESSOTHERWISENOTED. V Inputvoltagerange NormalOperating 350 385 420 V in V Maxinputvoltage Continuous 420 V inmax I Inputcurrent Vin=350V,FullLoad 1.15 A in I Inputnoloadcurrent Outputcurrentis0A 30 mA stby V V Decreasing(inputvoltageisdetectedonsecondaryside) 340 V on in Undervoltagelockout V V Increasing 360 V hys in Table7-3.OutputCharacteristics PARAMETER CONDITIONS MIN TYP MAX UNIT ALLSPECIFICATIONSatVin=400Vand25°CAMBIENTUNLESSOTHERWISENOTED. V Outputvoltagesetpoint Noloadonoutputs 12 V O Reg Lineregulation Alloutputs;360≤V ≤420;I =I 0.5 % line in O Omax Reg Loadregulation Alloutputs;0≤I ≤I ;V =400V 1 % load O Omax in V Rippleandnoise(1) 5Hzto20MHz 100 mVpp n I Outputcurrent 0 30 A O η Efficiencyatphase-shiftmode Vo=12V,Io=15A 93% η EfficiencyatPWMZVSmode Vo=12V,Io=15A 93% η Efficiencyathardswitchingmode Vo=12V,Io=15A 90% V Outputadjustrange 11.4 12.6 V adj Transientresponse V 50%LoadStepat1AµS,minloadat2A ±0.36 V tr overshoot/undershoot t Transientresponsesettlingtime 100 µS settling t Outputrisetime 10%to90%ofVout 50 mS start Overshoot AtStartup 2 % fs Switchingfrequency OverV andI ranges 150 kHz in O I Currentsharingaccuracy 50%-fullload ±5 % share φ Loopphasemargin 10%-Fullload 45 degree G Loopgainmargin 10%-Fullload 10 dB (1) Rippleandnoisearemeasuredwith10µFTantalumcapacitorand0.1µFceramiccapacitoracrossoutput. 7.2.2 Detailed Design Procedure 7.2.2.1 PCMC(PeakCurrentModeControl)PSFB(PhaseShiftedFullBridge)HardwareConfiguration Overview The hardware configuration of the UCD3138x PCMC PSFB converter contains two critical elements that arehighlightedinthesubsequentsections. • DPWM initialization - This section will highlight the key register settings and considerations necessary for the UCD3138x to generate the correct MOSFET waveforms for this topology. This maintains the proper phase relationship between the MOSFETs and synchronous rectifiers as well as the proper set uprequiredtofunctioncorrectlywithPCMC. • PCMC initialization - This section will discuss the register settings and hardware considerations necessarytomodulatetheDPWMpinswithPCMCandinternalslopecompensation. Copyright©2012–2017,TexasInstrumentsIncorporated ApplicationandImplementation 57 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 7.2.2.2 DPWMInitializationforPSFB The UCD3138x DPWM peripheral provides flexibility for a wide range of topologies. The PSFB configuration utilizes the Intra-Mux and Edge Generation Modules of the DPWM. For a diagram showing thesemodules,seetheUCD3138xDigitalPowerPeripheralsManual. HereisaschematicofthepowerstageofthePSFB: L1 T1 VOUT Q6 VBUS I_pri PRIM CURRENT Q5 T2 R2 D1 QT2 QT1 Lr T1 QB1 D2 QB2 ISOLATED GATE Transformer SYNCHRONOUS GATE DRIVE A B A B 3 3 2 2 B B M M M M 0 1 W W W W M M W W P P P P D D D D P P D D Figure7-2.Schematic –PSFBPowerStage 58 ApplicationandImplementation Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 HereisanoverviewofthekeyPSFBsignals: 3A– QB1 (DPWM1C) 3B– QT1 (DPWM2C) 2A– QT2 (EDGEGEN) 2B– QB2 X1 Y3 (EDGEGEN) X3 Transformer Y2 Voltage X2 1B– QSYN1,3 Y1 0B– QSYN2,4 DPWM3AF DPWM3BF DPWM2AF DPWM2BF Peak Level Current X1,X2,X3 andY1,Y2,Y3 are sets of moving edges All other edges are fixed. Figure7-3.KeyPSFBSignals 7.2.2.3 DPWMSynchronization DPWM1issynchronizedtoDPWM0,DPWM2issynchronizedtoDPWM1,andDPWM3issynchronizedto DPWM2, ½periodoutofphaseusingthesecommands: Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN=1;//configuredtoslave Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN=1;//configuredtoslave Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN=1;//configuredtoslave Dpwm0Regs.DPWMPHASETRIG.all=PWM_SLAVESYNC; Dpwm1Regs.DPWMPHASETRIG.all=PWM_SLAVESYNC; Dpwm2Regs.DPWMPHASETRIG.all=PWM_SLAVESYNC; LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL //Slavetodpwm-0 =0; //Slavetodpwm-1 LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL //Slavetodpwm-2 =1; LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL =2; Copyright©2012–2017,TexasInstrumentsIncorporated ApplicationandImplementation 59 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com If the event registers on the DPWMs are the same, the two pairs of signals will be symmetrical. All code examplesaretakenfromthePSFBEVMcode,unlessotherwisestated. 7.2.2.4 FixedSignalstoBridge The two top signals in the above drawing have fixed timing. The DPWM1CF and DPWM2CF signals are used for these pins. DPWMCxF refers to the signal coming out of the fault module of DPWMx, as shown inFigure7-4. Figure7-4.FixedSignalstoBridge 60 ApplicationandImplementation Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 ThesesignalsareactuallyroutedtopinsDPWM3Aand3BusingtheIntraMuxwiththesestatements: Dpwm3Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX=7;//SendDPWM1C Dpwm3Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX=8;//SendDPWM2C Since these signals are really being used as events in the timer, the #defines are called EV5 and EV6. Herearethestatementswhichinitializethem: //SetupwaveformforDPWM-C(re-usingblankingBregs) Dpwm2Regs.DPWMBLKBBEG.all=PWM2_EV5+(4*16); Dpwm2Regs.DPWMBLKBEND.all=PWM2_EV6; Period Start Period End Controlled by DPWM1Blanking register Blank B Begin Blank B End 3A– QB1 Even5 Even6 (DPWM1C) 3B– QT1 Even6 Even5 Even6 (DPWM2C) Blank B End Blank B Begin Controlled by DPWM2Blanking register Figure7-5.BlankBTimingInformation The statements for DPWM1 are the same. Remember that DPWMC reuses the Blank B registers for timinginformation. 7.2.2.5 DynamicSignalstoBridge DPWM0 and 1 are set at normal mode. PCMC triggering signal (fault) chops DPWM0A and 1A cycle by cycle. The corresponding DPWM0B and 1B are used for synchronous rectifier MOSFET control. The samePCMCtriggeringsignalisappliedtoDPWM2andDPWM3.Bothofthesearesettonormalmodeas well. DPWM2 and 3 are chopped and their edges are used to generate the next two dynamic signals to the bridge. They are generated using the Edge Generator Module in DPWM2. The Edge Generator sourcesareDPWM2andDPWM3.Theedgesusedare: DPWM2AturnedonbyarisingedgeonDPWM2BF DPWM2AturnedoffbyafallingedgeonDPWM3AF DPWM2BturnedonbyarisingedgeonDPWM3BF DPWM2BturnedoffbyafallingedgeonDPWM2AF Copyright©2012–2017,TexasInstrumentsIncorporated ApplicationandImplementation 61 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com Period Start Period End 3A– QB1 (DPWM1C) 3B– QT1 (DPWM2C) 2A– QT2 (EDGEGEN) 2B– QB2 (EDGEGEN) Y3 X3 1A 1B– QSYN1,3 Y2 s X2 nt 0A ve e 0B– Y1 y QSYN2,4 X1 odedb Me n DPWM3AF almi mr DPWM3BF Nordete e m DPWM2AF dti a e D DPWM2BF Peak Level Current Chopping point Chopping point X1,X2,X3 andY1,Y2,Y3 are sets of moving edges All other edges are fixed . Figure7-6.DynamicSignalstoBridge TheEdgeGeneratorisconfiguredwiththesestatements: Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE=2; Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE=5; Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE=6; Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE=1; Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX=1;//EDGEGEN-AouttheAoutput Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX=1;//EDGEGEN-BouttheBoutput Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN=1; The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing delaythroughtheDPWM. Thefinial6gatesignalsareshowninFigure7-7. 62 ApplicationandImplementation Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 Period Start Period End 3A– QB1 (DPWM1C) 3B– QT1 (DPWM2C) 2A– QT2 (EDGEGEN) 2B– QB2 (EDGEGEN) Y3 X3 1B– QSYN1,3 Y2 X2 0B– Y1 QSYN2,4 X1 Peak Level Current Chopping point Chopping point Figure7-7.Final6GateSignals Note how the falling edge of DPWM2AF aligns with the X1 edge, and how the rising edge of DPWM2BF aligns with the X3 edge. The falling edges on DPWM2AF and DPWM3AF are caused by the peak detection logic. This is fed through the Cycle By Cycle logic. The Cycle By Cycle logic also has a special feature to control the rising edges of DPWM2BF (X1 and X3) and DPWM3BF (Y1 and Y3). It uses the value of Event3 – Event2 to control the time between the edges. The same feature is used with DPWM0 and DPWM1 to control the X2 and Y2 signals. Using the other 2 DPWMs permits these signals to have a differentdeadtime. The same setup can be used for voltage mode control. In this case, the Filter output sets the timing of the fallingedgeonDPWMxAF. All DPWMs are configured in Normal mode, with CBC enabled. If external slope compensation is used, DPWM1A and DPWM1B are used to reset the external compensator at the beginning of each half cycle. If noPCMCeventoccurs,thevaluesofEvents2and3determinethelocationsoftheedges,justasinopen loopmode. 7.2.2.6 SystemInitializationforPCM PCM (Peak Current Mode) is a specialized configuration for the UCD3138x which involves several peripherals.Thissectiondescribeshowitworksacrosstheperipherals. 7.2.2.6.1 UseofFrontEndsandFiltersinPSFB All three front ends are used in PSFB. The same signals are used in the same places for both PCMC and voltage mode. The same hardware can be used for both control modes, with the mode determined by which firmware is loaded into the device. FE0 and FE1 are used with their associated filters, but Filter 2 is notusedatall. FE0– Vout– voltageloop FE1– Iout– currentloop FE2– Ipri– PCM InPCMCmode,FE2isusedforPCMC,andthevoltageloopisnormallyusedtoprovidethestartpointfor thecompensationramp.IftheCPCCfirmwaredetectsaneedforconstantcurrentmode,itswitchestothe currentloopforthestartpoint. Copyright©2012–2017,TexasInstrumentsIncorporated ApplicationandImplementation 63 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 7.2.2.6.2 PeakCurrentDetection Peak current detection involves all the major modules of the DPPs, the Front End, Filter, Loop Mux, Fault MuxandtheDPWMs.AdrawingofthemajorelementsisshowninFigure7-8. Ipri PCM Loop Fault Comparator Mux Mux DPWM Vout Voltage Loop Loop Ramp Loop Filter Mux Module Mux Front End Figure7-8.PeakCurrentDetectionFunction All signals without arrows flow from left to right. The voltage loop is used to select a peak current level. This level is fed to the Ramp module to generate a compensation ramp. The compensation ramp is compared to the primary current by the PCMC comparator in the Front End. When the ramp value is greater than the primary current, the APCMC signal is sent to the DPWM, causing the events described in theprevioussections. The DPWM frame start and output pin signals can be used to trigger the Ramp Module. In this case, unlike in the case of other ramp module functions, each DPWM frame triggers the start of the ramp. The rampstepsevery32ns. The Filter is configured normally, there is no real difference for PCMC. The PCM_FILTER_SEL bits in the LoopMux.PCMCTRLregisterareusedtoselectwhichfilterisconnectedtotherampmodule: LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL=0;//selectfilter0 With Firmware Constant Power/Constant current, Filter 1 and Front End 1 are used as a current control loop, with the EADCDAC set to high current. If the voltage loop value becomes higher than the current loopvalue,thenFilter1isusedtocontrolthePCMrampstartvalue: LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL=1; SPACE//selectfilter1forslopecompensationsource In the ramp module, there are 2 bitfields in the RAMPCTRL register which must be configured. The PCM_START_SEL must be set to a 1 to enable the Filter to be used as a ramp start source. The RAMP_ENbitmustbeset,ofcourse. The DAC_STEP register sets the slope of the compensation ramp. The DAC value is in volts, of course, so it is necessary to calculate the slope after the current to voltage conversion. Here is the formula for convertingfrommillivoltspermicrosecondtoDACSTEP. m=compensationslopeinmillivoltspermicrosecond ACSTEP=335.5× M InC,thiscanbewritten: #defineCOMPENSATION_SLOPE150//compensationslopeinmillivoltspermicrosecond #defineDACSTEP_COMP_VALUE((int)(COMPENSATION_SLOPE*335.5)) SPACE//valueinDACSTEPfordesiredcompensationslope SPACEFeCtrl0Regs.DACSTEP.all=DACSTEP_COMP_VALUE; 64 ApplicationandImplementation Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 ItmayalsobenecessarytosetarampendingvalueintheRAMPDACENDregister. In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling the differential to single ended comparator function. The front end diagram leaves it out for simplicity, but the connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator, however,issingleended.SoaconversionisnecessaryasshowninFigure7-9. AFE_GAIN 23-AFE_GAIN EAP0 6bitADC 8mV/LSB EAN0 2AFE_GAIN EADC X Averaging Signed9bit result (error)1mV/LSB SAR/Prebias Ramp DAC0 Filter x CPCC 10bit DAC 1.5625mV/LSB Σ Value Differential to Dither Single Ended 4bit dithering gives14bits of effective resolution 97.65625μV/LSB effective resolution Absolute Value 10bit result Calculation 1.5625mV/LSB Peak Current Detected Peak Current Mode Comparator Figure7-9.DifferentialtoSingle-EndedComparatorFunction TheEADC_MODEbitinEADCCTRLshouldbesettoa5forpeakcurrentmode. The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but thereare3frontends.SothePCM_FE_SELbitsinAPCMCTRLmustbeusedtoselectwhichfrontendis used: LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL=2;//useFE2forPCM*/ ThePCM_ENbitmustalsobeset. LoopMuxRegs.APCMCTRL.bit.PCM_EN=1;//EnablePCM Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4 DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to connect the PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration information on all of these bits, consult the appropriate EVM firmware. To avoid errors, it is best to configure your hardware design using the same DPWMs, filters, and front ends for the same functions as theEVM. DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in the Loop Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of theDPWMperiod. 7.2.2.6.3 PeakCurrentMode(PCM) There is one peak current mode control module in the device however any front end can be configured to usethismodule. Copyright©2012–2017,TexasInstrumentsIncorporated ApplicationandImplementation 65 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 7.2.3 Application Curves 30ALoad syncFETsoff 1A-16A-1A Vin=385V Figure7-11.V SoftStart Figure7-10.LoadTransient OUT Kp=14000 Kd=2000 Ki=300 Alpha=–2 Figure7-12.BodePlot 66 ApplicationandImplementation Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 8 Power Supply Recommendations 8.1 Power Supply Decoupling and Bulk Capacitors • Both3.3VDand3.3VAshouldhavealocal4.7-μFcapacitorplacedascloseaspossibletothedevice pins. • BP18shouldhavea1-μFcapacitor. Copyright©2012–2017,TexasInstrumentsIncorporated PowerSupplyRecommendations 67 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 9 Layout 9.1 Layout Guidelines • Single ground is recommended: SGND. A multilayer such as 4 layers board is recommended so that onesolidSGNDisdedicatedforreturncurrentpath,referredtothelayoutexample. • Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor hasdifferentESL,CapacitanceandESR,andtheyhavedifferentfrequencyresponse. • Avoid long traces close to radiation components, and place them into an internal layer, and it is preferredtohavegroundingshield,andintheend,addaterminationcircuit; • Analog circuit such as ADC sensing lines needs a return current path into the analog circuitry; digital circuitsuchasGPIO,PMBusandPWMhasareturncurrentpathintothedigitalcircuitry;althoughwith asingleplane,stilltrytoavoidtomixanalogcurrentanddigitalcurrent. • Don’tuseaferritebeadorlargerthan3 Ω resistortoconnectbetweenV33AandV33D. • Both 3.3VD and 3.3VA should have local 4.7 µF decoupling capacitors close to the device power pins, addvisastoconnectdecouplingcapsdirectlytoSGND. • Avoid negative current/negative voltage on all pins, so Schottky diodes may need to clamp the voltage; avoid the voltage spike on all pins more than 3.8 V or less than –0.3 V, add Schottky diodes on the pins which could have voltage spikes during surge test; be aware that a Schottky has relatively higher leakagecurrent,whichcanaffectthevoltagesensingathightemperature. • IfV33slewrateislessthan2.5V/mstheRESETpinshouldhavea2.21-kΩ resistorbetweenthereset pin and V33D and a 2.2-µF capacitor from RESET to ground. For more details please refer to the UCD3138 Family - Practical Design Guideline This capacitor must be located close to the device RESETpin. • ConfigureunusedGPIOpinstobeinputsorconnectthemtotheground(DGNDorSGND). • Select the cap ratio as shown below. Use 2.2 µF between V33D and BP18, and 1 µF between BP18 andDGNDorSGND. V33D 2.2 μF BP18 1.0 μF DGND 68 Layout Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 9.2 Layout Example Figure9-1.UCD313840-PinLayoutExample Figure9-2.UCD313840-PinLayoutExample(InternalLayer) Copyright©2012–2017,TexasInstrumentsIncorporated Layout 69 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 10 Device and Documentation Support 10.1 Device Support 10.1.1 Development Support TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code ComposerStudio™IntegratedDevelopmentEnvironment(IDE). Thefollowingproductssupportdevelopmentofthe yourdevicedeviceapplications: Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target softwareneededtosupportanyyourdevicedeviceapplication. HardwareDevelopmentTools: ExtendedDevelopmentSystem(XDS™)Emulator For a complete listing of development-support tools for the your device platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field salesofficeorauthorizeddistributor. 10.1.1.1 ToolsandDocumentation The application firmware for UCD3138 is developed on Texas Instruments Code Composer Studio (CCS) integrateddevelopmentenvironment(v3.3recommended). Device programming, real time debug and monitoring/configuration of key device parameters for certain power topologies are all available through Texas Instruments’ FUSION_DIGITAL_POWER_DESIGNER GraphicalUserInterface(http://www.ti.com/tool/fusion_digital_power_designer). The FUSION_DIGITAL_POWER_DESIGNER software application uses the PMBus protocol to communicate with the device over a serial bus using an interface adaptor known as the USB-TO-GPIO, available as an EVM from Texas Instruments (http://www.ti.com/tool/usb-to-gpio). PMBUS-based real-time debug capability is available through the ‘Memory Debugger’ tool within the Device GUI module of the FUSION_DIGITAL_POWER_DESIGNER GUI, which represents a powerful alternative over traditional JTAG-basedapproaches. The software application can also be used to program the devices, with a version of the tool known as FUSION_MFR_GUI optimized for manufacturing environments (http://www.ti.com/tool/fusion_mfr_gui). The FUSION_MFR_GUI tool supports multiple devices on a board, and includes built-in logging and reportingcapabilities. In terms of reference documentation, the following 3 programmer’s manuals are available offering detailed informationregardingtheapplicationandusageofUCD3138digitalcontroller: 1. UCD3138DigitalPowerPeripheralProgrammer'sManualKeytopicscoveredinthismanualinclude: – DigitalPulseWidthModulator(DPWM) – ModesofOperation(Normal/Multi/Phase-shift/Resonantandsoforth) – AutomaticModeSwitching – DPWMC,EdgeGenerationandIntra-Mux – FrontEnd – AnalogFrontEnd – ErrorADCorEADC – FrontEndDAC – RampModule – SuccessiveApproximationRegisterModule – Filter 70 DeviceandDocumentationSupport Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 www.ti.com SLUSAP2I–MARCH2012–REVISEDJANUARY2017 – FilterMath – LoopMux – AnalogPeakCurrentMode – ConstantCurrent/ConstantPower(CCCP) – AutomaticCycleAdjustment – FaultMux – AnalogComparators – DigitalComparators – FaultPinfunctions – DPWMFaultAction – IdealDiodeEmulation(IDE),DCMDetection – OscillatorFailureDetection – RegisterMapforalloftheaboveperipheralsinUCD3138 2. UCD3138MonitoringandCommunicationsProgrammer’sManual Keytopicscoveredinthismanualinclude: – ADC12 – Control,Conversion,Sequencing & Averaging – DigitalComparators – TemperatureSensor – PMBUSAddressing – DualSampleandHold – MiscellaneousAnalogControls(CurrentSharing,Brown-Out,Clock-Gating) – PMBUSInterface – GeneralPurposeInputOutput(GPIO) – TimerModules – PMBus – RegisterMapforalloftheaboveperipheralsinUCD3138 3. UCD3138ARMandDigitalSystemProgrammer’sManual Keytopicscoveredinthismanualinclude: – BootROMandBootFlash – BootROMFunction – MemoryRead/WriteFunctions – ChecksumFunctions – FlashFunctions – AvoidingProgramFlashLock-Up – ARM7Architecture – ModesofOperation – Hardware/SoftwareInterrupts – InstructionSet – DualStateInter-working(Thumb16-bitMode/ARM32-bitMode) – MemoryandSystemModule – AddressDecoder,DEC(MemoryMapping) – MemoryController(MMC) – CentralInterruptModule – RegisterMapforalloftheaboveperipheralsinUCD3138 4. FUSION_DIGITAL_POWER_DESIGNERforIsolatedPowerApplications – UserguideforDesignerGUI – UserguideforDeviceGUI – FirmwareMemoryDebugger – ManufacturingTool(MFRGUI) In addition to the tools and documentation described above, for the most up to date information regarding evaluation modules, reference application firmware and application notes/design tips, please visit http://www.ti.com/product/ucd3138. Copyright©2012–2017,TexasInstrumentsIncorporated DeviceandDocumentationSupport 71 SubmitDocumentationFeedback ProductFolderLinks:UCD3138

UCD3138 SLUSAP2I–MARCH2012–REVISEDJANUARY2017 www.ti.com 10.2 Documentation Support Forrelateddocumentationseethefollowing: 10.2.1 References 1. UCD3138DigitalPowerPeripheralsProgrammer’sManual(SLUU995) 2. UCD3138MonitoringandCommunicationsProgrammer’sManual(SLUU996) 3. UCD3138ARMandDigitalSystemProgrammer’sManual(SLUU994) 4. FUSION_DIGITAL_POWER_DESIGNERforIsolatedPowerApplications(SLUA676) 5. CodeComposerStudioDevelopmentToolsv3.3 –GettingStartedGuide (SPRU509) 6. ARM7TDMI-STechnicalReferenceManual 7. SystemManagementBus(SMBus)Specification 8. PMBus™PowerSystemManagementProtocolSpecification 10.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperrightcorner,clickon Alertmetoregisterandreceiveaweeklydigestofanyproductinformationthat haschanged.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 10.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI's TermsofUse. TIE2E™OnlineCommunity The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, exploreideasandhelpsolveproblemswithfellowengineers. DesignSupport TI's Design Support Quickly find helpful E2E forums along with design support tools andcontactinformationfortechnicalsupport. 10.5 Trademarks E2EisatrademarkofTexasInstruments. ARM7TDMI-SisatrademarkofARM. PMBusisatrademarkofSMIF,Inc.. Allothertrademarksarethepropertyoftheirrespectiveowners. 10.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 10.7 Glossary TIGlossary Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 11 Mechanical Packaging and Orderable Information 11.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 72 MechanicalPackagingandOrderableInformation Copyright©2012–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:UCD3138

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCD3138RGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD3138 & no Sb/Br) UCD3138RGCT ACTIVE VQFN RGC 64 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD3138 & no Sb/Br) UCD3138RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 UCD3138 & no Sb/Br) UCD3138RHAT ACTIVE VQFN RHA 40 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 UCD3138 & no Sb/Br) UCD3138RJAR ACTIVE VQFN RJA 40 3000 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 125 UCD3138 & no Sb/Br) UCD3138RJAT ACTIVE VQFN RJA 40 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 125 UCD3138 & no Sb/Br) UCD3138RMHR NRND WQFN RMH 40 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 3138RMH & no Sb/Br) UCD3138RMHT NRND WQFN RMH 40 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 3138RMH & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCD3138RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 UCD3138RGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 UCD3138RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 UCD3138RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 UCD3138RJAR VQFN RJA 40 3000 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 UCD3138RJAT VQFN RJA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 UCD3138RMHR WQFN RMH 40 2000 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 UCD3138RMHT WQFN RMH 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCD3138RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD3138RGCT VQFN RGC 64 250 210.0 185.0 35.0 UCD3138RHAR VQFN RHA 40 2500 367.0 367.0 38.0 UCD3138RHAT VQFN RHA 40 250 210.0 185.0 35.0 UCD3138RJAR VQFN RJA 40 3000 367.0 367.0 38.0 UCD3138RJAT VQFN RJA 40 250 210.0 185.0 35.0 UCD3138RMHR WQFN RMH 40 2000 367.0 367.0 38.0 UCD3138RMHT WQFN RMH 40 250 210.0 185.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE RJA0040A VQFN - 1 mm max height SCALE 2.000 PLASTIC QUAD FLATPACK - NO LEAD 6.1 B A 5.9 PIN 1 INDEX AREA 6.1 5.9 1 MAX C SEATING PLANE 0.05 0.00 0.08 2X 4.5 4.15 0.1 A3 (0.2) TYP A2 4X ( 0.32) 11 20 36X 0.5 10 21 2.74 TYP 2X 41 4.5 EXPOSED THERMAL PAD 30 0.30 1 40X 0.18 PIN 1 ID 40 31 A4 0.1 C A B (OPTIONAL) A1 40X 0.5 0.05 0.3 2.74 TYP 4222901/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RJA0040A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.15) SYMM 4X ( 0.32) 40X (0.6) 40 31 A1 A4 1 30 40X (0.24) (2.74) TYP (0.25) TYP 41 SYMM (5.8) (0.685) TYP 36X (0.5) (1.14) TYP ( 0.2) TYP VIA 10 21 A2 A3 (R0.05) TYP 11 20 (0.685) (1.14) TYP TYP (2.74) TYP (5.8) LAND PATTERN EXAMPLE SCALE:12X 0.05 MAX 0.05 MIN ALL AROUND ALL SIDES SOLDER MASK METAL OPENING SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4222901/A 05/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com

EXAMPLE STENCIL DESIGN RJA0040A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 9X ( 1.17) (1.37) TYP 4X ( 0.32) 40X (0.6) 40 31 A1 A4 40X (0.24) 1 41 30 (1.37) TYP (0.25) TYP SYMM (5.8) 36X (0.5) (R0.05) TYP 10 21 A2 A3 11 20 METAL SYMM TYP (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 41: 72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:12X 4222901/A 05/2016 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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GENERIC PACKAGE VIEW RGC 64 VQFN - 1 mm max height 9 x 9, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224597/A www.ti.com

PACKAGE OUTLINE RGC0064B VQFN - 1 mm max height SCALE 1.500 PLASTIC QUAD FLATPACK - NO LEAD 9.15 A B 8.85 PIN 1 INDEX AREA 9.15 8.85 1.0 0.8 C SEATING PLANE 0.05 0.08 C 0.00 2X 7.5 EXPOSED SYMM (0.2) TYP THERMAL PAD 17 32 16 33 SYMM 65 2X 7.5 4.25 0.1 60X 0.5 1 48 0.30 64X PIN 1 ID 64 49 0.18 0.1 C A B 0.5 64X 0.3 0.05 4219010/A 10/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGC0064B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.25) SEE SOLDER MASK SYMM 64X (0.6) DETAIL 64 49 64X (0.24) 1 48 60X (0.5) (R0.05) TYP (1.18) TYP (8.8) 65 SYMM (0.695) TYP ( 0.2) TYP VIA 16 33 17 32 (0.695) TYP (1.18) TYP (8.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X 0.07 MIN 0.07 MAX ALL AROUND ALL AROUND METAL UNDER METAL EDGE SOLDER MASK EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK OPENING METAL OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4219010/A 10/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGC0064B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 64X (0.6) 64 49 64X (0.24) 1 48 60X (0.5) (R0.05) TYP 9X ( 1.19) 65 SYMM (8.8) (1.39) 16 33 17 32 (1.39) (8.8) SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 10X EXPOSED PAD 65 71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 4219010/A 10/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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