(cid:21) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 (cid:1) Integrated 0.15-Ω Power MOSFET (cid:1) Unidirectional Switch (cid:1) (cid:1) 3-V to 8-V Operation Thermal Shutdown (cid:1) (cid:1) Digital Programmable Current Limit Fault-Output Indicator from 0 A to 3 A (cid:1) Maximum-Output Current Can Be Set to 1 A (cid:1) Electronic Circuit Breaker Function Above the Programmed Fault Level or to a (cid:1) 1µA I When Disabled Full 4 A CC (cid:1) Programmable On-Time (cid:1) Power SOIC, Low-Thermal Resistance (cid:1) Packaging Programmable Start Delay (cid:1) Fixed 3% Duty Cycle description The UCC3912 family of hot swap power managers provides complete power management, hot swap capability, and circuit breaker functions. The only component required to operate the device, other than supply bypassing, is the fault timing capacitor, C . All control and housekeeping functions are integrated, and externally T programmable. These include the fault current level, maximum output-sourcing current, maximum fault time, and startup delay. In the event of a constant fault, the internal fixed 3% duty cycle ratio limits average output power. The internal 4-bit DAC allows programming of the fault level current from 0 A to 3 A with 0.25-A resolution. The IMAX control pin sets the maximum sourcing current to 1 A above the fault level when driven low, and to a full 4 A when driven high for applications which require fast output capacitor charging. When the output current is below the fault level, the output MOSFET is switched on with a nominal on resistance of 0.15 Ω. When the output current exceeds the fault level, but is less than the maximum sourcing level, the output remains switched on, but the fault timer starts charging C . Once C charges to a preset threshold, the T T switch is turned off, and remains off for 30 times the programmed fault time. When the output current reaches the maximum sourcing level, the MOSFET transitions from a switch to a constant current source. (continued) block diagram H = 4 A 2 VIN IMAX 10 30 mV CHARGE REVERSE VOLTAGE + PUMP COMPARATOR − 3 VIN + VOUT CURRENT SENSE 4 A + POWER MAX CURRENT FET LEVEL − LINEAR CURRENT AMPLIFIER H = OPEN 1 A ABOVE FAULT ON TIME 14 VOUT CURRENT FAULT + CONTROL LEVEL 0A TO 3 A − 3% DUTY 15 VOUT CYCLE THERMAL OVERCURRENT SHUTDOWN 1.5 V 0 A−3 A COMPARATOR 0.25 INTERNAL + RES BIAS − 1 SHTDWN 6 7 8 9 5 4 13 12 11 16 UDG-99146 B3 B2 B1 B0 GND HEATSINK CT FAULT 4 BIT DAC GND PINS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:7)(cid:8)(cid:9)(cid:22)(cid:1)(cid:2)(cid:17)(cid:23)(cid:9)(cid:20) (cid:22)(cid:11)(cid:17)(cid:11) (cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) (cid:24)! "#(cid:28)(cid:28)$(cid:25)(cid:31) (cid:30)! (cid:27)(cid:26) %#&’(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25) ((cid:30)(cid:31)$) Copyright  2003, Texas Instruments Incorporated (cid:7)(cid:28)(cid:27)(#"(cid:31)! "(cid:27)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29) (cid:31)(cid:27) !%$"(cid:24)(cid:26)(cid:24)"(cid:30)(cid:31)(cid:24)(cid:27)(cid:25)! %$(cid:28) (cid:31)*$ (cid:31)$(cid:28)(cid:29)! (cid:27)(cid:26) (cid:17)$+(cid:30)! (cid:23)(cid:25)!(cid:31)(cid:28)#(cid:29)$(cid:25)(cid:31)! !(cid:31)(cid:30)(cid:25)((cid:30)(cid:28)( ,(cid:30)(cid:28)(cid:28)(cid:30)(cid:25)(cid:31)-) (cid:7)(cid:28)(cid:27)(#"(cid:31)(cid:24)(cid:27)(cid:25) %(cid:28)(cid:27)"$!!(cid:24)(cid:25). ((cid:27)$! (cid:25)(cid:27)(cid:31) (cid:25)$"$!!(cid:30)(cid:28)(cid:24)’- (cid:24)(cid:25)"’#($ (cid:31)$!(cid:31)(cid:24)(cid:25). (cid:27)(cid:26) (cid:30)’’ %(cid:30)(cid:28)(cid:30)(cid:29)$(cid:31)$(cid:28)!) www.ti.com 1

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:21) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 description (continued) The UCC3912 family is designed for unidirectional current flow, emulating an ideal diode in series with the power switch. This feature is particularly attractive in applications where many devices are powering a common bus, such as with SCSI Termpwr. The UCC3912 family can be put into sleep mode drawing only 1-µA of supply current. The SHTDWN pin has a preset threshold hysteresis which allows the user the ability to set a time delay upon startup to achieve sequencing of power. Other features include an open drain FAULT output indicator, thermal shutdown, under voltage lockout, and a low thermal resistance small outline package. absolute maximum ratings over operating free-air temperature (unless otherwise noted)†(cid:1) VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V FAULT sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA FAULT voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V IN Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Limiting Input voltage (B0, B1, B2, B3, IMAX, SHTDWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V IN Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C stg Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 150°C J Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Interface Products Data book (TI Literature Number SLUD002) for thermal limitations and considerations of packages. package information DIL-16, SOIC-16 TSSOP-24, N, DP Package PWP Package (TOP VIEW) (TOP VIEW) SHTDWN1 24 FAULT N/C 2 23 N/C VIN 3 22 VOUT VIN 4 21 VOUT GND* 5 20 GND* GND* 6 19 GND* GND* 7 18 GND* GND* 8 17 GND* EGND*9 16 GND* B3 10 15 CT B2 11 14 IMAX B1 12 13 B0 *Pin 5 serves as lowest impedance to the electrical *Pin 9 serves as lowest impedance to the electrical ground; ground; Pins 4, 12, and 13 serve as heat sink/ground. other GND pins serve as heat sink/ground. These pins should These pins should be connected to large etch areas to be connected to large etch areas to help dissipate heat. help dissipate heat. For N package, pins 4, 12, and 13 are N/C. 2 www.ti.com

(cid:21) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 electrical characteristics, these specifications apply for T = −40°C to 85°C for the UCC2912; A T = 0°C to 70°C for the UCC3912, VIN = 5 V, IMAX = 0.4 V, SHTDWN = 2.4 V A (unless otherwise stated) supply section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Voltage input range 3.0 8.0 V Supply current 1.0 2.0 mA Sleep mode current SHTDWN = 0.2 V 0.5 5.0 µA NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. output section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS IOUT = 1 A 0.15 0.22 V IOUT = 2 A 0.3 0.45 V IOUT = 3 A 0.45 0.68 V VVoollttaaggee ddrroopp IOUT = 1A, VIN = 3 V 0.17 0.27 V IOUT = 2 A, VIN = 3 V 0.35 0.56 V IOUT = 3 A, VIN = 3 V 0.5 0.8 V Reverse leakage current VIN < VOUT , SHTDWN = 0.2 V, VOUT = 5 V 5 20 µA Initial startup time See Note 2 100 µs Short circuit response See Note 2 100 ns Thermal shutdown See Note 2 170 °C Thermal hysteresis See Note 2 10 °C NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. NOTE 2: Ensured by design. Not production tested. DAC section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output leakage Code = 0000−0011 0 20 µA Code = 0100 0.1 0.25 0.45 A Code = 0101 0.25 0.50 0.75 A Code = 0110 0.5 0.75 1.0 A Code = 0111 0.75 1.00 1.25 A Code = 1000 1.0 1.25 1.5 A Code = 1001 1.25 1.50 1.75 A TTrriipp ccuurrrreenntt Code = 1010 1.5 1.75 2.0 A Code = 1011 1.7 2.00 2.3 A Code = 1100 1.9 2.25 2.58 A Code = 1101 2.1 2.50 2.9 A Code = 1110 2.3 2.75 3.2 A Code = 1111 2.5 3.0 3.5 A Maximum output current Code = 0000 to 0011 0.02 mA MMaaxxiimmuumm oouuttppuutt ccuurrrreenntt oovveerr ttrriipp UCC2912 Code = 0100 to 1111, IMAX = 0 V 0.5 1.0 2.0 A (current source mode) UCC3912 Code = 0100 to 1111, IMAX = 0 V 0.5 1.0 1.8 A Maximum output current (current source mode) Code = 0100 to 1111, IMAX = 2.4 V 3.0 4.0 5.2 A NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. www.ti.com 3

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:21) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 electrical characteristics, these specifications apply for T = −40°C to 85°C for the UCC2912; A T = 0°C to 70°C for the UCC3912, VIN = 5 V, IMAX = 0.4 V, SHTDWN = 2.4 V A (unless otherwise stated) timer section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CT charge current VCT = 1.0 V −45.0 -36.0 −22.0 µA UCC2912 VCT = 1.0 V 0.72 1.20 1.57 µA CCTT ddiisscchhaarrggee ccuurrrreenntt UCC3912 VCT = 1.0 V 0.72 1.20 1.50 µA Output duty cycle VOUT = 0 V 2.0 3.0 6.0 % CT fault threshold 1.3 1.5 1.7 V CT reset threshold 0.4 0.5 0.6 V NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. shutdown section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Shutdown threshold 1.1 1.5 1.9 V Shutdown hysteresis 100 mV Input current SHTDWN = 1 V 100 500 nA fault output section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output leakage current 500 nA Low level output voltage IOUT = 10 mA 0.4 0.8 V TTL input dc characteristics section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TTL input voltage high (can be connected to VIN) 2.0 V TTL input voltage low 0.8 V TTL input high current VIH = 2.4 V 3 10 µA TTL input low current VIL = 0.4 V 1 µA NOTE 1: All voltages are with respect to ground. Current is positive into and negative out of the specified terminal. pin description B0−B3: These pins provide digital input to the DAC which sets the fault current threshold. They can be used to provide a digital soft-start, adaptive current limiting. CT: A capacitor connected to ground sets the maximum fault time. The maximum fault time must be more than the time to charge the external capacitance in one cycle. The maximum fault time is defined as FAULT = 27.8 ×103 × CT. Once the fault time is reached the output will shutdown for a time given by: T = 833 ×103 × CT, this equates to a 3% duty cycle. SD FAULT: Open drain output which pulls low upon any condition which causes the output to open: fault, thermal shutdown, or shutdown. IMAX: When this pin is set to logic low the maximum sourcing current will always be 1 A above the programmed fault level. When set to logic high, the maximum sourcing current will be a constant 4 A for applications which require fast charging of load capacitance. 4 www.ti.com

(cid:21) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 pin description (continued) SHTDWN: When this pin is brought to a logic low, the IC is put into a sleep mode drawing typically less than 1 µA of I . The input threshold is hysteretic, allowing the user to program a startup delay with an external RC CC circuit. VIN: Input voltage to the UCC3912. The recommended voltage range is 3 V to 8 V. Both VIN pins should be connected together and to the power source. VOUT: Output voltage from the UCC3912. When switched the output voltage will be approximately V − (0.15 Ω × I ). Both VOUT pins should be connected together and to the load. IN OUT APPLICATION INFORMATION 4 12 13 5 VIN HGENADT PSIINNSK GND VOUT 2 14 VIN VOUT R1 CIN D1 3 15 RL COUT UCC2912 UCC3912 LED S6 RSD VIN 16 FAULT SHTDWN 1 11 CT CSD B3 B2 B1 B0 IMAX CT 6 7 8 9 10 VIN DIP S1 S2 S3 S4 S5 SWITCH NOTE: For demonstration board schematic see Design Note DN-58 (TI Literature Number SLUA187). UDG-99171 Figure 1. Evaluation Circuit protecting the UCC3912 from voltage transients The parasitic inductance associated with the power distribution can cause a voltage spike at V if the load IN current is suddenly interrupted by the UCC3912. It is important to limit the peak of this spike to less than 8 V to prevent damage to the UCC3912. This voltage spike can be minimized by: (cid:1) Reducing the power distribution inductance (e.g., twist the positive and negative leads of the power supply feeding V , locate the power supply close to the UCC3912, use a PCB ground plane,...etc.). IN (cid:1) Decoupling V with a capacitor, C (refer to Figure 1), located close to pins 2 and 3. This capacitor is IN IN typically less than 1 µF to limit the inrush current. (cid:1) Clamping the voltage at V below 8 V with a zener diode, D1 (refer to Figure 1), located close to pins 2 IN and 3. www.ti.com 5

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:21) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 APPLICATION INFORMATION UDG-93019-4 Figure 2. Load Current, Timing-Capacitor Voltage, and Output Voltage of the UCC3912 Under Fault Conditions. estimating maximum load capacitance For hot-swap applications, the rate at which the total output capacitance can be charged depends on the maximum output current available and the nature of the load. For a constant-current current-limited controller, the output will come up if the load asks for less than the maximum available short-circuit current. To ensure recovery of a duty-cycle from a short-circuited load condition, there is a maximum total output capacitance which can be charged for a given unit ON time (fault time). The design value of ON or fault time can be adjusted by changing the timing capacitor C . T For worst-case constant-current load of value just less than the trip limit; C can be estimated from: OUT(max) (cid:2) (cid:4) C (cid:1)(cid:2)I (cid:3)I (cid:4)(cid:5) 28(cid:5)103(cid:5)CT OUT(max) MAX LOAD V OUT where V is the output voltage. OUT 6 www.ti.com

(cid:21) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 APPLICATION INFORMATION For a resistive load of value RL, the value of C can be estimated from: OUT(max) (cid:7) (cid:10) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) (cid:6) C (cid:1)(cid:6)(cid:6) 28(cid:5)103(cid:5)CT (cid:6)(cid:6) OUT(max) (cid:6) (cid:7) (cid:10)(cid:6) (cid:6) (cid:6) (cid:6) (cid:6)(cid:6) (cid:6)(cid:6)(cid:6) (cid:6)(cid:6)RL(cid:5)(cid:9)n(cid:6)(cid:6) (cid:2) 1 (cid:4)(cid:6)(cid:6)(cid:6)(cid:6) V OUT (cid:8) (cid:8)1(cid:3) I (cid:5)RL (cid:11)(cid:11) MAX The overcurrent comparator senses both the DAC output and a representation of the output current. When the output current exceeds the programmed level the timing capacitor C charges with 36 µA of current. If the fault T occurs for the time it takes for C to charge up to 1.5 V, the fault latch is set and the output switch is opened. T The output remains opened until C discharges to 0.5 V with a 1.2-µA current source. Once the 0.5 V is reached T the output is enabled and will either appear as a switch, if the fault is removed, or a current source if the fault remains. If the over current condition is still present, then C will begin charging, starting the cycle over, resulting T in approximately a 3% on time. UDG-94019-1 Figure 3. UCC3912 On-Time Circuitry www.ti.com 7

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:21) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:3) (cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:12)(cid:12)(cid:11)(cid:13)(cid:14)(cid:15) (cid:16)(cid:9)(cid:17) (cid:18)(cid:19)(cid:11)(cid:7) (cid:7)(cid:9)(cid:19)(cid:15)(cid:8) (cid:12)(cid:11)(cid:20)(cid:11)(cid:10)(cid:15)(cid:8) SLUS241D − MARCH 1994 - REVISED NOVEMBER 2003 APPLICATION INFORMATION UDG-94019-1 Figure 4. R vs. Temperature at 2-A Load Current. DS(on) safety recommendations Although the UCC3912 family is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. For this reason, if the UCC3912 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UCC3912 will prevent the fuse from blowing virtually for all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. 8 www.ti.com

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2912DP ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2912DP & no Sb/Br) UCC2912PWP ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2912PWP & no Sb/Br) UCC3912DP ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3912DP & no Sb/Br) UCC3912DPG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3912DP & no Sb/Br) UCC3912DPTR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3912DP & no Sb/Br) UCC3912PWP ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3912PWP & no Sb/Br) UCC3912PWPG4 ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3912PWP & no Sb/Br) UCC3912PWPTR ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3912PWP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC3912DPTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC3912PWPTR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC3912DPTR SOIC D 16 2500 367.0 367.0 38.0 UCC3912PWPTR TSSOP PW 24 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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