Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 UCC2900x, UCC39002 Advanced 8-Pin Load-Share Controller 1 Features 3 Description • HighAccuracy,BetterThan1%CurrentShare The UCC39002 device is an advanced, high- 1 performance, and low-cost load share controller that ErroratFullLoad provides all necessary functions to parallel multiple • High-SideorLow-Side(GNDReference)Current- independent power supplies or DC-to-DC modules. SenseCapability Targeted for high-reliability applications in server, • Ultra-LowOffsetCurrentSenseAmplifier workstation, telecom, and other distributed power systems, the controller is suitable for N+1 redundant • SingleWireLoadShareBus systems or high current applications where off-the- • FullScaleAdjustability shelfpowersuppliesmustbeparalleled. • Intel®SSILoadShareSpecificationCompliant The BiCMOS UCC39002 is based on the automatic • DisconnectfromLoadShareBusatStand-By master or slave architecture of the UC3902 and • LoadShareBusProtectionAgainstShortstoGND UC3907 load share controllers. The device provides ortotheSupplyRail better than 1% current share error between modules at full load by using a very low offset post-package- • 8-PinMSOPPackageMinimizesSpace trimmed current sense amplifier and a high-gain • Lead-FreeAssembly negative feedback loop. And with the amplifier’s common-mode range of 0 V to the supply rail, the 2 Applications current sense resistor, R , can be placed in SHUNT • ModulesWithRemote-SenseCapability either the GND return path or in the positive output railofthepowersupply. • ModulesWithRemote-SenseCapability • ModulesWithRemote-SenseCapability DeviceInformation(1) • InConjunctionWiththeInternalFeedbackE/Aof PARTNUMBER PACKAGE BODYSIZE(NOM) OEMPowerSupplyUnits UCC29002 SOIC(8) 4.90mm×3.91mm UCC29002-1 VSSOP(8) 3.00mm×3.00mm UCC39002 PDIP(8) 9.81mm×6.35mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. TypicalLow-SideCurrent-SensingApplication VV++ RADJ S+ S UCC39002 BU LOAD S 1 CS− CSO 8 L POWER SUPPLY 2 CS+ LS 7 WITH REMOTE 3 VDD EAO 6 SENSE − + + M M 4 GND ADJ 5 E E T T S S Y Y S− S S RSHUNT V− Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 14 2 Applications........................................................... 1 8.1 ApplicationInformation ..........................................14 3 Description............................................................. 1 8.2 TypicalApplication .................................................15 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 18 5 PinConfigurationandFunctions......................... 3 10 Layout................................................................... 18 6 Specifications......................................................... 4 10.1 LayoutGuidelines.................................................18 6.1 AbsoluteMaximumRatings......................................4 10.2 LayoutExample....................................................18 6.2 ESDRatings..............................................................4 11 DeviceandDocumentationSupport................. 19 6.3 RecommendedOperatingConditions.......................4 11.1 DeviceSupport ....................................................19 6.4 ThermalInformation..................................................4 11.2 DocumentationSupport .......................................19 6.5 ElectricalCharacteristics...........................................5 11.3 RelatedLinks........................................................19 6.6 TypicalCharacteristics..............................................6 11.4 CommunityResources..........................................19 7 DetailedDescription.............................................. 7 11.5 Trademarks...........................................................19 7.1 Overview...................................................................7 11.6 ElectrostaticDischargeCaution............................19 7.2 FunctionalBlockDiagram.........................................7 11.7 Glossary................................................................20 7.3 FeatureDescription...................................................7 12 Mechanical,Packaging,andOrderable Information........................................................... 20 7.4 DeviceFunctionalModes........................................13 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionH(August2007)toRevisionI Page • AddedESDRatingtable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 5 Pin Configuration and Functions DorDGKPackage PPackage 8-PinSOICorVSSOP 8-PinPDIP TopView TopView CS− 1 8 CSO CS− 1 8 CSO CS+ 2 7 LS CS+ 2 7 LS VDD 3 6 EAO VDD 3 6 EAO GND 4 5 ADJ GND 4 5 ADJ PinFunctions PIN I/O DESCRIPTION NAME NO. Adjustamplifieroutput.Thisisthebufferedoutputoftheerroramplifierblocktoadjustoutputvoltageofthe ADJ 5 O powersupplybeingcontrolled.Thispinmustalwaysbeconnectedtoavoltageequaltoorgreaterthan V +1V. EAO CS– 1 I Currentsenseamplifierinvertinginput. CS+ 2 I Currentsenseamplifiernoninvertinginput. CSO 8 O Currentsenseamplifieroutput. EAO 6 O Outputforloadshareerroramplifier.(Transconductanceerroramplifier.) Ground.Referencegroundandpowergroundforalldevicefunctions.Returnthedevicetothelowcurrent GND 4 – sense−pathoftheconverter. LS 7 I/O Loadsharebus.Outputoftheloadsharebusdriveramplifier. Powersupplyprovidingbiastothedevice.Bypasswithagoodquality,lowESL0.1-µFto1-µF,maximum, VDD 3 I capacitorasclosetotheVDDpinandGNDaspossible. Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT V Supplyvoltage,currentlimited −0.3 15 V DD V Supplyvoltage,voltagesource −0.3 13.5 V DD V ,V Inputvoltage,currentsenseamplifier –0.3 V +0.3 V CS+ CS− DD V Currentsenseamplifieroutputvoltage −0.3 V V CSO DD V Loadsharebusvoltage −0.3 V V LS DD Supplycurrent(I +I ) 10 mA DD ZENER V Adjustpininputvoltage V +1V<V ≤V ADJ EAO ADJ DD I Adjustpinsinkcurrent 6 mA ADJ T Operatingjunctiontemperaturerange −55 150 °C J T Storagetemperature −65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoGND.Currentsarepositiveinto,negativeoutofthespecifiedterminal. 6.2 ESD Ratings VALUE UNIT Electrostatic Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V V (ESD) discharge Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage,voltagesource 4.575 13.5 V DD V Currentsenseamplifieroutputvoltage 0 11.8 V CSO V Loadsharebusvoltage 0 V –1.7 V LS DD I Adjustpinsinkcurrent 4.55 mA ADJ 6.4 Thermal Information UCC2900x/UCC39002 THERMALMETRIC(1) D(SOIC) DGK(VSSOP) P(PDIP) UNIT 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 111.9 168.0 54.1 °C/W θJA R Junction-to-case(top)thermalresistance 58.6 61.9 43.9 °C/W θJC(top) R Junction-to-boardthermalresistance 52.6 88.8 31.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 12.9 7.3 21.6 °C/W JT ψ Junction-to-boardcharacterizationparameter 52.0 87.2 31.1 °C/W JB R Junction-to-case(bottom)thermalresistance — — — °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 4 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 6.5 Electrical Characteristics V =12V,0°C<70°CfortheUCC39002,–40°C<T <105°CfortheUCC29002andUCC29002-1,T =T (unless DD A A J otherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT GENERAL Supplycurrent LSwithnoload,ADJ=5V 2.5 3.5 mA VDDclampvoltage IDD=6mA 13.5 14.25 15 V UNDERVOLTAGELOCKOUT Start-upvoltage(1) 4.175 4.375 4.575 V Hysteresis 0.2 0.375 0.55 CURRENTSENSEAMPLIFIER T =25C,V =0.5Vor11.5V,V =5V −100 100 µV A IC CSO V Inputoffsetvoltage IO Overtemperaturevariation ±10 µV/C A Gain 75 90 dB V CMRR Common-moderejectionratio 75 90 dB I Inputbiascurrent(CS+,CS−) −0.6 0.6 µA BIAS V High-leveloutputvoltage(CSO) 0.1V≤([CS+]−[CS−])≤0.4V,I =0mA 10.7 11 11.8 V OH OUT_CSO V Low-leveloutputvoltage(CSO) −0.4V≤([CS+]−[CS−])≤0.1V,I =0mA 0 0.1 0.15 V OL OUT_CSO I High-leveloutputcurrent(CSO) V =10V −1 −1.5 mA OH CSO I Low-leveloutputcurrent(CSO) V =1V 1 1.5 mA OL CSO GBW Gainbandwidthproduct(2) 2 MHz LOADSHAREDRIVER(LS) V Inputvoltagerange 0 10 V RANGE V =1V 0.995 1 1.005 CSO V Outputvoltage V OUT V =10V 0.995 10 1.005 CSO V Low-leveloutputvoltage V =0V,I =0mA 0 0.1 0.15 V OL CSO OUT_LS V High-leveloutputvoltage(2) VDD− V OH 1.7 I Outputcurrent 0.5V≤V ≤10V −1 −1.5 V OUT LS I Short-circuitcurrent V =0V,V =10V −10 −20 mA SC LS CSO V Drivershutdownthreshold V −V 0.3 0.5 0.7 V SHTDN CS− CS+ LOADSHAREBUSPROTECTION V =2V,V =2V,V =V ,V =5V 0 5 10 CSO EAO LS DD ADJ I Adjustamplifiercurrent µA ADJ V =2V,V =2V,V =0V,V =5V 0 5 10 CSO EAO LS ADJ ERRORAMPLIFIER V High-leveloutputvoltage I =0mA 3.5 3.65 3.8 V OH OUT_EAO g Transconductance I =±50µA 14 mS M EAO I High-leveloutputcurrent V −V =0.4V,R =2.2kΩ 0.7 0.85 1 mA OH LS CSO EAO ADJBUFFER V Inputoffsetvoltage(2) V =1.5V,V =0V −60 mV IO ADJ EAO I Sinkcurrent V =5.0V,V =0V 0 5 10 µA SINK ADJ EAO T =25°C 3.6 3.95 4.3 A V =5.0V, ADJ I Sinkcurrent 0°C≤T ≤70°C V =2.0V, 3.45 3.95 4.45 mA SINK A EAO LS=floating −40°C≤T ≤105°C 3.35 3.95 4.55 A (1) Enablestheloadsharebusatstart-up. (2) Ensuredbydesign.Notproductiontested. Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com 6.6 Typical Characteristics Figure1.ResultantLoadCurrentSharingAccuracy,asMeasuredAcrossShuntsfromtheOutputofEach Module 6 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 7 Detailed Description 7.1 Overview The UCC39002 is an advanced, high-performance, low-cost load-share controller that provides all the necessary functions to parallel multiple independent power supplies and modules. The UCC39002 can easily parallel currently available and popular synchronous buck converters, such as those designed with the TPS40050 controller. 7.2 Functional Block Diagram 8 CSO Current Sense Amp Disconnect Switch Load Share CS− 1 Bus Driver + + CS+ 2 Enable and Bias OK 7 LS VBIAS Load Share Bus 100 kΩ Receiver + VDD 3 ErrorAmp + 13.5 V gM 6 EAO to 15 V 3 V 3 V GND 4 Start Up AdjustAmp 5 ADJ and + Fault Adjust Protection Logic 500Ω Copyright © 2016,Texas Instruments Incorporated 7.3 Feature Description 7.3.1 DifferentialCurrentSenseAmplifier(CS+,CS−,CSO) The UCC39002 features a high-gain and high-precision amplifier to measure the voltage across a low-value current sense resistor. Because the amplifier is fully uncommitted, the current sense gain is user programmable. The extremely low input offset voltage of the UCC39002 current sense amplifier makes it suitable to measure current information across a low value sense resistor. Furthermore, the input common mode range includes groundandthepositivesupplyrailoftheUCC39002(V ).Accordingly,thecurrentsenseresistorcanbeplaced DD in the ground return path or in the positive output rail of the power supply V as long as V ≤ V . The current O O DD senseamplifierisnotunitygainstableandmusthaveaminimumgainofthree. 7.3.2 LoadShareBusDriverAmplifier(CSO) This is a unity-gain buffer amplifier to provide separation between the load share bus voltage and the output of the current sense amplifier. The circuit implements an ideal diode with virtually 0-V forward voltage drop by placing the diode inside the feedback loop of the amplifier. The diode function is used to automatically establish the role of the master module in the system. The UCC39002 which is assigned to be the master uses the load sharebusdriveramplifiertocopyitsoutputcurrentinformationontotheloadsharebus. Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com Feature Description (continued) All slave units, with lower output current levels by definition, have this ideal diode reversed biased (V < V ). CSO LS Consequently, the V and V signals will be separated. That allows the error amplifier of the UCC39002 to CSO LS compare its respective module’s output current to the master module’s output current and make the necessary correctionstoachieveabalancedcurrentdistribution. Since the bus is always driven by a single load share bus driver amplifier, the number of modules (n) are limited bytheoutputcurrentcapabilityoftheamplifieraccordingtoEquation1: 100 kW´I n= OUT,MIN V LS,FULL_SCALE where • 100kΩistheinputimpedanceoftheLSpinasshownintheblockdiagram, • I isgiveninthedatasheet OUT,MIN • andV isthemaximumvoltageontheloadsharebusatfullload. (1) LS,FULL_SCALE NOTE The number of parallel units can be increased by reducing the full scale bus voltage, that is,byreducingthecurrentsensegain. 7.3.3 LoadShareBusReceiverAmplifier(LS) The load share bus receiver amplifier is a unity-gain buffer monitoring the load share bus voltage. Its primary purpose is to ensure that the load share bus is not loaded by the internal impedances of the UCC39002. The LS pin is already internally compensated and has an internal 15-kHz filter. Adding external capacitance, including straycapacitance,mustbeavoidedtomaintainstability 7.3.4 ErrorAmplifier(EAO) As pictured in the block diagram, the UCC39002 employs a transconductance also called g type error amplifier. M Theg amplifierwaschosenbecauseitrequiresonlyonepin,theoutputtobeaccessibleforcompensation. M The purpose of the error amplifier is to compare the average, per module current level to the output current of the respective module controlled by the UCC39002. It is accommodated by connecting the buffered V voltage LS to its noninverting input and the V signal to its inverting input. If the average per module current, represented CSO by the load share bus is higher than the module’s own output current, an error signal will be developed across the compensation components connected between the EAO pin and ground. The error signal is than used by the adjust amplifier to make the necessary output voltage adjustments to ensure equal output currents among the paralleloperatedpowersupplies. In case the UCC39002 assumes the role of the master load share controller in the system or it is used in conjunction with a stand alone power module, the measured current signal on V is approximately equal to the CSO V voltage.Toavoiderroneousoutputvoltageadjustment,theinputoftheerroramplifierincorporatesatypically LS 25-mV offset to ensure that the inverting input of the error amplifier is biased higher than the noninverting input. Consequently,whenthetwosignalsareequal,therewillbenoadjustmentmadeandtheinitialoutputvoltageset pointismaintained. 7.3.5 AdjustAmplifierOutput(ADJ) A current proportional to the error voltage V on pin 6 is sunk by the ADJ pin. This current flows through the EAO adjustresistorR andchangestheoutputvoltageofthemodulecontrolledbytheUCC39002.Theamplitudeof ADJ the current is set by the 500-Ω internal resistor between ground and the emitter of the amplifier’s open collector outputtransistoraccordingtoFigure2.TheadjustcurrentvalueisgiveninEquation2: V I = EAO ADJ 500 W (2) At the master module V is 0 V, thus the adjust current must be zero as well. This ensures that the output EAO voltageofthemastermoduleremainsatitsinitialoutputvoltagesetpointatalltimes. 8 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 Feature Description (continued) Furthermore, at insufficient bias level, during a fault or when the UCC39002 is disabled, the noninverting input of the adjust amplifier is pulled to ground to prevent erroneous adjustment of the module’s output voltage by the loadsharecontroller. 7.3.6 EnableFunction(CS+,CS−) The two inputs of the current sense amplifier are also used for implementing an ENABLE function. During normal operation CS− = CS+ and the internal offset added between the CS− voltage and the inverting input of the enable comparator ensures that the UCC39002 is always enabled. By forcing the CS− pin approximately 0.5 V above the CS+ pin, the UCC39002 can be forced into a disable mode. While disabled, the UCC39002 disconnectsitselffromtheloadsharebusanditsadjustcurrentiszero. CS+ 2 + ENABLE 0.5 V + CS− 1 Figure2. EnableComparator 7.3.7 FaultProtection Accidentally, the load share bus might be shorted to ground or to the positive bias voltage of the UCC39002. These events might result in erroneous output voltage adjustment. For that reason, the load share bus is continuouslymonitoredbyawindowcomparatorasshowninFigure3. VDD−0.7 V + LS 7 FAULT + R CSO 8 2R Figure3. FaultProtectionComparators The FAULT signal is handled by the start-up and adjust logic which pulls the noninverting input of the adjust amplifierlowwhentheFAULTsignalisasserted. 7.3.8 Start-UpandAdjustLogic The start-up and adjust logic responds to unusual operating conditions during start up, fault and disable. Under these circumstances the information obtainable by the error amplifier of the UCC39002 is not sufficient to make the right output voltage adjustment, therefore the adjust amplifier is forced to certain known states. Similarly, the driveramplifierofUCC39002isdisabledduringtheseconditions. In the UCC39002 and UCC29002, during start-up, the load share driver amplifier is disabled by the disconnect switch and the adjust amplifier is forced to sink the maximum current through the adjust resistor. This operating mode ensures that the module controlled by the UCC39002 will be able to quickly engage in sharing the load current since its output will be adjusted to a sufficiently high voltage immediately at turnon. Both the load share driver and the adjust amplifiers revert to normal operation as soon as the measured current exceeds 80% of the average per module current level represented by the LS bus voltage. The UCC29002 and UCC29001 does not have this logic at start up. In this way, the UCC2900x does not adjust the output of the module to its maximum adjustmentrangeatturnonandengagesloadsharingatmoremoderaterate. Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com Feature Description (continued) In case of a fault shorting the load share bus to ground or to the bias of the UCC39002 the load share bus driver and the adjust amplifiers are disabled. The same action takes place when the UCC39002 is disabled using the CS+andCS−pinsorwhenthebiasvoltageisbelowtheminimumoperatingvoltage. 7.3.9 BiasandBiasOKCircuit(VDD) The UCC39002 is built on a 15-V, high-performance BiCMOS process. Therefore, the maximum voltage across the V and GND pins (pin 3 and 4 respectively) is limited to 15 V. The recommended maximum operating DD voltage is 13.5 V which corresponds to the tolerance of the on-board 14.2-V Zener clamp circuit. In case the bias voltage could exceed the 13.5-V limit, the UCC39002 should be powered through a current limiting resistor. The currentintotheV pinmustbelimitedto10mAaslistedinAbsoluteMaximumRatings. DD The bypass capacitor for VDD is also the compensation for the input active clamp of the device and, as such, mustbeplacedasclosetothedevicepins(VDDandGND)aspossible,usingagood-quality,low-ESLcapacitor, includingtracelength.Thedeviceisoptimizedforacapacitorvalueof0.1µFto1 µF. VDD 3 VBIAS (Internal Bias) 14.2 V + Bias_OK GND 4 4.375 V Figure4. V ClampandBiasMonitor DD The UCC39002 does not have an undervoltage lockout circuit. The bias OK comparator works as an enable function with a 4.375-V threshold. While V < 4.375 V the load share control functions are disabled. While this DD might be inconvenient for some low voltage applications it is necessary to ensure high accuracy. The load share accuracy is dependent on working with relatively large signal amplitudes on the load share bus. If the internal offsets, current sense error and ground potential difference between the UCC39002 controllers are comparable inamplitudetotheloadsharebusvoltage,theycancausesignificantcurrentdistributionerrorinthesystem.The maximum voltage on the load share bus is limited approximately 1.7 V below the bias voltage level (V ) which DD would result in an unacceptably low load share bus amplitude therefore poor accuracy at low V levels. To DD circumvent this potential design problem, the UCC39002 does not operate below the above mentioned 4.375-V bias voltage threshold. If the system does not have a suitable bias voltage available to power the UCC39002, TI recommends using an inexpensive charge pump which can generate the bias voltage for all the UCC39002s in theloadsharesystem. The maximum V of the UCC39002 is 15 V. For higher-voltage applications, use the application solution as DD recommended in Figure 5. A Zener clamp on the VDD pin is provided internally so the device can be powered fromhighervoltagerailsusingaminimumnumberofexternalcomponents. TheCSAinputsmustbeadjustedsoastonotexceedtheirabsolutemaximumvoltageratings. 10 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 Feature Description (continued) LOAD CURRENT DIRECTION VOUT+ R ADJ SNS+ RBIAS1 LOAD POWER SUPPLY UCC39002 SYSTEM OUTPUT GROUND 1 CS− CSO 8 LS BUS 2 CS+ LS 7 TOOTHER UCC39002 DEVICES 3 VDD EAO 6 C COMP R C BIAS2 BIAS 4 GND ADJ 5 R POWER SUPPLY COMP OUTPUT SNS− R SHUNT VOUT− Copyright © 2016,Texas Instruments Incorporated Figure5. HighVoltageApplication The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power modulesforloadsharing. 7.3.10 ParallelingthePowerModules • V =nominaloutputvoltageofthemodulestobeparalleled OUT • I =maximumoutputcurrentofeachmoduletobeparalleled OUT(max) • ΔV =maximumoutputvoltageadjustmentrangeofthepowermodulestobeparalleled ADJ • N=numberofmodules NOTE The power modules to be paralleled must be equipped with true remote sense or access tothefeedbackdividerofthemodule’serroramplifier. A typical high side application for a single module is shown in Figure 6 and is repeated for each module to be paralleled. Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com Feature Description (continued) RSHUNT 0.005Ω V+ P1 R15 C13 1 nF V− 274Ω TP11 R16 16.2 kΩ TP12 E R13 UL 274Ω U1 D UCC39002 O RSENSE R M 200Ω R18 1 CS− CSO 8 RADJUST E W 1 kΩ O 2 CS+ LS 7 V+ P Q1 C12 TP13 REAO V− Load SB2 475Ω 3 VDD EAO 6 R19 R14 C11 47 kΩ 16.2 kΩ 0.47µF CEAO S+ 4 GND ADJ 5 47µF S1 S− Load Share Bus Copyright © 2016,Texas Instruments Incorporated Figure6. TypicalHigh-SideApplicationforSinglePowerModule In Figure 6, P1 represents the output voltage terminals of the module, S1 represents the remote sense terminals of the module, and a signal on the SB2 terminal will enable the disconnect feature of the device. The load share busisthecommonbusbetweenalloftheparalleledloadsharecontrollers.VDDmustbedecoupledwithagood- qualityceramiccapacitorreturneddirectlytoGND. 7.3.11 MeasuringtheLoopoftheModules Using the configuration in Figure 7, measure the unity-gain crossover frequency of the power modules to be paralleled.AtypicalresultantbodeplotisshowninFigure8. + + + VOUT VIN DC−DC Module 50W Load + SENSE XFRMR Source Channel Channel Out A B NetworkAnalyzer Figure7. Unity-GainCrossoverFrequencyMeasurementConnectionDiagram 12 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 Feature Description (continued) 40 30 20 10 B d − 0 n ai G −10 UNITYGAIN −20 CROSSOVER FREQUENCY −30 fCO= 40 Hz −40 1 10 100 1000 f−Frequency−Hz Figure8. PowerModuleBodePlot 7.4 Device Functional Modes 7.4.1 Fault This condition occurs if the load share bus is shorted high or low. Under this condition the device responds by pullingtheinvertinginputoftheadjustamplifierlow.SeeFaultProtection fordetails. 7.4.2 Start-Up During start up the load share driver amplifier is disabled and the adjust amplifier is forced to sink the maximum currentthroughtheadjustresistor.SeeStart-UpandAdjustLogic fordetails. Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The UCC39002 is an advanced, high-performance load-share controller that provides all the necessary functions to parallel multiple independent power supplies or DC-to-DC modules. This load-share circuit is based upon the automatic master or slave architecture used in the UC3902 and the UC3907 load-share controllers providing betterthan1%current-shareerrorbetweenthemodulesatfullload. 14 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 8.2 Typical Application R SHUNT V+ R ADJ S+ UCC39002 1 CS− CSO 8 POWER SUPPLY 2 CS+ LS 7 WITH REMOTE SENSE 3 VDD EAO 6 4 GND ADJ 5 S− V− R SHUNT VV++ R ADJ S+ UCC39002 1 CS− CSO 8 POWER SUPPLY 2 CS+ LS 7 WITH LOAD REMOTE SENSE 3 VDD EAO 6 4 GND ADJ 5 S− V− R SHUNT VV++ R ADJ S+ UCC39002 1 CS− CSO 8 POWER SUPPLY 2 CS+ LS 7 WITH REMOTE SENSE 3 VDD EAO 6 4 GND ADJ 5 S− V− Figure9. TypicalHigh-SideCurrent-SensingApplication Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com Typical Application (continued) 8.2.1 DesignRequirements In order to properly configure and design with the UCC39002 it necessary to gather requirements for the followingsystemlevelperformancemetrics. 1. Required system level stability to include phase margin (φ ), gain margin (g ), and bandwidth (f ). Typical m m bw valuesareφ =45°,g =10dB,andf =f /10wheref istheswitchingfrequency. m m bw s s 2.Requiredcurrentsharingaccuracy.Typicallythisis1%. 8.2.2 DetailedDesignProcedure The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power modulesforloadsharing. 8.2.2.1 TheShuntResistor Selection of the shunt resistor is limited by its voltage drop at maximum module output current. This voltage drop shouldbemuchlessthanthevoltageadjustmentrangeofthemoduleshowninEquation3: I ´R <<DV OUT(max) SHUNT ADJ(max) (3) Other limitations for the sense resistor are the desired minimum power dissipation and available component ratings. 8.2.2.2 TheCSAGain The gain of the current sense amplifier is configured by the compensation components between Pin 1, CS−, and Pin 8, CSO, of the load share device. The voltage at the CSO pin is limited by the saturation voltage of the internalcurrentsenseamplifierandmustbeatleasttwovoltslessthanVDDinEquation4: V < VDD-2 V CSO(max) (4) ThemaximumcurrentsenseamplifiergainisequaltoEquation5: V A = CSO CSA R ´I SHUNT OUT(max) (5) Referring to Figure 6, the gain is equal to R16/R15 and a high-frequency pole, configured with C13, is used for noisefiltering.ThisimpedanceismirroredattheCS+pinofthedifferentialamplifierasshown. The current sense amplifier output voltage, V , serves as the input to the unity gain LS bus driver. The module CSO with the highest output voltage forward biases the internal diode at the output of the LS bus driver and determine the voltage on the load share bus, V . The other modules act as slaves and represent a load on the I of the LS VDD module due to the internal 100-kΩ resistor at the LS pin. This increase in supply current for the master module is equaltoN(V /100kΩ). LS 8.2.2.3 DeterminingR ADJUST The Sense+ terminal of the module is connected to the ADJ pin of the load-share controller. By placing a resistor between this ADJ pin and the load, an artificial Sense+ voltage is created from the voltage drop across R ADJUST due to the current sunk by the internal NPN transistor. The voltage at the ADJ pin must be maintained at approximately 1 V above the voltage at the EAO pin. This is necessary in order to keep the transistor at the output of the internal adjust amplifier from saturating. To fulfill this requirement, R is first calculated using ADJUST Equation6: ( ) DV -I ´R ´500 W ADJ(max) OUT(max) SHUNT R ³ ADJUST é æDV öù ADJ(max) êV -DV -1V-ç ´500 W÷ú êë OUT ADJ(max) çè RSENSE ÷øúû where • R isthecurrentsenseresistor, SHUNT • andR istheinternalresistancebetweenV andSENSE+withinthemodule. (6) SENSE OUT+ 16 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 Typical Application (continued) Also needed for consideration is the actual adjust pin current. The maximum sink current for the ADJ pin, I , ADJmax is 6 mA as determined by the internal 500-Ω emitter resistor and 3-V clamp. The value of adjust resistor, R , is based upon the maximum adjustment range of the module, ΔV . This adjust resistor is ADJUST ADJmax determinedusingEquation7: éDV -I ´R ù ë ADJ(max) OUT(max) SHUNTû R ³ ADJUST DV I - ADJ(max) ADJ(max) R SENSE (7) By selecting a resistor that meets both of these minimum requirements, the ADJ pin will be at least 1 V greater thantheEAOvoltageandtheadjustpinsinkcurrentwillnotexceedits6mAmaximum. 8.2.2.4 ErrorAmplifierCompensation The total load-share loop unity-gain crossover frequency, f , must be set at least one decade below the CO measured crossover frequency of the paralleled modules previously measured, f . (See Figure 8) CO(module) Compensation of the transconductance error amplifier is accomplished by placing the compensation resistor, R , and capacitor, C , between EAO and GND. The values of these components is determined using EAO EAO Equation8andEquation13. C =æç gM ö÷(A )(A )(A )(A (f )) EAO CSA V ADJ PWR CO 2p f è CO ø where • g isthetransconductanceoftheerroramplifier,typically14mS, M • f isequaltothedesiredcrossoverfrequencyinHzoftheloadshareloop,typicallyfCO(module)/10, CO • A istheCSAgain, CSA • A isthevoltagegain, V • A isthegainassociatedwiththeadjustamplifier, ADJ • |A (f )|isthemeasuredgainofthepowermoduleatthedesiredloadsharecrossoverfrequency,f , PWR CO CO convertedtoV/VfromdB (8) R16 A = CSA R15 (9) R V A = SHUNT, R = OUT V LOAD R I LOAD OUT(max) (10) R ´R A = ADJUST SENSE ADJ (R ´R )´500 W ADJUST SENSE (11) æG (f )ö APWR(fCO) =10çç MODU2L0E CO ÷÷ è ø where • G (f )isthemeasuredvalueofthegainfromFigure8,atthedesiredcrossoverfrequency. (12) MODULE co Once the C capacitor is determined, R is selected to achieve the desired loop response, using EAO EAO Equation13: æ 1 ö2 æ 1 ö2 R = ç ÷ -ç ÷ EAO çgm´ A (f )´A ´A ´A ÷ ç2p(f )(C )÷ è PWR CO V CSA ADJ ø è CO EAO ø (13) Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com Typical Application (continued) 8.2.3 ApplicationCurve 40 30 20 10 B d − 0 n ai G −10 UNITYGAIN −20 CROSSOVER FREQUENCY −30 fCO= 40 Hz −40 1 10 100 1000 f−Frequency−Hz Figure10. PowerModuleBodePlot 9 Power Supply Recommendations V must be decoupled with a good-quality ceramic capacitor returned directly to GND. The device is optimized DD foracapacitorvalueof0.1µFto1 µF. 10 Layout 10.1 Layout Guidelines The bypass capacitor for V is also the compensation for the input active clamp of the device and, as such, DD must be placed as close to the device pins (V and GND) as possible, using a good-quality, low-ESL capacitor, DD includingtracelength. 10.2 Layout Example V+ SHUNT VOUT S+ RES RES RES CAP Power Supply with 1 CS- CSO 8 Remote Sense 2 CS+ LS 7 LS BUS R ES 3 VDD EAO 6 C C A A P 4 GND ADJ 5 P S- RES CAP V- GND Figure11. LayoutExample 18 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 www.ti.com SLUS495I–SEPTEMBER2001–REVISEDMAY2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forfurtherdetails,refertothefollowingdocument: • Reference Design, 48-V , 12-V Loadshare System Using UCC39002 with Three DC/DC PH-100S4 IN OUT Modules,SLUA270 Foramorecompletedescriptionofgeneralloadsharingtopics,refertothefollowingdocuments. • Application Note, The UC3902 Load Share Controller and Its Performance in Distributed Power Systems, SLUA128 • ApplicationNote, UC3907LoadShareICSimplifiesParallelPowerSupplyDesign,SLUA147 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC29002 Clickhere Clickhere Clickhere Clickhere Clickhere UCC29002-1 Clickhere Clickhere Clickhere Clickhere Clickhere UCC39002 Clickhere Clickhere Clickhere Clickhere Clickhere 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks E2EisatrademarkofTexasInstruments. IntelisaregisteredtrademarkofIntelCorporation. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC29002 UCC39002

UCC29002,UCC29002-1,UCC39002 SLUS495I–SEPTEMBER2001–REVISEDMAY2016 www.ti.com 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 20 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC29002 UCC39002

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC29002D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 29002 & no Sb/Br) UCC29002D/1 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 290021 & no Sb/Br) UCC29002DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 29002 & no Sb/Br) UCC29002DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 29002 & no Sb/Br) UCC29002DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 105 29002 & no Sb/Br) UCC29002DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 29002 & no Sb/Br) UCC29002DR/1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 290021 & no Sb/Br) UCC29002P ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 105 UCC29002P (RoHS) UCC39002D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 39002 & no Sb/Br) UCC39002DGK ACTIVE VSSOP DGK 8 80 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR 0 to 70 39002 & no Sb/Br) UCC39002DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR 0 to 70 39002 & no Sb/Br) UCC39002DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 39002 & no Sb/Br) UCC39002P ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 UCC39002P (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC29002DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC29002DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC29002DR/1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC39002DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC39002DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC29002DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 UCC29002DR SOIC D 8 2500 340.5 338.1 20.6 UCC29002DR/1 SOIC D 8 2500 340.5 338.1 20.6 UCC39002DGKR VSSOP DGK 8 2500 366.0 364.0 50.0 UCC39002DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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