UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com UCC2800, UCC2801, UCCSL2U8S0227,0 GU C– MCA2R8C0H3 ,1 9U9C9 C– R2E8V0I4S,E UD CMCAY2 2800250 SLUS270G – MARCH 1999 – REVISED MAY 2020 UCC280x Low-Power BiCMOS Current-Mode PWM Controllers 1 Features 3 Description • 100-μA typical starting supply current The UCC280x family of high-speed, low-power • 500-μA typical operating supply current integrated circuits contain all of the control and drive • Operation up to 1 MHz components required for off-line and DC-to-DC fixed frequency current-mode switching mode power • Internal soft start supplies with minimal parts count. • Internal fault soft start • Internal leading-edge blanking of the current sense These devices have the same pin configuration as the signal UCx84x family, and also offer the added features of • 1-A totem-pole output internal full-cycle soft start and internal leading-edge blanking of the current-sense input. • 70-ns typical response from current-sense to gate drive output Device Information (1) • 1.5% tolerance voltage reference PART NUMBER PACKAGE BODY SIZE (NOM) • Same pinout as UC3842 and UC3842A UCC2800, UCC2801, 2 Applications UCC2802, SOIC (8) 3.91 mm × 4.90 mm UCC2803, • Switch mode power supplies (SMPS) UCC2804, • DC-to-DC converters UCC2805 • Power modules (1) For all available packages, see the orderable addendum at • Automotive PSU the end of the data sheet. • Battery-operated PSU Vin Vout UCC2803 7VCC OUT6 8REF CS3 Cin FB2 Cout 4RC GND COMP 5 1 Copyright © 2016, Texas Instruments Incorporated Simplified Application Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyrighint t©e l2le0c2t0u Tael xparso Ipnesrtrtuym meanttste Irnsc oarnpdor aottehder important disclaimers. PRODUCTION DATA. Submit Document Feedback 1

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com Table of Contents 1 Features............................................................................1 9.3 Feature Description...................................................11 2 Applications.....................................................................1 9.4 Device Functional Modes..........................................25 3 Description.......................................................................1 10 Application and Implementation................................26 4 Revision History..............................................................2 10.1 Application Information...........................................26 5 Description (continued)..................................................3 10.2 Typical Application..................................................26 6 Device Comparison Table...............................................3 11 Power Supply Recommendations..............................36 7 Pin Configuration and Functions...................................3 12 Layout...........................................................................37 Pin Functions....................................................................3 12.1 Layout Guidelines...................................................37 8 Specifications..................................................................6 12.2 Layout Example......................................................38 8.1 Absolute Maximum Ratings........................................6 13 Device and Documentation Support..........................39 8.2 ESD Ratings...............................................................6 13.1 Support Resources.................................................39 8.3 Recommended Operating Conditions.........................6 13.2 Trademarks.............................................................39 8.4 Thermal Information....................................................7 13.3 Electrostatic Discharge Caution..............................39 8.5 Electrical Characteristics.............................................7 13.4 Glossary..................................................................39 8.6 Typical Characteristics................................................9 13.5 Related Links..........................................................39 9 Detailed Description......................................................11 14 Mechanical, Packaging, and Orderable 9.1 Overview...................................................................11 Information....................................................................40 9.2 Functional Block Diagram.........................................11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (June, 2016) to Revision G (May, 2020) Page • Added Power Supply section to reflect power up of the device..........................................................................6 Changes from Revision E (June2016) to Revision F (*) Page • Added Maximum Junction Temperature ............................................................................................................6 • Added Recommended junction temperature range ...........................................................................................6 Changes from Revision D (August 2010) to Revision E (May 2016) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section...................1 Changes from Revision A (September 2000) to Revision B (June 2004) Page • Updated Abs Max Table to read: Analog Inputs (FB, CS, RC, COMP)... –0.3V to the lesser of 6.3V or VCC + 0.3V From: Analog Inputs (FB, CS)... –0.3V to 6.3V..........................................................................................6 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 5 Description (continued) The UCC280x family offers a variety of package options, temperature range options, choice of maximum duty cycle, and choice of critical voltage levels. Lower reference parts such as the UCC2803 and UCC2805 fit best into battery-operated systems, while the higher reference and higher UVLO hysteresis of the UCC2802 and UCC2804 make these ideal choices for use in off-line power supplies. The UCC280x series is specified for operation from –40°C to 125°C. 6 Device Comparison Table Device Comparison Table PART NUMBER MAXIMUM DUTY CYCLE REFERENCE VOLTAGE TURNON THRESHOLD TURNOFF THRESHOLD UCC2800 100% 5 V 7.2 V 6.9 V UCC2801 50% 5 V 9.4 V 7.4 V UCC2802 100% 5 V 12.5 V 8.3 V UCC2803 100% 4 V 4.1 V 3.6 V UCC2804 50% 5 V 12.5 V 8.3 V UCC2805 50% 4 V 4.1 V 3.6 V Temperature and Package Selection Table TEMPERATURE RANGE AVAILABLE PACKAGES UCC280x –40°C to 125°C D 7 Pin Configuration and Functions COMP 1 8 REF FB 2 7 VCC CS 3 6 OUT RC 4 5 GND Figure 7-1. UCC280x D Package 8-Pin SOIC Top View Pin Functions PIN I/O DESCRIPTION NAME SOIC COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the UCC280x family is a true, low output impedance, 2- MHz operational amplifier. As such, the COMP terminal can both source and sink COMP 1 O current. However, the error amplifier is internally current-limited, so the user can command zero duty cycle by externally forcing COMP to GND. The UCC280x family features built-in full-cycle soft start. Soft start is implemented as a clamp on the maximum COMP voltage. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com PIN I/O DESCRIPTION NAME SOIC CS is the input to the current sense comparators. The UCC280x family has two different current sense comparators: the PWM comparator and an overcurrent comparator. The UCC280x family contains digital current sense filtering, which disconnects the CS terminal from the current sense comparator during the 100-ns interval immediately following the rising edge of the OUT pin. This digital filtering, also CS 3 I called leading-edge blanking, means that in most applications, no analog filtering (RC filter) is required on CS. Compared to an external RC filter technique, the leading-edge blanking provides a smaller effective CS to OUT propagation delay. Note, however, that the minimum non-zero On-time of the OUT signal is directly affected by the leading-edge-blanking and the CS to OUT propagation delay. The overcurrent comparator is only intended for fault sensing, and exceeding the overcurrent threshold causes a soft-start cycle. FB is the inverting input of the error amplifier. For best stability, keep FB lead FB 2 I length as short as possible and FB stray capacitance as small as possible. GND 5 — GND is reference ground and power ground for all functions on this part. NC — — No connection pins OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding ±750 mA. OUT is actively held low when VCC is below the UVLO threshold. OUT 6 O The high-current power driver consists of FET output devices, which can switch all of the way to GND and all of the way to V . The output stage also provides a CC very low impedance to overshoot and undershoot. This means that in many cases, external schottky clamp diodes are not required. PWR GND — — Power ground of the IC RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor charging current by connecting a resistor from REF to RC. Set frequency by connecting a timing capacitor from RC to GND. For best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The frequency of oscillation can be estimated with the following equations: 1.5 = f R´C (1) RC 4 I 1.0 = f R´C (2) where • frequency is in Hz • resistance is in Ω • capacitance is in farads The recommended range of timing resistors is between 10 k and 200 k, and timing capacitor is 100 pF to 1000 pF. Never use a timing resistor less than 10 k. 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 PIN I/O DESCRIPTION NAME SOIC REF is the voltage reference for the error amplifier, and also for many other functions on the IC. REF is also used as the logic power supply for high-speed switching logic on the IC. When VCC is greater than 1 V and less than the UVLO threshold, REF is pulled to ground through a 5-kΩ resistor. This means that REF can be used as a logic output indicating power system status. It is important for reference stability that REF 8 O REF is bypassed to GND with a ceramic capacitor as close to the pin as possible. An electrolytic capacitor may also be used in addition to the ceramic capacitor. A minimum of 0.1-μF ceramic is required. Additional REF bypassing is required for external loads greater than 2.5 mA on the reference. To prevent noise problems with high speed switching transients, bypass REF to ground with a ceramic capacitor very close to the IC package. VCC is the power input connection for this device. In normal operation, VCC is powered through a current limiting resistor. Although quiescent VCC current is very low, total supply current is higher depending on OUT current. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Q ), average g OUT current can be calculated from: VCC 7 I I =Q ´ f OUT g (3) To prevent noise problems, bypass VCC to GND with a ceramic capacitor as close to the VCC pin as possible. An electrolytic capacitor may also be used in addition to the ceramic capacitor. There must be a minimum of 1 µF in parallel with a 0.1-µF ceramic capacitor from VCC to ground placed close to the device. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VCC voltage(3) 12 V VCC current(3) 30 mA OUT current ±1 A OUT energy (capacitive load) 20 µJ Analog inputs (FB, CS, RC, COMP) –0.3 6.3 or VCC + 0.3(4) V N or J package 1 Power dissipation at T < 25°C D package 0.65 W A L package 1.375 Lead temperature, soldering (10 s) 300 °C Storage Temperature, T –65 150 °C stg Junction Temperature, T -55 150 °C J (1) All voltages are with respect to GND. All currents are positive into the specified terminal. (2) Stresses beyond those listed under Section 8.1 may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 8.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (3) In normal operation Vcc is powered through a current limit resistor. The resistor must be sized so that the VCC voltage under all operating conditions is below 12 V but above the turnoff threshold. Absolute maximum of 12 V applies when VCC is driven from a low impedance source such that ICC does not exceed 30mA. Failure to limit VCC and ICC to these limits may result in permanent damage of the device. This is further discussed in the Section 11. (4) Return the minimum (lesser) value of the two. 8.2 ESD Ratings VALUE UNIT D PACKAGES Human-body model (HBM), per AEC Q100-002(1) ±2500 V Electrostatic discharge V (ESD) Charged-device model (CDM), per AEC Q100-011(1) ±1500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specifications. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V VCC bias supply voltage from low impedance source 11 V VCC V , V , FB CS Voltage on analog pins –0.1 6 or V V V , V VCC RC COMP V Gate driver output voltage –0.1 V V OUT VCC I Supply bias current 25 mA VCC I Average OUT pin current 20 mA OUT I REF pin output current 5 mA REF f Oscillator frequency 1 MHz OSC T Operating free-air temperature –55 125 °C A T Junction Temperature -55 125 °C J 6 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 8.4 Thermal Information UCC280x THERMAL METRIC(1) D (SOIC) UNIT 8 PINS R Junction-to-ambient thermal resistance 107.5 °C/W θJA R Junction-to-case (top) thermal resistance 49.3 °C/W θJC(top) R Junction-to-board thermal resistance 48.7 °C/W θJB ψ Junction-to-top characterization parameter 6.6 °C/W JT ψ Junction-to-board characterization parameter 48 °C/W JB R Junction-to-case (bottom) thermal resistance — °C/W θJC(bot) (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 8.5 Electrical Characteristics –40°C ≤ T ≤ 125°C for UCC280x. V = 10 V(1), RT = 100 k from REF to RC, CT = 330 pF from RC to GND, A CC 0.1-uF capacitor from V to GND, 0.1-uF capacitor from V to GND, and T = T (unless otherwise noted). CC REF A J PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE TJ= 25°C, I = 0.2 mA, UCC2800, UCC2801, UCC2802, and 4.925 5 5.075 Output voltage UCC2804 V TJ= 25°C, I = 0.2 mA, UCC2803 and UCC2805 3.94 4 4.06 Load regulation 0.2 mA < I < 5 mA UCC280x 10 30 mV TJ = 25°C, VCC = 10 V to clamp (IVCC = 25 mA) 1.9 Line regulation TJ = –40°C to 125°C, VCC = 10 V to UCC280x 2.5 mV/V clamp (IVCC = 25 mA) UCC2800, UCC2801, UCC2802, and UCC2804(5) 4.88 5 5.1 Total variation V UCC2803 and UCC2805(5) 3.9 4 4.08 Output noise voltage 10 Hz ≤ f ≤ 10 kHz, TJ= 25°C(7) 130 µV Long term stability TA = 125°C, 1000 hours(7) 5 mV Output short circuit –5 –35 mA OSCILLATOR UCC2800, UCC2801, UCC2802, UCC2804(2) 40 46 52 Oscillator frequency kHz UCC2803 and UCC2805(2) 26 31 36 Temperature stability(7) 2.5 % Amplitude peak-to-peak 2.25 2.4 2.55 V Oscillator peak voltage 2.45 V ERROR AMPLIFIER COMP = 2.5 V, UCC2800, UCC2801, UCC2802, and UCC2804 2.44 2.5 2.56 Input voltage V COMP = 2 V, UCC2803 and UCC2805 1.95 2 2.05 Input bias current –1 1 µA Open loop voltage gain 60 80 dB COMP sink current FB = 2.7 V, COMP = 1.1 V UCC280x 0.3 3.5 mA COMP source current FB = 1.8 V, COMP = REF – 1.2 V –0.2 –0.5 –0.8 mA Gain bandwidth product(7) 2 MHz Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com –40°C ≤ T ≤ 125°C for UCC280x. V = 10 V(1), RT = 100 k from REF to RC, CT = 330 pF from RC to GND, A CC 0.1-uF capacitor from V to GND, 0.1-uF capacitor from V to GND, and T = T (unless otherwise noted). CC REF A J PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM UCC2800, UCC2802, and UCC2803 97 99 100 Maximum duty cycle % UCC2801, UCC2804, and UCC2805 48 49 50 CURRENT SENSE Gain(3) 1.1 1.65 1.8 V/V Maximum input signal COMP = 5 V(4) 0.9 1 1.1 V Input bias current –200 200 nA CS blank time 50 100 150 ns Overcurrent threshold 1.42 1.55 1.68 V COMP to CS offset CS = 0 V 0.45 0.9 1.35 V OUTPUT I = 20 mA, all parts 0.1 0.4 I = 200 mA, all parts 0.35 0.9 OUT low level V I = 50 mA, VCC = 5 V, UCC2803 and UCC2805 0.15 0.4 I = 20 mA, VCC = 0 V, all parts 0.7 1.2 I = 20 mA, all parts 0.15 0.4 OUT high VSAT (VCC-OUT) I = 200 mA, all parts 1 1.9 V I = 50 mA, VCC = 5 V, UCC2803 and UCC2805 0.4 0.9 Rise time CL = 1 nF 41 70 ns Fall time CL = 1 nF 44 75 ns UNDERVOLTAGE LOCKOUT UCC2800 6.6 7.2 7.8 UCC2801 8.6 9.4 10.2 Start threshold(6) V UCC2802 and UCC2804 11.5 12.5 13.5 UCC2803 and UCC2805 3.7 4.1 4.5 UCC2800 6.3 6.9 7.5 UCC2801 6.8 7.4 8 Stop threshold(6) V UCC2802 and UCC2804 7.6 8.3 9 UCC2803 and UCC2805 3.2 3.6 4 UCC2800 0.12 0.3 0.48 UCC2801 1.6 2 2.4 Start to stop hysteresis V UCC2802 and UCC2804 3.5 4.2 5.1 UCC2803 and UCC2805 0.2 0.5 0.8 SOFT START COMP rise time FB = 1.8 V, rise from 0.5 V to REF – 1 V 4 10 ms OVERALL Start-up current VCC < start threshold 0.1 0.2 mA Operating supply current FB = 0 V, CS = 0 V 0.5 1 mA VCC internal Zener voltage ICC = 10 mA(6) (8) 12 13.5 15 V VCC internal Zener voltage minus UCC2802 and UCC2804(6) 0.5 1 V start threshold voltage (1) Adjust VCC above the start threshold before setting at 10 V. (2) Oscillator frequency for the UCCx800, UCC2802, and UCC2803 is the output frequency. Oscillator frequency for the UCC2801, UCC2804, and UCC2805 is twice the output frequency. (3) Gain is defined by: A = ΔV / Δ V . 0 ≤ V ≤ 0.8 V COMP CS CS (4) Parameter measured at trip point of latch with Pin 2 at 0 V. (5) Total variation includes temperature stability and load regulation. (6) Start threshold, stop threshold, and Zener shunt thresholds track one another. (7) Ensured by design. Not 100% tested in production. (8) The device is fully operating in clamp mode, as the forcing current is higher than the normal operating supply current. 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 8.6 Typical Characteristics 4.00 3.98 3.96 3.94 V) 3.92 ( F E R 3.90 V 3.88 3.86 3.84 3.82 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 VCC(V) Figure 8-2. UCC2803 and UCC2805V vs V , REF CC Figure 8-1. Error Amplifier Gain and Phase I = 0.5 mA LOAD Response 1000 1000 z) z) H H k k ( ( q. q. e e Oscillator Fr 100 132030000pppFFF Oscillator Fr 100 321300000pppFFF 10 1nF 10 1nF 10 100 1000 10 100 1000 RT(k ) RT(k ) Figure 8-3. UCC2800, UCC2801, UCC2802, and Figure 8-4. UCC2803 and UCC2805 Oscillator UCC2804 Oscillator Frequency vs R and C Frequency vs R and C T T T T 100 50 99.5 49.5 %) 99 %) e ( 98.5 e ( 49 mum Duty Cycl 9799.578 CT= 33C0TpF= 200pCFT= 100pF mum Duty Cycl 484.85 CT= 330pCFT= 200CpTF= 100pF axi 96.5 axi 47.5 M M 96 47 95.5 95 46.5 10 100 1000 10 100 1000 Oscillator Frequency (kHz) Oscillator Frequency (kHz) Figure 8-5. UCC2800, UCC2802, and UCC2803 Figure 8-6. UCC2801, UCC2804, and UCC2805 Maximum Duty Cycle vs Oscillator Frequency Maximum Duty Cycle vs Oscillator Frequency Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 16 8 14 7 (mA) 11802 VCC =V C1 C0 V=, 18nV,F 1nF (mA) 456 VCC V= C 1 C 0 V=, 81Vn, F1nF C C IC 246 VC VC C=C 1=0 V8,V N, No oL oLaodad IC 123 VC VC C =C 1=0 V8,V N, No oL oLaodad 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Oscillator Frequency (kHz) Oscillator Frequency (kHz) Figure 8-7. UCC2800 I vs Oscillator Frequency Figure 8-8. UCC2805 I vs Oscillator Frequency CC CC 1.1 s) 1.0 olt V et ( 0.9 s Off CS 0.8 Slope = 1.8mV/°C o Pt 0.7 M O C 0.6 0 -55-50 -25 0 25 50 75 100 125 Temperature (°C) Figure 8-10. COMP to CS Offset vs Temperature, CS = 0 V Figure 8-9. Dead Time vs C , R = 100 k T T 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 9 Detailed Description 9.1 Overview The UCC280x family of high-speed, low-power integrated circuits contain all of the control and drive components required for off-line and DC-to-DC fixed-frequency, current-mode switching mode power supplies with minimal parts count. These devices have the same pin configuration as the UCx84x family, and also offer the added features of internal full-cycle soft start and internal leading-edge blanking of the current-sense input. 9.2 Functional Block Diagram FB COMP CS 2 1 3 VCC 7 Leading Edge UCCx801 Blanking UCCx804 1.5V UCCx805 VCC Over-Current REF/2 only OK T Q S Q OUT R 0.65R Oscillator S Q 6 R 4V Voltage S Q PWM Reference Latch REF R 13.5V OK 0.5V Logic Power R 1V Full Cycle Soft Start j=4ms GND 5 8 4 REF RC Copyright © 2016, Texas Instruments Incorporated 9.3 Feature Description The UCC280x family offers numerous advantages that allow the power supply design engineer to meet these challenging requirements. Features include: • Bi-CMOS process • Low starting supply current: typically 100 μA • Low operating supply current: typically 500 μA • Pinout compatible with UC3842 and UC3842A families • 5-V operation (UCC2803 and UCC2805) • Leading edge blanking of current sense signal • On-chip soft start • Internal full cycle restart delay • 1.5% voltage reference • Up to 1-MHz oscillator • Low self-biasing output during UVLO • Very few external components required • 70-ns response from current sense to output • Available in surface-mount or PDIP package Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com The UCC280x family of devices are pinout compatible with the UCx84x and UCx84xA families. However, they are not plug-in compatible. In general, the UCC280x requires fewer external components and consumes less operating current. 9.3.1 Detailed Pin Description 9.3.1.1 COMP Unlike other devices, the error amplifier in the UCC280x family is a true, low output impedance, 2-MHz operational amplifier. As such, the COMP terminal can both source and sink current. However, the error amplifier is internally current-limited, so that one can command zero duty cycle by externally forcing COMP to GND. The UCC280x has a true low output impedance error amplifier which both sources and sinks current. The error amplifier associated with the UC3842 family is an open collector in parallel with a current source. The UCC280x has power-up soft start and fault soft start built on-chip with a fixed COMP rise time to 5 V in 4 ms. Therefore, no external soft-start circuitry is required, saving 1 resistor, 1 capacitor, and 1 PNP transistor. 9.3.1.2 FB FB is the inverting input of the error amplifier. For best stability, keep FB lead length as short as possible and FB stray capacitance as small as possible. The UCC280x features a 2-MHz bandwidth error amplifier versus 1 MHz on the UC3842 family. Feedback techniques are identical to the UC3842 family. 9.3.1.3 CS CS is the PWM comparator and an overcurrent comparator. The UCC280x family contains digital current sense filtering, which disconnects the CS terminal from the current sense comparator during the 100-ns interval immediately following the rising edge of the OUT pin. This digital filtering, also called leading-edge blanking, means that in most applications, no analog filtering (RC filter) is required on CS. Compared to an external RC filter technique, the leading-edge blanking provides a smaller effective CS to OUT propagation delay. Note, however, that the minimum non-zero on-time of the OUT signal is directly affected by the leading-edge-blanking and the CS to OUT propagation delay. The overcurrent comparator is only intended for fault sensing, and exceeding the overcurrent threshold causes a soft-start cycle. The UCC280x current sense is significantly different from its predecessor. The UC3842 family current sense input connects to only the PWM comparator. The UCC280x current sense input connects to two comparators: the PWM comparator and the overcurrent comparator. Internal leading edge blanking masks the first 100 ns of the current sense signal. This may eliminate the requirement for an RC current sense filter and prevent false triggering due to leading edge noises. Connect CS directly to MOSFET source current sense resistor. The gain of the current sense amplifier on the UCC280x family is typically 1.65 V/V versus typically 3 V/V with the UC3842 family. 9.3.1.4 RC RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor charging current by connecting a resistor from REF to RC. Set frequency by connecting timing capacitor from RC to GND. For the best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. The UCC280x’s oscillator allows for operation to 1 MHz versus 500 kHz with the UC3842 family. Both devices make use of an external resistor to set the charging current for the capacitor, which determines the oscillator frequency. For the UCC2802 and UCC2804, use Equation 4. 1.5 = f R´C (4) For the UCC2803 and UCC2805, use Equation 5. 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 1.0 = f R´C (5) In these two equations, switching frequency (f) is in Hz, R is in Ω, and C is in farads. The two equations are different due to different reference voltages. The recommended range of timing resistor values is between 10 kΩ and 200 kΩ; the recommended range of timing capacitor values is between 100 pF and 1000 pF. The peak-to-peak amplitude of the oscillator waveform is 2.45 V versus 1.7 V in UC3842 family. For best performance, keep the timing capacitor lead to GND as short as possible. TI recommends separate ground traces for the timing capacitor and all other pins. The maximum duty cycle for the UCC2802 and UCC2803 is approximately 99%; the maximum duty cycle for the UCC2803 and UCC2804 is approximately 49%. The duty cycle cannot be easily modified by adjusting R and C , unlike the UC3842A family. The maximum duty cycle T T limit is set by the ratio of the external oscillator charging resistor R and the internal oscillator discharge T transistor on-resistance, like the UC3842. However, maximum duty cycle limits less than 90% (for the UCC2802 and UCC2803) and less than 45% (for the UCC2804 and UCC2805) can not reliably be set in this manner. For better control of maximum duty cycle, consider using the UCCx807. 9.3.1.5 GND GND pin is the signal and power returning ground. TI recommends separating the signal return path and the high current gate driver path so that the signal is not affected by the switching current. 9.3.1.6 OUT OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currents exceeding 750 mA. OUT is actively held low when VCC is below the UVLO threshold. The high-current power driver consists of FET output devices, which can switch all of the way to GND and all of the way to VCC. The output stage also provides a low impedance to overshoot and undershoot. This means that in many cases, external Schottky clamp diodes are not required. The output of the UCC280x is a CMOS output versus a Bipolar output on the UC3842 family. Peak output current remains the same ±1 A. The CMOS output provides very smooth rising and falling waveforms, with virtually no overshoot or undershoot. Additionally, the CMOS output provides a low resistance to the supply in response to overshoot, and a low resistance to ground in response to undershoot. Because of this, Schottky diodes may not be necessary on the output. Furthermore, the UCC2802 has a self-biasing, active low output during UVLO. This feature eliminates the gate to source bleeder resistor associated with the MOSFET gate drive. Finally, no MOSFET gate voltage clamp is necessary with the UCC280x as the on-chip Zener diode automatically clamps the output to VCC. 9.3.1.7 VCC VCC is the power input connection for this device. In normal operation, VCC is powered through a current limiting resistor. Although quiescent VCC current is very low, total supply current is higher, depending on the OUT current. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 6. I =Q ´ f OUT g (6) The UCC280x has a lower VCC (supply voltage) clamp of 13.5 V typical versus 30 V on the UC3842. For applications that require a higher VCC voltage, a resistor must be placed in series with VCC to increase the source impedance. The maximum value of this resistor is calculated with Equation 7. V -V IN:min; VCC:max; R = max I +Q ×f VCC g (7) Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com In Equation 7, V (min) is the minimum voltage that is used to supply VCC, V (max) is the maximum VCC IN VCC clamp voltage and I is the IC supply current without considering the gate driver current and Q is the external VCC g power MOSFET gate charge and f is the switching frequency. Additionally, the UCC280x has an on-chip Zener diode to regulate VCC to 13.5 V. The turnon and turnoff thresholds for the UCC280x family are significantly different: 12.5 V and 8 V for the UCC2802 and UCC2804; 4.1 V and 3.6 V for the UCC2803 and UCC2805. 5-V PWM operation is now possible. To ensure against noise related problems, filter VCC with an electrolytic and bypass with a ceramic capacitor to ground. Keep the capacitors close to the IC pins. 9.3.1.8 Pin 8 (REF) REF is the voltage reference for the error amplifier and also for many other functions on the IC. REF is also used as the logic power supply for high-speed switching logic on the IC. When VCC is greater than 1 V and less than the UVLO threshold, REF is pulled to ground through a 5-kΩ resistor. This means that REF can be used as a logic output indicating power system status. It is important for reference stability that REF is bypassed to GND with a ceramic capacitor as close to the pin as possible. An electrolytic capacitor may also be used in addition to the ceramic capacitor. A minimum of 0.1-μF ceramic capacitor is required. Additional REF bypassing is required for external loads greater than 2.5 mA on the reference. To prevent noise problems with high-speed switching transients, bypass REF to ground with a ceramic capacitor close to the IC package. The UCC2802 and UCC2804 have a 5-V reference. The UCC2803 and UCC2805 have a 4-V reference; both ±1.5% versus ±2% on the UC3842 family. The output short-circuit current is lower 5 mA versus 30 mA. REF must be bypassed to ground with a ceramic capacitor to prevent oscillation and noise problems. REF can be used as a logic output; as when VCC is lower than the UVLO threshold, REF is held low. 9.3.2 Undervoltage Lockout (UVLO) The UCC280x devices feature undervoltage lockout protection circuits for controlled operation during power-up and power-down sequences. Both the supply voltage (VCC) and the reference voltage (Vref) are monitored by the UVLO circuitry. An active low, self-biasing totem pole output during UVLO design is also incorporated for enhanced power switch protection. Undervoltage lockout thresholds for the UCC2802, UCC2803, UCC2804, and UCC2805 devices are different from the previous generation of UCx842, UCx843, UCx844, and UCx845 PWMs. Basically, the thresholds are optimized for two groups of applications: off-line power supplies and DC-DC converters. The UCC2802 and UCC2804 feature typical UVLO thresholds of 12.5 V for turnon and 8.3 V for turnoff, providing 4.3 V of hysteresis. For low voltage inputs, which include battery and 5-V applications, the UCC2803 and UCC2805 turn on at 4.1 V and turn off at 3.6 V with 0.5 V of hysteresis. The UCC2800 and UCC2801 have UVLO thresholds optimized for automotive and battery applications. During UVLO the IC draws approximately 100 μA of supply current. Once crossing the turnon threshold the IC supply current increases typically to about 500 μA, over an order of magnitude lower than bipolar counterparts. 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 Figure 9-1. IC Supply Current at UVLO Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com Table 9-1. UVLO Level Comparison Table DEVICE Vton (V) Vtoff (V) UCC2800 7.2 6.9 UCC2801 9.4 7.4 UCC2802, UCC2804 12.5 8.3 UCC2803, UCC2805 4.1 3.6 9.3.3 Self-Biasing, Active Low Output The self-biasing, active low clamp circuit shown in Figure 9-2 eliminates the potential for problematic MOSFET turnon. As the PWM output voltage rises while in UVLO, the P device drives the larger N type switch ON, which clamps the output voltage low. Power to this circuit is supplied by the externally rising gate voltage, so full protection is available regardless of the ICs supply voltage during undervoltage lockout. 2 V V = OPEN CC V V = 2 V OUT CC V = 0 V CC V = 1 V 1 V CC 50 mA 100 mA I OUT Figure 9-2. Internal Circuit Holding OUT Low Figure 9-3. OUT Voltage vs OUT Current During During UVLO UVLO 9.3.4 Reference Voltage The traditional 5-V amplitude bandgap reference voltage of the UC3842 family can be also found on the UCC2800, UCC2801, UCC2802, and UCC2804 devices. However, the reference voltage of the UCC2803 and UCC2805 device is 4 V. This change was necessary to facilitate operation with input supply voltages below 5 V. Many of the reference voltage specifications are similar to the UC3842 devices although the test conditions have been changed, indicative of lower-current PWM applications. Similar to their bipolar counterparts, the BiCMOS devices internally pull the reference voltage low during UVLO, which can be used as a UVLO status indication. UCC380X REF R 0.1 µF TO BYPASS E/A+ R Copyright © 2016, Texas Instruments Incorporated Figure 9-4. Required Reference Bypass 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 Note that the 4-V reference voltage on the UCC2803 and UCC2805 is derived from the supply voltage (VCC) and requires about 0.5 V of headroom to maintain regulation. Whenever Vcc is below approximately 4.5 V, the reference voltage also drops outside of its specified range for normal operation. The relationship between VCC and V during this excursion is shown in Figure 9-5. REF 4.0 V 3.9 V 3.8 V F E R V 3.7 V 3.6 V 3.5 V 3.6 V 3.8 V 4.0 V 4.2 V 4.4 V 4.6 V 4.8 V 5.0 V V CC Figure 9-5. UCC2803 REF Output vs V VCC The noninverting input to the error amplifier is tied to half of the PWM's reference voltage, V . Note that this REF input is 2 V on the UCC2803 and UCC2805 and 2.5 V on the higher reference voltage parts: the UCC2800, UCC2801, UCC2802, and UCC2804. 9.3.5 Oscillator The UCC280x oscillator generates a sawtooth waveform on RC. The rise time is set by the time constant of R T and C . The fall time is set by C and an internal transistor on-resistance of approximately 130 Ω. During the fall T T time, the output is OFF and the maximum duty cycle is reduced below 50% or 100%, depending on the part number. Larger timing capacitors increase the discharge time and reduce the maximum duty cycle and frequency. REF 8 0.2V + RT R Q + S RC 4 2.65V C T Figure 9-6. Oscillator Equivalent Circuit The oscillator section of the UCC2800 through UCC2805 BiCMOS devices has few similarities to the UC3842 type — other than single pin programming. It does still use a resistor to the reference voltage and capacitor to ground to program the oscillator frequency up to 1 MHz. Timing component values must be changed because a much lower charging current is desirable for low-power operation. Several characteristics of the oscillator have been optimized for high-speed, noise-immune operation. The oscillator peak-to-peak amplitude has been increased to 2.45 V typical versus 1.7 V on the UC3842 family. The lower oscillator threshold has been dropped to approximately 0.2 V while the upper threshold remains fairly close to the original 2.8 V at approximately 2.65 V. Discharge current of the timing capacitor has been increased to nearly 20-mA peak as opposed to roughly 8 mA. This can be represented by approximately 130 Ω in series with the discharge switch to ground. A higher current was necessary to achieve brief dead times and high duty cycles with high-frequency operation. Practical applications can use these new ICs to a 1-MHz switching frequency. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 17

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 2.65 V V CT 0.2 V 0 V f CONV Figure 9-7. Oscillator Waveform 1000 800 600 400 z) 200 H C = 100 p k T ( ƒ 100 80 C = 180 p T 60 C = 270 p T C = 390 p 40 T C = 470 p T 20 0 20 40 60 80 100 120 R (kW) T Figure 9-8. Oscillator Frequency vs R For Several C T T 9.3.6 Synchronization Synchronization of these PWM controllers is best obtained by the universal technique shown in Figure 9-9. The ICs oscillator is programmed to free run at a frequency about 20% lower than that of the synchronizing frequency. A brief positive pulse is applied across the 50-Ω resistor to force synchronization. Typically, a 1-V amplitude pulse of 100-ns width is sufficient for most applications. The ICs can also be synchronized to a pulse train input directly to the oscillator RC pin. Note that the IC internally pulls low at this node once the upper oscillator threshold is crossed. This 130-Ω impedance to ground remains active until the pin is lowered to approximately 0.2 V. External synchronization circuits must accommodate these conditions. 18 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 REF R T RC C T SYNC §(cid:3)50 (cid:13)(cid:3) Figure 9-9. Synchronizing the Oscillator 9.3.7 PWM Generator Maximum duty cycle is higher for these devices than for their UC384x predecessor. This is primarily due to the higher ratio of timing capacitor discharge to charge current, which can exceed one hundred to one in a typical BiCMOS application. Attempts to program the oscillator maximum duty cycle much below the specified range by adjusting the timing component values of R and C must be avoided. There are two reasons to stay away from T T this design practice. First, the ICs high discharge current would necessitate higher charging currents than necessary for programming, defeating the purpose of low power operation. Secondly, a low-value timing resistor prevents the capacitor from discharging to the lower threshold and initiating the next switching cycle. 9.3.8 Minimum Off-Time Setting (Dead-Time Control) Dead time is the term used to describe the ensured OFF time of the PWM output during each oscillator cycle. It is used to ensure that even at maximum duty cycle, there is enough time to reset the magnetic circuit elements, and prevent saturation. The dead time of the UCC280x PWM family is determined by the internal 130-Ω discharge impedance and the timing capacitor value. Larger capacitance values extend the dead time whereas smaller values results in higher maximum duty cycles for the same operating frequency. A curve for dead time versus timing capacitor values is provided in Figure 9-10. Increasing the dead time is possible by adding a resistor between the RC pin of the IC and the timing components, as shown in Figure 9-11. The dead time increases with the discharge resistor value to about 470 Ω as indicated from the curve in Figure 9-12. Higher resistances must be avoided as they can decrease the dead time and reduce the oscillator peak-to-peak amplitude. Sinking too much current (1 mA) by reducing R will freeze the oscillator OFF by preventing T discharge to the lower comparator threshold voltage of 0.2 V. Adding this discharge control resistor has several impacts on the oscillator programming. First, it introduces a DC offset to the capacitor during the discharge – but not the charging portion of the timing cycle, thus lowering the usable peak-to-peak timing capacitor amplitude. Because of the reduced peak-to-peak amplitude, the exact value of C may require adjustment from UC3842 T type designs to obtain the correct initial oscillator frequency. One alternative is keep the same value timing capacitor and adjust both the timing and discharge resistor values because these are readily available in finer numerical increments. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 19

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 200 180 REF 160 RT 140 s) RD (n 120 RC Td <470 (cid:159) 100 CT 80 60 Copyright © 2016, Texas Instruments Incorporated 40 0 125 250 375 500 Figure 9-11. Circuit to Produce Controlled C (pF) Maximum Duty Cycle T Figure 9-10. Minimum Dead Time vs C T 100 99 98 97 %) 96 e ( ycl 95 C y Dut 94 x a M 93 92 91 90 89 0 250 500 750 1000 RD, Ohms Figure 9-12. Maximum Duty Cycle vs R for R = 20 kΩ D T 9.3.9 Leading Edge Blanking A 100-ns leading edge blanking interval is applied to the current sense input circuitry of the UCC280x devices. This internal feature has been incorporated to eliminate the requirement for an external resistor-capacitor filter network to suppress the switching spike associated with turnon of the power MOSFET. This 100-ns period must be adequate for most switch-mode designs but can be lengthened by adding an external R/C filter. Note that the 100-ns leading edge blanking is also applied to the cycle-by-cycle current limiting function in addition to the overcurrent fault comparator. 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 Figure 9-13. Current Sense Filter Required With Older PWM ICs Figure 9-14. Current Sense Waveforms With Leading Edge Blanking 9.3.10 Minimum Pulse Width The leading edge blanking circuitry can lead to a minimum pulse width equal to the blanking interval under certain conditions. This occurs when the error amplifier output voltage (minus a diode drop and divided by 1.65) is lower than the current sense input. However, the amplifier output voltage must also be higher than a diode forward voltage drop of about 0.5 V. It is only during these conditions that a minimum output pulse width equal to the blanking duration can be obtained. Note that the PWM comparator has two inputs; one is from the current sense input. The other PWM input is the error amplifier output that has a diode and two resistors in series to ground. The diode in this network is used to ensure that zero duty cycle can be reached. Whenever the E/A output falls below a diode forward voltage drop, no current flows in the resistor divider and the PWM input goes to zero, along with pulse width. + – Figure 9-15. Zero Duty Cycle Offset 9.3.11 Current Limiting A 1-V (typical) cycle-by-cycle current limit threshold is incorporated into the UCC280x family. Note that the 100- ns leading edge blanking pulse is applied to this current limiting circuitry. The blanking overrides the current limit comparator output to prevent the leading edge switch noise from triggering a current limit function. Propagation delay from the current limit comparator to the output is typically 70 ns. This high-speed path minimizes power semiconductor dissipation during an overload by abbreviating the ON time. For increased efficiency in the current sense circuitry, the circuit shown in Figure 9-16 can be used. Resistors R A and R bias the actual current sense resistor voltage up, allowing a small current sense amplitude to be used. B This circuitry provides current limiting protection with lower power loss current sensing. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 21

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com REF PWM + 0.1 µF 0 RA – V CS TO RCS 0 LOAD Q1 + RB CS – + 0 RCS – Figure 9-17. CS Pin Voltage with Biasing Copyright © 2016, Texas Instruments Incorporated Figure 9-16. Biasing CS For Lower Current Sense Voltage The example shown uses a 200-mV full scale signal at the current sense resistor. Resistor R biases this up by B approximately 700 mV to mate with the 0.9-V minimum specification of the current limit comparator of the IC. The value of resistor R changes with the specific IC used, due to the different reference voltages. The resistor A values must be selected for minimal power loss. For example, a 50-µA bias sets R = 13 kΩ, R = 75 kΩ B A (UCCx800, UCC2801, UCC2802, and UCC2804), or R = 56 kΩ with the UCC2803 and UCC2805 devices. A 9.3.12 Overcurrent Protection and Full Cycle Restart A separate overcurrent comparator within the UCC280x devices handle operation into a short-circuited or severely overloaded power supply output. This overcurrent comparator has a 1.5-V threshold and is also gated by the leading edge blanking signal to prevent false triggering. Once triggered, the overcurrent comparator uses the internal soft-start capacitor to generate a delay before retry is attempted. Often referred to as hiccup, this delay time is used to significantly reduce the input and dissipated power of the main converter and switching components. Full Cycle Soft Start ensures that there is a predictable delay of greater than 3 ms between successive attempts to operate during fault. The circuit shown in Figure 9-18 and the timing diagram in Figure 9-19 show how the IC responds to a severe fault, such as a saturated inductor. When the fault is first detected, the internal soft-start capacitor instantly discharges and stays discharged until the fault clears. At the same time, the PWM output is turned off and held off. When the fault clears, the capacitor slowly charges and allows the error amp output (COMP) to rise. When COMP gets high enough to enable the output, another fault occurs, latching off the PWM output, but the soft-start capacitor still continues to rise to 4 V before being discharged and permitting start of a new cycle. This means that for a severe fault, successive retries is spaced by the time required to fully charge the soft-start capacitor. TI recommends low leakage transformer designs in high- frequency applications to activate the overcurrent protection feature. Otherwise, the switch current may not ramp up sufficiently to trigger the overcurrent comparator within the leading edge blanking duration. This condition would cause continual cyclical triggering of the cycle-by-cycle current limit comparator but not the overcurrent comparator. This would result in brief high power dissipation durations in the main converter at the switching frequency. The intent of the overcurrent comparator is to reduce the effective retry rate under these conditions to a few milliseconds, thus significantly lowering the short-circuit power dissipation of the converter. 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 CS FB COMP 3 2 1 Over-Current Leading Edge Blanking VCC 1.5 V REF/2 OK S Q R 4 V Ref S Q OK R 0.5 V Full Cycle Soft Start t= 5 ms Figure 9-18. Detailed Block Diagram for Overcurrent Protection Figure 9-19. IC Behavior at Repetitive Fault 9.3.13 Soft Start Internal soft starting of the PWM output is accomplished by gradually increasing error amplifier (E/A) output voltage. When used in current mode control, this implementation slowly raises the peak switch current each PWM cycle in comparison, forcing a controlled start-up. In voltage mode (duty cycle) control, this feature continually widens the pulse width. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 23

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 2 1 3 Leading Edge Blanking REF/2 To Output Logic t= 4ms C SS Figure 9-20. Detailed Block Diagram for Soft-Start The internal soft-start capacitor (Css) is discharged following an undervoltage lockout transition or if the reference voltage is below a minimum value for normal operation. Additionally, discharge of Css occurs whenever the overcurrent protection comparator is triggered by a fault. Soft start is performed within the UCCx800, UCC2801, UCC2802, UCC2803, UCC2804, and UCC2805 devices by clamping the E/A amplifier output to an internal soft-start capacitor (Css), which is charged by a current source. The soft-start clamp circuitry is overridden once Css charges above the voltage commanded by the error amplifier for normal PWM operation. RC 0 Soft Start 0 PWM 0 CS 0 Figure 9-21. IC Soft-Start Behavior 9.3.14 Slope Compensation Slope compensation can be added in all current mode control applications to cancel the peak to average current error. Slope compensation is necessary with applications with duty cycles exceeding 50%, but also improves performance in those below 50%. Primary current is sensed using resistor Rcs in series with the converter switch. The timing resistor can be broken up into two series resistors to bias up the NPN follower. This is required to provide ample compliance for slope compensation at the beginning of a switching cycle, especially 24 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 with continuous current converters. A NPN voltage follower drives the slope compensating programming resistor (Rsc) to provide a slope compensating current into C . F REF R T To Main RC Switch C T R SC R F CS C R F CS Figure 9-22. Adding Slope Compensation 9.4 Device Functional Modes The UCC280x family of high-speed, low-power integrated circuits has the following function modes. 9.4.1 Normal Operation During this operation mode, IC controls the power converter into the voltage mode or current mode control, regulate the output voltage or current through the converter duty cycle. The regulation can be achieve through the integrated error amplifier or external feedback circuitry. 9.4.2 UVLO Mode During the system start-up, VCC voltage starts to rise from 0. Before the VCC voltage reaches its corresponding turn on threshold, the IC is operate under UVLO mode. In this mode, REF pin voltage is not generated. When VCC is above 1 V and below the turn on threshold, the RFE pin is actively pulled low through a 5-kΩ resistor. This way, REF pin can be used as a logic signal to indicate UVLO mode. 9.4.3 Soft Start Mode Once VCC voltage rises across the UVLO level, or comes out of a fault mode, it enters the soft start mode. During soft start, the internal soft start capacitor C clamps the error amplifier output voltage, forces it rise SS slowly. This in turn controls the power converter peak current rising slowly, reducing the voltage and current stress to the system. The UCC280x family has a fixed build in soft-start time at 4 ms. 9.4.4 Fault Mode A separate overcurrent comparator within the UCC280x devices handles operation into a short-circuited or severely overloaded power supply output. This overcurrent comparator has a 1.5-V threshold and is also gated by the leading edge blanking signal to prevent false triggering. When the fault is first detected, the internal soft- start capacitor instantly discharges and stays discharged until the fault clears. At the same time, the PWM output is turned off and held off. This is often referred to as hiccup. This delay time is used to significantly reduce the input and dissipated power of the main converter and switching components. Full cycle soft start insures that there is a predictable delay of greater than 3 milliseconds between successive attempts to operate during fault. When the fault clears, the capacitor slowly charges and allows the error amp output (COMP) to rise. When COMP gets high enough to enable the output, another fault occurs, latching off the PWM output, but the soft- start capacitor still continues to rise to 4 V before being discharged and permitting start of a new cycle. This means that for a severe fault, successive retries are spaced by the time required to fully charge the soft-start capacitor. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 25

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The UCC280x controllers are peak current mode (PCM) pulse width modulators (PWM). These controllers have an onboard amplifier and can be used in isolated and non-isolated power supply design. There is an onboard totem-pole gate driver capable of delivering 1 A of peak current. This is a high-speed PWM capable of operating at switching frequencies up to 1 MHz. 10.2 Typical Application Figure 10-1 illustrates a typical circuit diagram for an AC-DC converter using the UCC2800 in a peak current mode controlled flyback application. DCL FA VIN = 85 to 265V AC 5A – ~ + DA CCL 10 nF RCL 50 k(cid:159) DC VOUT+ ~ CIN CVCC2 NP COUT 120 uF RH 300 k(cid:159) DB RD QA VOUT- 22 VO NA RG 10 RCS RZ 1 k(cid:159) RAC U1 RLED VO¶ UCC2800 1 COMP REF 8 RT CFB RFB2 10 N(cid:159)(cid:3) 2 FB VCC 7 DC 10VRJ 1 k(cid:159) 3 CS OUT 6 CVCC1 CVREF 1µF 1µF VC 4 RC GND 5 RCSF U2 RRAMP CT CCSF RP RFBU 270 pF RFB1 RZ CZ CRAMP 10 nF 4.99 k(cid:159) U3 REG 1 k(cid:159) TL431 RFBB Copyright © 2016, Texas Instruments Incorporated Figure 10-1. Typical Application Circuit 26 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 10.2.1 Design Requirements Use the parameters in Table 10-1 to review the design of a 12-V, 48-W offline flyback converter using UCC2800 PWM controller. Table 10-1. Design Specifications PARAMETER CONDITIONS MIN NOM MAX UNIT INPUT CHARACTERISTICS V Input voltage (RMS) 85 265 V IN f Line frequency 47 63 Hz LINE OUTPUT CHARACTERISTICS V Output voltage 11.75 12 12.25 V OUT V Output ripple voltage 120 mV ripple PP I Output current 4 4.33 A OUT V Output transient Output voltage measured under 0-A to 4-A load step 11.75 12.25 V tran SYSTEM CHARACTERISTICS η Max load efficiency 85% 10.2.2 Detailed Design Procedure The design starts with selecting an appropriate bulk capacitor. The primary side bulk capacitor is selected based on the power level. Based on the desired minimum bulk voltage level, the bulk capacitor value can be calculated as Equation 8. “ 1 § VBULK(min) •” 2PINu«0.25(cid:14) uarcsin¤ ‚» CBULK (cid:11)2V«‹2IN(min)S(cid:16)V2BULK¤'(m2in)u(cid:12)uVfINLI(NmEin)‚„»… (8) In Equation 8, P is the maximum output power divided by target efficiency, V is the minimum AC input IN IN(min) voltage RMS value. V is the target minimum bulk voltage, and f is the line frequency. BULK(min) LINE Based on the equation, to achieve 75-V minimum bulk voltage, assuming 85% converter efficiency and 47-Hz minimum line frequency, the bulk capacitor must be larger than 127 µF and 180 µF was chosen in the design, considering the tolerance of the capacitors. The transformer design starts with selecting a suitable switching frequency. Generally the switching frequency selection is based on the tradeoff between the converter size and efficiency, based on the simple Flyback topology. Normally, higher switching frequency results in smaller transformer size. However, the switching loss is going to be increased and hurts the efficiency. Sometimes, the switching frequency is selected to avoid certain communication band to prevent the noise interference with the communication. The frequency selection is beyond the scope of this data sheet. The switching frequency is selected as 110 kHz, to minimize the transformer size. At the same time, the regulations start to have limit on EMI noise at 150 kHz, design 110-kHz switching frequency can help to minimize the EMI filter size. Then the transformer turns ratio can be selected based on the desired MOSFET voltage rating and diode voltage rating. Because maximum input voltage is 265 V AC, the peak voltage can be calculated as Equation 9. V = 2´V »375V BULK(max) IN(max) (9) To minimize the cost of the system, the popular 650-V MOSFET is selected. Considering the design margin and extra voltage ringing on the MOSFET drain, the reflected output voltage must be less than 120 V. The transformer turns ratio can be selected as Equation 10. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 27

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 120V n = =10 ps 12V (10) The diode voltage stress is the output voltage plus the reflected input voltage. The voltage stress on the diode can be calculated as Equation 11. V 375V V = BULK(max)+V = (cid:14)(cid:20)(cid:21)9§(cid:24)(cid:19)9 DIODE n OUT 10 ps (11) Consider the ringing voltage spikes and voltage derating the diode voltage rating must be higher than 50 V. The transformer inductance selection is based on the CCM condition. Larger inductor would allow the converter stays in CCM longer. However, it tends to increase the transformer size. Normally, the transformer magnetizing inductor is selected so that the converter enters CCM operation at about 50% load at minimum line voltage. This would be a tradeoff between the transformer size and the efficiency. In this particular design, due to the higher output current, it is desired to keep the converter deeper in the CCM and minimize the conduction loss and output ripple. The converter enters CCM operation at about 10% load at minimum bulk voltage. The inductor can be calculated as Equation 12. 2 æ ö n V V2 ´ç PS OUT ÷ L = 1 BULK(min) çèVBULK(min) +nPSVOUT ÷ø m 2 10%´P ´ f IN SW (12) In this equation, the switching frequency is 110 kHz. Therefore, the transformer inductance must be about 1.7 mH. 1.5 mH is chosen as the magnetizing inductor value. The auxiliary winding provides the power for UCC2800 normal operation. The auxiliary winding voltage is the output voltage reflected to the primary side. It is desired to have higher reflected voltage so that the IC can quickly get energy from the transformer and make the heavy load startup easier. However, the high the reflect voltage makes the IC consumes more power. Therefore, tradeoff is required. In this design, the auxiliary winding voltage is selected the same as the output voltage so that it is above the UVLO level and keep the IC and driving loss low. Therefore, the auxiliary winding to the output winding turns ratio is selected as Equation 13. 12V n = =1 as 12V (13) Based on calculated inductor value and the switching frequency, the current stress of the MOSFET and diode can be calculated. The peak current of the MOSFET can be calculated as Equation 14. n V PS OUT P 1V V +n V IN BULK(min) BULK:min; PS OUT I = + × PKMOS n V 2 L f V × PS OUT m sw BULK:min; V +n V BULK:min; PS OUT (14) The MOSFET peak current is 1.425 A. The diode peak current is the reflected MOSFET peak current on the secondary side. I =n ´I =14.25A PKDIODE ps PKMOS (15) The RMS current of the MOSFET can be calculated as Equation 16. 28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 I = 1D3 ´æçVBULK(min)ö÷2 -D2IPKMOSVBULK(min) +D´I2 RMSMOS 3 çè Lm´ fsw ÷ø Lm´ fsw PKMOS (16) In Equation 16, D is the MOSFET duty cycle at minimum bulk voltage and it can be calculated as Equation 17. n V D= ps OUT V +n V BULK(min) ps OUT (17) The MOSFET RMS current is 0.75 A. Therefore, IRFB9N65A is selected as primary side MOSFET. The diode average current is the output current 4 A with 60-V rating and 14.25-A peak current capability, 48CTQ060-1 is selected. Output capacitor is selected based on the output voltage ripple requirement. In this design, 0.1% voltage ripple is assumed. Based on the 0.1% ripple requirement, the capacitor value can be selected based on Equation 18. n V ps OUT I ´ OUT V +n V BULK(min) ps OUT C ³ =2105mF OUT 0.1%´V ´ f OUT sw (18) Consider the tolerance and temperature effect, together the ripple current rating of the capacitors, the output capacitor of 3 of 680 µF in parallel was selected. After the power stage is designed, the surround components can be selected. 10.2.2.1 Current Sensing Network The current sensing network consists of R , R , C , and optional R . Typically, the direct current sense CS CSF CSF P signal contains a large amplitude leading edge spike associated with the turnon of the main power MOSFET, reverse recovery of the output rectifier, and other factors including charging and discharging of parasitic capacitances. Therefore, C and R form a low-pass filter that provides additional immunity beyond the CSF CSF internal blanking time to suppress the leading edge spike. For this converter, C is chosen to be 270 pF to CSF provide enough filtering. Without R , R sets the maximum peak current in the transformer primary based on the maximum amplitude of P CS CS pin, 1 V. To achieve 1.425-A primary side peak current, a 0.75-Ω resistor is chosen for R . CS The high current sense threshold help to provide better noise immunity but the current sense loss is increased. The current sense loss can be minimized by injecting offset voltage into the current sense signal. R and R P CS form a resistor divider network from the current sense signal to the device’s reference voltage to offset the current sense voltage. This technique still achieves current mode control with cycle-by-cycle overcurrent protection. To calculate required offset value (Voffset), use Equation 19. RCSF Voffset VREF RCSF(cid:14)RP (19) 10.2.2.2 Gate Drive Resistor R is the gate driver resistor for the power switch, Q . The selection of this resistor value must be done in G A conjunction with EMI compliance testing and efficiency testing. Larger R slows down the turnon and turnoff of G the MOSFET. Slower switching speed reduces EMI but also increases the switching loss. A tradeoff between switching loss and EMI performance must be carefully performed. For this design, 10 Ω was chosen as the gate driver resistor. 10.2.2.3 Vref Capacitor A precision 5-V reference voltage is designed to perform several important functions. The reference voltage is divided down internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate output Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 29

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com voltage regulation. Other duties of the reference voltage are to set internal bias currents and thresholds for functions such as the oscillator upper and lower thresholds along with the overcurrent limiting threshold. Therefore, the reference voltage must be bypassed with a ceramic capacitor (C ), and 1-μF, 16-V ceramic VREF capacitor was selected for this converter. Placement of this capacitor on the physical printed-circuit board layout must be as close as possible to the respective REF and GND pins as possible 10.2.2.4 R C T T The internal oscillator uses a timing capacitor (C ) and a timing resistor (R ) to program operating frequency and T T maximum duty cycle. The operating frequency can be programmed based the curves in Figure 8-3, where the timing resistor can be found once the timing capacitor is selected. The selection of timing capacitor also affects the maximum duty cycle provided in Figure 8-5. It is best for the timing capacitor to have a flat temperature coefficient, typical of most COG or NPO type capacitors. For this converter, 13.6 kΩ and 1000 pF were selected for R and C to operate at 110-kHz switching. T T 10.2.2.5 Start-Up Circuit At startup, the IC gets its power directly from the high voltage bulk, through a high voltage resistor R . The H selection of start-up resistor is the tradeoff between power loss and start-up time. The current flowing through R H at minimum input voltage must be higher than the VCC current under UVLO condition (0.2 mA at its maximum value). A 150-kΩ resistor is chosen as the result of the tradeoff. After VCC is charged up above UVLO on threshold, UCC2800 starts to operate and consumes full operating current. At the beginning, because the output voltage is low, VCC cannot get energy from the auxiliary winding. VCC capacitor requires to hold enough energy to prevent its voltage drop below UVLO during start-up time, before output reaches high enough. A larger capacitor holds more energy but slows down the start-up time. In this design, a 120-µF capacitor is chosen to provide enough energy for the start-up purpose. 10.2.2.6 Voltage Feedback Compensation Feedback compensation, also called closed-loop control, reduces or eliminates steady state error, reduces the sensitivity to parametric changes, changes the gain or phase of a system over some desired frequency range, reduces the effects of small signal load disturbances and noise on system performance, and creates a stable system. The following section describes how to compensate an isolated Flyback converter with the peak current mode control. 10.2.2.6.1 Power Stage Gain, Zeroes, and Poles The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance, L , is greater than the P inductance for DCM, CCM boundary mode operation, called the critical inductance, or L , then the converter Pcrit operates in CCM calculated with Equation 20. R ´N2 æ V ö2 LPcrit = O2U´Tf PS ´çV +V IN ´N ÷ SW è IN OUT PS ø (20) For the entire input voltage range, the selected inductor has value larger than the critical inductor. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations. The current-to-voltage conversion is done externally with the ground-referenced current sense resistor, R , and CS the internal resistor divider sets up the internal current sense gain, A = 1.65. The IC technology allows the CS tight control of the resistor divider ratio, regardless of the actual resistor value variations. The DC open-loop gain, G , of the fixed-frequency voltage control loop of a peak current mode control CCM O flyback converter shown in Figure 10-1 is approximated by first using the output load, R , the primary to OUT secondary turns ratio, N , the maximum duty cycle, D, calculated in Equation 21. PS 30 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 R ´N 1 G = OUT PS ´ O RCS´ACS (1-D)2 +(2´M)+1 t L (21) In Equation 21, D is calculated with Equation 22, τ is calculated with Equation 23, and M is calculated with L Equation 24. N ´V D= PS OUT V +(N ´V ) IN PS OUT (22) 2´L ´f t = P SW L R ´N2 OUT PS (23) V ´N M= OUT PS V IN (24) For this design, a converter with an output voltage V of 12 V, and 48 W relates to an output load, R , equal OUT OUT to 3 Ω at full load. At minimum input voltage of 75 V DC, the duty cycle reaches it maximum value of 0.615. The current sense resistance, R , is 0.75 Ω, and a primary to secondary turns-ratio, N is 10. The open-loop gain calculates to CS PS 14.95 dB. A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero, f , are calculated with Equation 25. ESRz 1 w = ESRz R ´C ESR OUT (25) The f zero for a capacitance bank of three 680-µF capacitors for a total output capacitance of 2040 µF and a ESRz total ESR of 13 mΩ is placed at 6 kHz. CCM flyback converters have a zero in the right-half plane, RHP, in their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location, f RHPz in Equation 26, is a function of the output load, the duty cycle, the primary inductance, L , and the primary to P secondary side turns ratio, N . PS R ´(1-D)2 ´N2 f = OUT PS RHPz 2´p´L ´D P (26) Right half plane zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest right half plane zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency, f , is equal to 7.65 kHz at maximum duty cycle, full load. RHPz The power stage has one dominate pole, ω , which is in the region of interest, placed at a lower frequency, f , P1 P1 which is related to the duty cycle, D, the output load, and the output capacitance. There is also a double pole placed at half the switching frequency of the converter, f calculated with Equation 27 and Equation 28. P2 (1-D)3 +1+D t f = L P1 2´p´R ´C OUT OUT (27) Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 31

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com f f = SW P2 2 (28) Slope compensation is the large signal sub-harmonic instability that can occur with duty cycles that extends beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter. The target of slope compensation is to achieve idea quality coefficient, Q , at half of the switching frequency to p be 1. The Q is calculated with Equation 29. p 1 Q = P p´éëMC´(1-D)-0.5ùû (29) In Equation 29, D is the primary side switch duty cycle and M is the slope compensation factor, which is defined C with Equation 30. S M =1+ e C S n (30) In Equation 30, Se is the compensation ramp slope and the S is the inductor rise slope. The optimal goal of the n slope compensation is to achieve Q equal to 1, which mean M must be 2.128 when D reaches it maximum P C value of 0.615. The inductor rise slop on CS pin is calculated with Equation 31. V ×R 75V×0.75(cid:13) S = BULK(min) CS= =38mV/(cid:29)s n L 1.5mH P (31) The compensation slope is calculated with Equation 32. S =(M -1)´S =(2.128-1)´38mV/ms=46.3mV/ms e C n (32) The compensation slope is added into the system through R and R . The C is selected to RAMP CSF RAMP approximate high frequency short circuit. Choose C as 10 nF as the starting point, and make adjustments if RAMP required. The R and R forms a voltage divider from the RC pin ramp voltage and inject the slope RAMP CSF compensation into CS pin. Choose R much larger than the R resistor so that it won’t affect much the RAMP T frequency setting. In this design, R is selected as 24.9 kΩ. The RC pin ramp slope is calculated with RAMP Equation 33. S =2.4V´100kHz=240mV/ms RC (33) To achieve 46.3 mV/µs compensation slope, R resistor is calculated with Equation 34. CSF R = RRAMP = 24.9kW =5.95kW CSF S 240mV/ms RC -1 -1 R 46.3mV/ms e (34) The power stage open-loop gain and phase can be plotted as a function of frequency. The total gain, as a function of frequency can be characterized with Equation 35. 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 æ S ö æ S ö ç1+ ÷´ç1- ÷ H (S)=G ´è wESRz ø è wRHPz ø´ 1 0 0 1+ s(f) 1+ S + S2 wP1 wP2´QP wP22 (35) The bode is plotted accordingly (see Figure 10-2 and Figure 10-3). 20 0 -30 10 -60 Loop Gain (dB) -100 Phase (Degree) -1-9200 -150 -20 -180 1 10 100 1k 10k 100k -30 Frequency (Hz) 1 10 100 1k 10k 100k Figure 10-3. Converter Open Loop Bode Plot - Frequency (Hz) Figure 10-2. Converter Open Loop Bode Plot - Gain Phase 10.2.2.6.2 Compensation Loop For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth of a CCM flyback, f , is limited to ¼ of the RHP zero frequency, or approximately 1.9 kHz using Equation 36. BW f f = RHPz BW 4 (36) The gain of the open-loop power stage at f is equal to –22.4 dB and the phase at f is equal to –87°. First BW BW step is to choose the output voltage sensing resistor values. The output sensing resistors are selected based on the allowed power consumption and in this case, 1 mA of sensing current is assumed. The TL431 is used as the feedback amplifier. Given its 2.5-V reference voltage, the voltage sensing dividers R and R can be selected with Equation 37 and Equation 38. FBU FBB V -2.5V R = OUT =9.5kW FBU 1mA (37) 2.5V R = =2.5kW FBB 1mA (38) Next step is to put the compensator zero f at 190 Hz, which is 1/10 of the crossover frequency. Choose C as CZ Z a fixed value of 10 nF and choose the zero resistor value according to Equation 39. 1 1 R = = =83.77kW Z 2p´f ´C 2p´190Hz´10nF CZ Z (39) Then put a pole at the lower frequency of right half plane zero or the ESR zero. Based previous analysis, the right half plane zero is at 7.65 kHz and the ESR zero is at 6 kHz, the pole of the compensation loop must be put Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 33

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com at 6 kHz. This pole can be added through the primary side error amplifier. R and C provide the necessary FB FB pole. Choosing R as 10 kΩ and the C is selected with Equation 40. FB FB 1 C = =2.65nF FB 2p´10kW´6kHz (40) Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 41. 1 1+S×C ×R R 1 G(S)= × Z Z × FB2 × ×CTR×R R ×R S×C R S×C ×R +1 EG FBT LED Z FB1 FB FB2 (41) In this equation, the CTR is the current transfer ratio of the opto-coupler. Choose 1 as the nominal value for CTR. R is the opto-pulldown resistor and 1 kΩ is chosen as a default value. The only value required in this EG equation is R . The entire loop gain must be equal to 1 at the crossover frequency. R is calculated LED LED accordingly as 1.62 kΩ. The final close loop bode plots are show in Figure 10-4 and Figure 10-5. The converter achieves approximately 2-kHz crossover frequency and approximately 70o of phase margin. TI recommends checking the loop stability across all the corner cases including component tolerances to ensure system stability. 100 -100 80 -120 60 Phase (Degree)-140 40 L o -160 o p G a in (d 20 B -180 ) 1 10 100 1k 10k 100k Frequency (Hz) Figure 10-5. Converter Close Loop Bode Plot – 0 Phase -20 -40 1 10 100 1k 10k 100k Frequency (Hz) Figure 10-4. Converter Close Loop Bode Plot – Gain 34 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 10.2.3 Application Curves Figure 10-6. Primary Side MOSFET Drain to Source Figure 10-7. Primary Side MOSFET Drain to Source Voltage at 240-V AC Input (100 V/div) Voltage at 120-V AC Input (100 V/div) Figure 10-8. Output Voltage During 0.9-A to 2.7-A Figure 10-9. Output Voltage Ripple at Full Load Load Transient (CH1: Output Voltage AC Coupled, (100 mV/div) 200 mV/div; CH4: Output Current, 1 A/div) Figure 10-10. Output Voltage Behavior at Full Load Start-up (5 V/div) Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 35

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 11 Power Supply Recommendations An internal VCC shunt regulator is incorporated in each member of the UCC280xPWMs to regulate the supply voltage at approximately 13.5 V. A series resistor from VCC to the input supply source is required with inputs above 12 V to limit the shunt regulator current. A maximum of 10 mA can be shunted to ground by the internal regulator. The internal regulator in conjunction with the device’s low start-up and operating current can greatly simplify powering the device and may eliminate the requirement for a regulated bootstrap auxiliary supply and winding in many applications. The supply voltage is MOSFET gate level compatible and requires no external Zener diode or regulator protection with a current-limited input supply. The UVLO start-up threshold is 1 V below the shunt regulator level on the UCC2802 and UCC2804 devices to ensure start-up. It is important to bypass the ICs supply (VCC) and reference voltage (REF) pins with a 0.1-µF to 1-µF ceramic capacitor to ground. The capacitors must be placed as close to the actual pin connections as possible for optimal noise filtering. A second, larger filter capacitor may also be required in offline applications to hold the supply voltage (VCC) above the UVLO turnoff threshold during start-up. The UVLO start threshold of the UCC280-[2,4] devices has a range of 11.5 V to 13.5 V, while the protection zener voltage can vary from 12 V to 15 V. However, the absolute maximum supply voltage of the IC is specified at 12 V. This absolute maximum is defined as the lowest possible Zener voltage when driven from a low impedance (voltage) source. The zener voltage is always higher than the UVLO start voltage. These two parameters track each other and the chip is tested to guarantee that the Zener voltage will never be below that of the start voltage. To limit the current flowing in the internal clamp zener, a series resistor must be added. Failure to provide a series resistance between the auxiliary voltage source and the Vcc pin of the controller, to limit the current and voltage stress within rated levels on the Vcc pin may result in permanent damage to the controller. In automotive or industrial applications where there is a risk of high power load transients which may cause transients or voltage excursions on the Vcc rail supplying the PWM controller it is recommended to add an external Zener diode across the Vcc pin. The external Zener acts as an additional protection to the impedance provided by the series resistor between the Vcc source and Vcc pin. Placing a resistor, Rg, in series with the gate of the mosfet allows the mosfet switching speed to be adjusted and also can be used to keep the peak gate drive currents within the specified limits of the controller. HV DC BUS Rstart Bootstrap Rvcc To Output VCC REF Caux UCC280x OUT Rg 1uF External 13V Zener (Recommended 0.1uF when there is a risk of Rcs transients on bias supply) Figure 11-1. Different Ways of Powering Up the Device 36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 12 Layout 12.1 Layout Guidelines In addition to following general power management IC layout guidelines (star grounding, minimal current loops, reasonable impedance levels, and so on) layout for the UCC280x family must consider the following: • If possible, a ground plane must be used to minimize the voltage drop on the ground circuit and the noise introduced by parasitic inductances in individual traces. • A decoupling capacitor is required for both the VCC pin and REF pin and both must be returned to GND as close to the IC as possible. • For the best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions. • The CS pin filter capacitor must be as close to the IC possible and grounded right at the IC ground pin. This ensures the best filtering effect and minimizes the chance of current sense pin malfunction. • Gate driver loop area must be minimized to reduce the EMI noise because of the high di/dt current in the loop. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 37

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 12.2 Layout Example MOSFET Heatsink Track To TO-220FP Bottom View <= (cid:17)(cid:181)ol(cid:3)(cid:18)(cid:2)(cid:137)(cid:3)5 RCS1 S G 6 ½ RCS2 P Track To R Transformer => I W FBG in D d RSNUB1 in g RSNUB2 ½ P R Track To CSNUB I Win <= Bulk Cap + d in g 4 22AWG Jumper T Wire R RCSF A N CCSF S F O CT R M > GND RC CRAMP E = R = RG OUT CS RRAMP n UCC2800 o CVCC3 VCC FB 2 CVCC2 i t c REF COMP A e U ir CREF RFB2 Aux Cap X W D in er RT CFB din g ld RCSO RFB1 CVCC1 1 o S REG e v 22AWG Jumper Wires a E K W OPTO-ISOLATOR C A PCB Bottom-side View Copyright © 2016, Texas Instruments Incorporated Figure 12-1. UCC2800 Layout Example 38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 www.ti.com SLUS270G – MARCH 1999 – REVISED MAY 2020 13 Device and Documentation Support 13.1 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 13.2 Trademarks TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.4 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13.5 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 13-1. Related Links TECHNICAL TOOLS & SUPPORT & PARTS PRODUCT FOLDER ORDER NOW DOCUMENTS SOFTWARE COMMUNITY UCC2800 Click here Click here Click here Click here Click here UCC2801 Click here Click here Click here Click here Click here UCC2802 Click here Click here Click here Click here Click here UCC2803 Click here Click here Click here Click here Click here UCC2804 Click here Click here Click here Click here Click here UCC2805 Click here Click here Click here Click here Click here UCC2800 Click here Click here Click here Click here Click here UCC2801 Click here Click here Click here Click here Click here UCC2802 Click here Click here Click here Click here Click here UCC2803 Click here Click here Click here Click here Click here UCC2804 Click here Click here Click here Click here Click here UCC2805 Click here Click here Click here Click here Click here UCC2800 Click here Click here Click here Click here Click here UCC2801 Click here Click here Click here Click here Click here UCC2802 Click here Click here Click here Click here Click here UCC2803 Click here Click here Click here Click here Click here UCC2804 Click here Click here Click here Click here Click here UCC2805 Click here Click here Click here Click here Click here Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 39

UCC2800, UCC2801, UCC2802, UCC2803, UCC2804, UCC2805 SLUS270G – MARCH 1999 – REVISED MAY 2020 www.ti.com 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 40 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-9451301MPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451301MPA UCC1801 5962-9451302MPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451302MPA UCC1802 5962-9451303MPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451303MPA UCC1803 5962-9451304MPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451304MPA UCC1804 5962-9451305MPA ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451305MPA UCC1805 UCC1800J ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 UCC1800J UCC1800J883B ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 UCC1800J/ 883B UCC1800L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UCC1800L/ 883B UCC1801J ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 UCC1801J UCC1801J883B ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451301MPA UCC1801 UCC1802J ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 UCC1802J UCC1802J883B ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451302MPA UCC1802 UCC1803J ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 UCC1803J UCC1803J883B ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451303MPA UCC1803 UCC1804J ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 UCC1804J UCC1804J883B ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451304MPA UCC1804 UCC1805J ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 UCC1805J UCC1805J883B ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -55 to 125 9451305MPA Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UCC1805 UCC2800D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2800 & no Sb/Br) UCC2800DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2800 & no Sb/Br) UCC2800DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2800 & no Sb/Br) UCC2800DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2800 & no Sb/Br) UCC2800N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2800N & no Sb/Br) UCC2800PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2800 & no Sb/Br) UCC2801D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2801 & no Sb/Br) UCC2801DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2801 & no Sb/Br) UCC2801DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2801 & no Sb/Br) UCC2801DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2801 & no Sb/Br) UCC2801N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2801N & no Sb/Br) UCC2801PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2801 & no Sb/Br) UCC2802D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2802 & no Sb/Br) UCC2802DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2802 & no Sb/Br) UCC2802DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2802 & no Sb/Br) UCC2802J ACTIVE CDIP JG 8 1 TBD SNPB N / A for Pkg Type -40 to 85 UCC2802J UCC2802N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2802N & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UCC2802NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2802N & no Sb/Br) UCC2802PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2802 & no Sb/Br) UCC2803D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2803 & no Sb/Br) UCC2803DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2803 & no Sb/Br) UCC2803DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2803 & no Sb/Br) UCC2803DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2803 & no Sb/Br) UCC2803N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2803N & no Sb/Br) UCC2803PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2803 & no Sb/Br) UCC2803PWTR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2803 & no Sb/Br) UCC2804D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2804 & no Sb/Br) UCC2804DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2804 & no Sb/Br) UCC2804DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2804 & no Sb/Br) UCC2804N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2804N & no Sb/Br) UCC2804PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2804 & no Sb/Br) UCC2804PWTR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2804 & no Sb/Br) UCC2805D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2805 & no Sb/Br) UCC2805DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2805 & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UCC2805DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2805 & no Sb/Br) UCC2805N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2805N & no Sb/Br) UCC2805PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2805 & no Sb/Br) UCC2805PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2805 & no Sb/Br) UCC2805PWR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2805 & no Sb/Br) UCC3800D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3800 & no Sb/Br) UCC3800DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3800 & no Sb/Br) UCC3800DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3800 & no Sb/Br) UCC3800N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3800N & no Sb/Br) UCC3800NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3800N & no Sb/Br) UCC3800PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3800 & no Sb/Br) UCC3801D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3801 & no Sb/Br) UCC3801DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3801 & no Sb/Br) UCC3801DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3801 & no Sb/Br) UCC3801N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3801N & no Sb/Br) UCC3801NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3801N & no Sb/Br) UCC3801PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3801 & no Sb/Br) Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UCC3801PWTR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3801 & no Sb/Br) UCC3802D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3802 & no Sb/Br) UCC3802DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3802 & no Sb/Br) UCC3802DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3802 & no Sb/Br) UCC3802DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3802 & no Sb/Br) UCC3802N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3802N & no Sb/Br) UCC3802PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3802 & no Sb/Br) UCC3803D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3803 & no Sb/Br) UCC3803DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3803 & no Sb/Br) UCC3803DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3803 & no Sb/Br) UCC3803N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3803N & no Sb/Br) UCC3803PWTR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3803 & no Sb/Br) UCC3803PWTRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3803 & no Sb/Br) UCC3804D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3804 & no Sb/Br) UCC3804DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3804 & no Sb/Br) UCC3804DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3804 & no Sb/Br) UCC3804DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3804 & no Sb/Br) Addendum-Page 5

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UCC3804N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3804N & no Sb/Br) UCC3804NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3804N & no Sb/Br) UCC3804PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3804 & no Sb/Br) UCC3804PWTR ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3804 & no Sb/Br) UCC3805D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3805 & no Sb/Br) UCC3805DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3805 & no Sb/Br) UCC3805DTR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3805 & no Sb/Br) UCC3805DTRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3805 & no Sb/Br) UCC3805N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3805N & no Sb/Br) UCC3805NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3805N & no Sb/Br) UCC3805PW ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3805 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 6

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC1800, UCC1801, UCC1802, UCC1803, UCC1804, UCC1805, UCC2800, UCC2801, UCC2802, UCC2802M, UCC2803, UCC2804, UCC2805, UCC3800, UCC3801, UCC3802, UCC3803, UCC3804, UCC3805 : •Catalog: UCC3800, UCC3801, UCC3802, UCC3803, UCC3804, UCC3805, UCC2802 •Automotive: UCC2800-Q1, UCC2801-Q1, UCC2802-Q1, UCC2802-Q1, UCC2803-Q1, UCC2804-Q1, UCC2805-Q1 •Enhanced Product: UCC2800-EP, UCC2801-EP, UCC2802-EP, UCC2802-EP, UCC2803-EP, UCC2804-EP, UCC2805-EP •Military: UCC2802M, UCC1800, UCC1801, UCC1802, UCC1803, UCC1804, UCC1805 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 7

PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC2800DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2801DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2802DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2803DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2803PWTR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC2804DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2804PWTR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC2805DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2805PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC3800DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3801DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3801PWTR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC3802DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3803DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3803PWTR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC3804DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3804PWTR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC3805DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC2800DTR SOIC D 8 2500 340.5 338.1 20.6 UCC2801DTR SOIC D 8 2500 340.5 338.1 20.6 UCC2802DTR SOIC D 8 2500 340.5 338.1 20.6 UCC2803DTR SOIC D 8 2500 340.5 338.1 20.6 UCC2803PWTR TSSOP PW 8 2000 367.0 367.0 35.0 UCC2804DTR SOIC D 8 2500 340.5 338.1 20.6 UCC2804PWTR TSSOP PW 8 2000 367.0 367.0 35.0 UCC2805DTR SOIC D 8 2500 340.5 338.1 20.6 UCC2805PWR TSSOP PW 8 2000 367.0 367.0 35.0 UCC3800DTR SOIC D 8 2500 340.5 338.1 20.6 UCC3801DTR SOIC D 8 2500 340.5 338.1 20.6 UCC3801PWTR TSSOP PW 8 2000 367.0 367.0 35.0 UCC3802DTR SOIC D 8 2500 340.5 338.1 20.6 UCC3803DTR SOIC D 8 2500 340.5 338.1 20.6 UCC3803PWTR TSSOP PW 8 2000 367.0 367.0 35.0 UCC3804DTR SOIC D 8 2500 340.5 338.1 20.6 UCC3804PWTR TSSOP PW 8 2000 367.0 367.0 35.0 UCC3805DTR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated