UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 (cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:8)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15) (cid:16)(cid:17)(cid:18)(cid:2)(cid:19)(cid:20)(cid:8)(cid:18)(cid:8)(cid:1)(cid:16) (cid:21)(cid:1)(cid:2)(cid:22) (cid:2)(cid:8)(cid:18)(cid:12)(cid:20)(cid:8)(cid:7)(cid:7)(cid:15)(cid:20) FEATURES DESCRIPTION (cid:1) VOUT Resistor Programmable Down to 0.9 V The UCC3585 synchronous buck controller (cid:1) 3.3-V or 5.0-V Input Supply provides flexible high efficiency power conversion (cid:1) 1% DC Accuracy for output voltages as low as 0.9 V with ensured (cid:1) ±1% dc accuracy. With an input voltage range of High Efficiency Synchronous Switching 3.0 V to 5.5 V, it is the ideal choice for 3.3 V only, (cid:1) Drives P-Channel (High Side) and N-Channel 5.0 V only, or other low voltage systems. The fixed (Low Side) MOSFETs frequency oscillator is capable of providing (cid:1) Lossless Programmable Current Limit practical PWM operation to 500 kHz. (cid:1) Logic Compatible Shutdown The UCC3585 drives a complementary pair of power MOSFET transistors. A P-channel on the APPLICATIONS high side, and an N-channel on the low side step (cid:1) Local Microprocessor Core Voltage Power down the input voltage at up to 90% efficiency. Supplies for Desktop and Notebook A programmable two-level current limiting Computers function is provided by sensing the voltage drop (cid:1) DSP Core or I/O Powering across the high side P-channel MOSFET. This (cid:1) High-Speed GTL Bus Regulation circuit can be configured to provide pulse- by-pulse limiting, timed shutdown after seven consecutive faults, or latch-off after fault detec- tion, allowing maximum application flexibility. The current limit threshold can be programmed over a wide range with a single resistor. VIN C7 0.47 µ F 14R k4Ω VIN = 3.3 V + R1 UCC3585 VOUT = 1.8 V C1 10 kΩ IOUT = 3 A (max) 150 µ F 15 VIN CLSET 8 Q1 SI4562DY ENABLE L1 1 ENB PDRV 12 3.7 µ H C2 5600 pF R2 10 kΩ VOUT 2 COMP ISENSE 11 C3 47 pF 4 VFB NDRV 14 + + R5 10 SD N/C 6 2 kΩ C4 0.47 µ F C8 C9 3 SS N/C 9 150 µ F 10 µ F C5 0.1 µ F 16 CT PWRGND 13 C6 470 pF R6 7 ISET GND 5 2 kΩ RTN R3 100 kΩ RTN UDG−01127 (cid:23)(cid:20)(cid:8)(cid:24)(cid:1)(cid:2)(cid:12)(cid:25)(cid:8)(cid:18) (cid:24)(cid:13)(cid:12)(cid:13) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2001, Texas Instruments Incorporated (cid:23)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:12)&-!# (cid:25)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:23)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ www.ti.com 1

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 description (continued) The UCC3585 also includes undervoltage lockout, a logic controlled enable, and softstart functions. The UCC3585 is offered in the 16-pin surface mount and through-hole packages. absolute maximum ratings over operating free-air temperature (unless otherwise noted)†(cid:1) Analog pins Minimum and maximum forced voltage (reference to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.3 V Digital pins Minimum and maximum forced voltage (reference to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.3 V Power driver output pins Maximum forced current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.0 A Operating junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C J Storage temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (cid:2)Unless otherwise noted, voltages are reference to ground and currents are positive into, negative out of, the specified terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500 ns. N, D and M PACKAGES (TOP VIEW) ENB 1 16 CT COMP 2 15 VIN SS 3 14 NDRV VFB 4 13 PWRGND GND 5 12 PDRV N/C 6 11 ISENSE ISET 7 10 SD CLSET 8 9 N/C AVAILABLE OPTIONS PACKAGED DEVICES TTAA DIL (N) SOIC (D) QSOP (M) −40°C to 85°C UCC2585N UCC2585D UCC2585M 0°C to 85°C UCC3585N UCC3585D UCC3585M The M and D packages are available taped and reeled. Add an R suffix to the device type (e.g., UCC3585DR). DISSIPATION RATING TABLE PACKAGE POWTAE R≤ 2R5A°TCING DAERBAOTVIEN GTA F A= C2T5°OCR POWTAE R= 7R0A°TCING POWTAE R= 8R5A°TCING N 1.1 W 11 mW/°C 610 mW 440 mW D 830 mW 8.3 mW/°C 450 mW 330 mW M 580 mW 5.8 mW/°C 320 mW 230 mW 2 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 electrical characteristics, these specifications hold for T = 0(cid:1)C to 85(cid:1)C for the UCC3585 and A T = −40(cid:1)C to 85(cid:1)C for the UCC2585, T = T V = 3.3 V, V , V = V , V = 0.9 V, A A J, IN ENB ISENSE IN FB V = 1.5 V, C = 330 pF, R = 100 kΩ, R = 10 kΩ(cid:1) (unless otherwise noted) COMP T ISET CLSET input supply PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Supply current − total (active) 2.3 3.5 mA Supply current – shutdown ENB = 0 V 10 25 µA VIN turnon threshold (UVLO) 1.60 1.95 2.20 V VIN turnon hysteresis 110 200 mV voltage amplifier PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIN = 3.0 V to 3.6 V, TA = 25°C, See Note 1 0.891 0.9 0.909 VIN = 3.0 V to 3.6 V, TA = 0°C to 85°C, 0.889 0.9 0.911 IInnppuutt vvoollttaaggee ((iinntteerrnnaall rreeffeerreennccee)) See Note 1 VV VIN = 3.0 V to 3.6 V, TA = −40°C to 85°C, 0.886 0.9 0.914 See Note 1 Open loop gain COMP = 0.5 V to 2.5 V 60 80 dB Output voltage high ICOMP = –50 µA 2.80 2.95 VV Output voltage low ICOMP = 50 µA 0.10 0.25 Output source current –175 –300 µA Output sink current 2.0 3.0 mA NOTE: 1. Measured on COMP with the error amplifier in a unity gain (voltage follower) configuration. oscillator/PWM PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VIN = 3.3 V 345 420 475 kHz IInniittiiaall aaccccuurraaccyy VIN = 5.0 V 345 425 485 kHz TA = 0°C to 85°C 1.8 2.1 2.3 CCTT rraammpp ppeeaakk--ttoo--vvaalllleeyy TA = −40°C to 85°C 1.7 2.1 2.3 CT ramp peak 2.5 2.8 VV TA = 0°C to 85°C 0.3 0.4 CCTT rraammpp vvaalllleeyy vvoollttaaggee TA = −40°C to 85°C 0.27 0.40 PWM maximum duty cycle COMP = 2.8 V, Measured on PDRV 100 % PWM delay to outputs COMP = 2.5 V 85 140 ns Enable high threshold Measured on ENB, See Note 3 2.8 VV Enable low threshold Measured on ENB 0.5 SS = 0 V, TA = 0°C to 85°C 9.0 13.5 16.0 SSooffttssttaarrtt cchhaarrggee ccuurrrreenntt µAA SS = 0 V, TA = −40°C to 85°C 9.0 13.5 19.0 NOTE: 3. Enable high threshold = (VIN − 0.5). www.ti.com 3

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 electrical characteristics, these specifications hold for T = 0(cid:1)C to 85(cid:1)C for the UCC3585 and A T = −40(cid:1)C to 85(cid:1)C for the UCC2585, T = T V = 3.3 V, V , V = V , V = 0.9 V, A A J, IN ENB ISENSE IN FB V = 1.5 V, C = 330 pF, R = 100 kΩ, R = 10 kΩ(cid:1) (unless otherwise noted) COMP T ISET CLSET current limit PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Comparator offset voltage −25 0 25 mV VIN = 3.3 V, TA = 0°C to 85°C 10.0 11.5 14.0 VIN = 5 V, TA = 0°C to 85°C 11.0 12.5 15.0 CCLLSSEETT ccuurrrreenntt VIN = 3.3 V, TA = −40°C to 85°C 9.0 11.5 14.0 µAA VIN = 5 V, TA = −40°C to 85°C 9.5 12.5 15.0 SD = 2 V, TA = 0°C to 85°C 8.5 11.0 13.5 SSDD ssiinnkk ccuurrrreenntt SD = 2 V, TA = −40°C to 85°C 7.5 11.0 13.5 SD source current SD = 2 V 0.7 1.1 mA Restart threshold Measured on SD 0.40 0.55 0.70 V output driver PARAMETER TEST CONDITIONS MIN TYP MAX UNITS –50 mA (source), TA = 0°C to 85°C 4.5 6.0 9.0 PPuulllluupp rreessiissttaannccee ((PPDDRRVV)) –50 mA (source), TA = −40°C to 85°C 3.5 6.0 9.0 50 mA (sink), TA = 0°C to 85°C 6.0 9.0 16.5 PPuullllddoowwnn rreessiissttaannccee ((PPDDRRVV)) 50 mA (sink), TA = −40°C to 85°C 4.0 9.0 16.5 ΩΩ –50 mA (source), TA = 0°C to 85°C 4.5 6.0 9.0 PPuulllluupp rreessiissttaannccee ((NNDDRRVV)) –50 mA (source), TA = −40°C to 85°C 3 6 9 100 mA (sink), TA = 0°C to 85°C 2.0 3.0 4.5 PPuullllddoowwnn rreessiissttaannccee ((NNDDRRVV)) 50 mA (sink), TA = −40°C to 85°C 1.5 3.0 4.5 Deadtime delay (PDRV high to NDRV high) See Note 2 150 215 250 nnss Deadtime delay (NDRV low to PDRV low) See Note 2 70 125 175 NOTE: 1. Measured on COMP with the error amplifier in a unity gain (voltage follower) configuration. NOTE: 2. 50% point of PDRV rise to NDRV rise and 50% point of NDRV fall to PDRV fall. NOTE: 3. Enable high threshold = (VIN − 0.5). pin descriptions CLSET: CLSET is used to program the pulse-by-pulse and overcurrent shutdown levels for the UCC3585. A resistor connected between CLSET and VIN sets the over-current threshold. The over-current threshold follows the following relationship: 1.25 (cid:2)R R CLSET ISET l (cid:1) CL R DS(cid:3)on(cid:4) COMP: Output of the voltage error amplifier. Loop compensation components are connected between COMP and VFB. 4 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 pin descriptions CT: A high quality ceramic capacitor connected between this pin and ground sets the PWM oscillator frequency by the following relationship: f(cid:1)(cid:3) 1 (cid:4) 7000(cid:2)C T The oscillator is capable of reliable operation up to 500 kHz. ENB: A logical 1 (VIN – 0.5 V) on this input will activate the output drivers. A logical zero (0.5 V) will prevent switching of the output drivers. Do not allow ENB to remain between these levels steady state. GND: Reference level for the IC. All voltages and currents are with respect to GND. ISENSE: ISENSE monitors the voltage dropped across the high side P-channel MOSFET switch while it is conducting. This information is used to detect overcurrent conditions by the current limit circuitry. ISET: A resistor is connected between ISET and ground to program a precision bias for many of the UCC3585 circuit blocks. This resistor should be 100 kΩ with a maximum tolerance of 5%. 1.25 V is provided to ISET via a buffered version of the internal bandgap voltage reference. The resulting current, 1.25 V / R , is mirrored ISET directly over to CLSET to program the overcurrent threshold. NDRV: High current driver output for the low side N-channel MOSFET switch. PDRV: High current driver output for the high side P-channel MOSFET switch. PWRGND: High current return path for the MOSFET drivers. PWRGND and GND should be terminated together as close as possible to the device package . SD: This pin can configure current limit to operate in any one of three different ways. 1. A forced voltage of less than 250 mV on SD inhibits the shutdown function causing pulse by pulse limiting. 2. A capacitor from SD to GND provides a controller-converter shutdown timeout after seven consecutive overcurrent signals are received by the current limit circuitry. An internal 11-µA (typ) current sink discharges the SD capacitor to the 0.55-V (typ) restart threshold. The shutdown time is given by: (cid:5) (cid:3) (cid:4)(cid:7) C (cid:2) V (cid:6)0.55V SD IN t (cid:1) SHUT 11(cid:1)A where C is the value of the capacitor from SD to GND, and VIN is the chip supply voltage (on pin 15). SD At this point, a softstart cycle is initiated, and a 1-mA current source (typ) quickly recharges SD to VIN. During softstart, pulse-by-pulse current limiting is enabled, and the 7-cycle counter is disabled until softstart is complete (i.e. charged to approximately VIN volts). 3. A forced voltage of greater than 1 V on SD will cause the UCC3585 to latch off after seven overcurrent signals are received. After the controller is latched off, SD must drop below 250 mV to restart the controller. SS: A low leakage capacitor connected between SS and GND will provide a softstart function for the converter. The voltage on this capacitor slowly charges on start-up via an internal 13.5 µA (typ.) current source. The output of the voltage error amplifier (COMP) tracks this voltage, thereby limiting the controller duty ratio. VFB: Inverting input to the voltage type error amplifier. The common mode input range for VFB extends from GND to 1.5 V. VIN: Supply voltage for the UCC3585. Bypass with a 0.1-µF ceramic capacitor (minimum) to supply the peak gate drive currents required to change and discharge the power MOSFET gates. See application information for details. www.ti.com 5

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 block diagram ISET CLSET 7 8 UVLO 2 V PRECISION CURENT BIAS SET LIMIT ADJ VIN 15 ILIM CURRENT UVLO LIMIT 11 ISENSE 1.25 V DRIVER REF ENABLE 12 PDRV ENB 1 −0V.I8N V ANTI PWM SHOOT THRU COMP 2 R Q D PWM VFB 4 VIN LATCH DRIVER S Q 0.9 V UVLO 14 NDRV SS 3 13.5 µA PRECISION SOFTSTART COMPLETE BIAS 13 PWRGND OVER CURRENT COUNTER NC 9 ILIM SHUTDOWN TIMER CLK OSCILLATOR NC 6 11 µA L = NO SHUTDOWN DISABLE DRIVERS H = LATCHED SHUTDOWN CAP = TIMED SHUTDOWN 16 5 10 UDG−00070 CT GND SD APPLICATION INFORMATION ISET pin operation The ISET pin develops a precision current reference for many of the UCC3585’s internal circuit blocks. A resistor, R , connected from the ISET pin to ground sets the precision current value. The internal current ISET reference is set by buffering the 1.25-V internal reference to the ISET pin, which results in a current of 1.25 V/R . The UCC3585 is designed for R = 100 kΩ with a maximum tolerance of 5%. Using a different ISET ISET resistor value results in changed parametric performance and possibly unpredictable operation. oscillator The oscillator frequency is programmed by a timing capacitor connected from CT to ground. The maximum recommended frequency is 500 kHz. The timing capacitor is charged and discharged by current sources derived from the ISET pin. The voltage waveform on CT is a sawtooth ramp with approximately 95% of the period spent charging the timing capacitor. Ceramic capacitors should be used, and the capacitance tolerance adds to the accuracy of the oscillator frequency. For applications that operate over a wide temperature range or where the highest accuracy is required, temperature stable ceramic capacitors such as NPO or COG dielectric should be used for the CT capacitor. The aproximate operating frequency is determined by: f(cid:1)(cid:3) 1 (cid:4) 7000(cid:2)C T 6 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 APPLICATION INFORMATION soft-start The SS pin provides a way to prevent overshoot of the output voltage by slowly increasing the duty cycle of the PDRV output. A capacitor on SS to ground provides a controlled start-up of the supply. During start-up the COMP pin is directly clamped to the SS pin. The SS pin has an internal current source of 13.5 µA (typical) which charges the SS capacitor. Figure 1 shows the waveforms during softstart. The SS pin charges the external capacitor to VIN volts after start-up is complete. SS VIN ENB or VIN COMP V OUT V = 0.4 V + D x 2.1 0.4 V t t SS switching switching VOUT in VOUT in disabled until starts, VOUT regulation, SS regulation, SS SS reaches charging up continues to charged to VIN 0.4 V charge to VIN Figure 1. Waveforms During Softstart The softstart time is approximately: (cid:5) (cid:7) V 0.4(cid:8) OUT(cid:2)2.1 V IN t (cid:1)C (cid:2) SS SS 13.5(cid:1)A current limit operation The UCC3585 has a user configurable current limit for output overload protection. To reduce external component count and minimize losses, the P-channel MOSFET’s R is used as a current sense element. DS(on) The ISENSE pin is connected to the P-channel MOSFET drain, which is internally connected to the negative input to the current-sense comparator. The positive comparator input is connected to the CLSET pin, which has an internal current sink of 11.5 µA (typical). For highest accuracy, this current sink is derived from the ISET circuitry. A resistor from VIN to CLSET sets the current limit threshold. To eliminate errors due to PCB trace impedances, the CLSET resistor should be connected directly to the P-channel MOSFET source, and the ISENSE pin should be directly connected to the P-channel MOSFET drain. Figure 2 shows a simplified diagram of the current limit circuitry. www.ti.com 7

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 APPLICATION INFORMATION VIN 15 RCLSET S 12 G P−Channel MOSFET 8 Package To D PWM Logic 11 VOUT ISENSE ENABLE 14 11.5µA Figure 2. Current Limit Circuitry The peak current limit is calculated using the following equation: 1.25 (cid:2)R R CLSET ISET l (cid:1) CL R DS(cid:3)on(cid:4) When the R of the P-channel MOSFET is used as the sense element, several issues arise. Before the DS(on) current limit comparator is enabled, the P-channel MOSFET must be fully enhanced, and the drain to source voltage must be allowed to settle. The UCC3585 has an internal circuit that disables the current limit comparator, tISENSE, for a fixed time, starting at the PDRV output falling edge. It is important that no external gate resistor is used between the PDRV output and the P-channel gate. If a resistor is used, the PDRV output falls quickly, and the turnon of the P-channel MOSFET is delayed, possibly causing a false overcurrent event to be detected. Figure 3 shows the waveforms at the P-channel turnon instance and the t time interval. ISENSE 8 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 APPLICATION INFORMATION VIN ISENSE t ISENSE VIN/2 ISENSE PDRV Comparator Enabled 0 V −0.7 V time Figure 3. t Time Interval ISENSE The t time interval follows the approximate relationship: ISENSE (cid:3) (cid:4) V (cid:8)12.5(cid:1)A(cid:2)R (cid:2)3.2pF BE CLSET t (cid:1) ISENSE 12.5(cid:1)A As can be seen from the above equation, tISENSE is dependent upon two variables. First, tISENSE is longer for higher values of R . This allows more time for ISENSE to settle, which is beneficial for supplies with a higher CLSET current limit threshold. Second, tISENSE varies with the inherent temperature dependence of the VBE in the above equation. V can be assumed to be 0.65 V at 25°C with a temperature coefficient of −2 mV/°C. Since BE the t time interval decreases at high temperature, operation of the supply must be verified at the maximum ISENSE ambient temperature at full output load. Another issue with using the MOSFET R for the sense element is the minimum on time for the P-channel DS(on) MOSFET. Since there is a blanking interval, tISENSE , there is a minimum time that the P-channel MOSFET stays on during any PWM period. The minimum on time occurs even with the power supply output shorted, experimentally the minimum on time is approximately 400 ns. When a converter is operated continuously into a shorted or overloaded output, this minimum on time results in a significant power dissipation and stress on both MOSFETs. www.ti.com 9

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 APPLICATION INFORMATION A solution to this minimum on-time is a counter and time-out circuit. As described in the SD pin description, a capacitor on SD enables the time-out circuit. An internal digital counter is used to count the overcurrent events at the current-sense comparator output. When seven overcurrent conditions are reached, both MOSFET switches are turned off, the SS capacitor is discharged, and an 11 µA (typical) internal current sink discharges the SD capacitor. During this discharge time, both MOSFETs are held off, and the inductor current decays to zero. When the SD capacitor voltage reaches 0.55 V (typical), a softstart cycle restarts the converter. During softstart, the 7-cycle counter is disabled. However, the peak current limit comparator is enabled. When the SS voltage reaches the threshold equal to (VIN − 0.5 V), the 7-cycle counter is enabled. By sizing the SS capacitor relative to the SD capacitor, the amount of time spent switching the MOSFETs can be reduced when the output is overloaded. If the timeout mode is used, the relative capacitance values for C and C must fall into the SS SD following relationship: C (cid:9)20(cid:2)C SD SS This equation also states that, if the time-out mode is used, a softstart capacitor must be used. Figure 4 shows the waveforms when the converter is operated into a short circuit. VIN V(PDRV) 0 V VIN VIN−0.5 V V(SD) t SHUT V(SS) 0.55 V time Figure 4. Converter Operated Into Short Circuit 10 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4) UCC3585 Not Recommended for New Designs (cid:1)(cid:2)(cid:2)(cid:6)(cid:4)(cid:5)(cid:4) SLUS304F − JULY 1999 − REVISED JANUARY 2005 APPLICATION INFORMATION VIN bypass capacitor selection A ceramic capacitor must be used across VIN to GND on the UCC3585. This capacitor supplies the transient currents required to turn on and off both power MOSFETs. It is important to select a high enough capacitance value to keep the peak-to-peak ripple voltage at VIN below 100 mV. The maximum peak-to-peak ripple on VIN is somewhat arbitrary, and 100 mV is used as an estimate. Knowing the P-channel total gate charge, QP and the total gate charge for the N-channel MOSFET, Q , the minimum capacitance can be found: N Q (cid:8)Q C (cid:1) P N VIN(min) 100mV An estimate of Q can be found from the manufacturer’s data sheet curve for gate charge vs gate to source P voltage. Since the N-channel MOSFET is switched with essentially zero volts across it, a better estimation of Q is found by multiplying the input capacitance, C and the V voltage. Because C is voltage dependent, N ISS IN ISS it is important to use the C value for approximately zero volts drain to source. This gives a more accurate ISS estimation of the N-channel gate charge. power MOSFET drivers The UCC3585 contains two high current power MOSFET drivers. The source and sink current capability of these drivers has been sized to allow operation without external gate resistors. The P-channel driver has approximately three times stronger source current than sink current. This intentionally slows down the turnon of the P-channel MOSFET, which reduces the reverse recovery snap of the N-channel MOSFET body diode. The N-channel driver has a stronger sink current than source current which aids in keeping the N-channel MOSFET off when the P-channel MOSFET is turned on. Adding a gate resistor from NDRV to the N-channel MOSFET gate makes the N-channel more sensitive to dV/dt induced turnon and should be avoided. The MOSFET drivers have lower resistance at VIN = 5 V as compared to VIN = 3.3 V. At VIN = 5 V, the drivers have approximately 60% of the resistance specified at VIN = 3.3 V. operation over wide VIN ranges It is possible to design UCC3585 based supplies to operate over both the 3.3-V and 5-V input ranges. The resulting V range can be as wide at 3.0 V to 5.5 V. For a successful design, several design steps must be taken. IN First, both MOSFETs should have R rated at 2.7 V or 2.5 V. This assures reasonable efficiency at the DS(on) lowest input voltage. Second, the current limit threshold should be set at the minimum input voltage. At the minimum input voltage, the P-channel MOSFET has maximum R . As VIN is increased to 5.5 V, the R DS(on) DS(on) decreases considerably. The effect of this reduction in R is a higher current limit. Also, note that critical DS(on) parameters, such as CLSET current and oscillator frequency are specified at both 3.3 V and 5.0 V. www.ti.com 11

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC3585D NRND SOIC D 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 85 UCC3585D & no Sb/Br) UCC3585DG4 NRND SOIC D 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 85 UCC3585D & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

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