(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 (cid:2)(cid:1)(cid:11)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:12) (cid:19)(cid:2)(cid:14)(cid:20)(cid:21)(cid:12) (cid:2)(cid:22)(cid:19)(cid:16)(cid:23) (cid:23)(cid:24)(cid:16) (cid:2)(cid:17)(cid:13)(cid:14)(cid:11)(cid:17)(cid:22)(cid:22)(cid:12)(cid:11) FEATURES DESCRIPTION (cid:1) Low Output Jitter The UCC2891/2/3/4 family of PWM controllers is (cid:1) Soft−Stop Shutdown of MAIN and AUX designed to simplify implementation of the various (cid:1) Ideal for Active Clamp/Reset Forward, active clamp/reset switching power topologies. Flyback Converters The UCC289x is a peak current-mode, fixed- (cid:1) Provides Complementary Auxiliary Driver frequency, high-performance pulse width modulator. with Programmable Deadtime (Turn-On It includes the logic and the drive capability for the Delay) between AUX and MAIN Switches auxiliary switch with a simple method of (cid:1) Peak Current-Mode Control with programming the critical delays for proper active Cycle-by-Cycle Current Limiting clamp operation. (cid:1) 110-V Input Startup Regulator on UCC2891/3 The UCC2891/3 includes a 110-V start-up (cid:1) TrueDrive(cid:2) 2-A Sink, 2-A Source Outputs regulator for initial start-up and to provide (cid:1) Accurate Line UV and Line OV Threshold keep-alive power during stand-by. (cid:1) Programmable Slope Compensation Additional features include an internal (cid:1) 1.0-MHz Synchronizable Oscillator programmable slope compensation circuit, (cid:1) Precise Programmable Maximum Duty Cycle precise DMAX limit, and a single resistor programmable synchronizable oscillator. An (cid:1) Programmable Soft Start accurate line monitoring function also programs the converter’s ON and OFF transitions with APPLICATIONS regard to the bulk input voltage. Along with the UCC2897, this UCC289x family allows the power (cid:1) 150-W to 700-W SMPS supply designer to eliminate many of the external (cid:1) High-Efficiency, Low EMI/RFI Off-Line or components, reducing the size and complexity of DC/DC Converters the design. (cid:1) Server, 48-V Telecom, Datacom (cid:1) High Power Adapter, LCD-TV and PDP-TV BIAS RDEL UCC2891 WINDING +VIN 1 RDEL VIN 16 Lo Q4 RON CBULK D3 D4 Co LOAD 2 RTON LINE UV 15 ROFF CBIAS Q1 3 RTOFF VDD 14 ROUT CCLAMP D1 Q3 4 VREF OUT 13 SR CVREF CAUX Q2 D2 DRIVE 5 SYNC AUX 12 6 GND PGND 11 RCS CF CSS 7 CS SS/SD 10 DAUX SECONDARY 8 RSLOPE FB 9 SIDE E/A RSLOPE RF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:23)(cid:11)(cid:17)(cid:18)(cid:1)(cid:2)(cid:14)(cid:20)(cid:17)(cid:13) (cid:18)(cid:19)(cid:14)(cid:19) (cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!(cid:25)(cid:28)(cid:26) (cid:25)" #$(cid:29)(cid:29)%(cid:26)! (cid:31)" (cid:28)(cid:27) &$’((cid:25)#(cid:31)!(cid:25)(cid:28)(cid:26) )(cid:31)!%* Copyright  2003 − 2009, Texas Instruments Incorporated (cid:23)(cid:29)(cid:28))$#!" #(cid:28)(cid:26)(cid:27)(cid:28)(cid:29)(cid:30) !(cid:28) "&%#(cid:25)(cid:27)(cid:25)#(cid:31)!(cid:25)(cid:28)(cid:26)" &%(cid:29) !+% !%(cid:29)(cid:30)" (cid:28)(cid:27) (cid:14)%,(cid:31)" (cid:20)(cid:26)"!(cid:29)$(cid:30)%(cid:26)!" "!(cid:31)(cid:26))(cid:31)(cid:29)) -(cid:31)(cid:29)(cid:29)(cid:31)(cid:26)!.* (cid:23)(cid:29)(cid:28))$#!(cid:25)(cid:28)(cid:26) &(cid:29)(cid:28)#%""(cid:25)(cid:26)/ )(cid:28)%" (cid:26)(cid:28)! (cid:26)%#%""(cid:31)(cid:29)(cid:25)(. (cid:25)(cid:26)#($)% !%"!(cid:25)(cid:26)/ (cid:28)(cid:27) (cid:31)(( &(cid:31)(cid:29)(cid:31)(cid:30)%!%(cid:29)"* www.ti.com 1

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Line input voltage, VIN 120 V Supply voltage, VDD (IDD < 10 mA) 16.5 V −0.3 to (VREF + 0.3) Analog inputs FB, CS, SYNC, LINEOV, LINEUV V not to exceed 6 Output source current (peak), IO_SOURCE 2.5 OOUUTT,, AAUUXX AA Output sink current (peak), IO_SINK −2.5 Operating junction temperature range, TJ −55 to 150 °°CC Storage temperature, Tstg −65 to 150 Human body model, (HBM) 2000 EESSDD rraattiinngg VV Change device model (CDM) 500 Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Line input voltage, VIN 18 110 V Supply voltage, VDD 8.5 12.0 16.0 V Supply bypass capacitance 1 µF Timing resistance, RON = ROFF (for 250-kHz 75 kΩ operation) Operating junction temperature, TJ −40 105 °C Reference bypass capacitance, CREF 0.1 1 µF ORDERING INFORMATION PART NUMBERS CS AUX THRESHOLD 110-V START-UP SOIC−16 TSSOP−16 TA APPLICATION OUTPUT (INCLUDES CIRCUIT (D) (PW) POLARITY SLOPE COM- PENSATION) DC−DC 0.75 V Yes UCC2891D UCC2891PW PP--CChhaannnneell DC-DC/Sec. Side 1.27 V No UCC2892D UCC2892PW −−4400°°CC ttoo 112255°°CC DC−DC 0.75 V Yes UCC2893D UCC2893PW NN--CChhaannnneell Off−Line 1.27 V No UCC2894D UCC2894PW †The D and PW packages are available taped and reeled. Add R suffix to device type (e.g. UCC2891DR) to order quantities of 2,500 devices per reel (for the D package) and 2,000 devices per reel (for the PW package). Bulk quantities are 40 units per tube (for the D package) and 90 units per tube (for the PW package). 2 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 THERMAL RESISTANCE INFORMATION PACKAGE THERMAL RESISTANCE UNITS θjc 36.9 to 38.4 SSOOIICC−−1166 ((DD)) °°CC//WW θja (0 LFM) 73.1 to 111.6 θjc 33.6 to 35.0 TTSSSSOOPP−−1166 ((PPWW)) °°CC//WW θja (0 LFM) 108.4 to 147.0 PIN ASSIGNMENTS UCC2891 AND UCC2893 UCC2892 AND UCC2894 D and PW PACKAGEs D AND PW PACKAGE (TOP VIEW) (TOP VIEW) RTDEL 1 16 VIN RTDEL 1 16 LINEOV RTON 2 15 LINEUV RTON 2 15 LINEUV RTOFF 3 14 VDD RTOFF 3 14 VDD VREF 4 13 OUT VREF 4 13 OUT SYNC 5 12 AUX SYNC 5 12 AUX GND 6 11 PGND GND 6 11 PGND CS 7 10 SS/SD CS 7 10 SS/SD RSLOPE 8 9 FB RSLOPE 8 9 FB ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERALL ISTARTUP Start-up current VDD < VUVLO 300 500 µA IDD Operating supply current(1)(2) VOFuBtp u=t s0 nVo, t switchingVCS = 0 V, 2 3 mA HIGH-VOLTAGE BIAS SECTION (UCC2891, UCC2893) Current available from VDD during Start- IDD−ST VDD startup current up, VIN = 36 V, TA = −40°C to 85°C (3) 4 11 mA IVIN JFET leakage current VIN = 120 V; VDD = 14 V 75 µA UNDERVOLTAGE LOCKOUT Start threshold voltage(1) 12.2 12.7 13.2 Minimum operating voltage after start 7.6 8.0 8.4 VV Hysteresis 4.4 4.7 5.0 LINE MONITOR VLINEUV Line UV and Line OV voltage threshold 1.243 1.268 1.293 V ILINEHYS Line UV and Line OV hysteresis current 11.8 12.5 14.5 µA SOFT-START ISS Charge current RTON = 75 kΩ −10.5 −18.5 µAA ISS Discharge current RTON = 75 kΩ 10.5 18.5 VSS/SD Discharge/shutdown threshold voltage 0.4 0.5 0.6 V (1)Set VDD above the start threshold before setting at 12 V. (2)Does not include current of the external oscillator network. (3)The power supply starts with IDD−ST load on VDD, part will start up with no load up to 125°C. For more detailed information, see pin descriptions for VIN and VDD. (4)ISSC and ISS/SD are directly proportional to IRON. See equation 7. www.ti.com 3

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference TJ = 25°C 4.85 5.00 5.15 VVRREEFF RReeffeerreennccee vvoollttaaggee VV 0 A < IREF < 5 mA, over temperature 4.75 5.00 5.25 ISC Short circuit current REF = 0 V, TJ = 25°C −20 −11 −8 mA INTERNAL SLOPE COMPENSATION m Slope(3) FB = High -10% RCS +10% R SLOPE OSCILLATOR fOSC Oscillator frequency TJ = 25°C 237 250 263 kkkHHHzzz TToottaall vvaarriiaattiioonn −−4400 °°CC << TTJJ 112255°°CC;; 88..55 VV << 1144..55 VV 222255 227700 VP_P Oscillator amplitude (peak-to-peak) 2 V SYNCHRONIZATION VSYNCH SYNC theshold voltage 1.6 2.3 3.0 V tDEL SYNC-to-output delay 50 ns PWM Maximum duty cycle 66% 70% 74% Minimum duty cycle 0% PWM offset CS = 0 V 0.43 0.50 0.61 V CURRENT SENSE VLVL Current sense level shift voltage 0.40 0.50 0.60 VERR(max) Maximum voltage error (clamped) 4.8 5.0 5.2 UCC2891 VCS Current sense threshold UCC2893 0.71 0.75 0.79 V UCC2892 VCS Current sense threshold UCC2894 1.23 1.27 1.31 (1)Set VDD above the start threshold before setting at 12 V. (2)Does not include current of the external oscillator network. 4 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ELECTRICAL CHARACTERISTICS VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ, RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT (OUT AND AUX) tR Rise time CLOAD = 2 nF 19 28 tF Fall time CLOAD = 2 nF 14 23 nnss tDEL1 Delay time (AUX to OUT) CLOAD = 2 nF, RDEL = 10 kΩ 110 tDEL2 Delay time (OUT to AUX) CLOAD = 2 nF, RDEL = 10 kΩ 115 IOUT(src) Output source current −2 AA IOUT(sink) Output sink current 2 VOUT(low) Low-level output voltage IOUT = 150 mA 0.4 VV VOUT(high) High-level output voltage IOUT = −150 mA 11.1 50% 50% t OUT AUX 50% 50% t (N−channel) AUX 50% 50% t (P−channel) t t DEL1 DEL2 Figure 1. Output Timing Diagram www.ti.com 5

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL BLOCK DIAGRAM TYP: VREF = 5.0 V VREF 0.05 * IRDEL 92/94 1/2 x VREF VREF VIN (UCC2891/3) 16 LINEOV (UCC2892/4) IRDEL 0.05 * IRDEL + OV 1.27 V RDEL 1 91/93 1/2 x VREF + 15 LINEUV CLOCK UV 1.27 V VDD OK 13 V/ 8 V + RTON 2 VDD 1/2 x VREF 1−DMAX OUT PWM IRTON OFF 14 VDD VDD CT VREF RTOFF 3 SYNC IRDEL VDD REF OUT VREF 4 GEN PWM Offset TURN−ON 13 OUT 0.5 V S Q DELAY SYNC 5 + + R Q VREF 75k VDD VREF IRDEL 91/92 P−Ch. 5 * ISLOPE 12 AUX GND 6 TURN−ON CS 7 + DELAY 93/94 N−Ch. OV OFF 11 PGND 1−DMAX VREF UV OFF ISS = 0.43 x IRTON UCC2892/4 1.27 V 3 * R + 10 SS/SD UCC2891/3 0.75 V VDD CT 2 * R UV UVLO AND ISLOPE VREF SS ENABLE OV RSLOPE 8 + 9 FB 6 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TERMINAL FUNCTIONS TERMINAL UCC2891 UCC2892 I/O DESCRIPTION NAME UCC2893 UCC2894 This output drives the auxiliary clamp MOSFET which is turned on when the main PWM AUX 12 12 O switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A source turn-on current and 2-A sink turn-off current. This pin is used to sense the peak current utilized for current mode control and for current limiting functions. The peak signal which can be applied to this pin before pulse-by-pulse CS 7 7 I current limiting activates is approximately 0.75 V for the UCC2891 and UCC2893 and 1.27 V for the UCC2892 and UCC2894. This pin is used to bring the error signal from an external optocoupler or error amplifier into the PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoup- FB 9 9 I ler is used to pull the control pin closer to GND to reduce the pulse width of the OUT output driving the main power switch of the converter. This pin serves as the fundamental analog ground for the PWM control circuitry. This pin GND 6 6 − should be connected to PGND directly at the device. LINEOV − 16 I For the UCC2892/4, provides the LINE overvoltage function. This pin provides a means to accurately enable/disable the power converter stage by moni- toring the bulk input voltage or another parameter. When the circuit initially starts (or restarts from a disabled condition), a rising input on LINEUV enables the outputs when the threshold LINEUV 15 15 I of 1.27 V is crossed. After the circuit is enabled, then a falling LINEUV signal disables the outputs when the same threshold is reached. The hysteresis between the two levels is pro- grammed using an internal current source. This output pin drives the main PWM switching element MOSFET in an active clamp control- OUT 13 13 O ler. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sink turn-off current. A 10−kΩ resistor is recommended to connect this pin to PGND. The PGND should serve as the current return for the high-current output drivers OUT and PGND 11 11 − AUX. Ideally, the current path from the outputs to the switching devices, and back would be as short as possible, and enclose a minimal loop area. A resistor connected from this pin to GND programs an internal current source that sets the RSLOPE 8 8 I slope compensation ramp for the current mode control circuitry. A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs to RTDEL 1 1 I accommodate the resonant transitions of the active clamp power converter. A resistor connected from this pin to GND programs an internal current source that dis- RTOFF 3 3 I charges the internal timing capacitor. A resistor connected from this pin to GND programs an internal current source that charges RTON 2 2 I the internal timing capacitor. A capacitor from SS/SD to ground is charged by an internal current source of IRTON to pro- SS/SD 10 10 I gram the soft-start interval for the controller. During a fault condition this capacitor is dis- charged by a current source equal to IRTON. The SYNC pin serves as a unidirectional synchronization input for the internal oscillator. The SYNC 5 5 I synchronization function is implemented such that the user programmable maximum duty cycle (set by RTON and RTOFF) remains accurate during synchronized operation. This is the power supply for the device. There should be a 1-µF capacitor directly from VDD VDD 14 14 I to PGND. The capacitor value should be minimum 10 times greater than that on VREF. PGND and GND should be connected externally and directly from PGND to GND. For the UCC2891 and UCC2893, this pin is connected to the input power rail directly. Inside VIN 16 − I the device, a high-voltage start-up device is utilized to provide the start-up current for the controller until a bootstrap type bias rail becomes available. This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA. Since this reference provides the supply rail for internal logic, it should be bypassed to VREF 4 4 O AGND as close as possible to the device. The VREF bias profile may not be monotonic before VDD reached 5 V. www.ti.com 7

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS RDEL (pin 1) This pin is internally connected to an approximately 2.5-V DC source. A resistor (R ) to GND (pin 6) sets the DEL turn-on delay for both gate drive signals of the UCC2981 family of controllers. The delay time is identical for both switching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX (pin 14) is turning off and OUT (pin 13) is turning on. The delay time is defined as: t (cid:1)t (cid:1)11.1(cid:2)10(cid:3)12(cid:2)R (cid:4)15(cid:2)10(cid:3)9 seconds DEL1 DEL2 DEL (1) For proper selection of the delay time refer to the various references describing the design of active clamp power converters. RTON (pin 2) This pin is internally connected to an approximately 2.5-V DC source. A resistor (R ) to GND (pin 6) sets the ON charge current of the internal timing capacitor. The RTON pin, in conjunction with the RTOFF pin (pin 3) are used to set the operating frequency and maximum operating duty cycle of the UCC2891 family. RTOFF (pin3) This pin is internally connected to an approximately 2.5-V DC source. A resistor (R ) to GND (pin 6) sets the OFF discharge current of the internal timing capacitor. The RTON and RTOFF pins are used to set the switching period (T ) and maximum operating duty cycle (D ) according to the following equations: SW MAX t (cid:1)36.1(cid:2)10(cid:3)12(cid:2)R (cid:3)t seconds ON ON DEL1 (2) t (cid:1)15(cid:2)10(cid:3)12(cid:2)R (cid:4)t (cid:4)170(cid:2)10(cid:3)9 seconds OFF OFF DEL1 (3) T (cid:1)t (cid:4)t SW ON OFF (4) t D (cid:1) ON MAX T SW (5) VREF (pin 4) The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a good quality ceramic bypass capacitor (C ) to GND (pin 6) for noise filtering and to provide compensation to the regulator VREF circuitry. The recommended C value is 0.22-µF. The minimum bypass capacitor value is 0.022-µF limited VREF by stability considerations of the bias regulator, while the maximum is approximately 22-µF. Also, capacitor value on VDD should be minimum 10 times greater than that on VREF. The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC289x controllers. For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional Description section of this datasheet. 8 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) SYNC (pin 5) This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator of the UCC289x family of controllers. The synchronizing frequency must be higher than the free running (cid:5) (cid:7) frequency of the onboard oscillator T (cid:6)T . The acceptable minimum pulse width of the SYNC SW synchronization signal is approximately 50 ns (positive logic), and it should remain shorter than (cid:5) (cid:7) 1(cid:3)D (cid:2)T where D is set by R and R . If the pulse width of the synchronization signal stays MAX SYNC MAX ON OFF within these limits, the maximum operating duty ratio remains valid as defined by the ratio of R and R , ON OFF and D is the same in free running and in synchronized modes of operation. If the pulse width of the MAX (cid:5) (cid:7) synchronization signal would exceed the 1(cid:3)D (cid:2)T limit, the maximum operating duty cycle is MAX SYNC defined by the synchronization pulse width. For more information on synchronization of the UCC2891 family refer to the Functional Description section of this datasheet. GND (pin 6) This pin provides a reference potential for all small signal control and programming circuitry inside the UCC2891 family. CS (pin 7) This is a direct input to the PWM and current limit comparators of the UCC2891 family of controllers. The CS pin should never be connected directly across the current sense resistor (R ) of the power converter. A small, CS customary R−C filter between the current sense resistor and the CS pin is necessary to accommodate the proper operation of the onboard slope compensation circuit and in order to protect the internal discharge transistor connected to the CS pin (R , C ). F F Slope compensation is achieved across R by a linearly increasing current flowing out of the CS pin. The slope F compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT) of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the (cid:5) (cid:7) timing capacitor. This time interval is 1(cid:3)D (cid:2)T long and represents the guaranteed off time of the MAX SW main power switch. RSLOPE (pin 8) A resistor (R ) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation SLOPE current. During the on time of the main gate drive output (OUT) the voltage across R is a representation SLOPE of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across R SLOPE also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope compensation is proportional to this current flowing through R . SLOPE Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and inductance of the external circuit components connected to the RSLOPE pin should be carefully minimized. For more information on how to program the internal slope compensation refer to the Setup Guide section of this datasheet. www.ti.com 9

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) FB (pin 9) This pin is an input for the control voltage of the pulse width modulator of the UCC2891 family. The control voltage is generated by an external error amplifier by comparing the converters output voltage to a voltage reference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is located on the secondary side of the isolated power converter and its output voltage is sent across the isolation boundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistor to the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry. The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to make it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin is between approximately 1.25 V and 4.5 V. Control voltages below the 1.25-V threshold result in zero duty cycle (pulse skipping) while voltages above 4.5 V result in full duty cycle (D ) operation. MAX SS/SD (pin 10) A capacitor (C ) connected between this pin and GND (pin 6) programs the soft start time of the power SS converter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed by the R resistor connected to pin 2. The soft-start current is defined as: ON V I (cid:1)0.43(cid:2)I (cid:1)0.43(cid:2) REF(cid:2) 1 SS RTON 2 R ON (6) This DC current charges C from 0 V to approximately 5 V. Internal to the UCC2891 family of controllers, the SS soft start capacitor voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lower of the two voltages manipulates the controller’s PWM engine through the voltage divider described with regards to the FB pin. Accordingly, the useful control range on the SS pin is similar to the control range of the FB pin and it is between 1.25 V and 4.5 V approximately. PGND (pin 11) This pin serves as a dedicated connection to all high-current circuits inside the UCC2891 family of parts. The high-current portion of the controller consists of the two high-current gate drivers, and the various bias connections except VREF (pin 4). The PGND (pin 11) and GND (pin 6) pins are not connected internally, a low-impedance, external connection between the two ground pins is also required. It is recommended to form a separate ground plane for the low current setup components (R , R , R , C , C , R , C and DEL ON OFF VREF F SLOPE SS the emitter of the opto-coupler in the feedback circuit). This separate ground plane (GND) should have a single connection to the rest of the ground of the power converter (PGND) and this connection should be between pin 6 and pin 11 of the controller. AUX (pin 12) This is a high-current gate drive output for the auxiliary switch to implement the active clamp operation for the power stage. The auxiliary output (AUX) of the UCC2891 and UCC2892 drives a P-channel device as the clamp switch therefore it requires an active low operation (the switch is ON when the output is low). The UCC2893 and UCC2894 controllers are optimized for N-channel auxiliary switch therefore it employs the traditional active high drive signal. 10 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) OUT (pin 13) This high-current output drives an external N-channel MOSFET. Each controller in the UCC2891 family uses active high drive signals for the main switch of the converter. Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance of the external circuit components connected to these pins should be carefully minimized. A potential way of avoiding unnecessary parasitic inductances in the gate drive circuit is to place the controller in close proximity to the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices are connected by wide, overlapping traces. VDD (pin 14) The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator and for parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramic capacitor (C ) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate HF filtering. The recommended C value is 1-µF for most applications but its value might be affected by the HF properties of the external MOSFET transistors used in the power stage. In addition to the low-impedance, high-frequency filtering, the controller’s bias rail requires a larger value energy storage capacitor (C ) connected parallel to C . The energy storage capacitor must provide the hold up time BIAS HF to operate the UCC2891 family (including gate drive power requirements) during start up. In steady state operation the controller must be powered from a bootstrap winding off the power transformer or by an auxiliary bias supply. In case of an independent auxiliary bias supply, the energy storage is provided by the output capacitance of the bias supply. When using the internal JFET for startup, the external load on VDD must be limited to less than 4 mA. LINEUV (pin 15) This input monitors the incoming power source to provide an accurate undervoltage lockout function with user programmable hysteresis for the power supply controlled by the UCC2891 family. The unique property of the UCC2891 family is to use only one pin to implement these functions without sacrificing on performance. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage lockout comparator by an external resistor divider (R , R in Figure 7). Once the line monitor’s input threshold is IN1 IN2 exceeded, an internal current source gets connected to the LINEUV pin. The current generator is programmed by the R resistor connected to pin 1 of the controller. The actual current level is given as: DEL V I (cid:1) REF(cid:2) 1 (cid:2)0.05 HYST 2 R DEL (7) As this current flows through R of the input divider, the undervoltage lockout hysteresis is a function of I IN2 HYST and R allowing accurate programming of the hysteresis of the line monitoring circuit. IN2 For more information on how to program the line monitoring function refer to the Setup Guide of this datasheet. www.ti.com 11

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 DETAILED PIN DESCRIPTIONS (continued) VIN (pin 16 − UCC2891 and UCC2893 only) The UCC2891 and UCC2893 controllers are equipped with a high voltage, P-channel JFET start up device to initiate operation from the input power source of the converter in applications where the input voltage does not exceed the 110-V maximum rating of the start up transistor. In these applications, the VIN pin can be connected directly to the positive terminal of the input power source. The internal JFET start up transistor provides approximately 15-mA charge current for the energy storage capacitor (C ) connected across the VDD (pin BIAS 14) and PGND (pin 11) terminals. Note that the start up device is turned off immediately when the voltage on the VDD pin exceeds approximately 13.5 V, the controller’s undervoltage lockout threshold for turn-on. The JFET is also disabled at all times when the high-current gate drivers are switching to protect against excessive power dissipation and current through the device. When using the internal JFET for startup, the external load on VDD must be limited to less than 4 mA. For more information on biasing the UCC2891 family, refer to the Setup Guide and Additional Application Information Sections of this datasheet. LINEOV (pin 16 − UCC2892 and UCC2894 only) In the UCC2892 and UCC2894 controllers the high-voltage start-up device is not utilized thus pin 16 is used for a different function. This input monitors the incoming power source to provide an accurate overvoltage protection with user programmable hysteresis for the power supply controlled by the controller. The circuit implementation of the overvoltage protection function is identical to the technique used for monitoring the input power rail for undervoltage lockout. This allows implementing an accurate threshold and hysteresis using only one pin. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltage protection comparator by an external resistor divider (R , R in Figure 7). Once the line monitor’s input IN3 IN4 threshold is exceeded, an internal current source gets connected to the LINEOV pin. The current generator is programmed by the R resistor connected to pin 1 of the controller. The actual current level is given as: DEL V I (cid:1) REF(cid:2) 1 (cid:2)0.05 HYST 2 R DEL (8) As this current flows through R of the input divider, the overvoltage protection hysteresis is a function of I IN4 HYST and R allowing accurate programming of the hysteresis of the line monitoring circuit. IN4 For more information on how to program the overvoltage protection, refer to the Setup Guide of this datasheet. 12 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION JFET Control and UVLO The UCC2891 and UCC2893 controllers include a high voltage JFET start up transistor. The steady state power consumption of the of the control circuit which also includes the gate drive power loss of the two power switches of an active clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should only be used for initial start up of the control circuitry and to provide keep-alive power during stand-by mode when the gate drive outputs are not switching. Accordingly, the start-up device is managed by its own control algorithm implemented on board the UCC2891 and UCC2893. The following timing diagram illustrates the operation of the JFET start up device. VON V IN 13.5V 10.0V 8V <VDD < 10V 8.0V V Bootstrap bias DD JFET OFF OFF OFF ENABLE (See diagram on p.6) SS/SD OFF OFF SWITCHING OFF OUTPUTs SWITCHING UDG−03148 Figure 2. JFET Control Startup and Shutdown During initial power up the JFET is on and charges the C and C capacitors connected to the VDD pin (pin BIAS HF 14). The VDD pin is monitored by the controller’s undervoltage lockout circuit to ensure proper biasing before the operation is enabled. When the VDD voltage reaches approximately 12.7 V (UVLO turn-on threshold) the UVLO circuit enables the rest of the controller. At that time, the JFET is turned off and 5 V appears on the VREF terminal (pin 4). Switching waveforms might not appear at the gate drive outputs unless all other conditions of proper operation are met. These conditions are: (cid:1) sufficient voltage on the VREF pin (V > 4.5V) VREF (cid:1) the voltage on the CS pin is below the current limit threshold (cid:1) the control voltage is above the zero duty cycle boundary (V > 1.25 V) FB (cid:1) the input voltage is in the valid operating range (V <V <V ) i.e. the line under or overvoltage VON VIN VOFF protections are not activated. www.ti.com 13

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION As the controller starts operation it draws its bias power from the C capacitor until the bootstrap winding BIAS takes over (refering to Figure 12). During this time VDD voltage is falling rapidly as the JFET is already off but the bootstrap voltage is still not sufficient to power the control circuits. It is imperative to store enough energy in C to prevent the bias voltage to dip below the turn off threshold of the UVLO circuit during the start up BIAS time interval. Otherwise the power supply goes through several cycles of retry attempts before steady state operation might be established. During normal operation the bias voltage is determined by the bootstrap bias design. The UCC289x family can tolerate a wide range of bias voltages between the minimum operating voltage (UVLO turn-off threshold) and the absolute maximum operating voltage as defined in the Recommended Operating Conditions. In applications where the power supply must be able to go to stand by in response to an external command, the bias voltage of the controller must be kept alive to be able to react intelligently to the control signal. In stand by mode, switching action is suspended for an undefined period of time and the bootstrap power is unavailable to bias the controller. Without an alternate power source the bias voltage would collapse and the controller would initiate a re-start sequence. To avoid this situation, the on board JFET of the UCC289x controllers can keep the VDD bias alive as long as the gate drive outputs remain inactive. As shown in the timing diagram in Figure 2, the JFET is turned on when VDD = 10 V and charges the CBIAS capacitor to approximately 13.5 V. At that time the JFET turns off and VDD gradually decreases to 10 V then the procedure is repeated. When the power supply is enabled again, the controller is fully biased and ready to initiate its soft start sequence. As soon as the gate drive pulses appear the JFET are turned off and bias must be provided by the bootstrap bias generator. During power down the situation is different as switching action might continue until the VDD bias voltage drops below the controller’s own UVLO turn-off threshold (approximately 8 V). At that time the UCC289x shuts down completely turning off its 5 V bias rail and returning to start up state when the JFET device is turned on and the C capacitor starts charging again. In case the converter’s input voltage is re-established, the UCC289x BIAS attempts to restart the converter. Line Undervoltage Protection As shown in Figure 3, when the input power source is removed the power supply is turned off by the line undervoltage protection because the bootstrap winding keeps the VDD bias up as long as switching takes place in the power stage. As the power supply’s input voltage gradually decreases towards the line cut off voltage the converter’s operating duty cycle must compensate for the lower input voltage. At minimum input voltage the duty cycle nears its maximum value (D ). Under these conditions the voltage across the clamp capacitor MAX approaches its highest value since the transformer must be reset in a relatively short time. The timing diagram in Figure 3 highlights that in the instance when the converter stops switching the clamp capacitor voltage might be at its maximum level. Since the clamp capacitor’s only load is the power transformer, this high voltage could linger across the clamp capacitor for a long time when the converter is off. With this high voltage present across the clamp capacitor a soft start would be very dangerous, due to the narrow duty cycle of the main switch and the long on-time of the clamp switch. This could cause the power transformer to saturate during the next soft-start cycle. 14 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOFF VIN VCLAMP, MAX VCLAMP VSS TSW OUT AUX Figure 3. Line Undervoltage Shutdown Waveforms, P−Channel To eliminate this potential hazard the UCC289x controllers safely discharge the clamp capacitor during power down. The AUX and OUT output continues switching while the soft-start capacitor C is being slowly SS discharged. Notice that the AUX and OUT pulse width gradually decreases as the clamp voltage decreases never applying the high voltage across the transformer for extended period of time. From this, the function of soft stop is achieved. Line Overvoltage Protection When the line overvoltage protection is triggered in the UCC2892 and UCC2894 controllers, the gate drive signals are immediately disabled. At the same time, the slow discharge of C is initiated. While the soft-start SS capacitor is discharging the gate drive signals remains disabled. Once VSS = 0.5 V and the overvoltage disappears from the input of the power supply, operation resumes through a regular soft-start of the converter as it is demonstrated in Figure 4. www.ti.com 15

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION VOVP VOVH VIN VSS OUT AUX UDG−03150 Figure 4. Line Overvoltage Sequence, P−Channel Pulse Skipping During output load current transients or light load conditions most PWM controllers needs to be able to skip some number of PWM pulses. In an active clamp topology where the clamp switch is driven complementarily to the main switch, this would apply the clamp voltage across the transformer continuously. Since operating conditions might require skipping several switching cycles on the main transistor, saturating the transformer is very likely if the AUX output stays on. D = 0 Boundary 1.25 V FB TSW OUT AUX UDG−03151 Figure 5. Pulse Skipping Operation, P−Channel To overcome this problem, the UCC2891 family incorporates pulse skipping for both outputs in the controller. As can be seen above, when a pulse is skipped at the main output (OUT) because the feedback signal demands zero duty ratio, the corresponding output pulse on the AUX output is omitted as well. This operation allows to prevent reverse saturation of the power transformer and to preserve the clamp capacitor voltage level during pulse skipping operation. 16 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION Synchronization The UCC2891 family has a synchronization input pin which can be used to synchronize their oscillator to a constant frequency system clock. The synchronization signal must have a higher frequency than the free running oscillator frequency and can be either in-phase or out-of-phase for interleaved operation. The operation of the oscillator and relevant other waveforms in free running and synchronized mode are shown in Figure 6. SYNC CT DMAX OUT AUX UDG−03152 Figure 6. Synchronization Waveforms, P−Channel The most critical and unique feature of the oscillator is to limit the maximum operating duty cycle of the converter. It is achieved by accurately controlling the charge and discharge intervals of the on board timing capacitor. The maximum on-time of OUT (pin 13), which is also the maximum duty cycle of the active clamp converter is limited by the charging interval of the timing capacitor. While the capacitor is being reset to its initial voltage level OUT is guaranteed to be off. When synchronization is used, the rising edge of the signal terminates the charging period and initiate the discharge of the timing capacitor. Once the timing capacitor voltage reaches the predefined valley voltage, a new charge period starts automatically. This method of synchronization leaves the charge and discharge slopes of the timing waveform unaffected thus maintains the maximum duty cycle of the converter, independent of the mode of operation. Although the synchronization circuit is level sensitive, the actual synchronization event occurs at the rising edge of the waveform. This allows the synchronizing pulse width to vary significantly but certain limitations must be observed. The minimum pulse width should be sufficient to guarantee reliable triggering of the internal oscillator circuitry, therefore it should be greater than approximately 50 nanoseconds. The other limiting factor is to keep (cid:5) (cid:7) it shorter than 1(cid:3)DMAX (cid:2)TSYNC where TSYNC is the period of the synchronization frequency. www.ti.com 17

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 FUNCTIONAL DESCRIPTION (cid:5) (cid:7) When a wider than 1(cid:3)D (cid:2)T pulse is connected to the SYNC input, the oscillator is not able to MAX SYNC maintain the maximum duty cycle, originally set by the timing resistor ratio (R , R ). Furthermore, the timing ON OFF capacitor waveform has a flat portion as highlighted by the vertical marker in the timing diagram. During this flat portion of the waveform both outputs is off which state is not compatible with the operation of active clamp power converters. Therefore, this operating mode is not recommended . Note that both outputs of the UCC289x controllers are off if the synchronization signal stays continuously high. APPLICATION INFORMATION: SETUP GUIDE RIN2 RIN1 RIN2 RIN1 RIN4 RIN3 +VIN +VIN UCC2892 UCC2891 UCC2894 UCC2893 RDEL RDEL 1 RDEL LINEOV 16 1 RDEL VIN 16 RON CBIAS RON CBIAS 2 RTON LINEUV15 2 RTON LINEUV 15 E ROFF 3 RTOFF VDD 14 CHF TAGE ROFF 3 RTOFF VDD 14 CHF STAG S CVREF R CVREF R E E 4 VREF OUT 13 W 4 VREF OUT 13 W O O ROT P ROT P 5 SYNC AUX 12 5 SYNC AUX 12 6 GND PGND 11 −VIN 6 GND PGND 11 −VIN CF CF 7 CS SS/SD 10 7 CS SS/SD 10 RSLOPE RSLOPE 8 RSLOPE FB 9 8 RSLOPE FB 9 CSS CSS RF RF RVREF Isolated Feedback RVREF Isolated Feedback Figure 7. UCC289x Typical Setup 18 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE The UCC2891 family offers a highly integrated feature set and excellent accuracy to control an active clamp forward or active clamp flyback power converter. In order to take advantage of all the benefits integrated in these controllers, the following procedure can simplify the setup and avoid unnecessary iterations in the design procedure. Refer to Figure 7 setup diagrams for component names. Before the controller design begins, the power stage design must be completed. From the power stage design the following operating parameters are needed to complete the setup procedure of the controller: (cid:1) Switching frequency (f ) SW (cid:1) Maximum operating duty cycle (D ) MAX (cid:1) Soft start duration (t ) SS (cid:1) Gate drive power requirements of the external power MOSFETs (Q , Q ) G(main) G(aux) (cid:1) Bias method and voltage for steady state operation (bootstrap or bias supply) (cid:1) Gate drive turn-on delay (t ) DEL (cid:1) Turn−on input voltage threshold (V ) ON (cid:1) Minimum operating input voltage (VOFF) where VIN (off) < VIN(on) (cid:1) Maximum operating input voltage (V ) OVP (cid:1) overvoltage protection hysteresis (V ) OVH (cid:1) The down slope of the output inductor current waveform reflected across the primary side current sense (cid:5) (cid:7) resistor dV (cid:8)dt L Step 1. Oscillator The two timing elements of the oscillator can be calculated from f and D by the following two equations: SW MAX t (cid:5)(cid:1)(cid:7) D (cid:5)(cid:1)(cid:7) R (cid:1) ON (cid:2) (cid:1) MAX (cid:2) ON 37.33(cid:2)10(cid:3)12 s f (cid:2)37.33(cid:2)10(cid:3)12 s SW (9) t (cid:5)(cid:1)(cid:7) 1(cid:3)D (cid:5)(cid:1)(cid:7) R (cid:1) OFF (cid:2) (cid:1) MAX (cid:2) OFF 16(cid:2)10(cid:3)12 s f (cid:2)16(cid:2)10(cid:3)12 s SW (10) where D is a dimensionless number between 0 and 1. MAX Step 2. Soft Start Once R is defined, the charge current of the soft-start capacitor can be calculated as: ON V I (cid:1)0.43(cid:2) REF(cid:2) 1 SS 2 R ON (11) During soft start, C is being charged from 0 V to 5 V by the calculated I current. The actual control range SS SS of the soft-start capacitor voltage is between 1.25 V and 4.5 V. Therefore, the soft-start capacitor value must be based on this narrower control range and the required start up time (t ) according to: SS I (cid:2)t C (cid:1) SS SS SS 4.5V(cid:3)1.25V (12) www.ti.com 19

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Note, that t defines a time interval to reach the maximum current capability of the converter and not the time SS required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme does not allow accurate control over the ramp up time of the output voltage. In addition to the I and C values, SS SS the time required to reach the nominal output voltage of the converter is a function of the maximum output current (current limit), the output capacitance of the converter and the actual load conditions. If it is critical to implement a tightly controlled ramp-up time at the output of the converter, the soft-start must be implemented using a closed loop technique. Closed loop soft-start can be implemented with the error amplifier of the voltage regulation loop when its voltage reference is ramped from 0 V to its final steady state value during the required t start up time interval. SS Step 3. VDD Bypass Requirements First, the high-frequency filter capacitor is calculated based on the gate charge parameters of the external MOSFETs. Assuming that the basic switching frequency ripple should be kept below 0.1-V across C , its value HF can be approximated as: Q (cid:4)Q C (cid:1) G(main) G(aux) HF 0.1V (13) The energy storage requirements are defined primarily by the start up time (t ) and turn-on (approximately SS 12.7 V) and turn-off (approximately 8 V) thresholds of the controller’s undervoltage lockout circuit monitoring the VDD voltage at pin 14. In addition, the bias current consumption of the entire primary side control circuit (I DD + I ) must be known. This power consumption can be estimated as: EXT (cid:9) (cid:5) (cid:7) (cid:10) P (cid:1) I (cid:4)I (cid:4) Q (cid:4)Q (cid:2)f (cid:2)V BIAS DD EXT G(main) G(aux) SW DD (14) During start up (t ) this power is provided by C while its voltage must remain above the UVLO turn-off SS BIAS threshold. This relationship can be expressed as: P (cid:2)t (cid:6)1(cid:2)C (cid:2)(cid:5)132(cid:3)8.52(cid:7) BIAS SS 2 BIAS (15) Rearranging the equation yields the minimum value for C : BIAS 2(cid:2)P (cid:2)t CBIAS(cid:11) (cid:5)132B(cid:3)IAS8.52(cid:7)SS (16) Step 4. Delay Programming From the power stage design, the required turn-on delay (t ) of the gate drive signals is defined. The DEL corresponding R resistor value to implement this delay is given by: DEL (cid:5) (cid:7) (cid:1) R (cid:1)T (cid:2)0.91(cid:2)1011(cid:2) DEL DEL1 s (17) or (cid:5) (cid:7) (cid:1) R (cid:1)T (cid:2)0.91(cid:2)1011(cid:2) DEL DEL2 s (18) 20 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE Step 5. Input Voltage Monitoring The input voltage monitoring functions is governed by the following two expressions of the voltage at the LINEUV terminal (pin 15): R V (cid:1)V (cid:2) IN2 atturnon, and LINEUV ON R (cid:4)R IN1 IN2 (19) (cid:5) (cid:7) V (cid:3)V V (cid:1) OFF VON(cid:4)I (cid:2)R atturnoff. LINEUV R HYST IN2 IN1 (20) Since V and V are given by the power supply specification, V equals the 1.27-V threshold of the ON OFF LINEUV line monitor and I is already defined as: HYST V I (cid:1) REF(cid:2) 1 (cid:2)0.05 HYST 2 R DEL (21) the two unknown, R and R are fully determined. Solving the equations results the following two IN1 IN2 expressions for the input voltage divider: (cid:5) (cid:7) V (cid:3)V R (cid:1) ON OFF IN1 I HYST (22) R (cid:1)R (cid:2) 1.27V IN2 IN1 V (cid:3)1.27V ON (23) Similar methods can be used to define the divider components of the overvoltage protection input of the UCC2892 and UCC2894 controllers. Step 6. Current Sense and Slope Compensation The UCC2891 family offers onboard, user programmable slope compensation. The programming of the right amount of slope compensation is accomplished by the appropriate selection of two external resistors, R and F R . SLOPE First, the current sense filter resistor value (R ) must be calculated based on the desired filtering of the current F sense signal. The filter consists of two components, C and R . The C filter capacitor is connected between F F F the CS pin (pin 7) and the GND terminal (pin 6). While the value of C can be freely selected as the first step F of the filter design, it should be minimized to avoid filtering the slope compensation current exiting the CS pin. The recommended range for the filter capacitance is between 50 pF and 270 pF. The value of the filter resistor can be calculated from the filter capacitance and the desired filter corner frequency f . F R (cid:1) 1 F 2(cid:2)(cid:2)f (cid:2)C F F (24) After R is defined R can be calculated. The amount of slope compensation is defined by the stability F SLOPE requirements of the inner peak current loop of the control algorithm and is measured by the number m. When the slope of the applied compensation ramp equals the down slope of the output inductor current waveform (cid:5) (cid:7) reflected across the primary side current sense resistor dV (cid:8)dt , m equals 1. The minimum value of m is 0.5 L to prevent current loop instability. Best current mode performance can be achieved around m=1. The further increase of m moves the control closer to voltage mode control operation. www.ti.com 21

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 APPLICATION INFORMATION: SETUP GUIDE In the UCC289x controllers, slope compensation is implemented by sourcing a linearly increasing current at the CS pin. When this current passes through the current sense filter resistor (R ), it is converted to a slope F (cid:5) (cid:7) (cid:5) (cid:7) compensation ramp which can be characterized by its dV (cid:8)dt . The dV (cid:8)dt of the slope compensation S S current is defined by R according to: SLOPE dIS(cid:1) 5(cid:2)2V dt t (cid:2)R ON SLOPE (25) where (cid:1) 2V is the peak−to−peak ramp amplitude of the internal oscillator waveform (cid:1) 5 is the multiplication factor of the internal current mirror (cid:5) (cid:7) The voltage equivalent of the compensation ramp dV (cid:8)dt can be easily obtained by multiplying with R . After S F (cid:5) (cid:7) introducing the application specific m and dV (cid:8)dt values, the equation can be rearranged for R : L SLOPE 5(cid:2)2V(cid:2)R R (cid:1) (cid:5) F (cid:7) SLOPE dV t (cid:2)m(cid:2) L ON dt (26) 22 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION The UCC2891 family of controllers is dedicated to control current mode active clamp flyback or forward converters in an isolated power supply. The key advantage of the active clamp topologies is the zero voltage switching (ZVS) of the primary side semiconductors. This operating mode reduces the switching losses of the converter, thus facilitates higher switching frequencies or improves efficiency when operated at similar frequencies as its hard switched designs. The simplified schematics below demonstrate the typical implementations of these converters. This active clamp flyback converter shown in Figure 8 highlights a high-side clamp circuit using an N-channel MOSFET transistor as the auxiliary clamp switch. +VIN CCLAMP Load Bootstrap 16 Bias VIN QAUX 14 VDD AUX 12 N−Channel Gate Drive Synchronous Rectifier UCC2893 QMAIN Control OUT 13 CBIAS CIN ROT CS 7 RCS GND FB 9 Secondary−Side 6 Error Amplifier −VIN and Isolation UDG−03153 Figure 8. Zero Voltage Switching Flyback Application +VIN Load Bootstrap 16 Bias CCLAMP VIN 14 VDD P−Channel QAUX Synchronous AUX 12 Rectifier Gate Drive CIN Control UCC2891 QMAIN OUT 13 CBIAS CS 7 ROT RCS GND FB 9 Secondary−Side 6 Error Amplifier −VIN and Isolation UDG−03154 Figure 9. Active Clamp Forward Converter www.ti.com 23

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION Figure 9 shows an active clamp forward converter with high-side clamp utilizing a P-channel auxiliary switch. Detailed analysis and design examples of active clamp converters are published in the references listed at the end of this datasheet. Gate Drive Implementations Both topologies can make use of either the high-side or the low-side clamp arrangement. Depending on the choice of the clamp circuit, the gate drive requirements of the auxiliary switch are different. +VIN 12 +VIN CCLAMP CCLAMP QAUX QAUX QMAIN AUX 12 P QMAIN Figure 10. High-Side N-Channel (UCC2893/4) Figure 11. Low-Side P-Channel (UCC2891/2) Interfacing with a high side N-channel clamp switch is achievable by using high side gate drive integrated circuits or through a gate drive transformer. When a transformer is used, special attention must be paid to the fact that the clamp switch is operated by the complementary waveform of the main power switch. Since the operating duty cycle of the converter can vary between 0 and D , the gate drive transformer must be able to drive the MAX auxiliary switch with any duty cycle from 1−D to near 1. MAX The low side P-channel gate drive circuit involves a level shifter using a capacitor and a diode which ensures that the gate drive amplitude of the auxiliary switch is independent of the actual duty cycle of the converter. Detailed analysis and design examples of these and many similar gate drive solutions are given in reference [6]. Bootstrap Biasing Many converters use a bootstrap circuit to generate its own bias power during steady state operation. The popularity of this solutions is justified by the simplicity and high efficiency of the circuit. Usually, bias power is derived from the main transformer by adding a dedicated, additional winding to the structure. Using a flyback converter as shown in Figure 12, a bootstrap winding provides a quasi-regulated bias voltage for the primary side control circuits. The voltage on the VDD pin is equal to the output voltage times the turns ratio between the output and the bootstrap windings in the transformer. Since the output is regulated, the bias rail is regulated as well. 24 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION While the same arrangement can be used in a forward type converter, the bootstrap winding off the main power transformer would not be able to provide a quasi-regulated voltage. In the forward converter, the voltage across the bootstrap winding equals the input voltage times the turns ratio. Accordingly the bias voltage would vary with the input voltage and most likely would exceed the maximum operating voltage of the control circuits at high line. A linear regulator can be used to limit and regulate the bias voltage if the power dissipation is acceptable. Another possible solution for the forward converter is to generate the bias voltage from the output inductor as shown in Figure 13. Bootstrap Bias 1 +VIN 16 LOAD VIN VDD 14 CIN UCC2891 CBIAS Synchronous Rectifier GND QMAIN Control 6 UDG−03155 −VIN Figure 12. Bootstrap Bias 1, Flyback Example This solution uses the regulated output voltage across the output inductor during the freewheeling period to generate a quasi-regulated bias for the control circuits. Bootstrap Bias 2 +VIN 16 LOAD VIN VDD 14 CIN UCC2891 CBIAS Synchronous GND QMAIN Rectifier 6 Control −VIN UDG−03156 Figure 13. Bootstrap Bias 2, Forward Example www.ti.com 25

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION This solution uses the regulated output voltage across the output inductor during the freewheeling period to generate a quasi-regulated bias for the control circuits. Both of the illustrated solution provides reliable bias power during normal operation. Note that in both cases, the bias voltages are proportional to the output voltage. This nature of the bootstrap bias supply causes the converter to operate in a hiccup mode under significant overload or under short-circuit conditions as the bootstrap winding is not able to hold the bias rail above the undervoltage lockout threshold of the controller. ADDITIONAL APPLICATION INFORMATION References and Additional Development Tools 1. Evaluation Module: UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset. 2. User’s Guide: Using the UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset, (SLUU178) 3. Application Note: Designing for High Efficiency with the UCC2891 Active Clamp PWM Controller, Steve Mappus (SLUA303) 4. Power Supply Design Seminar Topic: Design Considerations for Active Clamp and Reset Technique, D. Dalal, SEM1100−Topic3 (SLUP112) 5. Power Supply Design Seminar Topic: Active Clamp and Reset Technique Enhances Forward Converter Performance, B. Andreycak, SEM1000−Topic 3. (SLUP108) 6. Power Supply Design Seminar Topic: Design and Application Guide for High Speed MOSFET Gate Drive Circuits, L. Balogh, SEM1400−Topic 2 (SLUP169) 7. Datasheet: UCC3580, Single Ended Active-Clamp/Reset PWM Controller, (SLUS292A) 8. Evaluation Module: UCC3580EVM, Flyback Converters, Active Clamp vs. Hard−Switched (SLUU085) 9. Reference Designs: Highly Efficient 100W Isolated Power Supply Reference Design Using UCC3580−1, Texas Instruments Hardware Reference Design Number PMP206−C (SLUU146) 10. Reference Designs: Active Clamp Forward Reference Design using UCC3580−1. Texas Instruments Hardware Reference Design Number PMP368 (SLVR053, SLVR079, SLVR096) Reference Circuit For completeness, the schematic diagram of a complete active clamp forward converter is shown in Figure 14. The detailed description of the circuit operation and design procedure can be found in SLUU178. 26 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 ADDITIONAL APPLICATION INFORMATION + + + + Figure 14. UCC2891 EVM Schematic www.ti.com 27

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS UVLO VOLTAGE THRESHOLDS QUIESCENT CURRENT vs vs JUNCTION TEMPERATURE SUPPLY VOLTAGE 14 2.5 12 V UVLO On s − 2.0 d A ol 10 m Thresh rent − 1.5 e 8 ur oltag UVLO Off ply C V p O 6 u L S 1.0 V − − U UVLO Hysteresis DD O 4 I L UV 0.5 V 2 0 0 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 TJ − Junction Temperature − °C VDD − Supply Voltage − V Figure 15 Figure 16 SUPPLY CURRENT vs REFERENCE VOLTAGE SUPPLY VOLTAGE vs 10 TEMPERATURE UCC2891/UCC2893 10 VIN = 36 V No Load 10 mA Load 0 0 V mA −10 e − − ag −10 nt olt e V urr ce y C −20 ren −20 ppl efe u R − SD −30 JFET Source Current − EF −30 D R I V −40 −40 −50 −50 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 VDD − Supply Voltage − V TJ − Junction Temperature − °C Figure 17 Figure 18 28 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS SOFTSTART CURRENTS LINE UV/OV VOLTAGE THRESHOLD vs vs TEMPERATURE JUNCTION TEMPERATURE 20 1.30 A 15 µs − Softstart Discharge Current 1.28 nt − V urre 10 holds 1.26 start C 5 es oft Thr − S 0 e G) n H Li 1.24 C −5 − S( H S VT /IS) −10 1.22 S(DI S −15 I Softstart Charge Current −20 1.20 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 19 Figure 20 SOFTSTART/SHUTDOWN THRESHOLD VOLTAGE SWITCHING FREQUENCY vs vs JUNCTION TEMPERATURE PROGRAMMING RESISTANCE 0.60 10 M V − e 0.58 g a olt 0.56 V z hold 0.54 y − H 1 M es nc hr 0.52 ue T q own 0.50 g Fre 100 K d n hut 0.48 chi art/S 0.46 Swit st − Soft 0.44 SW 10 K − f TH 0.42 V 0.40 1 K −50 −25 0 25 50 75 100 125 10 100 1000 TJ − Junction Temperature − °C RON = ROFF − Timing Resistance − kΩ Figure 21 Figure 22 www.ti.com 29

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY MAXIMUM DUTY CYCLE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 275 74 RON = ROFF = 75 kΩ RON = ROFF = 75 kΩ 270 73 Hz 265 % cy − k 260 cle − 72 en Cy 71 u 255 y eq ut r D g F 250 m 70 n u hi m witc 245 Maxi 69 − S 240 − X W A 68 fS 235 DM 67 230 225 66 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 23 Figure 24 CURRENT SENSE THRESHOLD VOLTAGE SYNCHRONIZATION THRESHOLD VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 1.4 2.50 V V e − 1.2 UCC2892/UCC2894 e − 2.45 g g a a olt olt d V 1.0 d V 2.40 ol ol h h s s e e 2.35 hr 0.8 hr T T se UCC2891/UCC2893 on 2.30 Sen 0.6 zati urrent 0.4 chroni 2.25 C n − Sy 2.20 S − VC 0.2 NC 2.15 Y S V 0 2.10 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 25 Figure 26 30 www.ti.com

(cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:8)(cid:7) (cid:1)(cid:2)(cid:2)(cid:3)(cid:4)(cid:5)(cid:9) (cid:10) SLUS542F − OCTOBER 2003 − REVISED JULY 2009 TYPICAL CHARACTERISTICS DELAY TIME OUT AND AUX RISE AND FALL TIME vs vs DELAY RESISTANCE JUNCTION TEMPERATURE 25 800 CLOAD = 2 nF Rise Time 700 20 Fall Times − ns 15 Fall Time Time − ns 560000 ttDDEELL12 d y 400 n a e a Del Ris 10 − L 300 − E /t RF tD 200 t 5 100 0 0 0 10 20 30 40 50 60 70 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C RDEL − Delay Resistance − kΩ Figure 27 Figure 28 DELAY TIME DELAY TIME vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 250 800 RDEL = 10 kΩ RDEL = 50 kΩ 700 200 600 me − ns 150 OUT to AUX µme − s 500 AUX to OUT Ti Ti OUT to AUX Delay Delay 400 − 100 − L L 300 E E D D t t 200 50 AUX to OUT 100 0 0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 29 Figure 30 www.ti.com 31

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2891D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2891 & no Sb/Br) UCC2891DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2891 & no Sb/Br) UCC2891DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2891 & no Sb/Br) UCC2891DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2891 & no Sb/Br) UCC2891PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2891 & no Sb/Br) UCC2891PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2891 & no Sb/Br) UCC2892D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2892 & no Sb/Br) UCC2892DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2892 & no Sb/Br) UCC2892PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 UCC2892 & no Sb/Br) UCC2893D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2893 & no Sb/Br) UCC2893DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2893 & no Sb/Br) UCC2893PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 UCC2893 & no Sb/Br) UCC2893PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 UCC2893 & no Sb/Br) UCC2893PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 UCC2893 & no Sb/Br) UCC2894D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2894 & no Sb/Br) UCC2894DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2894 & no Sb/Br) UCC2894DRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2894 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2894PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2894 & no Sb/Br) UCC2894PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2894 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC2891DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2891PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC2892DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2893DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2893PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC2894DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2894PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC2891DR SOIC D 16 2500 333.2 345.9 28.6 UCC2891PWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2892DR SOIC D 16 2500 333.2 345.9 28.6 UCC2893DR SOIC D 16 2500 333.2 345.9 28.6 UCC2893PWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2894DR SOIC D 16 2500 333.2 345.9 28.6 UCC2894PWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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