UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 (cid:1) Precision Negative Series Pass Voltage DP PACKAGE (FRONT VIEW) Regulation (cid:1) 0.2 V Dropout at 0.5 A VOUTS 1 8 SD/CT (cid:1) Wide Input Voltage Range –3.2 V to –15 V (cid:1) Low Quiescent Current Irrespective of Load VIN 2 7 VIN (cid:1) Simple Logic Shutdown Interfacing (cid:1) VIN 3 6 VIN –5 V, –12 V, and Adjustable Output (cid:1) 2.5% Duty Cycle Short Circuit Protection GND 4 5 VOUT description The UCC384-x family of negative linear-series pass regulators is tailored for low-dropout applications where low-quiescent power is important. Fabricated with a BCDMOS technology ideally suited for low input-to-output differential applications, the UCC384-x passes 0.5 A while requiring only 0.2 V of input-voltage headroom. Dropout voltage decreases linearly with output current, so that dropout at 50 mA is less than 20 mV. Quiescent current consumption for the device under normal (non-dropout) conditions is typically 200 µA. An integrated charge pump is internally enabled only when the device is operating near dropout with low VIN. This ensured that the device meets the dropout specifications even for maximum load current and a VIN of –3.2 V with only a modest increase in quiescent current. Quiescent current is always less than 350 µA, with the charge pump enabled. The quiescent current of the UCC384 does not increase with load current. Short-circuit current is internally limited. The device responds to a sustained overcurrent condition by turning off after a t delay. The device then stays off for a period, t , that is 40 times the t delay. The device then ON OFF ON begins pulsing on and off at the t /t duty cycle of 2.5%. This drastically reduces the power dissipation during ON OFF short circuit such that heat sinking, if at all required, must only accommodate normal operation. An external capacitor sets the on time. The off time is always 40 times t . ON The UCCx84-x can be shutdown to 45 µA (maximum) by pulling the SD/CT pin more positive than –0.7 V. To allow for simpler interfacing, the SD/CT pin may be pulled up to 6 V above the ground pin without turning on clamping diodes. Internal power dissipation is further controlled with thermal-overload protection circuitry. Thermal shutdown occurs if the junction temperature exceeds 140°C. The chip remains off until the temperature has dropped 20°C (T = 120°C). J AVAILABLE OPTIONS OUTPUT VOLTAGE (V) PACKAGE DEVICES TTAA TYP (SOIC) DP –5 UCC284DP–5 –4400°CC ttoo 8855°CC –12 UCC284DP–12 ADJ UCC284DP–ADJ –5 UCC384DP–5 0°C to 70°C –12 UCC384DP–12 ADJ UCC384DP–ADJ †All package types are available taped and reeled. Add TR suffix to device type (e.g. UCC284DP–5TR) to order quantities of 3000 devices per reel. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2000, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 functional block diagram (+) 4 GND 1– µA R1 R2 DISCHARGE UCC384–ADJ 0 OPEN + –2.2 V SHUTDOWN UCC384–5 375K 125K –0.7 V 1.25 V R2 50 k UCC384–12 375K 43.6K + –1.6 V S Q TON SD/CT 8 TOFF R Q VPUMP –2.6 V + + R1 GM 40µA CHARGE 1 VOUTS OVERCURRENT 700 mA + VIN 2 THERMAL SHUTDOWN VIN 3 VIN 6 UVLO VIN 7 5 VOUT (–) (–) UDG–99030 (cid:1)(cid:2) absolute maximum ratings over operating free-air temperature (unless otherwise noted) Input voltage range‡, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –16 V IN Shutdown voltage range, SD/CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 6 V Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C J Storage temperature range T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg Lead temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 electrical characteristics T = 0°C to 70°C for the UCC384 and –40°C to 85°C for the UCC284, A VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For UCC384–ADJ, VOUT is set to –3.3V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UCC384–5 Fixed –5-V 0.5-A Regulation Section TA = 25°C –5.075 –5 –4.925 V OOuuttppuutt vvoollttaaggee Over all conditions –5.100 –4.850 V Line regulation VIN = –5.2 V to –15 V 1.5 10 mV Load regulation IOUT = 0 mA to 0.5 A 0.1 0.25 % Output noise voltage TA = 25°C, BW = 10 Hz to 10 kHz 200 µVRMS IOUT 0.5 A, VOUT = –4.8 V 0.20 0.50 V DDrrooppoouutt vvoollttaaggee, VVOOUUTT – VVIINN IOUT 50 mA, VOUT = –4.8 V 20 50 mV UCC384–5 Fixed –5-V 0.5-A Power Supply Section Input voltage range –15 –5.2 V Quiescent current charge pump on VIN = –4.85 V, See Note 1 280 350 µA Quiescent current VIN = –15 V 200 250 µA VIN = –13 V, SD/CT = 0 V TA = 0°C to 85°C, See Note 2 15 45 µA QQuuiieesscceenntt ccuurrrreenntt iinn sshhuuttddoowwnn VIN = –13 V, SD/CT = 0 V TA = –40°C to 0°C, See Note 2 100 µA Shutdown threshold At shutdown pin (SD/CT) –1.0 –0.7 –0.4 V Shutdown input current SD/CT = 0 V 5 10 25 µA VIN = –15 V, VOUT = 0 V, Output leakage in shutdown 1 50 µA See Note 3 Overtemperature shutdown 140 °C Overtemperature hysteresis 20 °C UCC384–5 Fixed –5-V 0.5-A Current Limit Section Peak current limit VOUT = 0 V 0.7 1.1 1.5 A Overcurrent threshold 0.55 0.7 0.9 A Current limit duty cycle VOUT = 0 V 2.5 4 % Overcurrent time out, tON VOUT = 0 V 300 500 700 µs UCC384–12 Fixed 12-V 0.5-A Regulation Section TA = 25°C –12.18 –12 –11.82 V OOuuttppuutt vvoollttaaggee Over all conditions –12.24 –11.64 V Line regulation VIN = –12.5 V to –15 V 5 15 mV Load regulation IOUT= 0 mA to 0.5 A 0.1 0.3 % Output noise voltage TA = 25°C BW = 10 Hz to 10 kHz 200 µVRMS IOUT 0.5 A, VOUT = –11.6 V 0.15 0.5 V DDrrooppoouutt vvoollttaaggee, VVOOUUTT – VVIINN IOUT 50 mA, VOUT = –11.6 V 15 50 mV UCC384–12 Fixed –12 V-0.5-A Power Supply Section Input voltage range –15 –12.5 V Quiescent current VIN = –15 V 220 350 µA VIN = –13 V, SD/CT = 0 V TA = 0°C to 85°C, See Note 2 15 45 µA QQuuiieesscceenntt ccuurrrreenntt iinn sshhuuttddoowwnn VIN = –13 V, SD/CT = 0 V TA = –40°C to 0°C, See Note 2 100 µA NOTES: 1. The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required, it is disabled, which lowers overall device power consumption. 2. Ensured by design. Not production tested. 3. In the application during shutdown mode, output leakage current adds to quiescent current. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 electrical characteristics T = 0°C to 70°C for the UCC384 and –40°C to 85°C for the UCC284, A VIN = VOUT – 1.5 V, IOUT = 0 mA, COUT = 4.7 µF, and CT = 0.015 µF. For UCC384–ADJ, VOUT is set to –3.3V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UCC384–12 Fixed –12 V-0.5-A Power Supply Section (continued) Shutdown threshold At shutdown pin (SD/CT) –1.0 –0.7 –0.4 V Shutdown input current SD/CT = 0 V 5 10 25 µA VIN = –15 V, VOUT = 0 V, Output leakage in shutdown 1 50 µA See Note 3 Overtemperature shutdown 140 °C Overtemperature hysteresis 20 °C UCC384–12 Fixed –12-V 0.5-A Current Limit Section Peak current limit VOUT = 0 V 0.7 1.1 1.5 A Overcurrent threshold 0.55 0.7 0.9 A Current limit duty cycle VOUT = 0 V 2.5 4 % Overcurrent time out, tON VOUT = 0 V 300 500 700 µs UCC384–ADJ Adjustable 0.5-A Regulation Section TA = 25°C –1.27 –1.25 –1.23 V RReeffeerreennccee vvoollttaaggee Over temperature –1.275 –1.215 V Line regulation VIN = –3.5 V to –15 V, VOUT = VOUTS 0.5 3 mV Load regulation IOUT = 0 mA to 0.5 A 0.1 0.18 % Output noise voltage BW = 10 Hz to 10 kHz, TA = 25°C 200 µVRMS IOUT 0.5 A, VOUT = –3.15 V 0.25 0.5 V DDrrooppoouutt vvoollttaaggee, VVOOUUTT – VVIINN IOUT 50 mA, VOUT = –3.15 V 25 50 mV Sense pin input current 100 250 nA UCC384–ADJ Adjustable 0.5-A Power Supply Section Input voltage range –15 –3.5 V Undervoltage lockout –3.2 –2.95 –2.7 V Quiescent current charge pump on VIN = –3.15 V, See Note 1 200 350 µA Quiescent current VIN = –15 V 200 250 µA VIN = –13 V, SD/CT = 0 V TA = 0°C to 85°C, See Note 2 15 45 µA QQuuiieesscceenntt ccuurrrreenntt iinn sshhuuttddoowwnn VIN = –13 V, SD/CT = 0 V TA = –40°C to 0°C, See Note 2 100 µA Shutdown threshold At shutdown pin (SD/CT) –1.0 –0.7 –0.4 V Shutdown input current SD/CT = 0V 5 10 25 µA VIN = –15V, VOUT = 0 V, Output leakage in shutdown 1 50 µA See Note 3 Overtemperature shutdown 140 °C Overtemperature hysteresis 20 °C UCC384–ADJ Adjustable 0.5-A Current Limit Section Peak current limit VOUT = 0 V 0.7 1.1 1.5 A Overcurrent threshold 0.55 0.7 0.9 A Current limit duty cycle VOUT = 0 V 2.5 4 % Overcurrent time out, tON VOUT = 0 V 300 500 700 µs NOTES: 1. The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required, it is disabled, which lowers overall device power consumption. 2. Ensured by design. Not production tested. 3. In the application during shutdown mode, output leakage current adds to quiescent current. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 pin descriptions GND: This is the low noise ground reference input. All voltages are measured with respect to the GND pin. SD/CT: This is the shutdown pin and also the short-circuit timing pin. Pulling this pin more positive than –0.7 V puts the circuit in a low-current shutdown mode. Placing a timing capacitor between this pin and GND sets the short-circuit charging time, t during an overcurrent condition. During an overcurrent condition, the output ON pulses at approximately a 2.5% duty cycle. NOTE:The CT capacitor must be connected between this pin and GND, not VIN, to assure that the SD/CT pin is not pulled significantly negative during power-up. This pin should not be externally driven more negative than –5 V or the device will be damaged. VIN: This is the negative input supply. Bypass this pin to GND with at least 1 µF of low ESR or ESL capacitance. VOUT: Regulated negative-output voltage. A single 4.7-µF capacitor should be connected between this pin and GND. Smaller value capacitors can be used for light loads, but this degrades the load-step performance of the regulator. VOUTS: This is the feedback pin for sensing the output of the regulator. For the UCC384-5 and UCC384-12 versions, VOUTS can be connected directly to VOUT. If the load is placed at a considerable distance from the regulator, the VOUTS lead can be used as a Kelvin connection to minimize errors due to lead resistance. Connecting VOUTS at the load moves the resistance of the VOUT wire into the control loop of the regulator, thereby effectively canceling the IR drop associated with the load path. APPLICATION INFORMATION overview The UCCx84-x family of negative low-dropout linear (LDO) regulators provides a regulated-output voltage for applications with up to 0.5 A of load current. The regulators feature a low-dropout voltage and short-circuit protection, making their use ideal for demanding applications requiring fault protection. programming the output voltage on the UCC384 The UCC384-5 and UCC384-12 have output voltages that are fixed at –5 V and –12 V respectively. Connecting VOUTS to VOUT gives the proper output voltage with respect to ground. The UCC384-ADJ can be programmed for any output voltage between –1.25 V and –15 V. This is easily accomplished with the addition of an external resistor divider connected between GND and VOUT with VOUTS connected to the center tap of the divider. For an output of –1.25 V, no resistors are needed and VOUTS is connected directly to VOUT. The regulator-input voltage cannot be more positive than the UVLO threshold, or approximately –3 V. Thus, low dropout cannot be achieved when programming the output voltage more positive than approximately –3.3 V. A typical application circuit is shown in Figure 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION programming the output voltage on the UCC384 (continued) (+) (+) CT 0.015µF 4 R2 VOUT GND + 8 SD/CT VOUTS 1 COUT CIN 4.7µF + 1µF C1 R1 VIN UCC384–ADJ VOUT 5 (–) VIN VIN VIN VIN 2 3 6 7 (–) UDG–99029 Figure 1. Typical Application Circuit For the UCC384–ADJ, the output voltage is programmed by the following equation: (cid:4) (cid:6) VOUT(cid:1)(cid:2)1.25(cid:3) 1(cid:5)R1 (1) R2 When R1 or R2 are selected to be greater than about 100 kΩ, a small ceramic capacitor should be placed across R1 to cancel the input pole created by R1 and the parasitic capacitance appearing on VOUTS. Values of approximately 20 pF should be adequate. dropout performance The UCC384 is tailored for low-dropout applications where low-quiescent power is important. Fabricated with a BCDMOS technology ideally suited for low input-to-output differential applications, the UCC384 passes 0.5 A while requiring only 0.2 V of headroom. The dropout voltage is dependent on operating conditions such as load current, input and load voltages, and temperature. The UCC384 achieves a low R (on) through the use of an DS internal charge-pump that drives the MOSFET gate. Figure 2 shows typical dropout voltages versus output voltage for the UCC384-5 V and -12 V versions as well as the UCC384–ADJ version programmed between –3.3 V and –15 V. Since the dropout voltage is also affected by output current, Figure 3 shows typical dropout voltages versus load current for different values of VOUT. Operating temperatures also affect the R (on) and the dropout voltage of the UCC384. Figure 4 shows typical DS dropout voltages for the UCC384 over temperature under a full load of 0.5 A. short-circuit protection The UCC384 provides unique short-circuit protection circuitry that reduces power dissipation during a fault. When an overcurrent condition is detected, the device enters a pulsed mode of operation, limiting the output to a 2.5% duty cycle. This reduces the heat sink requirements during a fault. The operation of the UCC384 during an overcurrent condition is shown in Figure 5. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION short-circuit protection (continued) DROPOUT VOLTAGE DROPOUT VOLTAGE vs vs LOAD CURRENT OUTPUT VOLTAGE 0.30 0.25 V = –5 V OUT V V 0.25 IOUT = 0.3 A e – 0.20 VOUT = –3.3 V – g Voltage 0.20 IOUT = 0.4 A IOUT = 0.5 A out Volta 0.15 ut op o 0.15 r p D – Dro ) – UT 0.10 –V) NOUT 00..0150 I = 0.2 A (V–VINO 0.05 V = –15 VVOUT = –12 V VI OUT OUT ( I = 0.1 A OUT 0.00 3 6 9 12 15 0.05 0.15 0.25 0.35 0.45 V – Output Voltage – V I – Load Current – A OUT OUT Figure 2 Figure 3 DROPOUT VOLTAGE vs TEMPERATURE 0.40 0.35 V = –3.3 V V OUT – e 0.30 g V = –5 V a OUT olt V 0.25 ut o rop 0.20 VOUT = –12 V D – ) T 0.15 U O V 0.10 – N V = –15 V VI OUT ( 0.05 0 –50 –25 0 25 50 75 100 T – Free-Air Temperature – (cid:3)C A Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION tOFF tOFF t t t ON ON ON IOUT=0A ~40 x tON ~40 x tON IOUT (NOM) IOVER IPEAK NOTE: CURRENT FLOW IS INTO THE DEVICE VOUT = 0V VOUT =(IPEAK)(RL) VOUT NOM. (–V) CT = 0V CT (NOM) = – 1.6V CT = – 2.6V UDG–99031 Figure 5. Short Circuit Timing UCC384 short circuit timing During normal operation the output voltage is in regulation and the SD/CT pin is held to –1.5 V via a 50-kΩ internal-source impedance. If the output-current rises above the overcurrent threshold, the CT capacitor is charged by a 40-µA current sink. The voltage on the SD/CT pin moves in a negative direction with respect to GND. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION UCC384 short-circuit timing (continued) During an overcurrent condition, the regulator actively limits the maximum output current to the peak-current limit. This limits the output voltage of the regulator to: V (cid:1)I (cid:3)R (1) OUT PEAK L If the output current stays above the overcurrent threshold, the voltage on the SD/CT pin reaches –2.6 V with respect to GND and the output turns off. The CT capacitor is then discharged by a 1-µA current source. When the voltage on the SD/CT pin reaches –1.6 V with respect to GND, the output turns back on. This process repeats until the output current falls below the overcurrent threshold. t , the time the output is on during an overcurrent condition is determined by the following equation: ON t (cid:1)CT((cid:1)F)(cid:3) 1V seconds (2) ON 40(cid:1)A t , the time the output is off during an overcurrent condition is determined by the following equation: OFF t (cid:1)CT((cid:1)F)(cid:3) 1V seconds (3) OFF 1(cid:1)A capacitive loads A capacitive load on the regulator’s output appears as a short-circuit during start-up. If the capacitance is too large, the output voltage does not begin to regulate during the initial t period and the UCC384 enters a pulsed ON mode operation. For a constant current load the maximum allowed output capacitance is calculated as follows: (cid:7) (cid:8) t (sec) C (cid:1) I (A)(cid:2)I (A) (cid:3) ON Farads (4) OUT(max) PEAK LOAD V (V) OUT For worst case calculations, the minimum value for t should be used, which is based on the value of CT ON capacitor selected. For a resistive load the maximum output capacitor can be estimated as follows: t (sec) C (cid:1) ON Farads (5) OUT(max) (cid:11) (cid:13) (cid:10) (cid:10) (cid:10) (cid:10) R ((cid:2))(cid:3)(cid:9)n(cid:10) (cid:4) 1 (cid:6)(cid:10) LOAD V (V) OUT (cid:12)1(cid:2) I (A)(cid:3)R ((cid:2)) (cid:14) MAX LOAD Figure 6 and Figure 7 are oscilloscope photos of the UCC384–ADJ operating during an overcurrent condition. Figure 6 shows operation of the circuit as the output current initially rises above the overcurrent threshold. This is shown on a 1ms/div. scale. Figure 7 shows operation of the same circuit on a 25 ms/div. scale showing one complete cycle of operation during an overcurrent condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION UCC384–ADJ UCC384–ADJ OVERCURRENT CONDITION OPERATION OVERCURRENT CONDITION OPERATION 1 ms/div 25 ms/div Figure 6 Figure 7 shutdown feature of the UCC384 The shutdown feature of the UCC384 allows the device to be placed in a low quiescent current mode. The UCC384 is shut down by pulling the SD/CT pin more positive than –0.7 V with respect to GND. Figure 8 shows how a shutdown circuit can be configured for the UCC384 using a standard transistor-transistor logic signal to control it. TTL SHUTDOWN CIRCUIT +5 V +5 V 470 k LOGIC INPUT GND (+) (+) 0.015µF CT 4 R2 GND VOUT + 8 SD/CT 1 COUT VOUTS 4.7µF + CIN C1 R1 VIN UCC384–ADJ 1µF 5 (–) VOUT VIN VIN VIN VIN 2 3 6 7 (–) UDG–99032 Figure 8. TTL Controlled Shutdown Circuit for the UCC384 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION controlling the SD/CT pin Forcing the SD/CT pin to any fixed voltage affects the operation of the circuit. As mentioned before, pulling the SD/CT pin more positive than –0.7 V puts the circuit in a shutdown mode, limiting the quiescent current to less than 45 µA. Pulling this pin more positive than 6 V with respect to GND damages the device. Forcing the SD/CT pin to any fixed voltage between –0.7 V and –1.6 V with respect to GND enables the output. However, in an overcurrent condition, the output does not pulse at a 2.5% duty cycle, but the output current is still limited to the peak current limit. This circuit may be used where a fixed current limit is needed, where a 2.5% duty cycle is undesirable. The UCC384 supplies a maximum current in this configuration as long as the temperature of the device does not exceed the overtemperature shutdown. This is determined by the peak current being supplied, the input and output voltages, and the type of heat sink being used. Thermal design is discussed later on in this data sheet. Forcing the SD/CT pin to a voltage level between approximately –1.6 V and –2.6 V with respect to GND is not recommended as the output may or may not be enabled. Forcing the SD/CT pin to a voltage level between approximately –2.6 V and –5 V with respect to GND turns the output off completely. The output remains off as long as the voltage is applied. Pulling this pin more negative than –5 V with respect to GND damages the device (see Table 1). Table 1 SD/CT Voltage Levels SD/CT STATE 6 V to –0.7 V Output disabled and device in low quiescent shutdown mode. –0.7 V to –1.6 V Output enabled –1.6 V to –2.6 V Output enabled or disabled depending on the previous state. –2.6 V to –5 V Output disabled VIN TO VOUT DELAY TIME DURING POWER-UP WITH CT = 0.22 µF Figure 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION VIN to VOUT Delay During power-up there is a delay between VIN and VOUT. The majority of this delay time is due to the charging time of the CT capacitor. When VIN moves more negative than the UVLO of the device with respect to GND, the CT capacitor begins to charge. A 17-µA current sink is used only during power up to charge the CT capacitor. When the voltage on the SD/CT pin reaches approximately –1.6 V with respect to GND, the output turns on and regulates. The larger the value of the CT capacitor, the greater the delay time between VIN and VOUT. Figure 9 shows the VIN to VOUT start-up delay, approximately 16 ms for a circuit with CT = 0.22 µF. Shorter delay times can be achieved with a smaller CT capacitor. The problem with a smaller CT capacitor is that with a very large load, the circuit may stay in overcurrent mode and never turn on. A circuit with a large capacitive load needs a large CT capacitor to operate properly. One way to shorten the delay from VIN to VOUT during powerup, is with the use of the quick start-up circuit shown in Figure 10. (+) (+) CT 4 R2 0.22µF GND + 8 SD/CT VOUTS 1 COUT VOUT 4.7µF VIN + CIN C1 R4 R1 1µF C2 18 k UCC384–ADJ 0.1µF VOUT 5 (–) Q1 2N7000 VIN VIN VIN VIN R3 2 3 6 7 12 k (–) QUICK START CURRENT UDG–99033 Figure 10. Quick Start-Up Circuit for UCC384 With the quick start-up circuit, the delay time between VIN and VOUT during start-up can be reduced dramatically. Figure 11 shows that with the quick start-up circuit, the VIN to VOUT delay time has been reduced to approximately 1 ms. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION VIN to VOUT Delay VIN TO VOUT DELAY TIME VIN TO VOUT DELAY TIME WITH QUICK START-UP CIRCUIT WITH CT CAPACITOR REMOVED Figure 11 Figure 12 operation of the quick start-up circuit During normal start-up, the UCC384 does not turn on until the voltage on the SD/CT pin reaches approximately –1.6 V with respect to ground. It takes a certain amount of time for the CT capacitor to charge to this point. For a circuit that has a very large load, the CT capacitor needs to be large in order for the overcurrent timing to work properly. A large value of capacitance on the SD/CT pin increases the VIN to VOUT delay time. The quick start-up circuit uses Q1 to quickly pull the SD/CT pin in a negative direction during start-up, thus decreasing the VIN-to-VOUT delay time. When VIN is applied to the circuit, Q1 turns on and starts to charge the CT capacitor. The current pulled through R4 determines the rate at which CT is charged. R4 can be calculated as follows: V (V)(cid:3)T seconds R4(cid:1) IN D ohms (6) 1.6(cid:3)CT(F) t is the approximate VIN-to-VOUT delay time desired. D Q1 needs to be turned off after a fixed time to prevent the SD/CT pin from going too far negative with respect to GND. If the SD/CT pin is allowed to go too far negative with respect to GND, the output turns off again or possibly even damages the SD/CT pin. The maximum amount of time that Q1 should be allowed to be on is referred to as t and can be calculated as follows: M t (cid:1)2.6(cid:3)t seconds (7) M 1.6 D R3 along with C2 set the time that Q1 is allowed to be on. Since t is the maximum amount of time that Q1 should M be allowed to stay on, an added safety margin may be to use 0.9 × t instead. This ensures that Q1 is turned M off in the proper amount of time. With a chosen value for C2, R3 can be calculated as follows: POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002 APPLICATION INFORMATION operation of the quick start-up circuit (continued) 0.9(cid:3)t seconds R3(cid:1) (cid:4)M (cid:6) Ohms (8) V (V)(cid:2)1.6 C2(F)(cid:3)(cid:9)n 1(cid:2) IN V (V) IN After the CT capacitor has charged up for a time equal to 0.9 ×t , Q1 turns off and allows the SD/CT pin to M be pulled back to –1.5 V with respect to GND through a 50-kΩ resistor. At this point , the SD/CT pin can be used by the UCC384 overcurrent timing control. minimum VIN to VOUT delay time Although it may desirable to have as short a delay time as possible, a small portion of this delay time is fixed by the UCC384 and cannot be shortened. This is shown in Figure 12, where the CT capacitor has been removed from the circuit completely, giving a fixed VIN to VOUT delay of approximately 150 µs for a circuit with VIN = –6 V and VOUT = –5 V. thermal design The Packaging Information section of the Power Supply Control Products Data Book (TI Literature No. SLUD003) contains reference material for the thermal ratings of various packages. The section also includes an excellent article entitled Thermal Characteristics of Surface Mount Packages, which is the basis for the following discussion. Thermal design for the UCC384 includes two modes of operation, normal and pulsed. In normal mode, the linear regulator and heat sink must dissipate power equal to the maximum forward voltage drop multiplied by the maximum load current. Assuming a constant current load, the expected heat rise at the regulator’s junction can be calculated as follows: t (cid:1)P (cid:3)((cid:3)jc(cid:5)(cid:3)ca) (9) RISE DISS Theta (θ) is the thermal resistance and PDISS is the power dissipated. The junction-to-case thermal resistance (θjc) of the SOIC–8 DP package is 22°C/W. In order to prevent the regulator from going into thermal shutdown, the case-to-ambient thermal resistance (θca) must keep the junction temperature below 150°C. If the UCC384 is mounted on a 5 square inch pad of 1-ounce copper, for example, the thermal resistance (θja) becomes 40–70°C/W. If a lower thermal resistance is required for the application, the device heat sinking needs to be improved. When the UCC384 is in a pulsed mode, due to an overcurrent condition, the maximum average power dissipation is calculated as follows: (cid:4) (cid:6) (cid:7) (cid:8) t (seconds) P (cid:1) V (V)(cid:2)V (V) (cid:3)I (A)(cid:3) ON Watts (10) avg IN OUT PEAK 40(cid:3)t (seconds) ON As seen in equation (10), the average power during a fault is reduced dramatically by the duty cycle, allowing the heat sink to be sized for normal operation. Although the peak power in the regulator during the t period ON can be significant, the thermal mass of the package normally keeps the junction temperature from rising unless the t period is increased to several milliseconds. ON 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty UCC284DP-12 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DP-12G4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DP-5 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DP-5G4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DP-ADJ ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DP-ADJG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DPTR-5 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DPTR-5G4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DPTR-ADJ ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC284DPTR-ADJG4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DP-12 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DP-12G4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DP-5 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DP-5G4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DP-ADJ ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DP-ADJG4 ACTIVE SOIC D 8 75 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DPTR-12 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DPTR-12G4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DPTR-5 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DPTR-5G4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DPTR-ADJ ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) UCC384DPTR-ADJG4 ACTIVE SOIC D 8 2500 Green(RoHS& CUNIPDAU Level-2-260C-1YEAR noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. Addendum-Page1

PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) UCC284DPTR-5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC284DPTR-ADJ SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC384DPTR-12 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC384DPTR-5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC384DPTR-ADJ SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC284DPTR-5 SOIC D 8 2500 346.0 346.0 29.0 UCC284DPTR-ADJ SOIC D 8 2500 346.0 346.0 29.0 UCC384DPTR-12 SOIC D 8 2500 346.0 346.0 29.0 UCC384DPTR-5 SOIC D 8 2500 346.0 346.0 29.0 UCC384DPTR-ADJ SOIC D 8 2500 346.0 346.0 29.0 PackMaterials-Page2

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