Product Order Technical Tools & Support & Folder Now Documents Software Community UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 UCC2822x Interleaved Dual PWM Controller With Programmable Max Duty Cycle 1 Features 3 Description • 2-MHzHigh-FrequencyOscillatorWith1-MHz The UCC28220 and UCC28221 are a family of 1 BiCMOS interleaved dual channel PWM controllers. OperationPerChannel Peak current mode control is used to ensure current • MatchedInternalSlopeCompensationCircuits sharing between the two channels. A precise • ProgrammableMaximumDutyCycleClamp60% maximum duty cycle clamp can be set to any value to90%PerChannel between60%and90%dutycycleperchannel. • PeakCurrentModeControlWithCycle-by-Cycle The UCC28220 has an UVLO turnon threshold of CurrentLimit 10 V for use in 12-V supplies while UCC28221 has a • CurrentSenseDischargeTransistorforImproved turnon threshold of 13 V for systems needing wider NoiseImmunity UVLOhysteresis.Bothhave8-Vturnoffthresholds. • AccurateLineUndervoltageandOvervoltage Additional features include a programmable internal SenseWithProgrammableHysteresis slope compensation with a special circuit which is used to ensure exactly the same slope is added to • Opto-CouplerInterface each channel and a high-voltage 110-V internal JFET • 110-VInternalStart-UpJFET(UCC28221) for easier start-up for the wider hysteresis UCC28221 • OperatesFrom12-VSupply(UCC28220) version. • ProgrammableSoftStart The UCC28220 is available in both 16-pin SOIC and low-profile TSSOP packages. The UCC28221 also 2 Applications comes in 16-pin SOIC package and a slightly larger 20-pin TSSOP package to allow for high-voltage pin • HighOutputCurrent(50-Ato100-A)Converters spacing to meet UL1950 creepage clearance safety • MaximumPowerDensityDesigns requirements. • High-Efficiency48-VInputWithLowOutputRipple Converters DeviceInformation(1) • High-PowerOffline,Telecom,andDatacom PARTNUMBER PACKAGE BODYSIZE(NOM) PowerSupplies UCC28220, SOIC(16) 9.00mm×3.90mm UCC28221 TSSOP(16) 5.00mm×4.40mm UCC28221 TSSOP(20) 6.50mm×4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. TypicalApplication VIN (+48V) CS1 1 LINEOV VIN16 2 LINE LINEUV15 HYS Bias 3 VDD REF14 VOUT 1/2UCC27324 4 CS1 OUT113 5 SLOPE OUT212 CS2 6 CS2 GND11 7 SS CHG10 REF 8 CTRL DISCHG 9 1/2UCC27324 E/A Copyright © 2016,Texas Instruments Incorporated Pin16isanoconnect(NC)onUCC28220whichdoesnotincludetheJFEToption. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................13 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 17 3 Description............................................................. 1 9.1 ApplicationInformation............................................17 4 RevisionHistory..................................................... 2 9.2 TypicalApplication..................................................17 5 DeviceComparisonTable..................................... 3 10 PowerSupplyRecommendations..................... 19 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 20 11.1 LayoutGuidelines.................................................20 7 Specifications......................................................... 5 11.2 LayoutExample....................................................20 7.1 AbsoluteMaximumRatings......................................5 12 DeviceandDocumentationSupport................. 21 7.2 ESDRatings..............................................................5 7.3 RecommendedOperatingConditions.......................5 12.1 DocumentationSupport........................................21 7.4 ThermalInformation..................................................5 12.2 RelatedLinks........................................................21 7.5 ElectricalCharacteristics...........................................6 12.3 ReceivingNotificationofDocumentationUpdates21 7.6 TypicalCharacteristics..............................................8 12.4 CommunityResources..........................................21 12.5 Trademarks...........................................................21 8 DetailedDescription............................................ 11 12.6 ElectrostaticDischargeCaution............................21 8.1 Overview.................................................................11 12.7 Glossary................................................................22 8.2 FunctionalBlockDiagram.......................................11 13 Mechanical,Packaging,andOrderable 8.3 FeatureDescription.................................................12 Information........................................................... 22 4 Revision History ChangesfromRevisionF(September2016)toRevisionG Page • DeletedControlLoopCompensationsection. ..................................................................................................................... 19 • DeletedCurrentLoopsection............................................................................................................................................... 19 • DeletedVoltageLoop(T )section..................................................................................................................................... 19 V(s) ChangesfromRevisionE(March2009)toRevisionF Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedOrderingInformationtable;seePOAattheendofthedatasheet........................................................................... 3 • AddedThermalInformationtable........................................................................................................................................... 5 2 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 5 Device Comparison Table DEVICE DESCRIPTION PACKAGEOPTION UCC2732x Dual4-AHighSpeedLowSideMOSFETDrivers SOIC(8),PowerPADMSOP(8),PDIP(8) UCC2742x Dual4-AHighSpeedLowSideMOSFETDriverswithEnable SOIC(8),PowerPADMSOP(8),PDIP(8) TPS281x Dual2.4-AHighSpeedLowSideMOSFETDrivers SOIC(8),TSSOP(8),PDIP(8) UC371x Dual2.4-AHighSpeedLowSideMOSFETDrivers SOIC(8),PowerSOIC(14),PDIP(8) 6 Pin Configuration and Functions DorPWPackage 16-PinSOICorTSSOP PWPackage TopView 20-PinTSSOP TopView VIN (for UCC28221) LINEOV 11 186 NC (for UCC28220) NC 11 280 VIN LINEHYS 22 175 LINEUV LINEOV 22 179 NC VDD 33 164 REF LINEHYS 33 168 LINEUV CS1 444 1553 OUT1 VDD 444 1557 REF SLOPE 52 172 OUT2 CS1 52 176 OUT1 CS2 36 161 GND SLOPE 36 165 OUT2 SS 74 1550 CHG CS2 74 1554 GND CTRL 84 59 DISCHG SS 884 1593 CHG CTRL 94 1552 DISCHG NC 140 151 NC PinFunctions PIN SOIC, I/O DESCRIPTION NAME TSSOP(20) TSSOP(16) Setsoscillatorchargecurrent:AresistorfromthispintoGNDsetsupthe chargingcurrentoftheinternalC capacitorusedintheoscillator.Thisresistor, T CHG 10 13 I inconjunctionwiththeresistorontheDISCHGpinisusedtosetupthe operatingfrequencyandmaximumdutycycle.Undernormaloperationthedc voltageonthispinis2.5V. Channel1currentsenseinput:These2pinsarethecurrentsenseinputstothe device.Thesignalsareinternallylevelshiftedby0.5Vbeforethesignalgetsto thePWMcomparator.Internallytheslopecompensationrampisaddedtothis CS1 4 5 I signal.Thelinearoperatingrangeonthisinputis0to1.5V.Also,thispingets pulledtogroundeachtimeitsrespectiveoutputgoeslow(thatis:OUT1and OUT2). Channel2currentsenseinput:These2pinsarethecurrentsenseinputstothe device.Thesignalsareinternallylevelshiftedby0.5Vbeforethesignalgetsto thePWMcomparator.Internallytheslopecompensationrampisaddedtothis CS2 6 7 I signal.Thelinearoperatingrangeonthisinputis0to1.5V.Also,thispingets pulledtogroundeachtimeitsrespectiveoutputgoeslow(thatis:OUT1and OUT2). CTRL 8 9 I Feedbackcontrolinput: Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com PinFunctions(continued) PIN SOIC, I/O DESCRIPTION NAME TSSOP(20) TSSOP(16) Setsoscillatordischargecurrent:AresistorfromthispintoGNDsetsupthe dischargecurrentoftheinternalC capacitorusedintheoscillator.This T DISCHG 9 12 I resistor,inconjunctionwiththeresistorontheCHGpinisusedtosetupthe operatingfrequencyandmaximumdutycycle.Undernormaloperationthedc voltageonthispinis2.5V. GND 11 14 — Deviceground Setslinecomparatorhysteresis:ThispiniscontrolledbyboththeLINEOVand LINEHYS 2 3 I LINEUVpins.Itisusedtocontrolthehysteresisvaluesforboththeoverand undervoltagelinedetectors. Inputforlineovervoltagecomparator:Thispinisconnectedtoacomparator LINEOV 1 2 I andusedtomonitorthelinevoltageforanovervoltagecondition.Thetypical thresholdis1.26V. Inputforlineundervoltagecomparator:Thispinisconnectedtoacomparator LINEUV 15 18 I andusedtomonitorthelinevoltageforanundervoltagecondition.Thetypical thresholdis1.26V. N/C 16 1,10,11,19 — Noconnection PWMoutputfromchannel1:Theseoutputbuffersareintendedtointerfacewith highcurrentMOSFETdrivers.Theoutputdrivecapabilityisapproximately33 OUT1 13 16 O mAandhasanoutputimpedanceof100Ω.TheoutputsswingbetweenGND andREF. PWMoutputfromchannel2:Theseoutputbuffersareintendedtointerfacewith highcurrentMOSFETdrivers.Theoutputdrivecapabilityisapproximately33 OUT2 12 15 O mAandhasanoutputimpedanceof100Ω.TheoutputsswingbetweenGND andREF. Referencevoltageoutput:REFisa3.3-Voutputusedprimarilyasasourcefor theoutputbuffersandotherinternalcircuits.Itisprotectedfromaccidental REF 14 17 O shortstoground.Forimprovednoiseimmunity,TIrecommendsthereference pinbebypassedwithaminimumof0.1µFofcapacitancetoGND. Setsslopecompensation:Thispinsetsupacurrentusedfortheslope compensationramp.Aresistortogroundsetsupacurrent,whichisinternally SLOPE 5 6 I dividedby25andthenappliedtoaninternal10-pFcapacitor.Undernormal operationthdcvoltageonthispinis2.5V. Soft-startinput:Acapacitortogroundsetsupthesoft-starttimefortheopen loopsoft-startfunction.Thesourceandsinkcurrentfromthispinisequalto 3/7thoftheoscillatorchargecurrentsetbytheresistorontheCHGpin.The softstartcapacitorisheldlowduringUVLOandduringaLineOVorUV SS 7 8 I condition.OnceanOVorUVfaultoccurs,thesoft-startcapacitorisdischarged byacurrentequaltoitschargingcurrent.ThecapacitordoesNOTquickly dischargeduringfaults.Inthisway,thecontrollerhastheabilitytorecover quicklyfromveryshortlinetransients.Thispincanalsobeusedasan Enable/Disablefunction. Devicesupplyinput:Thisisusedtosupplypowertothedevice,monitoringthis pinisatheUVLOcircuit.Thisisusedtoinsureglitch-freestartupoperation. UntilVDDreachesitsUVLOthreshold,itremainsinalowpowermode, drawingapproximately150µAofcurrentandforcingpins,SS,CS1,CS2, VDD 3 4 I OUT1,andOUT2tologic0states.IftheVDDfallsbelow8Vafterreaching turnon,itgoesbackintothislowpowerstate.InthecaseoftheUCC28221,the UVLOthresholdis13V.Itis10VfortheUCC28220.Bothversionshavea turnoffthresholdof8V. Highvoltagestart-upinput:ThispinhasaninternalhighvoltageJFETusedfor startup.ThedrainisconnectedtoVIN,whileits’sourceisconnectedtoVDD. VIN — 20 I Duringstartup,thisJFETdelivers12mAtypicallywithaminimumof4mAto VDD,whichinturn,chargesuptheVDDbypasscapacitor.WhenVDDgetsto 13V,theJFETisturnedoff. 4 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT High-voltagestart-upinput,V 110 V IN Supplyvoltage,V 15 V DD Outputcurrent(OUT1,OUT2)dc,I ±10 mA OUT(dc) OUT1/OUT2capacitiveload 200 pF REFoutputcurrent,I 10 mA REF Currentsenseinputs,CS1,CS2 –1 2 V Analoginputs(CHG,DISCHG,SLOPE,REF,CNTRL) –0.3 3.6 V Analoginputs(SS,LINEOV,LINEUV,LINEHYS) –0.3 7 V PWpackage 400 PowerdissipationatT =25°C mW A Dpackage 650 Junctionoperatingtemperature,T –55 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V High-voltagestart-upinput 36 76 V IN V Supplyvoltage 8.4 14.5 V DD 7.4 Thermal Information UCC28220,UCC28221 UCC28221 THERMALMETRIC(1) D(SOIC) PW(TSSOP) PW(TSSOP) UNIT 16PINS 16PINS 20PINS R Junction-to-ambientthermalresistance 73 100.9 92.5 °C/W θJA R Junction-to-case(top)thermalresistance 32.6 28.8 27.6 °C/W θJC(top) R Junction-to-boardthermalresistance 30.6 46.6 43.7 °C/W θJB ψ Junction-to-topcharacterizationparameter 5.7 1.4 1.4 °C/W JT ψ Junction-to-boardcharacterizationparameter 30.3 46 43.2 °C/W JB R Junction-to-case(bottom)thermalresistance — — — °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com 7.5 Electrical Characteristics V =12V,0.1-µFcapacitorfromVDDtoGND,0.1-µFcapacitorfromREFtoGND,F =1MHz,T =–40°Cto105°C, DD OSC A andT =T (unlessotherwisenoted). A J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OVERALL OperatingVDD 8.4 14.5 V Quiescentcurrent SS=0V,noswitching,F =1MHz 1.5 3 4 mA OSC Operatingcurrent Outputsswitching,F =1MHz 1.6 3.5 6 mA OSC START-UP Startupcurrent UCC28220,VDD<(UVLO–0.8) 200 µA UCC28220 9.5 10 10.5 UVLOstartthreshold V UCC28221 12.3 13 13.7 UVLOstopthreshold 7.6 8 8.4 V UCC28220 1.8 2 2.2 UVLOhysteresis V UCC28221 4.8 5 5.2 SS=0,outputsnotswitching,VDDdecreasing 9.5 10 10.5 JFETONthreshold SS=2V,Cntrl=2V,outputswitching,VDD V 7.6 8 8.4 decreasing;samethresholdasUVLOstop VIN=36Vto76V,VDD=0V 16 48 100 HighvoltageJFETcurrent VIN=36Vto76V,VDD=10V 4 16 40 mA VIN=36Vto76V,VDD<UVLO 4 12 40 JFETleakage VIN=36Vto76V,VDD=14V 100 µA REFERENCE Outputvoltage 8V<VDD<14V,ILOAD=0mAto–10mA 3.15 3.3 3.45 V Outputcurrent Outputsnotswitching,CNTRL=0V 10 mA Outputshort-circuitcurrent V =0V –40 –20 –10 mA REF V UVLO 2.55 3 3.25 V REF SOFTSTART SSchargecurrent RCHG=10.2kΩ,SS=0V –70 –100 –130 µA SSdischargecurrent RCHG=10.2kΩ,SS=2V 70 100 130 µA SSinitialvoltage LINEOV=2V,LINEUV=0V 0.5 1 1.5 V SSvoltageat0%dc Pointatwhichoutputstartsswitching 0.5 1.2 1.8 V SSvoltageratio 75% 90% 100% SSmaxvoltage LINEOV=0V,LINEUV=2V 3 3.5 4 V OSCILLATORANDPWM Outputfrequency RCHG=10.2kΩ,RDISCHG=10.2kΩ 450 500 550 kHz Oscillatorfrequency RCHG=10.2kΩ,RDISCHG=10.2kΩ 900 1000 1100 kHz RCHG=10.2kΩ,RDISCHG=10.2kΩ, Outputmaximumdutycycle 73% 75% 77% measuredatOUT1andOUT2 CHGvoltage 2 2.5 3 V DSCHGvoltage 2 2.5 3 V SLOPECOMPENSATION RSLOPE=75kΩ,RCH=66kΩ, Slope 140 200 260 mV/us RDISCHG=44kΩ,Csx=0Vto0.5V Channelmatching RSLOPE=75kΩ,Csx=0V 0% 10% CURRENTSENSE CS1,CS2biascurrent CS1=0,CS2=0 –500 0 500 nA PropdelayCSxtoOUTx CSxinput0Vto1.5Vstep 40 85 ns CS1,CS2sinkcurrent CSx=2V 2.3 4.5 7 mA 6 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 Electrical Characteristics (continued) V =12V,0.1-µFcapacitorfromVDDtoGND,0.1-µFcapacitorfromREFtoGND,F =1MHz,T =–40°Cto105°C, DD OSC A andT =T (unlessotherwisenoted). A J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CNTRL Resistorratio(1) 0.6 Ctrlinputcurrent CTRL=0Vand3.3V –100 0 100 nA CSx=0V,pointatwhichoutputstartsswitching Ctrlvoltageat0%dc 0.5 1.2 1.8 V (checksresistorratio) OUTPUT(OUT1,OUT2) Lowlevel I =10mA 0.4 1 V OUT Highlevel I =−10mA,VREF–VOUT 0.4 1 V OUT Risetime C =50pF 10 20 ns LOAD Falltime C =50pF 10 20 ns LOAD LINESENSE T =25°C 1.24 1.26 1.28 A LINEOVthreshold V T =–40°Cto105°C 1.235 1.26 1.285 A T =25°C 1.24 1.26 1.28 A LINEUVthreshold V T =–40°Cto105°C 1.235 1.26 1.285 A LINEHYSTpullupvoltage LINEOV=2V,LINEUV=2V 3.1 3.25 3.4 V LINEHYSToffleakage LINEOV=0V,LINEUV=2V –500 0 500 nA LINEHYSpullupresistance I=–20µA 100 500 Ω LINEHYSpulldownresistance I=20µA 100 500 Ω LINEOV,LINEUVbiasI LINEOV=1.25V,LINEUV=1.25V –500 500 nA (1) Ensuredbydesign.Not100%testedinproduction. Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com 7.6 Typical Characteristics 4.0 13.5 UCC28221 UVLO on threshold 3.5 UCC28221EXCLUDESJFETCURRENT V A − 12.5 m ds − 3.0 hreshol 11.5 Current 2.5 T O nt V−UVLUVLO190.5.5 UCUJCFC2E8CT222 8o02n a2 tn0h drUe UVsCLhOoCl 2do8 n(2w 2thh1re UensV nhLooOtld so waffni ttdch hrUeiCnsgCh)o2l8d2 2a1nd I−QuiesceDD112...050 UCC28220 UCC28221 8.5 UCC28221 JFET on threshold (when switching) 0.5 7.5 0.0 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 Tj−Temperature−°C VDD−SupplyVoltage−V Figure1.UVLOThresholdsvsTemperature Figure2.QuiescentCurrentvsSupplyVoltage 30 3.45 20 VIN= 36 V 3.40 A UCC28221 V m 10 − − ge ply Current −010 erenceVolta33..3305 NoLoad Sup Ref − −20 − DD REF3.25 I −30 V Load 3.20 −40 JFET source current −50 3.15 0 2 4 6 8 10 12 14 16 −50 −25 0 25 50 75 100 125 VDD−Supply Voltage−V Tj−Temperature−°C Figure3.SupplyCurrentvsSupplyVoltage Figure4.ReferenceVoltagevsTemperature 1.270 230 225 1.265 s RSLOPE= 75 kΩ µ 220 er 1.260 LINEOV V p 215 V m − − 210 d1.255 n TripThreshol11..224550 LINEUV Compensatio 122900505 CS1=0V Vth−1.240 Slope 118950 CS1 = 0.5 V − PE 180 1.235 O SL 175 1.230 170 −50 −25 0 25 50 75 100 125 −50 −25 0.0 25 50 75 100 125 Tj−Temperature−°C Tj−Temperature−°C Figure5.LINEOVandLINEUVThresholdsvsTemperature Figure6.SlopeCompensationvsTemperature 8 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 Typical Characteristics (continued) 107 10 Ω − 8 or st 6 si e mming R 106 −% 24 e Progra Mismatch −02 CRSSL0O=P0EV= 75 kΩ p CS1 = 0 V Slo 105 −4 − E OP −6 L S R −8 104 −10 10 100 1000 −50 −25 0.0 25 50 75 100 125 SLOPE−SlopeCompensation−mVperµs Tj−Temperature−°C Figure7.ProgrammingResistorvsSlopeCompensation Figure8.Channel1andChannel2SlopeMatching vsTemperature 20 1.0 19 1178 0.9 IOUT= 10 mA ns 16 0.8 e− 15 V m 14 − 0.7 RiseandFallTi 1111891023 FallTimeRiseTime utputVoltage 000...456 VREF−VOUT(VOH) ndTf− 756 OV-O0.3 VOL Tra 4 0.2 3 2 0.1 1 0 0.0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 Tj−Temperature−°C Tj−Temperature−°C C =50pF space L Figure9.RiseandFallTimevsTemperature Figure10.VOHandVOLvsTemperature −70 130 RCHG= 10.2 kΩ A −80 120 µ A − µ Current −90 urrent− 110 e C Charg −100 harge 100 − C H − ISSC −110 SSdis 90 I −120 80 −130 70 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 Tj−Temperature−°C Tj−Temperature−°C Figure11.Soft-StartChargeCurrentvsTemperature Figure12.Soft-StartDischargeCurrentvsTemperature Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com Typical Characteristics (continued) 1M 550 540 RCHRG=RDISRG=10.2kΩ Ω 530 − RCHRG=RDISRG e nc DMAX= 75% Hz520 sta 100K −k Resi ncy510 DISRG− Freque459000 R 10K or RCHRG Oscillat447800 - S460 f 1K 450 10K 100K 1M 10M −50 −25 0 25 50 75 100 125 fS-SwitchingFrequency−Hz Tj−Temperature−°C Figure13.ProgrammingResistorsvsSwitchingFrequency Figure14.OscillatorFrequencyvsTemperature 77 100 90 RCHRG=RDISRG=10.2kΩ 105°C 80 76 s % n 70 − − y cle ela 60 Duty Cy 75 OUTxd 50 −40°C 25°C C− xto 40 D S C 30 74 20 10 73 0 −50 −25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Tj−Temperature−°C CSx−PeakVoltage−V Figure15.ProgrammableMaxDutyCyclevsTemperature Figure16.CSxtoOUTxDelayvsCSxPeakVoltage 10 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 8 Detailed Description 8.1 Overview The UCC2822x device is comprised of several housekeeping blocks as well as two slope compensated PWM channels that are interleaved. The circuit is intended to run from an external VDD supply voltage between 8 V and 14 V; however, the UCC28221 has the addition of a high-voltage start-up JFET with control circuitry which can be used for system start-up. Other functions contained in the device are supply UVLO, 3.3-V reference, accurate line OV and UV functions, a high-speed programmable oscillator for both frequency and duty cycle, programmableslopecompensation,andprogrammablesoft-startfunctions. The UCC2822x is a primary side controller for a two-channel interleaved power converter. The device is compatible with forward or flyback converters as long as a duty cycle clamp between 60% and 90% is required. The active clamp forward and flyback converters as well as the RCD and resonant reset forward converters are therefore compatible with this device. To ensure the two channels share the total converter output current, current mode control with internal slope compensation is used. Slope compensation is user programmable through a dedicated pin and can be set over a 50:1 range, ensuring good small-signal stability over a wide range ofapplications. 8.2 Functional Block Diagram RUN REF 14 REFERENCE UVLO/ JFET 16 VIN CONTROL (N/C on UCC28220) 2 CHG 10 OSC T Q CLK1 3 VDD DISCHG 9 FF CLK2 Q S Q VREF CLK1 + + LATCH CS1 4 13 OUT1 0.5 V R Q RUN 11 GND SLOPE COMPENSATION CS2 6 0.5 V CLK2 S Q VREF + + LATCH 12 OUT2 R Q RUN SLOPE 5 20 kΩ CTRL 8 + + 1 LINEOV − 30 kΩ 1 pF LINE OV/UV 2 LINEHYS 15 LINEUV Soft−Start SS 7 RUN Copyright © 2016,Texas Instruments Incorporated Pinoutfor16pinoptionshown.Seethe20-pinconnectiontoUCC28221-PWinPinConfigurationandFunctions. Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com 8.3 Feature Description 8.3.1 VDD Because the driver output impedance is high, the energy storage requirement on the VDD capacitor is low. For improvednoiseimmunity,TIrecommendsthattheVDDpinisbypassedwithaminimumof0.1-µFcapacitanceto GND. In most typical applications, the bias voltage for the MOSFET drivers is also used as the VDD supply voltage for the chip. It is beneficial to add a low valued resistor between the bulk storage capacitor of the driver and the VDD capacitor for the UCC2822x. By adding a resistor in series with the bias supply with the bias supply,anynoisethatispresentonthebiassupplyisfilteredoutbeforegettingtotheVDDpinofthecontroller. 8.3.2 Reference Forimprovednoiseimmunity,TIrecommendsthatthereferencepin,REF,isbypassedwithaminimumof0.1-µF capacitancetoGND. 8.3.3 OscillatorOperationandMaximumDutyCycleSetpoint The oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator is programmable over a 200-kHz to 2-MHz frequency range with 20% to 80% maximum duty cycle range. Both the dead time and the frequency of the oscillator are divided by 2 to generate the PWM clock and off-time information for each of the outputs. In this way, a 20% oscillator duty cycle corresponds to a 60% maximum duty cycleateachoutput,wherean80%oscillatordutycycleyieldsa90%dutycycleclampateachoutput. The design equations for the oscillator and maximum duty cycle setpoint are given in Equation 1 through Equation4. F =2´F OSC OUT (1) D =1-2´(1-D ) MAX(osc) MAX(out) (2) D R =K ´ MAX(osc) CHG OSC F OSC (3) (1-D ) R =K ´ MAX(osc) DISCHG OSC F OSC where • K =2.04×1010(Ω/s) OSC • F =Switchingfrequencyattheoutputsofthechip(Hz) OUT • D =Maximumdutycyclelimitattheoutputsofthechip MAX(out) • D =Maximumdutycycleoftheoscillatorforthedesiredmaximumdutycycleattheoutputs MAX(osc) • F =Oscillatorfrequencyfordesiredoutputfrequency(Hz) OSC • R =Externaloscillatorresistorwhichsetsthechargecurrent(Ω) CHG • R =Externaloscillatorresistorwhichsetsthediscargecurrent(Ω) (4) DISCHG 8.3.4 SoftStart A current is forced out of the SS pin, equal to 3/7 of the current set by R , to provide a controlled ramp CHG voltage. The current set by the R resistor is equal to 2.5 V divided by R . This ramp voltage overrides the CHG CHG commanded duty cycle on the CTRL pin, allowing a controlled start-up. Assuming the UCC288221 is biased on the primary side, the soft start must be quite quick to allow the secondary bias to be generated and the secondary side control can then take over. Once the soft-start time interval is complete, a closed-loop soft-start onthesecondarysidecanbeexecuted,suchasEquation5. 3 2.5 ISS= ´ 7 R CHG where • ISS=currentwhichissourcedoutoftheSSpinduringthesoft-starttime(A) (5) 12 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 Feature Description (continued) 8.3.5 CurrentSense The current sense signals CS1 and CS2 are level shifted by 0.5 V and have the slope compensation ramps addedtothembeforebeingcomparedtothecontrolvoltageattheinputofthePMWcomparators.Theamplitude of the current sense signal at full load must be selected such that it is very close to the maximum control voltage tolimitthepeakoutputcurrentduringshort-circuitoperation. 8.3.6 OutputDrivers The UCC2822x is intended to interface with the UCC2732x family of MOSFET drivers. As such, the output drive capabilityislow,effectively100 Ω,andthedriveroutputswingbetweenGNDandREF. 8.4 Device Functional Modes 8.4.1 LineOvervoltageandUndervoltage Three pins are provided to turn off the output drivers and reset the soft-start capacitor when the converter input voltage is outside a prescribed range. The undervoltage setpoint and undervoltage hysteresis are accurately set through external resistors. The overvoltage set point is also accurately set through a resistor ratio, but the hysteresisisfixedbythesameresistorthatsettheundervoltagehysteresis. Figure 17 and Figure 18 show the detailed functional diagram and operation of the undervoltage lockout (UVLO) and overvoltage lockout (OVLO) features. Equation 6 through Equation 9 are for setting the thresholds define in Figure18. R1 V1=1.26´ +1.26 (R2+R3) (6) (R1+Rx) V2=1.26´ ,whereRx =R4P(R2+R3) Rx (7) (R1+R2+R3) V4=1.26´ R3 (8) æR1ö V3= V4-1.26´ ç ÷ èR4ø (9) Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com Device Functional Modes (continued) Input Voltage R1 UV 15 + 1.26 V 1.26 V + S1 OPEN HYS 2 R4 S2 CLOSED LINE_GOOD R2 OV 1 + R3 1.26 V Copyright © 2016,Texas Instruments Incorporated Figure17. LineUVLOandOVLOFunctionalDiagram ENABLE LINE_GOOD OFF V1 V2 V3 V4 Figure18. LineUVLOandOVLOOperation The UVLO hysteresis and the OVLO hysteresis can be calculated as V2 – V1 and V4 – V3, respectively. By examining the design equations, it becomes apparent that the value of R4 sets the amount of hysteresis at both thresholds. By realizing this fact, the designer can then set the value of R4 based on the most critical hysteresis specification either at high line or at low line. In most designs the value of R4 is determined by the desired amount of hysteresis around the UVLO threshold. As an example, consider a telecom power supply with the followinginputUVLOandOVLOdesignspecifications: • V1=32V • V2=34V • V3=83V • V4=84.7V Then, • R1=976kΩ • R2=24.9kΩ • R3=15kΩ • R4=604kΩ 14 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 Device Functional Modes (continued) 8.4.2 Start-UpJFETSection A 110-V start-up JFET is included to start the device from a wide range (36 V to 75 V) telecom input source. When VDD is lower than 13 V, the JFET is on, behaving as a current source charging the bias capacitors on VDD and supplying current to the device. In this way, the VDD bypass capacitors are charged to 13 V where the outputs start switching and the JFET is turned off. To enable a constant bias supply to the device during a pulse skipping condition, the JFET is turned back on whenever VDD decreases below 10 V and the outputs are not switching. Thus, the current from the JFET can overcome the internal bias currents, as long as the device is not actively switching the output drivers. See Figure 19 for a representation of the JFET and VDD operation. The OCC28220 does not contain an internal JFET and has a start-up threshold of 10 V which makes it capable of directlyoperatingoffa12-Vdcbus. VDD 13 V 13 V 8−14 V 10 V NORMALOPERATION 8 V (UVLO off) 0V OUTx OFF GATEDRV ON ON OFF HV JFET Figure19. JFETDeviceOperationWithVDDVoltage 8.4.3 SlopeCompensation The slope compensation circuit in the UCC2822x operates on a cycle-by-cycle basis. The two channels have separate slope compensation circuits. These are fabricated in precisely the same way so as current sharing is unaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever that channel's output is off. At the beginning of the PMW cycle, a current is mirrored off the SLOPE pin into the capacitor, developing an independent ramp. Because the two channel's ramps start when the channel's output changesfromalowtohighstate,therampsarethusinterleaved.Theseinternalrampsareaddedtothevoltages onthecurrentsensepins,CS1andCS2,andformaninputtothePMWcomparators. Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com Device Functional Modes (continued) REF SLOPE 2.5/(16.6∗R_SLOPE)=I_SC (5) R_SLOPE PWM CTRL − (8) TO RESET + of + PWMLATCH 0.5V C_SC OUT1 S1 10 pF ON OFF CS1 (4) S2 Figure20. SlopeCompensationDetailforChanel1. DuplicateMatchedCircuitryExistsforChannel2. To ensure stability, the slope compensation circuit must add between 1/5 and 1 times the inductor downslope to eachofthecurrentsensesignalsbeforebeingappliedtotheinputofthePWMcomparator. 16 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The UCC28220 control device from Texas Instruments is used in a dual-interleaved, forward converter that enables the power supply designer to reduce output current ripple and reduce magnetic size per power stage allowing for improved transient response. The UCC28220 is a dual-interleaved PWM controller with programmable maximum duty cycle per channel up to 90% for interleaved forward and interleaved flyback designs. 9.2 Typical Application VIN CS1 UCC28220 1 OV N/C 16 2 HYS UV 15 Bias 1/2 UCC27424 3 VDD REF 14 4 CS1 OUT1 13 5 SLOPE OUT2 12 VOUT CS2 6 CS2 GND 11 7 SS CHG 10 8 CTRL DISCHG 9 1/2 UCC27424 E/A Copyright © 2016,Texas Instruments Incorporated Figure21. InterleavedBoostApplicationCircuitUsingtheUCC28220 Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com Typical Application (continued) 9.2.1 DesignRequirements Table1liststhedesignparametersfortheinterleavedboostapplicationcircuit. Table1.DesignParameters PARAMETER MIN TYP MAX UNIT V 85 110or230 265 VRMS IN V 374 390 425 V OUT V — — 30 V RIPPLE CurrentTHDat350W — — 10% PFat350W 0.95 — — Fullloadefficiency 90% — — f — 100 — kHz S Holduprequirements,t — — 20 ms HOLD f 47 50 60 Hz LINE 9.2.2 DetailedDesignProcedure 9.2.2.1 OvervoltageProtectionandUndervoltageLockout The OVP function and undervoltage lockout (UVLO) were handled by the UCC28220. It is a simple comparator that monitors the boost voltage. The OVP for this design was set to 425 V and UVLO was set to 108 V. The preregulatordoesnotstartswitchinguntilV reaches108V. OUT 9.2.2.2 PeakCurrentLimit Peak current limit is set by the maximum control voltage (V ) at the input of the UCC28220’s PWM comparator C with Equation 10 through Equation 12. Where a is the current sense transformer turns ratio of T1 and T2. The peakcurrentlimittrippointwassetfor130%ofthenominalpeakcurrenttoprotecttheboostFETs. N V I 1 a= P = P = S = N V I 50 S S P (10) I =æç POUT ´ 2 + DIL1ö÷´1.3 PEAK ç2´v h 2 ÷ è in(min)´ ø (11) V =1.8,V wassettoamaximumof3VtoprotecttheUCC28220CTRLpin. C CTRL V -0.5V C 2 R = SENSE I ´a PEAK (12) Equation12considersslopecompensationthatisaddedlater. The peak current of the FET during power up is 2 times I under normal operation as calculated with PEAK Equation13.Thisisduetotheexcessiveslopecompensationthatisrequiredforstability. I =2´I PEAK(startup) PEAK (13) 9.2.2.3 CurrentSenseTransformerResetResistor(T1andT2) V -0.5V C 2 R = RESET ( ) I ´ 1-D ´a PEAK MIN(LL) (14) 18 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 9.2.2.4 OscillatorandMaximumDutyCycleClamp The UCC28220’s oscillator and maximum duty cycle clamp are setup through resistor R and discharge. The CHG desireddutycycleclamp(D )wassetat0.9tostopthecurrentsensetransformersfromsaturating. MAX K =(2.04´1010)W OSC S (15) Equation15isUCC28220'soscillatorconstant. F =2´f OSC S (16) Equation16isUCC28220'sinternaloscillatorfrequency. F =2´f OSC S (17) Equation17istheinternaldutycycleclamp. D =1-2(1-D ) MAX(OSC) MAX (18) ( ) 1-D MAX(OSC) R =K DISCHG OSC F OSC (19) 9.2.3 ApplicationCurves CH2: V OUT 100 V/div.. 10 mV/div. CH1: 100 V/div. Rectified Line t−Time−100ms/div. t−Time−5 ms/div. Linetransientsat350-Wload POUT=350W VINsteppedfrom240Vto120Vto240V Figure22.OutputRippleVoltage Figure23.LineDropoutatFullLoad 10 Power Supply Recommendations The VDD power terminal for the device requires the placement of electrolytic capacitor as energy storage capacitor. And requires the placement of low-ESR noise decoupling capacitance as directly as possible from the VDD terminal to the VSS terminal, ceramic capacitors with stable dielectric characteristics over temperature are recommended,suchasX7Rorbetter.TIrecommendsa1-µF,50-Ve-capacitor. Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com 11 Layout 11.1 Layout Guidelines 1. TI recommends placing a 1-µF ceramic decoupling capacitor as close as possible between the VDD terminal andGND,trackeddirectlytobothterminals. 2. TI recommends placing a small, external filter capacitor on the CS1 and CS2 terminal. Track the filter capacitorasdirectlyaspossiblefromtheCStoGNDterminal. 3. ReducethetotalsurfaceareaoftracesontheCSnettoaminimum. 4. Connect decoupling and noise filter capacitors, as well as sensing resistors directly to the GND terminal in a star-point fashion, ensuring that the current-carrying power tracks (such as the gate drive return) are track separatelytoavoidnoiseandground-dropsthatcouldaffecttheanaloguesignalintegrity. 11.2 Layout Example 1 LINEOV VIN 16 2 LINEHYS LINEUV 15 3 VDD REF 14 4 CS1 OUT1 13 5 SLOPE OUT2 12 6 CS2 GND 11 7 SS CHG 10 8 CTRL DISCHG 9 Figure24. UCC28221Layout 20 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 www.ti.com SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation An evaluation module and an associated user’s guide are available. The UCC28221 is used in a two-channel interleaved Forward design converting from 36-V to 76-V dc input voltage to a regulated 12-V dc output. The power module has two isolated 100 W forward power stages operating at 500 kHz, which are operating 180 degrees out of phase with each other allowing for output current ripple cancellation and smaller magnetic design. This design also takes advantage of the UCC28221’s on-board 110-V internal JFET start up circuit that removes the need of an external trickle charge resistor for boot strapping. This circuit turns off after auxiliary power is suppliedtothedeviceconservingpower. UCC28221200-WEvaluationModule(EVM) (SLUU173) Forotherrelateddocumentationseethefollowing: • Unitrode - UC3854A/B and UC3855A-B Provide Power Limiting With Sinusoidal Input Current for PFC Front Ends(SLUA196) • AdvancedPFC/PWMCombinationControllerWithTrailing-Edge/Trailing-EdgeModulation (SLUS608) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC28220 Clickhere Clickhere Clickhere Clickhere Clickhere UCC28221 Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. Copyright©2003–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC28220 UCC28221

UCC28220,UCC28221 SLUS544G–SEPTEMBER2003–REVISEDAPRIL2017 www.ti.com 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 22 SubmitDocumentationFeedback Copyright©2003–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28220 UCC28221

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC28220D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 28220 & no Sb/Br) UCC28220DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 28220 & no Sb/Br) UCC28220PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 28220 & no Sb/Br) UCC28220PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 28220 & no Sb/Br) UCC28221D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 28221 & no Sb/Br) UCC28221DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 28221 & no Sb/Br) UCC28221PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 28221 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC28220 : •Automotive: UCC28220-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Apr-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC28220DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC28220PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Apr-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC28220DR SOIC D 16 2500 367.0 367.0 38.0 UCC28220PWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated