Product Sample & Technical Tools & Support & Folder Buy Documents Software Community UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 UCC2817, UCC2818, UCC3817 and UCC3818 BiCMOS Power Factor Pregulator 1 Features 3 Description • ControlsBoostPreregulatortoNear-UnityPower The UCCx817 and UCCx818 family provides all the 1 functions necessary for active power factor-corrected Factor preregulators. The controller achieves near-unity • LimitsLineDistortion power factor by shaping the AC input line current • WorldWideLineOperation waveform to correspond to that of the AC input line • Over-VoltageProtection voltage. Average current mode control maintains stable,lowdistortionsinusoidallinecurrent. • AccuratePowerLimiting Designed in Texas Instrument’s BiCMOS process, • AverageCurrentModeControl the UCCx817 and UCCx818 offers new features such • ImprovedNoiseImmunity as lower start-up current, lower power dissipation, • ImprovedFeed-ForwardLineRegulation overvoltage protection, a shunt UVLO detect circuitry, • LeadingEdgeModulation a leading-edge modulation technique to reduce ripple current in the bulk capacitor, and an improved, low- • 150-μATypicalStart-UpCurrent offset (±2-mV) current amplifier to reduce distortion at • Low-PowerBiCMOSOperation lightloadconditions. • Upto18-VOperation DeviceInformation(1) • FrequencyRange6kHzto220kHz PARTNUMBER PACKAGE BODYSIZE(NOM) 2 Applications UCC2817, 3.91mm×9.9mm UCC2818, SOIC(16) • PCPower UCC3817, 7.5mm×10.3mm • ConsumerElectronics UCC3818 PDIP(16) 6.35mm×19.3mm • Lighting (1) For all available packages, see the orderable addendum at theendofthedatasheet. • IndustrialPowerSupplies • IEC6100-3-2CompliantSuppliesLessThan 300W BlockDiagram VCC 15 OVP/EN 10 16 V (FOR UCC2817 ONLY) 7.5 V REFERENCE 9 VREF SS 13 1.9 V t ENABLE UVLO VAOUT 7 + 16 V/10 V (UCC2817) ZERO POWER 10.5 V/10 V (UCC2818) 0.33 V t VCC VOLTAGE VSENSE 11 t ERROR AMP + CURRENT 8.0 V + OVP 7.5 V + AMP X t yX MULT t t PWM 16 DRVOUT + S Q VFF 8 X2 + PWM OSC LATCH R R MIRROR CLK 2:1 1 GND CLK IAC 6 OSCILLATOR t 2 PKLMT + MOUT 5 4 3 12 14 CAI CAOUT RT CT Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 15 2 Applications........................................................... 1 8.1 ApplicationInformation............................................15 3 Description............................................................. 1 8.2 TypicalApplication .................................................16 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 24 5 PinConfigurationandFunctions......................... 3 9.1 PowerSwitchSelection..........................................24 6 Specifications......................................................... 4 10 Layout................................................................... 25 6.1 AbsoluteMaximumRatings......................................4 10.1 LayoutGuidelines.................................................25 6.2 ESDRatings..............................................................5 10.2 LayoutExample....................................................27 6.3 RecommendedOperatingConditions.......................5 11 DeviceandDocumentationSupport................. 28 6.4 ThermalInformation..................................................5 11.1 DocumentationSupport .......................................28 6.5 ElectricalCharacteristics...........................................5 11.2 RelatedLinks........................................................28 6.6 TypicalCharacteristics..............................................8 11.3 ReceivingNotificationofDocumentationUpdates28 7 DetailedDescription.............................................. 9 11.4 CommunityResources..........................................28 7.1 Overview...................................................................9 11.5 Trademarks...........................................................28 7.2 FunctionalBlockDiagram.........................................9 11.6 ElectrostaticDischargeCaution............................28 7.3 FeatureDescription.................................................10 11.7 Glossary................................................................28 7.4 DeviceFunctionalModes........................................13 12 Mechanical,Packaging,andOrderable Information........................................................... 29 4 Revision History ChangesfromRevisionJ(March2009)toRevisionK Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection. ................................................................................................ 1 2 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 5 Pin Configuration and Functions D,DW,N,andPWPackages 16Pins TopView GND 1 16 DRVOUT PKLMT 2 15 VCC CAOUT 3 14 CT CAI 4 13 SS MOUT 5 12 RT IAC 6 11 VSENSE VAOUT 7 10 OVP/EN VFF 8 9 VREF PinFunctions PIN I/O DESCRIPTION NAME NO. Ground.Allvoltagesmeasuredwithrespecttoground.VCCandREFshouldbebypassed GND 1 – directlytoGNDwitha0.1-μForlargerceramiccapacitor. PFCpeakcurrentlimit.Thethresholdforpeaklimitis0V.Usearesistordividerfromthe negativesideofthecurrentsenseresistortoVREFtolevelshiftthissignaltoavoltagelevel PKLMT 2 I definedbythevalueofthesenseresistorandthepeakcurrentlimit.Peakcurrentlimitis reachedwhenPKLMTvoltagefallsbelow0V. Currentamplifieroutput.Thisistheoutputofawidebandwidthoperationalamplifierthat CAOUT 3 O senseslinecurrentandcommandsthePFCpulse-widthmodulator(PWM)toforcethe correctdutycycle.CompensationcomponentsareplacedbetweenCAOUTandMOUT. Currentamplifiernoninvertinginput.PlacearesistorbetweenthispinandtheGNDsideof CAI 4 I currentsenseresistor.Thisinputandtheinvertinginput(MOUT)remainfunctionaldownto andbelowGND. Multiplieroutputandcurrentamplifierinvertinginput.Theoutputoftheanalogmultiplierand theinvertinginputofthecurrentamplifierareconnectedtogetheratMOUT.Asthemultiplier outputisacurrent,thisisahigh-impedanceinputsotheamplifiercanbeconfiguredasa differentialamplifier.Thisconfigurationimprovesnoiseimmunityandallowsfortheleading- edgemodulationoperation.Themultiplieroutputcurrentislimitedto(2×I ).Themultiplier IAC outputcurrentisgivenbytheequation: MOUT 5 I/O I × (V – 1) IAC VAOUT I = MOUT 2 V × K VFF where • K=1/Visthemultipliergainconstant (1) Currentproportionaltoinputvoltage.Thisinputtotheanalogmultiplierisacurrent IAC 6 I proportionaltoinstantaneouslinevoltage.Themultiplieristailoredforverylowdistortion fromthiscurrentinput(I )tomultiplieroutput.TherecommendedmaximumI is500μA. IAC IAC Voltageamplifieroutput.Thisistheoutputoftheoperationalamplifierthatregulatesoutput VAOUT 7 O voltage.Thevoltageamplifieroutputisinternallylimitedtoapproximately5.5Vtoprevent overshoot. Feed-forwardvoltage.TheRMSvoltagesignalgeneratedatthispinbymirroring1/2ofthe VFF 8 I I intoasinglepoleexternalfilter.Atlowline,theVFFvoltageshouldbe1.4V. IAC Voltagereferenceoutput.VREFistheoutputofanaccurate7.5-Vvoltagereference.This outputiscapableofdelivering20mAtoperipheralcircuitry,andisinternallyshort-circuit VREF 9 O current-limited.VREFisdisabledandremainsat0VwhenV isbelowtheUVLO VCC threshold.BypassVREFtoGNDwitha0.1-μForlargerceramiccapacitorforbeststability. RefertoFigure1andFigure2forVREFlineandloadregulationcharacteristics. Over-voltage/enable.Awindowcomparatorinputthatdisablestheoutputdriveriftheboost OVP/EN 10 I outputvoltageisaprogrammedlevelabovethenominal,ordisablesboththePFCoutput driverandresetsSSifpulledbelow1.9V(typ). Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com PinFunctions(continued) PIN I/O DESCRIPTION NAME NO. Voltageamplifierinvertinginput.Thisisnormallyconnectedtoacompensationnetworkand VSENSE 11 I totheboostconverteroutputthroughadividernetwork. Oscillatorchargingcurrent.AresistorfromRTtoGNDisusedtoprogramoscillatorcharging RT 12 I current.Aresistorbetween10kΩand100kΩisrecommended.Nominalvoltageonthispin is3V. Soft-start.V isdischargedforV lowconditions.Whenenabled,SSchargesanexternal SS VCC capacitorwithacurrentsource.Thisvoltageisusedasthevoltageerrorsignalduringstart- up,enablingthePWMdutycycletoincreaseslowly.IntheeventofaV dropout,the SS 13 I VCC OVP/ENisforcedbelow1.9V(typ),SSquicklydischargestodisablethePWM.Note:Inan open-looptestcircuit,groundingtheSSpindoesnotensure0%dutycycle.Seethe ApplicationandImplementationfordetails. Oscillator timing capacitor. A capacitor from CT to GND sets the PWM oscillator frequency accordingto: CT 14 I f≈0.6/(RT×CT) (2) The lead from the oscillator timing capacitor to GND should be as short and direct as possible. Positivesupplyvoltage.Connecttoastablesourceofatleast20mAbetween10Vand17 Vfornormaloperation.BypassVCCdirectlytoGNDtoabsorbsupplycurrentspikes VCC 15 I requiredtochargeexternalMOSFETgatecapacitances.Topreventinadequategatedrive signals,theoutputdevicesareinhibitedunlessV exceedstheupperundervoltage VCC lockoutvoltagethresholdandremainsabovethelowerthreshold. Gatedrive.Theoutputdrivefortheboostswitchisatotem-poleMOSFETgatedriveron DRVOUT.Useaseriesgateresistortopreventinteractionbetweenthegateimpedanceand DRVOUT 16 O theoutputdriverthatmightcausetheDRVOUTtoovershootexcessively.SeeFigure6to determineminimumrequiredgateresistervalue.SomeovershootoftheDRVOUToutputis alwaysexpectedwhendrivingacapacitiveload. 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) MIN MAX UNIT SupplyvoltageVCC 18 V SupplycurrentICC 20 mA Gatedrivecurrent,continuous 0.2 A Gatedrivecurrent 1.2 A Inputvoltage,CAI,MOUT,SS 8 V Inputvoltage,PKLMT 5 V Inputvoltage,VSENSE,OVP/EN 10 V Inputcurrent,RT,IAC,PKLMT 10 mA Inputcurrent,VCC(noswitching) 20 mA Maximumnegativevoltage,DRVOUT,PKLMT,MOUT –0.5 V Powerdissipation 1 W T Junctiontemperature –55 150 °C J T Storagetemperature –65 150 °C stg T Leadtemperature(soldering,10seconds) 300 °C sol (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 4 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT VCC Inputvoltage 12 V VSENSE Inputsensevoltage 7.5 10 V Inputcurrentforoscillator 1.36 10 mA 6.4 Thermal Information UCC281x,UCC381x THERMALMETRIC(1) SOIC(D) SOIC(DW) PDIP(N) TSSOP UNIT (PW) 16PINS 16PINS 16PINS 16PINS R Junction-to-ambientthermalresistance 73.9(2) 74.1(2) 49.3(2) 98.9(3) °C/W θJA R Junction-to-case(top)thermalresistance 33.5 35.5 38.9 30.2(3) °C/W θJC(top) R Junction-to-boardthermalresistance 31.4 38.9 29.4 44.8 °C/W θJB ψ Junction-to-topcharacterizationparameter 5.8 9.9 18.9 1.9 °C/W JT ψ Junction-to-boardcharacterizationparameter 31.1 38.3 29.2 44.1 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,Formoreinformationabouttraditionalandnewthermalmetrics,seethe SemiconductorandICPackageThermalMetricsapplicationreport. (2) Specifiedθ (junctiontoambient)isfordevicesmountedto5-inch2FR4PCboardwithoneouncecopper,wherenoted.When ja resistancerangeisgiven,lowervaluesarefor5inch2aluminumPCboard.TestPWBwas0.062-inchthickandtypicallyused0.635-mm tracewidthsforpowerpackagesand1.3-mmtracewidthsfornon-powerpackageswitha100-mil×100-milprobelandareaattheend ofeachtrace. (3) Modeleddata.Ifvaluerangegivenforθ ,lowervalueisfor3×3inch.1ozinternalcoppergroundplane,highervalueisfor1×1-inch. ja groundplane.Allmodeldataassumesonlyonetraceforeachnon-fusedlead. 6.5 Electrical Characteristics T =0°Cto70°CfortheUCC3817,andT =−40°Cto85°CfortheUCC2817,T =T,VCC=12V,R =22kΩ,C =270 A A A J T T pF,(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT VCC=(VCCturn-onthreshold Supplycurrent,off 150 300 µA −0.3V) VCC=12V,Noloadon Supplycurrent,on 2 4 6 mA DRVOUT UVLO VCCturn-onthreshold(UCCx817) 15.4 16 16.6 V VCCturn-offthreshold(UCCx817) 9.4 9.7 V UVLOhysteresis(UCCx817) 5.8 6.3 V Maximumshuntvoltage(UCCx817) I =10mA 15.4 17 17.5 V VCC VCCturn-onthreshold(UCCx818) 9.7 10.2 10.8 V VCCturn-offthreshold(UCCx818) 9.4 9.7 V UVLOhysteresis(UCCx818) 0.3 0.5 V VOLTAGEAMPLIFIER Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com Electrical Characteristics (continued) T =0°Cto70°CfortheUCC3817,andT =−40°Cto85°CfortheUCC2817,T =T,VCC=12V,R =22kΩ,C =270 A A A J T T pF,(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT T =0°Cto70°C 7.387 7.5 7.613 A Inputvoltage V T =−40°Cto85°C 7.369 7.5 7.631 A V =V ,VAOUT=2.5 V biascurrent SENSE REF 50 200 nA SENSE V Openloopgain VAOUT=2Vto5V 50 90 dB High-leveloutputvoltage I =−150μA 5.3 5.5 5.6 V L Low-leveloutputvoltage I =150μA 0 50 150 mV L OVERVOLTAGEPROTECTIONANDENABLE Overvoltagereference VREF+0.48 VREF+0.50 VREF+0.52 V Hysteresis 300 500 600 mV Enablethreshold 1.7 1.9 2.1 V Enablehysteresis 0.1 0.2 0.3 V CURRENTAMPLIFIER Inputoffsetvoltage V =0V,V =3V –3.5 0 2.5 mV CM CAOUT Inputbiascurrent V =0V,V =3V –50 –100 nA CM CAOUT Inputoffsetcurrent V =0V,V =3V 25 100 nA CM CAOUT V =0V,V =2Vto5 Openloopgain CM CAOUT 90 dB V V =0Vto1.5V,V = Common-moderejectionratio CM CAOUT 60 80 dB 3V High-leveloutputvoltage I =−120μA 5.6 6.5 6.8 V L Low-leveloutputvoltage I =1mA 0.1 0.2 0.5 V L Gainbandwidthproduct (1)2.5 MHz VOLTAGEREFERENCE T =0°Cto70°C 7.387 7.5 7.613 A Inputvoltage V T =−40°Cto85°C 7.369 7.5 7.631 A Loadregulation I =1mAto2mA 0 10 mV REF Lineregulation VCC=10.8Vto15V, (2) 0 10 mV Short-circuitcurrent V =0V –20 –25 –50 mA REF OSCILLATOR Initialaccuracy T =25°C 85 100 115 kHz A Voltagestability VCC=10.8Vto15V –1% 1% Totalvariation Line,temp 80 120 kHz Ramppeakvoltage 4.5 5 5.5 V Rampamplitudevoltage(peakto 3.5 4 4.5 V peak) PEAKCURRENTLIMIT PKLMTreferencevoltage –15 15 mV PKLMTpropagationdelay 150 350 500 ns MULTIPLIER I ,highline,lowpoweroutput I =500μA,V =4.7V, MOUT AC FF 0 –6 –20 µA current,(0°Cto85°C) VAOUT=1.25V I ,highline,lowpoweroutput I =500μA,V =4.7V, MOUT AC FF 0 –6 –23 µA current,(–40°Cto85°C) VAOUT=1.25V I ,highline,highpoweroutput I =500μA,V =4.7V, MOUT AC FF –70 –90 –105 µA current VAOUT=5V (1) Ensuredbydesign,notproductiontested. (2) ReferencevariationforV <VisshowninFigure1. CC 6 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 Electrical Characteristics (continued) T =0°Cto70°CfortheUCC3817,andT =−40°Cto85°CfortheUCC2817,T =T,VCC=12V,R =22kΩ,C =270 A A A J T T pF,(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I ,lowline,lowpoweroutput I =150μA,V =1.4V, MOUT AC FF –10 –19 –50 µA current VAOUT=1.25V I ,lowline,highpoweroutput I =150μA,V =1.4V, MOUT AC FF –268 –300 –345 µA current VAOUT=5V I =150μA,V =1.3V, I ,IAClimitedoutputcurrent AC FF –250 –300 –400 µA MOUT VAOUT=5V I =300μA,V =3V, Gainconstant(K) AC FF 0.5 1 1.5 1/V VAOUT=2.5V I =150μA,V =1.4V, AC FF 0 –2 VAOUT=0.25V I ,zerocurrent µA MOUT I =500μA,V =4.7V, AC FF 0 –2 VAOUT=0.25V I =500μA,V =4.7V, I ,zerocurrent,(0°Cto85°C) AC FF 0 –3 µA MOUT VAOUT=0.5V I =500μA,V =4.7V, I ,zerocurrent,(–40°Cto85°C) AC FF 0 –3.5 µA MOUT VAOUT=0.5V I =150μA,V =1.4V, Powerlimit(I xV ) AC FF –375 –420 –485 µW MOUT FF VAOUT=5V FEED-FORWARD VFFoutputcurrent I =300μA –140 –150 –160 µA AC SOFTSTART SSchargecurrent –6 –10 –16 µA GATEDRIVER Pullupresistance I =–100mAto−200mA 5 12 Ω O Pulldownresistance I =100mA 2 10 Ω O C =1nF,R =10Ω, Outputrisetime L L 25 50 ns V =0.7Vto9.0V DRVOUT C =1nF,R =10Ω, Outputfalltime L L 10 50 ns V =9.0Vto0.7V DRVOUT Maximumdutycycle 93% 95% 99% Minimumcontrolleddutycycle At100kHz 2% ZEROPOWER Zeropowercomparatorthreshold MeasuredonVAOUT 0.20 0.33 0.50 V Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 6.6 Typical Characteristics 7.60 7.510 V V − 7.55 −7.505 Voltage Voltage Reference 7.50 Reference7.500 − − REF REF V 7.45 V7.495 7.40 7.490 9 10 11 12 13 14 0 5 10 15 20 25 VCC−Supply Voltage−V IVREF−Reference Current−mA Figure1.ReferenceVoltagevsSupplyVoltage Figure2.ReferenceVoltagevsReferenceCurrent 350 1.5 IAC = 150µA A VFF= 1.4 V µ 300 nt− 1.3 urre 250 IAC = 150 µA C put 200 K 1.1 Out IAVCFF == 3 30.00 µVA ain− er 150 G Multipli 100 ultiplier 0.9 IAC = 500µA IAC = 300µA M - UT 0.7 O 50 M I IAC = 500µA VFF= 4.7 V 0 0.5 0.0 1.0 2.0 3.0 4.0 5.0 1.0 2.0 3.0 4.0 5.0 VAOUT−VoltageErrorAmplifierOutput−V VAOUT−VoltageErrorAmplifierOutput−V Figure3.MultiplierOutputCurrentvsVoltageError Figure4.MultiplierGainvsVoltageErrorAmplifierOutput AmplifierOutput 500 Ω e− 17 c n 400 sista 16 )−WµUT 300 VAOUT = 5 V GateRe 1145 O m ×IFM VAOUT = 4 V nimu 13 (VF 200 dMi 12 e VAOUT = 3 V nd 11 e m 100 m 10 o VAOUT = 2 V Rec 9 - E 0 AT 8 G 0.0 1.0 2.0 3.0 4.0 5.0 R 10 12 14 16 18 20 VFF−FeedforwardVoltage−V VCC−Supply Voltage−V Figure5.MultiplierConstantPowerPerformance Figure6.RecommendedMinimumGateResistancevs SupplyVoltage 8 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 7 Detailed Description 7.1 Overview The UCC3817 and the UCC3818 family of products provides PFC controllers all the necessary functions for achievingnearunityPFC. The UCC3817 and UCC3818, while being pin-compatible with other industry controllers providing similar functionality, offer many feature enhancements and tighter specifications, leading to an overall reduction in systemimplementationcost. The system performance is enhanced by incorporating many innovative features such as average current-mode control which maintains stable noise immune low distortion sinusoidal current. Also, the device features a leading edge modulation which when synchronized properly with a second stage DC-DC converter can reduce the ripple currentontheoutputcapacitortherebyincreasingtheoveralllifetimeofthepowersupply. In addition to these features, the key difference between the UCC281x and the UCC381x is that the UCC2817 can work over the extended temperature range of –40 to +85°C as opposed to 0 to +70°C in the case of the UCC3817. 7.2 Functional Block Diagram VCC 15 OVP/EN 10 16 V (FOR UCC2817 ONLY) 7.5 V REFERENCE 9 VREF SS 13 1.9 V t ENABLE UVLO VAOUT 7 + 16 V/10 V (UCC2817) ZERO POWER 10.5 V/10 V (UCC2818) 0.33 V t VCC VOLTAGE VSENSE 11 t ERROR AMP + CURRENT 8.0 V + OVP 7.5 V + AMP X t yX MULT t t PWM 16 DRVOUT + S Q VFF 8 X2 + PWM OSC LATCH R R MIRROR CLK 2:1 1 GND CLK IAC 6 OSCILLATOR t 2 PKLMT + MOUT 5 4 3 12 14 CAI CAOUT RT CT Copyright © 2016, Texas Instruments Incorporated Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 7.3 Feature Description 7.3.1 ReferenceSectionandErrorAmplifier Thereferenceisahighlyaccurate7-Vreferencewithanaccuracyofthereferenceis1.5%. Theerroramplifierisaclassicvoltageerroramplifierandhasashortcircuitcurrentcapabilityof20mA. 7.3.2 ZeroPowerBlock When the output of the zero power comparator goes below 2.3 V, the zero power comparator latches the gate drivesignallow. 7.3.3 Multiplier The multiplier has 3 inputs. The inputs to the multiplier are VAOUT, the voltage amplifier error signal, IIAC, a representationoftheinputrectifiedAClinevoltage,andaninputvoltagefeedforwardsignal,VVFF. ThemultiplierperformsthecalculationinEquation3. IMOUNT=IAC×(VVAOUT–1)/(K×VVff2) where • K=1/V (3) As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation operation. 7.3.4 OutputOvervoltageProtection When the output voltage exceeds the OVP threshold, the IC stops switching. The OVP reference is at 1.07%. Thereisalsoa500mVofhysteresisatthepin. 7.3.5 PinDescriptions 7.3.5.1 CAI Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting input (MOUT)remainfunctionaldowntoandbelowGND. 7.3.5.2 CAOUT This is the output of a wide bandwidth operational amplifier that senses line current and commands the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed between CAOUTandMOUT. 7.3.5.3 CT AcapacitorfromCTtoGNDsetsthePWMoscillatorfrequencyaccordingtoEquation4: § 0.6 • f |¤ ‚ 'RTuCT„ (4) TheleadfromtheoscillatortimingcapacitortoGNDshouldbeasshortanddirectaspossible. 10 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 Feature Description (continued) 7.3.5.4 DRVOUT The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. To avoid the excessive overshoot of the DRVOUT while driving a capacitive load, a series gate current-limiting/damping resistor is recommended to prevent interaction between the gate impedance and the output driver. The value of the series gate resistor is based on the pulldown resistance (R which is 4 Ω typical), the maximum VCC voltage pulldown (VCC), and the required maximum gate drive current (I ). Using Equation 5, a series gate resistance of MAX resistance 11 Ω would be required for a maximum VCC voltage of 18 V and for 1.2 A of maximum sink current. Thesourcecurrentwillbelimitedtoapproximately900mA(basedontheRpullupof9-Ωtypical). VCC(cid:16)(cid:11)IMAXuRpulldown(cid:12) RGATE IMAX (5) 7.3.5.5 GND All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with a 0.1-µF orlargerceramiccapacitor. 7.3.5.6 IAC This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (I ) to multiplier output. The recommended maximum I is IAC IAC 500µA. 7.3.5.7 MOUT The output of the analog multiplier and the inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this is a high-impedance input so the amplifier can be configured as a differential amplifier. This configuration improves noise immunity and allows for the leading-edge modulation operation.Themultiplieroutputcurrentislimitedto(2 × I ).ThemultiplieroutputcurrentisgivenbyEquation6: IAC IMOUT IIACu(VVAOUT(cid:16)1) VVFF2uK (6) 1 K = V where isthemultipliergainconstant. 7.3.5.8 OVP/EN A window comparator input that disables the output driver if the boost output voltage is a programmed level abovethenominalordisablesboththePFCoutputdriverandresetsSSifpulledbelow1.9V(typical). 7.3.5.9 PKLMT The threshold for peak limit is 0 V. Use a resistor divider from the negative side of the current sense resistor to VREF to level shift this signal to a voltage level defined by the value of the sense resistor and the peak current limit.PeakcurrentlimitisreachedwhenPKLMTvoltagefallsbelow0V. 7.3.5.10 RT A resistor from RT to GND is used to program oscillator charging current. TI recommends a resistor between 10kΩand100kΩ.Nominalvoltageonthispinis3V. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com Feature Description (continued) 7.3.5.11 SS VSS is discharged for VVCC low conditions. When enabled, SS charges an external capacitor with a current source. This voltage is used as the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a V dropout, the OVP/EN is forced below 1.9 V (typ), SS quickly discharges to disable VCC thePWM. NOTE In an open-loop test circuit, grounding the SS pin does not ensure 0% duty cycle. See the applicationsectionfordetails. 7.3.5.12 VAOUT This is the output of the operational amplifier that regulates output voltage. The voltage amplifier output is internallylimitedtoapproximately5.5Vtopreventovershoot. 7.3.5.13 VCC Connect to a stable source of at least 20 mA from 10 V to 17 V for normal operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless V exceeds the upper undervoltage VCC lockoutvoltagethresholdandremainsabovethelowerthreshold. 7.3.5.14 VFF The RMS voltage signal generated at this pin by mirroring 1/2 of the I into a single pole external filter. At low IAC line,theVFFvoltageshouldbe1.4V. 7.3.5.15 VSENSE This is normally connected to a compensation network and to the boost converter output through a divider network. 7.3.5.16 VREF VREF is the output of an accurate 7.5-V voltage reference. This output is capable of delivering 20 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled and remains at 0 V when V VCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger ceramic capacitor for best stability. SeeFigure13andFigure14forVREFlineandloadregulationcharacteristics. 12 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 7.4 Device Functional Modes 7.4.1 TransitionModeControl The boost converter, the most common topology used for power factor correction, can operate in two modes: continuous conduction code (CCM) and discontinuous conduction mode (DCM). Transition mode control, also referred to as critical conduction mode (CRM) or boundary conduction mode, maintains the converter at the boundarybetweenCCMandDCMbyadjustingtheswitchingfrequency. The CRM converter typically uses a variation of hysteretic control, with the lower boundary equal to zero current. It is a variable frequency control technique that has inherently stable input current control while eliminating reverse recovery rectifier losses. As shown in Figure 7, the switch current is compared to the reference signal (output of the multiplier) directly. This control method has the advantage of simple implementation and good powerfactorcorrection. L VAC D Q Load C R IAC GateDriver IAC ZCD S Q Logic X÷ MULT IMO + R VEA X + UDG−02124 VREF Figure7. BasicBlockDiagramofCRMBoostPFC Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com Device Functional Modes (continued) The power stage equations and the transfer functions of the CRM are the same as the CCM. However, implementations of the control functions are different. Transition mode forces the inductor current to operate just at the border of CCM and DCM. The current profile is also different, and affects the component power loss and filtering requirements. The peak current in the CRM boost is twice the amplitude of CCM, leading to higher conduction losses. The peak-to-peak ripple is twice the average current, which affects MOSFET switching losses andmagneticsAClosses. For low to medium power applications up to approximately 300 W, the CRM boost has an advantage in losses. The filtering requirement is not severe, and therefore is not a disadvantage. For medium to higher power applications, where the input filter requirements dominate the size of the magnetics, the CCM boost is a good choice due to lower peak currents (which reduces conduction losses) and lower ripple current (which reduces filter requirements). The main tradeoff in using CRM boost is lower losses due to no reverse recovery in the boostdiodevshigherrippleandpeakcurrents. IAVERAGE (a) CCM IPEAK IAVERAGE (b) DCM IPEAK IAVERAGE Note:OperatingFrequency>>120Hz (C) CRM UDG−02123 Figure8. PFCInductorCurrentProfiles 14 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The UCC3817 is a BiCMOS average current mode boost controller for high power factor, high efficiency preregulator power supplies. Figure 9 shows the UCC3817 in a 250-W PFC preregulator circuit. Off-line switching power converters normally have an input current that is not sinusoidal. The input current waveform has a high harmonic content because current is drawn in pulses at the peaks of the input voltage waveform. An active power-factor correction circuit programs the input current to follow the line voltage, forcing the converter to look like a resistive load to the line. A resistive load has 0° phase displacement between the current and voltage waveforms. Power factor can be defined in terms of the phase angle between two sinusoidal waveforms of the samefrequency: PF=cosθ Therefore, a purely resistive load would have a power factor of 1. In practice, power factors of 0.999 with THD (total harmonic distortion) of less than 3% are possible with a well-designed circuit. The following guidelines are providedtodesignPFCboostconvertersusingtheUCC3817. NOTE Schottky diodes, D5 and D6, are required to protect the PFC controller from electrical over stressduringsystempowerup. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 8.2 Typical Application R16 C10 C11 100: 1PF 1PF VCC R15 D7 24k D8 R21 R13 383k 383k L1 IAC 1mH R18 24k D1 VO 8A, 600V F1 AC2 + D2 C14 C13 6A, 600V VLINE 1.5PF 0.47PF 85-270 VAC 400V D3 600V Q1 VOUT C12 385V-DC AC1 R14 220PF 0.25: 450V 6A 600V 3W t R17 UCC3817 20: R12 R9 R10 2k 4.02k 4.02k 1 GND DRVOUT 16 D4 VCC C3 2 PKLIMIT 1PF CER R11 D5 VCC 15 10k 3 CAOUT C2 100PF AI EI 4 CAI C1 560pF VREF 5 MOUT CT 14 R8 12k C9 1.2nF C4 0.01PF 6 IAC SS 13 C8 270pF R1 12k D6 C7 150nF RT 12 R7 100k C15 2.2PF VSENSE 11 R2 R19 VO 7 VAOUT R3 20k 499k 499k C6 2.2PF R4 8 VFF R20 274k 249k OVP/EN 10 R6 30k C5 1PF R5 10k VREF 9 VREF Copyright © 2016, Texas Instruments Incorporated Figure9. TypicalApplicationCircuit 8.2.1 DesignRequirements Table1liststheparametersforthisapplication. Table1.DesignParameters PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VIN InputRMSvoltage 85 270 V Inputfrequency 50/60 Hz VOUT OutputVoltage 385 420 V POUT OutputPower 250 W HoldupTime Alllineandloadconditions 16 ms Efficiency Efficiencyat85Vrms,100%Load 91% 16 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 Typical Application (continued) Table1.DesignParameters(continued) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT THDatLowLine 85Vrms=100%Load 5% THDatHighLine 265Vrms,100%Load 15% 8.2.2 DetailedDesignProcedure 8.2.2.1 PowerStage 8.2.2.1.1 L BOOST Theboostinductorvalueisdeterminedby: (V × D) IN(min) L = BOOST (ΔI × fs) where • Disthedutycycle • ΔIistheinductorripplecurrent • f istheswitchingfrequency (7) S For the example circuit in Figure 9, a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688, and a minimum input voltage of 85 V give a boost inductor value of approximately 1 mH. RMS The values used in this equation are at the peak of low line, where the inductor current and its ripple are at a maximum. 8.2.2.1.2 C OUT Two main criteria, the capacitance and the voltage rating, dictate the selection of the output capacitor. The value of capacitance is determined by the holdup time required for supporting the load after input ac voltage is removed. Holdup is the amount of time that the output stays in regulation after the input has been removed. For thecircuitinFigure9,thedesiredholduptimeisapproximately16ms.Expressingthecapacitorvalueintermsof outputpower,outputvoltage,andholduptimegivestheequation: (2 × P × Δt) OUT C = OUT (V 2 – V 2) OUT OUT(min) (8) In practice, the calculated minimum capacitor value may be inadequate, because output ripple voltage specifications limit the amount of allowable output capacitor ESR. Attaining a sufficiently low value of ESR often requires the use of a much larger capacitor value than calculated. The amount of output capacitor ESR allowed isdeterminedbydividingthemaximumspecifiedoutputripplevoltagebytheinductorripplecurrent.Inthedesign in Figure 9, holdup time is the dominant determining factor, and a 220-μF, 450-V capacitor was chosen for the outputvoltagelevelof385VDCat250W. 8.2.2.2 Softstart Thesoftstartcircuitrypreventsovershootoftheoutputvoltageduringstart up by bringing up the voltage amplifier output (V ) slowly, which allows for the PWM duty cycle to increase slowly. Use the following equation to VAOUT selectacapacitorforthesoftstartpin. Inthisexample,t isequalto7.5ms,whichwouldyieldaC of10nF. DELAY SS 10µA × t DELAY C = SS 7.5V (9) In an open-loop test circuit, shorting the softstart pin to ground does not ensure 0% duty cycle. This is due to the input offset voltage of the current amplifier, which could force the current amplifier output high or low depending on the polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and biascurrenttoovercometheoffsetvoltageofthecurrentamplifier. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 8.2.2.3 Multiplier The output of the multiplier of the UCC3817 is a signal representing the desired input line current. The multiplier isaninputtothecurrentamplifier,whichprogramsthecurrentlooptocontroltheinputcurrenttogivehighpower factor operation. As such, the proper functioning of the multiplier is key to the success of the design. The inputs to the multiplier are VAOUT, the voltage amplifier error signal, I , a representation of the input rectified ac line IAC voltage,andaninputvoltagefeedforwardsignal,V .Theoutputofthemultiplier,I ,canbeexpressedas: VFF MOUT (V – 1) VAOUT I = I × MOUT IAC 2 K ×V VFF where • Kisaconstanttypicallyequalto1/V (10) Electrical Characteristics covers all the required operating conditions for designing with the multiplier. Additionally, Figure 3, Figure 4, and Figure 5 provide typical multiplier characteristics over its entire operating range. The I signal is obtained through a high-value resistor connected between the rectified ac line and the IAC pin IAC of the UCC381x. This resistor (R ) is sized to give the maximum I current at high line. For the UCC381x, the IAC IAC maximum I current is approximately 500 μA. A higher current than this can drive the multiplier out of its linear IAC range.Asmallercurrentlevelisfunctional,butnoisecanbecomeanissue,especiallyatlowinputline.Assuming a universal line operation of 85 V to 265 V gives an R value of 750 kΩ. Because of voltage rating RMS RMS IAC constraints of standard 1/4-W resistor, use a combination of lower value resistors connected in series to give the required resistance and distribute the high voltage amongst the resistors. For the design example in Figure 9, two383-kΩ resistorsareusedinseries. The current into the IAC pin is mirrored internally to the VFF pin, where it is filtered to produce a voltage feed forward signal proportional to line voltage. The VFF voltage keeps the power stage gain constant, and to provide input power limiting. Refer to Texas Instruments application note DN-66 UC3854A/B and UC3855A/B Provide Power Limiting with Sinusoidal Input (SLUA196) for detailed explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF resistor (R ) to provide power limiting where VFF V is the minimum RMS input voltage, and R is the total resistance connected between the IAC pin and IN(min) IAC therectifiedlinevoltage. R = 1.4V ≈ 30kΩ VFF V ×0.9 IN(min) 2×R IAC (11) 18 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 Because the VFF voltage is generated from line voltage, it must be adequately filtered to reduce total harmonic distortion caused by the 120-Hz rectified line voltage. Refer to Unitrode Power Supply Design Seminar, SEM−700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter is adequate forthedesigninFigure9.Assumingthatanallocationof1.5%totalharmonicdistortionfromthisinputisallowed, and that the second harmonic ripple is 66% of the input AC line voltage, the amount of attenuation required by thisfilteris: 1.5%/66%=0.022 Witharipplefrequency(f )of120Hzandanattenuationof0.022,thepoleofthefilter(f )mustbeplacedat: R P f =120Hz×0.022≈2.6Hz (12) P The following equation can be used to select the filter capacitor (C ) required to produce the desired low pass VFF filter. C =1/(2×π×R ×f )≈2.2µF (13) VFF VFF P The R resistor is sized to match the maximum current through the sense resistor to the maximum multiplier MOUT current.Themaximummultipliercurrent,orI ,isdeterminedbytheequation: MOUT(max) IIAC@VIN(min)× (VVAOUT(max) – 1V) I = MOUT(max) 2 K × V VFF (min) (14) I forthedesigninFigure9 isapproximately315μA.TheR resistoristhendeterminedby: MOUT(max) MOUT R =V /I (15) MOUT RSENSE MOUT(max) In this example, V is selected to give a dynamic operating range of 1.25 V, which gives an R of RSENSE MOUT approximately3.91kΩ. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 8.2.2.4 VoltageLoop The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of thelinefrequency.Thisrippleisfedbackthroughtheerroramplifier,andappearsasa3rd-harmonicrippleatthe input to the multiplier. The voltage loop must be compensated, not just for stability, but also to attenuate the contributionofthisrippletothetotalharmonicdistortionofthesystem(refertoFigure10). VOUT Cf Rf CZ RIN − RD + VREF Figure10. VoltageAmplifierConfiguration The gain of the voltage amplifier, G , is determined by first calculating the amount of ripple present on the VA outputcapacitor.Thepeakvalueofthesecondharmonicvoltageisgivenbytheequation: V =P /(2π×f ×C ×V ) (16) OPK IN R OUT OUT In this example, V is equal to 3.91 V. Assuming an allowable contribution of 0.75% (1.5% peak to peak) from OPK thevoltagelooptothetotalharmonicdistortionbudget,setthegainequalto: G =(ΔV )(0.015)/(2×V ) VA VAOUT OPK where • ΔV istheeffectiveoutputvoltagerangeoftheerroramplifier(5VfortheUCC3817) (17) VAOUT The network must realize this filter is comprised of an input resistor, R , and feedback components C, C , and IN f Z R. The value of R is already determined, because of its function as one half of a resistor divider from V f IN OUT feedingbacktothevoltageamplifierforoutputvoltageregulation.Inthiscase,thevaluewaschosentobe1MΩ. This high value was chosen to reduce power dissipation in the resistor. In practice, the resistor value would be realized by the use of two 500-kΩ resistors in series, because of the voltage rating constraints of most standard 1/4-Wresistors.ThevalueofC isdeterminedbytheequation: f C =1/(2π×f ×G ×R ) (18) f R VA IN 20 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 In this example, C equals 150 nF. Resistor R sets the dc gain of the error amplifier and thus determines the f f frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop equation to one, and solving for the crossover frequency. The frequency, expressed in terms of input power, can becalculatedbytheequation: f 2=P /(2π2×ΔV ×V ×R ×C ×C) (19) VI IN VAOUT OUT IN OUT f f for this converter is 10 Hz. A derivation of this equation can be found in the Unitrode Power Supply Design VI Seminar SEM1000, Topic 1, [A 250-kHz, 500-W Power Factor Correction Circuit Employing Zero Voltage Transitions]. SolvingforR becomes: f R =1/(2π×f ×C) (20) f VI f orR equals100kΩ. f Due to the low output impedance of the voltage amplifier, capacitor C was added in series with R to reduce Z F loading on the voltage divider. To ensure the voltage loop crossed over at f , C was selected to add a zero at a VI Z 10thoff .ForthedesigninFigure9,a2.2-μFcapacitorwaschosenforC .Thefollowingequationcancalculate VI Z C . Z 1 C = Z f VI 2 ×π × × R 10 f (21) Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 8.2.2.5 CurrentLoop Thegainofthepowerstageis: G (s)=(V ×R )/(s×L ×V ) (22) ID OUT SENSE BOOST P R has been chosen to give the desired differential voltage for the current sense amplifier at the desired SENSE current limit point. In this example, a current limit of 4 A and a reasonable differential voltage to the current amp of 1 V gives a R value of 0.25 Ω. V in this equation is the voltage swing of the oscillator ramp, 4 V for the SENSE P UCC3817. Setting the crossover frequency of the system to 1/10th of the switching frequency, or 10 kHz, requires a power stage gain at that frequency of 0.383. For the system to have a gain of 1 at the crossover frequency, the current amplifier must have a gain of 1/G at that frequency. G , the current amplifier gain is ID EA then: G =(1/G )=(1/0.383)=2.611 (23) EA ID R is the R resistor, previously calculated to be 3.9 kΩ. (refer to Figure 11). The gain of the current amplifier I MOUT isR/R,somultiplyingR byG givesthevalueofR,whichinthiscaseisapproximately12kΩ.Settingazeroat f I I EA f thecrossoverfrequencyandapoleathalftheswitchingfrequencycompletesthecurrentloopcompensation. C =1/(2×π×R ×f ) (24) Z f C C =1/(2×π×R ×f /2) (25) P f S C P Rf CZ R I − CAOUT + Figure11. CurrentLoopCompensation The UCC3817 current amplifier has the input from the multiplier applied to the inverting input. This change in architecture from previous Texas Instruments PFC controllers improves noise immunity in the current amplifier and adds a phase inversion into the control loop. The UCC3817 takes advantage of this phase inversion to implement leading-edge duty cycle modulation. Synchronizing a boost PFC controller to a downstream dc-to-dc controller reduces the ripple current seen by the bulk capacitor between stages, reducing capacitor size and cost and reducing EMI. This is explained in greater detail in Capacitor Ripple Reduction. The UCC3817 current amplifierconfigurationisshowninFigure12. LBOOST VOUT − RSENSE + QBOOST Zf MULT PWM CA COMPARATOR − − + + Figure12. UCC3817CurrentAmplifierConfiguration 22 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 8.2.2.6 StartUp The UCC3818 version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC3817 has an internal shunt regulator, enabling the device to be powered from bootstrap circuitry as shown in Figure 9. The current drawn by the UCC3817 during undervoltage lockout, or start-up current, is typically 150 μA. Once VCC is above the UVLO threshold, the device is enabled and draws 4 mA typically. A resistor connected between the rectified ac line voltage and the VCC pin provides current to the shunt regulator during power up. Once the circuit is operational, the bootstrap winding of the inductor provides the VCC voltage. Sizing of the start-upresistorisdeterminedbythestart-uptimerequirementofthesystemdesign. I =C(ΔV/Δt) (26) C R=(V ×0.9)/I RMS C where • I isthechargecurrent C • CisthetotalcapacitanceattheVCCpin • ΔVistheUVLOthreshold • Δtistheallowedstart-uptime (27) Assuming a 1 second allowed start-up time, a 16-V VCC turn-on threshold, and a total VCC capacitance of 100 μF, a resistor value of 51 kΩ is required at a low line input voltage of 85 V . The IC start-up current is RMS sufficientlysmallastobeignoredinsizingthestart-upresistor. 8.2.3 ApplicationCurves 100 1.2 VIN = 85 V 1.12 VIN = 175 V VIN = 265 V 95 1.04 0.96 y (%) 90 ctor 0.88 c a cien er F 0.8 Effi 85 ow P 0.72 0.64 80 0.56 VIN = 85 V VIN = 175 V 0.48 VIN = 265 V 75 25 50 75 100 125 150 175 200 225 250 0.4 Output Power 25 50 75 100 125 150 175 200 225 250 275 D001 Output Power (W) D001 Figure13.EfficiencyvsOutputPower Figure14.PowerFactorvsOutputPower Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 9 Power Supply Recommendations 9.1 Power Switch Selection As in any power supply design, tradeoffs between performance, cost, and size must be made. When selecting a power switch, calculate the total power dissipation in the switch for several different devices at the switching frequencies being considered for the converter. Total power dissipation in the switch is the sum of switching loss and conduction loss. Switching losses are the combination of the gate charge loss, C loss and turnon and OSS turnofflosses: P =Q ×V ×f (28) GATE GATE GATE S P =1/2×C ×V2 ×f (29) COSS OSS OFF S P +P =1/2×V ×I ×(t +t )×f ON OFF OFF L ON OFF S where • Q isthetotalgatecharge GATE • V isthegatedrivevoltage GATE • f istheclockfrequency S • C isthedrainsourcecapacitanceoftheMOSFET OSS • I isthepeakinductorcurrent L • t andt aretheswitchingtimes(estimatedusingdeviceparametersR ,Q andV ) ON OFF GATE GD TH • V isthevoltageacrosstheswitchduringtheofftime;inthiscaseV =V (30) OFF OFF OUT Conduction loss is calculated as the product of the R of the switch (at the worst case junction temperature) DS(on) andthesquareofRMScurrent: P =R ×K×I2 COND DS(on) RMS where • Kisthetemperaturefactorfoundinthemanufacturer’sR vs.junctiontemperaturecurves (31) DS(on) Calculating these losses and plotting against frequency gives a curve that enables the designer to determine either which device has the best performance at the desired switching frequency, or which switching frequency has the least total loss for a particular power switch. For the design example in Figure 9, an IRFP450 HEXFET from International Rectifier was chosen because of its low R and its V rating. The IRFP450 R of 0.4 DS(on) DSS DS(on) ΩandthemaximumV of500Vmadeitanidealchoice.Anexcellentreviewofthisprocedurecanbefoundin DSS the Unitrode Power Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W, [Multiple Output High DensityDC/DCConverter]. 24 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 10 Layout 10.1 Layout Guidelines 10.1.1 CapacitorRippleReduction ForapowersystemwherethePFCboostconverterisfollowedbyadc-to-dcconverterstage,itcanbebeneficial to synchronize the two converters. In addition to the usual advantages such as noise reduction and stability, proper synchronization can significantly reduce the ripple currents in the output capacitor of the boost circuit. Figure 15 helps illustrate the impact of proper synchronization, by showing a PFC boost converter together with thesimplifiedinputstageofaforwardconverter. The capacitor current during a single switching cycle depends on the status of the switches Q1 and Q2, and is shown in Figure 16. With a synchronization scheme that maintains conventional trailing-edge modulation on both converters, the capacitor current ripple is highest. The greatest ripple current cancellation is attained when the overlap of Q1 offtime and Q2 ontime is maximized. One method of achieving this is to synchronize the turnon of the boost diode (D1) with the turnon of Q2. This approach implies that the leading edge of the boost converter is pulse-width modulated, while the forward converter is modulated with traditional trailing-edge PWM. The UCC3817 is designed as a leading-edge modulator with easy synchronization to the downstream converter to facilitate this advantage. Table 2 compares the I for D1/Q2 synchronization as offered by UCC3817 versus CB(rms) theI fortheotherextremeofsynchronizingtheturnonofQ1andQ2fora200-WpowersystemwithaV CB(rms) BST of385V. Figure15. SimplifiedRepresentationofa2-StagePFCPowerSupply Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com Layout Guidelines (continued) Figure16. TimingWaveformsforSynchronizationScheme Table2.EffectsofSynchronizationonBoostCapacitorCurrent V =85V V =120V V =240V IN IN IN D(Q2) Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 0.35 1.491A 0.835A 1.341A 0.663A 1.024A 0.731A 0.45 1.432A 0.93A 1.276A 0.664A 0.897A 0.614A Table 2 illustrates that the boost capacitor ripple current can be reduced by approximately 50% at nominal line, and about 30% at high line with the synchronization scheme facilitated by the UCC3817. Figure 17 shows the suggested technique for synchronizing the UCC3817 to the downstream converter. With this technique, maximumripplereductionasshowninFigure16isachievable.Theoutputcapacitancevaluecanbesignificantly reduced if its choice is dictated by ripple current, or the capacitor life can be increased as a result. In cost- sensitivedesignswhereholduptimeisnotcritical,thisisasignificantadvantage. An alternative method of synchronization makes it possible to achieve the same ripple reduction. In this method, the turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and maintains trailing edge modulation on both converters, the synchronization is more difficult to achieve, and thecircuitcanbecomesusceptibletonoiseasthesynchronizingedgeitselfisbeingmodulated. Gate Drive From Down Stream PWM C1 UCC3817 D2 CT C D1 T R T RT Figure17. SynchronizingtheUCC3817toaDown-StreamConverter 26 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 10.2 Layout Example D2 V0 GND HIGH TEMPERATURE - SEE EVM WARNINGS AND R18R15 RESTRICTIONS HS1 D1 Q1 D7 R14 HIGH VOLTAGE - C12 SEE EVM WARNINGS AND XL1 RESTRICTIONS C10 R16 R10 D8 L1 C11 HIGH VOLTAGE - AC2 C13 R21 R9 C2 R17GND SEE EVM WARNINGS AND RESTRICTIONS R11 C3 D4 R13 C9 U1 R22 VCC XC12 D3 C8 C1 AC1 R12 R8 C4 SYNC C15 C14 R1 R2 C7 R19 R3 C6 R7 R4 FA1 D5 D6 C5 R20 UCC3817 EVALUATION BOARD R6 R5 Figure18. UCC3817EVMEvaluationBoardLayoutAssembly Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: 1. DifferencesBetweenUCC3817A/18A/19AandUCC3817/18/19 (SLUA294) 2. UCC3817BiCMOSPowerFactorPreregulatorEvaluationBoard (SLUU077) 3. SynchronizingaPFCControllerfromaDownStreamControllerGateDrive (SLUA245) 4. Seminartopic,HighPowerFactorSwitchingPreregulatorDesignOptimization,L.H.Dixon,SEM-700,1990. 5. Seminartopic,HighPowerFactorPreregulatorforOff-lineSupplies,L.H.Dixon,SEM-600,1988. 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC2817 Clickhere Clickhere Clickhere Clickhere Clickhere UCC2818 Clickhere Clickhere Clickhere Clickhere Clickhere UC3817 Clickhere Clickhere Clickhere Clickhere Clickhere UC3818 Clickhere Clickhere Clickhere Clickhere Clickhere 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 28 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

UCC2817,UCC2818,UCC3817,UCC3818 www.ti.com SLUS395K–FEBRUARY2000–REVISEDOCTOBER2015 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UCC2817 UCC2818 UCC3817 UCC3818

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2817D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2817D & no Sb/Br) UCC2817DTR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2817D & no Sb/Br) UCC2817DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2817DW & no Sb/Br) UCC2817N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2817N & no Sb/Br) UCC2818D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2818D & no Sb/Br) UCC2818DTR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2818D & no Sb/Br) UCC2818DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2818DW & no Sb/Br) UCC2818DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2818DW & no Sb/Br) UCC2818N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2818N & no Sb/Br) UCC2818PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 2818PW & no Sb/Br) UCC3817D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3817D & no Sb/Br) UCC3817DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3817D & no Sb/Br) UCC3817DTR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3817D & no Sb/Br) UCC3817DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3817DW & no Sb/Br) UCC3817DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3817DW & no Sb/Br) UCC3817N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3817N & no Sb/Br) UCC3817NG4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3817N & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC3818D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3818D & no Sb/Br) UCC3818DTR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3818D & no Sb/Br) UCC3818DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3818D & no Sb/Br) UCC3818DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3818DW & no Sb/Br) UCC3818DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3818DW & no Sb/Br) UCC3818DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3818DW & no Sb/Br) UCC3818N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3818N & no Sb/Br) UCC3818NG4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3818N & no Sb/Br) UCC3818PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 3818PW & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC2818 : •Enhanced Product: UCC2818-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC2817DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2818DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2818DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 UCC3817DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC3817DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 UCC3818DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC3818DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC2817DTR SOIC D 16 2500 333.2 345.9 28.6 UCC2818DTR SOIC D 16 2500 333.2 345.9 28.6 UCC2818DWTR SOIC DW 16 2000 367.0 367.0 38.0 UCC3817DTR SOIC D 16 2500 333.2 345.9 28.6 UCC3817DWTR SOIC DW 16 2000 367.0 367.0 38.0 UCC3818DTR SOIC D 16 2500 333.2 345.9 28.6 UCC3818DWTR SOIC DW 16 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated