Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 UCCx813-x Low-Power Economy BiCMOS Current-Mode PWM 1 Features 3 Description • 100-µAtypicalstartingsupplycurrent The UCC3813-x device family of high-speed, low- 1 power integrated circuits contains all of the control • 500-µAtypicaloperatingsupplycurrent and drive components required for off-line and DC-to- • Operationto1MHz DC fixed-frequency current-mode switching power • Internalsoftstart supplieswithminimalpartscount. • Internalfaultsoftstart These devices have the same pin configuration as • Internalleading-edgeblankingofthecurrent- the UC384x device family, and also offer the added features of internal full-cycle soft start and internal sensesignal leading-edgeblankingofthecurrent-senseinput. • 1-Atotem-poleoutput The UCC3813-x device family offers a variety of • 70-nstypicalresponsefromcurrent-sensetogate- package options, temperature-range options, choice driveoutput of maximum duty cycle, and choice of critical voltage • 1.5%ToleranceVoltageReference levels. Devices with lower reference voltage such as • SamePinoutastheUCC3802device,UC3842 the UCC3813-3 and UCC3813-5 fit best into battery device,andUC3842Adevicefamilies operated systems, while the higher reference and the higher UVLO hysteresis of the UCC3813-2 device 2 Applications and UCC3813-4 device make these ideal choices for useinoff-linepowersupplies. • Switchmodepowersupplies(SMPS) The UCC2813-x device series is specified for • DC-DCconverters operation from –40°C to 85°C and the UCC3813-x • Powermodules device series is specified for operation from 0°C to • IndustrialPSUs 70°C. • BatteryoperatedPSUs DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) PDIP(8) 6.35mm×9.81mm UCC2813-x, SOIC(8) 3.91mm×4.90mm UCC3813-x TSSOP(8) 4.40mm×3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. BlockDiagram FB COMP CS 2 1 3 7 VCC UCCx813-1 Leading Edge UCCx813-4 VCC Over Cu1r.r5e nVt REF/2 Blanking UCCOxn8ly13-5 OK T Q S Q R Oscillator S Q 6 OUT 4 V S Q Voltage R Reference PWM 13.5 V R Latch REF OK 0.5 V Full Cycle Soft Start Logic Power τ=4ms 1V 5 GND 8 4 REF Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................20 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 22 3 Description............................................................. 1 9.1 ApplicationInformation............................................22 4 RevisionHistory..................................................... 2 9.2 TypicalApplication..................................................22 5 DeviceComparisonTable..................................... 3 10 PowerSupplyRecommendations..................... 31 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 32 11.1 LayoutGuidelines.................................................32 7 Specifications......................................................... 4 11.2 LayoutExample....................................................33 7.1 AbsoluteMaximumRatings......................................4 12 DeviceandDocumentationSupport................. 34 7.2 ESDRatings..............................................................4 7.3 RecommendedOperatingConditions.......................4 12.1 DocumentationSupport........................................34 7.4 ThermalInformation..................................................5 12.2 RelatedLinks........................................................34 7.5 ElectricalCharacteristics...........................................5 12.3 ReceivingNotificationofDocumentationUpdates34 7.6 TypicalCharacteristics..............................................7 12.4 CommunityResources..........................................34 12.5 Trademarks...........................................................34 8 DetailedDescription.............................................. 9 12.6 ElectrostaticDischargeCaution............................34 8.1 Overview...................................................................9 12.7 Glossary................................................................34 8.2 FunctionalBlockDiagram.........................................9 13 Mechanical,Packaging,andOrderable 8.3 FeatureDescription...................................................9 Information........................................................... 35 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionE(August,2016)toRevisionF Page • AddedNotesunderAbsMaxSection.................................................................................................................................... 4 • ChangedPowerSupplysectiontoreflectpowerupofthedevice....................................................................................... 31 ChangesfromRevisionD(May2013)toRevisionE Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection. ................................................................................................ 1 ChangesfromRevisionC(August2010)toRevisionD Page • Addedtemperaturerangetablenotetosecondpartoforderinginformationtableforclarityinnewdatasheetformat........3 • AddedTI'sgeneralAbsoluteMaximumRatingstablenotetoendofABSOLUTEMAXIMUMRATINGStable.................... 4 • AddedThermalInformationTable.......................................................................................................................................... 5 • AddedUCCX813-3toTotalvariationtestconditionlinecontainingUCCx813-5inELECTRICAL CHARACTERISTICStable..................................................................................................................................................... 5 • ChangedpartnumbersinDeadTimevsC ,R =100kgraphinAPPLICATIONINFORMATION...................................... 7 T T • ChangedlayoutfromUnitrodeProductsdatasheettoTIdatasheet...................................................................................... 7 ChangesfromRevisionB(April2008)toRevisionC Page • AddedAnaloginputsRCandCOMPintheAbsoluteMaximumRatingstable..................................................................... 4 • AddedclarificationtoAnalogInputsmin-maxrangeintheAbsoluteMaximumRatingstable.............................................. 4 2 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 5 Device Comparison Table PARTNUMBER(1) MAXIMUMDUTY REFERENCE TURNON TURNOFF UNIT CYCLE VOLTAGE THRESHOLD THRESHOLD UCCx813-0 100% 5 7.2 6.9 V UCCx813-1 50% 5 9.4 7.4 V UCCx813-2 100% 5 12.5 8.3 V UCCx813-3 100% 4 4.1 3.6 V UCCx813-4 50% 5 12.5 8.3 V UCCx813-5 50% 4 4.1 3.6 V (1) ThexinthepartnumberreferstotheoperatingtemperaturerangedifferencebetweentheUCC2813devicesandtheUCC3813 devices. 6 Pin Configuration and Functions NandDPackages PWPackage 8-PinPDIPandSOIC 8-PinTSSOP TopView TopView COMP 1 8 REF COMP 1 8 REF FB 2 7 VCC FB 2 7 VCC CS 3 6 OUT CS 3 6 OUT RC 4 5 GND RC 4 5 GND Not to scale Not to scale PinFunctions PIN I/O DESCRIPTION NAME NO. COMPistheoutputoftheerroramplifierandtheinputofthePWMcomparator.Feedbackloop COMP 1 O compensationisappliedbetweenthispinandtheFBpin. CS 3 I CSistheinputtothecurrent-sensecomparators:thePWMcomparatorandtheovercurrentcomparator. FB 2 I FBistheinvertinginputoftheerroramplifier. GND 5 — GNDisthereferencegroundandpowergroundforallfunctionsofthisdevice. OUT 6 O OUTistheoutputofahigh-currentpowerdrivercapableofdrivingthegateofapowerMOSFET. RCistheoscillatortimingprogrammingpin.Anexternalresistorandcapacitorareappliedtothisinputto RC 4 I programtheswitchingfrequencyandmaximumduty-cycle. REFisthevoltagereferencefortheerroramplifierandmanyotherfunctions,andisthebiassourceforlogic REF 8 O functionsofthisdevice. VCCisthebias-powerinputforthisdevice.Innormaloperation,VCCisconnectedtoavoltagesource VCC 7 I throughacurrent-limitingresistor. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT VCCvoltage(3) 12 V VCCcurrent 30 mA OUTcurrent ±1 A OUTenergy(capacitiveload) 20 µJ 6.3or Analoginputs FB,CS,RC,COMP –0.3 V +0.3(4) V VCC Npackage 1 PowerdissipationatT <25°C W A Dpackage 0.65 Leadtemperature,soldering(10s) 300 °C Junctiontemperature –55 150 °C Storagetemperature,T –65 150 °C stg (1) AllvoltagesarewithrespecttoGND.Allcurrentsarepositiveintothespecifiedterminal. (2) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (3) InnormaloperationVccispoweredthroughacurrentlimitresistor.TheresistormustbesizedsothattheVCCvoltageunderall operatingconditionsisbelow12Vbutabovetheturnoffthreshold.Absolutemaximumof12VapplieswhenVCCisdrivenfromalow impedancesourcesuchthatICCdoesnotexceed30mA.FailuretolimitVCCandICCtotheselimitsmayresultinpermanentdamage ofthedevice.ThisisfurtherdiscussedinthePowerSupplyRecommendations (4) Whicheverissmaller. 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V VCCbiassupplyvoltagefromalowimpedancesource 11 V VCC I Supplybiascurrent 25 mA VCC V Gatedriveroutputvoltage –0.1 V V OUT VCC I AverageOUTpincurrent 20 mA OUT I REFpinoutputcurrent 5 mA REF 6or Voltageonanalogpins FB,CS,RC,COMP –0.1 V (1) V VCC f Oscillatorfrequency 1 MHz OSC (1) Whicheverissmaller. 4 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 7.4 Thermal Information UCCx813-x THERMALMETRIC(1) P(PDIP) D(SOIC) PW(TSSOP) UNIT 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 50.9 107.5 153.8 °C/W θJA R Junction-to-case(top)thermalresistance 40.3 49.3 38.4 °C/W θJC(top) R Junction-to-boardthermalresistance 28.1 48.7 83.8 °C/W θJB ψ Junction-to-topcharacterizationparameter 17.6 6.6 2.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 28 48 82 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 7.5 Electrical Characteristics Unlessotherwisestated,thesespecificationsapplyfor–40°C≤T ≤85°CfortheUCC2813-xdevice;0°C≤T ≤70°Cforthe A A UCC3813-xdevice,T =T ;V =10V(1);R =100kΩfromREFtoRC;C =330pFfromRCtoGND;0.1-µFcapacitor J A VCC T T fromVCCtoGND;0.1-µFcapacitorfromVREFtoGND. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT REFERENCE T =25°C,I=0.2mA,UCCx813-[0,1,2,4] 4.925 5 5.075 J Outputvoltage V T =25°C,I=0.2mA,UCCx813-[3,5] 3.94 4 4.06 J Loadregulation 0.2mA<I<5mA 10 30 mV UCCx813-[0,1,2,4](2) 4.84 5 5.1 Totalvariation V UCCx813-[3,5](2) 3.84 4 4.08 Outputnoisevoltage 10Hz≤f≤10kHz,T =25°C(3) 70 µV J Longtermstability T =125°C,1000hours(3) 5 mV A Outputshortcircuit –5 –35 mA OSCILLATOR UCCx813-[0,1,2,4](4) 40 46 52 Oscillatorfrequency kHz UCCx813-[3,5](4) 26 31 36 Temperaturestability Seenote (3) 2.5% Amplitudepeak-to-peak 2.25 2.4 2.55 V Oscillatorpeakvoltage 2.45 V ERRORAMPLIFIER V =2.5V;UCCx813-[0,1,2,4] 2.42 2.5 2.56 COMP Inputvoltage V V =2V;UCCx813-[3,5] 1.92 2 2.05 COMP Inputbiascurrent –2 2 µA Openloopvoltagegain 60 80 dB COMPsinkcurrent V =2.7V,V =1.1V 0.4 2.5 mA FB COMP COMPsourcecurrent V =1.8V,V =V –1.2V –0.2 –0.5 –0.8 mA FB COMP REF Gain-bandwidthproduct Seenote (3) 2 MHz PWM UCCx813-[0,2,3] 97% 99% 100% Maximumdutycycle UCCx813-[1,4,5] 48% 49% 50% Minimumdutycycle V =0V 0% COMP (1) AdjustVCCabovethestartthresholdbeforesettingat10V. (2) Totalvariationincludestemperaturestabilityandloadregulation. (3) Ensuredbydesign.Not100%testedinproduction. (4) OutputfrequencyfortheUCCx813-[0,2,3]deviceistheoscillatorfrequency.OutputfrequencyfortheUCCx813-[1,4,5]deviceisone-half theoscillatorfrequency. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com Electrical Characteristics (continued) Unlessotherwisestated,thesespecificationsapplyfor–40°C≤T ≤85°CfortheUCC2813-xdevice;0°C≤T ≤70°Cforthe A A UCC3813-xdevice,T =T ;V =10V(1);R =100kΩfromREFtoRC;C =330pFfromRCtoGND;0.1-µFcapacitor J A VCC T T fromVCCtoGND;0.1-µFcapacitorfromVREFtoGND. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTSENSE Gain Seenote (5) 1.1 1.65 1.8 V/V Maximuminputsignal V =5V(6) 0.9 1 1.1 V COMP Inputbiascurrent –200 200 nA CSblanktime 50 100 150 ns Overcurrentthreshold 1.32 1.55 1.7 V COMPtoCSoffset V =0V 0.45 0.9 1.35 V CS OUTPUT I=20mA,allparts 0.1 0.4 I=200mA,allparts 0.35 0.9 OUTlowlevel V I=50mA,V =5V,UCCx813-[3,5] 0.15 0.4 VCC I=20mA,VCC=0V,allparts 0.7 1.2 I=–20mA,allparts 0.15 0.4 V – VCC OUThighV I=–200mA,allparts 1 1.9 V OUT sat I=–50mA,V =5V,UCCx813-[3,5] 0.4 0.9 VCC Risetime C =1nF 41 70 ns L Falltime C =1nF 44 75 ns L UNDERVOLTAGELOCKOUT UCCx813-0 6.6 7.2 7.8 UCCx813-1 8.6 9.4 10.2 Startthreshold (7) V UCCx813-[2,4] 11.5 12.5 13.5 UCCx813-[3,5] 3.7 4.1 4.5 UCCx813-0 6.3 6.9 7.5 UCCx813-1 6.8 7.4 8 Stopthreshold (7) V UCCx813-[2,4] 7.6 8.3 9 UCCx813-[3,5] 3.2 3.6 4 UCCx813-0 0.12 0.3 0.48 UCCx813-1 1.6 2 2.4 Starttostophysteresis V UCCx813-[2,4] 3.5 4.2 5.1 UCCx813-[3,5] 0.2 0.5 0.8 SOFTSTART COMPrisetime V =1.8V,Risefrom0.5VtoREF–1V 4 ms FB OVERALL Start-upcurrent V <startthreshold 0.1 0.23 mA VCC Operatingsupplycurrent V =0V,V =0V,V =0V 0.5 1.2 mA FB CS RC VCCinternalZenervoltage(7) I =10mA 12 13.5 15 V CC VCCinternalZenervoltageminus start-thresholdvoltage (7) UCCx813-[2,4] 0.5 1 V DV A = COMP 0£ V £0.8 V DV CS (5) Gainisdefinedby: CS . (6) ParametermeasuredattrippointoflatchwithFBat0V. (7) Startthreshold,stopthreshold,andZener-shuntthresholdstrackoneanother. 6 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 7.6 Typical Characteristics 80 4.00 3.98 60 135 3.96 3.94 Phase 40 90 V) 3.92 Gain(dB) Gain Phase(º) V(REF 3.90 20 45 3.88 3.86 0 0 3.84 3.82 -20 10k 10k 100k 1M 10M 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 Frequency(Hz) VCC(V) C001 I =0.5mA LOAD Figure1.ErrorAmplifierGainandPhaseResponse Figure2.UCC3813-[3,5]:VREFvsVCC 1000 1000 z) z) H H k k q. ( q. ( e e Oscillator Fr 100 132030000pppFFF Oscillator Fr 100 321300000pppFFF 10 1nF 10 1nF 10 100 1000 10 100 1000 RT(kΩ) RT(kΩ) Figure3.UCC3813-[0,1,2,4]:OscillatorFrequencyvs Figure4.UCC3813-[3,5]:OscillatorFrequencyvsR andC T T R andC T T 100 50 99.5 49.5 %) 99 %) e ( 98.5 e ( 49 um Duty Cycl 9799.578 CT= 33C0Tp= 200pCFT= 100pF um Duty Cycl 484.85 CT= 330pCT= 200CpTF= 100pF m F m F axi 96.5 axi 47.5 M M 96 47 95.5 95 46.5 10 100 1000 10 100 1000 Oscillator Frequency (kHz) Oscillator Frequency (kHz) Figure5.UCC3813-[0,2,3]:MaximumDutyCyclevs Figure6.UCC3813-[1,4,5]:MaximumDutyCyclevs OscillatorFrequency OscillatorFrequency Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com Typical Characteristics (continued) 16 8 14 7 (mA) 11802 V CC =V C1C0 V=, 18nV,F 1nF (mA) 456 VCC V= C1C0 V=, 81Vn, F1nF C C IC 246 VCVCC=C 1=0 V8,V N, No oL oLaodad IC 123 VCVCC=C 1=0 V8,V N, No oL oLaodad 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Oscillator Frequency (kHz) Oscillator Frequency (kHz) Figure7.UCC3813-0:I vsOscillatorFrequency Figure8.UCC3813-5:I vsOscillatorFrequency CC CC 500 1.1 450 400 s) 1.0 350 Volt ad Time (ns) 223050000 UCCx813/5 CS Offset ( 00..89 Slope = 1.8mV/°C De 150 UCCx813/1/2/4 Pto 0.7 M 100 O C 0.6 50 0 0 100 200 300 400 500 600 700 800 900 1000 -55-50 -25 0 25 50 75 100 125 CT (pF) Temperature (°C) RT=100kΩ VCS=0V Figure9.DeadTimevsC Figure10.COMPToCSOffsetvsTemperature T 8 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 8 Detailed Description 8.1 Overview The UCCx813-x family of high-speed, low-power integrated circuits contain all of the control and drive functions required for off-line and DC-to-DC fixed-frequency current-mode switched-mode power supplies having minimal external parts count. The UCCx813-x family is a cost-reduced version of the UCCx80x family, with some relaxation of certain parameter limits. See Differences Between the UCC3813 and UCC3800 PWM Families for moreinformation. These devices have the same pin configuration as the UCx84x and UCx84xA families, and also offer the added features of internal full-cycle soft start and internal leading-edge blanking of the current-sense input. The UCCx813-x devices are pin-out compatible with the UCx84x and UCx84xA families, however they are not plug-in compatible. In general, the UCCx813-x requires fewer external components and consumes less operating current. 8.2 Functional Block Diagram FB COMP CS 2 1 3 7 VCC UCCx813-1 Leading Edge UCCx813-4 Blanking UCCx813-5 1.5 V VCC Over Current REF/2 Only OK T Q S Q R Oscillator S Q 6 OUT 4 V S Q Voltage R Reference PWM 13.5 V R Latch REF OK 0.5 V Full Cycle Soft Start Logic Power τ=4ms 1V 5 GND 8 4 REF Copyright © 2016,Texas Instruments Incorporated 8.3 Feature Description The UCCx813-x family offers numerous advantages that allow the power supply design engineer to meet their challengingrequirements. Featuresinclude: • Bi-CMOSprocess • Lowstartingsupplycurrent:typically100µA • Lowoperatingsupplycurrent:typically500µA • PinoutcompatiblewithUC3842andUC3842Afamilies • 5-Voperation(UCCx813-[3,5]) • Leading-edgeblankingofcurrent-sensesignal • On-chipsoftstartforstart-upandfaultrecovery • Internalfullcyclerestartdelay Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com Feature Description (continued) • 1.5%voltagereference • Upto1-MHzoscillator • Lowself-biasingoutputduringUVLO • 70-nsresponsefromcurrentsensetooutput • Veryfewexternalcomponentsrequired • Availableinsurface-mountandPDIPpackages 8.3.1 DetailedPinDescriptions 8.3.1.1 COMP COMP is the output of the error amplifier and the input of the PWM comparator. Unlike earlier-generation devices, the error amplifier in the UCCx813-x device family is a true low-output-impedance 2-MHz operational amplifier. As such, the COMP terminal both sources and sinks current. However, the error amplifier is internally currentlimited,sozerodutycyclemaybecommandedbyexternallyforcingCOMPtoGND. The UCCx813-x device family features built-in full cycle soft start at power up and after fault recovery, and no external components are necessary. Soft start is implemented as a rising clamp on the COMP voltage, increasingfrom0Vto5Vin4ms. 8.3.1.2 CS CS is the input to the current-sense comparators. The UCCx813-x current sense is significantly different from its predecessor. The UCCx813-x device family has two different current-sense comparators: the PWM comparator andanovercurrentcomparator.Theovercurrent comparator is intended only for fault sensing, and exceeding the overcurrent threshold causes a soft-start cycle. The earlier UC3842 family current-sense input connects to only thePWMcomparator. The UCCx813-x device family contains digital current-sense filtering, which disconnects the CS terminal from the current sense comparator during the 100-ns interval immediately following the rising edge of the OUT pin. This digital filtering, also called leading-edge blanking, prevents false triggering due to leading edge noises which means that in most applications, no analog filtering (external R-C filter) is required on CS. Compared to an external RC filter technique, the leading-edge blanking provides a smaller effective CS-to-OUT delay. However, theminimumnon-zeroon-timeoftheOUTsignalis determined by the leading-edge-blanking time and the CS-to- OUT propagation delay. The gain of the current sense amplifier is typically 1.65 V/V in the UCCx813-x family versustypically3V/VintheUC3842family.ConnectCSdirectlytoMOSFETsourcecurrentsenseresistor. 8.3.1.3 FB FB is the inverting input of the error amplifier. For best stability, keep the FB lead length as short as possible and FB stray capacitance as small as possible. At 2 MHz, the gain-bandwidth of the error amplifier is twice that of earlierUC3842familydevices,andfeedbackdesigntechniquesareidentical. 8.3.1.4 GND GND is the signal reference ground and power ground for all functions on this part. TI recommends separating the signal return paths and the high current gate driver path so that signals are not affected by the switching current. 8.3.1.5 OUT OUT is the output of a high-current power driver capable of driving the gate of a power MOSFET with peak currentsexceeding ±750mA(upto ±1A).OUTisactivelyheldlowwhenVCC is below the UVLO threshold. This featureeliminatestheneedforagate-to-sourcebleederresistorassociatedwiththeMOSFETgatedrive. The high-current power driver consists of CMOS FET output devices, which can switch all of the way to GND and all of the way to VCC. The output provides very smooth rising and falling waveforms, providing very low impedances to overshoot and undershoot which means that in many cases, external Schottky clamp diodes may not be necessary on the output. Finally, no external gate voltage clamp is necessary with the UCCx813-x as the on-chipZenerdiodeautomaticallyclampstheoutputtoVCC. 10 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 Feature Description (continued) 8.3.1.6 RC RC is the oscillator timing pin. For fixed frequency operation, set the timing-capacitor charging current by connecting a resistor from REF to RC. Set frequency by connecting a timing capacitor from RC to GND. For best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate groundtracesforthetimingcapacitorandallotherfunctions. The UCCx813-x’s oscillator allows for operation to 1 MHz versus 500 kHz with the UC3842 family. Both devices make use of an external resistor to set the charging current for the capacitor, which determines the oscillator frequency.FortheUCCx813-[0,1,2,4],useEquation1. 1.5 = f R´C where • ƒistheoscillatorfrequencyinhertz(Hz) • Risthetiminingresistanceinohms(Ω) • Cisthetimingcapacitanceinfarads(F) (1) FortheUCCx813-[3,5],useEquation2. 1.0 = f R´C (2) The recommended timing resistance is from 10 kΩ to 200 kΩ and timing capacitance is from 100 pF to 1000 pF. Neveruseatimingresistorlessthan10kΩ. The two equations are different due to different reference voltages. The peak-to-peak amplitude of the oscillator waveformis 2.45 V versus 1.7 V in UC3842 family. For best performance, keep the timing capacitor lead to GND as short as possible. TI recommends separate ground traces for the timing capacitor and all other pins. The maximum duty cycle for the UCCx813-[0,2,3] is approximately 99%; the maximum duty cycle for the UCCx813- [1,4,5] is approximately 49%. The duty cycle cannot be easily modified by adjusting R and C , unlike the T T UC3842A family. The maximum duty cycle limit is set by the ratio of the external oscillator charging resistor R T and the internal oscillator discharge transistor on-resistance, like the UC3842. However, maximum duty cycle limits less than 90% (for the UCCx813-[0,2,3]) and less than 45% (for the UCCx813-[1,4,5]) can not reliably be setinthismanner.Forbettercontrolofmaximumdutycycle,considerusingtheUCCx807. 8.3.1.7 REF REFisthe voltage reference for the error amplifier and also for many other functions on the IC. REF is also used as the logic power supply for high speed switching logic on the IC. The UCCx813-[0,1,2,4] have a 5-V reference and the UCCx813-[3,5] have a 4-V reference. Both have ±1.5% accuracy at 25°C versus ±2% in the UC3842 family.TheREFoutputshort-circuitcurrentislowerat5mA,comparedto30mAintheUC3842family. For reference stability and to prevent noise problems with high speed switching transients, it is important to bypass REF to GND with a ceramic capacitor as close to the pins as possible. A minimum of 0.1-µF ceramic is required. Additional REF bypassing is required for external loads greater than 2.5 mA on the reference. An electrolyticcapacitorcanalsobeusedinadditiontotheceramiccapacitor. When VCC is greater than 1 V and less than the UVLO on-threshold, REF is internally pulled to ground through a5-kΩresistorwhichmeansthatREFcanbeusedasalogicoutputindicatingpower-systemstatus. 8.3.1.8 VCC VCC is the power input connection for this device. In normal operation, VCC is powered through a current limiting resistor to a low-impedance source. To prevent noise problems, bypass VCC to GND with a 0.1-µF ceramic capacitor in parallel as close to the VCC pin as possible. An electrolytic capacitor can also be used in additiontotheceramiccapacitor. Although quiescent VCC current is very low, total supply current is higher, depending on the OUT current. Total VCC current is the sum of quiescent VCC current and the average OUT current. Knowing the switching frequencyfandtheMOSFETgatecharge(Qg),averageOUTcurrentcanbecalculatedfromEquation3. I =Q ´ f OUT g (3) Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com Feature Description (continued) The UCCx813-x has a lower VCC (supply voltage) clamp of 13.5 V typical versus 30 V on the UC3842. For applications that require a higher VCC voltage, a resistor must be placed in series with VCC to increase the sourceimpedance.ThemaximumvalueofthisresistoriscalculatedwithEquation4. V -V IN:min; VCC:max; R = max I +Q ×f VCC g where • V istheminimumvoltagethatisusedtosupplyVCC IN(min) • V isthemaximumVCCclampvoltageofthecontroller VCC(max) • I istheICsupplycurrentwithoutconsideringthegatedrivercurrent VCC • Q istheexternalpowerMOSFETgatecharge,andfistheswitchingfrequency (4) g Additionally, the UCCx813-x has an on-chip Zener diode to limit VCC to 13.5 V, which also limits the maximum OUT voltage. If the bias-supply source is always lower than 12 V, it may be connected directly to VCC. With UVLO thresholds at 4.1 V and 3.6 V for the UCCx813-3 and UCCx813-5, respectively, 5-V PWM operation is nowpossible. 8.3.2 UndervoltageLockout(UVLO) TheUCCx813-[2,4]devicesfeatureundervoltagelockoutprotectioncircuitsforcontrolledoperationduringpower- up and power-down sequences. Both the supply voltage (V ) and the reference voltage (V ) are monitored VCC REF by the UVLO circuitry. During UVLO, an active-low, self-biasing totem-pole output structure is also incorporated forenhancedpowerswitchprotection. Undervoltage lockout thresholds for the UCCx813-[2,3,4,5] devices are different from the previous generation of UCx84[2,3,4,5] PWM controllers. The thresholds are optimized for two groups of applications: off-line power suppliesandDC-DCconverters.SeeTable1forthespecificthresholdsforeachdevice. Table1.UVLOLevelComparisonTable DEVICE V (V) V (V) ON OFF UCCx813-0 7.2 6.9 UCCx813-1 9.4 7.4 UCCx813-[2,4] 12.5 8.3 UCCx813-[3,5] 4.1 3.6 The UCCx813-[2,4] feature typical UVLO thresholds of 12.5 V for turnon and 8.3 V for turnoff, providing 4.3 V of hysteresis. For low voltage inputs, which include battery and 5-V applications, the UCCx813-[3,5] turn on at 4.1 V and turn offat3.6Vwith0.5Vofhysteresis. TheUCCx813-[0,1]haveUVLOthresholdsoptimizedforautomotiveandbatteryapplications. During UVLO, the device draws approximately 100 µA of supply current. Once VCC crosses the turnon threshold, the IC supply current increases typically to about 500 µA, over an order of magnitude lower than bipolar counterparts. Figure 11 indicates the supply current behavior at the relative UVLO turnon and turnoff thresholds,notincludingaverageOUTcurrent. 12 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 Figure11. ICSupplyCurrentatUVLO 8.3.3 Self-Biasing,ActiveLowOutput The self-biasing, active-low clamp circuit shown in Figure 12 eliminates the potential for problematic MOSFET turnon. As the PWM output voltage rises while in UVLO, the P-channel device drives the larger N-channel switch ON,whichclampstheoutputvoltagelow.Power to this circuit is supplied by the externally rising gate voltage, so fullprotectionisavailableregardlessofthedevice'ssupplyvoltageduringundervoltagelockout. 2 V V = OPEN CC V V = 2 V OUT CC V = 0 V CC V = 1 V 1 V CC 50 mA 100 mA I OUT Figure12.InternalCircuitHoldingOUTLowDuring Figure13.OUTVoltagevsOUTCurrentDuring UVLO UVLO 8.3.4 ReferenceVoltage The traditional 5-V band-gap-derived reference voltage of the UC3842 family can be also found on the UCCx813-[0,1,2,4] devices. However, the reference voltage of the UCCx813-[3,5] devices is 4 V. This change was necessary to facilitate operation with input supply voltages below 5 V. Many of the reference voltage specifications are similar to the UC3842 devices although the test conditions have been changed, indicative of lower-current PWM applications. Similar to their bipolar counterparts, the BiCMOS devices internally pull the referencevoltagelowduringUVLO,whichcanbeusedasalogicstatusindication. The 4-V reference voltage on the UCCx813-[3,5] is derived from the supply voltage (V ) and requires about VCC 0.5 V of headroom to maintain regulation. Whenever V is below approximately 4.5 V, the reference voltage VCC also drops outside of its specified range for normal operation. The relationship between V and V during VCC REF thisexcursionisshowninFigure14. The noninverting input to the error amplifier is tied to one-half of the controller's reference voltage (V ). This REF inputis2VontheUCCx813-[3,5]and2.5Vonthehigherreferencevoltageparts:theUCCx813-[0,1,2,4]. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com 4.0 V UCC3813-x 3.9 V REF 3.8 V EF R 0.1 µF VR TO BYPASS 3.7 V E/A+ R 3.6 V 3.5 V 3.6 V 3.8 V 4.0 V 4.2 V 4.4 V 4.6 V 4.8 V 5.0 V V CC Figure14.UCC3813-3REFOutputvsV Figure15.RequiredReferenceBypassMinimum VCC Capacitance 8.3.5 Oscillator The UCCx813-x oscillator generates a sawtooth waveform on RC. The rise time is set by the time constant of R T and C . The fall time is set by C and an internal transistor on-resistance of approximately 130 Ω. During the fall T T time, the output is OFF and the maximum duty cycle is reduced below 50% or 100%, depending on the part number. Larger values for the timing capacitor increase the discharge time and reduce the maximum duty cycle andfrequencyslightly,asseeninFigure5andFigure6. REF 8 0.2V + RT R Q + S RC 4 2.65V C T Figure16. OscillatorEquivalentCircuit The oscillator section of the UCCx813-x BiCMOS family has few similarities to the UC3842 type — other than single-pin programming. It does still use a resistor to the reference voltage and capacitor to ground to program the oscillator frequency up to 1 MHz. Timing component values must be changed because a much lower charging current is desirable for low-power operation. Several characteristics of the oscillator have been optimized for high-speed, noise-immune operation. The oscillator peak-to-peak amplitude has been increased to 2.45 V typical versus 1.7 V on the UC3842 family. The lower oscillator threshold has been dropped to approximately0.2Vwhiletheupperthresholdremainsfairlyclosetotheoriginal2.8Vatapproximately2.65V. Discharge current of the timing capacitor has been increased to nearly 20-mA peak as opposed to roughly 8 mA. This can be represented by approximately 130 Ω in series with the discharge switch to ground. The higher current is necessary to achieve brief dead times and high duty cycles with high-frequency operation. Practical applicationscanusethesedevicestoa1-MHzswitchingfrequency. 14 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 1000 800 2.65 V 600 400 V CT z) 200 H C = 100 p k T ( 0.2 V ƒ 100 0 V f 80 C = 180 p CONV T 60 C = 270 p T C = 390 p 40 T C = 470 p T 20 0 20 40 60 80 100 120 R (kW) T Figure17.OscillatorWaveformatRC Figure18.OscillatorFrequencyvsR ForSeveral T C T 8.3.6 Synchronization Synchronization of these PWM controllers is best obtained by the universal technique shown in Figure 19. The device oscillator is programmed to free-run at a frequency about 20% lower than that of the synchronizing frequency. A brief positive pulse is applied across the 50-Ω resistor to force synchronization. Typically, a 1-V amplitudepulseof100-nswidthissufficientformostapplications. The controller can also be synchronized to a pulse-train applied directly to the oscillator RC pin. The device internally pulls low at this node once the upper oscillator threshold is crossed. This 130-Ω impedance to ground remains active until the voltage on RC is lowered below 0.2 V. External synchronization circuits must accommodatetheseconditions. REF R T RC C T SYNC §(cid:3)50 (cid:13)(cid:3) Figure19. SynchronizingtheOscillator 8.3.7 PWMGenerator Maximum duty cycle is higher for these devices than for their UC384[2,3,4,5] predecessors. This is primarily due to the higher ratio of timing capacitor discharge-to-charge current, which can exceed one hundred-to-one in a typical BiCMOS application. Attempts to program the oscillator maximum duty cycle much below the specified range, by adjusting the timing component values of R and C , must be avoided. There are two reasons to T T refrain from this design practice. First, the device's high discharge current would necessitate higher charging current than necessary for programming, defeating the purpose of low power operation. Second, a low-value timing resistor may prevent the capacitor from discharging to the lower threshold and initiating the next switching cycle. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com 8.3.8 MinimumOff-TimeAdjustment(Dead-TimeControl) Dead time is the term used to describe the ensured OFF time of the PWM output during each oscillator cycle. It is used to ensure that even at maximum duty cycle, there is enough time to reset the magnetic circuit elements, and prevent saturation. The dead time of the UCCx813-x PWM family is determined by the internal 130-Ω discharge impedance and the timing capacitor value. Larger capacitance values extend the dead time whereas smaller values results in higher maximum duty cycles for the same operating frequency. A curve for dead time versus timing capacitor values is provided in Figure 20. Further increasing the dead time is possible by adding a low-value resistor between the RC pin and the timing components, as shown in Figure 21. The dead time increases with increasing discharge resistor value to about 470 Ω as indicated from the curve in Figure 22. Higher resistances must be avoided as they can decrease the dead time and reduce the oscillator peak-to-peak amplitude.Sinkingtoomuchcurrent (1 mA) by reducing R will freeze the oscillator OFF by preventing discharge T to the lower comparator threshold voltage of 0.2 V. Adding this discharge control resistor has several impacts on the oscillator programming. First, it introduces a DC offset to the capacitor during the discharge interval – but not the charging interval of the timing cycle, thus lowering the usable peak-to-peak timing capacitor amplitude. Because of the reduced peak-to-peak amplitude, the exact value of C may require adjustment to obtain the T correct oscillator frequency. One alternative is keep the same value timing capacitor and adjust both the timing anddischargeresistorvaluesbecausethesearereadilyavailableinfinernumericalincrements. 200 180 REF 160 RT 140 s) RD (n 120 RC Td <470 (cid:159) 100 CT 80 60 Copyright © 2016, Texas Instruments Incorporated 40 0 125 250 375 500 C (pF) T Figure20.MinimumDeadTimevsC Figure21.CircuittoProduceControlledMaximum T DutyCycle 100 99 98 97 %) 96 e ( Cycl 95 Duty 94 ax M 93 92 91 90 89 0 250 500 750 1000 RD, Ohms R =20kΩ T Figure22.MaximumDutyCyclevsR D 16 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 8.3.9 LeadingEdgeBlanking A 100-ns leading-edge-blanking interval is applied to the current-sense input circuitry of the UCCx813-x devices. This internal feature eliminates the requirement for an external resistor-capacitor filter network to suppress the switching spike associated with turnon of the power MOSFET. This 100-ns period should be adequate for most switch-mode designs but can be lengthened by adding an external R/C filter. The 100-ns leading edge blanking isalsoappliedtotheovercurrentfaultcomparatorinadditiontothecycle-by-cyclecurrent-limitingPWMfunction. Figure23.Current-SenseFilterRequired Figure24.UCCx813-xCurrent-SenseWaveforms WithOlderPWMDevices WithLeadingEdgeBlanking 8.3.10 MinimumPulseWidth The PWM comparator has two inputs; one is from the current sense input, the other input is the attenuated error- amplifier output (COMP) that has a diode and two resistors in series to ground. The diode in this network is used to ensure that zero duty-cycle can be reached. Whenever the E/A output falls below a diode forward voltage drop,nocurrentflowsintheresistordividerandthePWMinputgoestozero,resultinginzeropulsewidth. Under certain conditions, the leading-edge-blanking circuitry can lead to an output pulse of minimum width equal to the blanking interval. This occurs when the COMP is slightly higher than a diode forward voltage drop of about 0.5 V, such that the attenuated COMP input to the PWM comparator allows an output pulse to start. If the attenuated COMP level commands a peak current whose pulse width would fall within the leading-edge-blanking interval, the output will remain ON until the blanking interval is finished and the peak current will be higher than desired by the COMP level. The usual result is that the converter output voltage rises, increasing the error, and COMP is driven lower than the diode drop which then produces zero pulse width. Cycle-skipping may result as theoutputvoltagerisesandfallsaroundthisminimumpulse-widthcondition. + – Figure25. ZeroDuty-CycleOffset 8.3.11 CurrentLimiting A 1-V (typical) cycle-by-cycle current limit threshold is incorporated into the UCCx813-x family. The 100-ns leading-edge-blanking interval is applied to this current-limiting circuitry. The blanking overrides the current-limit comparator output to prevent the leading-edge switch noise from triggering a current-limit function. Propagation delay from the current-limit comparator to the output is typically 70 ns. This high-speed path minimizes power semiconductordissipationduringanoverloadbyabbreviatingtheONtime. For increased efficiency in the current-sense circuitry, the circuit shown in Figure 26 can be used. Resistors R A and R bias the actual current-sense resistor voltage up, allowing a smaller current sense amplitude to be used. B Thiscircuitryprovidescurrent-limitingprotectionwithlowerpower-losscurrentsensing. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com REF PWM + 0.1 µF 0 RA – V CS TO RCS 0 LOAD Q1 + RB CS – + 0 RCS – Copyright © 2016, Texas Instruments Incorporated Figure26.BiasingCSForLower Figure27.CSPinVoltagewithBiasing Current-SenseVoltage The example shown uses a 200-mV full-scale signal at the current sense resistor. Resistor R biases this up by B approximately 700 mV to match the 0.9-V minimum specification of the current-limit comparator of the IC. The value of resistor R changes with the specific IC used, due to the different reference voltages. The resistor A values should be selected for minimal power loss. For example, a 50-µA bias current sets R = 13 kΩ, and B R =75kΩforUCCx813-[0,1,2,4]orR =56kΩforUCCx813-[3,5]devices. A A 8.3.12 OvercurrentProtectionandFull-CycleRestart A separate overcurrent comparator within the UCCx813-x devices handles operation into a short-circuited or severely overloaded power supply output. This overcurrent comparator has a 1.5-V threshold and is also gated by the leading edge blanking signal to prevent false triggering. Once triggered, the overcurrent comparator uses the internal soft-start capacitor to generate a delay before retry is attempted. Often referred to as hiccup, this delay time is used to significantly reduce the input and dissipated power of the main converter and switching components. Full-cycle soft start ensures that there is a predictable delay of greater than 3 ms between successive attempts to operate during fault conditions. The circuit shown in Figure 28 and the timing diagram in Figure 29 show how the IC responds to a severe fault, such as a saturated inductor. When the peak current fault isfirstdetected,the internal soft-start capacitor instantly discharges and stays discharged until the fault clears. At the same time, the PWM output is turned off and held off. When the fault clears, the capacitor slowly charges and allows the error amp output (COMP) to rise. When COMP gets high enough to enable the output, another fault occurs, latching off the PWM output, but the soft-start capacitor still continues to rise to 4 V before being discharged and permitting start of a new cycle. This means that for a severe fault, successive retries is spaced by the time required to fully charge the soft-start capacitor. TI recommends low leakage transformer designs in high-frequency applications to activate the overcurrent protection feature. Otherwise, the switch current may not ramp up sufficiently to trigger the overcurrent comparator within the leading edge blanking duration. This condition would cause continual cyclical triggering of the cycle-by-cycle current limit comparator but not the overcurrent comparator. This would result in brief high power dissipation durations in the main converter at the switching frequency. The intent of the overcurrent comparator is to reduce the effective retry rate under these conditionstoafewmilliseconds,thussignificantlyloweringtheshort-circuitpowerdissipationoftheconverter. 18 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 CS FB COMP 3 2 1 Over-Current Leading Edge Blanking VCC 1.5 V REF/2 OK S Q R 4 V Ref S Q OK R 0.5 V Full Cycle Soft Start t= 5 ms Figure28. DetailedBlockDiagramforOvercurrentProtection Figure29. DeviceBehaviorwithRepetitiveFaultatCS 8.3.13 SoftStart Internal soft starting of the PWM output is accomplished by gradually increasing the error amplifier (E/A) output voltage at COMP. When used in current-mode control, this implementation slowly raises the peak switch current each PWM cycle in succession, forcing a controlled start-up. In voltage-mode (duty-cycle) control, this feature continuallywidensthepulsewidth. Soft-startisperformedwithintheUCCx813-xdevicesbyclampingtheE/Aamplifieroutput(COMP) to the voltage on an internal soft-start capacitor (C ), which is charged by a current source. C is discharged following an SS SS undervoltage lockout transition or if the reference voltage is below a minimum value for normal operation. Additionally, discharge of C occurs whenever the overcurrent protection comparator is triggered by a fault. The SS soft-start clamp circuitry is overridden once C charges above the voltage commanded by the error amplifier for SS normalPWMoperation. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com 2 1 3 RC 0 Leading Edge Blanking Soft Start 0 REF/2 PWM 0 CS 0 To Output Logic t= 4ms C SS Figure30.DetailedBlockDiagramforSoft-Start Figure31.DeviceSoft-StartBehavior 8.3.14 SlopeCompensation Slope compensation can be added in all current-mode control applications to cancel the peak-to-average current error. Slope compensation is necessary in applications with duty-cycles exceeding 50%, but also improves performance in those below 50%. Primary current is sensed using resistor R in series with the converter CS switch. The timing resistor can be broken up into two series resistors to bias up an NPN voltage-follower, as shown in Figure 32. This is required to provide ample compliance for slope compensation at the beginning of a switching cycle, especially with continuous-current converters. The voltage follower drives the slope compensatingprogrammingresistor(R )toprovideaslope-compensatingcurrentintoC . SC F REF R T To Main RC Switch C T R SC R F CS C R F CS Figure32. AddingSlopeCompensation 8.4 Device Functional Modes The UCCx813-x family of high-speed, low-power current-mode PWM controllers has the following functional modes. 8.4.1 NormalOperation During this operation mode, the IC controls the power converter into the voltage-mode or current-mode control, regulates the output voltage or current through the converter duty cycle. The regulation can be achieve through theintegratederroramplifierorexternalfeedbackcircuitry. 20 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 Device Functional Modes (continued) 8.4.2 UVLOMode During the system start-up, V voltage starts to rise from 0 V. Before the VCC voltage reaches its VCC corresponding turn-on threshold, the IC operates in UVLO mode. In this mode, REF pin voltage is not generated. When V is above 1 V and below the turnon threshold, the REF pin is actively pulled low through a 5-kΩ VCC resistor.Thisway,V canbeusedasalogicsignaltoindicateUVLOmode. REF 8.4.3 Soft-StartMode Once VCC voltage rises above the UVLO level, or the device comes out of a fault mode, it enters the soft-start mode. During soft-start, the internal soft-start capacitor C clamps the error amplifier output voltage, forcing it to SS rise slowly. This in turn controls the power converter peak current to rise slowly, reducing the voltage and current stresstothesystem.TheUCCx813-xfamilyhasafixedbuilt-insoft-starttimeat4ms. 8.4.4 FaultMode A separate overcurrent comparator within the UCCx813-x devices handles operation into a short-circuited or severely overloaded power supply output. This overcurrent comparator has a 1.5-V threshold and is also gated by the leading-edge-blanking signal to prevent false triggering. When the fault is first detected, the internal soft- start capacitor instantly discharges and stays discharged until the fault clears. At the same time, the PWM output is turned off and held off. This is often referred to as hiccup. This delay time is used to significantly reduce the input and dissipated power of the main converter and switching components. Full-cycle soft-start insures that there is a predictable delay of greater than 3 milliseconds between successive attempts to operate during fault. When the fault clears, the capacitor slowly charges and allows the error amp output (COMP) to rise. When COMP gets high enough to enable the output, another fault occurs, latching off the PWM output, but the soft- start capacitor still continues to rise to 4 V before being discharged and permitting start of a new cycle. This means that for a severe fault, successive retries are spaced by the time required to fully charge the soft-start capacitor. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The UCCx813-x controllers are peak-current-mode (PCM) pulse-width modulators (PWM). These controllers have an onboard amplifier and can be used in isolated and nonisolated power supply design. There is an onboard totem-pole gate driver capable of delivering up to ±1 A of peak current. These controllers are capable of operatingatswitchingfrequenciesupto1MHz. 9.2 Typical Application Figure 33 illustrates a typical circuit diagram for an AC-DC converter using the UCC2813-0 in a peak-current- mode-controlledflybackapplication. D CL F A 5A DA CCL 10 nF RCL 50 kΩ ~ D C V V = 85 to 265 VAC – + OUT+ IN ~ NP NS CIN CVCC2 COUT 120 µF RH 300 kΩ VOUT- DB RD QA V O NA 22Ω RG 10Ω R RZE 1 kΩ RAC CS U1 V ’ O R UCC2813-0 LED RT CFB RFB2 10 kΩ 1 COMP REF 8 D 10 V RJ 1 kΩ 2 FB VCC 7 C C C 3 CS OUT 6 VCC1 VREF 1 µF 1 µF V C 4 RC GND 5 R CSF U2 RRAMP RFBU CT CCSF RP 270 pF RFB1 RZ CZ C 10 nF RAMP 4.99 kΩ U3 REG 1 kΩ TL431 R FBB Copyright © 2016,Texas Instruments Incorporated Figure33. TypicalApplicationCircuitDiagram 22 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 Typical Application (continued) 9.2.1 DesignRequirements Use the parameters in Table 2 to review the design of a 12-V, 48-W offline flyback converter using the UCC2813-0PWMcontroller. Table2.DesignParameters PARAMETER TESTCONDITIONS MIN NOM MAX UNIT INPUTCHARACTERSTICS V Inputvoltage(RMS) 85 265 V IN f Linefrequency 47 63 Hz LINE OUTPUTCHARACTRSTICS V Outputvoltage 11.75 12 12.25 V OUT V Outputripplevoltage 120 mV ripple PP I Outputcurrent 4 4.33 A OUT Outputvoltagemeasuredunder0-Ato4-A V Outputtransient 11.75 12.25 V tran loadstep SYSTEMCHARACTRSTICS η Maxloadefficiency 85% 9.2.2 DetailedDesignProcedure 9.2.2.1 BulkCapacitorCalculation Thedesignstartswithselectinganappropriatebulkcapacitor. The primary-side bulk capacitor is selected based on the input power level and on the desired minimum bulk voltagelevel.ThebulkcapacitorvaluecanbecalculatedbyEquation5. “ 1 § VBULK(min) •” 2PINu«0.25(cid:14) uarcsin¤ ‚» CBULK (cid:11)2V«‹2IN(min)S(cid:16)V2BULK¤'(m2in)u(cid:12)uVfINLI(NmEin)‚„»… where • P isthemaximumoutputpowerdividedbythetargetefficiencyatmaximumload IN • V istheminimumACinputvoltageRMSvalue IN(min) • V isthetargetminimumbulkvoltage BULK(min) • f isthelinefrequency (5) LINE Based on this equation, to achieve 75-V minimum bulk voltage, assuming 85% converter efficiency and 47-Hz minimum line frequency, the bulk capacitor must be larger than 127 µF. 180 µF was chosen in the design, consideringthetypicaltoleranceofbulkcapacitors. 9.2.2.2 TransformerDesign The transformer design starts with selecting a suitable switching frequency. Generally the switching frequency selectionisbasedonatradeoffbetweentheconvertersizeandefficiency,basedonthesimpleFlybacktopology. Normally,higherswitchingfrequencyresultsinsmallertransformersize.However,theswitchingloss is increased andhurtstheefficiency.Sometimes,theswitchingfrequencyisselectedtoavoid certain communication bands to prevent noise interference with the communication. The frequency selection is beyond the scope of this data sheet. The switching frequency is targeted for 110 kHz, to minimize the transformer size. At the same time, because EMI regulations start to limit conducted noise at 150 kHz, choosing 110-kHz switching frequency can help to reducetheEMIfiltersize. The transformer turns ratio can be selected based on the desired MOSFET voltage rating and diode voltage rating.Becausemaximuminputvoltageis265VAC,thepeakbulkvoltagecanbecalculatedbyEquation6. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com V = 2´V »375V BULK(max) IN(max) (6) To minimize the cost of the system, a popular 650-V MOSFET is selected. Considering the design margin and extra voltage ringing on the MOSFET drain, the reflected output voltage must be less than 120 V. The transformerturnsratiocanbeselectedbyEquation7. 120V n = =10 ps 12V (7) The transformer inductance selection is based on the continuous conduction mode (CCM) condition. Higher inductance would allow the converter to stay in CCM longer. However, it tends to increase the transformer size. Normally, the transformer magnetizing inductance is selected so that the converter enters CCM operation at about 50% load at minimum line voltage. This would be a tradeoff between the transformer size and the efficiency. In this particular design, due to the higher output current, it is desired to keep the converter deeper in CCM and minimize the conduction loss and output ripple. The converter enters CCM operation at about 10% loadatminimumbulkvoltage. TheinductorcanbecalculatedasEquation8. 2 æ ö n V V2 ´ç PS OUT ÷ L = 1 BULK(min) çèVBULK(min) +nPSVOUT ÷ø m 2 10%´PIN´ fSW (8) In this equation, the switching frequency is 110 kHz. Therefore, the transformer inductance must be about 1.7mH.1.5mHischosenasthemagnetizinginductancevalue. The auxiliary winding provides the bias power for UCC2813-0 normal operation. The auxiliary winding voltage is the output voltage reflected to the primary side. It is desired to have higher reflected voltage so that the IC can quickly get energy from the transformer and make start-up under heavy load easier. However, higher reflected voltagemakestheICconsumemorepower.Therefore,atradeoffisrequired. In this design, the auxiliary winding voltage is selected to be the same as the output voltage so that it is above the UVLO level but keeps the IC and driving loss low. Therefore, the auxiliary winding to the output winding turns ratioisselectedbyEquation9. 12V n = =1 as 12V (9) Based on calculated primary inductance value and the switching frequency, the current stress of the MOSFET anddiodecanbecalculated. 9.2.2.3 MOSFETandOutputDiodeSelection ThepeakcurrentoftheMOSFETiscalculatedbyEquation10. n V PS OUT P 1V V +n V IN BULK(min) BULK:min; PS OUT I = + × PKMOS n V 2 L f V × PS OUT m sw BULK:min; V +n V BULK:min; PS OUT (10) TheMOSFETpeakcurrentis1.425A. TheRMScurrentoftheMOSFETcanbecalculatedasEquation11. I = 1D3 ´æçVBULK(min)ö÷2 -D2IPKMOSVBULK(min) +D´I2 RMSMOS 3 çè Lm´ fsw ÷ø Lm´ fsw PKMOS where • DistheMOSFETdutycycleatminimumbulkvoltageanditcanbecalculatedasEquation12 (11) n V D= ps OUT V +n V BULK(min) ps OUT (12) 24 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 TheMOSFETRMScurrentis0.75A.With less than 0.9-Ω on-resistance, IRFB9N65A is selected as the primary- sideMOSFET. ThediodepeakcurrentisthereflectedMOSFETpeakcurrentonthesecondaryside. I =n ´I =14.25A PKDIODE ps PKMOS (13) The diode voltage stress is the output voltage plus the reflected input voltage. The voltage stress on the diode canbecalculatedbyEquation14. V 375V V = BULK(max)+V = (cid:14)(cid:20)(cid:21)9§(cid:24)(cid:19)9 DIODE n OUT 10 ps (14) Consideringtheringingvoltagespikesandvoltagederating,thediodevoltageratingmustbehigherthan50V. The diode average current is the output current (4 A), so 48CTQ060-1, with 60-V rating and 40-A average currentcapability,isselected. 9.2.2.4 OutputCapacitorCalculation The output capacitor is selected based on the output voltage ripple requirement. In this design, 0.1% voltage ripple is assumed. Based on the 0.1% ripple requirement, the capacitor value can be selected based on Equation15. n V ps OUT I ´ OUT V +n V BULK(min) ps OUT C ³ =2105mF OUT 0.1%´VOUT ´ fsw (15) Considering the tolerance and temperature effect, together the ripple current rating of the capacitors, 3 parallel 680-µFcapacitorsareselectedfortheoutput. Afterthebasicpowerstageisdesigned,thesurroundingcontrollercomponentscanbeselected. 9.2.2.5 CurrentSensingNetwork The current sensing network consists of R , R , C , and optional R . Typically, the direct current sense CS CSF CSF P signal contains a large-amplitude leading-edge spike associated with the turn-on of the main power MOSFET, reverse recovery of the output rectifier, and other factors including charging and discharging of parasitic capacitances. Therefore, C and R form a low-pass filter that provides additional immunity beyond the CSF CSF internal blanking time to suppress the leading edge spike. For this converter, C is chosen to be 270 pF to CSF provideenoughfiltering. Without R , R sets the maximum peak current in the transformer primary based on the maximum amplitude of P CS CSpin,1V.Toachieve1.425-Aprimarysidepeakcurrent,a0.75-Ω resistorischosenforR . CS The high current-sense threshold helps to provide better noise immunity but the current-sense loss is increased. The current-sense loss can be minimized by injecting an offset voltage into the current-sense signal. R and P R form a resistor-divider network from the current-sense signal to the device’s reference voltage to offset the CSF current-sense voltage. This technique still achieves current-mode control with cycle-by-cycle overcurrent protection.Tocalculaterequiredoffsetvalue(Voffset),useEquation16. RCSF Voffset VREF RCSF(cid:14)RP (16) 9.2.2.6 GateDriveResistor R is the gate driver resistor for the power switch, Q . The selection of this resistor value must be done in G A conjunction with EMI compliance testing and efficiency testing. Larger R slows down the turn-on and turn-off of G the MOSFET. Slower switching speed reduces EMI but also increases the switching loss. A tradeoff between switching loss and EMI performance must be carefully performed. For this design, 10 Ω was chosen as the gate driverresistor. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com 9.2.2.7 REFBypassCapacitor The precision 5-V reference voltage at REF is designed to perform several important functions. The reference voltage is divided down internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate outputvoltageregulation.Otherdutiesofthereferencevoltagearetosetinternalbiascurrentsandthresholdsfor functions such as the oscillator upper and lower thresholds along with the overcurrent limiting threshold. Therefore, the reference voltage must be bypassed with a ceramic capacitor (C ), and 1-µF, 16-V ceramic VREF capacitor was selected for this converter. Placement of this capacitor on the physical printed-circuit board layout mustbeascloseaspossibletotherespectiveREFandGNDpins. 9.2.2.8 R andC T T The internal oscillator uses a timing capacitor (C ) and a timing resistor (R ) to program operating frequency and T T maximum duty cycle. The operating frequency can be programmed based the curves in Figure 3, where the timing resistor can be found once the timing capacitor is selected. The selection of timing capacitor also affects the maximum duty cycle provided in Figure 5. It is best for the timing capacitor to have a flat temperature coefficient, typical of most COG or NPO type capacitors. For this converter, 1000 pF and 13.6 kΩ were selected forC andR tooperateat110-kHzswitchingfrequency. T T 9.2.2.9 Start-UpCircuit At start-up, the IC gets its power directly from the high voltage bulk, through a high-voltage resistor R . The H selection of start-up resistor is the tradeoff between power loss and start-up time. The current flowing through R H at minimum input voltage must be higher than the VCC current under UVLO condition (0.2 mA at its maximum value).A300-kΩ resistorischosenastheresultofthetradeoff. After VCC is charged up above the UVLO turnon threshold, UCC2813-0 starts to operate and consumes full operating current. At the beginning, because the output voltage is low, VCC cannot get energy from the auxiliary winding.TheVCCcapacitorisrequiredtoholdenoughenergytopreventitsvoltagedropbelow UVLO during the start-up time, until the output reaches high enough. A larger capacitor holds more energy but slows down the start-uptime.Inthisdesign,a120-µFcapacitorischosentoprovideenoughenergyforthestart-uppurpose. 9.2.2.10 VoltageFeedbackCompensationProcedure Feedback compensation, also called closed-loop control, reduces or eliminates steady-state output voltage error, reduces the sensitivity to parametric changes, changes the gain or phase of a system over some desired frequency range, reduces the effects of small-signal load disturbances and noise on system performance, and creates a stable system. This section describes how to compensate an isolated Flyback converter with the peak- current-modecontrol. 9.2.2.10.1 PowerStageGain,Zeroes,andPoles The first step in compensating a fixed-frequency flyback is to verify if the converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (L ) is greater than P the inductance for DCM-CCM boundary mode operation, called the critical inductance (L ), then the converter Pcrit operatesinCCM.L iscalculatedwithEquation17. Pcrit R ´N2 æ V ö2 LPcrit = O2U´Tf PS ´çV +V IN ´N ÷ SW è IN OUT PS ø (17) For loads greater than 10% of P over the entire input voltage range, the selected primary inductance has MAX value larger than the critical inductance. Therefore, the converter operates in CCM and the compensation loop requiresdesignbasedonCCMflybackequations. The current-to-voltage conversion is done externally with the ground-referenced current-sense resistor (R ) and CS the internal resistor divider sets up the internal current-sense gain, A = 1.65. The IC technology allows tight CS controloftheresistor-dividerratio,regardlessoftheactualresistorvaluevariations. The DC open-loop gain (G ) of the fixed-frequency voltage control loop of a peak-current-mode control CCM O flyback converter shown in Figure 33 is approximated by first using the output load (R ), the primary to OUT secondaryturnsratio(N ),andthemaximumdutycycle(D)asshowninEquation18. PS 26 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 R ´N 1 G = OUT PS ´ O RCS´ACS (1-D)2 +(2´M)+1 t L where • R =V /I OUT OUT OUT • DiscalculatedwithEquation19 • τ iscalculatedwithEquation20 L • MiscalculatedwithEquation21 (18) N ´V D= PS OUT V +(N ´V ) IN PS OUT (19) 2´L ´f t = P SW L R ´N2 OUT PS (20) V ´N M= OUT PS V IN (21) For this design, a converter with an output voltage (V ) of 12 V, and 48 W relates to an output load (R ) OUT OUT equalto3Ωatfullload. At minimum input bulk voltage of 75 V DC, the duty cycle reaches its maximum value of 0.615. The current sense resistance (R ) is 0.75 Ω and a primary to secondary turns-ratio (N ) is 10. The open-loop gain CS PS calculatesto14.95dB. A CCM flyback transfer function has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero to the power stage, and the frequency of this zero (f ) is calculated with ESRz Equation22. 1 w = ESRz R ´C ESR OUT (22) The f zero for a capacitance bank of three 680-µF capacitors (for a total output capacitance of 2040 µF) and ESRz atotalESRof13mΩislocatedat6kHz. CCM flyback converters have a zero in the right-half plane (RHP) of their transfer function. RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location (f ) RHPz in Equation 23 is a function of the output load, the duty cycle, the primary inductance (L ), and the primary to P secondarysideturnsratio(N ). PS R ´(1-D)2 ´N2 f = OUT PS RHPz 2´p´L ´D P (23) RHP zero frequency increases with higher input voltage and lighter load. Generally, the design requires considerationoftheworstcaseofthelowestRHPzero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zerofrequency(f )isequalto7.65kHzatmaximumdutycycle(fullload). RHPz The power stage has one dominant pole (ω ) which is in the region of interest, located at a lower frequency (f ) P1 P1 which is related to the duty cycle (D), the output load, and the output capacitance. There is also a double pole (f ) located at half the switching frequency of the converter. These poles are frequencies calculated with P2 Equation24andEquation25. (1-D)3 +1+D t f = L P1 2´p´R ´C OUT OUT (24) f f = SW P2 2 (25) Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com Subharmonic oscillation is the large signal instability that can occur in CCM flyback converters when duty cycles extend beyond 50%. The subharmonic oscillation increases the output voltage ripple and sometimes it even limits the power handling capability of the converter. Slope compensation to the CS signal is a technique used to eliminatetheinstability. Ideally, the target of slope compensation is to achieve quality coefficient (Q = 1) at half of the switching P frequency.TheQ iscalculatedbyEquation26. P 1 Q = P p´éëMC´(1-D)-0.5ùû where • Distheprimarysideswitchdutycycle • M istheslopecompensationfactor,whichisdefinedbyEquation27 (26) C S M =1+ e C S n where • S isthecompensationrampslope e • S representstherisingcurrentslopeofthetransformerprimaryinductance (27) n The optimal goal of the slope compensation is to achieve Q equal to 1, which means M must be 2.128 when D P C reachesitmaximumvalueof0.615. TheinductancecurrentslopeattheCSpiniscalculatedbyEquation28. V ×R 75V×0.75(cid:13) BULK(min) CS S = = =38mV/(cid:29)s n L 1.5mH P (28) ThecompensationslopeiscalculatedbyEquation29. S =(M -1)´S =(2.128-1)´38mV/ms=46.3mV/ms e C n (29) The compensation slope is added into the system through R and R . A series capacitor (C ) is RAMP CSF RAMP selected to approximate a high-frequency short circuit. Choose C as 10 nF as the starting point, and make RAMP adjustments if required. R and R form a voltage divider to scale the RC pin ramp voltage and inject the RAMP CSF slope compensation into CS pin. Choose R much larger than the R resistor so that it does not affect the RAMP T frequency setting very much. In this design, R is selected as 24.9 kΩ. The RC pin ramp slope is calculated RAMP withEquation30. S =2.4 V´100kHz=240mV/ms RC (30) Toachieve46.3mV/µscompensationslope,R resistoriscalculatedwithEquation31. CSF RCSF = SRRAMP = 2402 4m.9V /k(cid:29)(cid:13)s = 5.95 k(cid:13) RC(cid:237)1 (cid:237)1 Se 46.3 mV/(cid:29)s (31) The power stage open-loop gain and phase can be plotted as a function of frequency. The total open-loop transferfunction,asafunctionoffrequency,canbecharacterizedbyEquation32. S S 1+ × 1(cid:237) l & p l & p 1 H :S; = G × ESRz RHPz × 0 0 1+&S 1+ S + S2 P1 & ×Q &2 P2 P P2 where • ω andω arebasedonthefrequenciescalculatedbyEquation24andEquation25 (32) P1 P2 Theopen-loopgainandphaseBodeplotsaregraphedaccordingly(seeFigure34andFigure35). 28 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 20 0 -30 10 -60 Loop Gain (dB) -100 Phase (Degree) -90 -120 -20 -150 -180 -30 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure34.ConverterOpen-LoopBodePlot:Gain Figure35.ConverterOpen-LoopBodePlot:Phase 9.2.2.10.2 CompensatingtheLoop For good transient response, the bandwidth of the finalized design must be as wide as possible. The bandwidth ofaCCMflyback(f )islimitedto¼ oftheRHP-zerofrequency,orapproximately1.9kHzusingEquation33. BW f f = RHPz BW 4 (33) The gain of the open-loop power stage at f is equal to –22.4 dB and the phase at f is equal to –87°. First BW BW step is to choose the output voltage-sensing resistor values. The output sensing resistors are selected based on theallowedpowerconsumptionandinthiscase,1mAofsensingcurrentisassumed. The TL431 is used as the feedback amplifier. Given its 2.5-V reference voltage, the voltage-sensing dividers R andR canbeselectedwithEquation34andEquation35. FBU FBB V -2.5 V R = OUT =9.5kW FBU 1mA (34) 2.5 V R = =2.5kW FBB 1mA (35) Next step is to put the compensator zero f at 190 Hz, which is 1/10 of the target crossover frequency. Choose CZ C asafixedvalueof10nFandchoosethezeroresistorvalueaccordingtoEquation36. Z 1 1 R = = =83.77kW Z 2p´f ´C 2p´190Hz´10nF CZ Z (36) Next, place a pole at the lower of RHP-zero or the ESR-zero frequencies. Based previous analysis, the RHP zero is at 7.65 kHz and the ESR zero is at 6 kHz, so the pole of the compensation loop should be put at 6 kHz. This pole can be added through the primary side error amplifier. R and C provide the necessary pole. FB FB ChoosingR as10kΩ,C iscalculatedbyEquation37. FB FB 1 C = =2.65nF FB 2p´10kW´6kHz (37) Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation38. 1 1+S(cid:132)C (cid:132)R R 1 G:S; = (cid:132) Z Z(cid:132) FB2(cid:132) (cid:132)CTR(cid:132)R R (cid:132)R S(cid:132)C R S(cid:132)C (cid:132)R +1 EG FBU LED Z FB1 FB FB2 where • CTRisthecurrenttransferratiooftheopto-coupler.Choose1asthenominalvalueforCTR. • R istheopto-emitterpulldownresistorand1kΩischosenasadefaultvalue (38) EG Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com The only remaining unknown value required in this equation is R . The entire loop gain must be equal to 1 at LED thecrossoverfrequency.R iscalculatedaccordinglyas1.62kΩ. LED The final closed-loop Bode plots are shown in Figure 36 and Figure 37. The converter achieves approximately 2- kHzcrossoverfrequencyandapproximately70° ofphasemargin. TI recommends checking the loop stability across all the corner cases, including component tolerances, to ensuresystemstability. 100 -100 80 60 -120 Loop Gain (dB) 2400 Phase (Degree)-140 0 -160 -20 -40 -180 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure36.ConverterClosed-LoopBodePlot:Gain Figure37.ConverterClosed-LoopBodePlot:Phase 9.2.3 ApplicationCurves 100V/div 2µs/div 100V/div 2µs/div Figure38.PrimarySideMOSFETDraintoSourceVoltage Figure39.PrimarySideMOSFETDraintoSourceVoltage at240-VACInput at120-VACInput 30 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 CH1:outputvoltageACcoupled 200mV/div 100mV/div 10µs/div CH4:outputcurrent 1A/div 5ms/div Figure40.OutputVoltageDuring0.9-Ato2.7-ALoad Figure41.OutputVoltageRippleatFullLoad Transient 5V/div 2ms/div Figure42.OutputVoltageBehavioratFullLoadStart-Up 10 Power Supply Recommendations An internal VCC shunt regulator is incorporated into each member of the UCCx813-x family to limit the supply voltage to approximately 13.5 V. A series resistor from VCC to the input supply source is required with inputs above 12 V to limit the shunt regulator current. A maximum of 10 mA can be shunted to ground by the internal regulator. The internal regulator in conjunction with the device’s low start-up and operating current can greatly simplify powering the device and may eliminate the requirement for a regulated bootstrap auxiliary supply and winding in many applications. The supply voltage is MOSFET gate level compatible and requires no external Zener diode or regulator protection with a current-limited input supply. The UVLO start-up threshold is 1 V below the shunt regulator level on the UCCx813-[2,4] devices to ensure start-up. It is important to bypass the device's supply (VCC) and reference voltage (REF) pins each with a 0.1-µF to 1-µF ceramic capacitor to ground. The capacitorsmustbeplacedasclosetotheactualpin connections as possible for optimal noise filtering. A second, larger filter capacitor may also be required in offline applications to hold the supply voltage (V ) above the VCC UVLOturnoffthresholdduringstart-up. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com The UVLO start threshold of the UCC2813-[2,4] devices has a range of 11.5 V to 13.5 V, while the protection zener voltage can vary from 12 V to 15 V. However, the absolute maximum supply voltage of the IC is specified at 12 V. This absolute maximum is defined as the lowest possible Zener voltage when driven from a low impedance (voltage) source. The zener voltage is always higher than the UVLO start voltage. These two parameterstrackeachotherandthechipistestedtoguaranteethattheZenervoltagewillnever be below that of the start voltage. To limit the current flowing in the internal clamp zener, a series resistor must be added. Failure to provide a series resistance between the auxiliary voltage source and the Vcc pin of the controller, to limit the currentand voltage stress within rated levels on the Vcc pin may result in permanent damage to the controller. In automotive or industrial applications where there is a risk of high power load transients which may cause transients or voltage excursions on the Vcc rail supplying the PWM controller it is recommended to add an external Zener diode across the Vcc pin. The external Zener acts as an additional protection to the impedance providedbytheseriesresistorbetweentheVccsourceandVccpin. HV DC BUS Rstart Bootstrap Rvcc To Output VCC REF Caux UCC2813-X OUT Rg 1uF External 13V Zener (Recommended 0.1uF when there is a risk of Rcs transients on bias supply) Figure43. DifferentWaystoPowerUptheDevice Placing a resistor, Rg, in series with the gate of the mosfet allows the mosfet switching speed to be adjusted and alsocanbeusedtokeepthepeakgatedrivecurrentswithinthespecifiedlimitsofthecontroller. 11 Layout 11.1 Layout Guidelines In addition to following general power management IC layout guidelines (star grounding, minimal current loops, reasonableimpedancelevels,andsoon)layoutfortheUCCx813-xfamilymustconsiderthefollowing: • If possible, a ground plane should be used to minimize the voltage drop on the ground circuit and the noise introducedbyparasiticinductancesinindividualtraces. • A decoupling capacitor is required for each the VCC pin and REF pin and both must be returned to GND as closetotheICaspossible. • For the best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, useseparategroundtracesforthetimingcapacitorandallotherfunctions. • The CS pin filter capacitor must be as close to the IC possible and grounded right at the IC ground pin. This ensuresthebestfilteringeffectandminimizesthechanceofcurrentsensepinmalfunction. • Gate-drive loop area must be minimized to reduce the EMI noise generated by the high di/dt of the current in theloop. 32 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 11.2 Layout Example Figure44. UCC2813-0LayoutExampleforSingle-LayerPCB Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 SLUS161F–APRIL1999–REVISEDMAY2020 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: DifferencesBetweentheUCC3813andUCC3800PWMFamilies (SLUA247) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC2813-0 Clickhere Clickhere Clickhere Clickhere Clickhere UCC2813-1 Clickhere Clickhere Clickhere Clickhere Clickhere UCC2813-2 Clickhere Clickhere Clickhere Clickhere Clickhere UCC2813-3 Clickhere Clickhere Clickhere Clickhere Clickhere UCC2813-4 Clickhere Clickhere Clickhere Clickhere Clickhere UCC2813-5 Clickhere Clickhere Clickhere Clickhere Clickhere UCC3813-0 Clickhere Clickhere Clickhere Clickhere Clickhere UCC3813-1 Clickhere Clickhere Clickhere Clickhere Clickhere UCC3813-2 Clickhere Clickhere Clickhere Clickhere Clickhere UCC3813-3 Clickhere Clickhere Clickhere Clickhere Clickhere UCC3813-4 Clickhere Clickhere Clickhere Clickhere Clickhere UCC3813-5 Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.4 Community Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight fromtheexperts.Searchexistinganswersoraskyourownquestiontogetthequickdesignhelpyouneed. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do notnecessarilyreflectTI'sviews;seeTI'sTermsofUse. 12.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 34 SubmitDocumentationFeedback Copyright©1999–2020,TexasInstrumentsIncorporated ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

UCC2813-0,UCC2813-1,UCC2813-2,UCC2813-3,UCC2813-4,UCC2813-5 UCC3813-0,UCC3813-1,UCC3813-2,UCC3813-3,UCC3813-4,UCC3813-5 www.ti.com SLUS161F–APRIL1999–REVISEDMAY2020 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©1999–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2813D-0 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-0 2813D-0 UCC2813D-0G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-0 2813D-0 UCC2813D-1 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-1 2813D-1 UCC2813D-2 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-2 2813D-2 UCC2813D-2G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-2 2813D-2 UCC2813D-3 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-3 2813D-3 UCC2813D-4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-4 2813D-4 UCC2813D-5 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-5 2813D-5 UCC2813D-5G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-5 2813D-5 UCC2813DTR-0 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-0 2813D-0 UCC2813DTR-0G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-0 2813D-0 UCC2813DTR-1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-1 2813D-1 Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2813DTR-2 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-2 2813D-2 UCC2813DTR-3 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-3 2813D-3 UCC2813DTR-3G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-3 2813D-3 UCC2813DTR-4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-4 2813D-4 UCC2813DTR-4G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-4 2813D-4 UCC2813DTR-5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UCC2813 & no Sb/Br) D-5 2813D-5 UCC2813N-0 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2813N-0 & no Sb/Br) UCC2813N-1 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2813N-1 & no Sb/Br) UCC2813N-2 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2813N-2 & no Sb/Br) UCC2813N-4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2813N-4 & no Sb/Br) UCC2813N-5 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UCC2813N-5 & no Sb/Br) UCC2813PW-0 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28130 & no Sb/Br) UCC2813PW-1 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28131 & no Sb/Br) UCC2813PW-2 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28132 & no Sb/Br) UCC2813PW-3 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28133 & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC2813PW-3G4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28133 & no Sb/Br) UCC2813PW-4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28134 & no Sb/Br) UCC2813PW-5 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28135 & no Sb/Br) UCC2813PW-5G4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28135 & no Sb/Br) UCC2813PWTR-0 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28130 & no Sb/Br) UCC2813PWTR-1 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28131 & no Sb/Br) UCC2813PWTR-3 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28133 & no Sb/Br) UCC2813PWTR-4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28134 & no Sb/Br) UCC2813PWTR-4G4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28134 & no Sb/Br) UCC2813PWTR-5 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 28135 & no Sb/Br) UCC3813D-0 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-0 3813D-0 UCC3813D-1 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-1 3813D-1 UCC3813D-1G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-1 3813D-1 UCC3813D-2 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-2 3813D-2 UCC3813D-3 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-3 3813D-3 UCC3813D-4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-4 Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 3813D-4 UCC3813D-5 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-5 3813D-5 UCC3813DTR-0 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-0 3813D-0 UCC3813DTR-0G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-0 3813D-0 UCC3813DTR-1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-1 3813D-1 UCC3813DTR-1G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-1 3813D-1 UCC3813DTR-2 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-2 3813D-2 UCC3813DTR-3 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-3 3813D-3 UCC3813DTR-4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-4 3813D-4 UCC3813DTR-5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UCC3813 & no Sb/Br) D-5 3813D-5 UCC3813N-0 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-0 & no Sb/Br) UCC3813N-0G4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-0 & no Sb/Br) UCC3813N-1 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-1 & no Sb/Br) UCC3813N-2 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-2 & no Sb/Br) UCC3813N-2G4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-2 & no Sb/Br) Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC3813N-3 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-3 & no Sb/Br) UCC3813N-4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-4 & no Sb/Br) UCC3813N-5 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UCC3813N-5 & no Sb/Br) UCC3813PW-0 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38130 & no Sb/Br) UCC3813PW-1 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38131 & no Sb/Br) UCC3813PW-2 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38132 & no Sb/Br) UCC3813PW-3 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38133 & no Sb/Br) UCC3813PW-4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38134 & no Sb/Br) UCC3813PW-4G4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38134 & no Sb/Br) UCC3813PW-5 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38135 & no Sb/Br) UCC3813PW-5G4 ACTIVE TSSOP PW 8 150 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38135 & no Sb/Br) UCC3813PWTR-0 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38130 & no Sb/Br) UCC3813PWTR-0G4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38130 & no Sb/Br) UCC3813PWTR-3 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38133 & no Sb/Br) UCC3813PWTR-3G4 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38133 & no Sb/Br) UCC3813PWTR-5 ACTIVE TSSOP PW 8 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 38135 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 5

PACKAGE OPTION ADDENDUM www.ti.com 12-May-2020 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC2813-0, UCC2813-1, UCC2813-2, UCC2813-3, UCC2813-4, UCC2813-5 : •Automotive: UCC2813-0-Q1, UCC2813-1-Q1, UCC2813-2-Q1, UCC2813-3-Q1, UCC2813-4-Q1, UCC2813-5-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 6

PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC2813DTR-0 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2813DTR-1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2813DTR-2 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2813DTR-3 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2813DTR-4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2813DTR-5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2813PWTR-0 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC2813PWTR-1 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC2813PWTR-3 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC2813PWTR-4 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC2813PWTR-5 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC3813DTR-0 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3813DTR-1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3813DTR-2 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3813DTR-3 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3813DTR-4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3813DTR-5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC3813PWTR-0 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2020 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC3813PWTR-3 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 UCC3813PWTR-5 TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC2813DTR-0 SOIC D 8 2500 340.5 338.1 20.6 UCC2813DTR-1 SOIC D 8 2500 340.5 338.1 20.6 UCC2813DTR-2 SOIC D 8 2500 340.5 338.1 20.6 UCC2813DTR-3 SOIC D 8 2500 340.5 338.1 20.6 UCC2813DTR-4 SOIC D 8 2500 340.5 338.1 20.6 UCC2813DTR-5 SOIC D 8 2500 340.5 338.1 20.6 UCC2813PWTR-0 TSSOP PW 8 2000 367.0 367.0 35.0 UCC2813PWTR-1 TSSOP PW 8 2000 367.0 367.0 35.0 UCC2813PWTR-3 TSSOP PW 8 2000 367.0 367.0 35.0 UCC2813PWTR-4 TSSOP PW 8 2000 367.0 367.0 35.0 UCC2813PWTR-5 TSSOP PW 8 2000 367.0 367.0 35.0 UCC3813DTR-0 SOIC D 8 2500 340.5 338.1 20.6 UCC3813DTR-1 SOIC D 8 2500 340.5 338.1 20.6 UCC3813DTR-2 SOIC D 8 2500 340.5 338.1 20.6 UCC3813DTR-3 SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2020 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC3813DTR-4 SOIC D 8 2500 340.5 338.1 20.6 UCC3813DTR-5 SOIC D 8 2500 340.5 338.1 20.6 UCC3813PWTR-0 TSSOP PW 8 2000 367.0 367.0 35.0 UCC3813PWTR-3 TSSOP PW 8 2000 367.0 367.0 35.0 UCC3813PWTR-5 TSSOP PW 8 2000 367.0 367.0 35.0 PackMaterials-Page3

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP SEATING PLANE 6.2 PIN 1 ID A 0.1 C AREA 6X 0.65 8 1 3.1 2X 2.9 NOTE 3 1.95 4 5 0.30 8X 0.19 4.5 1.2 MAX B 0.1 C A B 4.3 NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.75 0 - 8 0.05 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) 1 TYP 8 SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) SYMM (R0.05) TYP 8X (0.45) 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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