UCC28060 UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 Natural Interleaving™ DUAL-PHASE TRANSITION-MODE PFC CONTROLLER NATURAL INTERLEAVING FEATURES SYSTEM FEATURES 1 • EasyPhaseManagementFacilitates • CostSavings 234 CompliancetoLight-LoadEfficientStandards • ImprovedEfficiencyandDesignFlexibility • FailSafeOVPwithDualPathsPreventsOutput overTraditional,Single-PhaseContinuous ConductionMode(CCM) Over-voltageConditionsCausedby Voltage-SensingFailures • InputFilterandOutputCapacitorCurrent Cancellation: • SensorlessCurrentShapingSimplifiesBoard – Reducedcurrentrippleforhighersystem LayoutandImprovesEfficiency reliabilityandsmallerbulkcapacitor • InrushSafeCurrentLimiting: – ReducedEMIfiltersize – PreventsMOSFETconductionduring • EnablesUseofLow-CostDiodeswithout inrush ExtensiveSnubberCircuitry – Eliminatesreverserecoveryeventsin • ImprovedLight-LoadEfficiency outputrectifiers • ImprovedTransientResponse • CompleteSystem-LevelProtection • 1-ASource/1.8-ASinkGateDrivers • OperatingTemperatureRange:–40°Cto 85-265VAC +125°CinanSOIC16-pinpackage EMI 400 VDC Filter - + APPLICATIONS VCC ZCDA GDA • 100-Wto800-WPowerSupplies CS VINAC ZCDB • LCD,Plasma,andDLP®TVs • ComputerPowerSupplies UCC28060 • EntryLevelServers TSET GDB • ElectronicLightingBallasts PWMCNTL Power-Good to Downstream Converter VSENSE 5 COMP POUT= 600 W PHB V = 400 V OUT VREF A) 4 nt ( 1-Phase TM HVSEN urre C AGND PGND e pl 3 p Ri 1-Phase CCM TypicalApplicationCircuit citor a ap 2 C 2-Phase TM Interleave 1 70 120 170 220 270 Input Voltage (V) RippleCurrentReduction 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. DLPisaregisteredtrademarkofTexasInstruments. 2 NaturalInterleavingisatrademarkofTexasInstuments. 3 Allothertrademarksarethepropertyoftheirrespectiveowners. 4 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com CONTENTS • OrderingInformation2 • ElectricalCharacteristics4 • DeviceInformation7 • FunctionalBlockDiagram9 • TypicalCharacteristics10 • ApplicationInformation17 • DesignExample23 • AdditionalReferences30 DESCRIPTION Optimized for high-volume consumer applications, this solution extends the advantages of transition mode—high efficiency with low-cost components—to higher power ratings than previously possible. By utilizing a Natural Interleaving technique, both channels operate as masters (that is, there is no slave channel) synchronized to the same frequency. This approach delivers inherently strong matching, faster responses, and ensures that each channeloperatesintransitionmode. Complete system-level protections feature input brownout, output over-voltage, open-loop, overload, soft-start, phase-fail detection, and thermal shutdown. The additional FailSafe over-voltage protection (OVP) feature protectsagainstshortstoanintermediatevoltagethat,ifundetected,couldleadtocatastrophicdevicefailure. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) PARTNUMBER PACKAGE(2) OPERATINGTEMPERATURERANGE,T A UCC28060D SOIC16-Pin(D) –40°Cto+125°C (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) SOIC(D)packageisavailabletapedandreeledbyaddingRtotheabovepartnumber.ReeledquantitiesforUCC28060DRare2500 devicesperreel. 2 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 ABSOLUTE MAXIMUM RATINGS(1) AllvoltagesarewithrespecttoGND,–40°C<T =T <+125°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. UCC28060 UNIT VCC(2) –0.5to+21 PWMCNTL –0.5to+20 Inputvoltagerange V COMP(3),CS,PHB,HVSEN(4),VINAC(4),VSENSE(4) –0.5to+7 ZCDA,ZCDB –0.5to+4 Continuousinputcurrent VCC 20 Inputcurrent PWMCNTL 10 Inputcurrentrange ZCDA,ZCDB,VSENSE –5to+5 mA Outputcurrent VREF –10 Continuousgatecurrent GDA,GDB(5) ±25 Operating –40to+125 Junctiontemperature,T J Storage –65to+150 °C Leadtemperature,T Soldering,10s +260 SOL (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionbeyondthoseincludedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsoftimemayaffectdevicereliability. (2) VoltageonVCCisinternallyclamped.VCCmayexceedtheabsolutemaximuminputvoltageifthesourceiscurrentlimitedbelowthe absolutemaximumcontinuousVCCinputcurrentlevel. (3) Innormaluse,COMPisconnectedtocapacitorsandresistorsandisinternallylimitedinvoltageswing. (4) Innormaluse,VINAC,VSENSE,andHVSENareconnectedtoresistorsandareinternallylimitedinvoltageswing.Althoughnot recommendedforextendeduse,VINAC,VSENSE,andHVSENcansurviveinputcurrentsashighas±10mAfromhighvoltage sources. (5) NoGDAorGDBcurrentlimitingisrequiredwhendrivingapowerMOSFETgate.However,asmallseriesresistormayberequiredto dampringingduetostrayinductance.SeeFigure13andFigure14fordetails. DISSIPATION RATINGS THERMALIMPEDANCE PACKAGE JUNCTION-TO-AMBIENT T =+25°CPOWERRATING T =+85°CPOWERRATING A A SOIC16-Pin(D) 140°C/W(1) 890mW(1) 460mW(1) (1) TestedperJEDECEIA/JESD51-1.Thermalresistanceisastrongfunctionofboardconstructionandlayout.Airflowwillreducethermal resistance.Thisnumberisonlyageneralguide;seeTIdocumentSPRA953deviceThermalMetrics. RECOMMENDED OPERATING CONDITIONS AllvoltagesarewithrespecttoGND,–40°C<T =T <+125°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. MIN MAX UNIT VCCinputvoltagefromalow-impedancesource 14 21 V VCCinputcurrentfromahigh-impedancesource 8 18 mA VREFloadcurrent 0 –2 mA VINACInputvoltage 0 6 V ZCDA,ZCDBseriesresistor 20 80 kΩ TSETresistortoprogramPWMon-time 66.5 270 kΩ HVSENinputvoltage 0.8 4.5 V PWMCNTLpull-upresistortoVREF 1 10 kΩ ELECTROSTATIC DISCHARGE (ESD) PROTECTION RATING UNIT Humanbodymodel(HBM) 2000 V Chargeddevicemodel(CDM) 500 V Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,–40°C<T =T <+125°C,andcurrentsarepositiveintoandnegativeoutof J A thespecifiedterminal,unlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VCCBIASSUPPLY VCC(shunt) VCCshuntvoltage(1) IVCC=10mA 22 24 26 V IVCC(stby) VCCcurrent,disabled VSENSE=0V 100 200 m A IVCC(on) VCCcurrent,enabled VSENSE=6V 5 8 mA UNDERVOLTAGELOCKOUT(UVLO) VCC(on) VCCturn-onthreshold 11.5 12.6 13.5 V VCC(off) VCCturn-offthreshold 9.5 10.35 11.5 V UVLOHysteresis 1.85 2.25 2.65 V REFERENCE VREF VREFoutputvoltage,noload IVREF=0mA 5.82 6.00 6.18 V VREFchangewithload 0mA≤IVREF ≤ –2mA 1 6 mV VREFchangewithVCC 12V≤VCC≤20V 1 10 mV ERRORAMPLIFIER VSENSEinputregulationvoltage TA=+25°C 5.85 6.00 6.15 V VSENSEinputregulationvoltage 5.82 6.00 6.18 V VSENSEinputbiascurrent Inregulation 125 300 800 nA COMPhighvoltage,clamped VSENSE=5.8V 4.70 4.95 5.10 V COMPlowvoltage,saturated VSENSE=6.2V 0.03 0.125 V gm VSENSEtoCOMPtransconductance C5.O94MVP<=V3SVE,NSE<6.06V 75 96 110 m S COMPsourcecurrent,overdriven VSENSE=5V,COMP=3V –120 –160 –190 m A COMPsinkcurrent VSENSE=6.4V,COMP=3V 18 25 32 m A VSENSEthresholdforCOMPoffsetenable,down fromVREF VoltagebelowVREF 135 185 235 mV VOVP VSENSEover-voltagethreshold,rising 6.25 6.45 6.7 V VSENSEover-voltagehysteresis 0.1 0.2 0.4 V VSENSEenablethreshold,rising 1.15 1.25 1.35 V VSENSEenablehysteresis 0.02 0.05 0.2 V OUTPUTMONITORING VPWMCNTL HVSENthresholdtoPWMCNTL HVSENrising 2.35 2.50 2.65 V HVSENinputbiascurrent,high HVSEN=3V –0.5 0.5 m A HVSENinputbiascurrent,low HVSEN=2V 28 36 41 m A HVSENrisingthresholdtoover-voltagefault 4.64 4.87 5.1 V HVSENfallingthresholdtoover-voltagefault 4.45 4.67 4.80 V PHB=5V, PhaseFailfiltertimetoPWMCNTLhigh 8 14 20 ms ZCDAswitching,ZCDB=0.5V PWMCNTLleakagecurrenthigh HVSEN=2V,PWMCNTL=15V –1 1 m A PWMCNTLoutputvoltagelow HVSENS=3V,IPWMCNTL=5mA 0.2 0.5 V (1) ExcessiveVCCinputvoltageandcurrentwilldamagethedevice.Thisclampdoesnotprotectthedevicefromanunregulatedsupply.If anunregulatedsupplyisused,aFixedPositiveVoltageRegulatorsuchastheUA78L15Aisrecommended.SeetheAbsoluteMaximum RatingstableforthelimitsonVCCvoltageandcurrent. 4 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 ELECTRICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,–40°C<T =T <+125°C,andcurrentsarepositiveintoandnegativeoutof J A thespecifiedterminal,unlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT GATEDRIVE(2) GDA,GDBoutputvoltagehigh IGDA,IGDB=–100mA 11.5 13 15 V GDA,GDBoutputvoltagehigh,clamped VCC=20V,IGDA,IGDB=–5mA 12 13.5 15 V GDA,GDBoutputvoltagehigh,lowVCC VCC=12V,IGDA,IGDB=–5mA 10 10.5 11.5 V GDA,GDBon-resistancehigh IGDA,IGDB=–100mA 8 14 Ω GDA,GDBoutputvoltagelow IGDA,IGDB=100mA 0.15 0.3 V GDA,GDBon-resistancelow IGDA,IGDB=100mA 2 3 Ω Risetime 1Vto9V,CLOAD=1nF 18 30 ns Falltime 9Vto1V,CLOAD=1nF 12 25 ns GDA,GDBoutputvoltageUV IGDA,IGDB=2.5mA 1.6 2 V ZEROCURRENTDETECTOR ZCDA,ZCDBvoltagethreshold,falling 0.8 1.0 1.2 V ZCDA,ZCDBvoltagethreshold,rising 1.5 1.68 1.88 V ZCDA,ZCDBclamp,high IZCDA=+2mA,IZCDB=+2mA 2.6 3.0 3.4 V ZCDA,ZCDBinputbiascurrent ZCDA=1.4V,ZCDB=1.4V –0.5 0.5 m A ZCDA,ZCDBclamp,low IZCDA=–2mA,IZCDB=–2mA –0.4 –0.2 0 V ZCDA,ZCDBdelaytoGDA,GDBoutputs(2) Respectivegatedriveoutputrising10% 45 100 ns fromzerocrossinginputfallingto1V CURRENTSENSE CSinputbiascurrent Atrisingthreshold –150 –250 m A CScurrentlimitrisingthreshold –0.18 –0.20 –0.22 V CScurrentlimitfallingthreshold –0.005 –0.015 –0.029 V CScurrentlimitresponsetime(2) FromCSexceedingthreshold–0.05Vto 60 100 ns GDxdropping10% MAINSINPUT VINACinputbiascurrent VINAC=2V –0.5 0.5 m A VINAClinerangethreshold,rising ToPWMon-timechange 3.25 3.45 3.60 V VINAClinerangethreshold,falling 3.05 3.20 3.35 V VINAClinefallingrangechangefiltertime(2) VINAClinechangesforlessthantherange 18 26 36 ms changefiltertime BROWNOUT VINACbrownoutthreshold VINACfalling 1.34 1.39 1.44 V VINACbrownoutcurrent VINAC=1V 5 7 9 m A VINACfailstoexceedthebrownout VINACbrownoutfiltertime 340 440 540 ms thresholdforthebrownoutfiltertime (2) RefertoFigure13,Figure14,Figure15,andFigure16intheTypicalCharacteristicsfortypicalgatedrivewaveforms. Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,–40°C<T =T <+125°C,andcurrentsarepositiveintoandnegativeoutof J A thespecifiedterminal,unlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT PULSE-WIDTHMODULATOR KTH On-timefactor,phasesAandB,highrange VINAC=3.75V,VSENSE=5.8V(3) 1.25 1.35 1.5 m s/V KTHS On-timefactor,single-phase,A,highrange VPIHNBAC=0=V3.(73)5V,VSENSE=5.8V, 2.4 2.7 3.0 m s/V KTL On-timefactor,phasesAandB,lowrange VINAC=3.2V,VSENSE=5.8V(3) 3.6 4.0 4.4 m s/V KTLS On-timefactor,single-phase,A,lowrange VPIHNBAC=0=V3.(23)V,VSENSE=5.8V, 7.2 8 8.9 m s/V PhaseBtophaseAon-timematching, VSENSE=5.8V,VINAC=3.2V –6 6 % lowlinerange PhaseBtophaseAon-timematching, VSENSE=5.8V,VINAC=3.75V –6 6 % highlinerange Zero-crossingdistortioncorrectionadditionalon COMP=0.25V,VINAC=1V 2 m s time COMP=0.25V,VINAC=0.1V 20 m s PHBthresholdfalling,tosingle-phaseoperation, ToGDBoutputshutdownVINAC=1.5V 0.7 0.8 0.9 V lowlinerange PHBthresholdrising,totwo-phaseoperation, ToGDBoutputrunningVINAC=1.5V 0.9 1.0 1.1 V lowlinerange PHBthresholdfalling,tosingle-phaseoperation, ToGDBoutputshutdownVINAC=4.0V 1.0 1.1 1.2 V highlinerange PHBthresholdrising,totwo-phaseoperation, ToGDBoutputrunningVINAC=4.0V 1.2 1.3 1.4 V highlinerange COMPthresholdfallingtoshutdown GDAandGDBoutputsshutdown 0.125 0.150 0.175 V COMPthresholdrisingtorun GDAandGDBoutputsrunning 0.17 0.20 0.23 V T(min) Minimumswitchingperiod RTSET=133kΩ(3) 1.7 2.2 2.5 m s PWMrestarttime ZCDA=ZCDB=2V(4) 165 200 265 m s THERMALSHUTDOWN Thermalshutdowntemperature TJ,temperaturerising(5) +160 °C Thermalrestarttemperature TJ,temperaturefalling(5) +140 °C (3) Gatedriveon-timeisproportionaltoV –125mV.Theon-timeproportionalityfactor,K ,isdifferentinhighandlowrangesandalso COMP T differentintwo-phaseandsingle-phasemodes.Theon-timefactor,K ,scaleslinearlywiththevalueofR .Theminimumswitching T TSET periodisproportionaltoR . TSET (4) Anoutputon-timeisgeneratedatbothGDAandGDBifbothZCDAandZCDBnegative-goingedgesarenotdetectedfortherestart time.Insingle-phasemode,therestarttimeappliesfortheZCDAinputandtheGDAoutput. (5) Thermalshutdownoccursattemperatureshigherthanthenormaloperatingrange.Deviceperformanceabovethenormaloperating temperatureisnotspecifiedorassured. 6 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 DEVICE INFORMATION UCC28060D SOIC16-Pin(D) TopView ZCDB 1 16 ZCDA VSENSE 2 15 VREF TSET 3 14 GDA PHB 4 13 PGND COMP 5 12 VCC AGND 6 11 GDB VINAC 7 10 CS HVSEN 8 9 PWMCNTL TERMINALFUNCTIONS TERMINAL DESCRIPTION NAME NO. I/O Analogground:Connectanalogsignalbypasscapacitors,compensationcomponents,andanalog AGND 6 — signalreturnstothispin.Connecttheanalogandpowergroundsatasinglepointtoisolatehigh-current noisesignalsofthepowercomponentsfrominterferencewiththelow-currentanalogcircuits. Erroramplifieroutput:Theerroramplifierisatransconductanceamplifier,sothisoutputisa high-impedancecurrentsource.Connectvoltageregulationloopcompensationcomponentsfromthis pintoAGND.Theon-timeseenatthegatedriveoutputsisproportionaltothevoltageatthispinminus anoffsetofapproximately125mV.Duringsoft-startevents(undervoltage,brownout,ordisable),COMP COMP 5 O ispulledlow.Normaloperationonlyresumesafterthesoft-starteventclearsandCOMPhasbeen dischargedbelow0.5V,makingsurethatthecircuitrestartswithalowCOMPvoltageandashort on-time.DonotconnectCOMPtoalow-impedancesourcethatwouldinterferewithCOMPfallingbelow 0.5V. Currentsenseinput:Connectthecurrentsenseresistorandthenegativeterminalofthediodebridge tothispin.ConnectthereturnofthecurrentsenseresistortotheAGNDpinwithaseparatetrace.As inputcurrentincreases,thevoltageonCSgoesmorenegative.Thiscycle-by-cycleover-current protectionlimitsinputcurrentbyturningoffbothgatedriver(GDx)outputswhenCSismorenegative thantheCSrisingthreshold(approximately–200mV).TheGDoutputsremainlowuntilCSfallstothe CSfallingthreshold(approximately–15mV).Currentsenseisblankedforapproximately100ns CS 10 I followingthefallingedgeofeitherGDoutput.Thisblankingfiltersnoisethatoccurswhencurrent switchesfromapowerFETtoaboostdiode.Inmostcases,noadditionalcurrentsensefilteringis required.Iffilteringisrequired,thefilterseriesresistancemustbeunder100Ωtomaintainaccuracy.To preventexcessivenegativevoltageontheCSpinduringinrushconditions,connectthecurrentsensing resistortotheCSpinthroughalowvalueexternalresistor.Aswiththefilterseriesresistance,this externalresistorneedstobeunder100Ωtomaintainaccuracy. GDA 14 O ChannelAandchannelBgatedriveoutput:ConnectthesepinstothegateofthepowerFETfor eachphasethroughtheshortestconnectionpractical.Ifitisnecessarytouseatracelongerthan0.5in GDB 11 O (12.6mm)forthisconnection,someringingmayoccurduetotraceseriesinductance.Thisringingcan bereducedbyaddinga5-Ωto10-ΩresistorinserieswithGDAandGDB. Highvoltageoutputsense:TheUCC28060incorporatesFailSafeOVPsothatanysinglefailuredoes notallowtheoutputtoboostabovesafelevels.Outputover-voltageismonitoredbybothVSENSEand HVSENandshutsdownthePWMifeitherpinexceedstheappropriateover-voltagethreshold.Using twopinstomonitorforover-voltageprovidesredundantprotectionandfaulttolerance.HVSENcanalso beusedtoenableadownstreampowerconverterwhenthevoltageonHVSENiswithintheoperating HVSEN 8 I region.SelecttheHVSENdividerratioforthedesiredover-voltageandpower-goodthresholds.Select theHVSENdividerimpedanceforthedesiredpower-goodhysteresis.Duringoperation,HVSENmust neverfallbelow0.8V.DroppingHVSENbelow0.8VputstheUCC28060intoaspecialtestmode,used onlyforfactorytesting.AbypasscapacitorfromHVSENtoAGNDisrecommendedtofilternoiseand preventfalseover-voltageshutdown. Powergroundfortheintegratedcircuit:ConnectthispintoAGNDthroughaseparateshorttraceto PGND 13 — isolategatedrivernoisefromanalogsignals. Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com TERMINALFUNCTIONS(continued) TERMINAL DESCRIPTION NAME NO. I/O PhaseBenable:Thispinturnson/offchannelBoftheboostconverter.Thecommandedon-timefor channelAisimmediatelydoubledwhenchannelBisdisabled,whichhelpstokeepCOMPvoltage constantduringthephasemanagementtransient.ThePHBthresholdschangewithlinerangeforthe PHB 4 I bestefficiencywhenPHBisconnectedtoCOMP.PHBcanalsobedrivenbyexternallogicsignalsto allowcustomizedphasemanagement.Todisablephasemanagement,connectthePHBpintothe VREFpin. PWMenablelogicoutput:Thisopen-drainoutputgoeslowwhenHVSENiswithintheHVSENgood PWMCNTL 9 O regionandtheZCDAandZCDBinputsareswitchingcorrectlyifoperatingintwo-phasemode(seePHB Pin).Otherwise,PWMCNTLishighimpedance. Timingset:PWMon-timeprogramminginput.ConnectaresistorfromTSETtoAGNDtosetthe TSET 3 I on-timeversusCOMPvoltageandtheminimumperiodatthegatedriveoutputs. Biassupplyinput:Connectthispintoacontrolledbiassupplyofbetween14Vand21V.Alsoconnect VCC 12 — a0.1-m FceramicbypasscapacitorfromthispintoPGND.Thissupplypowersallcircuitsinthedevice andmustbecapableofdelivering6mAdcplusthetransientpowerMOSFETgatechargingcurrent. Inputacvoltagesense:Fornormaloperation,connectthispintoavoltagedivideracrosstherectified inputpowermains.Thisinputsensesinputvoltagerangetosettheramprateandsensesbrownout. InputvoltagerangechangeswhenthepeakvoltageonVINACbecomesandstaysbelowtherange changethresholdfortherangechangefiltertimeorthepeakvoltageonVINACbecomesabovethe VINAC 7 I rangechangethreshold.WhenthevoltageonVINACremainsbelowthebrownoutthresholdformore thanthebrownoutfiltertime,thedeviceentersabrownoutmodeandbothoutputdrivesaredisabled. Selecttheinputvoltagedividerratioforthedesiredbrownoutthresholdandpowerlinerange.Selectthe dividerimpedanceforthedesiredbrownouthysteresis. Voltagereferenceoutput:Connecta0.1-m FceramicbypasscapacitorfromthispintoAGND. VREF 15 O This6VDCreferencecanbeusedtobiasothercircuitsrequiringlessthan2mAoftotalsupplycurrent. Outputdcvoltagesense:Connectthispintoavoltagedivideracrosstheoutputofthepower converter.Theerroramplifierreferencevoltageis6V.Selecttheoutputvoltagedividerratioforthe desiredoutputvoltage.Connectthegroundsideofthisdividertogroundthroughaseparateshorttrace VSENSE 2 I forbestoutputregulationaccuracyandnoiseimmunity.VSENSEcanbepulledlowbyanopen-drain logicoutputor6-Vlogicoutputinserieswithalow-leakagediodetodisabletheoutputsandreduce VCCcurrent.IfVSENSEisdisconnected,open-loopprotectionprovidesaninternalcurrentsourceto pullVSENSElow,turningoffthegatedrivers. Zerocurrentdetectioninputs:Theseinputsexpecttoseeanegativeedgewhentheinductorcurrent intherespectivephasesgotozero.Theinputsareclampedat0Vand3V.Signalsshouldbecoupled ZCDA 16 I throughaseriesresistorthatlimitstheclampingcurrenttolessthan±3mA.Connectthesepinsthrough acurrentlimitingresistortothezerocrossingdetectionwindingsoftheappropriateboost inductor.Theinductorwindingmustbeconnectedsothatthisvoltagedropswheninductorcurrent decaystozero.Whentheinductorcurrentdropstozero,theZCDinputmustdropbelowthefalling ZCDB 1 I threshold,approximately1V,tocausethegatedriveoutputtorise.WhenthepowerMOSFETturnsoff, theZCDinputmustriseabovetherisingthreshold,approximately1.7V,toarmthelogicforanother fallingZCDedge. 8 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 FUNCTIONALBLOCKDIAGRAM Overcurrent HVSENOV STOPA OV CS 10 OC TSD STOPB -0.2V/-0.015V + OC BurstOperation SinglePhase 1.4V + 440msDelay Brownout VINAC 7 Thermal 12.6V ShutDown + 10.35V UV T + J TSD 7mA (UCC28060only) 160C 12 VCC InputRange 24V + 26ms _ H LDelay 3.20V STOPA 13.5V Crossover PhaseA Notch 14 GDA OnTimeControl Reduction PGND TSET 3 Interleave Control ZCDA 16 ZCA 13.5V 1.68V/1V + PhaseB 11 GDB OnTimeControl ZCB ZCDB 1 13 PGND 1.68V/1V + 150mV + BurstOperation (UCC28060only) STOPB VREF 15 6V UV Brownout HVSENOV UV EN + OV(UCC28061only) 4.87V EN + gm + 8 HVSEN VSENSE 2 4.95V 1.1V(HIGH-LINE + 2.5V 96ms UCC28060only) SinglePhase 0.8V(LOW-LINE) EN 36mA 1.25V + PhaseFail 6.45V Detector Phase OV + OK 300nA 5 4 6 9 COMP PHB AGND PWMCNTL Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,T =T =+25°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. BIASSUPPLYCURRENT BIASSUPPLYCURRENT vs vs BIASSUPPLYVOLTAGE TEMPERATURE 5.5 6.0 Operating 5.0 5.8 4.5 A A 5.6 m m - 4.0 - 5.4 nt nt e 3.5 e rr rr 5.2 u u C 3.0 C ply ply 5.0 p 2.5 p u u S VCC Turn-Off VCC Turn-On S 4.8 s 2.0 s a a Bi Bi 4.6 - 1.5 - C C IVC 1.0 IVC 4.4 0.5 4.2 0 4.0 0 2 4 6 8 10 12 14 16 18 20 -40 -20 0 20 40 60 80 100 120 V -Bias Supply Voltage-V T -Temperature-°C VCC J Figure1. Figure2. BIASSUPPLYCURRENT vs TEMPERATURE ERRORAMPLIFIERTRANSFERFUNCTION 140 40 20 120 Transconductance 96mS Sink Current 0 A 25mA m - 100 A -20 nt m Input Regulation Voltage urre nt- -40 0mA at 6.0 V C 80 e y urr -60 pl C Sup 60 put -80 COMP Offset Enable as Out -100 165 mV Down from Bi- 40 -P -120 Regulation Voltage CC OM IV IC -140 20 -160 Disabled Source Current Overdriven -160mA 0 -180 -40 -20 0 20 40 60 80 100 120 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 T -Temperature-°C V -Input Voltage-V J VSENSE Figure3. Figure4. 10 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 TYPICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,T =T =+25°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. ERRORAMPLIFIERTRANSCONDUCTANCE ERRORAMPLIFIEROUTPUTCURRENT vs vs TEMPERATURE OUTPUTVOLTAGE 110 11 5.94 V < VSENSE< 6.06 V 10 105 9 s A m m 8 ce- 100 nt- 7 n e a r ct ur 6 u C ond 95 put 5 sc ut an O 4 Tr 90 - P - M 3 gm ICO 85 2 1 V = 6.1 V SENSE 80 0 -40 -20 0 20 40 60 80 100 120 0 1 2 3 4 5 T -Temperature-°C V -Output Voltage-V J COMP Figure5. Figure6. ERRORAMPLIFIERINPUTBIASCURRENT CURRENTSENSEINPUTBIASCURRENT vs vs INPUTVOLTAGE TEMPERATURE 440 150 400 A m - A 360 nt 145 n re - 320 ur nt C urre 280 Bias 140 sC 240 ut Bia np -Input NSE 211062000 ent Sense I 135 IVSE 80 Curr 130 - 40 S C I 0 125 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 -40 -20 0 20 40 60 80 100 120 V -Input Voltage-V T -Temperature-°C VSENSE J Figure7. Figure8. Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,T =T =+25°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. ZEROCURRENTDETECTCLAMPCURRENT ZEROCURRENTDETECTCLAMPCURRENT vs vs HIGHINPUTVOLTAGE LOWINPUTVOLTAGE 5 0 -0.5 4 A A m m -1.0 - - nt 3 nt re re -1.5 r r u u C C p p m m -2.0 a 2 a Cl Cl - - D D -2.5 C C Z Z I I 1 -3.0 0 -3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 V -Input Voltage-V V -Input Voltage-V ZCD ZCD Figure9. Figure10. BROWNOUTFILTERDELAYTIME RANGECHANGEFILTERDELAYTIME vs vs TEMPERATURE TEMPERATURE 500 30 490 29 480 s m s 470 28 m - -e 460 me 27 m 450 Ti Ti y Delay 444300 er Dela 2265 Filter 441200 e Filt 24 ut 400 arg o h 23 Brown 338900 nge C 22 a 370 R 21 360 350 20 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 T -Temperature-°C T -Temperature-°C J J Figure11. Figure12. 12 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 TYPICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,T =T =+25°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. GATEDRIVERISING GATEDRIVEFALLING vs vs TIME TIME 14 3.0 14 3.0 VCC= 20 V and 12 V VCC= 20 V and 12 V 12 CLOAD= 4.7 nF 2.5 12 CLOAD= 4.7 nF 2.5 A A 10 2.0 - 10 2.0 - V GD Voltage: ntV GD Sink Current: nt -put 8 GD Source Current: VVCC== 2102 VV 1.5 Curre-put 8 VVCC== 2102 VV 1.5 Curre ut V = 20 V CC e ut CC e ve O 6 VCCCC= 12 V 1.0 ourcve O 6 1.0 ourc ate Dri 4 0.5 Drive Sate Dri 4 0.5 Drive S G 2 0 ate G 2 0 ate G G GD Voltage: 0 -0.5 0 V = 20 V -0.5 CC V = 12 V CC -2 -1.0 -2 -1.0 0 50 100 150 200 250 300 350 0 20 40 60 80 100 120 140 Time-ns Time-ns Figure13. Figure14. GATEDRIVERISING GATEDRIVEFALLING vs vs TIMEANDDELAYFROMZCDINPUT TIMEANDDELAYFROMCSINPUT 7 14 500 14 C = 4.7 nF C = 4.7 nF LOAD LOAD 6 12 400 12 5 10 V 300 10 GD Output: Vm V -ZCD InputV 432 TTTJJJ=== -++421052°5°CC°C 864 -Gate Drive Output-Current Sense Input -2110000000 CVoSl tIangpeut GTTTJJJD=== O -++u421t052p°5°uCC°tC: 8642 -Gate Drive Output 1 2 -200 0 0 0 ZCD Input Voltage -300 -2 -1 -2 -25 0 50 100 150 200 250 300 -25 0 50 100 150 200 250 300 Time-ns Time-ns Figure15. Figure16. Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,T =T =+25°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. GATEDRIVEOUTPUTHIGH GATEDRIVEOUTPUTINUVLO vs vs VCC SINKCURRENT 15 2.5 R = 2.7 kW LOAD 14 T =-40°C J 2.0 T =-40°C 13 J V V - T = +25°C - J e T = +125°C e g J g 1.5 a 12 a olt olt T = +25°C V V J e e Driv 11 Driv 1.0 ate ate TJ= +125°C G 10 G 0.5 9 8 0 10 11 12 13 14 15 16 17 18 19 20 0 1 2 3 4 5 6 7 8 9 10 V -Bias Supply Voltage-V Gate Drive Sink Current-mA VCC Figure17. Figure18. GATEDRIVEHIGHVOLTAGE ON-TIMEFACTOR vs vs TEMPERATURE TIMESETTINGRESISTOR 15 10 14 9 13 Clamped VCC³15 V 8 K V TL V 12 s/ 7 m - - ge 11 or 6 olta Unclamped VCC = 12 V act V 10 F 5 ve me Gate Dri 98 On-Ti- 43 (UCC28060 only) KT KTH 7 2 6 1 R = 2 kW LOAD 5 0 -40 -20 0 20 40 60 60 100 120 60 80 100 120 140 160 180 200 220 240 260 280 T -Temperature-°C R -Time Setting Resistor-kW J TSET Figure19. Figure20. 14 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 TYPICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,T =T =+25°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. ON-TIMEFACTORPHASEAANDB,LOWRANGE ON-TIMEFACTORPHASEAANDB,HIGHRANGE vs vs TEMPERATURE TEMPERATURE 9 3.0 R = 266 kW TSET 8 RTSET= 266 kW 2.5 7 V V s/ s/ m m - 6 - 2.0 or or ct 5 ct a a e F RTSET= 133 kW e F 1.5 m 4 m Ti Ti R = 133 kW n- n- TSET O 3 O 1.0 - - TL TH RTSET= 66 kW K 2 K RTSET= 66 kW 0.5 1 0 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 T -Temperature-°C T -Temperature-°C J J Figure21. Figure22. ON-TIMEFACTOR PWMRESTARTTIME vs vs PHASESHIFT TEMPERATURE 110 300 GDA R = 266 kW GDB 108 TSET 275 106 R = 133 kW TSET 250 104 s R = 66 kW m TSET - % 102 me 225 -K/KTT0 10908 Restart Ti 210705 M 96 W P 150 94 2(K ´K ) TA TB K = 92 T0 KTA+ KTB 125 90 100 150 160 170 180 190 200 210 -40 -20 0 20 40 60 80 100 120 Phase Shift of GDA Relative to GDB-Degrees T -Temperature-°C J Figure23. Figure24. Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) AtVCC=16V,AGND=PGND=0V,VINAC=3V,VSENSE=6V,HVSEN=3V,PHB=5V,R =133kΩ;allvoltages TSET arewithrespecttoGND,alloutputsunloaded,T =T =+25°C,andcurrentsarepositiveintoandnegativeoutofthe J A specifiedterminal,unlessotherwisenoted. ADDITIONALON-TIME vs VINACZERO-CROSSINGDISTORTIONCORRECTION 100 R = 266 kW TSET R = 133 kW TSET s RTSET= 66 kW m - 10 e m Ti n- O al n o diti 1 d A 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 V -Input AC Voltage Sense-V VINAC Figure25. 16 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 APPLICATION INFORMATION Theory of Operation The UCC28060 contains the control circuits for two boost pulse-width modulation (PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on the error amplifier output. Each power converter then turns off the power MOSFET until current in the boost inductor decays to 0, as sensed on the zero current detection inputs (ZCDA and ZCDB). Once the inductor current decays to 0, the power converter starts another cycle. This on/off cycling produces a triangle wave of current,withpeakcurrentsetbytheon-timeandpowermainsinputvoltage,asshowninEquation1. VINAC (t)´T ON I (t) = PEAK L (1) Theaveragelinecurrentisexactlyequaltohalfofthepeaklinecurrent,asshowninEquation2. VINAC (t)´T ON I (t) = AVG 2´L (2) With T and L being essentially constant during an ac line period, the resulting triangular current waveform ON during each switching cycle has an average value proportional to the instantaneous value of the rectified ac line voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a near-unitypowerfactor. The outputs of the two PWMs operate 180° out-of-phase so that power-line ripple current for the two PWMs is greatly reduced from the ripple current of each individual PWM. This design reduces ripple current at the input andoutput,allowingthereductioninsizeandcostofinputandoutputfilters. Optimal phase balance occurs if the individual power stages and the on-times are well-matched. Mismatches in inductorvaluesdonotaffectthephaserelationship. On-Time Control, Maximum Frequency Limiting, and Restart Timer Gatedriveon-timevarieswiththeerroramplifieroutputvoltagebyafactorcalledK ,asshowninEquation3. T T = K (V -125 mV) ON T COMP (3) Where: V istheoutputoftheerroramplifier,and125mVisamodulatoroffset. COMP Tocompensatefortheeffectsoflinevoltagechangesonloopgain,K isthreetimeslargerinlow-linerangethan T inhigh-linerange,asshowninEquation4. K = 3´K TL TH (4) To provide smooth transition between two-phase and single-phase operation, K increases by a factor of two in T single-phasemode: • K =2×K ;activeinhigh-linerangeandsingle-phaseoperation THS TH • K =2×K ;activeinlow-linerangeandsingle-phaseoperation TLS TL The clamped maximum output of the error amplifier is limited to 4.95 V. This value, less the 125 mV modulator offset,limitson-timetoEquation5. T = K ´4.825 V ON(max) T (5) Thison-timelimitsetsthemaximumpowerthatcanbedeliveredbytheconverteratagiveninputvoltagelevel. The switching frequency of each phase is limited by minimum period timers. If the current decays to 0 before the minimumperiodtimerelapses,turn-onisdelayed,resultingindiscontinuousphasecurrent. The restart timer ensures starting under all circumstances by restarting both phases if either phase ZCD input has not transitioned high-to-low for approximately 200 m s. To prevent the circuit from operating in continuous conductionmode(CCM),therestarttimedoesnottriggerturn-onuntilbothphasecurrentsreturnto0. Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com The on-time factors (K , K , K , K ) and the minimum switching period T are proportional to the time TH THS TL TLS MIN setting resistor R , the resistor from the TSET pin to ground, and they can be calculated by Equation 6 TSET throughEquation8: R ms K = TSET ´1.35 ; Active in High-Line Range (UCC28060 only) TH 133 kW V (6) R ms K = TSET ´4.0 ; Active in Low-Line Range TL 133 kW V (7) R T = TSET ´2.2ms; Minimum Switching Period MIN 133 kW (8) The proper value of R results in the clamped maximum on-time, T , required by the converter operating TSET ON(max) attheminimuminputlineandmaximumload. Natural Interleaving Undernormaloperatingconditions,theUCC28060regulatestherelativephasing of the channel A and channel B inductor currents to be very close to 180°, minimizing the ripple currents seen at the line source and output capacitor. The phase control function differentially modulates the on-times of the A and B channels based on the phase and frequency relationship. This natural interleaving method allows the converter to achieve 180° phase shift and transition mode operation for both phases without the requirements on boost inductor tolerance. As a result, the current sharing of the A and B channels are proportional to the inductor tolerance. The best current sharingisachievedwhenbothinductorsareexactlythesamevalue. Easy Phase Management At light load conditions, because of the small conduction losses resulting from small load current and large switching losses caused by the discharging of the MOSFET junction capacitors, shutting down one of the power stages reduces switching loss and increases conduction loss. At certain power levels, the reduction of switching losses is greater than the increase in conduction losses; better efficiency can be realized. This feature is one of the major benefits of interleaved power factor correction (PFC) and it is especially valuable for meeting light-load efficientstandardsdesignrequirements. The easy phase management function allows the user to shut down one of the power stages to achieve higher efficiency at light load conditions by connecting the COMP pin to the PHB pin. Based on theoretical analysis and experimental results, the UCC28060 preset phase management thresholds can achieve maximum efficiency improvement. According to the COMP pin voltage, easy phase management shuts down phase B at correspondingpowerlevels.ThethresholdsandcorrespondingpowerlevelsarelistedinTable1. Table1.PHBManagementPerformancewithPHBConnectedtoCOMP PHBTHRESHOLDS PHBTHRESHOLDVOLTAGE PERCENTAGEOFFULLPOWER COMPVOLTAGEAT HIGHTOLOW LOWTOHIGH VAC FULLPOWER HIGHTOLOW LOWTOHIGH (PHASEBOFF) (PHASEBON) RMS 85 4.85V 0.8V 1.0V 14% 19% 115 2.7V 0.8V 1.0V 26% 34% 133 2.1V 0.8V 1.0V 35% 45% 187 3.1V 1.1V 1.3V 33% 40% 230 2.1V 1.1V 1.3V 50% 61% 265 1.6V 1.1V 1.3V 67% 81% The PHB pin can also be driven by an external logic signal to allow customized phase management. To disable phasemanagement,connectthePHBpintotheVREFpin. 18 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 Zero Crossing Detection and Valley Switching Intransition-modePFCcircuits,theMOSFETturnsonwhentheboostinductorcurrentcrosses0.Becauseofthe resonance between the boost inductor and the parasitic capacitor at the MOSFET drain node, part of the energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore, when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley switching). In this way, the energyrecoverycanbemaximizedandswitchinglossisminimized. The RC time constant is generally derived empirically, but a good starting point is a value equal to 25% of the resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 26. BecausetheZCDpinisinternallyclamped,amoreaccuratedelaycanalsoberealizedbyusingFigure27. R ZCD R1 ZCD CT C CT C R2 Figure26.SimpleRCDelayCircuit Figure27.MoreAccurateTimeDelayCircuit Brownout Protection As the power line RMS voltage decreases, RMS input current increases to maintain the output voltage constant for a specific load. Brownout protection prevents the RMS input current from exceeding a safe operating level. Power line RMS voltage is sensed at VINAC. When the voltage applied to VINAC fails to exceed the brownout threshold for the brownout filter time, a brownout condition is detected and both gate drive outputs immediately pulllow.Duringbrownout,COMPisactivelypulledlow.Gatedriveoutputsremainlowuntil the voltage on VINAC risesabovethebrownoutthreshold.Afterabrownout,thepowerstagesoft-startsasCOMPrises. The brownout detection threshold and its hysteresis are set by the voltage divider ratio and resistor values. This pin also detects the input line range to set the corresponding on-time factors. Both the brownout protection and line range detection are based on VINAC peak voltage; the threshold and hysteresis are also based on line peak voltage. The peak VINAC voltage can be easily translated into RMS value. Suggested resistor values for the voltage divider are 3 MΩ ±1% from the rectified input voltage to VINAC and 46.4 kΩ ±1% from VINAC to ground. TheseresistorssetthetypicalthresholdsforRMSlinevoltages,asshowninTable2. Table2.BrownoutandRangeChangeThresholds THRESHOLD BROWNOUT(RMS) MAINSSELECT(RMS) Falling 65V 150.9V Rising 79.8V 161.2V Failsafe OVP—Output Over-Voltage Protection FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input senses an over-voltage condition. The output voltage can still maintain a safe level with either loop failure. The device is re-enabled when both sense inputs fall back into the normal range. At that time, the gate drive outputs resume switching under PWM control. Output over-voltage does not cause soft-start and the COMP pin is not dischargedduringanoutputover-voltageevent. Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com Over-Current Protection Under certain conditions (such as inrush, brownout recovery, and output overload), the PFC power stage sees largecurrents.Itiscriticalthatthepowerdevicesbeprotectedfromswitchingduringtheseconditions. The conventional current sensing method uses a shunt resistor in series with the MOSFET source to sense the converter current, resulting in multiple ground points and high power dissipation. Furthermore, since no current information is available when the MOSFETs are off, the source resistor current sensing method requires repeated turn-ons of the MOSFETs during over-current conditions. As a result, the converter may temporarily operate in continuous current mode (CCM) and experience failures induced by excessive reverse recovery currentsintheboostdiode. TheUCC28060usesasingleresistortocontinuouslysensethetotalinductor(input)current.Thisway,turn-onof the MOSFETs is completely avoided when the inductor currents are excessive. The drive to the MOSFETs is inhibited until total inductor current drops to near zero, precluding reverse recovery induced failures (these failuresaremostlikelytooccurwhentheaclinerecoversfromabrownoutcondition). Following an over-current condition, both MOSFETs are turned on in phase when the input current drops to near 0. Because two phase currents are temporarily operating in phase, set the over-current protection threshold to more than twice of each phase maximum current ripple value in order to allow a return to normal operation after anover-currentevent. Phase Fail Protection The UCC28060 detects failure of one phase by monitoring the sequence of ZCD pulses. During normal two-phase operation, if one ZCD input remains idle for longer than approximately 14 ms while the other ZCD input switches normally, PWMCNTL goes high, indicating that the power stage is not operating correctly. During normalsingle-phaseoperation,phasefailureisnotmonitored. Distortion Reduction Because of the resonance between the capacitance present across the drain-source of the switching MOSFET and the boost inductor, conventional transition mode power factor correction circuits may not be able to absorb power from the input line when the input voltage is around 0 V. This limitation results in waveform distortion and increased harmonic distortion. To reduce line current distortion to the lowest possible level, the UCC28060 increases switching MOSFET on-time when input voltage is around 0 V to increase the power absorption and compensateforthiseffect. 20 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 Improved Error Amplifier The voltage error amplifier is a transconductance amplifier. Voltage loop compensation is connected from the error amplifier output, COMP, to analog ground, AGND. The recommended compensation network is shown in Figure28. REF COMP + VSENSE - C Z C P 4.95 V R Z Figure28.TypicalErrorAmplifierCompensation To improve the transient response, the error amplifier output current is increased by 100 m A when the error amp input is below 5.815 V, as shown in Figure 29. This increase allows faster charging of the compensation componentsfollowingsuddenloadcurrentincreases(alsorefertoFigure4intheTypicalCharacteristics). 160mA + OV PWM 6.45V Shutdown 5.75V + VSENSE 6V + g m COMP SoftStart R Q 0.5V + Brownout UV S Q EN OV (UCC28061) Figure29.ErrorAmplifierBlockDiagramShowingSpeed-UpandLatchedSoft-Start Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com Open-Loop Protection If the feedback loop is disconnected from the device, a current source internal to the UCC28060 pulls the VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device is disabled. When disabled, supply current decreases, and both gate drive outputs and COMP are actively pulled low. The device is re-enabled when VSENSE rises above 1.25 V. At that time, the gate drive outputs begin switching under PWM control. The device can be externally disabled by grounding the VSENSE pin with an open-drain or open-collector driver. When disabled, device supply current drops and COMP is actively pulled low. When VSENSE is released, the device soft-starts. This disable method forces the device into standby mode and minimizes its power consumption.Thisfeatureisparticularlyusefulwhenstandbypowerisakeydesignaspect. If the feedback loop is disconnected from ground, the VSENSE voltage goes high. When VSENSE rises above the over-voltage protection threshold, both gate drive outputs go low, and COMP is actively pulled low. The device is re-enabled when VSENSE falls back into range. At that time, the gate drive outputs begin switching under PWM control. The VSENSE pin is internally clamped to protect the device from damage under this condition. Soft-Start The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to AGND charges from a low level to the final value. This process implements a soft-start, with a time constant set by the output current of the error amplifier and the value of the compensation capacitors. In the event of a brownout, logic disable, or VCC undervoltage fault, COMP is actively pulled low so the PWM soft-starts after this event is cleared. Even if a fault event happens very briefly, soft-start fully discharges the compensation componentsbeforeresumingoperation,ensuringsoft-starting.SeeFigure29fordetails. Light-Load Operation As load current decreases, the error amplifier commands less input current by lowering the COMP voltage. If PHB (normally connected to COMP) falls below 0.8 V at low input line (or 1.1 V at high input line), channel B stops switching and channel A on-time doubles to compensate. If COMP falls below 150 mV, channel A also stopsswitchingandtheloopentersahystereticcontrolmode.ThePWMskipscyclestomaintainregulation. Command for the Downstream Converter In the UCC28060, the PWMCNTL pin is used to coordinate the PFC stage with a downstream converter. Through the HVSEN pin, the output voltage is sensed. When the output voltage is within the desired range, the PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. The enable threshold and hysteresis can be adjusted independently through the voltage divider ratio and resistor values. The HVSEN pin is also used for the FailSafe over-voltage protection. When designing the voltage divider, make sure thisFailSafeover-voltageprotectionlevelissetabovenormaloperatinglevels. VCC Undervoltage Protection VCC must rise above the undervoltage threshold for the PWM to begin functioning. If VCC drops below the threshold during operation, both gate drive outputs and COMP are actively pulled low. VCC must rise above the thresholdforPWMfunctiontorestart. VCC VCC is connected to a bias supply of between 13 V and 21 V. When powered from a poorly-regulated supply, an externalzenerdiodeisrecommendedtopreventexcessivecurrentintoVCC. 22 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 DESIGN EXAMPLE An example of the UCC28060 PFC controller in a two-phase transition mode interleaved PFC pre-regulator is showninFigure30. F1 Bridge - + D3 CIN 12 V 2C2 Fp4F L1 CA D1 VOUT R 2.2mF 1W RZA CS VCC ZCDA 20 kW R5GW1 Q1 CF1 GDA 1 nF CF5 22 pF UCC28060 RZB L2 COMP ZCDB PWMCNTL 20 kW RC RLOAD PHB D2 RZ RP TSET PWMCNTL 12 V VREF 50 kW RA RG2 COUT VINAC 5W Q2 GDB VSENSE RS CZ CP RT C2.B2mF RF CF4HVASGENND PGND C1.F22 nF RB C1.F23 nF RD 1.2 nF RE Figure30.TypicalTransitionModeInterleavedPFCPre-Regulator Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com Design Goals The specifications for this design were chosen based on the power requirements of a 300 W LCD TV. These specificationsareshowninTable3. Table3.DesignSpecifications PARAMETER MIN TYP MAX UNIT V RMSinputvoltage 85(V ) 265(V ) V IN IN_MIN IN_MAX RMS V Outputvoltage 390 V OUT f Linefrequency 47 63 Hz LINE PF Powerfactoratmaximumload 0.90 P 300 W OUT h Fullloadefficiency 0.92 f Minimumswitchingfrequency 45 kHz MIN Recommended PCB Device Layout Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current, allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input and output filter capacitors should be located after the two phase currents are combined together. Similar to other power management devices, when laying out the printed circuit board (PCB) it is important to use star grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in (25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath magnetic elements. Because of the precise timing requirement, the timing setting resistor R should be put as T close as possible to the TSET pin and returned to the analog ground. See Figure 31 for a recommended componentlayoutandplacement. 24 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 V OUT + - RG1 VCC S R A CB Z CA RP R 2 R G R 1 F U1 C B F2 R C RA B Z R CP RC RD CF3 RT CF4 RF RE CZ V OUT RZ V OUT Figure31.RecommendedPCBLayout Inductor Selection The boost inductor is selected based on the inductor ripple current requirements at the peak of low line. Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (D ), PEAK_LOW_LINE asshowninEquation9. V -V Ö2 390 V-85 VÖ2 OUT IN_MIN D = = »0.69 PEAK_LOW_LINE V 390 V OUT (9) The minimum switching frequency of the converter (f ) occurs at the peak of low line and is set between 25 MIN kHzand50kHztoavoidaudiblenoise.Forthisdesignexample,f wassetto45kHz: MIN h ´V 2x D 0.92(85 V)20.69 IN_MIN PEAK_LOW_LINE L1 = L2 = = »340mH P ´f 300 W´45 kHz OUT MIN (10) The inductor for this design would have a peak current (I ) of 5.4 A, as shown in Equation 11, and an RMS LPEAK current(I )of2.2A,asshowninEquation12. LRMS Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com P Ö2 300 WÖ2 I = OUT = »5.4 A LPEAK V ´ h 85 V´0.92 IN_MIN (11) I 5.4 A I = LPEAK = »2.2 A LRMS Ö6 Ö6 (12) This converter uses constant on-time (T ) and zero-current switching (ZCS) to set up the converter timing. ON Auxiliary windings off of L1 and L2 detect when the inductor currents are 0. Selecting the turns ratio in Equation 13 ensures that there is at least 2 V at the peak of high line to reset the ZCD comparator after every switchingcycle. Theturns-ratioofeachauxiliarywindingis: NP = VOUT-VIN_MAXÖ2 = 390 V-265 VÖ2 »8 N 2 V 2 V S (13) ZCD Resistor Selection (R , R ) ZA ZB The minimum value of the ZCD resistors is selected based on the internal zener clamp maximum current rating of3mA,asshowninEquation14. V N OUT S 390 V R = R ³ = »16.3 kW ZA ZB N ´3 mA 8´3 mA P (14) InthisdesigntheZCDresistorsweresetto20kΩ,asshowninEquation15. R = R = 20 kW ZA ZB (15) HVSENSE TheHVSENSEpinprogramsthePWMCNTL output of the UCC28060. The PWMCNTL open-drain output can be used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts in high impedance and pulls to ground when the HVSENSE increases above 2.5 V. Setting the point where PWMCNTL becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 16 to Equation 20 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominal value. V = V ´0.90»351 V OUT_OK OUT (16) Resistor R sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal. E Forthisexample,R wasselectedtoprovide108Vofhysteresis,asshowninEquation17. E Hysteresis 108 V R = = = 3 MW E 36mA 36mA (17) ResistorR isusedtoprogramthePWMCNTLactivethreshold,asshowninEquation18. F 2.5 V 2.5 V R = = = 31.185 kW»31.6 kW F V -2.5 V 351 V-2.5 V OUT_ORK -36mA 3 MW -36mA E (18) This PWMCNTRL output remains active until a minimum output voltage (V ) is reached, as shown in OUT_MIN Equation19. 2.5 V (R + R ) 2.5 V (3 MW+ 31.6 kW) V = E F = »240 V OUT_MIN R 31.6 kW F (19) Accordingtotheresistorvalue,theFailSafeOVPthresholdshouldbesetaccordingtoEquation20: 4.87 V (R + R ) 4.87 V (3 MW+ 31.6 kW) V = E F = »467 V OV_FAILSAFE R 31.6 kW F (20) 26 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 Output Capacitor Selection Theoutputcapacitor(C )isselectedbasedonholduprequirementsasshowninEquation21. OUT POUT 1 300 W 1 2 2 h f 0.92 47 Hz C ³ LINE = »147mF OUT V 2-(V )2 (390 V)2-(240 V)2 OUT OUT_MIN (21) Two100-m Fcapacitorswereusedinparallelfortheoutputcapacitor: C = 200mF OUT (22) Forthissizecapacitor,theoutputvoltageripple(V )isapproximately11V,asshowninEquation23: RIPPLE 2´P 1 2´300W V = OUT = »14V RIPPLE h V ´4p ´f ´C 0.92´390V ´4p ´47Hz´200mF OUT LINE OUT (23) In addition to hold-up requirements, a capacitor must be selected so that it can withstand the low-frequency RMS current (I ) and the high-frequency RMS current (I ); see Equation 24 to Equation 26. COUT_100 Hz COUT_HF High-voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current rating on the productdatasheets. P 300 W I = OUT = = 0.591 A COUT_100Hz V ´ h´Ö2 390 V´0.92´Ö2 OUT (24) 2 P 2Ö2 4Ö2V I = OUT IN_MIN -(I )2 COUT_HF 2´h´V 9pV COUT_100Hz IN_MIN OUT (25) 2 300 W´2Ö2 4Ö2´85 V I = -(0.591 A)2 »0.966 A COUT_HF 2´0.92´85 V 9p´390 V (26) Selecting an R for Peak Current Limiting S The UCC28060 peak limit comparator senses the total input current and is used to protect the MOSFETs during inrush and over-load conditions. For reliability, the peak current limit (I ) threshold in this design is set for PEAK 120%ofthenominalinrushcurrentthatisobservedduringpower-up,asshowninEquation27. 2P Ö2(1.2) 2´300 WÖ2´1.2 I = OUT = »13 A PEAK h´V 0.92´85 V IN_MIN (27) A standard 15-mΩ metal-film current-sense resistor is used for current sensing, as shown in Equation 28. The estimated power loss of the current sense resistor (P ) is less than 0.25 W during normal operation, as shown RS inEquation29. 200 mV 200 mV R = = »15 mW S I 13 A PEAK (28) P 2 300 W 2 P = OUT R = ´15 mW»0.22 W RS V ´h S 85 V´0.92 IN_MIN (29) Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere squared seconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was chosen to protect the design from a short-circuit condition. To ensure the current-sense resistors have a high enough surge protection, a 15-MΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-Wsurgeratingfor5seconds.Thisresulttranslates into 833 A2s and has a high enough I2t rating to survive a short-circuitbeforethefuseopens,asdescribedinEquation30. 2.5 W I2t = ´5 s =833 A2s 0.015W (30) Power Semiconductor Selection (Q1, Q2, D1, D2): The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note SLUU138, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-Regulator, explains how to selectpowersemiconductorcomponentsfortransition-modePFCpre-regulators. TheMOSFETmaximum-pulseddraincurrent(Q1,Q2)isshowninEquation31: I ³I = 13 A DM PEAK (31) TheMOSFETRMScurrentcalculation(Q1,Q2)isshowninEquation32: I = IPEAK 1 - 4Ö2VIN_MIN = 13 A 1 - 4Ö2´85 V »2.3 A DS 2 6 9p´V 2 6 9p´390 V OUT (32) To meet the power requirements of the design, IRFB11N50N 500-V MOSFETs from International Rectifier were chosenforQ1andQ2. TheboostdiodeRMScurrent(D1,D2)isshowninEquation33: I = IPEAK 4Ö2VIN_MIN = 13 A 4Ö2´85 V »1.4 A D 2 9p´V 2 9p´390 V OUT (33) To meet the power requirements of the design, MURS306T3 600-V diodes from On Semiconductor were chosen forthedesignforD1andD2. Brownout Protection Resistor R and R are selected to activate brownout protection at 75% of the specified minimum operated input A B voltage. Resistor R programs the brownout hysteresis comparator, which was selected to provide 21 V of A hysteresis.R andR areshowninEquation34andEquation35. A B In this design example, brownout becomes active when the input drops below 64 V and deactivates when the RMS inputreaches79V . RMS Hysteresis 21 V R = = »3 MW A 7mA 7mA (34) 1.4 V´R 1.4 V´3 MW R = A = »47 kW B V ´0.75Ö2-1.4 V 85 V´0.75Ö2-1.4 V IN_MIN (35) 28 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

UCC28060 www.ti.com.................................................................................................................................................... SLUS767E–MAY2007–REVISEDNOVEMBER2008 Converter Timing Select the timing resistor, R , for the correct on-time (T ) based on K , as shown in Equation 36. To ensure TSET ON TL proper operation, the timing must be set based on the highest boost inductance (L1 ). In this design example, MAX theboostinductorcouldbeashighas390m H,basedonlineandloadconditions,asshowninEquation37. V ´Ö2 h´(VIN_MIN)2 1- IN_VMIN 0.92´(85 V)2 1- 85 V´Ö2 OUT 390 V f = = = 39.2 kHz MIN P ´L1 300 W´390mH OUT MAX (36) V ´Ö2 133 kW 1- IN_VMIN 133 kW 1- 85 V´Ö2 OUT 390 V R = = »121 kW TSET 4.85 V´4ms´f 4.85 V´4ms´39.2 kHz MIN (37) Thisresultsetsthemaximumfrequencyclamp(f ), as shown in Equation 38, which improves efficiency at light MAX load. 133 kW 133 kW f = = »550 kHz MAX 2ms´R 2ms´121 kW T (38) Programming V OUT Resistor R is selected to minimize error because of VSENSE input bias current and minimize loading on the C power line when the PFC is disabled. Construct resistor R from two or more resistors in series to meet C high-voltage requirements. R was also selected to be of a similar value of R and R to simplify the bill of C A E materialsandreducedesigncosts. Based on the resistor values shown in Equation 39 to Equation 41, the primary output over-voltage protection thresholdshouldbeasshowninEquation42: R = 3 MW C (39) V = 6 V REF (40) V ´R 6 V´3 MW R = REF C = »47 kW D (V -V ) (390 V-6V) OUT REF (41) R + R 3 MW+ 47 kW V = 6.45 V C D = 6.45 V = 418 V OVP R 47 kW D (42) Loop Compensation Resistor R is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This Z valueensuresgoodpowerfactorandlowinputcurrentharmonicdistortion. ThetransconductanceamplifiergainisshowninEquation43: g = 96mS m (43) ThevoltagedividerfeedbackgainisshowninEquation44andEquation45: V 6 V H = REF = »0.015 V 390 V OUT (44) 100 mV 100 mV R = = = 6.313 kW»6.34 kW Z V ´H´g 11 V´0.015´96mS RIPPLE m (45) C isthensettoadd45°ofphasemarginat1/5thoftheswitchingfrequency,asshowninEquation46: Z Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):UCC28060

UCC28060 SLUS767E–MAY2007–REVISEDNOVEMBER2008.................................................................................................................................................... www.ti.com 1 1 C = = = 2.67mF Z f 47 Hz 2p´ LINE ´R 2p´ ´6.34 kW 5 Z 5 (46) C issizedtoattenuatehigh-frequencynoise,asshowninEquation47: P 1 1 C = = = 1.12 nF P f 45 kHz 2p´ MIN ´R 2p´ ´6.34 kW 2 Z 2 (47) ThestandardvaluesofEquation48andEquation49shouldbechosenforC andC . Z P C = 2.2mF Z (48) C = 1 nF P (49) ADDITIONAL REFERENCES Related Parts Table4listsseveralTIpartsthathavecharacteristicssimilartotheUCC28060. Table4.RelatedParts DEVICE DESCRIPTION UCC28051 PFCcontrollerforlowtomediumpowerapplications UCC28019 8-pincontinuousconductionmode(CCM)PFCcontroller References These references, design tools, and links to additional references, including design software, may be found at www.power.ti.com: • EvaluationModule,UCC28060EVM300WinterleavedPFCPre-regulator,SLUU280fromTexasInstruments • Application Note, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator, SLUU138fromTexasInstruments Package Outline and Recommended PCB Footprint The mechanical packages at the end of this data sheet outline the mechanical dimensions of the 16-pin D (SOIC)packageandproviderecommendationsforPCBlayout. 30 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCC28060

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) HPA00721DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28060 & no Sb/Br) UCC28060D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28060 & no Sb/Br) UCC28060DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28060 & no Sb/Br) UCC28060DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28060 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC28060DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC28060DR SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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