Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 UCC28019A 8-Pin Continuous Conduction Mode (CCM) PFC Controller 1 Features 3 Description • 8-PinSolutionReducesExternalComponents The UCC28019A 8-pin active Power Factor 1 Correction (PFC) controller uses the boost topology • Wide-RangeUniversalACInputVoltage operating in Continuous Conduction Mode (CCM). • Fixed65-kHzOperatingFrequency The controller is suitable for systems in the 100 W to • MaximumDutyCycleof98%(typ.) >2 kW range over a wide-range universal ac line input. Start-up current during undervoltage lockout is • OutputOver/UndervoltageProtection less than 200 μA. The user can control low power • InputBrown-OutProtection standby mode by pulling the VSENSE pin below • Cycle-by-CyclePeakCurrentLimiting 0.77V. • OpenLoopDetection Low-distortion wave shaping of the input current • Low-PowerUser-ControlledStandbyMode using average current mode control is achieved without input line sensing, reducing the external 2 Applications component count. Simple external networks allow for flexible compensation of the current and voltage • CCMBoostPowerFactorCorrectionPower control loops. The switching frequency is internally Convertersinthe100Wto>2kWRange fixed and trimmed to better than ±5% accuracy at • DigitalTV 25°C. Fast 1.5-A peak gate current drives the externalswitch. • HomeElectronics • WhiteGoodsandIndustrialElectronics Numerous system-level protection features include peak current limit, soft over-current, open-loop • ServerandDesktopPowerSupplies detection, input brown-out, and output over/undervoltage. Soft-start limits boost current during start-up. A trimmed internal reference provides accurate protection thresholds and a regulation set- point. An internal clamp limits the gate drive voltage to12.5V. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(8) 3.91mm×4.9mm UCC28019A PDIP(8) 6.35mm×9.81mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic EMIFilter VOUT LINE – Bridge + INPUT Rectifier 1 GND GATE 8 2 ICOMP VCC 7 ASuuxpilpalryy 3 ISENSE VSENSE 6 4 VINS VCOMP 5 Rload UCC28019A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 20 2 Applications........................................................... 1 8.1 ApplicationInformation............................................20 3 Description............................................................. 1 8.2 TypicalApplication .................................................21 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 40 5 PinConfigurationandFunctions......................... 3 9.1 BiasSupply.............................................................40 6 Specifications......................................................... 4 10 Layout................................................................... 41 6.1 AbsoluteMaximumRatings .....................................4 10.1 LayoutGuidelines.................................................41 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................42 6.3 RecommendedOperatingConditions.......................4 11 DeviceandDocumentationSupport................. 43 6.4 ThermalInformation..................................................4 11.1 DeviceSupport......................................................43 6.5 ElectricalCharacteristics...........................................5 11.2 DocumentationSupport........................................43 6.6 TypicalCharacteristics..............................................7 11.3 CommunityResources..........................................43 7 DetailedDescription............................................ 10 11.4 Trademarks...........................................................43 7.1 Overview.................................................................10 11.5 ElectrostaticDischargeCaution............................43 7.2 FunctionalBlockDiagram.......................................11 11.6 Glossary................................................................43 7.3 FeatureDescription.................................................12 12 Mechanical,Packaging,andOrderable Information........................................................... 44 7.4 DeviceFunctionalModes........................................19 4 Revision History ChangesfromRevisionC(August2015)toRevisionD Page • ChangedVCOMPandICOMPMAXvaluefrom7Vto7.5V................................................................................................ 4 • AddedVCOMPandICOMPnote. ......................................................................................................................................... 4 ChangesfromRevisionB(April2009)toRevisionC Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection. ................................................................................................ 1 2 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 5 Pin Configuration and Functions D,PPackage 8-PinSOIC,8-PinPDIP TopView 1 GND GATE 8 2 ICOMP VCC 7 3 ISENSE VSENSE 6 4 VINS VCOMP 5 PinFunctions PIN NO. I/O DESCRIPTION NAME SOIC, PDIP GND 1 — Ground:devicegroundreference. Currentloopcompensation:Transconductancecurrentamplifieroutput.Acapacitorconnectedto ICOMP 2 O GNDprovidescompensationandaveragingofthecurrentsensesignalinthecurrentcontrolloop. ThecontrollerisdisabledifthevoltageonICOMPislessthan0.6V. Inductorcurrentsense:Inputforthevoltageacrosstheexternalcurrentsenseresistor,which representstheinstantaneouscurrentthroughthePFCboostinductor.Thisvoltageisaveragedbythe currentamplifiertoeliminatetheeffectsofrippleandnoise.SoftOverCurrent(SOC)limitsthe ISENSE 3 I averageinductorcurrent.Cycle-by-cyclePeakCurrentLimit(PCL)immediatelyshutsofftheGATE driveifthepeak-limitvoltageisexceeded.Aninternal1.5-μAcurrentsourcepullsISENSEabove0.1 VtoshutdownPFCoperationifthispinbecomesopen-circuited.Usea220-Ωresistorbetweenthis pinandthecurrentsenseresistortolimitinrush-surgecurrentsintothispin. Inputacvoltagesense:Afilteredresistor-dividernetworkconnectsfromthispintotherectified-mains node.InputBrown-OutProtection(IBOP)detectswhenthesystemac-inputvoltageisaboveauser- definednormaloperatinglevel,orbelowauser-defined“brown-out”level.Atstartupthecontrolleris VINS 4 I disableduntiltheVINSvoltageexceedsathresholdof1.5V,initiatingasoftstart.Thecontrolleris alsodisabledifVINSdropsbelowthebrown-outthresholdof0.8V.Operationwillnotresumeuntil bothVINSandVSENSEvoltagesexceedtheirenablethresholds,initiatinganothersoftstart. Voltageloopcompensation:Transconductancevoltageerroramplifieroutput.Aresistor-capacitor networkconnectedfromthispintoGNDprovidescompensation.VCOMPisheldatGNDuntilVCC, VINS,andVSENSEallexceedtheirthresholdvoltages.Oncetheseconditionsaresatisfied,VCOMP VCOMP 5 O ischargeduntiltheVSENSEvoltagereaches99%ofitsnominalregulationlevel.WhenEnhanced DynamicResponse(EDR)isengaged,ahighertransconductanceisappliedtoVCOMPtoreducethe chargetimeforfastertransientresponse.SoftStartisprogrammedbythecapacitanceonthispin. TheEDRhighertransconductanceisinhibitedduringSoftStart. Outputvoltagesense:Anexternalresistor-dividernetworkconnectedfromthispintothePFCoutput voltageprovidesfeedbacksensingforregulationtotheinternal5-Vreferencevoltage.Asmall capacitorfromthispintoGNDfiltershigh-frequencynoise.Standbymodedisablesthecontrollerand dischargesVCOMPwhenthevoltageatVSENSEdropsbelowtheenablethresholdof0.8V.An VSENSE 6 I internal100-nAcurrentsourcepullsVSENSEtoGNDforOpen-LoopProtection(OLP),includingpin disconnection.OutputOver-VoltageProtection(OVP)disablestheGATEoutputwhenVSENSE exceeds105%ofthereferencevoltage.EnhancedDynamicResponse(EDR)rapidlyreturnsthe outputvoltagetoitsnormalregulationlevelwhenasystemlineorloadstepcausesVSENSEtofall below95%ofthereferencevoltage. Devicesupply:Externalbiassupplyinput.Under-VoltageLockout(UVLO)disablesthecontrolleruntil VCCexceedsaturn-onthresholdof10.5V.OperationcontinuesuntilVCCfallsbelowtheturn-off VCC 7 (UVLO)thresholdof9.5V.Aceramicby-passcapacitorof0.1μFminimumvalueshouldbe connectedfromVCCtoGNDasclosetothedeviceaspossibleforhighfrequencyfilteringofthe VCCvoltage. Gatedrive:Integratedpush-pullgatedriverforoneormoreexternalpowerMOSFETs.Typical2.0-A GATE 8 O sinkand1.5-Asourcecapability.Outputvoltageistypicallyclampedat12.5V. Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) Overoperatingfree-airtemperaturerangeunlessotherwisenoted.Unlessnoted,allvoltagesarewithrespecttoGND. Currentsarepositiveintoandnegativeoutofthespecifiedterminal. MIN MAX UNIT VCC,GATE –0.3 22 V VINS,VSENSE, –0.3 7 V Inputvoltagerange VCOMP,ICOMP(2) –0.3 7.5 V ISENSE –24 7 V Inputcurrentrange VSENSE,ISENSE –1 1 mA Leadtemperature,T Soldering,10s 300 °C SOL Operating –55 150 °C Junctiontemperature,T J Storage –65 150 °C (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionbeyondthoseincludedunder“recommendedoperating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsoftimemayaffectdevicereliability. (2) TheVCOMPandICOMPpincangoto7.5V±6%duetointernaldrivecircuitry.Absolutemaximumratingis7Vwhenanexternalbias isappliedtothepin,withthesourcecurrentlimitedbelow50µA. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- C101(2) ±500 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VCCinputvoltagefromalow-impedancesource VCC +1V 21 V OFF Operatingjunctiontemperature,T -40 125 °C J 6.4 Thermal Information UCC28019A THERMALMETRIC(1) P(PDIP) D(SOIC) UNIT 8PINS 8PINS R Junction-to-ambientthermalresistance 52.8 113.0 °C/W θJA R Junction-to-case(top)thermalresistance 42.3 61.5 °C/W θJC(top) R Junction-to-boardthermalresistance 30.0 53.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 19.5 15.9 °C/W JT ψ Junction-to-boardcharacterizationparameter 29.9 52.7 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 4 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 6.5 Electrical Characteristics Unlessotherwisenoted,VCC=15V ,0.1μFfromVCCtoGND,-40°C≤T =T ≤125°C.Allvoltagesarewithrespectto DC J A GND.Currentsarepositiveintoandnegativeoutofthespecifiedterminal. PARAMETER TESTCONDITION MIN TYP MAX UNIT VCCBiasSupply ICC ICCpre-startcurrent VCC=VCC –0.1V 25 100 200 μA PRESTART ON ICC ICCstandbycurrent VSENSE=0.5V 1 2.2 2.9 mA STBY ICC ICCoperatingcurrent VSENSE=4.5V,C =4.7nF 4 7.5 10 mA ON_load GATE UnderVoltageLockout(UVLO) VCC VCCturnonthreshold 10 10.5 11 V ON VCC VCCturnoffthreshold 9 9.5 10 V OFF UVLOhysteresis 0.8 1 1.2 V Oscillator T =25°C 61.7 65 68.3 kHz A f Switchingfrequency -25°C≤T ≤125°C 59 65 71 kHz SW A -40°C≤T ≤125°C 57 71 kHz A PWM VCOMP=0V,VSENSE=5V, D Minimumdutycycle 0% MIN ICOMP=6.4V D Maximumdutycycle VSENSE=4.95V 94% 98% 99.3% MAX t Minimumofftime VSENSE=3V,ICOMP=1V 100 250 600 ns OFF(min) SystemProtection ISENSEthreshold,SoftOverCurrent V -0.66 -0.73 -0.79 V SOC (SOC) ISENSEthreshold,PeakCurrentLimit V -1 -1.08 -1.15 V PCL (PCL) ISENSEbiascurrent,ISENSEOpen-Pin I ISENSE=0V -2.1 -4.0 μA ISOP Protection(ISOP) ISENSEthreshold,ISENSEOpen-Pin V ISENSE=openpin 0.082 V ISOP Protection(ISOP) VSENSEthreshold,OpenLoop ICOMP=1V,ISENSE=-0.1V, V 0.77 0.82 0.86 V OLP Protection(OLP) VCOMP=1V OpenLoopProtection(OLP)Internal VSENSE=0.5V 100 250 nA pull-downcurrent VSENSEthreshold,outputUnder- VUVD VoltageDetection(UVD)(1) 4.63 4.75 4.87 V VSENSEthreshold,outputOver-Voltage V ISENSE=-0.1V 5.12 5.25 5.38 V OVP Protection(OVP) V InputBrown-OutDetection(IBOP) INSBROWNOUT 0.76 0.82 0.88 V high-to-lowthreshold _th InputBrown-OutDetection(IBOP) V 1.4 1.5 1.6 V INSENABLE_th low-to-highthreshold I VINSbiascurrent VINS=0V 0 ±0.1 μA VINS_0V ICOMPthreshold,externaloverload 0.6 V protection (1) Notproductiontested.Characterizedbydesign. Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Electrical Characteristics (continued) Unlessotherwisenoted,VCC=15V ,0.1μFfromVCCtoGND,-40°C≤T =T ≤125°C.Allvoltagesarewithrespectto DC J A GND.Currentsarepositiveintoandnegativeoutofthespecifiedterminal. PARAMETER TESTCONDITION MIN TYP MAX UNIT CurrentLoop g Transconductancegain T =25°C 0.75 0.95 1.15 mS mi A Outputlinearrange(1) ±50 μA ICOMPvoltageduringOLP VSENSE=0.5V 3.7 4 4.3 V VoltageLoop V Referencevoltage -40°C≤T ≤125°C 4.9 5 5.1 V REF A g TransconductancegainwithoutEDR -31.5 -42 -52.5 μS mv g TransconductancegainunderEDR VSENSE=4.65V -440 μS mv-EDR Maximumsinkcurrentundernormal VSENSE=6V,VCOMP=4V 21 30 38 μA operation Sourcecurrentundersoftstart VSENSE=4V,VCOMP=2.5V -21 -30 -38 μA MaximumsourcecurrentunderEDR VSENSE=4V,VCOMP=2.5V -300 μA operation VSENSE=4V,VCOMP=4V -170 μA EnhanceddynamicresponseVSENSE lowthreshold,falling(1) 4.63 4.75 4.87 V VSENSEinputbiascurrent VSENSE=5V 20 100 250 nA VCOMPvoltageduringOLP VSENSE=0.5V,I =0.5mA 0 0.2 0.4 V VCOMP VCOMPrapiddischargecurrent VCOMP=3V,VCC=0V 0.77 mA V VCOMPprechargevoltage I =-100μA,VSENSE=5V 1.76 V PRECHARGE VCOMP I VCOMPprechargecurrent VCOMP=1.0V -1 mA PRECHARGE VSENSEthreshold,endofsoftstart Initialstartup 4.95 V GATEDriver GATEcurrent,peak,sinking(1) C =4.7nF 2 A GATE GATEcurrent,peak,sourcing(1) C =4.7nF -1.5 A GATE GATErisetime C =4.7nF,GATE=2Vto8V 8 40 60 ns GATE GATEfalltime C =4.7nF,GATE=8Vto2V 8 25 40 ns GATE GATElowvoltage,noload I =0A 0 0.05 V GATE GATElowvoltage,sinking I =20mA 0.3 0.8 V GATE GATElowvoltage,sourcing I =-20mA -0.3 -0.8 V GATE VCC=5V,I =5mA 0.2 0.75 1.2 V GATE GATElowvoltage,sinking,deviceOFF VCC=5V,I =20mA 0.2 0.9 1.5 V GATE VCC=20V,C =4.7nF 11.0 12.5 14.0 V GATE VCC=11V,C =4.7nF 9.5 10.5 11.0 V GATEhighvoltage GATE VCC=VCC +0.2V,C = OFF GATE 8.0 9.4 10.2 V 4.7nF 6 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 6.6 Typical Characteristics Unlessotherwisenoted,VCC=15V ,0.1μFfromVCCtoGND,-40°C≤T =T ≤125°C.Allvoltagesarewithrespectto DC J A GND.Currentsarepositiveintoandnegativeoutofthespecifiedterminal. 12.0 4.0 T =25°C J 3.5 VSENSE=VINS=3V NoGateLoad V - d 11.0 VCCTurnON 3.0 ol A h m s hre nt- 2.5 T e UVLO 10.0 yCurr 2.0 ICCTurnOFF ICCTurnON V/V-CC(on)CC(off) 9.0 VCCTurnOFF I-SupplCC 11..50 0.5 8.0 0 -60 -35 -10 15 40 65 90 115 140 0 5 10 15 20 T -Temperature-°C VCC-BiasSupplyVoltage-V J Figure1.UVLOThrasholdsvsTemperature Figure2.SupplyCurrentvsBiasSupplyVoltage 10 0.5 9 VCC=15V 8 0.4 VCC=UVLO-0.1V A mA 7 Operating,GATELoad=4.7nF -m - nt urrent 6 Curre 0.3 C 5 y upply 4 Suppl 0.2 Pre-Start S - I-CC 23 Standby ICC(start) 0.1 1 0 0 -60 -35 -10 15 40 65 90 115 140 -60 -35 -10 15 40 65 90 115 140 T -Temperature-°C T -Temperature-°C J J Figure3.SupplyCurrentvsTemperature Figure4.SupplyCurrentvsTemperature 75 75 73 VCC=15V 73 T =25°C J Hz 71 Hz 71 k k - 69 - 69 y y c c n n ue 67 SwitchingFrequency ue 67 SwitchingFrequency q q e e Fr 65 Fr 65 g g n n hi 63 hi 63 c c wit wit S 61 S 61 - - W W fS 59 fS 59 57 57 55 55 -60 -35 -10 15 40 65 90 115 140 10 12 14 16 18 20 T -Temperature-°C VCC-BiasSupplyVoltage-V J Figure5.OscillatorFrequencyvsTemperature Figure6.OscillatorFrequencyvsBiasSupplyVoltage Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Typical Characteristics (continued) Unlessotherwisenoted,VCC=15V ,0.1μFfromVCCtoGND,-40°C≤T =T ≤125°C.Allvoltagesarewithrespectto DC J A GND.Currentsarepositiveintoandnegativeoutofthespecifiedterminal. 2.0 50 1.8 VCC=15V 48 VCC=15V 1.6 46 1.4 44 Gain,NoEDR V V A/ 1.2 Gain A/ 42 m µ Gain- 1.0 Gain- 40 mi- 0.8 mv- 38 g g 0.6 36 0.4 34 0.2 32 0 30 -60 -35 -10 15 40 65 90 115 140 -60 -35 -10 15 40 65 90 115 140 T -Temperature-°C T -Temperature-°C J J Figure7.CurrentAveragingAmplifierTransconductancevs Figure8.VoltageErrorAmplifierTransconductancevs Temperature Temperature 5.50 0 VCC=15V -0.1 VCC=15V -0.2 V 5.25 V nceVoltage- 5.00 ReferenceVoltage EThreshold- ---000...435 e S Refer ISEN -0.6 SoftOver-CurrentProtection(SOC) V-REF 4.75 V-SOC -0.7 -0.8 -0.9 4.50 -1.0 -60 -35 -10 15 40 65 90 115 140 -60 -35 -10 15 40 65 90 115 140 TJ-Temperature-°C TJ-Temperature-°C Figure9.ReferenceVoltagevsTemperature Figure10.ISENSEThresholdvsTemperature 5.50 2.0 VCC=15V 1.8 VCC=15V V 1.6 d- 5.25 V NSEThreshol 5.00 Over-VoltageProtection(VOVP) EThreshold- 111...042 OpenLoopProtection SE NS V/V-VOVPUVD 4.75 Under-VoltageProtection(V ) V–VSEOLP 000...648 UVD 0.2 4.50 0 -60 -35 -10 15 40 65 90 115 140 -60 -35 -10 15 40 65 90 115 140 T -Temperature-°C T -Temperature-°C J J Figure11.VSENSEThresholdvsTemperature Figure12.VSENSEThresholdvsTemperature 8 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 Typical Characteristics (continued) Unlessotherwisenoted,VCC=15V ,0.1μFfromVCCtoGND,-40°C≤T =T ≤125°C.Allvoltagesarewithrespectto DC J A GND.Currentsarepositiveintoandnegativeoutofthespecifiedterminal. 2.0 600 V old- 1.8 VCC=15V 550 VISCEONMSPE==13VV h s hre 1.6 500 T NS 1.4 VINSEnable(VINSENABLE_TH) 450 VI – 1.2 s 400 WNOUT_TH 1.0 Time-n 350 SBROU 0.8 t- 300 tOFF(min) N 0.6 InputBrown-OutProtection(VINS ) 250 VI BROWNOUT_TH S/ENABLE_TH 00..24 210005 N 0 100 VI -60 -35 -10 15 40 65 90 115 140 -60 -35 -10 15 40 65 90 115 140 T -Temperature-°C T -Temperature-°C J J Figure13.VINSThresholdvsTemperature Figure14.MinimumOffTimevsTemperature 50 50 T =25°C, 45 VCC=15V 45 C J =4.7nF 40 CVGGAATTEE==42.V7-8nVF 40 VGGAATTEE=2V-8V 35 35 s 30 s 30 n n - - RiseTime me 25 FallTime me 25 Ti Ti t- 20 t- 20 FallTime 15 RiseTime 15 10 10 5 5 0 0 -60 -35 -10 15 40 65 90 115 140 10 12 14 16 18 20 T -Temperature-°C VCC-BiasSupplyVoltage-V J Figure15.GateDriveSwitchingvsTemperature Figure16.GateDriveSwitchingvsBiasSupplyVoltage 2.0 VCC=5V 1.8 I =20mA CC 1.6 V e- 1.4 g a Volt 1.2 VGATE w o 1.0 L e Gat 0.8 – GATE 0.6 V 0.4 0.2 0 -60 -35 -10 15 40 65 90 115 140 T -Temperature-°C J Figure17.GateLowVoltageWithDeviceOffvsTemperature Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 7 Detailed Description 7.1 Overview The UCC28019A is a switch-mode controller used in boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate as an active PFC pre-regulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz, ensuring that both the fundamental and second harmonic components of the conducted-EMI noise spectrum are belowtheEN55022conducted-band150kHzmeasurementlimit. Its tightly-trimmed internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide85-265VACmainsinputrangefromzerotofulloutputload. Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the sinusoidal input voltage under continuous inductor current conditions. Under light load conditions, depending on the boost inductor value, the inductor current may go discontinuous but still meet Class-D requirements of EN61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by generating a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gainparametersformaintainingalow-distortionsteady-stateinputcurrentwave-shape. 10 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 7.2 Functional Block Diagram EMIFilter L D BST BST INLIPNUET –RBercidtigfieer+ VOUT CIN RVINS1 QBST RGATE RFB1 C R OUT LOAD R RVINS2 10k RFB2 SENSE 0.6V + ICOMPProtection ISOP UCC28019ABlockDiagram ICOMP 2 FAULT ACmuprrleifnietr + CoKmPPWpCa(Msra)tor GateDriver VCC CICOMP gmi S Q + 4V IBOP Fault GMA1,INK1 PRMWA2MMP MinOffTRimeQ UOVLLPO LFoaguilct 8 GATE 65kHz Oscillator PCL S Q OVP Clock R Q Pre-Driveand Auxiliary M2 ClampCircuit Supply M1 VCOMP RISENSEfilter SOC UVLO + 7 VCC VCC ISENSE 40k 40k PeakCurrentLimit(PCL) Q S 10.5VON CVCC 3 CISENSEfilter 1.V0P8CVL LeaBd3lai0nn0gkniEnsgdge UVLO Q R + V9C.5CVOFF 1 GND + + ISENSEOpen-pinProtection -1x SoftOverCurrent(SOC) OVP + O5.V25EVRVOLTAGE + UNDERVOLTAGE V 0.73V SOC 4.75V ISOP SOC EDR + + OLP/STANDBY 0.82V InputBrown-OutProtection OLP/STANDBY VINS 20k (IBOP) 100nA 4 + VoltageError CVINS 5V VINENABLE_th1.5V SR QQ IBOP Amplifiergm+v 5V 6 VSENSE VINBROWNOUT_th0.82V + gmvEnhancement + CVSENSE ENDOF ENDOFSS SOFT-START 4.95V VCOMP 5 RapidDischarge R UVLO when SS EDR CV VCC<VCCOFF Q S ENDOFSS FAULT CCV2 VPRECHARGE FAULT Q R FAULT CCV1 Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 7.3 Feature Description 7.3.1 Soft-Start Soft Start controls the rate of rise of VCOMP in order to obtain a linear control of the increasing duty cycle as a function of time. VCOMP, the output of the voltage loop transconductance amplifier, is pulled low during UVLO, IBOP, and OLP (Open-Loop Protection)/STANDBY. Once the fault condition is released, an initial pre-charge source rapidly charges VCOMP to about 1.9 V. After that point, a constant 30 μA of current is sourced into the compensation components causing the voltage on this pin to ramp linearly until the output voltage reaches 85% of its final value. At this point, the sourcing current decreases until the output voltage reaches 99% of its final rated voltage. The Soft-Start time is controlled by the voltage error amplifier compensation capacitor values selected, and is user programmable based on desired loop crossover frequency. Once the output voltage exceeds99%ofratedvoltage,thepre-chargesourceisdiscountinuedandEDRisnolongerinhibited. Soft-Start + 5V VCOMP gmv VSENSE FAULT VCOMP I =-30uA SS forVSENSE<4.25V duringSoft-Start FAULT ENDOFSS (LATCHED) V PRECHARGE sourcefor + rapidpre-charge ofVCOMPprior toSoft-Start Figure18. SoftStart 12 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 Feature Description (continued) 7.3.2 SystemProtection System-levelprotectionfeatureshelpkeeptheconverterwithinsafeoperatinglimits. 7.3.2.1 VCCUndervoltageLockout(UVLO) During startup, Under-Voltage Lockout (UVLO) keeps the device in the off state until VCC rises above the 10.5-V enable threshold, VCC . With a typical 1 V of hysteresis on UVLO to increase noise immunity, the device turns ON offwhenVCCdropstothe9.5-Vdisablethreshold,VCC . OFF UVLO VCC AuxilarySupply + S Q VCC 10.5V ON C UVLO DECOUPLE GND R Q VCC 9.5V + OFF Figure19. UVLO If, during a brief ac-line dropout, the VCC voltage falls below the level necessary to bias the internal FAULT circuitry, the UVLO condition enables a special rapid discharge circuit which continues to discharge the VCOMP capacitors through a low impedance despite a complete lack of VCC. This helps to avoid an excessive current surge should the ac-line return while there is still substantial voltage stored on the VCOMP capacitors. Typically, thesecapacitorscanbedischargedtolessthan1.2Vwithin150msoflossofVCC. 7.3.2.2 InputBrown-OutProtection(IBOP) The sensed line-voltage input, VINS, provides a means for the designer to set the desired mains RMS voltage level at which the PFC pre-regulator should start-up, V , as well as the desired mains RMS level at which it ACturnon should shut down, V . This prevents unwanted sustained system operation at or below a brown-out ACturnoff voltage, where excessive line current could overheat components. In addition, because VCC bias is not derived directly from the line voltage, IBOP protects the circuit from low line conditions that may not trigger the VCC UVLOturn-off. InputBrown-OutProtection (IBOP) RVINS1 VINS 20k RectifiedACLine + S Q R C VINENABLE_th1.5V CIN VINS2 VINS IBOP 5V R Q VIN 0.8V + BROWNOUT_th Figure20. InputBrown-OutProtection Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Feature Description (continued) Input line voltage is sensed directly from the rectified ac mains voltage through a resistor-divider filter network providing a scaled and filtered value at the VINS input. IBOP will put the device into standby mode when VINS falls (high to low) below 0.8 V, VINS . The device comes out of standby when VINS rises (low to high) BROWNOUT_th above 1.5 V, VINS . Bias current sourced from VINS, I , is less than 0.1 μA. With a bias current this ENABLE_th VINS_0V low, there is little concern for any set-point error caused by this current flowing through the sensing network. The highest praticable value resistance for this network should be chosen to minimize power dissipation, especially in applications requiring low standby power. Be aware that higher resistance values are more susceptible to noise pickup, but low-noise PCB layout techniques can help mitigate this. Also, depending on the resistor type used anditsvoltagerating,R shouldbeimplementedwithmultipleresistorsinseriestoreducevoltagestresses. VINS1 First,selectR basedonchoosingthehighestreasonableresistancevalueavailablefortypicalapplications. VINS1 ThenselectR basedonthisvalue: VINS2 VINS R = R ENABLE_th VINS2 VINS1 2V -VINS ACturnon ENABLE_th (1) Powerdissipatedintheresistornetworkis: V 2 P = IN(RMS) VINS R +R VINS1 VINS2 (2) The filter capacitor, C , has two functions. First, to attenuate the voltage ripple to levels between the enable VINS and brown-out threshold to prevent ripple on VINS from falsely triggering IBOP when the converter is operating at low line. Second, C delays the brown-out protection operation for a desired number of line-half-cycle VINS periodswhilestillhavingagoodresponsetoanactualbrown-outevent. The capacitor is chosen so that it will discharge to the VINS level after a delay of N number of line ½- BROWNOUT_th cyclestoaccommodateac-linedropoutride-throughrequirements. -t C = dischrg VINS æ ö ç ÷ VINS R lnç BROWNOUT_th ÷ VINS2 ç R ÷ 0.9V VINS2 ç ÷ è ACmin R +R ø VINS1 VINS2 (3) Where, 1 t = N dischrg 2f LINE (4) andV isthelowestnormaloperatingrmsinputvoltage. ACmin 14 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 Feature Description (continued) 7.3.2.3 OutputOvervoltageProtection(OVP) V is the output voltage exceeding 5% of the rated value, causing VSENSE to exceed a 5.25-V threshold OUT(OVP) (5-V reference voltage + 5%), V . The normal control loop is bypassed and the GATE output is disabled until OVP VSENSEfallsbelow5.25V.V is420Vinasystemwitha400-Vratedoutput,forexample. OUT(OVP) 7.3.2.4 OpenLoopProtection/Standby(OLP/Standby) If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16% of its rated voltage, causingVSENSEtofallbelow0.8V,thedeviceisputinstandby,astatewherethePWMswitchingishaltedand the device is still on but draws standby current below 2.9 mA. This shutdown feature also gives the designer the optionofpullingVSENSElowwithanexternalswitch. 7.3.2.5 ISENSEOpen-PinProtection(ISOP) If the current feedback components were to fail and disconnect (open loop) the signal to the ISENSE input, then it is likely that the PWM stage would increase the GATE output to maximum duty cycle. To prevent this, an internal pull-up source drives ISENSE above 0.1 V so that a detector forces a state where the PWM switching is halted and the device is still on but draws standby current below 2.9 mA. This shutdown feature avoids continual operationinOVPandseverelydistortedinputcurrent. 7.3.2.6 OutputUndervoltageDetection(UVD)andEnhancedDynamicResponse(EDR) During normal operation, small perturbations on the PFC output voltage rarely exceed 5% deviation and the normal voltage control loop gain drives the output back into regulation. For large changes in line or load, if the output voltage drop exceeds -5%, an output under-voltage is detected (UVD) and Enhanced Dynamic Response (EDR) acts to speed up the slow response of the low-bandwidth voltage loop. During EDR, the transconductance of the voltage error amplifier is increased approximately 16 times to speed charging of the voltage-loop compensation capacitors to the level required for regulation. EDR is removed when VSENSE > 4.75 V. The EDR featureisnotactivateduntilsoftstartiscompleted. OverandUnderVoltageProtection OpenLoopProtection /Standby OutputVoltage Soft-StartComplete R + OVP FB1 Standby OVERVOLTAGE 5.25V VSENSE R UNDERVOLTAGE 4.75V + UVD FB2 Optional SOFT-STARTCOMPLETE 4.95V ENDOFSS + OPENLOOP PROTECTION/STANDBY 0.82V + OLP/STANDBY Figure21. OVP,UVD,OLP/Standby,SoftStartComplete Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Feature Description (continued) OVP105%V REF 100%V REF Feedback EDR 95%V REF Voltage OLP/SS 16%V REF Protection Soft-Start OVP UVD State OLP (NoEDR Run Run OLP (NoGateOutput) (EDRon) to99%V ) REF Figure22. SoftStartandProtectionStates 7.3.2.7 Over-CurrentProtection Inductor current is sensed by R , a low value resistor in the return path of input rectifier. The other side of ISENSE the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is always negative. The voltage at ISENSE is buffered by a fixed gain of -1.0 to provide a positive internal signal to the current functions. There are two over-current protection features; Soft Over-Current (SOC) protects against anoverloadontheoutputandPeakCurrentLimit(PCL)protectsagainstinductorsaturation. SoftOverCurrent (SOC) VSOC ISENSEOpen-Pin 0.73V SOC Protection (ISOP) + LINE – + INPUT I V ISOP OUT 1.5µA VISOP 0.1V ISOP R ISENSE + ISENSE RISENSEfilter CISENSEfilter VPCL 300ns (Optional) 1.08V LeadingEdge PCL Blanking + + -1x PeakCurrentLimit(PCL) Figure23. SoftOverCurrent/PeakCurrentLimit 7.3.2.8 SoftOverCurrent(SOC) Soft Over-Current (SOC) limits the input current. SOC is activated when the current sense voltage on ISENSE reaches -0.73 V, affecting the internal VCOMP level, and the control loop is adjusted to reduce the PWM duty cycle. 16 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 Feature Description (continued) 7.3.2.9 PeakCurrentLimit(PCL) Peak Current Limit (PCL) operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE reaches -1.08 V, PCL is activated, immediately terminating the active switch cycle. PCL is leading-edge blanked toimprovenoiseimmunityagainstfalsetriggering. 7.3.2.10 CurrentSenseResistor,R ISENSE The current sense resistor, R , is sized using the minimum threshold value of Soft Over Current (SOC), ISENSE V =0.66V.Toavoidtriggeringthisthresholdduringnormaloperation,resultinginadecreasedduty-cycle, SOC(min) theresistorissizedforanoverloadcurrentof10%morethanthepeakinductorcurrent, V R £ SOC(min) ISENSE 1.1I L_PEAK(max) (5) Since R sees the average input current, worst-case power dissipation occurs at input low-line when input ISENSE currentisatitsmaximum.Powerdissipatedbythesenseresistorisgivenby: P =(I )2R RISENSE IN_RMS(max) ISENSE (6) Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor reachesthePCLthreshold,V .Theabsolutemaximumpeakcurrent,I ,isgivenby: PCL PCL V I = PCL PCL R ISENSE (7) 7.3.3 GateDriver The GATE output is designed with a current-optimized structure to directly drive large values of total MOSFET gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the MOSFET gate to 12.5 V (typical). When VCC voltage is below the UVLO level, the GATE output is held in the Off state. An external gate drive resistor, R , can be used to limit the rise and fall times and dampen ringing caused by GATE parasitic inductances and capacitances of the gate drive circuit and to reduce EMI. The final value of the resistor depends upon the parasitic elements associated with the layout and other considerations. A 10-kΩ resistor close to the gate of the MOSFET, between the gate and ground, discharges stray gate capacitance and helps protect againstinadvertentdv/dt-triggeredturn-on. VCC GateDriver Rectified UVLO Fault FAULT From VCC AC LBOOST DBOOST VOUT OLP PWM Logic Latch Q IBOP BOOST GATE C OUT R GATE PCL S Q 10k OVP GND CLOCK R Q Pre-Driveand ClampCircuit Figure24. GateDriver Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Feature Description (continued) 7.3.4 CurrentLoop The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator (PWM)stage,theexternalboostinductorstageandtheexternalcurrentsensingresistor. 7.3.5 ISENSEandICOMPFunctions The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. The internal positive signal is then averaged by the current amplifier (g ), whose output is the ICOMP pin. The mi voltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to the ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is determined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide ac-line voltagerange. ICOMPisconnectedto4VinternallywheneverthedeviceisinaFaultorStandbycondition. 7.3.6 PulseWidthModulator The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated output signal which is High whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined byanon-linearfunctionoftheinternalVCOMPvoltage. PWM cycle V ICOMP V = RAMP F(V ) VCOMP t t PWM OFF ON t Figure25. PWMGeneration The PWM output signal always starts Low at the beginning of the cycle, triggered by the internal clock. The output stays Low for a minimum off-time, t , after which the ramp rises linearly to intersect the ICOMP OFF_min voltage. The ramp-ICOMP intersection determines t , and hence D . Since D = V /V by the boost- OFF OFF OFF IN OUT topology equation, and since VIN is sinusoidal in wave-shape, and since ICOMP is proportional to the inductor current, it follows that the control loop forces the inductor current to follow the input voltage wave-shape to maintainboostregulation.Therefore,theaverageinputcurrentisalsosinusoidalinwave-shape. 7.3.7 ControlLogic The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various protection functions incorporated into the device. The GATE output duty-cycle may be as high as 99%, but will always have a minimum off-time t . Normal duty-cycle operation can be interrupted directly by OVP and OFF_min PCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the GATE output pulse, and furtherinhibitoutputuntiltheSSoperationcanbegin. 7.3.8 VoltageLoop The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing stage,thevoltageerroramplifierstage,andthenon-lineargaingeneration. 18 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 Feature Description (continued) 7.3.9 OutputSensing A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference voltage. Like the VINS input, the very low bias current at the VSENSE input allows the choice of the highest practicable resistor values for lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves tofilterthesignalinahigh-noiseenvironment.Thisfiltertimeconstantshouldgenerallybelessthan100 μs. 7.3.10 VoltageErrorAmplifier Thetransconductanceerroramplifier(g )generatesanoutputcurrentproportionaltothedifferencebetweenthe mv voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges or discharges the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage for the system operating conditions. Proper selection of the compensation network components leads to a stable PFC pre- regulatorovertheentireac-linerangeand0-100%loadrange.Thetotalcapacitancealsodeterminestherate-of- riseoftheVCOMPvoltageatsoftstart,asdiscussedearlier. The amplifier output VCOMP is pulled to GND during any Fault or Standby condition to discharge the compensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delays complete discharge for their respective time constant (which may be several hundred milliseconds). If VCC bias voltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the large capacitor could be left with substantial voltage on it, negating the benefit of a subsequent soft start. The UCC28019A incorporates a parallel discharge path which operates without VCC bias, to further discharge the compensationnetworkafterVCCisremoved. When output voltage perturbations greater than ±5% appear at the VSENSE input, the amplifier moves out of linear operation. On an over-voltage, the OVP function acts directly to shut off the GATE output until VSENSE returns within ±5% of regulation. On an under-voltage, the UVD function invokes EDR which immediately increases the voltage error amplifier transconductance to about 440 μS. This higher gain facilitates faster chargingofthecompensationcapacitorstothenewoperatinglevel. 7.3.11 Non-LinearGainGeneration The voltage at VCOMP is used to set the current amplifier gain and the PWM ramp slope. This voltage is bufferedinternallyandisthensubjecttomodificationbytheSOCfunction,asdiscussedearlier. Together the current gain and the PWM slope adjust to the different system operating conditions (set by the ac- line voltage and output load level) as VCOMP changes, to provide a low-distortion, high-power-factor input currentwave-shapefollowingthatoftheinputvoltage. 7.4 Device Functional Modes Thisdevicehasnofunctionalmodes. Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The UCC28019A is a switch-mode controller used in boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate asanactivePFCpre-regulator.Theoperatingswitchingfrequencyisfixedat65kHz. The internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85- V to 265-V mains input range from zero to full output load. The usable system load ranges from 100 W to AC AC fewkW. Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the sinusoidal input voltage under continuous inductor current conditions. Under light-load conditions, depending on the boost inductor value, the inductor current may go discontinuous but still meet Class-A/D requirements of IEC 61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by generating a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain parametersformaintainingalow-distortion,steady-state,input-currentwaveshape. 20 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 8.2 Typical Application Figure 26 illustrates the design process and component selection for a continuous conduction mode power factor correction boost converter utilizing the UCC28019A. The target design is a universal input, 350-W PFC designed for an ATX supply application. This design process is directly tied to the UCC28019A Design Calculator (SLUC117) spreadsheet that can be found in the Tools section of the UCC28019A product folder on the Texas Instrumentswebsite. + + Figure26. DesignExampleSchematic Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Typical Application (continued) 8.2.1 DesignRequirements Design goal parameters for a continuous conduction mode power factor correction boost converter utilizing the UCC28019A. Table1.DesignGoalParameters PARAMETER TESTCONDITION MIN TYP MAX UNIT Inputcharacteristics V Inputvoltage 85 115 265 VAC IN f Inputfrequency 47 63 Hz LINE V I =0.9A 75 V AC(on), OUT AC Brownoutvoltage V I =0.9A 65 V AC(off), OUT AC Outputcharacteristics 85VAC≤V ≤265VAC,47Hz≤f ≤63 IN LINE V Outputvoltage Hz 380 390 402 V OUT DC 0A≤I ≤0.9A OUT VRIPPLE(SW Highfrequencyoutput VIN=115VAC,fLINE=60Hz,IOUT=0.9A 3.9 VPP ) voltageripple VIN=230VAC,fLINE=50Hz,IOUT=0.9A 3.9 VPP VRIPPLE(f_LI Linefrequencyoutput VIN=115VAC,fLINE=60Hz,IOUT=0.9A 19.5 VPP NE) voltageripple VIN=230VAC,fLINE=50Hz,IOUT=0.9A 19.5 VPP 85VAC≤V ≤265VAC,47Hz≤f ≤63 I Outputloadcurrent IN LINE 0.9 A OUT Hz P Outputpower 350 W OUT Outputovervoltage V 410 V OUT(OVP) protection Outputundervoltage V 370 V OUT(UVP) protection Controlloopcharacteristics f Switchingfrequency T =25°C 61.7 65 68.3 kHz SW J f Controlloopbandwidth V =162VDC,I =0.45A 14 Hz (CO) IN OUT Phasemargin V =162VDC,I =0.45A 70 degrees IN OUT PF Powerfactor V =115VAC,I =0.9A 0.98 IN OUT V =115VAC,f =60Hz,I =0.9A 4.3% 10% IN LINE OUT THD Totalharmonicdistortion V =230VAC,f =50Hz,I =0.9A 6.6% 10% IN LINE OUT η Fullloadefficiency V =115VAC,f =60Hz,I =0.9A 0.95 IN LINE OUT T Ambienttemperature 50 °C AMB 22 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 8.2.2 DetailedDesignProcedure 8.2.2.1 CurrentCalculations First,determinethemaximumaverageoutputcurrent,I : OUT(max) P I = OUT(max) OUT(max) V OUT (8) 350W I = @0.9A OUT(max) 390V (9) The maximum input RMS line current, I , is calculated using the parameters from Table 1 and the IN_RMS(max) efficiencyandpowerfactorinitialassumptions: P I = OUT(max) IN_RMS(max) hV PF IN(min) (10) 350W I = =4.52A IN_RMS(max) 0.92´85V´0.99 (11) Based upon the calculated RMS value, the maximum peak input current, I , and the maximum average IN_PEAK(max) inputcurrent,I ,assumingthewaveformissinusoidal,canbedetermined. IN_AVG(max) I = 2I IN_PEAK(max) IN_RMS(max) (12) I = 2´4.52A=6.39A IN_PEAK(max) (13) 2I I = IN_PEAK(max) IN_AVG(max) p (14) 2´6.39A I = =4.07A IN_AVG(max) p (15) 8.2.2.2 BridgeRectifier Assuming a forward voltage drop, V , of 0.95 V across the rectifier diodes, BR1, the power loss in the F_BRIDGE inputbridge,P ,canbecalculated: BRIDGE P =2V I BRIDGE F_BRIDGE IN_AVG(max) (16) P =2´0.95V´4.07A=7.73W BRIDGE (17) Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 8.2.2.3 InputCapacitor Note that the UCC28019A is a continuous conduction mode controller and as such the inductor ripple current should be sized accordingly. High inductor ripple current has an impact on the CCM/DCM boundary and results in higher light-load THD, and also affects the choices for R and C values. Allowing an inductor ripple SENSE ICOMP current, I , of 20% and a high frequency ripple voltage factor, ΔV , of 6%, the minimum input RIPPLE RIPPLE_IN capacitorvalue,C ,iscalculatedbyfirstdeterminingtheinputripplecurrent,I ,andtheinputripplevoltage, IN RIPPLE V : IN_RIPPLE(max) I =DI I RIPPLE RIPPLE IN_PEAK(max) (18) DI =0.2 RIPPLE (19) I =0.2´6.39A=1.28A RIPPLE (20) V =DV V IN_RIPPLE(max) RIPPLE_IN IN_RECTIFIED(min) (21) DV =0.06 RIPPLE_IN (22) V = 2V IN_RECTIFIED IN (23) V = 2´85V =120.2V IN_RECTIFIED(min) (24) V =0.06´120.2V =7.21V IN_RIPPLE(max) (25) Thevaluefortheinputx-capacitorcannowbecalculated: I C = RIPPLE IN 8f V SW IN_RIPPLE(max) (26) 1.28A C = =0.341mF IN 8´65kHz´7.21V (27) A0.33μF,275VACex-2filmcapacitorwasselectedforC . IN 24 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 8.2.2.4 BoostInductor Theboostinductor,L ,isselectedafterdeterminingthemaximuminductorpeakcurrent,I : BST L_PEAK(max) I I = I + RIPPLE L_PEAK(max) IN_PEAK(max) 2 (28) 1.28A I =6.39A+ =7.03A L_PEAK(max) 2 (29) Theminimumvalueoftheboostinductoriscalculatedbaseduponaworstcasedutycycleof0.5: V D(1-D) L ³ OUT BST(min) f I SW(typ) RIPPLE (30) 390V´0.5(1-0.5) L ³ ³1.17mH BST(min) 65kHz´1.28A (31) Theactualvalueoftheboostinductorthatwillbeusedis1.25mH. Themaximumdutycycle,DUTY ,canbecalculatedandwilloccurattheminimuminputvoltage: (max) V -V DUTY = OUT IN_RECTIFIED(min) (max) V OUT (32) V = 2´85V =120V IN_RECTIFIED(min) (33) 390V -120V DUTY = =0.692 (max) 390V (34) 8.2.2.5 BoostDiode The diode losses are estimated based upon the forward voltage drop, V , at 125°C and the reverse recovery F charge, Q , of the diode. This design uses a silicon-carbide diode. Although somewhat more expensive, it RR essentiallyeliminatesthereverserecoverylossesbecauseQ isequalto0nC. RR P =V I +0.5f V Q DIODE F_125C OUT(max) SW(typ) OUT RR (35) V =1.5V F_125C (36) Q =0nC RR (37) P =1.5V´0.897A+0.5´65kHz´390V´0nC =1.35W DIODE (38) Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 8.2.2.6 SwitchingElement The conduction losses of the switch are estimated using the R of the FET at 125°C , found in the FET data DS(on) sheet,andthecalculateddraintosourceRMScurrent,I : DS_RMS P = I2 R COND DS_RMS DSon(125C) (39) R =0.35W DSon(125C) (40) P 16V I = OUT(max) 2- IN_RECTIFIED(min) DS_RMS V 3pV IN_RECTIFIED(min) OUT (41) 350W 16´120V I = 2- =3.54A DS_RMS 120V 3p´390V (42) P =3.54A2´0.35W=4.38W COND (43) The switching losses are estimated using the rise time, (t), and fall time, (t), of the gate, and the output r f capacitancelosses. Fortheselecteddevice: t = 5.0 ns,t =4.5ns r f (44) C =780pF OSS (45) P = f (0.5V I (t +t )+0.5C V2 ) SW SW(typ) OUT IN-PEAK(max) r f OSS OUT (46) P =65kHz(0.5´390V´6.39A(5n+4.5ns)+0.5´780pF´390V2 )=4.626W SW (47) TotalFETlosses: P +P =4.38W +4.626W =9.007W COND SW (48) 26 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 8.2.2.7 SenseResistor To accommodate the gain of the internal non-linear power limit, R is sized such that it will trigger the soft SENSE over-current at 25% higher than the maximum peak inductor current using the minimum SOC threshold, V , of SOC ISENSE. V R = SOC SENSE I ´1.25 L_PEAK(max) (49) 0.66V R = =0.075W SENSE 7.03A´1.25 (50) Usingaparallelcombinationofavailablestandardvalueresistors,thesenseresistorischosen. R =0.067W SENSE (51) Thepowerdissipatedacrossthesenseresistor,P ,mustbecalculated: Rsense P = I2 R Rsense IN_RMS(max) SENSE (52) P =(4.52A)2´0.067W=1.37W Rsense (53) Thepeakcurrentlimit,PCL,protectionfeaturewillbetriggeredwhencurrentthroughthesenseresistorresultsin the voltage across R to be equal to the V threshold. For a worst case analysis, the maximum V SENSE PCL PCL thresholdisused: V I = PCL PCL R SENSE (54) 1.15V I = =17.16A PCL 0.067W (55) Toprotectthedevicefrominrushcurrent,astandard220-Ω resistor,R ,isplacedinserieswiththeISENSE ISENSE pin.A1000-pFcapacitor,C ,isplacedclosetothedevicetoimprovenoiseimmunityontheISENSEpin. ISENSE Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 8.2.2.8 OutputCapacitor The output capacitor, C , is sized to meet holdup requirements of the converter. Assuming the downstream OUT converters require the output of the PFC stage to never fall below 300 V, V , during one line cycle, OUT_HOLDUP(min) t =1/f ,theminimumcalculatedvalueforthecapacitoris: HOLDUP LINE(min) 2P t C ³ OUT HOLDUP OUT(min) V2 -V2 OUT OUT_HOLDUP(min) (56) 2´350W´21.28ms C ³ ³240mF OUT(min) 390V2 -300V2 (57) Itisadvisabletode-ratethiscapacitorvalueby20%;theactualcapacitorusedis270 μF. Setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the controller. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current oftheoutputcapacitorarecalculated: V <0.05V OUT_RIPPLE(pp) OUT (58) V <0.05´390V <19.5V OUT_RIPPLE(pp) PP (59) I V = OUT OUT_RIPPLE(pp) p(2f )C LINE(min) OUT (60) 0.9A V = =11.26V OUT_RIPPLE(pp) p(2´47Hz)´270mF (61) Therequiredripplecurrentratingattwicethelinefrequencyisequalto: I I = OUT(max) Cout_2fline 2 (62) 0.9A I = =0.635A Cout_2fline 2 (63) Therewillalsobeahighfrequencyripplecurrentthroughtheoutputcapacitor: 16V I = I OUT -1.5 Cout_HF OUT(max) 3pV IN_RECTIFIED(min) (64) 16´390V I =0.9A -1.5 =1.8A Cout_HF 3p´120V (65) The total ripple current in the output capacitor is the combination of both and the output capacitor must be selectedaccordingly: I = I2 +I2 Cout_RMS(total) Cout_2fline Cout_HF (66) I = 0.635A2 +1.8A2 =1.9A Cout_RMS(total) (67) 28 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 8.2.2.9 OutputVoltageSetPoint For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 MΩ for the top voltage feedback divider resistor, R . Multiple resistors in series are used due to the maximum FB1 allowable voltage across each. Using the internal 5-V reference, V , select the bottom divider resistor, R , to REF FB2 meettheoutputvoltagedesigngoals. V R R = REF FB1 FB2 V -V OUT REF (68) 5V´1MW R = =13.04kW FB2 390V -5V (69) Using13kΩ forR resultsinanominaloutputvoltagesetpointof391V. FB2 Theover-voltageprotection,OVD,willbetriggeredwhentheoutputvoltageexceeds5%ofitsnominalset-point: æ R +R ö V =VSENSE ç FB1 FB2 ÷ OUT(OVP) OVPè R ø FB2 (70) æ1MW+13kWö V =5.25V´ç ÷=410.7V OUT(OVP) è 13kW ø (71) The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominal set- point: æ R +R ö V =VSENSE ç FB1 FB2 ÷ OUT(UVD) UVDè R ø FB2 (72) æ1MW+13kWö V = 4.75V ´ç ÷=371.6V OUT(UVD) è 13kW ø (73) A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that the RC time constant is less than 0.1 ms so as not to significantly reduce the control response time to output voltage deviations. With careful layout, the noise on this design is minimal, so an RC time constant of 0.01 ms wasallthatwasneeded: 0.01ms C = VSENSE R FB2 (74) 0.01ms C = =769pF VSENSE 13kW (75) Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 8.2.2.10 LoopCompensation The selection of compensation components, for both the current loop and the voltage loop, is made easier by using the UCC28019A Design Calculator spreadsheet that can be found in the Tools section of the UCC28019A product folder on the Texas Instruments website. The current loop is compensated first by determining the productoftheinternalloopvariables,M M ,usingtheinternalcontrollerconstantsK andK : 1 2 1 FQ I V2 R K M M = OUT(max) OUT SENSE 1 1 2 h2V2 K IN_RMS FQ (76) 1 K = FQ f SW(typ) (77) 1 K = =15.385ms FQ 65kHz (78) K =7 1 (79) 0.9A´391V2´0.067W´7 V M M = =0.374 1 2 0.922´115V2´15.385ms ms (80) The VCOMP operating point is found on Figure 27. The Design Calculator spreadsheet enables the user to iterativelyselecttheappropriateVCOMPvalue. MM 1 2 vs VCOMP 2.0 1.8 1.6 1.4 1.2 M2 1.0 M1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 VCOMP -V Figure27. M M vs.VCOMP 1 2 30 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 ForthegivenM M of0.374V/μs,theVCOMPisapproximatelyequalto4,asshowninFigure27. 1 2 The individual loop factors, M which is the current loop gain factor, and M which is the voltage loop PWM ramp 1 2 slope,arecalculatedusingthefollowingconditions: TheM currentloopgainfactor: 1 • if:0<VCOMP <2 then : M = 0.064 1 (81) • if:2≤ VCOMP <3 then: M =0.139´VCOMP-0.214 1 (82) • if:3≤ VCOMP <5.5 then : M = 0.279´VCOMP -0.632 1 (83) • if:5.5≤ VCOMP <7 then: M =0.903 1 (84) Inthisexample: VCOMP=4 M =0.279´4-0.632=0.484 1 (85) TheM PWMrampslope: 2 • if:0<VCOMP <1.5 V then: M =0 2 ms (86) • if:1.5≤ VCOMP <5.6 V then: M =0.1223´(VCOMP-1.5)2 2 ms (87) • if:5.6≤ VCOMP <7 V then: M =2.056 2 ms (88) Inthisexample: VCOMP=4 V V M =0.1223´(4-1.5)2 =0.764 2 ms ms (89) Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Verify that the product of the individual gain factors is approximately equal to the M M factor determined above, 1 2 ifnot,reselectVCOMPandrecalculateM M . 1 2 V V M ´M =0.484´0.764 =0.37 1 2 ms ms (90) V V 0.37 @ M M =0.372 ms 1 2 ms (91) Thenon-lineargainvariable,M ,cannowbecalculated: 3 • if:0<VCOMP <3 then: M =0.0510´VCOMP2 -0.1543´VCOMP-0.1167 3 (92) • if:3≤ VCOMP <7 then: M =0.1026´VCOMP2 -0.3596´VCOMP+0.3085 3 (93) Inthisexample: VCOMP=4 M =0.1026´42 -0.3596´4+0.3085=0.512 3 (94) The frequency of the current averaging pole, f , is chosen to be at 9.5 kHz. The required capacitor on ICOMP, IAVG C ,forthisisdeterminedusingthetransconductancegain,g ,oftheinternalcurrentamplifier: ICOMP mi g M C = mi 1 ICOMP K 2p f 1 IAVG (95) 0.95mS´0.484 C = =1100pF ICOMP 7´2´p´9.5kHz (96) Usinga1200pFcapacitorforC resultsinacurrentaveragingpolefrequencyof8.7kHz: ICOMP g M f = mi 1 IAVG K 2pC 1 ICOMP (97) 0.95mS´0.484 f = =8.7kHz IAVG 7´2´p´1200pF (98) 32 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 Thetransferfunctionofthecurrentloopcanbeplotted: K R V 1 G ( f )= 1 SENSE OUT ´ CL K M M L s( f )2K C FQ 1 2 BST s( f )+ 1 ICOMP g M mi 1 (99) G ( f )=20log(G ( f )) CLdB CL (100) CURRENTAVERAGINGCIRCUIT 100 -80 80 60 Phase -100 40 20 -120 G(f)CLdB 0 Gain qG(f)CL -20 -140 -40 -60 -160 -80 -100 -180 10 100 1*103 1*104 1*105 1*106 f-Hz Figure28. BodePlotoftheCurrentAveragingCircuit. Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com The open loop of the voltage transfer function, G (f) contains the product of the voltage feedback gain, G , and VL FB the gain from the pulse width modulator to the power stage, G , which includes the pulse width modulator PWM_PS topowerstagepole,f .TheplottedresultisshowninFigure29. PWM_PS R G = FB2 FB R +R FB1 FB2 (101) 13kW G = =0.013 FB 1MW+13kW (102) 1 f = PWM_PS K R V3 C 2p 1 SENSE OUT OUT K M M V2 FQ 1 2 IN(typ) (103) 1 f = =1.581Hz PWM_PS 7´0.067W´391V3´270mF 2p V 15.385ms´0.484´0.764 ´115V2 ms (104) M V 3 OUT M M ´1ms G ( f )= 1 2 PWM_PS s( f ) 1+ 2p f PWM_PS (105) G ( f )=G G ( f ) VL FB PWM_PS (106) G ( f )=20log(G ( f )) VLdB VL (107) OPENLOOPVOLTAGETRANSFER FUNCTION 20 0 -20 0 Gain -40 G(f)VLdB -20 Phase qG(f)VL -60 -40 -80 -60 -100 0.01 0.1 1 10 100 1*103 1*104 f-Hz Figure29. BodePlotoftheOpenLoopVoltageTransferFunction 34 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 The voltage error amplifier is compensated with a zero, f , at the f pole and a pole, f , placed at 20 ZERO PWM_PS POLE Hztorejecthighfrequencynoiseandrolloffthegainamplitude.Theoverallvoltageloopcrossover,f ,isdesired V tobeat10Hz.Thecompensationcomponentsofthevoltageerroramplifierareselectedaccordingly. 1 f = ZERO 2pR C VCOMP VCOMP (108) 1 f = POLE R C C 2p VCOMP VCOMP VCOMP_P C +C VCOMP VCOMP_P (109) é ù ê ú ê 1+s( f )R C ú G ( f )= gmvê VCOMP VCOMP ú EA ê(C +C )s( f )êé1+s( f )çæ RVCOMPCVCOMPCVCOMP_P ÷öùúú ê VCOMP VCOMP_P ç C +C ÷ ú ë êë è VCOMP VCOMP_P øúûû (110) f =10Hz V (111) Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com From Figure 29, and the Design Calculator spreadsheet, the open loop gain of the voltage transfer function at 10 Hz is approximately 0.667 dB. Estimating that the parallel capacitor, C , is much smaller than the series VCOMP_P capacitor, C , the unity gain will be at f , and the zero will be at f , the series compensation capacitor VCOMP V PWM_PS isdetermined: f gmv V f C = PWM_PS VCOMP 10GVLd2B0(f)´2p f V (112) 10Hz 42mS´ 1.581Hz C = =3.92mF VCOMP 100.66270dB ´2´p´10Hz (113) A3.3-μFcapacitorisusedforC . VCOMP 1 R = VCOMP 2p f C ZERO VCOMP (114) 1 R = =30.51kW VCOMP 2´p´1.581Hz´3.3mF (115) A33.2-kΩ resistorisusedforR . VCOMP C C = VCOMP VCOMP_P 2p f R C -1 POLE VCOMP VCOMP (116) 3.3mF C = =0.258mF VCOMP_P 2´p ´20Hz´33.2kW´3.3mF -1 (117) 36 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 A0.22-μFcapacitorisusedforC . VCOMP_P Thetotalclosedlooptransferfunction,G ,containsthecombinedstagesandisplottedinFigure30. VL_total G ( f )=G ( f )G ( f )G ( f ) VL_total FB PWM_PS EA (118) G ( f )=20log(G ( f )) VL_totaldB VL_total (119) CLOSEDLOOPVOLTAGETRANSFER FUNCTION 100 100 50 80 G(f)VL_totaldB -500 Gain 4600 qG(f)VL_total Phase -100 20 -150 0 0.01 0.1 1 10 100 1*103 1*104 f-Hz Figure30. ClosedLoopVoltageBodePlot Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 8.2.2.11 BrownOutProtection Select the top divider resistor into the VINS pin so as not to contribute excessive power loss. The extremely low bias current into VINS means the value of R could be hundreds of megaOhms. For practical purposes, a VINS1 value less than 10 MΩ is usually chosen. Assuming approximately 150 times the input bias current through the resistor dividers will result in an R that is less than 10 MΩ , so as to not contribute excessive noise, and still VINS1 maintain minimal power loss. The brown out protection will turn off the gate drive when the input falls below the userprogrammableminimumvoltage,V ,andturnonwhentheinputrisesaboveV . AC(off) AC(on) I =150´I VINS VINS_0V (120) I =150´0.1mA=15mA VINS (121) V =75V AC(on) (122) V = 65V AC(off ) (123) 2´V -V -VINS R = AC(on) F_BRIDGE ENABLE_th(max) VINS1 I VINS (124) 2´75V -0.95V -1.6V R = =6.9MW VINS1 15mA (125) A6.5-Mresistanceischosen. VINS ´R R = ENABLE_th(max) VINS1 VINS2 2´V -VINS -V AC(on) ENABLE_th(max) F_BRIDGE (126) 1.6V´6.5MW R = =100kW VINS2 2´75V -1.6V -0.95V (127) 38 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 The capacitor on VINS, C , is selected so that it's discharge time is greater than the output capacitor hold up VINS time.C waschosentomeetone-cyclehold-uptimesoC willbechosentomeet2.5half-linecycles. OUT VINS N t = HALF_CYCLES CVINS_dischrg 2´ f LINE(min) (128) 2.5 t = = 25.6ms CVINS_dischrg 2´47Hz (129) -t C = CVINS_dischrg VINS é ù ê ú VINS ê ú R ´ln BROWNOUT_th(min) VINS2 ê æ R öú ê0.9´V ´ç VINS2 ÷ú êë IN_RMS(min) è RVINS1+RVINS2 øúû (130) -25.6ms C = =0.63mF VINS é ù ê 0.76V ú 100kW´lnê ú ê0.9´85V´æ 100kW öú ç ÷ êë è6.5MW+100kWøúû (131) 8.2.3 ApplicationCurves 1 20 IOUT 85 VAC 85 VAC, 50 Hz 0.95 IIOOUUTT 121350 VVAACC 18 121350 VVAACC,, 5500 HHzz IOUT 265 VAC 265 VAC, 50 Hz 16 0.9 D) H 0.85 on (T 14 actor storti 12 er F 0.8 c Di w ni 10 o o P m 0.75 ar H 8 al 0.7 Tot 6 0.65 4 0.6 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Load Current (A) Load Current (A) D001 D001 Figure31.PowerFactorvs.LoadCurrent Figure32.TotalHarmonicDistortionvs.LoadCurrent Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 9 Power Supply Recommendations 9.1 Bias Supply The UCC28019A operates from an external bias supply. It is recommended that the device be powered from a regulatedauxiliarysupply. NOTE This device is not intended to be used from a bootstrap bias supply. A bootstrap bias supply is fed from the input high voltage through a resistor with sufficient capacitance on VCC to hold up the voltage on VCC until current can be supplied from a bias winding on the boost inductor. For that reason, the minimal hysteresis on VCC would require an unreasonablevalueofhold-upcapacitance. During normal operation, when the output is regulated, current drawn by the device includes the nominal run currentplusthecurrentsuppliedtothegateoftheexternalboostswitch.Decouplingofthebiassupplymusttake switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitor of 0.1 μFminimumvaluefromVCCtoGNDwithshort,widetracesisrecommended. VCC VCC 10.5V (ON) VCC 9.5V (OFF) I CC I CC(ON) I <2.9mA CC(stby) I <200µA CC(start) Controller Soft- State UVLO Soft-Start Run Fault/Standby Run UVLO Start PWM OFF Ramp Regulated OFF Ramp Regulated OFF State Figure33. DeviceSupplyStates The device bias operates in several states. During startup, VCC Under-Voltage Lock-Out (UVLO) sets the minimum operational dc input voltage of the controller. There are two UVLO thresholds. When the UVLO turn-on threshold is exceeded, the PFC controller turns ON. If the VCC voltage falls below the UVLO turn-off threshold, the PFC controller turns off. During UVLO, current drawn by the device is minimal. After the device turns on, Soft Start (SS) is initiated and the boost inductor current is ramped up in a controlled manner to reduce the stress on the external components and avoids output voltage overshoot. During Soft Start and after the output is in regulation, the device draws its normal run current. If any of several fault conditions is encountered or if the deviceisputinStandbywithanexternalsignal,thedevicedrawsareducedstandbycurrent. 40 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 10 Layout 10.1 Layout Guidelines As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. The pin out of the UCC28019A is ideally suited for separating the high di/dt induced noise on the power ground from the low current quiet signal ground required for adequate noise immunity. A star point ground connection at the GND pin of the device can be achieved with a simple cut out in the ground plane of the printed circuit board. As shown in Figure 34, the capacitors on ISENSE, VINS, VCOMP, and VSENSE must all be returned directly to the quiet portion of the ground plane, indicated by Signal GND, and not the high current return path of the converter, shown as the Power GND. Because the example circuit in Figure 34 uses surface mount components, the ICOMP capacitor, C10, has its own dedicated return to the GND pin. Table2.LayoutComponents REFERENCEDESIGNATOR FUNCTION U1 UCC28019A Q1 Mainswitch R1 R GATE R5 Pull-downresistoronGATE C13,C14 VCCbypasscapacitors C10 ICOMPcompensation,C ICOMP R6 Inrushcurrentlimitingresistor,R ISENSE C11 I filter,C SENSE ISENSE R12,R13,R14 R onVSENSE FB1 R18 R onVSENSE FB2 C16 C VSENSE R16,C17,C15 VCOMPcompensationcomponents,R ,C ,C VCOMP VCOMP VCOMP_P C12,R17 C ,R onVINS VINS VINS2 D2 Boostdiode Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com Layout Guidelines (continued) 10.2 Layout Example Power GND Cut out in ground plane GND GATE ICOMP VCC ISENSE VSENSE VINS VCOMP Signal GND Figure34. RecommendedLayoutfortheUCC28019A 42 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

UCC28019A www.ti.com SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 RelatedProducts ThefollowingpartshavecharacteristicssimilartotheUCC28019Aandmaybeofinterest. Table3.RelatedProducts DEVICE DESCRIPTION UCC28019 8-PinCCMPFCController UCC3817/18 Full-FeaturePFCController UC2853A 8-PinCCMPFCController 11.2 Documentation Support 11.2.1 RelatedDocumentation These references, additional design tools, and links to additional references, including design software and modelsmaybefoundonthewebatwww.power.ti.comunderTechnicalDocuments. 1. DesignSpreadsheet,UCC28019ADesignCalculator,SLUC117 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2008–2017,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:UCC28019A

UCC28019A SLUS828D–DECEMBER2008–REVISEDOCTOBER2017 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 44 SubmitDocumentationFeedback Copyright©2008–2017,TexasInstrumentsIncorporated ProductFolderLinks:UCC28019A

PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC28019AD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 28019A & no Sb/Br) UCC28019ADR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 28019A & no Sb/Br) UCC28019AP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 125 28019A (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC28019ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Oct-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC28019ADR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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