Product Sample & Technical Tools & Support & Folder Buy Documents Software Community UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 UCC2752x Dual 5-A High-Speed, Low-Side Gate Driver 1 Features 3 Description • Industry-StandardPinout The UCC2752x family of devices are dual-channel, 1 high-speed, low-side gate-driver devices capable of • TwoIndependentGate-DriveChannels effectively driving MOSFET and IGBT power • 5-APeakSourceandSink-DriveCurrent switches. Using a design that inherently minimizes • Independent-EnableFunctionforEachOutput shoot-through current, UCC2752x can deliver high- peak current pulses of up to 5-A source and 5-A sink • TTLandCMOSCompatibleLogicThreshold into capacitive loads along with rail-to-rail drive IndependentofSupplyVoltage capability and extremely small propagation delay • Hysteretic-LogicThresholdsforHighNoise (typically 13 ns). In addition, the drivers feature Immunity matched internal propagation delays between the two • InputsandEnablePin-VoltageLevelsNot channels. These delays are very well suited for applications requiring dual-gate drives with critical RestrictedbyVDDPinBiasSupplyVoltage timing, such as synchronous rectifiers. This also • 4.5-Vto18-VSingle-SupplyRange enables connecting two channels in parallel to • OutputsHeldLowDuringVDD-UVLO,(Ensures effectively increase current-drive capability or driving Glitch-FreeOperationatPowerupandPower two switches in parallel with one input signal. The Down) input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and • FastPropagationDelays(13-nsTypical) independent of the VDD supply voltage. Wide • FastRiseandFallTimes(7-nsand6-nsTypical) hysteresisbetweenthehighandlowthresholdsoffers • 1-nsTypicalDelayMatchingBetweenTwo excellentnoiseimmunity. Channels DeviceInformation(1) • TwoOutputsareinParallelforHigherDrive Current PARTNUMBER PACKAGE BODYSIZE(NOM) • OutputsHeldLowWhenInputsFloating SOT-23(8) 4.90mm×3.91mm • PDIP(8),SOIC(8),MSOP(8) PowerPAD™and UCC27523 HVSSOP(8) 3.00mm×3.00mm 3-mm×3-mmWSON-8PackageOptions WSON(8) • OperatingTemperatureRangeof–40°Cto140°C SOT-23(8) 4.90mm×3.91mm HVSSOP(8) UCC27524 3.00mm×3.00mm 2 Applications WSON(8) PDIP(8) 9.81mm×6.35mm • Switched-ModePowerSupplies SOT-23(8) 4.90mm×3.91mm • DC-DCConverters UCC27525 HVSSOP(8) • MotorControl,SolarPower 3.00mm×3.00mm WSON(8) • GateDriveforEmergingWideBand-GapPower UCC27526 WSON(8) 3.00mm×3.00mm DevicessuchasGaN (1) For all available packages, see the orderable addendum at theendofthedatasheet. PinConfiguration OneInvertingandOne DualInputConfiguration DualInvertingInputs DualNon-InvertingInputs Non-InvertingInput UCC27526 UCC27523 UCC27524 UCC27525 INA- 1 8 INA+ ENA 1 8 ENB ENA 1 8 ENB ENA 1 8 ENB + INA 2 7 OUTA INA 2 7 OUTA INA 2 7 OUTA INB- 2 7 INB+ GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD GND 3 + 6 OUTA INB 4 5 OUTB INB 4 5 OUTB INB 4 5 OUTB OUTB 4 5 VDD 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.3 FeatureDescription.................................................13 2 Applications........................................................... 1 8.4 DeviceFunctionalModes........................................20 3 Description............................................................. 1 9 ApplicationandImplementation........................ 21 4 RevisionHistory..................................................... 2 9.1 ApplicationInformation............................................21 9.2 TypicalApplication..................................................21 5 Description(continued)......................................... 4 10 PowerSupplyRecommendations..................... 26 6 PinConfigurationandFunctions......................... 4 11 Layout................................................................... 26 7 Specifications......................................................... 6 11.1 LayoutGuidelines.................................................26 7.1 AbsoluteMaximumRatings......................................6 11.2 LayoutExample....................................................27 7.2 ESDRatings..............................................................6 11.3 ThermalConsiderations........................................27 7.3 RecommendedOperatingConditions.......................6 12 DeviceandDocumentationSupport................. 29 7.4 ThermalInformation..................................................6 7.5 ElectricalCharacteristics...........................................7 12.1 RelatedLinks........................................................29 7.6 SwitchingCharacteristics..........................................8 12.2 Trademarks...........................................................29 7.7 TypicalCharacteristics..............................................9 12.3 ElectrostaticDischargeCaution............................29 12.4 Glossary................................................................29 8 DetailedDescription............................................ 12 13 Mechanical,Packaging,andOrderable 8.1 Overview.................................................................12 Information........................................................... 29 8.2 FunctionalBlockDiagrams.....................................12 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionF(May,2013)toRevisionG Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 • ChangedUCC2752XGateDriverOutputStructureimage.................................................................................................. 17 ChangesfromRevisionE(June2012)toRevisionF Page • Added0.5toP equationinDriveCurrentandPowerDissipationsection....................................................................... 24 SW ChangesfromRevisionD(April2012)toRevisionE Page • AddedOUTA,OUTBvoltagefieldandvalues....................................................................................................................... 6 • Changedtablenotefrom"Valuesareverifiedbycharacterizationandarenotproductiontested."to"Valuesare verifiedbycharacterizationonbench."................................................................................................................................... 6 • Addednote,"Valuesareverifiedbycharacterizationandarenotproductiontested.".......................................................... 6 • ChangedSwitchingTimet valuesfrom10nsand25nsto15nsand25nsns............................................................... 7 PW • ChangedFunctionalBlockDiagramsimages....................................................................................................................... 12 • ChangedSlowInputSignalFigure33.................................................................................................................................. 18 2 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 ChangesfromRevisionC(March2012)toRevisionD Page • ChangedInputs(INA,INB,INA+,INA–,INB+,INB-)sectiontoincludeUCC2752X(D,DGN,DSD)information................ 7 • AddedInputs(INA,INB,INA+,INA-,INB+,INB-)UCC27524PONLYsection..................................................................... 7 • ChangedEnable(ENA,ENB)sectiontoincludeUCC2752X(D,DGN,DSD)information.................................................... 7 • AddedENABLE(ENA,ENB)UCC27524PONLYsection..................................................................................................... 7 ChangesfromRevisionB(December2011)toRevisionC Page • AddedR noteintheOutputs(OUTA,OUTB)section........................................................................................................ 7 OH • AddedanupdatedOutputStagesection............................................................................................................................. 17 • AddedUCC2752XGateDriverOutputStructureimage...................................................................................................... 17 • AddedanupdatedLowPropagationDelaysandTightlyMatchedOutputssection............................................................ 18 • AddedSlowInputSignalCombinedwithDifferencesinInputThresholdVoltageimage.................................................... 18 • AddedupdatedDriveCurrentandPowerDissipationsection............................................................................................. 23 • AddedaPSW...equation..................................................................................................................................................... 24 ChangesfromRevisionA(November2011)toRevisionB Page • ChangedSupplystartthresholdrowtoincludetwotemperatureranges............................................................................... 7 • ChangedMinimumoperatingvoltageaftersupplystartminandmaxvaluesfrom3.6Vto4.2Vto3.40Vand4.40V......7 • ChangedSupplyvoltagehysteresistypvaluefrom0.35to0.30........................................................................................... 7 • ChangedUCC27526BlockDiagramdrawing...................................................................................................................... 13 • ChangedUCC27526ChannelAinInvertingandChannelBinNon-InvertingConfigurationdrawing................................ 21 ChangesfromOriginal(November2011)toRevisionA Page • ChangeddatasheetstatustoProductionData...................................................................................................................... 1 Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com 5 Description (continued) The UCC2752x family provide the combination of three standard logic options — dual inverting, dual noninverting, one inverting and one noninverting driver. UCC27526 features a dual input design which offers flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin controls the state of the driver output. The unused input pin is used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family ensure that outputs are held LOW when input pins are in floating condition. The UCC27523, UCC27524, and UCC27525 devices feature Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation. UCC2752x family of devices are available in SOIC-8 (D), MSOP-8 with exposed pad (DGN) and 3-mm × 3-mm WSON-8 with exposed pad (DSD) packages. UCC27524 is also offered in PDIP-8 (P) package. UCC27526 is onlyofferedin3-mm ×3-mmWSON(DSD)package. 6 Pin Configuration and Functions D,DGN,orPPackageUCC2752(3,4,5) 8-PinSOT-23,HVSSOP,orPDIP DSDPackageUCC2752(3,4,5) TopView 8-PinWSON TopView EENNAA 11 88 EENNBB EENNAA 11 88 EENNBB IINNAA 22 77 OOUUTTAA IINNAA 22 77 OOUUTTAA GGNNDD 33 66 VVDDDD GGNNDD 33 66 VVDDDD IINNBB 44 55 OOUUTTBB IINNBB 44 55 OOUUTTBB DSDPackageUCC27526 8-PinWSON TopView IINNAA-- 11 88 IINNAA++ IINNBB-- 22 77 IINNBB++ GGNNDD 33 66 OOUUTTAA OOUUTTBB 44 55 VVDDDD 4 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 PinFunctions(UCC27523/UCC27524/UCC27525) PIN I/O DESCRIPTION NO. NAME EnableinputforChannelA:ENAbiasedLOWDisablesChannelAoutputregardlessofINAstate, 1 ENA I ENAbiasedHIGHorfloatingEnablesChannelAoutput,ENAallowedtofloathencethepin-to-pin compatibilitywithUCC2732XN/Cpin. InputtoChannelA:InvertingInputinUCC27523,Non-InvertingInputinUCC27524,Inverting 2 INA I InputinUCC27525,OUTAheldLOWifINAisunbiasedorfloating. 3 GND - Ground:Allsignalsreferencedtothispin. InputtoChannelB:InvertingInputinUCC27523,Non-InvertingInputinUCC27524,Non-Inverting 4 INB I InputinUCC27525,OUTBheldLOWifINBisunbiasedorfloating. 5 OUTB O OutputofChannelB 6 VDD I Biassupplyinput 7 OUTA O OutputofChannelA EnableinputforChannelB:ENBbiasedLOWDisablesChannelBoutputregardlessofINBstate, 8 ENB I ENBbiasedHIGHorfloatingEnablesChannelBoutput,ENBallowedtofloathencethepin-to-pin compatibilitywithUCC2732XN/Cpin. PinFunctions(UCC27526) PIN I/O DESCRIPTION NO. NAME InvertingInputtoChannelA:WhenChannelAisusedinNon-Invertingconfiguration,connect 1 INA– I INA–toGNDinordertoEnableChannelAoutput,OUTAheldLOWifINA–isunbiasedorfloating. InvertingInputtoChannelB:WhenChannelBisusedinNon-Invertingconfiguration,connect 2 INB– I INB–toGNDinordertoEnableChannelBoutput,OUTBheldLOWifINB–isunbiasedorfloating. 3 GND - Ground:Allsignalsreferencedtothispin. 4 OUTB I OutputofChannelB 5 VDD O BiasSupplyInput 6 OUTA I OutputofChannelA Non-InvertingInputtoChannelB:WhenChannelBisusedinInvertingconfiguration,connect 7 INB+ O INB+toVDDinordertoEnableChannelBoutput,OUTBheldLOWifINB+isunbiasedorfloating. Non-InvertingInputtoChannelA:WhenChannelAisusedinInvertingconfiguration,connect 8 INA+ I INA+toVDDinordertoEnableChannelAoutput,OUTAheldLOWifINA+isunbiasedorfloating. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings(1)(2) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Supplyvoltage VDD –0.3 20 DC –0.3 VDD+0.3 V OUTA,OUTBvoltage Repetitivepulse<200ns(3) –2 VDD+0.3 Outputcontinuoussource/sink I 0.3 current OUT_DC A Outputpulsedsource/sinkcurrent I 5 (0.5µs) OUT_pulsed INA,INB,INA+,INA–,INB+,INB–,ENA,ENBvoltage(4) –0.3 20 V Operatingvirtualjunctiontemperature,T –40 150 J Soldering,10s 300 °C Leadtemperature Reflow 260 Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoGNDunlessotherwisenoted.Currentsarepositiveinto,negativeoutofthespecifiedterminal.See Mechanical,Packaging,andOrderableInformationforthermallimitationsandconsiderationsofpackages. (3) Valuesareverifiedbycharacterizationonbench. (4) ThemaximumvoltageontheInputandEnablepinsisnotrestrictedbythevoltageontheV pin. DD 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±4000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- ±1000 V C101(2) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Supplyvoltage,VDD 4.5 12 18 V Operatingjunctiontemperature –40 140 °C Inputvoltage,INA,INB,INA+,INA–,INB+,INB– 0 18 V Enablevoltage,ENAandENB 0 18 7.4 Thermal Information UCC27523/4/5 UCC27524 UCC27523/4/5/6 THERMALMETRIC(1) SOIC(D) MSOP(DGN) PDIP(P) WSON(DSD) UNIT 8PINS 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 130.9 71.8 62.1 46.7 θJA R Junction-to-case(top)thermalresistance 80 65.6 52.7 46.7 θJC(top) R Junction-to-boardthermalresistance 71.4 7.4 39.1 22.4 θJB °C/W ψ Junction-to-topcharacterizationparameter 21.9 7.4 31 0.7 JT ψ Junction-to-boardcharacterizationparameter 70.9 31.5 39.1 22.6 JB R Junction-to-case(bottom)thermalresistance – 19.6 – 9.5 θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 6 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 7.5 Electrical Characteristics V =12V,T =T =–40°Cto140°C,1-µFcapacitorfromV toGND.Currentsarepositiveinto,negativeoutofthe DD A J DD specifiedterminal(unlessotherwisenoted,) PARAMETER TESTCONDITION MIN TYP MAX UNIT BIASCURRENTS V =3.4V, DD INA=V , 55 110 175 DD Start-upcurrent, INB=V DD I (basedonUCC27524Input μA DD(off) configuration) VDD=3.4V, INA=GND, 25 75 145 INB=GND UNDERVOLTAGELOCKOUT(UVLO) T =25°C 3.91 4.2 4.5 J V Supplystartthreshold ON T =–40°Cto140°C 3.7 4.2 4.65 J Minimumoperatingvoltage V V 3.4 3.9 4.4 OFF aftersupplystart VDD_H Supplyvoltagehysteresis 0.2 0.3 0.5 INPUTS(INA,INB,INA+,INA–,INB+,INB–),UCC2752X(D,DGN,DSD) Outputhighfornon-invertinginputpins V Inputsignalhighthreshold 1.9 2.1 2.3 IN_H Outputlowforinvertinginputpins Outputlowfornon-invertinginputpins V V Inputsignallowthreshold 1 1.2 1.4 IN_L Outputhighforinvertinginputpins V Inputhysteresis 0.7 0.9 1.1 IN_HYS INPUTS(INA,INB,INA+,INA–,INB+,INB–)UCC27524PONLY Outputhighfornon-invertinginputpins V Inputsignalhighthreshold 2.3 IN_H Outputlowforinvertinginputpins Outputlowfornon-invertinginputpins V V Inputsignallowthreshold 1 IN_L Outputhighforinvertinginputpins V Inputhysteresis 0.9 IN_HYS ENABLE(ENA,ENB)UCC2752X(D,DGN,DSD) V Enablesignalhighthreshold Outputenabled 1.9 2.1 2.3 EN_H V Enablesignallowthreshold Outputdisabled 0.95 1.15 1.35 V EN_L V Enablehysteresis 0.7 0.95 1.1 EN_HYS ENABLE(ENA,ENB)UCC27524PONLY V Enablesignalhighthreshold Outputenabled 2.3 EN_H V Enablesignallowthreshold Outputdisabled 0.95 V EN_L V Enablehysteresis 0.95 EN_HYS OUTPUTS(OUTA,OUTB) I Sink/sourcepeakcurrent(1) C =0.22µF,F =1kHz ±5 A SNK/SRC LOAD SW V -V Highoutputvoltage I =–10mA 0.075 DD OH OUT V V Lowoutputvoltage I =10mA 0.01 OL OUT R Outputpullupresistance(2) I =–10mA 2.5 5 7.5 Ω OH OUT R Outputpulldownresistance I =10mA 0.15 0.5 1 Ω OL OUT (1) Ensuredbydesign. (2) R representson-resistanceofonlytheP-ChannelMOSFETdeviceinpullupstructureofUCC2752Xoutputstage. OH Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com 7.6 Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Risetime (1) C =1.8nF 7 18 R LOAD t Falltime(1) C =1.8nF 6 10 F LOAD INA=INB,OUTAandOUTBat50% t Delaymatchingbetween2channels 1 4 M transitionpoint ns Minimuminputpulsewidththat t 15 25 PW changestheoutputstate t ,t Inputtooutputpropagationdelay (1) C =1.8nF,5-Vinputpulse 6 13 23 D1 D2 LOAD t ,t ENtooutputpropagationdelay (1) C =1.8nF,5-Venablepulse 6 13 23 D3 D4 LOAD (1) SeetimingdiagramsinFigure1,Figure2,Figure3,andFigure4 High High Input Input Low Low High High Enable Enable Low Low 90% 90% Output Output 10% 10% tD3 tD4 UDG-11217 tD3 tD4 UDG-11218 Figure1.EnableFunction Figure2.EnableFunction (ForNon-InvertingInputDriverOperation) (ForInvertingInputDriverOperation) High High Input Input Low Low High High Enable Enable Low Low 90% 90% Output Output 10% 10% tD1 tD2 UDG-11219 tD1 tD2 UDG-11220 Figure3.Non-InvertingInputDriverOperation Figure4.InvertingInputDriverOperation 8 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 7.7 Typical Characteristics 4 Input=VDD 0.14 Input=GND A) m A) nt ( nt (m 0.12 Curre 3.5 urre ply artup C 0.1 ng Sup 3 St ati VDD = 12 V 0.08 per fSW = 500 kHz O CL = 500 pF VDD=3.4V 0.06 2.5 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G001 G002 Figure5.Start-UpCurrentvsTemperature Figure6.OperatingSupplyCurrentvsTemperature (OutputsSwitching) 0.6 5 Input=GND UVLO Rising Input=VDD UVLO Falling A) 0.5 V) 4.5 upply Current (m 0.4 VLO Threshold ( 4 S 0.3 U 3.5 Enable=12 V VDD = 12 V 0.2 3 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G012 G003 Figure7.SupplyCurrentvsTemperature(OutputsinDC Figure8.UVLOThresholdvsTemperature ON/OFFCondition) 2.5 2.5 hold (V) 2 VDD = 12 V shold (V) 2 VDD = 12 V hres 1.5 Thre 1.5 ut T ble p a n n I 1 E 1 Input High Threshold Enable High Threshold Input Low Threshold Enable Low Threshold 0.5 0.5 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G004 G005 Figure9.InputThresholdvsTemperature Figure10.EnableThresholdvsTemperature Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Typical Characteristics (continued) 7 1 VDD = 12 V VDD = 12 V Wnce () 6 IOUT = −10 mA Wance () 0.8 IOUT = 10 mA esista Resist p R 5 wn 0.6 u o − d Pull ull− put 4 ut P 0.4 Out utp O 3 0.2 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G006 G007 Figure11.OutputPullupResistancevsTemperature Figure12.OutputPulldownResistancevsTemperature 10 9 VDD = 12 V VDD = 12 V CLOAD = 1.8 nF CLOAD = 1.8 nF 9 8 me (ns) 8 me (ns) 7 Rise Ti 7 Fall Ti 6 6 5 5 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G008 G009 Figure13.RiseTimevsTemperature Figure14.FallTimevsTemperature 18 18 nput to Output Propagation Delay (ns) 11110246 TTuurrnn−−oonff VCDLOD A=D 1=2 1 V.8 nF EN to Output Propagation Delay (ns) 11110246 EENN ttoo OOuuttppuutt HLoigwh VCDLOD A=D 1=2 1 V.8 nF I 8 8 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G010 G011 Figure15.InputtoOutputPropagationDelayvs Figure16.ENtoOutputPropagationDelayvsTemperature Temperature 10 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Typical Characteristics (continued) 60 22 VDD = 4.5 V Input to Output On delay A) 50 VDD = 12 V Input to Ouptut Off Delay Current (m 40 CLOADV =D D1 .=8 1n5F V elays (ns) 18 EENN ttoo OOuuttppuutt OOnff DDeellaayy ply 30 Both channels switching n D 14 p o Su ati erating 20 Propag 10 p 10 O CLOAD = 1.8 nF 0 6 0 100 200 300 400 500 600 700 800 900 1000 4 8 12 16 20 Frequency (kHz) Supply Voltage (V) G013 G014 Figure17.OperatingSupplyCurrentvsFrequency Figure18.PropagationDelaysvsSupplyVoltage 18 10 CLOAD = 1.8 nF CLOAD = 1.8 nF me (ns) 14 me (ns) 8 Rise Ti 10 Fall Ti 6 6 4 4 8 12 16 20 4 8 12 16 20 Supply Voltage (V) Supply Voltage (V) G015 G016 Figure19.RiseTimevsSupplyVoltage Figure20.FallTimevsSupplyVoltage 2.5 Enable High Threshold VDD = 4.5 V Enable Low Threshold V) 2 d ( ol h s hre 1.5 T e bl a n E 1 0.5 −50 0 50 100 150 Temperature (°C) G017 Figure21.EnableThresholdvsTemperature Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com 8 Detailed Description 8.1 Overview The UCC2752x family of products represent TI’s latest generation of dual-channel, low-side, high-speed gate- driver devices featuring 5-A source and sink current capability, industry best-in-class switching characteristics and a host of other features listed in Table 1 all of which combine to ensure efficient, robust and reliable operationinhigh-frequencyswitchingpowercircuits. Table1.UCC2752xFamilyofFeaturesandBenefits FEATURE BENEFIT Best-in-class13-ns(typ)propagationdelay Extremelylow-pulsetransmissiondistortion 1-ns(typ)delaymatchingbetweenchannels Easeofparallelingoutputsforhigher(2times)currentcapability, easeofdrivingparallel-powerswitches ExpandedVDDOperatingrangeof4.5to18V Flexibilityinsystemdesign Expandedoperatingtemperaturerangeof–40°Cto140°C (SeeElectricalCharacteristics) VDDUVLOProtection OutputsareheldLowinUVLOcondition,whichensurespredictable, glitch-freeoperationatpower-upandpower-down OutputsheldLowwheninputpins(INx)infloatingcondition Safetyfeature,especiallyusefulinpassingabnormalconditiontests duringsafetycertification Outputsenablewhenenablepins(ENx)infloatingcondition Pin-to-pincompatibilitywithUCC2732XfamilyofproductsfromTI,in designswherepin1and8areinfloatingcondition CMOS/TTLcompatibleinputandenablethresholdwithwide Enhancednoiseimmunity,whileretainingcompatibilitywith hysteresis microcontrollerlogiclevelinputsignals(3.3V,5V)optimizedfor digitalpower Abilityofinputandenablepinstohandlevoltagelevelsnotrestricted Systemsimplification,especiallyrelatedtoauxiliarybiassupply byV pinbiasvoltage architecture DD 8.2 Functional Block Diagrams VDD VDD VDD VDD 200kW 200kW 200kW 200kW ENA 1 8 ENB ENA 1 8 ENB VDD VDD VDD 200kW INA OUTA INA 2 7 OUTA 2 7 VDD 400kW VDD GND 3 VDD VDD VDD VDD UVLO 6 VDD GND 3 UVLO 6 VDD VDD 200kW INB OUTB INB 4 5 OUTB 4 5 400kW UDG-11221 Figure22.UCC27523BlockDiagram Figure23.UCC27524BlockDiagram 12 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Functional Block Diagrams (continued) VDD VDD INA+ 8 VDD 200kW 200kW 400kW 5 VDD ENA 1 8 ENB VDD VDD 200kW VDD 200kW VDD INA- 1 6 OUTA INA 2 7 OUTA VDD VDD GND 3 VDD UVLO GND 3 UVLO 6 VDD VDD VDD INB+ 7 4 OUTB INB 4 5 OUTB VDD 400kW 400kW 200kW UDG-11223 INB- 2 UDG-11222 Figure24.UCC27525BlockDiagram Figure25.UCC27526BlockDiagram 8.3 Feature Description 8.3.1 V andUndervoltageLockout DD The UCC2752x devices have internal undervoltage-lockout (UVLO) protection feature on the V pin supply DD circuit blocks. When V is rising and the level is still below UVLO threshold, this circuit holds the output LOW, DD regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis prevents chatter when low V supply voltages have noise from the power supply and also when there are DD droops in the V bias voltage when the system commences switching and there is a sudden increase in I . DD DD The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics,isespeciallysuitedfordrivingemergingGaNpowersemiconductordevices. For example, at power up, the UCC2752x driver-device output remains LOW until the V voltage reaches the DD UVLO threshold if Enable pin is active or floating. The magnitude of the OUT signal rises with V until steady- DD state V is reached. The non-inverting operation in Figure 26 shows that the output remains LOW until the DD UVLO threshold is reached, and then the output is in-phase with the input. The inverting operation in Figure 27 shows that the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input. With UCC27526 the output turns to high-state only if INX+ is high and INX– is low after the UVLO thresholdisreached. Because the device draws current from the V pin to bias all internal circuits, for the best high-speed circuit DD performance,TIrecommendstwoV bypasscapacitorstopreventnoiseproblems.TIhighlyrecommendsusing DD surface-mount components. A 0.1-μF ceramic capacitor must be located as close as possible to the V to GND DD pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low ESR must be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors presents a low impedance characteristic for the expected current levels andswitchingfrequenciesintheapplication. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Feature Description (continued) VDDThreshold VDDThreshold VDD VDD EN EN IN IN OUT OUT UDG-11228 UDG-11229 Figure26. PowerupNon-InvertingDriver Figure27.PowerupInvertingDriver 8.3.2 OperatingSupplyCurrent The UCC2752x products feature very low quiescent I currents. The typical operating-supply current in UVLO DD state and fully on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and Figure 7. The I current when the device is fully on and outputs are in a static state (DC high or DC low, refer DD Figure 6) represents lowest quiescent I current when all the internal logic circuits of the device are fully DD operational. The total supply current is the sum of the quiescent I current, the average I current due to DD OUT switching and finally any current related to pullup resistors on the enable pins and inverting input pins. For example when the inverting Input pins are pulled low additional current is drawn from V supply through the DD pullup resistors (refer to Figure 22 though Figure 25). Knowing the operating frequency (f ) and the MOSFET SW gate (Q ) charge at the drive voltage being used, the average I current can be calculated as product of Q G OUT G andf . SW A complete characterization of the I current as a function of switching frequency at different V bias voltages DD DD under 1.8-nF switching load in both channels is provided in Figure 17. The strikingly linear variation and close correlation with theoretical value of average I indicates negligible shoot-through inside the gate-driver device OUT attestingtoitshigh-speedcharacteristics. 14 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Feature Description (continued) 8.3.3 InputStage The input pins of UCC2752x gate-driver devices are based on a TTL and CMOS compatible input-threshold logic that is independent of the V supply voltage. With typically high threshold = 2.1 V and typically low threshold = DD 1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from 3.3-V and 5-V digital power-controller devices. Wider hysteresis (typ 0.9 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. UCC2752x devices also feature tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature (refer to Figure 9). The very low input capacitance on these pins reducesloadingandincreasesswitchingspeed. The UCC2752x devices feature an important safety feature wherein, whenever any of the input pins is in a floating condition, the output of the respective channel is held in the low state. This is achieved using V pullup DD resistors on all the Inverting inputs (INA, INB in UCC27523, INA in UCC27525 and INA–, INB– in UCC27526) or GND pulldown resistors on all the non-inverting input pins (INA, INB in UCC27524, INB in UCC27525 and INA+, INB+inUCC27526),asshowninthedeviceblockdiagrams. While UCC27523/4/5 devices feature one input pin per channel, the UCC27526 features a dual input configurationwithtwoinputpinsavailabletocontroltheoutputstateofeachchannel.WiththeUCC27526device the user has the flexibility to drive each channel using either a non-inverting input pin (INx+) or an inverting input pin (INx–). The state of the output pin is dependent on the bias on both the INx+ and INx– pins (where x = A, B). OnceanInputpinischosentodriveachannel,theotherinputpinofthatchannel(theunusedinputpin)mustbe properly biased in order to enable the output of the channel. The unused input pin cannot remain in a floating condition because, as mentioned earlier, whenever any input pin is left in a floating condition, the output of that channel is disabled using the internal pullup or pulldown resistors for safety purposes. Alternatively, the unused inputpinisusedeffectivelytoimplementanenable/disablefunction,asexplainedbelow. • In order to drive the channel x (x = A or B) in a non-inverting configuration, apply the PWM control input signal to INx+ pin. In this case, the unused input pin, INx-, must be biased low (for example, tied to GND) in ordertoenabletheoutputofthischannel. – Alternately, the INx– pin can be used to implement the enable/disable function using an external logic signal.OUTxisdisabledwhenINx-isbiasedHighandOUTxisenabledwhenINX–isbiasedlow. • Inordertodrivethechannelx(x=AorB)inanInvertingconfiguration,applythePWMcontrolinputsignalto INX– pin. In this case, the unused input pin, INX+, must be biased high (for example, tied to VDD) in order to enabletheoutputofthechannel. – Alternately, the INX+ pin can be used to implement the enable/disable function using an external logic signal.OUTXisdisabledwhenINX+isbiasedlowandOUTXisenabledwhenINX+isbiasedhigh. • Finally, it is worth noting that the UCC27526 output pin can be driven into high state only when INx+ pin is biasedhighandINx-inputisbiasedlow. Refer to the input/output logic truth table and typical application diagrams, (Figure 34, Figure 35, and Figure 35), foradditionalclarification. The input stage of each driver is driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (< 200 ns) with a slow changing input voltage, the output of the driver may switch repeatedly at a high frequency. While the wide hysteresis offered in UCC2752x definitely alleviates this concern over most other TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall times to the power device is the primary goal, then TI highly recommends an external resistance between the output of the driver and the power device. This external resistor has the additional benefit of reducing part of the gate-charge related power dissipation in the gate-driver device package and transferring it into the external resistoritself. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Feature Description (continued) 8.3.4 EnableFunction The enable function is an extremely beneficial feature in gate-driver devices especially for certain applications such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative currentcirculationandtoimprovelight-loadefficiency. UCC27523/4/5 devices are provided with independent enable pins ENx for exclusive control of each driver- channel operation. The enable pins are based on a non-inverting configuration (active-high operation). Thus when ENx pins are driven high the drivers are enabled and when ENx pins are driven low the drivers are disabled. Like the input pins, the enable pins are also based on a TTL and CMOS compatible input-threshold logic that is independent of the supply voltage and are effectively controlled using logic signals from 3.3-V and 5- V microcontrollers. The UCC2752X devices also feature tight control of the Enable-function threshold-voltage levels which eases system design considerations and ensures stable operation across temperature (refer to Figure 10). The ENx pins are internally pulled up to V using pullup resistors as a result of which the outputs of DD the device are enabled in the default state. Hence the ENx pins are left floating or Not Connected (N/C) for standard operation, where the enable feature is not needed. Essentially, this floating allows the UCC27523/4/5 devices to be pin-to-pin compatible with TI’s previous generation drivers UCC27323/4/5 respectively, where pins 1, 8 are N/C pins. If the Channel A and Channel B inputs and outputs are connected in parallel to increase the drivercurrentcapacity,ENAandENBareconnectedanddriventogether. The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an enable/disable function is easily implemented in UCC27526 using the unused input pin. When INx+ is pulled downtoGNDorINx– ispulleddowntoVDD,theoutputisdisabled.ThusINx+pinisusedlikeanenablepinthat is based on active high logic, while INx– is used like an enable pin that is based on active low logic. Note that while the ENA, ENB pins in UCC27523/4/5 are allowed to be in floating condition during standard operation and the outputs will be enabled, the INx+, INx– pins in UCC27526 are not allowed to be floating because this will disabletheoutputs. 16 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Feature Description (continued) 8.3.5 OutputStage The UCC2752x device output stage features a unique architecture on the pullup structure which delivers the highest peak-source current when it is most needed during the Miller plateau region of the power-switch turnon transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a P-channel MOSFET and an additional N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon. This is accomplished by briefly turning-on the N-channel MOSFET during a narrow instant when the output is changing state from Low to High. VCC R OH R ,Pull Up NMOS Gate Voltage OUT Input Signal Anti Shoot- Boost Through Circuitry Narrow Pulse at each Turn On R OL Figure28. UCC2752xGateDriverOutputStructure The R parameter (see Electrical Characteristics) is a DC measurement and it is representative of the on- OH resistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC condition and is turned-on only for a narrow instant when output changes state from low to high. Note that effective resistance of UCC2752x pullup stage during the turnon instant is much lower than what is represented byR parameter. OH The pulldown structure in UCC2752x is simply composed of a N-Channel MOSFET. The R parameter (see OL Electrical Characteristics), which is also a DC measurement, is representative of the impedance of the pulldown stage in the device. In UCC2752x, the effective resistance of the hybrid pullup structure during turnon is estimatedtobeapproximately1.5×R ,estimatedbasedondesignconsiderations. OL Each output stage in UCC2752x can supply 5-A peak source and 5-A peak sink current pulses. The output voltage swings between V and GND providing rail-to-rail operation, thanks to the MOS-output stage which DD delivers very low drop-out. The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots which means that in many cases, external Schottky-diode clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damagetothedeviceorlogicmalfunction. The UCC2752x devices are particularly suited for dual-polarity, symmetrical drive-gate transformer applications where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being driven complementary to each other. This situation is due to the extremely low drop-out offered by the MOS output stage of these devices, both during high (V ) and low (V ) states along with the low impedance of the driver OH OL output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance. Thelowpropagationdelaysalsoensureaccurateresetforhigh-frequencyapplications. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Feature Description (continued) For applications that have zero voltage switching during power MOSFET turnon or turnoff interval, the driver supplies high-peak current for fast switching even though the miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before power MOSFETisswitchedon. 8.3.6 LowPropagationDelaysandTightlyMatchedOutputs TheUCC2752xdriverdevicesfeatureabestinclass,13-ns(typical)propagationdelaybetweeninputandoutput which goes to offer the lowest level of pulse-transmission distortion available in the industry for high frequency switching applications. For example in synchronous rectifier applications, the SR MOSFETs are driven with very low distortion when one driver device is used to drive both the SR MOSFETs. Further, the driver devices also feature an extremely accurate, 1-ns (typ) matched internal-propagation delays between the two channels which is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both channels are driven by a common control signal from the PFC controller device. In this case the 1ns delay matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turnon delay difference. Yet another benefit of the tight matching between the two channels is that the two channels are connected together to effectively increase current drive capability, for example A and B channels may be combined into one driver by connecting the INA and INB inputs together and the OUTA and OUTB outputs together.Then,onesignalcontrolstheparalleledcombination. Caution must be exercised when directly connecting OUTA and OUTB pins together because there is the possibility that any delay between the two channels during turnon or turnoff may result in shoot-through current conduction as shown in Figure 29. While the two channels are inherently very well matched (4-ns Max propagation delay), note that there may be differences in the input threshold voltage level between the two channels which causes the delay between the two outputs especially when slow dV/dt input signals are employed. TI recommends the following guidelines whenever the two driver channels are paralleled using direct connectionsbetweenOUTAandOUTBalongwithINAandINB: • Use very fast dV/dt input signals (20 V/µs or greater) on INA and INB pins to minimize impact of differences ininputthresholdscausingdelaysbetweenthechannels. • INAandINBconnectionsmustbemadeasclosetothedevicepinsaspossible. Wherever possible, a safe practice would be to add an option in the design to have gate resistors in series with OUTA and OUTB. This allows the option to use 0-Ω resistors for paralleling outputs directly or to add appropriate seriesresistancestolimitshoot-throughcurrent,shoulditbecomenecessary. VDD VDD 200kW 200kW ENA 1 8 ENB VDD ISHOOT-THROUGH Slow Input Signal INA OUTA 2 7 VIN_H (Channel B) 400kW VDD V(CINh_HannelA) VDD VDD UVLO GND 3 6 VDD INB OUTB 4 5 400kW Figure29. SlowInputSignalMayCauseShoot-ThroughBetweenChannelsDuringParalleling (RecommendeddV/dTis20V/ΜsorHigher) 18 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Feature Description (continued) Figure30.TurnonPropagationDelay Figure31.TurnonRiseTime (C =1.8nF,V =12V) (C =1.8nF,V =12V) L DD L DD Figure32.TurnoffPropagationDelay Figure33.TurnoffFallTime (C =1.8nF,V =12V) (C =1.8nF,V =12V) L DD L DD Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com 8.4 Device Functional Modes Table2.DeviceLogicTable(UCC27523/4/5) UCC27523/4/5 UCC27523 UCC27524 UCC27525 ENA ENB INA INB OUTA OUTB OUTA OUTB OUTA OUTB H H L L H H L L H L H H L H H L L H H H H H H L L H H L L L H H H H L L H H L H L L Any Any L L L L L L Any Any x(1) x(1) L L L L L L x(1) x(1) L L H H L L H L x(1) x(1) L H H L L H H H x(1) x(1) H L L H H L L L x(1) x(1) H H L L H H L H (1) Floatingcondition. Table3.DeviceLogicTable(UCC27526) INx+(x=AorB) INx-(x=AorB) OUTx(x=AorB) L L L L H L H L H H H L x(1) Any L Any x(1) L (1) x=Floatingcondition. 20 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to effect fast switching of power devices and reduce associated switching-power losses, a powerful gate-driver device employs between the PWM output of control devices and the gates of the power semiconductor devices. Further, gate-driver devices are indispensable when having the PWM controller device directly drive the gates of the switching devices is sometimes not feasible. With advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a powerswitch.Alevel-shiftingcircuitryisneededtoboostthe3.3-Vsignaltothegate-drivevoltage(suchas12V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer-drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations, prove inadequate with digital power because they lack level-shifting capability. Gate-driver devices effectively combine both the level-shifting and buffer-drive functions. Gate-driver devices also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation andthermalstressincontrollerdevicesbymovinggate-chargepowerlossesintothecontroller. Finally, emerging wide band-gap power-device technologies such as GaN based switches, which can support very high switching frequency operation, are driving special requirements in terms of gate-drive capability. These requirements include operation at low V voltages (5 V or lower), low propagation delays, tight delay matching DD andavailabilityincompact,low-inductancepackageswithgoodthermalcapability. In summary gate-driver devices are extremely important components in switching power combining benefits of high-performance,low-cost,component-count,board-spacereduction,andsimplifiedsystemdesign. 9.2 Typical Application ENB UCC2752x ENA 1 ENA ENB 8 INA 2 INA OUTA 7 3 GND VDD 6 V+ GND INB 4 INB OUTB 5 GND GND UDG-11225 Figure34. UCC2752xTypicalApplicationDiagram(x=3,4,or5) Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Typical Application (continued) UCC27526 INA- 1 INA- INA+ 8 2 INB- INB+ 7 INB+ 3 GND OUTA 6 V+ GND GND 4 OUTB VDD 5 GND UDG-11226 Figure35. UCC27526ChannelAinInvertingandChannelBinNon-InvertingConfiguration(Enable FunctionNotUsed) OUTAis UCC27526 ENABLEDwhen ENAisHIGH INA- 1 INA- INA+ 8 ENA ENB 2 INB- INB+ 7 INB+ OUTBis ENABLEDwhen 3 GND OUTA 6 ENBisLOW V+ GND GND 4 OUTB VDD 5 GND UDG-11227 Figure36. UCC27526ChannelAinInvertingandChannelBinNon-InvertingConfiguration(Enable FunctionImplemented) 9.2.1 DesignRequirements When selecting the proper gate-driver device for an end application, some design considerations must be evaluated first in order to make the most appropriate selection. Among these considerations are input-to-output logic,VDD,UVLO,Drivecurrentandpowerdissipation. 9.2.2 DetailedDesignProcedure 9.2.2.1 Input-to-OutputLogic Thedesignshouldspecifywhichtypeofinput-to-outputconfigurationshouldbeused.TheUCC27523devicecan provide dual inverting input to output with enable control. The UCC27524 device can provide dual non-inverting input to output with enable control. The UCC27525 device can provide one inverting and one non-inverting input to output control. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred, then the non-inverting configuration must be selected. If turning off the power MOSFET or IGBT when the input 22 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Typical Application (continued) signal is in high state is preferred, the inverting configuration must be chosen. UCC27526 has dual configuration channel. Each Channel of UCC27526 device can be configured in either an inverting or non-inverting input-to- output configuration using the INx– or INx+ pins respectively like in Figure 35 and Figure 36. To configure the channelforuseininvertingmode,tietheINx+pintoVDDandapplytheinputsignaltotheINx– pin.Forthenon- invertingconfiguration,tietheINx– pintoGNDandapplytheinputsignaltotheINx+pin. 9.2.2.2 EnableandDisableFunction Certain applications demand independent control of the output state of the driver. The UCC27523/4/5 device offerstwoindependentenablepinsENxforexclusivecontrolofeachdriverchannelsaslistedinTable2. The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an enable/disable function can be easily implemented in UCC27526 using the unused input pin. When INx+ is pulled-downtoGNDorINx– ispulled-downtoVDD,theoutputisdisabledaslistedinTable3.ThusINx+pincan be used like an enable pin that is based on active high logic, while INx– can be used like an enable pin that is based on active low logic. It is important to note that while the ENA, ENB pins in the UCC27523/4/5 are allowed to be in floating condition during standard operation and the outputs will be enabled, the INx+, INx– pins in UCC27526arenotallowedtobefloatingbecausethiswilldisabletheoutputs. 9.2.2.3 VDDBiasSupplyVoltage The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the Recommended Operating Conditions. However, different power switches demand different voltage levels to be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the VDD bias supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC2752x device can be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10 V, 12 V), IGBTs(VGE=15V,18V). 9.2.2.4 PropagationDelay The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC2752x device features fast 13-ns (typical) propagation delays which ensures very little pulse distortion and allows operation at very high- frequencies. See the Switching Characteristics for the propagation and switching characteristics of the UCC2752xdevice. 9.2.2.5 DriveCurrentandPowerDissipation The UCC27523/4/5/6 family of drivers are capable of delivering 5-A of current to a MOSFET gate for a period of several-hundred nanoseconds at V = 12 V. High peak current is required to turn the device ON quickly. Then, DD to turn the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the operatingfrequencyofthepowerdevice.Thepowerdissipatedinthegate-driverdevicepackagedependsonthe followingfactors: • Gate charge required of the power MOSFET (usually a function of the drive voltage V , which is very close GS toinputbiassupplyvoltageV duetolowV drop-out) DD OH • Switchingfrequency • Useofexternalgateresistors Because UCC2752x features very low quiescent currents and internal logic to eliminate any shoot-through in the output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be negligible. Whenadriverdeviceistestedwithadiscrete,capacitiveloadcalculatingthepowerthatisrequiredfromthebias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given byEquation1. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Typical Application (continued) 1 E = C V 2 G LOAD DD 2 where • C isloadcapacitor LOAD • V isbiasvoltagefeedingthedriver. (1) DD There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss givenbyEquation2. P =C V 2f G LOAD DD SW where • f istheswitchingfrequency (2) SW WithV =12V,C =10nFand ƒ =300kHzthepowerlossiscalculatedas(seeEquation3): DD LOAD SW P =10nF´12V2´300kHz=0.432W G (3) The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Q , the power that must be dissipated when g charging a capacitor is determined which by using the equivalence Q = C V to provide Equation 4 for g LOAD DD power: P =C V 2f =Q V f G LOAD DD SW g DD SW (4) Assuming that UCC2752x is driving power MOSFET with 60 nC of gate charge (Q = 60 nC at V = 12 V) on g DD eachoutput,thegatechargerelatedpowerlossiscalculatedas(seeEquation5): P =2x60nC´12V´300kHz=0.432W G (5) This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driverandMOSFET/IGBT,thispoweriscompletelydissipatedinsidethedriverpackage.Withtheuseofexternal gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistorinaccordancetotheratiooftheresistances(morepowerdissipatedinthehigherresistancecomponent). Based on this simplified analysis, the driver power dissipation during switching is calculated as follows (see Equation6): æ R R ö PSW =0.5´QG´VDD´fSW ´ç OFF + ON ÷ R +R R +R è OFF GATE ON GATE ø where • R =R OFF OL • R (effectiveresistanceofpullupstructure)=1.5xR (6) ON OL In addition to the above gate-charge related power dissipation, additional dissipation in the driver is related to the power associated with the quiescent bias current consumed by the device to bias all internal circuits such as inputstage(withpullupandpulldownresistors),enable,andUVLOsections.AsshowninFigure6,thequiescent current is less than 0.6 mA even in the highest case. The quiescent power dissipation is calculated easily with Equation7. P =I V Q DD DD (7) Assuming,I =6mA,thepowerlossis: DD P =0.6mA´12V =7.2mW Q (8) Clearly,thispowerlossisinsignificantcomparedtogatechargerelatedpowerdissipationcalculatedearlier. 24 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Typical Application (continued) With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the quiescentconsumption: P 0.432 W I ~ G = =0.036 A DD V 12 V DD (9) 9.2.3 ApplicationCurves Figure 37 and Figure 38 show the typical switching characteristics of the non-inverting input driver operation for UCC27523/4/5/6device.C =1.8nF,V =12V L DD Figure37.TypicalTurnonWaveform Figure38.TypicalTurnoffWaveform Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com 10 Power Supply Recommendations The bias supply voltage range for which the UCC2752X device is rated to operate is from 4.5 V to 18 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VON supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDDpinis18V. The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage has exceeded the threshold voltage, device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD_H. Therefore, ensuring that, while operating at or near the 4.2-V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the VOFF threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system startup, the device does not begin operation until the VDD pin voltage has exceeded above the VON threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. It is important to recognize that the charge for source current pulses delivered by the OUTA/B pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the output pins, a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that local bypass capacitors are provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI recommends having two capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged very close tothepinsofthedeviceandanothersurface-mountcapacitoroffewmicrofaradsaddedinparallel. 11 Layout 11.1 Layout Guidelines Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device operation and design robustness. The UCC27523/4/5/6 family of gate drivers incorporates short propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power MOSFET to facilitate voltage transitions very quickly. At higher V voltages, the peak current DD capability is even higher (5-A peak current is at V = 12 V). Very high di/dt causes unacceptable ringing if the DD trace lengths and impedances are not well controlled. TI strongly recommends the following circuit layout guidelineswhendesigningwiththesehigh-speeddrivers. • Locate the driver device as close as possible to power device in order to minimize the length of high-current tracesbetweentheOutputpinsandtheGateofthepowerdevice. • LocatetheV bypasscapacitorsbetweenV andGNDascloseaspossibletothedriverwithminimaltrace DD DD length to improve the noise filtering. These capacitors support high peak current being drawn from V during DD turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and chip capacitorsishighlyrecommended. • The turnon and turnoff current loop paths (driver device, power MOSFET and V bypass capacitor) should DD be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is established in these loops at 2 instances during turnon and turnoff transients, which will induce significant voltagetransientsontheoutputpinofthedriverdeviceandGateofthepowerMOSFET. • Whereverpossible,parallelthesourceandreturntraces,takingadvantageoffluxcancellation • Separatepowertracesandsignaltraces,suchasoutputandinputsignals. • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM controller at one, single point. The connected paths must be as short as possible to reduce inductance and beaswideaspossibletoreduceresistance. • Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition tonoiseshielding,thegroundplanecanhelpinpowerdissipationaswell 26 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 Layout Guidelines (continued) • In noisy environments, tying inputs of an unused channel of UCC27526 to V (in case of INx+) or GND (in DD case of INX–) using short traces in order to ensure that the output is enabled and to prevent noise from causingmalfunctionintheoutputmaybenecessary. • ExercisecautionwhenreplacingtheUCC2732x/UCC2742xdeviceswiththeUCC2752x: – UCC2752xisamuchstrongergatedriver(5-Apeakcurrentversus4-Apeakcurrent). – UCC2752xisamuchfastergatedriver(13-ns/13-nsrise/fallpropagationdelayversus25-ns/35-nsrise/fall propagationdelay). 11.2 Layout Example Figure39. LayoutExampleforUCC27523/4/5(D,DGN) 11.3 Thermal Considerations The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a gate-driver device to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC27523/4/5/6 family of drivers is available in four different packages to cover a range of application requirements. The thermal metrics for each of these packages are summarized in Thermal Information. For detailed information regarding the thermal information table, refer to Application Note fromTexasInstrumentsentitled,ICPackageThermalMetrics (SPRA953). Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 www.ti.com Thermal Considerations (continued) Among the different package options available in the UCC2752x family, of particular mention are the DSD and DGN packages when it comes to power dissipation capability. The MSOP PowerPAD-8 (DGN) package and 3- mm × 3-mm WSON (DSD) package offer a means of removing the heat from the semiconductor junction through the bottom of the package. Both these packages offer an exposed thermal pad at the base of the package. This pad is soldered to the copper on the printed-circuit-board directly underneath the device package, reducing the thermalresistancetoaverylowvalue.Thisallowsasignificantimprovementinheat-sinkingoverthatavailablein the D or P packages. The printed-circuit-board must be designed with thermal lands and thermal vias to complete the heat removal subsystem. Note that the exposed pads in the MSOP-8 (PowerPAD) and WSON-8 packages are not directly connected to any leads of the package, however, it is electrically and thermally connected to the substrate of the device which is the ground of the device. TI recommends to externally connect theexposedpadstoGNDinPCBlayoutforbetterEMIimmunity. 28 SubmitDocumentationFeedback Copyright©2011–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

UCC27523,UCC27524,UCC27525,UCC27526 www.ti.com SLUSAQ3G–NOVEMBER2011–REVISEDAPRIL2015 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC27523 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27524 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27525 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27526 Clickhere Clickhere Clickhere Clickhere Clickhere 12.2 Trademarks PowerPADisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2011–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UCC27523 UCC27524 UCC27525 UCC27526

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC27523D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27523 & no Sb/Br) UCC27523DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 140 27523 & no Sb/Br) UCC27523DGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 140 27523 & no Sb/Br) UCC27523DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27523 & no Sb/Br) UCC27523DSDR ACTIVE SON DSD 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 27523 & no Sb/Br) UCC27523DSDT ACTIVE SON DSD 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 27523 & no Sb/Br) UCC27524D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27524 & no Sb/Br) UCC27524DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 140 27524 & no Sb/Br) UCC27524DGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 140 27524 & no Sb/Br) UCC27524DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27524 & no Sb/Br) UCC27524DSDR ACTIVE SON DSD 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 SBA & no Sb/Br) UCC27524DSDT ACTIVE SON DSD 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 SBA & no Sb/Br) UCC27524P ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 140 27524 & no Sb/Br) UCC27525D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27525 & no Sb/Br) UCC27525DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 140 27525 & no Sb/Br) UCC27525DGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 140 27525 & no Sb/Br) UCC27525DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27525 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC27525DSDR ACTIVE SON DSD 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 27525 & no Sb/Br) UCC27525DSDT ACTIVE SON DSD 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 27525 & no Sb/Br) UCC27526DSDR ACTIVE SON DSD 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 SCB & no Sb/Br) UCC27526DSDT ACTIVE SON DSD 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 140 SCB & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC27523DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27523DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27523DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27523DSDT SON DSD 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27524DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27524DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27524DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27524DSDT SON DSD 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27525DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27525DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27525DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27525DSDT SON DSD 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27526DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27526DSDT SON DSD 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC27523DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 UCC27523DR SOIC D 8 2500 367.0 367.0 35.0 UCC27523DSDR SON DSD 8 3000 367.0 367.0 35.0 UCC27523DSDT SON DSD 8 250 210.0 185.0 35.0 UCC27524DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 UCC27524DR SOIC D 8 2500 367.0 367.0 35.0 UCC27524DSDR SON DSD 8 3000 367.0 367.0 35.0 UCC27524DSDT SON DSD 8 250 210.0 185.0 35.0 UCC27525DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 UCC27525DR SOIC D 8 2500 367.0 367.0 35.0 UCC27525DSDR SON DSD 8 3000 367.0 367.0 35.0 UCC27525DSDT SON DSD 8 250 210.0 185.0 35.0 UCC27526DSDR SON DSD 8 3000 367.0 367.0 35.0 UCC27526DSDT SON DSD 8 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 2.15 1.95 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.846 TYPICAL 1.646 4225480/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.846) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (2.15) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225480/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.846) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (2.15) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.06 X 2.40 0.125 1.846 X 2.15 (SHOWN) 0.15 1.69 X 1.96 0.175 1.56 X 1.82 4225480/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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