Product Sample & Technical Tools & Support & Folder Buy Documents Software Community UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 UCC2751x Single-Channel, High-Speed, Low-Side Gate Driver (With 4-A Peak Source and 8-A Peak Sink) 1 Features 1 • Low-CostGate-DriverDeviceOfferingSuperior • 6-PinDBV(SOT-23)and6-PinDRS(3-mm× ReplacementofNPNandPNPDiscreteSolutions 3-mmWSONWithExposedThermalPad) • 4-APeakSourceand8-APeakSink PackageOptions AsymmetricalDrive 2 Applications • StrongSinkCurrentOffersEnhancedImmunity AgainstMillerTurnon • Switched-ModePowerSupplies • SplitOutputConfiguration(AllowsEasyand • DC-to-DCConverters IndependentAdjustmentofTurnonandTurnoff • CompanionGate-DriverDevicesforDigitalPower Speeds)intheUCC27511Saves1Diode Controllers • FastPropagationDelays(13-nsTypical) • SolarPower,MotorControl,UPS • FastRiseandFallTimes(9-nsand7-nsTypical) • GateDriverforEmergingWideBand-GapPower • 4.5-Vto18-VSingleSupplyRange Devices(suchasGaN) • OutputsHeldLowDuringVDDUVLO(Ensures 3 Description Glitch-FreeOperationatPowerUpandPower Down) The UCC27511 and UCC27512 single-channel, high- speed, low-side gate-driver device can effectively • TTLandCMOSCompatibleInput-LogicThreshold drive MOSFET and IGBT power switches. Using a (IndependentofSupplyVoltage) design that inherently minimizes shoot-through • Hysteretic-LogicThresholdsforHigh-Noise current, UCC27511 and UCC27512 are capable of Immunity sourcing and sinking high peak-current pulses into • Dual-InputDesign(ChoiceofanInverting(IN– capacitive loads offering rail-to-rail drive capability Pin)orNoninverting(IN+Pin)Driver and extremely small propagation delay, typically 13 ns. Configuration) – UnusedInputPincanbeUsedforEnableor DeviceInformation(1) DisableFunction PARTNUMBER PACKAGE BODYSIZE(NOM) • OutputHeldLowWhenInputPinsAreFloating UCC27511 SOT-23(6) 2.90mmx1.60mm • InputPinAbsoluteMaximumVoltageLevelsNot UCC27512 WSON(6) 3.00mmx3.00mm RestrictedbyVDDPinBiasSupplyVoltage (1) For all available packages, see the orderable addendum at • OperatingTemperatureRangeof–40°Cto140°C theendofthedatasheet. TypicalApplicationDiagrams Noninverting Input Noninverting Input V+ VSOURCE VSOURCE 4.5V to18V C2 L1 L1 UCC27511 UCC27512 D1 D1 IN+ 6 IN+ VDD 1 VOUT IN+ 1 IN+ IN- 6 VOUT R1 Q1 Q1 5 IN- OUTH 2 2 GND GND 5 R2 + C1 4.5V to18V R3 + C1 4 GND OUTL 3 V+ 3 VDD OUT 4 C2 Inverting Input Inverting Input V+ VSOURCE VSOURCE C2 4.5V to18V 6 IN+UCC27511VDD 1 L1 D1 VOUT 1 IN+UCC27512IN- 6 IN- L1 D1 IN- 54 IGNN-D OOUUTTHL 23 RR12 Q1 + C1 4.V5+V to18V 23 GVDNDD GONUDT 54 R3 Q1 + C1 C2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9.2 FunctionalBlockDiagram.......................................15 2 Applications........................................................... 1 9.3 FeatureDescription.................................................16 3 Description............................................................. 1 9.4 DeviceFunctionalModes........................................21 4 RevisionHistory..................................................... 2 10 ApplicationandImplementation........................ 22 10.1 ApplicationInformation..........................................22 5 Description(Continued)........................................ 4 10.2 TypicalApplication................................................22 6 UCC2751xProductFamily.................................... 4 11 PowerSupplyRecommendations..................... 27 7 PinConfigurationandFunctions......................... 5 12 Layout................................................................... 27 8 Specifications......................................................... 7 12.1 LayoutGuidelines.................................................27 8.1 AbsoluteMaximumRatings......................................7 12.2 LayoutExample....................................................28 8.2 HandlingRatings.......................................................7 13 DeviceandDocumentationSupport................. 29 8.3 RecommendedOperatingConditions.......................7 13.1 RelatedLinks........................................................29 8.4 ThermalInformation..................................................8 13.2 Trademarks...........................................................29 8.5 ElectricalCharacteristics...........................................9 13.3 ElectrostaticDischargeCaution............................29 8.6 SwitchingCharacteristics........................................10 13.4 Glossary................................................................29 8.7 TypicalCharacteristics............................................12 14 Mechanical,Packaging,andOrderable 9 DetailedDescription............................................ 15 Information........................................................... 29 9.1 Overview.................................................................15 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionE(December2013)toRevisionF Page • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................................................................... 1 ChangesfromRevisionD(May2013)toRevisionE Page • ChangedOUTLintheABSMaxRatingstabletoshowDCandRepetitivepulsevalues..................................................... 7 ChangesfromRevisionC(June2012)toRevisionD Page • Added0.05toP equationinthePowerDissipationsection............................................................................................ 26 SW ChangesfromRevisionB(March,2012)toRevisionC Page • AddedUCC27512devicethroughout. ................................................................................................................................... 1 • Added6-PinDRSpackagefeature........................................................................................................................................ 1 • AddedDRSpinoutfortheUCC27512.................................................................................................................................... 5 • AddedUCC27512TERMINALFUNCTIONStable................................................................................................................ 6 • AddedOUTvoltageabmaxratingsfortheUCC27512......................................................................................................... 7 • Added (1)................................................................................................................................................................................. 7 • ChangedESDratingsofHumanBodyModel,HBMfrom2000Vto4000V........................................................................ 7 • ChangedESDratingsofChargedDeviceModel,CDMSOT-23from500Vto1000V........................................................ 7 • AddedUCC27512ThermalInformation................................................................................................................................. 8 • AddedpowerdissipationconditionsnotetoThermalInformationsection............................................................................. 8 • AddedUCC27512FunctionalBlockDiagram...................................................................................................................... 16 (1) Valuesareverifiedbycharacterizationonbench. 2 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 • AddedUCC27512applicationdiagrams.............................................................................................................................. 22 • AddedTypicalApplicationDiagramnote.............................................................................................................................. 23 • AddedPCBlayoutbullet....................................................................................................................................................... 28 Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com 5 Description (Continued) UCC27511 features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and noninverting (IN+ pin) configuration with the same device. Either IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when input pins are in floating condition. Hence the unused input pin is not left floating and must be properly biased to ensure that driveroutputisinenabledfornormaloperation. The input pin threshold of the UCC27511 device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the V supply voltage. Wide hysteresis between the high and low thresholds offers DD excellentnoiseimmunity. The UCC27511 and UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turnon effect. The UCC27511 device also features a unique split output configuration where the gate-drive current is sourced through OUTH pin and sunk through OUTL pin. This unique pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switchingslewrates. UCC27511 and UCC27512 are designed to operate over a wide V range of 4.5 to 18 V and wide temperature DD range of –40°C to 140°C. Internal Undervoltage Lockout (UVLO) circuitry on V pin holds output low outside DD V operating range. The capability to operate at low voltage levels such as below 5 V, along with best-in-class DD switching characteristics, is especially suited for driving emerging wide band-gap power-switching devices such asGaNpower-semiconductordevices. 6 UCC2751x Product Family The UCC2751x family of gate-driver products (Table 1) represent Texas Instruments’ latest generation of single- channel low-side high-speed gate-driver devices featuring high-source/sink current capability, industry best-in- class switching characteristics and a host of other features (Table 2) all of which combine to ensure efficient, robustandreliableoperationinhigh-frequencyswitchingpowercircuits. Table1.UCC2751xProductFamilySummary PARTNUMBER PACKAGE PEAKCURRENT INPUTTHRESHOLDLOGIC (SOURCE/SINK) UCC27511DBV SOT-23,6pin 4-A/8-A UCC27512DRS 3-mmx3-mmWSON,6pin (AsymmetricalDrive) CMOS/TTL-Compatible (lowvoltage,independentofVDD UCC27516DRS (1) 3-mmx3-mmWSON,6pin biasvoltage) UCC27517DBV (1) SOT-23,5pin 4-A/4-A UCC27518DBV (1) SOT-23,5pin (SymmetricalDrive) CMOS UCC27519DBV (1) SOT-23,5pin (followsVDDbiasvoltage) (1) Visitwww.ti.comforthelatestproductdatasheet. Table2.UCC2751xFeaturesandBenefits FEATURE BENEFIT HighSourceandSinkCurrentCapability HighcurrentcapabilityoffersflexibilityinemployingUCC2751x 4Aand8A(Asymmetrical)–UCC2751/6/7/8/9 familyofdevicestodriveavarietyofpowerswitchingdevicesat 4Aand4A(Symmetrical)–UCC27511andUCC27512 varyingspeeds Best-in-class13-ns(typ)Propagationdelay Extremelylowpulse-transmissiondistortion ExpandedVDDOperatingrangeof4.5Vto18V Flexibilityinsystemdesign ExpandedOperatingTemperaturerangeof–40°Cto140°C LowVDDoperationensurescompatibilitywithemergingwideband- (SeeElectricalCharacteristicstable) gappowerdevicessuchasGaN OutputsareheldlowinUVLOcondition,whichensurespredictable VDDUVLOProtection glitch-freeoperationatpowerupandpowerdown Safetyfeature,especiallyusefulinpassingabnormalconditiontests Outputsheldlowwheninputpins(INx)infloatingcondition duringsafetycertification 4 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 Table2.UCC2751xFeaturesandBenefits(continued) FEATURE BENEFIT Abilityofinputpins(andenablepininUCC27518/9)tohandle Systemsimplification,especiallyrelatedtoauxiliarybiassupply voltagelevelsnotrestrictedbyVDDpinbiasvoltage architecture SplitoutputstructureinUCC27511(OUTH,OUTL) Allowsindependentoptimizationofturnonandturnoffspeeds Strongsinkcurrent(8A)andlowpulldownimpedance(0.375Ω)in HighimmunitytoCxdV/dtMillerturnonevents UCC27511andUCC27512 Enhancednoiseimmunity,whileretainingcompatibilitywith CMOS/TTLcompatibleinput-thresholdlogicwithwidehysteresisin microcontrollerlogic-levelinputsignals(3.3V,5V)optimizedfor UCC27511,UCC27512,UCC27516andUCC27517 digitalpower CMOSinputthresholdlogicinUCC27518/9(VIN_H–70%VDD, Wellsuitedforslowinput-voltagesignals,withflexibilitytoprogram VIN_L–30%VDD) delaycircuits(RCD) 7 Pin Configuration and Functions 6-Pins DBVPackage (TopView) VVDDDD 11 66 IINN++ OOUUTTHH 22 55 IINN-- OOUUTTLL 33 44 GGNNDD 6-Pins DRS Package (Top View) IN+ 1 6 IN- GND 2 5 GND VDD 3 4 OUT Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com PinFunctions-UCC27511 PIN I/O DESCRIPTION NO. NAME 1 VDD I Biassupplyinput. Sourcingcurrentoutputofdriver.ConnectresistorbetweenOUTHandGateof 2 OUTH O power-switchingdevicetoadjustturnonspeed. Sinkingcurrentoutputofdriver.ConnectresistorbetweenOUTLandGateof 3 OUTL O power-switchingdevicetoadjustturnoffspeed. 4 GND - Ground:Allsignalsreferencedtothispin. Invertinginput:Whenthedriverisusedinnoninvertingconfiguration,connectIN-to 5 IN- I GNDinordertoenableoutput,OUTheldLOWifIN-isunbiasedorfloating Noninvertinginput:Whenthedriverisusedininvertingconfiguration,connectIN+ 6 IN+ I toVDDinordertoenableoutput,OUTheldLOWifIN+isunbiasedorfloating PinFunctions-UCC27512 PIN I/O DESCRIPTION NO. NAME 1 IN+ I Noninvertinginput:Whenthedriverisusedininvertingconfiguration,connectIN+ toVDDinordertoenableoutput,OUTheldLOWifIN+isunbiasedorfloating. 2,5 GND - Ground:Allsignalsreferencedtothispin.TIrecommendstoconnectpin2andpin5 onPCBasclosetothedeviceaspossible. 3 VDD I Biassupplyinput. 4 OUT O Sourcing/sinkingcurrentoutputofdriver. 6 IN- I Invertinginput:Whenthedriverisusedinnoninvertingconfiguration,connectIN-to GNDinordertoenableoutput,OUTheldLOWifIN-isunbiasedorfloating. 6 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 8 Specifications 8.1 Absolute Maximum Ratings(1)(2)(3) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Supplyvoltagerange VDD –0.3 20 OUTHvoltage,(UCC27511) –0.3 VDD+0.3 DC –0.3 20 OUTLvoltage,(UCC27511) V Repetitivepulselessthan200ns(4) –2 20 DC –0.3 VDD+0.3 OUTvoltage,(UCC27512) Repetitivepulselessthan200ns(4) –2 VDD+0.3 Outputcontinuouscurrent IOUT_DC(source) 0.3 (OUTHsourcecurrentandOUTLsinkcurrent) I (sink) 0.6 OUT_DC A Outputpulsedcurrent(0.5µs) IOUT_pulsed(source) 4 (OUTHsourcecurrentandOUTLsinkcurrent) I (sink) 8 OUT_pulsed IN+,IN–(5) –0.3 20 V Soldering,10sec. 300 Leadtemperature °C Reflow 260 (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoGNDunlessotherwisenoted.Currentsarepositiveintoandnegativeoutofthespecifiedterminal.See PackagingSectionofthedatasheetforthermallimitationsandconsiderationsofpackages. (3) Thesedevicesaresensitivetoelectrostaticdischarge;followproperdevicehandlingprocedures. (4) Valuesareverifiedbycharacterizationonbench. (5) MaximumvoltageoninputpinsisnotrestrictedbythevoltageontheVDDpin. 8.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all pins(1) –4000 4000 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecification JESD22-C101,allpins(2) –1000 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 8.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT Supplyvoltagerange,VDD 4.5 12 18 V Operatingjunctiontemperaturerange –40 140 °C Inputvoltage,IN+andIN- 0 18 V Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com 8.4 Thermal Information UCC27511 UCC27512 THERMALMETRIC DBV WSON(1) UNIT 6PINS 6PINS θ Junction-to-ambientthermalresistance(2) 217.8 85.6 JA θ Junction-to-case(top)thermalresistance(3) 97.6 100.1 JCtop θ Junction-to-boardthermalresistance(4) 72.2 58.6 JB °C/W ψ Junction-to-topcharacterizationparameter(5) 8.6 7.5 JT ψ Junction-to-boardcharacterizationparameter(6) 71.6 58.7 JB θ Junction-to-case(bottom)thermalresistance(7) n/a 23.7 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,high-Kboard,as specifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a. (3) Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.NospecificJEDEC- standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. (4) Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCB temperature,asdescribedinJESD51-8. (5) Thejunction-to-topcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted JT fromthesimulationdataforobtainingR ,usingaproceduredescribedinJESD51-2a(sections6and7). θJA (6) Thejunction-to-boardcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted JB fromthesimulationdataforobtainingR ,usingaproceduredescribedinJESD51-2a(sections6and7). θJA (7) Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.Nospecific JEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88. Spacer NOTE Under identical power dissipation conditions, the DRS package will allow to maintain a lower die temperature than the DBV. θ metric should be used for comparison of power JA dissipationcapabilitybetweendifferentpackages(RefertothePowerDissipationSection). 8 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 8.5 Electrical Characteristics V =12V,T =T =–40°Cto140°C,1-µFcapacitorfromV toGND.Currentsarepositiveinto,negativeoutofthe DD A J DD specifiedterminal. PARAMETER TESTCONDITION MIN TYP MAX UNIT BIASCURRENTS IN+=VDD,IN–=GND 40 100 160 I Startupcurrent VDD=3.4V IN+=IN–=GNDorIN+=IN–=VDD 25 75 145 µA DD(off) IN+=GND,IN–=VDD 20 60 115 UNDERVOLTAGELOCKOUT(UVLO) T =25°C 3.91 4.20 4.5 A V Supplystartthreshold ON T =–40°Cto140°C 3.70 4.20 4.65 A Minimumoperating V V 3.45 3.9 4.35 OFF voltageaftersupplystart V Supplyvoltagehysteresis 0.2 0.3 0.5 DD_H INPUTS(IN+,IN-) Inputsignalhigh OutputhighforIN+pin, V 2.2 2.4 IN_H threshold OutputlowforIN–pin OutputlowforIN+pin, V V Inputsignallowthreshold 1.0 1.2 IN_L OutputhighforIN–pin V Inputsignalhysteresis 1.0 IN_HYS SOURCE/SINKCURRENT Source/sinkpeak ISRC/SNK current(1) CLOAD=0.22µF,FSW=1kHz -4/+8 A OUTPUTS(OUTH,OUTL,OUT) VDD=12V 50 90 VDD- Highoutputvoltage IOUTH=-10mA VOH VDD=4.5V 60 130 I =-10mA OUTH mV VDD=12 5 6.5 I =10mA OUTL V Lowoutputvoltage OL VDD=4.5V 5.5 10 I =10mA OUTL VDD=12V 5.0 7.5 Outputpull-up IOUTH=-10mA ROH resistance(2) VDD=4.5V 5.0 11.0 I =-10mA OUTH Ω VDD=12V 0.375 0.650 Outputpull-down IOUTL=10mA R OL resistance VDD=4.5V 0.45 0.750 I =10mA OUTL (1) EnsuredbyDesign. (2) R representson-resistanceofP-ChannelMOSFETinpullupstructureoftheoutputstageoftheUCC27511andUCC27512. OH Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com 8.6 Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT VDD=12V C =1.8nF,connectedtoOUTH 8 12 LOAD t Risetime(1) andOUTLpinstiedtogether R VDD=4.5V 16 22 C =1.8nF LOAD VDD=12V C =1.8nF,connectedtoOUTH 7 11 LOAD t Falltime(1) andOUTLpinstiedtogether F VDD=4.5V 7 11 C =1.8nF LOAD VDD=12V 5-VinputpulseCLOAD=1.8nF, 4 13 23 ns connectedtoOUTHandOUTLpins tiedtogether t IN+tooutputpropagationdelay(1) D1 VDD=4.5V 5-VinputpulseC =1.8nF, LOAD 4 15 26 connectedtoOUTHandOUTLpins tiedtogether VDD=12V C =1.8nF,connectedtoOUTH 4 13 23 LOAD andOUTLpinstiedtogether t IN-tooutputpropagationdelay(1) D2 VDD=4.5V C =1.8nF,connectedtoOUTH 4 19 30 LOAD andOUTLpinstiedtogether (1) SeetimingdiagramsinFigure1,Figure2,Figure3andFigure4. HHiigghh IINNPPUUTT ((IINN++ ppiinn)) LLooww HHiigghh IINN--ppiinn LLooww 9900%% OOUUTTPPUUTT 1100%% tt tt tt tt DD11 rr DD11 ff (PWMInputtoIN+Pin(IN–PinTiedtoGND),OutputRepresentsOUTHAndOUTLPinsTiedTogetherinthe UCC27511) Figure1. NoninvertingConfiguration 10 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 HHiigghh IINNPPUUTT ((IINN--ppiinn)) LLooww HHiigghh IINN++ ppiinn LLooww 9900%% OOUUTTPPUUTT 1100%% tt tt tt tt DD22 ff DD22 rr (PWMInputtoIN–Pin(IN+PinTiedtoVDD),OutputRepresentsOUTHandOUTLPinsTiedTogetherinthe UCC27511) Figure2. InvertingConfiguration HHiigghh IINNPPUUTT ((IINN--ppiinn)) LLooww HHiigghh EENNAABBLLEE ((IINN++ ppiinn)) LLooww 9900%% OOUUTTPPUUTT 1100%% tt tt tt tt DD11 rr DD11 ff (EnableandDisableSignalAppliedtoIN+Pin,PWMInputtoIN–Pin,OutputRepresentsOUTHandOUTLPinsTied TogetherintheUCC27511) Figure3. EnableandDisableFunctionUsingIN+Pin HHiigghh IINNPPUUTT ((IINN++ ppiinn)) LLooww HHiigghh EENNAABBLLEE ((IINN--ppiinn)) LLooww 9900%% OOUUTTPPUUTT 1100%% tt tt tt tt DD22 ff DD22 rr (EnableandDisableSignalAppliedtoIN–Pin,PWMInputToIN+Pin,OutputRepresentsOUTHandOUTLPins TiedTogetherintheUCC27511) Figure4. EnableandDisableFunctionUsingIN– Pin Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com 8.7 Typical Characteristics 0.12 4 IN+=Low,IN−=Low 0.11 IN+=High, IN−=Low A) 0.1 3.5 m up Current ( 00..0089 IDD (mA) 3 VDD = 12 V Start 0.07 2.5 fCswLo =ad 5 =0 05 0k0H pzF 0.06 VDD = 3.4 V 0.05 2 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G001 G013 Figure5.Start-UpCurrentvsTemperature Figure6.OperatingSupplyCurrentvsTemperature(Output Switching) 0.5 4.6 IN+=Low,IN−=Low UVLO Rising A) IN+=High, IN−=Low UVLO Falling m 4.4 nt ( 0.4 V) Curre hold ( 4.2 pply 0.3 hres g Su LO T 4 n V ati 0.2 U er 3.8 p O VDD = 12 V 0.1 3.6 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G002 G003 Figure7.SupplyCurrentvsTemperature(OutputInDC Figure8.UVLOThresholdVoltagevsTemperature On/OffCondition) 3.5 8 Turn−On VDD = 12 V RoH Turn−Off CLoad = 1.8 nF ) hreshold (V) 2.53 WUp Resistance ( 67 ut T 2 ull− p P In ut 5 1.5 utp VDD = 12 V O Iout = 10 mA 1 4 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G014 G004 Figure9.InputThresholdvsTemperature Figure10.OutputPullupResistancevsTemperature 12 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 Typical Characteristics (continued) 0.8 8 We () 0.7 ROL VCDLoDa =d =1 21 .V8 nF nc 7 a Down Resist 0.5 e Time (ns) 6 Pull− 0.3 Ris put VDD = 12 V 5 Out Iout = 10 mA 0.1 4 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G005 G000 Figure11.OutputPulldownResistancevsTemperature Figure12.RiseTimevsTemperature 10 20 VDD = 12 V Turn−On CLoad = 1.8 nF Turn−Off 9 s) n e (ns) Delay ( 15 m 8 n all Ti gatio F pa 10 o 7 Pr VDD = 12 V 6 5 −50 0 50 100 150 −50 0 50 100 150 Temperature (°C) Temperature (°C) G000 G006 Figure13.FallTimevsTemperature Figure14.InputtoOutputPropagationDelayvs Temperature 20 20 VDD=4.5V 18 VDD=12V 18 16 VDD=15V nt (mA) 1124 elay (ns) 1146 e D Supply Curr 1680 Propagation 1102 4 2 CLoad = 1.8 nF 8 Turn−On Turn−Off 0 6 0 100 200 300 400 500 600 700 0 4 8 12 16 20 Frequency (kHz) Supply Voltage (V) G010 G007 Figure15.OperatingSupplyCurrentvsFrequency Figure16.PropagationDelaysvsSupplyVoltage Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Typical Characteristics (continued) 20 10 8 me (ns) 15 me (ns) 6 Rise Ti 10 Fall Ti 4 5 2 0 4 8 12 16 20 0 4 8 12 16 20 Supply Voltage (V) Supply Voltage (V) G008 G009 Figure17.RiseTimevsSupplyVoltage Figure18.FallTimevsSupplyVoltage 14 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 9 Detailed Description 9.1 Overview The UCC27511/2 single-channel high-speed low-side gate-driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC27511 device is capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail- to-raildrivecapabilityandextremelysmallpropagationdelayof13ns(typical). The UCC27511 device provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turnon effect. The UCC27511 device also features a unique split output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This unique pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins (respectively) and easily control the switching slew rates. Alternatively the OUTH and OUTL pins can be tied together, which results in a typical gate driver output configuration where the source and sink currents are delivered from the same pin. In case of UCC27511 device, the state of the device's output is simply determined by the combined states of the OUTH and OUTL pins when tiedtogether.OutputhighimpliesthatOUTHpinispulledclosetoV pinbiasvoltagewhileOUTLpinisinhigh- DD impedance state. Similarly output low implies that OUTL pin is pulled close to the GND pin while OUTH pin is in high-impedancestate.OUTHpulledtoVDD,whileOUTLpulledtoGNDpinsimultaneouslyisnotavalidstatefor thedevice. The UCC27511 device is designed to operate over a wide V range of 4.5 to 18 V and wide temperature range DD of –40°C to 140°C. Internal undervoltage lockout (UVLO) circuitry on the V pin holds the output low outside DD V operating range. The capability to operate at low voltage levels, such as below 5 V, along with best-in-class DD switching characteristics, is especially suited for driving emerging wide band-gap power-switching devices such asGaNpower-semiconductordevices. The UCC27511 device features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and noninverting (IN+ pin) configuration with the same device. Either the IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For system robustness, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when the input pins are in floating condition. Therefore the unused input pin is not left floating and must be properlybiasedtoensurethatdriveroutputisinenabledfornormaloperation. The input pin threshold of the UCC27511A-Q1 device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the V supply voltage. Wide hysteresis between the high and low thresholds DD offersexcellentnoiseimmunity. 9.2 Functional Block Diagram VDD IN+ 6 1 VDD VDD 230kW 200kW IN- 5 2 OUTH VDD GND 4 UVLO 3 OUTL Figure19. UCC27511FunctionalBlockDiagram Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Functional Block Diagram (continued) VDD IN+ 1 3 VDD VDD 230kW 200kW IN- 6 4 OUT VDD GND 2 UVLO 5 GND Figure20. UCC27512FunctionalBlockDiagram 9.3 Feature Description In the following sections with respect to UCC27511, the term output, or OUT refers to the combined state that results when the OUTH pin is tied directly to the OUTL pin. As stated earlier, output high, or OUT high refers to the state when the OUTH pin is pulled close to V pin bias voltage while the OUTL pin is in high-impedance DD state. Similarly output low or OUT low implies that the OUTL pin is pulled close to the GND pin while the OUTH pinisinhigh-impedancestate. 9.3.1 V andUndervoltageLockout DD The UCC27511 and UCC27512 devices have internal Undervoltage LockOut (UVLO) protection feature on the V pin supply circuit blocks. Whenever the driver is in UVLO condition (for example when V voltage less than DD DD V during power up and when V voltage is less than V during power down), this circuit holds all outputs ON DD OFF LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis prevents chatter when low V supply voltages have noise from the power supply and also when DD there are droops in the V bias voltage when the system commences switching and there is a sudden increase DD in I . The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching DD characteristics,isespeciallysuitedfordrivingemergingGaNwideband-gappower-semiconductordevices. For example, at power up, the UCC27511 and UCC27512 driver output remains LOW until the V voltage DD reaches the UVLO threshold. The magnitude of the OUT signal rises with V until steady-state V is reached. DD DD In the noninverting operation (PWM signal applied to IN+ pin) shown in Figure 21, the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN- pin) shown in Figure 22 the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that in these devices the output turns to high state only if IN+ pin is high and IN- pin is lowaftertheUVLOthresholdisreached. Since the driver draws current from the V pin to bias all internal circuits, for the best high-speed circuit DD performance, two V -bypass capacitors are recommended to prevent noise problems. The use of surface- DD mountcomponentsishighlyrecommended.A0.1-μFceramiccapacitorshouldbelocatedascloseaspossibleto the V to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR DD should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors should present a low impedance characteristic for the expected currentlevelsandswitchingfrequenciesintheapplication. 16 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 Feature Description (continued) VVDDDD VVDDDD TThhrreesshhoolldd VVDDDD TThhrreesshhoolldd IINN-- IINN++ IINN++ IINN-- OOUUTT OOUUTT Figure21.Powerup(NoninvertingDrive) Figure22.Powerup(InvertingDrive) 9.3.2 OperatingSupplyCurrent The UCC27511 and UCC27512 feature very low quiescent I currents. The typical operating-supply current in DD Undervoltage LockOut (UVLO) state and fully-on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and Figure 7. The I current when the device is fully on and outputs are in a static state (DC DD high or DC low, refer Figure 7) represents lowest quiescent I current when all the internal logic circuits of the DD device are fully operational. The total supply current is the sum of the quiescent I current, the average I DD OUT current due to switching, and finally any current related to pullup resistors on the unused input pin. For example, when the inverting input pin is pulled low additional current is drawn from V supply through the pullup resistors DD (refer to for the device Block Diagram). Knowing the operating frequency (f ) and the MOSFET gate (Q ) SW G chargeatthedrivevoltagebeingused,theaverageI currentcanbecalculatedasproductofQ andf . OUT G SW A complete characterization of the IDD current as a function of switching frequency at different V bias voltages DD under 1.8-nF switching load is provided in Figure 15. The strikingly linear variation and close correlation with theoretical value of average I indicates negligible shoot-through inside the gate-driver device attesting to its OUT high-speedcharacteristics. 9.3.3 InputStage The input pins of the UCC27511 and UCC27512 devices are based on a TTL and CMOS compatible input- threshold logic that is independent of the V supply voltage. With a typicalyl high threshold of 2.2 V and a DD typically low threshold of 1.2 V, the logic-level thresholds can be conveniently driven with PWM control signals derived from 3.3-V and 5-V digital-power controllers. Wider hysteresis (1 V typical) offers enhanced noise immunity compared to traditional TTL-logic implementations, where the hysteresis is typically less than 0.5 V. This device also feature tight control of the input-pin threshold-voltage levels which eases system design considerations and ensures stable operation across temperature. The very-low input capacitance on these pins reducesloadingandincreasesswitchingspeed. Whenever any of the input pins are in a floating condition, the output of the respective channel is held in the low state. This function is achieved using V -pullup resistors on all the inverting inputs (IN– pin) or GND-pulldown DD resistorsonallthenoninvertinginputpins(IN+pin),(seethe). The device also features a dual-input configuration with two input pins available to control the state of the output. The user has the flexibility to drive the device using either a noninverting input pin (IN+) or an inverting input pin (IN–). The state of the output pin is dependent on the bias on both the IN+ and IN– pins. For additional clarification, refer to the I/O-logic truth table (Table 3) and the typical application diagrams, (Figure 25 and Figure26). When an input pin is selected for PWM drive, the other input pin (the unused input pin) must be properly biased in order to enable the output. As previously stated, the unused input pin cannot remain in a floating condition because whenever any input pin is left in a floating condition the output is disabled. Alternatively, the unused inputpincaneffectivelybeusedtoimplementanenableordisablefunction.Thefollowingexplainsthisfunction: • In order to drive the device in a noninverting configuration, apply the PWM-control input signal to IN+ pin. In thiscase,theunusedinputpin,IN–,mustbebiasedlow(suchastiedtoGND)inordertoenabletheoutput. – Alternately, the IN– pin is used to implement the enable or disable function using an external logic signal. Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) OUTisdisabledwhenIN– isbiasedhighandOUTisenabledwhenIN–isbiasedlow. • In order to drive the device in an inverting configuration, apply the PWM-control input signal to IN– pin. In this case,the unusedinputpin,IN+,mustbebiasedhigh(suchastiedtoV )inordertoenabletheoutput. DD – Alternately, the IN+ pin is used to implement the enable or disable function using an external logic signal. OUTisdisabledwhenIN+isbiasedlowandOUTisenabledwhenIN+isbiasedhigh. • Finally, note that the output pin can be driven into a high state only when the IN+ pin is biased high and the IN–inputisbiasedlow. The input stage of the driver is preferably driven by a signal with a short rise or fall time. Use caution whenever the driver is used with slowly varying input signals, especially in situations where the device is located in a mechanicalsocketorPCBlayoutthatisnotoptimal: • High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. The differential voltage between input pins and GND is modified and triggers an unintended change of output state because of fast 13-ns propagation delay which can ultimately result in high-frequency oscillations that increasepowerdissipationandposeariskofdamagetothedevice. • A1-Vinput-thresholdhysteresisboostsnoiseimmunitycomparedtomostotherindustrystandarddrivers. • Intheworstcase,whenaslowinputsignalisusedandPCBlayoutisnotoptimal,addingasmallcapacitor(1 nF) between the input pin and GND pin very close to the driver device may be necessary which helps to convert the differential mode noise with respect to the input-logic circuitry into common-mode noise and avoid unintendedchangeofoutputstate. If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly recommended between the output of the driver and the power device instead of adding delays on the input signal. This external resistor has the additional benefit of reducing part of the gate-charge related power dissipationinthegate-driverdevicepackageandtransferringthepowerdissipationintotheexternalresistor. 9.3.4 EnableFunction As mentioned earlier, an enable and disable function is easily implemented in UCC27511 and UCC27512 devices using the unused input pin. When the IN+ pin is pulled down to GND or the IN– pin is pulled down to V , the output is disabled. Thus the IN+ pin can be used like an enable pin that is based on active-high logic, DD whiletheIN– pincanbeusedlikeanenablepinthatisbasedonactive-lowlogic. 9.3.5 OutputStage Figure 23 shows the output stage of the UCC27511 and UCC27512 devices. The UCC27511 and UCC27512 devices feature a unique architecture on the output stage which delivers the highest peak-source current when the peak source current is most needed during the Miller plateau region of the power switch turnon transition (when the power-switch drain or collector voltage experiences dV/dt). The device output stage features a hybrid pullupstructureusingaparallelarrangementofN-channelandP-channelMOSFETdevices.ByturningontheN- channel MOSFET during a narrow instant when the output changes state from low to high, the gate-driver device isabletodeliverabriefboostinthepeak-sourcingcurrentenablingfastturnon. 18 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 Feature Description (continued) VDD RO(H) Pullup R(NMOS) Gate voltage OUTH Inputsignal Antishoot- boost through OUTL circuitry Narrowpulseat eachturnon RO(L) Figure23. UCC27511GateDriverOutputStructure The R parameter (see the Electrical Characteristics table) is a DC measurement and is representative of the O(H) on-resistance of the P-channel device only, because the N-Channel device is turned on only during output changeofstatefromlowtohigh.Thustheeffectiveresistanceofthehybridpullupstageismuchlowerthanwhat is represented by R parameter. The pulldown structure is composed of a N-channel MOSFET only. The R O(H) O(L) parameter (see the Electrical Characteristics table), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In the UCC27511 and UCC27512 devices, the effective resistanceofthehybridpullupstructureisapproximately2.7× R . O(L) The UCC27511 device features a unique split output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This unique pin arrangement allows users to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the turnon and turnoff switching dV/dt. This pin arrangement, along with the low pulldown impedance of the output driver stage, is especially useful in applications where a high C × dV/dt Miller turnon immunity is needed (such as with GaN power switches, SR MOSFETs and other applications) and the OUTL pin can be directly tied to the gate of thepowerdevice. The UCC27511 and UCC27512 devices are capable of delivering 4-A source, 8-A sink (asymmetrical drive) at V equal to 12 V. Strong sink capability in asymmetrical drive results in a very-low pulldown impedance in the DD driver output stage which boosts immunity against parasitic, Miller turnon (C × dV/dt turnon) effect, especially wherethelowgate-chargeMOSFETsoremergingwideband-gapGaN-powerswitchesareused. An example of a situation where the Miller turnon effect is a concern is synchronous rectification (SR). In an SR application, the dV/dt occurs on the MOSFET drain when the MOSFET is already held in off state by the gate driver. The current discharging the C Miller capacitance during this dV/dt is shunted by the pulldown stage of (GD) the driver. If the pulldown impedance is not low enough then a voltage spike can result in the V of the GS MOSFET, which can result in spurious turnon. This phenomenon is shown in Figure 24. The UCC27511 and UCC27512 device offers a best-in-class, 0.375-Ω (typ) pulldown impedance boosting immunity against Miller turnon. Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) VDS (ofMOSFET) MillerTurnonSpikeinVGS GateDriver C(GD) RG VGSof VTH MOSFET I(SNK) C(OSS) ON OFF OUTL C(GS) VI RO(L) VDSof MOSFET Figure24. Very-LowPulldownImpedanceinUCC27511andUCC27512,4-Aand8-AAsymmetricalDrive (OutputStageMitigatesMillerTurnonEffect) The driver-output voltage swings between the V and GND pins which provides rail-to-rail operation as a result DD of the MOS-output stage which delivers very-low dropout. The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots. In many cases, external Schottky diode clamps are eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damagetothedeviceorlogicmalfunction. 9.3.6 LowPropagationDelays The UCC27511 and UCC27512 driver devices feature best-in-class input-to-output propagation delay of 13 ns (typ) at V = 12 V, which promises the lowest level of pulse transmission distortion available from industry- DD standard gate-driver devices for high-frequency switching applications. As seen in Figure 14, there is very little variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns propagationdelaysacrosstheentirerangeofapplicationconditions. 20 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 9.4 Device Functional Modes The device operates in normal mode and UVLO mode. See the V and Undervoltage Lockout section for DD informationonUVLOoperationmode.InthenormalmodetheoutputstateisdependentonstatesoftheIN+and IN–pins.Table3 liststheoutputstatesfordifferentinputpincombinations. Table3.DeviceLogicTable OUT (OUTHandOUTLpins IN+PIN IN-PIN OUTHPIN OUTLPIN tiedtogetherinthe UCC27511) L L Highimpedance L L L H Highimpedance L L H L H Highimpedance H H H Highimpedance L L x(1) Any Highimpedance L L Any x(1) Highimpedance L L (1) x=FloatingCondition Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information High-current gate-driver devices are required in switching-power applications for a variety of reasons. In order to effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver employs between the PWM output of controllers and the gates of the power-semiconductor devices. Further, gate drivers are indispensable when having the PWM controller directly drive the gates of the switching devices isimpossible.Withadventofdigitalpower,thissituationwillbeoftenencounteredsincethePWMsignalfromthe digitalcontrollerisoftena3.3-Vlogicsignalwhichisnotcapableofeffectivelyturningonapowerswitch.Alevel- shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power since they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses into itself. Finally, emerging wide band-gap power device technologies such as GaN based switches, which are capable of supporting very high switching frequency operation, are driving very special requirements in terms of gate drive capability. These requirements include operation at low V voltages DD (5 V or lower), low propagation delays and availability in compact, low-inductance packages with good thermal capability. In summary gate-driver devices are extremely important components in switching power combining benefitsofhigh-performancelow-costcomponentcountandboard-spacereductionandsimplifiedsystemdesign. 10.2 Typical Application Typical application diagrams of UCC27511 and UCC27512 devices are shown below illustrating use in non- inverting and inverting driver configurations. The UCC27511 device features a unique split output configuration where the gate-drive current is sourced through OUTH pin and sunk through OUTL pin. This unique pin arrangement allows user to apply independent turn-on and turn-off resistors to the OUTH and OUTL pins respectively and easily control the turn-on and turn-off switching dV/dt. This pin arrangement, along with the low pulldown impedance of the output driver stage, is especially handy in applications where a high C x dV/dt Miller turnon immunity is needed (such as with GaN power switches, SR MOSFETs, and so forth) and OUTL pin can bedirectlytiedtothegateofthepowerdevice. V+ VSOURCE VSOURCE 4.5V to18V C2 L1 L1 UCC27511 UCC27512 D1 D1 IN+ 6 IN+ VDD 1 VOUT IN+ 1 IN+ IN- 6 VOUT Q1 Q1 R1 5 IN- OUTH 2 2 GND GND 5 + 4.5V to18V + R2 C1 R3 C1 4 GND OUTL 3 V+ 3 VDD OUT 4 C2 Figure25. UsingNoninvertingInput(IN–IsGroundedtoEnableOutput) 22 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 Typical Application (continued) V+ VSOURCE VSOURCE C2 4.5V to18V L1 L1 UCC27512 UCC27511 D1 D1 1 IN+ IN- 6 IN- 6 IN+ VDD 1 VOUT Q1 R1 2 GND GND 5 Q1 IN- 5 IN- OUTH 2 4.5V to18V + + R3 R2 C1 V+ 3 VDD OUT 4 C1 4 GND OUTL 3 C2 Figure26. UsingInvertingInput(IN+IsTiedtoV EnableOutput) DD NOTE The UCC27512 features two ground pins, pin 2 and pin 5. TI recommends tying both pins togetherusingPCBtraceascloseaspossibletothedevice. 10.2.1 DesignRequirements When selecting the proper gate driver device for an end application, some design considerations must be evaluated first in order to make the most appropriate selection. Among these considerations are input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, availability of independentenableanddisablefunctions,propagationdelay,powerdissipation,andpackagetype. 10.2.2 DetailedDesignProcedure 10.2.2.1 Input-to-OutputLogic The design should specify which type of input-to-output configuration should be used. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred, then the non-inverting configuration must be selected. If turning off the power MOSFET or IGBT when the input signal is in high state is preferred, the inverting configuration must be chosen. The UCC27511 and UCC27512 devices can be configured in either an inverting or noninverting input-to-output configuration using the IN– or IN+ pins respectively. To configure the device for use in inverting mode, tie the IN+ pin to V and apply the input signal to the IN– pin. For the DD noninvertingconfiguration,tietheIN– pintoGNDandapplytheinputsignaltotheIN+pin. 10.2.2.2 InputThresholdType ThetypeofInputvoltagethresholddeterminesthetypeofcontrollerthatcanbeusedwiththegatedriverdevice. The UCC27511 and UCC27512 devices feature a TTL and CMOS-compatible input threshold logic, with wide hysteresis. The threshold voltage levels are low voltage and independent of the V supply voltage, which allows DD compatibility with both logic-level input signals from microcontrollers as well as higher-voltage input signals from analog controllers. See the Electrical Characteristics table for the actual input threshold voltage levels and hysteresisspecificationsfortheUCC27511andUCC27512devices. 10.2.2.3 V BiasSupplyVoltage DD The bias supply voltage to be applied to the V pin of the device should never exceed the values listed in the DD Recommended Operating Conditions table. However, different power switches demand different voltage levels to be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the V bias supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC27511 DD and UCC27512 devices can be used to drive a variety of power switches, such as Si MOSFETs (for example, V = 4.5 V, 10 V, 12 V), IGBTs (V = 15 V, 18 V), and wide-bandgap power semiconductors (such as GaN, GS GE certaintypesofwhichallownohigherthan6Vtobeappliedtothegateterminals). Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Typical Application (continued) 10.2.2.4 PeakSourceandSinkCurrents Generally, the switching speed of the power switch during turnon and turnoff should be as fast as possible in order to minimize switching power losses. The gate driver device must be able to provide the required peak currentforachievingthetargetedswitchingspeedsforthetargetedpowerMOSFET. Using the example of a power MOSFET, the system requirement for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dV /dt). For example, the DS system requirement might state that a SPP20N60C3 power MOSFET must be turned-on with a dV /dt of 20 DS V/ns or higher under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC-converter application. This type of application is an inductive hard-switching application and reducing switching power losses is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET turn-on event (from 400 V in the OFF state to V in on state) must be completed in approximately 20 ns or DS(on) less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (Q parameter in GD SPP20N60C3 power MOSFET data sheet = 33 nC typical) is supplied by the peak current of gate driver. According to power MOSFET inductive switching mechanism, the gate-to-source voltage of the power MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage of the powerMOSFET,V . GS(TH) In order to achieve the targeted dV /dt, the gate driver must be capable of providing the Q charge in 20 ns or DS GD less.Inotherwordsapeakcurrentof1.65A(=33nC/20ns)orhighermustbeprovidedbythegatedriver.The UCC27511 and UCC27512 gate driver is capable of providing 4-A peak sourcing current which clearly exceeds the design requirement and has the capability to meet the switching speed needed. The 2.4x overdrive capability provides an extra margin against part-to-part variations in the Q parameter of the power MOSFET along with GD additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus EMI optimizations. However, in practical designs the parasitic trace inductance in the gate drive circuit of the PCB will have a definitive role to play on the power MOSFET switching speed. The effect of this trace inductance is to limit the dI/dt of the output current pulse of the gate driver. In order to illustrate this, consider output current pulse waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle (½ × I × time) would equal the total gate charge of the power MOSFET (Q parameter in SPP20N60C3 power PEAK G MOSFETdatasheet=87nCtypical).IftheparasitictraceinductancelimitsthedI/dtthenasituationmayoccurin which the full peak current capability of the gate driver is not fully achieved in the time required to deliver the QG required for the power MOSFET switching. In other words the time parameter in the equation would dominate and the I value of the current pulse would be much less than the true peak current capability of the device, PEAK while the required QG is still delivered. Because of this, the desired switching speed may not be realized, even when theoretical calculations indicate the gate driver is capable of achieving the targeted switching speed. Thus, placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with minimalPCBtraceinductanceisimportanttorealizethefullpeak-currentcapabilityofthegatedriver. 10.2.2.5 EnableandDisableFunction Certain applications demand independent control of the output state of the driver without involving the input signal. A pin which offers an enable and disable function achieves this requirement. The UCC27511 and UCC27512 devices offer 2 input pins, IN+ and IN–, both of which control the state of the output as listed in Table 3. Based on whether an inverting or noninverting input signal is provided to the driver, the appropriate input pin can be selected as the primary input for controlling the gate driver. The other unused input pin can be conveniently used for the enable and disable functionality. If the design does not require an enable function, the unused input pin can be tied to either the V pin (in case IN+ is the unused pin), or GND (in case IN– is unused DD pin)inordertoensureitdoesnotaffecttheoutputstatus. 10.2.2.6 PropagationDelay The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC27511 and UCC27512 devices feature industry best-in-class 13-ns (typical) propagation delays which ensures very little pulse distortion and allows operation at very high-frequencies. See the table for the propagation and switching characteristics of the UCC27511andUCC27512devices. 24 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 Typical Application (continued) 10.2.2.7 ThermalInformation The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal characteristics of the package. In order for a gate driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The thermal metrics for the driver package is listed in the table. For detailed information regarding the table, please refer to the Application Note from Texas Instruments entitled IC Package Thermal Metrics (SPRA953). The UCC27511 device is offered in a SOT-23, 6-pin package (DBV). The section lists the thermal performance metrics related to SOT-23 package. The ψ and ψ metrics are used when estimating the die temperature JT JB duringactualapplicationmeasurements. HeatremovaloccursprimarilythroughtheleadsofthedeviceandthePCBtracesconnectedtotheleads. 10.2.2.8 PowerDissipation PowerdissipationofthegatedriverhastwoportionsasshowninEquation1. P =P +P DISS DC SW (1) The DC portion of the power dissipation is P = I x VDD where I is the quiescent current for the driver. The DC Q Q quiescentcurrentisthecurrentconsumedbythedevicetobiasallinternalcircuitssuchasinputstage,reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through, and so forth). The UCC27511 and UCC27512 features very low quiescent currents (less than 1 mA, refer Figure 7) and contains internal logic to eliminate any shoot-through in the output driver stage. Thus the effect of theP onthetotalpowerdissipationwithinthegatedrivercanbesafelyassumedtobenegligible. DC Thepowerdissipatedinthegate-driverpackageduringswitching(P )dependsonthefollowingfactors: SW • Gate charge required of the power device (usually a function of the drive voltage V , which is very close to G inputbiassupplyvoltageVDDduetolowV drop-out). OH • Switchingfrequency. • Useofexternalgateresistors. Whenadriverdeviceistestedwithadiscrete,capacitiveloadcalculatingthepowerthatisrequiredfromthebias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given byEquation2. 1 E = C V 2 G LOAD DD 2 where • C isloadcapacitor LOAD • V isbiasvoltagefeedingthedriver (2) DD There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss givenbyEquation3. P =C V 2f G LOAD DD SW where • ƒ istheswitchingfrequency (3) SW TheswitchingloadpresentedbyapowerMOSFET/IGBTisconvertedtoanequivalentcapacitancebyexamining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus theaddedchargeneededtoswingthedrainvoltageofthepowerdeviceasitswitchesbetweentheONandOFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when chargingacapacitorwhichiscalculatedusingtheequation,Q =C xV ,toprovideEquation4forpower. G LOAD DD P =C V 2f =Q V f G LOAD DD SW g DD SW (4) Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Typical Application (continued) This power P is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or G off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is calculatedinEquation5. æ R R ö P =0.5´Q ´VDD´f ´ç OFF + ON ÷ SW G SW èROFF +RGATE RON+RGATE ø where • R =R OFF OL • R (effectiveresistanceofpull-upstructure)=2.7xR (5) ON OL 10.2.3 ApplicationCurves Figure27andFigure28showthetypicalswitchingcharacteristicsoftheUCC27511device. V =10V C =1nF V =10V C =1nF DD (LOAD) DD (LOAD) Figure27.TypicalTurnonWaveform Figure28.TypicalTurnoffWaveform 26 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 11 Power Supply Recommendations The bias supply voltage range for which the UCC27511 and UCC27512 device is rated to operate is from 4.5 V to 18 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the V pin supply circuit blocks. Whenever the driver is in UVLO condition when the V pin voltage is below DD DD the V supply start threshold, this feature holds the output low, regardless of the status of the inputs. The (ON) upper end of this range is driven by the 20-V absolute maximum voltage rating of the V pin of the device DD (which is a stress rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommendedvoltagefortheV pinis18V. DD The UVLO protection feature also involves a hysteresis function. This means that when the V pin bias voltage DD has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification V . DD(hys) Therefore, ensuring that, while operating at or near the 4.5 V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the V pin voltage has dropped below the V DD (OFF) threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system startup, the device does not begin operation until the V pin voltage has exceeded above the V DD (ON) threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the V pin. DD Although this fact is well known, recognizing that the charge for source current pulses delivered by the OUTH pin is also supplied through the same V pin is important. As a result, every time a current is sourced out of the DD output pins (OUTH), a corresponding current pulse is delivered into the device through the V pin. Thus DD ensuring that local bypass capacitors are provided between the V and GND pins and located as close to the DD device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI recommends to have 2 capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged veryclosetothepinsofthedeviceandanothersurface-mountcapacitoroffewmicrofaradsaddedinparallel. 12 Layout 12.1 Layout Guidelines Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device operation and design robustness. The UCC27511 and UCC27512 gate driver incorporates short-propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power switch to facilitate voltage transitions very quickly. At higher V voltages, the peak-current DD capability is even higher (4-A/8-A peak current is at V = 12 V). Very high di/dt causes unacceptable ringing if DD the trace lengths and impedances are not well controlled. The following circuit-layout guidelines are strongly recommendedwhendesigningwiththesehigh-speeddrivers. • Locate the driver device as close as possible to power device in order to minimize the length of high-current tracesbetweentheoutputpinsandthegateofthepowerdevice. • LocatetheV -bypasscapacitorsbetweenV andGNDascloseaspossibletothedriverwithminimaltrace DD DD length to improve the noise filtering. These capacitors support high-peak current being drawn from V during DD turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and chip capacitorsishighlyrecommended. • The turnon and turnoff current-loop paths (driver device, power MOSFET and V bypass capacitor) should DD be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is established in these loops at two instances – during turnon and turnoff transients, which will induce significant voltagetransientsontheoutputpinofthedriverdeviceandgateofthepowerswitch. • Whereverpossible,parallelthesourceandreturntraces,takingadvantageoffluxcancellation. • Separatepowertracesandsignaltraces,suchasoutputandinputsignals. • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM controller, and so forth, at one, single point. The connected paths should be as short as possible to reduce inductanceandbeaswideaspossibletoreduceresistance. • Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 www.ti.com Layout Guidelines (continued) during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition tonoiseshielding,thegroundplanecanhelpinpowerdissipationaswell. • In noisy environments, tying the unused Input pin of UCC27511 and UCC27512 to V (in case of IN+) or DD GND (in case of IN-) using short traces in order to ensure that the output is enabled and to prevent noise fromcausingmalfunctionintheoutputmaybenecessary. • The UCC27512 device offers two ground pins, pin 2 and pin 5. Shorting the two pins together using the PCB traceisextremelyimportant.Theshortesttraceshouldbelocatedascloseaspossibletothedevice. 12.2 Layout Example Figure29. UCC27511LayoutExample 28 SubmitDocumentationFeedback Copyright©2012–2014,TexasInstrumentsIncorporated ProductFolderLinks:UCC27511 UCC27512

UCC27511,UCC27512 www.ti.com SLUSAW9F–FEBRUARY2012–REVISEDNOVEMBER2014 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC27511 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27512 Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2012–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UCC27511 UCC27512

PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC27511DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 140 7511 & no Sb/Br) UCC27511DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 140 7511 & no Sb/Br) UCC27512DRSR ACTIVE SON DRS 6 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 140 27512 & no Sb/Br) UCC27512DRST ACTIVE SON DRS 6 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 140 27512 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC27512 : •Enhanced Product: UCC27512-EP NOTE: Qualified Version Definitions: •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC27511DBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 UCC27511DBVT SOT-23 DBV 6 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 UCC27512DRSR SON DRS 6 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 UCC27512DRST SON DRS 6 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC27511DBVR SOT-23 DBV 6 3000 203.0 203.0 35.0 UCC27511DBVT SOT-23 DBV 6 250 203.0 203.0 35.0 UCC27512DRSR SON DRS 6 3000 367.0 367.0 35.0 UCC27512DRST SON DRS 6 250 210.0 185.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0006A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 B A 1.45 MAX PIN 1 INDEX AREA 1 6 2X 0.95 3.05 2.75 1.9 5 2 4 3 0.50 6X 0.25 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214840/B 03/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178. www.ti.com

EXAMPLE BOARD LAYOUT DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214840/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0006A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 6X (1.1) 1 6X (0.6) 6 SYMM 2 5 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214840/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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