Product Sample & Technical Tools & Support & Folder Buy Documents Software Community UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 UCC2742x Dual 4-A High Speed Low-Side MOSFET Drivers With Enable 1 Features 3 Description • Industry-StandardPin-Out The UCC2742x family of high-speed dual MOSFET 1 drivers can deliver large peak currents into capacitive • EnableFunctionsforEachDriver loads. Three standard logic options are offered – • HighCurrentDriveCapabilityof±4A dual-inverting, dual-noninverting, and one-inverting • UniqueBiPolarandCMOSTrueDriveOutput and one-noninverting driver. The thermally enhanced StageProvidesHighCurrentatMOSFETMiller 8-pin PowerPAD™ MSOP package (DGN) drastically lowers the thermal resistance to improve long-term Thresholds reliability. It is also offered in the standard SOIC-8 (D) • TTL/CMOSCompatibleInputsIndependentof orPDIP-8(P)packages. SupplyVoltage Using a design that inherently minimizes shoot- • 20-nsTypicalRiseand15-nsTypicalFallTimes through current, these drivers deliver 4A of current with1.8-nFLoad where it is needed most at the Miller plateau region • TypicalPropagationDelayTimesof25nswith during the MOSFET switching transition. A unique InputFallingand35nswithInputRising BiPolar and MOSFET hybrid output stage in parallel • 4-Vto15-VSupplyVoltage also allows efficient current sourcing and sinking at lowsupplyvoltages. • DualOutputsCanBeParalleledforHigherDrive Current The UCC2742x provides enable (ENB) functions to have better control of the operation of the driver • AvailableinThermallyEnhancedMSOP applications. ENBA and ENBB are implemented on PowerPAD™Package pins 1 and 8 which were previously left unused in the • RatedFrom –40°Cto125°C industry standard pin-out. They are internally pulled up to V for active high logic and can be left open DD 2 Applications forstandardoperation. • SwitchModePowerSupplies DeviceInformation(1) • DC/DCConverters PARTNUMBER PACKAGE BODYSIZE(NOM) • MotorControllers SOIC(8) 4.90mm×3.91mm UCC27423 • LineDrivers UCC27424 MSOP-PowerPAD(8) 3.00mm×3.00mm • ClassDSwitchingAmplifiers UCC27425 PDIP(8) 9.81mm×6.35mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedApplicationDiagram ENBB UCC2742x ENBA 1 ENBA ENBB 8 INA 2 INA OUTA 7 3 GND VDD 6 V+ GND INB 4 INB OUTB 5 GND GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................13 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 14 3 Description............................................................. 1 9.1 ApplicationInformation............................................14 4 RevisionHistory..................................................... 2 9.2 TypicalApplication .................................................14 5 DeviceComparisonTable..................................... 3 10 PowerSupplyRecommendations..................... 19 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 19 11.1 LayoutGuidelines.................................................19 7 Specifications......................................................... 4 11.2 LayoutExample....................................................20 7.1 AbsoluteMaximumRatings......................................4 11.3 ThermalConsiderations........................................20 7.2 ESDRatings..............................................................4 12 DeviceandDocumentationSupport................. 21 7.3 RecommendedOperatingConditions.......................4 7.4 ThermalInformation..................................................4 12.1 DeviceSupport......................................................21 7.5 ElectricalCharacteristics...........................................5 12.2 DocumentationSupport........................................21 7.6 DissipationRatings...................................................6 12.3 RelatedLinks........................................................21 7.7 TypicalCharacteristics..............................................7 12.4 CommunityResources..........................................21 12.5 Trademarks...........................................................22 8 DetailedDescription............................................ 12 12.6 ElectrostaticDischargeCaution............................22 8.1 Overview.................................................................12 12.7 Glossary................................................................22 8.2 FunctionalBlockDiagram.......................................12 13 Mechanical,Packaging,andOrderable 8.3 FeatureDescription.................................................12 Information........................................................... 22 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(May2013)toRevisionE Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 ChangesfromRevisionC(July2011)toRevisionD Page • AddedPinFunctionstablenote.............................................................................................................................................. 3 • AddedABSOLUTEMAXIMUMRATINGSnote...................................................................................................................... 4 • AddedadditionalENABLEpindescription........................................................................................................................... 12 ChangesfromRevisionB(November2004)toRevisionC Page • Changedtemperaturerating................................................................................................................................................... 1 • ChangedORDERINGINFORMATIONtemperaturerange,threeinstances......................................................................... 1 • ChangedOutputcurrent(OUTA,OUTB)DCfrom0.3Ato0.2A.......................................................................................... 4 • ChangedELECTRICALCHARACTERISTICStemperaturerating........................................................................................ 5 • ChangedLow-leveloutputlevelfrom40mVmaxto45mVmax.......................................................................................... 5 2 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 5 Device Comparison Table PACKAGEDDEVICES OUTPUT TEMPERATURERANGE CONFIGURATION T =T SOIC-8 MSOP-8PowerPAD PDIP-8 A J (D)(1) (DGN)(2) (P) Dualinverting –40°Cto125°C UCC27423D UCC27423DGN UCC27423P DualnonInverting –40°Cto125°C UCC27424D UCC27424DGN UCC27424P Oneinverting, –40°Cto125°C UCC27425D UCC27425DGN UCC27425P onenoninverting (1) D(SOIC-8)andDGN(PowerPAD-MSOP)packagesareavailabletapedandreeled.AddRsuffixtodevicetype(e.g.UCC27423DR, UCC27424DGNR)toorderquantitiesof2,500devicesperreelforDor1,000devicesperreelforDGNpackage. (2) ThePowerPAD™isnotdirectlyconnectedtoanyleadsofthepackage.However,itiselectricallyandthermallyconnectedtothe substratewhichisthegroundofthedevice. 6 Pin Configuration and Functions DPackage,DGNPackage,PPackage 8-PinSOIC,8-PInMSOP-PowerPAD,8-PinPDIP TopView UCC27423 UCC27424 UCC27425 ENBA 1 8 ENBB ENBA 1 8 ENBB ENBA 1 8 ENBB INA 2 7 OUTA INA 2 7 OUTA INA 2 7 OUTA GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD INB 4 5 OUTB INB 4 5 OUTB INB 4 5 OUTB (DUALINVERTING) (DUALNON-INVERTING) (ONE INVERTINGAND ONE NON-INVERTING) PinFunctions PIN I/O DESCRIPTION NAME NO. EnableinputforthedriverAwithlogiccompatiblethresholdandhysteresis.Thedriveroutputcanbeenabledanddisabledwith ENBA 1 I thispin.ItisinternallypulleduptoVDDwith100kΩresistorforactivehighoperation.Theoutputstatewhenthedeviceis disabledwillbelowregardlessoftheinputstate. EnableinputforthedriverBwithlogiccompatiblethresholdandhysteresis.Thedriveroutputcanbeenabledanddisabledwith ENBB 8 I thispin.ItisinternallypulleduptoVDDwith100kΩresistorforactivehighoperation.Theoutputstatewhenthedeviceis disabledwillbelowregardlessoftheinputstate.(1) GND 3 — Commonground:thisgroundshouldbeconnectedverycloselytothesourceofthepowerMOSFETwhichthedriverisdriving. InputA:inputsignaloftheAdriverwhichhaslogiccompatiblethresholdandhysteresis.Ifnotused,thisinputshouldbetiedto INA 2 I eitherVDDorGND.Itshouldnotbeleftfloating.(1) InputB.InputsignaloftheAdriverwhichhaslogiccompatiblethresholdandhysteresis.Ifnotused,thisinputshouldbetiedto INB 4 I eitherVDDorGND.Itshouldnotbeleftfloating. OUTA 7 O DriveroutputA.Theoutputstageiscapableofproviding4AdrivecurrenttothegateofapowerMOSFET. OUTB 5 O DriveroutputB.Theoutputstageiscapableofproviding4AdrivecurrenttothegateofapowerMOSFET. VDD 6 I Supply.Supplyvoltageandthepowerinputconnectionforthisdevice. (1) RefertoDetailedDescriptionformoredetails. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT V Supplyvoltage –0.3 16 V DD I Outputcurrent(OUTA,OUTB)DC 0.2 A OUT_DC I Pulsed,(0.5μs) 4.5 A OUT_PULSED V Inputvoltage(INA,INB) –5 6orV +0.3(whicheverislarger) V IN DD Enablevoltage(ENBA,ENBB) –0.3 6orV +0.3(whicheverislarger) V DD DGNpackage 3 W Powerdissipationat Dpackage 650 TA=25°C mW Ppackage 350 T Junctionoperatingtemperature –55 150 °C J Leadtemperature(soldering,10s) 300 °C T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) WhenV ≤6V,ENratingmaxvalueis6V;whenV >6V,ENratingmaxvalueisV +0.3V. DD DD DD 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500 V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Supplyvoltage 4 15 V DD INAandINB Inputvoltage –2 15 V ENAandENB Enablevoltage 0 15 V T Operatingjunctiontemperature –40 125 °C J 7.4 Thermal Information UCC2742x THERMALMETRIC(1) D(SOIC) DGN(MSOP) P(PDIP) UNIT 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 107.3 56.6 55.5 °C/W θJA R Junction-to-case(top)thermalresistance 52.2 52.8 45.3 °C/W θJC(top) R Junction-to-boardthermalresistance 47.3 32.6 32.6 °C/W θJB ψ Junction-to-topcharacterizationparameter 10.2 1.8 23.0 °C/W JT ψ Junction-to-boardcharacterizationparameter 46.8 32.3 32.5 °C/W JB R Junction-to-case(bottom)thermalresistance – 5.9 – °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 4 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 7.5 Electrical Characteristics V =4.5Vto15V,T =–40°Cto125°C,T =T,(unlessotherwisenoted) DD A A J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUT(INA,INB) V Logic1inputthreshold 2 IN_H V V Logic0inputthreshold 1 IN_L Inputcurrent 0V≤V ≤V –10 0 10 μA IN DD OUTPUT(OUTA,OUTB) Outputcurrent V =14V (1) 4 A DD V High-leveloutputvoltage V =V –V ,I =–10mA 330 450 OH OH DD OUT OUT mV V Low-leveloutputlevel I =10mA 22 45 OL OUT T =25°C,I =–10mA,V =14V(2) 25 30 35 A OUT DD Outputresistancehigh T =fullrange,I =–10mA,V =14V(2) 18 45 A OUT DD Ω T =25°C,I =10mA,V =14V(2) 1.9 2.2 2.5 A OUT DD Outputresistancelow T =fullrangeI =10mA,V =14V(2) 1.2 4.0 A OUT DD Latch-upprotection 500 mA SWITCHINGTIME t Risetime(OUTA,OUTB) C =1.8nF 20 40 r LOAD t Falltime(OUTA,OUTB) C =1.8nF 15 40 f LOAD ns t Delay,INrising(INtoOUT) C =1.8nF 25 40 d1 LOAD t Delay,INfalling(INtoOUT) C =1.8nF 35 50 d2 LOAD ENABLE(ENBA,ENBB) V High-levelinputvoltage LOtoHItransition 1.7 2.4 2.9 V IN_H V Low-levelinputvoltage HItoLOtransition 1.1 1.8 2.2 V IN_L Hysteresis 0.15 0.55 0.90 V R Enableimpedance V =14V,ENB=GND 75 100 140 kΩ ENB DD t Propagationdelaytime(seeFigure2) C =1.8nF 30 60 ns D3 LOAD t Propagationdelaytime(seeFigure2) C =1.8nF 100 150 ns D4 LOAD OVERALL INA=0V,INB=0V 900 1350 UCC27423 INA=0V,INB=HIGH 750 1100 I Staticoperatingcurrent,V =15V, μA DD DD ENBA=ENBB=15V INA=HIGH,INB=0V 750 1100 INA=HIGH,INB=HIGH 600 900 INA=0V,INB=0V 300 450 UCC27424 INA=0V,INB=HIGH 750 1100 I Staticoperatingcurrent,V =15V, μA DD DD ENBA=ENBB=15V INA=HIGH,INB=0V 750 1100 INA=HIGH,INB=HIGH 1200 1800 INA=0V,INB=0V 600 900 UCC27425 INA=0V,INB=HIGH 1050 1600 I Staticoperatingcurrent,V =15V, μA DD DD ENBA=ENBB=15V INA=HIGH,INB=0V 450 700 INA=HIGH,INB=HIGH 900 1350 INA=0V,INB=0V 300 450 Alldisabled,V =15V, INA=0V,INB=HIGH 450 700 I DD μA DD ENBA=ENBB=0V INA=HIGH,INB=0V 450 700 INA=HIGH,INB=HIGH 600 900 (1) Thepullup/pulldowncircuitsofthedriverarebipolarandMOSFETtransistorsinparallel.Thepulsedoutputcurrentratingisthe combinedcurrentfromthebipolarandMOSFETtransistors. (2) Thepullup/pulldowncircuitsofthedriverarebipolarandMOSFETtransistorsinparallel.TheoutputresistanceistheRds(on)ofthe MOSFETtransistorwhenthevoltageonthedriveroutputislessthanthesaturationvoltageofthebipolartransistor. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com 7.6 Dissipation Ratings POWERRATING(mW) DERATINGFACTORABOVE PACKAGE SUFFIX T =70°C(1) 70°C(mW/°C)(1) A SOIC-8 D 344–655(2) 6.25–11.9(2) PDIP-8 P 500 9 MSOP(3) DGN 1370 17.1 (1) 125°Coperatingjunctiontemperatureisusedforpowerratingcalculations (2) Therangeofvaluesindicatestheeffectofpc-board.Thesevaluesareintendedtogivethesystemdesigneranindicationofthebest andworstcaseconditions.Ingeneral,thesystemdesignershouldattempttouselargertracesonthepc-boardwherepossibleinorder tospreadtheheatawayformthedevicemoreeffectively.ForinformationonthePowerPAD™package,refertoTechnicalBrief, PowerPadThermallyEnhancedPackage,TexasInstruments(SLMA002)andApplicationBrief,PowerPadMadeEasy,Texas Instruments(SLMA004). (3) ThePowerPAD™isnotdirectlyconnectedtoanyleadsofthispackage.However,itiselectricallyandthermallyconnectedtothe substratewhichisthegroundofthedevice. (a) (b) +5V 90% 90% INPUT INPUT 10% 10% 0V tD1 tF tD2 tR tF tR 16V 90% 90% 90% tD1 OUTPUT OUTPUT tD2 10% 10% 0V Figure1. SwitchingWaveformsfor(a)InvertingDriverand(b)NoninvertingDriver 5V ENBx VIN_H VIN_L 0V tD3 tD4 VDD 90% 90% OUTx tR tF 10% 0V NOTE: The 10% and90% thresholds depict thedynamicsoftheBiPolar outputdevicesthat dominate thepowerMOSFET transitionthroughtheMillerregionsofoperation. Figure2. SwitchingWaveformforEnabletoOutput 6 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 7.7 Typical Characteristics 100 100 80 80 mA 10 nF mA 10 nF nt - 60 nt - 60 4.7 nF urre urre C C pply 40 4.7 nF pply 40 u u 2.2 nF S S - - IDD 20 2.2 nF IDD 20 1 nF 1 nF 0 470 pF 470 pF 0 0 500 K 1 M 1.5 M 2 M 0 500 K 1 M 1.5 M 2 M f -Frequency- Hz f -Frequency- Hz Figure3.SupplyCurrentvsFrequency(V =4.5V) Figure4.SupplyCurrentvsFrequency(V =8.0V) DD DD 200 150 A m nt - 10 nF 4.7 nF e urr C 100 y pl p 2.2 nF u S - D ID 50 1 nF 470 pF 0 0 500 K 1 M 1.5 M 2 M f -Frequency- Hz Figure5.SupplyCurrentvsFrequency(VDD=12V) Figure6.SupplyCurrentvsFrequency(VDD=15V) 90 160 80 140 2 MHz 70 mA 120 ply Current - 5600 1 MHz Current - mA 18000 2 MHz 1 MHz I- SupDD 3400 500 kHz - Supply DD 6400 500 kHz 20 I 200 kHz 200 kHz 10 20 100/50 kHz 100 kHz 0 0 50/20 kHz 4 6 8 10 12 14 16 4 9 14 19 VDD- Supply Voltage - V VDD- Supply Voltage - V Figure7.SupplyCurrentvsSupplyVoltage Figure8.SupplyCurrentvsSupplyVoltage (CLOAD=2.2nF) (CLOAD=4.7nF) Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com Typical Characteristics (continued) Figure9.SupplyCurrentvsSupplyVoltage(UCC27423) Figure10.SupplyCurrentvsSupplyVoltage(UCC27424) 0.75 25 0.70 20 tr 0.65 ent - mA 0.60 Input = VDD me - ns 15 upply Curr 00..5505 Rise/iFall T 10 tf I- SDD 0.45 Input = 0 V tt- r/f 0.40 5 0.35 0.30 0 4 6 8 10 12 14 16 -50 0 50 100 150 VDD- Supply Voltage - V TJ- Temperature -°C Figure11.SupplyCurrentvsSupplyVoltage(UCC27425) Figure12.RiseTimeandFallTime vsTemperature(UCC27423) s m e - m Ti all F - tf Figure13.RiseTimevsSupplyVoltage Figure14.FallTimevsSupplyVoltage 8 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 Typical Characteristics (continued) 30 38 28 36 10 nF 26 10 nF 34 ime - nsT 2224 4.7 nF me - ns 3320 4.7 nF y iT ela 20 ay 28 tD1 - D 18 D2 - Del 26 2.2 nF 2.2 nF t 16 24 470 pF 1 nF 14 470 pF 22 1 nF 12 20 4 6 8 10 12 14 16 4 6 8 10 12 14 16 VDD- Supply Voltage - V VDD- Supply Voltage - V Figure15.DelayTime(tD1)vsSupplyVoltage(UCC27423) Figure16.DelayTime(tD2)vsSupplyVoltage(UCC27423) 3.0 ENBL - ON V 2.5 sis - kΩ e er st 2.0 y h d n a d 1.5 ol h s e e thr 1.0 abl ENBL - OFF n E 0.5 ENBL - HYSTERESIS 0 -50 -25 0 25 50 75 100 125 TJ- Temperature -°C Figure17.EnableThresholdandHysteresisvsTemperature Figure18.EnableResistancevsTemperature 50ms/div 50ms/div Figure19.OutputBehaviorvsSupplyVoltage(Inverting) Figure20.OutputBehaviorvsSupplyVoltage(Inverting) Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com Typical Characteristics (continued) IN = VDD ENBL = VDD V ge - VDD a upply oltV1 V/div S - OUT D D V 0 V 10nF Between Output and GND 50ms/div 50ms/div Figure21.OutputBehaviorvsVDD(Inverting) Figure22.OutputBehaviorvsVDD(Inverting) 50ms/div 50ms/div Figure23.OutputBehaviorvsVDD(Noninverting) Figure24.OutputBehaviorvsVDD(Noninverting) IN = GND ENBL = VDD V e - VDD g a uoltpply V1 V/div OUT S - D D V 0 V 10nF Between Output and GND 50ms/div 50ms/div Figure25.OutputBehaviorvsVDD(Noninverting) Figure26.OutputBehaviorvsVDD(Noninverting) 10 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 Typical Characteristics (continued) 2.0 1.9 VDD= 15 V V e - 1.8 g a oltd V1.7 ol h es1.6 hr T put 1.5 VDD= 10 V n - ION1.4 VDD= 4.5 V V 1.3 1.2 -50 -25 0 25 50 75 100 125 TJ- Temperature -°C Figure27.InputThresholdvsTemperature Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com 8 Detailed Description 8.1 Overview The UCC2742x family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. Three standard logic options are offered – dual-inverting, dual-noninverting and one-inverting and one- noninverting driver. The thermally enhanced 8-pin PowerPAD™ MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard SOIC-8 (D) or PDIP-8 (P) packages. Using a design that inherently minimizes shoot-through current, these drivers deliver 4A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique Bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.Table1highlightsmoredetailsaboutUCC2742x. Table1.UCC2742xFeaturesandBenefits FEATURE BENEFIT Easeofparallelingoutputsforhigher(2times)currentcapability, 1-ns(typ)delaymatchingbetweenchannels easeofdrivingparallel-powerswitches ExpandedV operatingrangeof4to15V Flexibilityinsystemdesign DD Pin-to-pincompatibilitywiththeUCC27324devicefromTexas Outputsenabledwhenenablepins(ENx)infloatingcondition Instrumentsandindustrystandardpinout,indesignswherePin1 andPin8areinfloatingcondition Enhancednoiseimmunity,whileretainingcompatibilitywith CMOS/TTLcompatibleinputandenablethresholdwithwide microcontrollerlogic-levelinputssignals(3.3V,5V)optimizedfor hysteresis digitalpower Abilitytohandle–5V (max)atinputpins(INA/B) Increasedrobustnessinnoisyenvironments DC 8.2 Functional Block Diagram 8 ENBB ENBA 1 INVERTING 7 OUTA VDD INA 2 NON-INVERTING 6 VDD INVERTING GND 3 5 OUTB INB 4 NON-INVERTING UDG-01063 8.3 Feature Description 8.3.1 Enable UCC2742x provides dual Enable inputs for improved control of each driver channel operation. The inputs incorporate logic compatible thresholds with hysteresis. They are internally pulled up to V with 100kΩ resistor DD for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when ENBA and ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver and therefore can be left open for standard operation. However, if the enable pin is left open, it is recommended to terminate any PCB traces to be as short as possible to limit noise. If large noise is present due to non-optimal PCB layout, it is recommended to tie the Enable pin to Vcc or to add a filter capacitor (0.1 µF) to the Enable pin. The output states when the drivers are disabled is low regardless of the input state. See the truth table of Table 2 for the operationusingenablelogic. 12 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 Feature Description (continued) Enable input are compatible with both logic signals and slow changing analog signals. They can be directly driven or a power-up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and ENBBcontrolinputAandinputBrespectively. 8.3.2 InputStage Theinputthresholdshave3.3VlogicsensitivityoverthefullrangeofV voltages;itisequallycompatiblewith0 DD to V signals. The inputs of the UCC2742x driver family are designed to withstand 500-mA reverse current DD without damaging the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmfultothedriver,theoutputofthedrivermayswitchrepeatedlyatahighfrequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limited rise or fall times to the power device is desired, an external resistance can be added between the output of the driver and the load device which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package, as discussed in the section on ThermalConsiderations. Importantly, input signal of the two channels, INA and INB, which has logic compatible threshold and hysteresis. Ifnotused,INAandINBmustbetiedtoeitherV orGND;itmustnotbeleftfloating. DD 8.3.3 OutputStage Inverting output s of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channel MOSFETs.NoninvertingoutputsoftheUCC27424andOUTBoftheUCC27425areintendedtodriveexternalN- Channel MOSFETs. Each output stage is capable of supplying ±4 A peak current pulses and swings to both V DD and GND. The pullup/pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the R of the MOSFET transistor when the voltage on the driver output is less than the DS(on) saturationvoltageofthebipolartransistor.Eachoutputstagealsoprovidesverylowimpedancetoovershootand undershoot due to the body diode of the external MOSFET. This means that in many cases, external-Schottky- clamp diodes are not required. The UCC2742x family delivers 4 A of gate drive where it is most needed during the MOSFET switching transition (at the Miller plateau region) providing improved efficiency gains. A unique BipolarandMOSFEThybridoutputstageinparallelalsoallowsefficientcurrentsourcingatlowsupplyvoltages. 8.4 Device Functional Modes With V power supply in the range of 4 V to 16 V, the output stage is dependent on the states of the HI and LI DD pins.Table2showstheUCC2742xtruthtable. Table2.Input/OutputLogic INPUTS(VIN_L,VIN_H) UCC27423 UCC27424 UCC27425 ENBA ENBB INA INB OUTA OUTB OUTA OUTB OUTA OUTB H H L L H H L L H L H H L H H L L H H H H H H L L H H L L L H H H H L L H H L H L L X X L L L L L L Importantly,ifINAandINBarenotused,theymustbetiedtoeitherV orGND;itmustnotbeleftfloating. DD Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information High frequency power supplies often require high-speed, high-current drivers such as the UCC2742x family. A leading application is the need to provide a high power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the needtosimultaneouslydrivemultipledeviceswhichcanpresentanextremelylargeloadtothecontrolcircuitry. Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC2742x. Finally, the control IC may be under thermal stress due to power dissipation, and an external driver can help by movingtheheatfromthecontrollertoanexternalpackage. 9.2 Typical Application ENBB UCC2742x ENBA 1 ENBA ENBB 8 INA 2 INA OUTA 7 3 GND VDD 6 V+ GND INB 4 INB OUTB 5 GND GND Figure28. UCC2742xDrivingTwoIndependentMOSFETs 9.2.1 DesignRequirements To select proper device from UCC2742x family, it is recommended to first check the appropriate logic for the outputs. UCC27423 has dual inverting outputs; UCC27424 has dual non-inverting outputs; UCC27425 has an inverting channel A and non-inverting channel B. Moreover, some considerations must be evaluated in order to makethemostappropriateselection.AmongtheseconsiderationsareV ,drivecurrent,andpowerdissipation. DD 14 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 Typical Application (continued) 9.2.2 DetailedDesignProcedure 9.2.2.1 SourceandSinkCapabilitiesDuringMillerPlateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC2742x drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging and discharging of the drain- gatecapacitancewithcurrentsuppliedorremovedbythedriverdevice. Two circuits are used to test the current capabilities of the UCC2742x driver. In each case external circuitry is added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurementsaremadeatatimeof200nsaftertheinputpulseisapplied,aftertheinitialtransient. The circuit in Figure 29 is used to verify the current sink capability when the output of the driver is clamped around 5V, a typical value of gate-source voltage during the Miller plateau region. The UCC2742x is found to sink4.5AatV =15Vand4.28AatV =12V. DD DD UCC2742x VDD 1 ENBA ENBB 8 DSCHOTTKY 10 (cid:13) 2 INA OUTA 7 C2 C3 1 (cid:29)F 100 (cid:29)F + VADJ 5.5 V Signal 3 GND VDD 6 generator producing 250-ns wide VSNS pulse 4 INB OUTB 5 RSNS 0.1 (cid:13) 1 (cid:29)F 100 (cid:29)F CER AL EL Figure29. CurrentSinkCapabilityTest The circuit show in Figure 30 is used to test the current source capability with the output clamped around 5 V withastringofZenerdiodes.TheUCC2742xisfoundtosource4.8AatV =15Vand3.7AatV =12V. DD DD Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com Typical Application (continued) UCC2742x VDD 1 ENBA ENBB 8 DSCHOTTKY 10 (cid:13) 2 INA OUTA 7 C2 C3 Signal 1 (cid:29)F 100 (cid:29)F 4.5 V Generator 3 GND VDD 6 VSNS 250 ns 4 INB OUTB 5 RSNS 0.1 (cid:13) 1 (cid:29)F 100 (cid:29)F CER AL EL Figure30. CurrentSourceCapabilityTest 9.2.2.2 ParallelOutputs TheAandBdriversmaybecombinedintoasingledriverbyconnectingtheINAandINBinputstogetherandthe OUTA and OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure31. UCC2742x VDD INPUT 1 ENBA ENBB 8 2 INA OUTA 7 3 GND VDD 6 CLOAD 4 INB OUTB 5 1 (cid:29)F 2.2 (cid:29)F CER Figure31. ParallelOperationofUCC27423andUCC27424 Important consideration about paralleling two channels for UCC27423/4 include the INA and INB should be shorted in PCB layout as close to the device as possible, as well as for OUTA and OUTB, in which condition PCB layout parasitic mismatching between two channels could be minimized. The INA/B slope signal should be fast enough to avoid mismatched V / V , t / t between channel-A and channel-B. It is recommended to IN_H IN_L d1 d2 haveinputsignalslopefasterthan20V/us. 16 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 Typical Application (continued) 9.2.2.3 V DD Although quiescent V current is very low, total supply current will be higher, depending on OUTA and OUTB DD current and the programmed oscillator frequency. Total V current is the sum of quiescent V current and the DD DD average OUT current. Knowing the operating frequency and the MOSFET gate charge (Q ), average OUT g currentcanbecalculatedfromEquation1. I =Q ×f OUT g where • f=switchingfrequency (1) For the best high-speed circuit performance, two V bypass capacitors are recommended to prevent noise DD problems. The use of surface mount components is highly recommended. A 0.1μF ceramic capacitor should be located closest to the V to ground connection. In addition, a larger capacitor (such as 1μF) with relatively low DD ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels in the driver application. 9.2.2.4 DriveCurrentandPowerRequirements The UCC2742x family of drivers are capable of delivering 4 A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switchingdeviceusedinhighfrequencypowerconversionequipment. References 1 and 2 in Documentation Support discuss the current required to drive a power MOSFET and other capacitive-input switching devices. Reference 2 in Documentation Support includes information on the previous generationofbipolarICgatedrivers. When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor isgivenbyEquation2. E(cid:1)1CV2 2 where • C=loadcapacitor,andV=biasvoltage(feedingthedriver) (2) There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a powerlossgivenbyEquation3. P=CV2×f where • f=switchingfrequency (3) This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditionsofthepreviousgatedrivewaveformshouldhelpclarifythis. WithV =12V,C =10nF,andf=300kHz,thepowerlosscanbecalculatedasEquation4. DD LOAD P=10nF×(12V)2×(300kHz)=0.432W (4) Witha12Vsupply,thiswouldequatetoacurrentofEquation5. P 0.432W I= = =36mA V 12V (5) Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com Typical Application (continued) The actual current measured from the supply was 0.037A, and is very close to the predicted value. But, the I DD current that is due to the IC internal consumption should be considered. With no load the IC current draw is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However, these small current differences are buried in the high frequency switching spikes, and are beyond the measurement capabilities of a basic lab setup. The measured current with 10 nF load is reasonably close to that expected. The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Q , one can determine the power that must be dissipated when g chargingacapacitor.ThisisdonebyusingtheequivalenceQ =C VtoprovidethepowerlossinEquation6. g eff P=C×V2×f=V×Q ×f (6) g This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specificbiasvoltage. 9.2.3 ApplicationCurves Figure 32 and Figure 33 shows rising/falling time and turn-on/off propagation delay testing waveform in room temperature for UCC27424, and waveform measurement data (see the bottom part of the waveform). Each channel,INA/INB/OUTA/OUTB,islabeledanddisplayedonthelefthandofthewaveforms. Theloadcapacitancetestingconditionis1.8nF,V =12V,andf=300kHz. DD HI and LI share one same input from function generator, therefore, besides the propagation delay and rising/falling time, the difference of the propagation delay between HO and LO gives the propagation delay matchingdata. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. CL=1.8nF,V =12V,f=300kHz CL=1.8nF,V =12V,f=300kHz DD DD Figure32.RisingTimeandTurnonPropagationDelay Figure33.FallingTimeandTurnoffPropagationDelay 18 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 10 Power Supply Recommendations The recommended bias supply voltage range for UCC2742x is from 4 V to 15 V. The upper end of this range is driven by the 16 V absolute maximum voltage rating of the V . It is recommended to keep proper margin to DD allowfortransientvoltagespikes. AlocalbypasscapacitorshouldbeplacedbetweentheVDD andGNDpins.Andthiscapacitorshouldbelocated as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. TI recommends using 2 capacitors across VDD and GND: a 100 nF ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10 μF,forICbiasrequirements. 11 Layout 11.1 Layout Guidelines Optimum performance of gate drivers cannot be achieved without taking due considerations during circuit board layout.Thefollowingpointsareemphasized: 1. Low ESR/ESL capacitors must be connected close to the IC between VDD and GND pins to support high peakcurrentsdrawnfromVDDduringtheturn-onoftheexternalMOSFETs. 2. Groundingconsiderations: – The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close aspossibletotheMOSFETs. – Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM controller at one, single point. The connected paths must be as short as possible to reduce inductance. – Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential.Inadditiontonoiseshielding,thegroundplanecanhelpinpowerdissipationaswell. 3. In noisy environments, tying inputs of an unused channel of the UCC2742x device to VDD or GND using short traces in order to ensure that the output is enabled and to prevent noise from causing malfunction in theoutputmaybenecessary. 4. Separatepowertracesandsignaltraces,suchasoutputandinputsignals. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com 11.2 Layout Example Ground plane UCC2742x Figure34. RecommendedPCBLayoutforUCC2742x 11.3 Thermal Considerations The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristicsoftheICpackage.Inorderforapowerdrivertobeusefuloveraparticulartemperaturerange,the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2742x family of drivers is available in three different packages to cover a range of applicationrequirements. As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages have a power rating of around 0.5 W with T = 70°C. This limit is imposed in conjunction with the power derating factor also given in A Dissipation Ratings. Note that the power dissipation in our earlier example is 0.432W with a 10nF load, 12 V , DD switched at 300kHz. Thus, only one load of this size could be driven using the D or P package, even if the two onboarddriversareparalleled.Thedifficultieswithheatremovallimitthedriveavailableintheolderpackages. The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As illustrated in Reference 3 of Documentation Support, the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the IC package, reducing the R down to 5.9°C/W. Data θJC(bot) is presented in Reference 3 of Documentation Support to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference 4 of Documentation Support. This allows a significant improvement in heatsinking over that available in the D or P packages, and is shown to more than double the power capability of the D and P packages. Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and thermally connectedtothesubstratewhichisthegroundofthedevice. 20 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 www.ti.com SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 12 Device and Documentation Support 12.1 Device Support 12.1.1 RelatedProducts PRODUCT DESCRIPTION PACKAGES UCC37323 UCC37324 Dual4-ALow-SideDrivers MSOP-8PowerPAD,SOIC-8,PDIP-8 UCC37325 UCC37321 Single9-ALow-SideDriverwithEnable MSOP-8PowerPAD,SOIC-8,PDIP-8 UCC37322 TPS2811 TPS2812 Dual2-ALow-SideDriverswithInternalRegulator TSSOP-8,SOIC-8,PDIP-8 TPS2813 TPS2814 Dual2-ALow-SideDriverswithTwoInputsperChannel TSSOP-8,SOIC-8,PDIP-8 TPS2815 TPS2816 TPS2817 Single2-ALow-SideDriverwithInternalRegulator 5-PinSOT-23 TPS2818 TPS2819 TPS2828 Single2-ALow-SideDriver 5-PinSOT-23 TPS2829 12.2 Documentation Support 12.2.1 RelatedDocumentation • Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate DriveCircuits,byLaszloBalogh,TexasInstruments(SLUP133). • Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits,byBillAndreycak,TexasInstruments(SLUA105) • TechnicalBrief, PowerPadThermallyEnhancedPackage,TexasInstruments(SLMA002) • ApplicationBrief,PowerPADMadeEasy,TexasInstruments(SLMA004) 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC27423 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27424 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27425 Clickhere Clickhere Clickhere Clickhere Clickhere 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC27423 UCC27424 UCC27425

UCC27423,UCC27424,UCC27425 SLUS545E–NOVEMBER2002–REVISEDDECEMBER2015 www.ti.com 12.5 Trademarks PowerPAD,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 22 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:UCC27423 UCC27424 UCC27425

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UCC27423D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27423 & no Sb/Br) UCC27423DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 105 27423 & no Sb/Br) UCC27423DGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 105 27423 & no Sb/Br) UCC27423DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27423 & no Sb/Br) UCC27423P ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 105 27423 (RoHS) UCC27424D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27424 & no Sb/Br) UCC27424DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 105 27424 & no Sb/Br) UCC27424DGNG4 ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27424 & no Sb/Br) UCC27424DGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 105 27424 & no Sb/Br) UCC27424DGNRG4 ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27424 & no Sb/Br) UCC27424DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27424 & no Sb/Br) UCC27424DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27424 & no Sb/Br) UCC27424P ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 105 27424 (RoHS) UCC27425D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27425 & no Sb/Br) UCC27425DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27425 & no Sb/Br) UCC27425DGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 105 27425 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UCC27425DGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 105 27425 & no Sb/Br) UCC27425DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27425 & no Sb/Br) UCC27425DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 105 27425 & no Sb/Br) UCC27425P ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 105 27425 (RoHS) UCC27425PE4 ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type -40 to 105 27425 (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC27423, UCC27424, UCC27425 : •Automotive: UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 •Enhanced Product: UCC27423-EP, UCC27424-EP NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC27423DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27423DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27424DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27424DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27424DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27425DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27425DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC27423DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 UCC27423DR SOIC D 8 2500 340.5 338.1 20.6 UCC27424DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 UCC27424DR SOIC D 8 2500 367.0 367.0 35.0 UCC27424DR SOIC D 8 2500 340.5 338.1 20.6 UCC27425DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 UCC27425DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 2.15 1.95 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.846 TYPICAL 1.646 4225480/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.846) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (2.15) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225480/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008G PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.846) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (2.15) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.06 X 2.40 0.125 1.846 X 2.15 (SHOWN) 0.15 1.69 X 1.96 0.175 1.56 X 1.82 4225480/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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