Product Sample & Technical Tools & Support & Folder Buy Documents Software Community UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 UCC2732x-Q1 Single 9-A High-Speed Low-Side MOSFET Driver With Enable 1 Features 3 Description • QualifiedforAutomotiveApplications The UCC2732x-Q1 family of high-speed drivers 1 delivers 9 A of peak drive current in an industry- • AEC-Q100QualifiedWiththeFollowingResults: standard pinout. These drivers can drive large – DeviceTemperatureGrade1: –40°Cto125°C MOSFETs for systems requiring extreme Miller AmbientOperatingTemperatureRange current due to high dV/dt transitions. This eliminates – DeviceHBMESDClassificationLevel 2 additional external circuits and can replace multiple components to reduce space, design complexity, and – DeviceCDMESDClassificationLevelC6 assembly cost. Two standard logic options are • Industry-StandardPinoutWithAdditionofEnable offered, inverting (UCC27321-Q1) and noninverting Function (UCC27322-Q1). • HighPeak-CurrentDriveCapabilityof±9Aatthe Using a design that minimizes shoot-through current, MillerPlateauRegionUsingTrueDrive™ the outputs of these devices can provide high gate Technology drive current where it is most needed at the Miller • EfficientConstant-CurrentSourcingUsinga plateau region during the MOSFET switching transition. A unique hybrid-output stage paralleling UniqueBipolarandCMOSOutputStage bipolar and MOSFET transistors (TrueDrive) allows • TTLandCMOS-CompatibleInputsIndependentof efficient current delivery at low supply voltages. With SupplyVoltage this drive architecture, UCC2732x-Q1 can be used in • 20-nsTypicalRiseand15-nsTypicalFallTimes industry standard 6-A, 9-A, and many 12-A driver With10-nFLoad applications. Latch-up and ESD protection circuits are also included. Finally, the UCC2732x-Q1 provides an • TypicalPropagationDelayTimesof25nsWith enable (ENBL) function to better control the operation InputFallingand35nsWithInputRising of the driver applications. ENBL is implemented on • 4-Vto15-VSupplyVoltage pin 3, which was previously left unused in the • AvailableinThermallyEnhancedMSOP industry-standard pinout. It is internally pulled up to PowerPAD™Package VDD for active-high logic and can be left open for standardoperation. • TrueDriveOutputArchitectureUsingBipolarand CMOSTransistorsinParallel DeviceInformation(1) 2 Applications PARTNUMBER PACKAGE BODYSIZE(NOM) UCC27321-Q1, • Switch-ModePowerSupplies UCC27322-Q1 SOIC(8) 6.00mm×4.90mm • DC-DCConverters UCC27322-Q1 MSOP-PowerPAD(8) 4.90mm×3.00mm • MotorControllers (1) For all available packages, see the orderable addendum at • LineDrivers theendofthedatasheet. • Class-DSwitchingAmplifiers • PulseTransformerDriver FunctionalBlockDiagram INPUT/OUTPUTTABLE VDD 1 8 VDD ENBL IN OUT INVERTING 0 0 0 0 1 0 7 OUT INVERTING VDD UCC27321-Q1 1 0 1 NON 1 1 0 IN 2 INVERTING 6 OUT 0 0 0 RENBL NON 0 1 0 INVERTING ENBL 3 UCC27322-Q1 1 0 0 1 1 1 AGND 4 5 PGND Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 9.4 DeviceFunctionalModes........................................15 2 Applications........................................................... 1 10 ApplicationandImplementation........................ 16 3 Description............................................................. 1 10.1 ApplicationInformation..........................................16 4 RevisionHistory..................................................... 2 10.2 TypicalApplication................................................16 5 Description(Continued)........................................ 3 11 PowerSupplyRecommendations..................... 19 6 DeviceComparisonTable..................................... 3 12 Layout................................................................... 19 12.1 LayoutGuidelines.................................................19 7 PinConfigurationandFunctions......................... 3 12.2 LayoutExample....................................................20 8 Specifications......................................................... 4 12.3 ThermalConsiderations........................................20 8.1 AbsoluteMaximumRatings......................................4 12.4 PowerDissipation.................................................21 8.2 ESDRatings..............................................................4 13 DeviceandDocumentationSupport................. 22 8.3 RecommendedOperatingConditions.......................4 13.1 DocumentationSupport........................................22 8.4 ThermalInformation..................................................4 13.2 RelatedLinks........................................................22 8.5 ElectricalCharacteristics...........................................5 13.3 ReceivingNotificationofDocumentationUpdates22 8.6 SwitchingCharacteristics..........................................5 13.4 CommunityResources..........................................22 8.7 TypicalCharacteristics..............................................7 13.5 Trademarks...........................................................22 9 DetailedDescription............................................ 11 13.6 ElectrostaticDischargeCaution............................22 9.1 Overview.................................................................11 13.7 Glossary................................................................22 9.2 FunctionalBlockDiagram.......................................11 14 Mechanical,Packaging,andOrderable 9.3 FeatureDescription.................................................11 Information........................................................... 23 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(January2012)toRevisionD Page • AddedDeviceInformationtable,ESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes, ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection....................................... 1 • ChangedUCC3732xtoUCC2732x-Q1throughoutdocument............................................................................................... 1 • DeletedOrderingInformationtable;seePOAaddedattheendofthedatasheet............................................................... 1 • ChangedtabledescriptionsforAGNDandPGND................................................................................................................. 3 • UpdatedvaluesintheThermalInformationtabletoalignwithJEDECstandards................................................................. 4 • Changedx-axisvaluesfrom1,10,100to0.1,1,10inRiseTimevsLoadCapacitancegraph........................................... 7 • Deletednotereference[1].................................................................................................................................................... 12 ChangesfromRevisionB(January2011)toRevisionC Page • Changedenableimpedancemaximumfrom135kΩto145kΩ............................................................................................ 5 2 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 5 Description (Continued) In addition to 8-pin SOIC (D) package offerings, the UCC2732x-Q1 also comes in the thermally enhanced but tiny 8-pin MSOP-PowerPAD (DGN) package. The PowerPAD package drastically lowers the thermal resistance toextendthetemperatureoperationrangeandimprovelong-termreliability. 6 Device Comparison Table Table1.RelatedProducts PRODUCT DESCRIPTION PACKAGE UCC2742x-Q1 Dual4-Alow-sidedriverswithenable MSOP-8PowerPAD,SOIC-8,PDIP-8 TPS2811-Q1 Dual2-Alow-sidedriverswithinternalregulator TSSOP-8,SOIC-8,PDIP-8 TPS2819-Q1 Single2-Alow-sidedriverwithinternalregulator 5-pinSOT-23 TPS2829-Q1 Single2-Alow-sidedriver 5-pinSOT-23 7 Pin Configuration and Functions DPackage 8-PinSOIC DGNPackage TopView 8-PinMSOPwithPowerPAD TopView VDD 1 8 VDD VDD 1 8 VDD IN 2 7 OUT IN 2 7 OUT PowerPAD ENBL 3 6 OUT ENBL 3 6 OUT AGND 4 5 PGND AGND 4 5 PGND Not to scale Not to scale PinFunctions PIN TYPE DESCRIPTION NAME NO. TheAGNDandthePGNDmustbeconnectedbyasinglethicktracedirectlyunderthedevice.There mustbealowESR,lowESLcapacitorof0.1µFbetweenVDD(pin1)andAGND.ThepowerMOSFETs AGND 4 GND mustbeplacedonthePGNDsideofthedevicewhilethecontrolcircuitmustbeontheAGNDsideofthe device.ThecontrolcircuitgroundmustbecommonwiththeAGNDwhilethePGNDmustbecommon withthesourceofthepowerFETs. Enableinputforthedriverwithlogic-compatiblethresholdandhysteresis.Thedriveroutputcanbe ENBL 3 I enabledanddisabledwiththispin.ItisinternallypulleduptoVDDwithapullupresistorforactive-high operation.Theoutputstatewhenthedeviceisdisabledislow,regardlessoftheinputstate. Inputsignalofthedriver,whichhaslogic-compatiblethresholdandhysteresis.ForUCC27321-Q1,INis IN 2 I inverting,andforUCC37322-Q1,INisnoninverting. Driveroutputsthatmustbeconnectedtogetherexternally.Theoutputstageiscapableofproviding9-A OUT 6,7 O peakdrivecurrenttothegateofapowerMOSFET. Commongroundforoutputstage.Thisgroundmustbeconnectedveryclosetothesourceofthepower MOSFETwhichthedriverisdriving.Groundsareseparatedtominimizeringingeffectsduetooutput PGND 5 GND switchingdi/dt,whichcanaffecttheinputthreshold.TheremustbealowESR,lowESLcapacitorof0.1 µFbetweenVDD(pin8)andPGND. Supplyvoltageandthepowerinputconnectionsforthisdevice.Thesepinsmustbeconnectedtogether VDD 1,8 PWR externally. PowerPADonDGNpackageonly.ThePowerPADthermalpadisnotdirectlyconnectedtoanyleadsof PowerPAD Pad GND thepackage.However,itiselectricallyandthermallyconnectedtothesubstrate,whichisthegroundof thedevice. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)(2) MIN MAX UNIT Supplyvoltage –0.3 16 V Outputcurrent OUT 0.6 A 6or Inputvoltage IN,ENBL –5 V V +0.3 DD Dpackage 650 mW PowerdissipationatT =25°C A DGNpackage 3 W Operatingjunctiontemperature,T –55 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoGND.Currentsarepositiveintoandnegativeoutofthespecifiedterminal. 8.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perAECQ100-002(1) 2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perAECQ100-011 1000 (1) AECQ100-002indicatesthatHBMstressingshallbeinaccordancewiththeANSI/ESDA/JEDECJS-001specification. 8.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltage VDD 4.5 15 V DD 8.4 Thermal Information UCC2732x-Q1 UCC27322-Q1 THERMALMETRIC(1)(2)(3) D(SOIC) DGN(MSOP- UNIT PowerPAD) 8PINS 8PINS R Junction-to-ambientthermalresistance 113 58.6 °C/W θJA R Junction-to-case(top)thermalresistance 61.7 45.3 °C/W θJC(top) R Junction-to-boardthermalresistance 53.2 34.3 °C/W θJB ψ Junction-to-topcharacterizationparameter 16 1.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 52.7 34 °C/W JB R Junction-to-case(bottom)thermalresistance — 11.9 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. (2) Ingeneral,thesystemdesignermustattempttouselargertracesonthePCBwherepossibletospreadtheheatawayfromthedevice moreeffectively.ForinformationonthePowerPADpackage,seePowerPad™ThermallyEnhancedPackageandPowerPad™Made Easy. (3) ThePowerPADthermalpadisnotdirectlyconnectedtoanyleadsofthepackage.However,itiselectricallyandthermallyconnectedto thesubstrate,whichisthegroundofthedevice. 4 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 8.5 Electrical Characteristics V =4.5Vto15V,T =T =–40°Cto125°C(unlessotherwisenoted) DD J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 150 225 IN=Low,ENBL=Low,V =15V DD 440 650 UCC27321-Q1 370 550 IN=High,ENBL=Low,V =15V DD 370 550 I Staticoperatingcurrent µA DD 150 225 IN=Low,ENBL=High,V =15V DD 450 650 UCC27322-Q1 75 125 IN=High,ENBL=High,V =15V DD 675 1000 INPUT(IN) V Logic1inputthreshold 2 V IH V Logic0inputthreshold 1 V IL Inputcurrent 0V≤V ≤V –10 0 10 µA IN DD Latch-upprotection(1) 500 mA OUTPUT(OUT) Peakoutputcurrent(1)(2) V =14V 9 A DD V High-leveloutputvoltage V =V –V I =–10mA 150 300 mV OH OH DD OUT, OUT V Low-leveloutputvoltage I =10mA 11 25 mV OL OUT Outputresistancehigh(3) I =–10mA,V =14V 15 25 Ω OUT DD Outputresistancelow(3) I =10mA,V =14V 1.1 2.5 Ω OUT DD Latch-upprotection(1) 500 mA ENABLE(ENBL) V Enablerisingthresholdvoltage Low-to-hightransitions 1.5 2.2 2.7 V EN_H V Enablefallingthresholdvoltage High-to-lowtransition 1.1 1.65 2 V EN_L Hysteresis 0.18 0.55 0.9 V R Enableimpedance V =14V,ENBL=Low 75 100 145 kΩ (ENBL) DD t Propagationdelaytime C =10nF(seeFigure2) 60 95 ns D3 LOAD t Propagationdelaytime C =10nF(seeFigure2) 60 95 ns D4 LOAD (1) Specifiedbydesign (2) ThepullupandpulldowncircuitsofthedriverarebipolarandMOSFETtransistorsinparallel.Thepulsedoutputcurrentratingisthe combinedcurrentfromthebipolarandMOSFETtransistors. (3) ThepullupandpulldowncircuitsofthedriverarebipolarandMOSFETtransistorsinparallel.TheoutputresistanceistheR ofthe DS(ON) MOSFETtransistorwhenthevoltageonthedriveroutputislessthanthesaturationvoltageofthebipolartransistor. 8.6 Switching Characteristics V =4.5Vto15V,T =T =–40°Cto125°C(unlessotherwisenoted)(seeFigure1) DD J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Risetime(OUT) C =10nF 20 75 ns R LOAD t Falltime(OUT) C =10nF 20 35 ns F LOAD t Delaytime,INrising(INtoOUT) C =10nF 25 75 ns D1 LOAD t Delaytime,INfalling(INtoOUT) C =10nF 35 75 ns D2 LOAD Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com (a) (b) 5V IN VTH VTH IN VTH VTH 0V tD1 tD2 tD1 tD2 tF VDD 80% 80% 80% 80% OUT tR OUT tR tF 20% 20% 0V The20%and80%thresholdsdepictthedynamicsofthebipolaroutputdevicesthatdominatethepowerMOSFET transitionthroughtheMillerregionsofoperation. Figure1. SwitchingWaveformsforInvertingDriver(a)andNoninvertingDriver(b) 5V ENBL VIN_H VIN_L 0V tD3 tD4 VDD 80% 80% OUT tR tF 20% 0V The20%and80%thresholdsdepictthedynamicsofthebipolaroutputdevicesthatdominatethepowerMOSFET transitionthroughtheMillerregionsofoperation. Figure2. SwitchingWaveformsforEnabletoOutput 6 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 8.7 Typical Characteristics 700 700 600 600 μA ENINBL= =5V 0V μA ENBL= 0V – 500 – 500 IN= 5V I–InputCurrentIdleDD 423000000 ENINBL= =5 VVDD ENINBL= =0V 0V I–InputCurrentIdleDD 423000000 ENINBL= =0V 0V ENBL= VDD, IENN I=NB 0L=V =5 VVDD 100 100 0 ENBL= VDD, IN = 0V 0 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 VDD–Supply Voltage–V VDD–Supply Voltage–V Figure3.InputCurrentIdlevs Figure4.InputCurrentIdlevs SupplyVoltage(UCC27321-Q1) SupplyVoltage(UCC27322-Q1) 800 800 700 700 ENBL= HIIGH IN=HIIGH A–CurrentIdleμ 645000000 EINN=B LHI= LO EINN=B LHI= HI EINN=B LLO= HI CurrAentIdle–μ 645000000 EINN=B HLIIG= HLOW ut ut I–InpDD 230000 EINN=B LLO= LO I–InpDD230000 EINN=B LLO=W LOW EINN=B LLO=W HIIGH 100 100 0 0 --50 --25 0 25 50 75 100 125 --50 --25 0 25 50 100 75 125 TJ–Temperature–°C TJ–Temperature–°C Figure5.InputCurrentIdlevsTemperature(UCC27321-Q1) Figure6.InputCurrentIdlevsTemperature(UCC27322-Q1) 70 CLOAD=10nF CLOAD= 10 nF 60 50 tA=–40°C s n – 40 Time tA=105°C tA=25°C se 30 Ri – tR 20 10 tA=0°C 0 4 6 8 10 12 14 16 VDD–SupplyVoltage–V Figure7.RiseTimevsSupplyVoltage Figure8.FallTimevsSupplyVoltage Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com Typical Characteristics (continued) 40 200 VDD=5V VDD=5V 160 30 VDD=10V ns VDD=10V s VDD=15V me– VDD=15V e–n 120 t–Rise TiR 20 t–Fall TimR 80 10 40 0 0 0.1 1 10 0.1 1 10 CLOAD–- LoadCapacitance–nF CLOAD– LoadCapacitance–nF Figure9.RiseTimevsLoadCapacitance Figure10.FallTimevsOutputCapacitance 70 70 CLOAD=10nF CLOAD=10nF 60 60 tA=105°C tA=105°C ns 50 50 tA=25°C e-- tA=25°C ns DelayTim 40 ayTime-- 40 -– 30 Del 30 tD1 20 t–D2 20 tA=0°C tA=–40°C tA=–40°C 10 tA=0°C 10 0 0 4 6 8 10 12 14 16 4 6 8 10 12 14 16 VDD–SupplyVoltage–V VDD– SupplyVoltage–V Figure11.t DelayTimevsSupplyVoltage Figure12.t DelayTimevsSupplyVoltage D1 D2 70 70 VDD=5V 60 60 -–ns 50 VDD=5V VDD=10V e–ns 50 Time 40 yTim 40 t–DelayD1 3200 VDD=15V t–DelaD2 3200 VDD=15V VDD=10V 10 10 0 0 1 10 100 1 10 100 CLOAD– LoadCapacitance–nF CLOAD–LoadCapacitance–nF Figure13.tD1DelayTimevsLoadCapacitance Figure14.tD2DelayTimevsLoadCapacitance 8 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 Typical Characteristics (continued) 50 2.0 VDD=15V 45 tD2 CLTOAAD==251°0CnF 1.9 VDD=15V 40 V tRISE – 1.8 PropagationTime--ns 3231205550 nputThreshold Voltage 111...567 VDD=10V 10 tD1 tFALL V–ION 1.4 VDD=4.5 V 1.3 5 0 1.2 0 5 10 15 --50 --25 0 25 50 75 100 125 VIN(peak)– PeakInput Voltage–V TJ–Temperature–°C Figure15.PropagationTimesvsPeakInputVoltage Figure16.InputThresholdvsTemperature 3.0 150 140 ENBL--ON 2.5 V 130 esis– Ωe– 120 Enablethresholdandhyster 112...050 ENBL--OFF R–EnableResistancENBL 111078900000 0.5 ENBL--HYSTERESIS 60 0 50 --50 --25 0 25 50 75 100 125 --50 --25 0 25 50 75 100 125 TJ– Temperature–°C TJ–Temperature– °C Figure17.EnableThresholdandHysteresisvsTemperature Figure18.EnableResistancevsTemperature IN= GND IN= GND ENBL= VDD ENBL= VDD V V – – –Input Voltage1 V/div –InputVoltage1V/div VDD VDD VDD OUT OUT 0V 0V VDD 10nF Between Output and GND 10nF Between Output and GND 50μs/div 50μs/div Figure19.OutputBehaviorvsVDD(UCC27321-Q1) Figure20.OutputBehaviorvsVDD(UCC27321-Q1) Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com Typical Characteristics (continued) ENINBL= V= DVDDD ENINBL= V= DVDDD V – ge V SupplyVolta1V/div VDD plyVoltage–V/div VDD – up1 D S VD OUT – OUT D D V 0V 0V 10nF Between Output and GND 10nF Between Output and GND 50μs/div 50μs/div Figure21.OutputBehaviorvsV (Inverting) Figure22.OutputBehaviorvsV (Inverting) DD DD IN= GND IN= GND ENBL= VDD ENBL= VDD V V – – –SupplyVoltage1V/div VDD OUT –SupplyVoltage1V/div OUT VDD D D D D V V 0V 0V 10nF Between Output and GND 10nF Between Output and GND 50μs/div 50μs/div Figure23.OutputBehaviorvsVDD(Noninverting) Figure24.OutputBehaviorvsVDD(Noninverting) 10 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 9 Detailed Description 9.1 Overview The UCC27321-Q1 and UCC27322-Q1 drivers serve as an interface between low-power controllers (discrete controllers, DSPs, MCUs, or microprocessors) and power MOSFETs. High-frequency power supplies often require high-speed, high-current drivers such as the UCC2732x-Q1 family. A leading application provides a high- power buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the device drives the power device gates through a drive transformer. Synchronous rectification supplies also have the need to drive multiple devices simultaneously, which can presentanextremelylargeloadtothecontrolcircuitry. Theinvertingdriver(UCC27321-Q1)isusefulforgeneratinginvertedgate-drivesignalsfromcontrollersthathave outputs of the opposite polarity. For example, this driver can provide a gate signal for ground-referenced, N- channel synchronous rectifier MOSFETs in buck derived converters. This driver can also be used for generating agate-drivesignalforaP-channelMOSFETfromacontrollerthatisdesignedforN-channelapplications. MOSFET gate drivers are generally used when it is not feasible to have the primary PWM regulator device directly drive the switching devices for one or more reasons. The PWM device may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases, there may be a desire to minimize the effect of high-frequency switching noise by placing the high- current driver physically close to the load. Also, newer devices that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high-impedance inputtoadriversuchastheUCC2732x-Q1.Finally,thecontroldevicemaybeunderthermalstressduetopower dissipationandanexternaldrivercanhelpbymovingtheheatfromthecontrollertoanexternalpackage. 9.2 Functional Block Diagram INPUT/OUTPUTTABLE VDD 1 8 VDD ENBL IN OUT INVERTING 0 0 0 0 1 0 7 OUT INVERTING UCC27321-Q1 1 0 1 VDD NON 1 1 0 IN 2 INVERTING 6 OUT 0 0 0 RENBL NON 0 1 0 INVERTING ENBL 3 UCC27322-Q1 1 0 0 1 1 1 AGND 4 5 PGND Copyright © 2016,Texas Instruments Incorporated 9.3 Feature Description 9.3.1 InputStage The IN threshold has a 3.3-V logic sensitivity over the full range of VDD voltage; yet, it is equally compatible with 0-V to V signals. The inputs of UCC2732x-Q1 family of drivers are designed to withstand 500-mA reverse DD current without either damage to the device or logic upset. In addition, the input threshold turnoff of the UCC2732x-Q1 is slightly raised for improved noise immunity. The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied in typical power-supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The IN input of the driverfunctionsasadigitalgate,andisnotintendedforapplicationswhereaslow-changinginputvoltageisused to generate a switching output when the logic threshold of the input section is reached. While this may not be harmfultothedriver,theoutputofthedrivermayswitchrepeatedlyatahighfrequency. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com Feature Description (continued) Usersmustnotattempttoshapetheinputsignalstothedriverinanattempttoslowdown(ordelay)thesignalat the output. If limiting the rise or fall times to the power device is desired, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help dissipate power from the device package, as discussed in Thermal Considerations. 9.3.2 OutputStage The TrueDrive output stage is capable of supplying ±9-A peak current pulses and swings to both VDD and GND and can encourage even the most stubborn MOSFETs to switch. The pullup and pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the R of the MOSFET transistor DS(ON) when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the internal MOSFET.Thismeansthatinmanycases,externalSchottkyclampingdiodesarenotrequired. This unique bipolar and MOSFET hybrid output architecture (TrueDrive) allows efficient current sourcing at low supply voltages. The UCC2732x-Q1 family delivers 9 A of gate drive where it is most needed during the MOSFETswitchingtransition—attheMillerplateauregion—providingimprovedefficiencygains. 9.3.3 SourceandSinkCapabilitiesDuringMillerPlateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC2732x-Q1 drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging betweenthevoltagelevelsdictatedbythepowertopology,requiringthechargingordischargingofthedrain-gate capacitancewithcurrentsuppliedorremovedbythedriver. Two circuits are used to test the current capabilities of the UCC2732x-Q1 driver. In each case, external circuitry is added to clamp the output near 5 V while the device is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test, there is a transient period when the current peaked up and then settled down to a steady-state value. The noted current measurementsaremadeatatimeof200nsaftertheinputpulseisapplied,aftertheinitialtransient. The circuit in Figure 25 is used to verify the current-sink capability when the output of the driver is clamped at approximately 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC2732x-Q1 is foundtosink9AatV =15V. DD VDD UCC2732x-Q1 INPUT 1 VDD VDD 8 IN OUT DSCHOTTKY 10Ω 2 7 OUT C2 C3 + VSUPPLY 3 ENBL 6 1 µF 100 µF 5.5 V 4 AGND PGND 5 VSNS 1 µF 100 µF RSNS 0.1Ω CER ALEL Copyright © 2016,Texas Instruments Incorporated Figure25. SinkCurrentTestCircuit 12 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 Feature Description (continued) The circuit in Figure 26 is used to test the current-source capability with the output clamped to approximately 5 V withastringofZenerdiodes.TheUCC2732x-Q1isfoundtosource9AatV =15V. DD VDD UCC2732x-Q1 INPUT 1 VDD VDD 8 DSCHOTTKY IN OUT 2 7 3 ENBL OUT 6 C1µ2F C1030 µF 4D.A5D VJ 4 AGND PGND 5 VSNS RSNS 1µF 100 µF 0.1Ω CER ALEL Copyright © 2016,Texas Instruments Incorporated Figure26. SourceCurrentTestCircuit The current-sink capability is slightly stronger than the current source capability at lower V . This is due to the DD differences in the structure of the bipolar-MOSFET power output section, where the current source is a P- channelMOSFETandthecurrentsinkhasanN-channelMOSFET. In a large majority of applications, it is advantageous that the turnoff capability of a driver is stronger than the turnon capability. This helps to ensure that the MOSFET is held off during common power-supply transients that mayturnthedevicebackon. 9.3.4 VDD AlthoughquiescentVDDcurrentisverylow,totalsupplycurrentishigher,dependingontheOUTcurrentandthe programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Q ), average OUT current can be g calculatedfromEquation1: I =Q ×f OUT g where • f=frequency (1) For the best high-speed circuit performance, TI recommends two VDD bypass capacitors to prevent noise problems. TI highly recommends the use of surface-mount components. A 0.1-µF ceramic capacitor must be placed closest to the VDD-to-ground connection. In addition, a larger capacitor (such as 1-µF) with relatively low ESRmustbeconnectedinparallel,tohelpdeliverthehigh-currentpeakstotheload.Theparallelcombinationof capacitorsmustpresentalow-impedancecharacteristicfortheexpectedcurrentlevelsinthedriverapplication. 9.3.5 DriveCurrentandPowerRequirements The UCC2732x-Q1 family of drivers is capable of delivering 9 A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn an N-channel device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. An N-channel MOSFET is used in this discussion because it is the mostcommontypeofswitchingdeviceusedinhigh-frequencypower-conversionequipment. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com Feature Description (continued) Design And Application Guide For High Speed MOSFET Gate Drive Circuits and Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits contain detailed discussions of the drive current required to drive a power MOSFET and other capacitive-input switching devices. Much information is provided in tabular form to give a range of the current required for various devices at various frequencies. The information pertinent to calculating gate-drive current requirements is summarized here. See MOSFET and IGBT drivers for additionaldocumentation. When a driver is tested with a discrete capacitive load, it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor isgivenbyEquation2: E=½CV2 where • C=loadcapacitor • V=biasvoltagefeedingthedriver (2) There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a powerlossgivenbyEquation3: P=2×½CV2f where • f=switchingfrequency (3) This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditionsofthepreviousgate-drivewaveformmusthelpclarifythis. WithV =12V,C =10nF,andf=300kHz,thepowerlosscanbecalculatedasinEquation4: DD LOAD P=10nF×(12V)2×(300kHz)=0.432W (4) Witha12-Vsupply,inEquation5thisequatestoacurrentof: I=P/V=0.432W/12V=0.036A (5) The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge required to swing the drain of the device between the on and off states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specifiedconditions.UsingthegatechargeQ ,thepowerthatmustbedissipatedwhenchargingacapacitorcan g bedetermined.ThisisdonebyusingtheequivalenceQ =CeffVtoprovidetheEquation6forpower: g P=C×V2×f=Q ×V×f (6) g Equation 6 allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specificbiasvoltage. 9.3.6 Enable UCC2732x-Q1 provides an enable input for improved control of the driver operation. This input also incorporates logic-compatible thresholds with hysteresis. The input is internally pulled up to V with a 100-kΩ (typical) DD resistor for active-high operation. When ENBL is high, the device is enabled, and when ENBL is low, the device isdisabled.ThedefaultstateoftheENBLpinistoenablethedevice,andthereforecanbeleftopenforstandard operation. The output state when the device is disabled is low, regardless of the input state. See the truth table (Table2)foroperationusingenablelogic. The ENBL input is compatible with both logic signals and slow-changing analog signals. It can be directly driven, orapower-updelaycanbeprogrammedwithacapacitorbetweenENBLandAGND. 14 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 9.4 Device Functional Modes The UCC2732x-Q1 device has two functional modes; enabled when ENBL is HIGH and disabled when ENBL is LOW.Table2liststhelogicofthisdevice. Table2.DeviceLogicandModesTable ENBL IN OUT 0 0 0 0 1 0 InvertingUCC27321-Q1 1 0 1 1 1 0 0 0 0 0 1 0 NoninvertingUCC27322-Q1 1 0 0 1 1 1 Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information High-current gate driver devices are required in switching power applications for a variety of reasons. To enable fast switching of power devices and reduce associated power losses, a powerful gate driver can be employed between the PWM output of controllers or signal isolation devices and the gates of the power semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the PWM controller directly drive the gates of the switching devices. The situation may be encountered because the PWM signalfromadigitalcontrollerorsignalisolationdeviceisoftena3.3-Vor5-Vlogicsignalwhichisnotcapableof effectively turning on a power switch. A level-shifting circuitry is required to boost the logic-level signal to the gate-drive voltage to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on bipolar or MOSFET transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting and buffer drive functions. Gate drivers may also minimize the effect of switching noise by placing the high-current driver physically close to the power switch, drive gate-driver transformers and control floating power device gates, reducing power dissipation and thermal stressincontrollersbyabsorbinggate-chargepowerlosses. In summary gate drivers are extremely important components in switching power combining benefits of high- performance,low-cost,lowcomponentcount,board-spacereduction,andsimplifiedsystemdesign. 10.2 Typical Application Q1 8 6 VDD OUT 1 7 C2 VDD OUT R4 UCC27322-Q1 2 4 IN AGND INPUT 3 5 ENBL PGND ENABLE Copyright © 2016, Texas Instruments Incorporated Figure27. TypicalApplicationDiagramofUCC27322-Q1 16 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 Typical Application (continued) 10.2.1 DesignRequirements When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. The following design parameters should be used when selecting the proper gate driver device for an end application: input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, availability of independent enable and disable functions, propagation delay, power dissipation, and package type. See the example design parameters and requirementsinTable3. Table3.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Input-to-outputconfiguration Noninverting Inputthresholdtype CMOS Biassupplyvoltagelevels 12V dVDS/dt(1) 20V/ns Enablefunction Yes Propagationdelay <50ns Powerdissipation <0.45W Packagetype SOIC(8) (1) dVDS/dtisatypicalrequirementforagivendesign.Thisvaluecan beusedtofindthepeaksourceandsinkcurrentsrequiredasshown inPeakSourceandSinkCurrents. 10.2.2 DetailedDesignProcedure 10.2.2.1 Input-to-OutputConfiguration The design must specify which type of input-to-out configuration is used. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred, then a device capable of the noninverting configuration must be selected. If turning off the power MOSFET or IGBT when the input signal is in high state is preferred, then a device capable of the inverting configuration must be chosen. Based on this noninverting requirement of thisapplication,theproperdeviceistheUCC27322-Q1. 10.2.2.2 InputThresholdType The type of input voltage threshold determines the type of controller that can be used with the gate driver device. The UCC2732x-Q1 devices feature a TTL and CMOS-compatible input threshold logic, with wide hysteresis. The threshold voltage levels are low voltage and independent of the VDD supply voltage, which allows compatibility with both logic-level input signals from microcontrollers as well as higher-voltage input signals from analog controllers. See Electrical Characteristics for the actual input threshold voltage levels and hysteresis specificationsfortheUCC2732x-Q1devices. 10.2.2.3 VDDBiasSupplyVoltage The bias supply voltage to be applied to the VDD pins of the device must never exceed the values listed in Recommended Operating Conditions. However, different power switches require different voltage levels to be applied at the gate. With a wide operating range from 4.5 V to 15 V, the UCC2732x-Q1 device can be used to drive a variety of power switches, such as Si MOSFETs (V = 4.5 V, 10 V, 12 V), IGBTs (V = 15 V), and GS GE wide-bandgap power semiconductors (such as GaN, certain types of which allow no higher than 6 V to be appliedtothegateterminals). 10.2.2.4 PeakSourceandSinkCurrents Generally, the switching speed of the power switch during turnon and turnoff must be as fast as possible to minimize switching power losses. The gate driver device must be able to provide the required peak current for achievingthetargetedswitchingspeedsforthetargetedpowerMOSFET. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com Using the example of a power MOSFET, the system requirement for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dvds/dt). For example, the system requirement might state that a SPP20N60C3 power MOSFET must be turned on with a dvds/dt of 20 V/ns or higher under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC- converter application. This type of application is an inductive hard-switching application and reducing switching power loss is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET turnon event (from 400 V in the OFF state to V in ON state) must be completed in approximately DS(ON) 20 ns or less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (Q for gd SPP20N60C3 power MOSFET is 33 nC, typically) is supplied by the peak current of gate driver. According to power MOSFET inductive switching mechanism, the gate-to-source voltage of the power MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage of the power MOSFET (V ). GS(th) To achieve the targeted dvds/dt, the gate driver must be capable of providing the Q charge in 20 ns or less. In gd other words, a peak current of 1.65 A = (33 nC) / (20 ns) or higher must be provided by the gate driver. The UCC2732x-Q1 devices can provide 9-A peak sourcing or sinking current which clearly exceeds the design requirement and has the capability to meet the switching speed required. This 9-A peak sourcing or sinking currentprovidesanextramarginagainstpart-to-partvariationsintheQ parameterofthepowerMOSFETalong gd with additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus EMIoptimizations. In practical designs, the parasitic trace in the gate driver circuit of the PCB has a definitive role to play on the powerMOSFETswitchingspeed.Theeffortofthistraceinductanceistolimitthedi/dtoftheoutputcurrentpulse of the gate driver. To illustrate this effect, consider output current pulse waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle (0.5 × IPEAK × time) would equal the total gate charge of the power MOSFET (Q for SPP20N60C3 power MOSFET is 87 nC typically). If the parasitic g trace inductance limits the di/dt then a situation may occur in which the full peak current capability of the gate driver is not fully achieved in the time required to deliver the Q required for the power MOSFET switching. In g other words, the time parameter in the equation would dominate and the IPEAK value of the current pulse would be much less than the true peak current capability of the device, while the required Q is still delivered. Because g of this, the desired switching speed may not be realized, even when theoretical calculations indicate the gate driver can achieve the targeted witching speed. Thus, placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with minimal PCB trace inductance is important to realize the full peak-currentcapabilityofthegatedriver. 10.2.2.5 EnableandDisableFunction Certain applications demand independent control of the output state of the driver without involving the input signal. A pin which offers enable and disable functions achieves the requirements. For these applications, the UCC2732x-Q1devicesaresuitableastheyfeatureaninputpinandanEnablepin. 10.2.2.6 PropagationDelay The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC2732x-Q1 devices feature 25-ns turnon propagation delay and 35-ns turnoff propagation delay (typical), which ensure very little distortion and allow operation at higher frequencies. See Electrical Characteristics for the propagation and Switching Characteristics oftheUCC2732x-Q1devices. 18 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 10.2.3 ApplicationCurves IN = VDD IN = VDD ENBL= VDD ENBL= VDD V V − − −Input Voltage1 V/div −Input Voltage1 V/div VDD VDD VDD VDD OUT OUT 0 V 0 V 10nF Between Output and GND 10 nF Between Output and GND 50µs/div 50µs/div Figure28.OutputBehaviorvsV (UCC27322-Q1) Figure29.OutputBehaviorvsV (UCC27322-Q1) DD DD 11 Power Supply Recommendations Although quiescent VDD current is very low, total supply current is higher, depending on OUTA and OUTB current and the operating frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Q ), average OUT current can be g calculatedusingEquation7. I =Q ×f (7) OUT g For the best high-speed circuit performance, TI recommends two VDD bypass capacitors to prevent noise problems. TI also highly recommends using surface mount components. A 0.1-µF ceramic capacitor must be placed closest to the VDD to ground connection. In addition, a larger capacitor (such as 1 µF) with relatively low ESR must be connected in parallel to help deliver the high current peaks to the load. The parallel combination of capacitorspresentsalowimpedancecharacteristicfortheexpectedcurrentlevelsinthedriverapplication. 12 Layout 12.1 Layout Guidelines It can be a significant challenge to avoid the overshoot or undershoot and ringing issues that can arise from circuit layout. The low impedance of these drivers and their high di/dt can induce ringing between parasitic inductancesandcapacitancesinthecircuit.Takeutmostcareinthecircuitlayout. In general, position the driver physically as close to its load as possible. Place a 1-µF bypass capacitor as close to the output side of the driver as possible, connecting it to pins 1 and 8. Connect a single trace between the two VDD pins (pin 1 and pin 8); connect a single trace between PGND and AGND (pin 5 and pin 4). If a ground plane is used, it may be connected to AGND; do not extend the plane beneath the output side of the package (pins 5 to 8). Connect the load to both OUT pins (pins 7 and 6) with a single trace on the adjacent layer to the component layer; route the return current path for the output on the component side, directly over the output path. Extreme conditions may require decoupling the input power and ground connections from the output power and ground connections. The UCCx732[1,2] has a feature that allows the user to take these extreme measures, if necessary. There is a small amount of internal impedance of about 15 Ω between the AGND and PGND pins; there is also a small amount of impedance (approximately 30 Ω) between the two VDD pins. To take advantage of this feature, connect a 1-µF bypass capacitor between VDD and PGND (pins 5 and 8) and connect a 0.1-µF bypass capacitor between VDD and AGND (pins 1 and 4). Further decoupling can be achieved by connecting between the two VDD pins with a jumper that passes through a 40-MHz ferrite bead and connects bias power only to pin 8 (VDD). Even more decoupling can be achieved by connecting between AGND and PGND with a pairofanti-paralleldiodes(anodeconnectedtocathodeandcathodeconnectedtoanode). Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com 12.2 Layout Example Figure30. LayoutRecommendation 12.3 Thermal Considerations The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal characteristics of the package. For a power driver to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2732x-Q1 family of drivers is available in two different packages to cover a range of application requirements. The 8-pin SOIC (D) package has a power rating of approximately 0.5 W at T = 70°C. This limit is imposed in A conjunction with the power derating factor also given in the table. The power dissipation in our earlier example is 0.432Wwitha10-nFload,12-VV ,switchedat300kHz.Thus,onlyoneloadofthissizecouldbedrivenusing DD theDpackage.Thedifficultieswithheatremovallimitthedriveavailableintheolderpackages. The 8-pin MSOP PowerPAD (DGN) significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As illustrated in PowerPad Thermally Enhanced Package, the PowerPAD packages offer a lead-frame die pad that is exposed at the base of the package. This pad is soldered to the copper on the PCB directly underneath the package, reducing the θ to 4.7°C/W. Data is presented in JC PowerPadThermallyEnhancedPackagetoshowthatthepowerdissipationcanbequadrupledinthePowerPAD package when compared to the standard packages. The PCB must be designed with thermal lands and thermal viastocompletetheheatremovalsubsystem,assummarizedinPowerPADMadeEasy.Thisallowsasignificant improvement in heatsink capability over that available in the D package and is shown to more than double the powercapabilityoftheDpackage. NOTE The PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of thedevice. 20 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 12.4 Power Dissipation The UCC2732x-Q1 family of drivers are capable of delivering 9-A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn an N-channel device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. An N-channel MOSFET is used in this discussion because it is the mostcommontypeofswitchingdeviceusedinhigh-frequencypowerconversionequipment. Design And Application Guide For High Speed MOSFET Gate Drive Circuits and Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits contain detailed discussions of the drive current required to drive a power MOSFET and other capacitive-input switching devices. Much information is provided in tabular form to give a range of the current required for various devices at various frequencies. The information pertinenttocalculatinggatedrivecurrentrequirementsissummarizedhere. When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitorisgivenbyEquation8. 1 E= CV2 2 where • Cistheloadcapacitor • Visthebiasvoltagefeedingthedriver (8) There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a powerlossgivenbyEquation9. 1 P=2 ´ CV2f 2 where • fistheswitchingfrequency (9) This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An example using the conditions of thepreviousgate-drivewaveformhelpstoclarifythis. WithV =12V,C =10nF,andf=300kHz,thepowerlosscanbecalculatedasshowninEquation11. DD LOAD P=10nF ´ (12)2´ (300kHz)=0.432W (10) Witha12-Vsupply,thiswouldequate,asshowninEquation11,toacurrentof: P 0.432W I= = =0.036A V 12V (11) The switching load presented by a power MOSFETcan be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus theaddedchargerequiredtoswingthedrainofthedevicebetweentheONandOFFstates.Mostmanufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when chargingacapacitor.ThisisdonebyusingtheequivalenceQg=CeffVtoprovideEquation12forpower. P = C ´ V2 ´ f = Qg ´ V ´ f (12) Equation 12 allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specificbiasvoltage. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: • Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate DriveCircuits(SLUP133) • PracticalConsiderationsinHighPerformanceMOSFET,IGBTandMCTGateDriveCircuits (SLUA105) • MOSFETandIGBTdrivers • PowerPadThermallyEnhancedPackage(SLMA002) • PowerPADMadeEasy(SLMA004) 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC27321-Q1 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27322-Q1 Clickhere Clickhere Clickhere Clickhere Clickhere 13.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 13.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 13.5 Trademarks TrueDrive,PowerPAD,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 13.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 22 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

UCC27321-Q1,UCC27322-Q1 www.ti.com SLUSA13D–FEBRUARY2010–REVISEDSEPTEMBER2016 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UCC27321-Q1 UCC27322-Q1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC27321QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 27321Q & no Sb/Br) UCC27322QDGNRQ1 ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 125 EACQ & no Sb/Br) UCC27322QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 27322Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC27321-Q1, UCC27322-Q1 : •Catalog: UCC27321, UCC27322 •Enhanced Product: UCC27322-EP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC27321QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27322QDGNRQ1 HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27322QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC27321QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 UCC27322QDGNRQ1 HVSSOP DGN 8 2500 350.0 350.0 43.0 UCC27322QDRQ1 SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

None

PACKAGE OUTLINE DGN0008B PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.98 1.78 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.88 TYPICAL 1.62 4218837/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008B PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.88) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.98) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4218837/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008B PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.88) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.98) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.10 X 2.21 0.125 1.88 X 1.98 (SHOWN) 0.15 1.72 X 1.81 0.175 1.59 X 1.67 4218837/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated