Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 UCC2720x, 120-V Boot, 3-A Peak, High Frequency, High-Side and Low-Side Driver 1 Features 3 Description • DrivesTwoN-ChannelMOSFETsinHigh-Side The UCC2720x family of high-frequency N-channel 1 MOSFETdriversincludea120-Vbootstrapdiodeand andLow-SideConfiguration high-side and low-side drivers with independent • NegativeVoltageHandlingonHS(–5V) inputs for maximum control flexibility. This allows for • MaximumBootVoltageof120V N-channel MOSFET control in half-bridge, full-bridge, • MaximumVDDVoltageof20V two-switch forward, and active clamp forward converters. The low-side and the high-side gate • On-Chip0.65-VVF,0.6-Ω RDBootstrapDiode drivers are independently controlled and matched to • Greaterthan1MHzofOperation 1nsbetweentheturnonandturnoffofeachother. • 20-nsPropagationDelayTimes An on-chip bootstrap diode eliminates the external • 3-ASinkand3-ASourceOutputCurrents discrete diodes. Undervoltage lockout is provided for • 8-nsRiseand7-nsFallTimeWith1000-pFLoad both the high-side and the low-side drivers forcing the outputs low if the drive voltage is below the specified • 1-nsDelayMatching threshold. • UndervoltageLockoutforHigh-SideandLow-Side Two versions of the UCC27200 are offered. The Driver UCC27200 has high noise immune CMOS input • Specifiedfrom–40°Cto140°C thresholds while the UCC27201 has TTL compatible thresholds. 2 Applications • PowerSuppliesforTelecom,Datacom,and DeviceInformation(1) MerchantMarkets PARTNUMBER PACKAGE BODYSIZE(NOM) • Half-BridgeApplicationsandFull-Bridge SOIC(8) 3.91mm×4.90mm Converters UCC2720x SOPowerPAD™(8) 3.90mm×4.89mm • IsolatedBusArchitecture VSON(8) 4.00mm×4.00mm • Two-SwitchForwardConverters (1) For all available packages, see the orderable addendum at theendofthedatasheet. • Active-ClampForwardConverters • High-VoltageSynchronous-BuckConverters • Class-DAudioAmplifiers SimplifiedApplicationDiagram 12 V 100 V VDD Secondary Side HB Circuit HI Drive HO High CoPnWtroMller ntrol HS o LI C LO Drive Low UCC2720x V SS Isolation and Feedback Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................13 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 14 3 Description............................................................. 1 8.1 ApplicationInformation............................................14 4 RevisionHistory..................................................... 2 8.2 TypicalApplication..................................................15 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 20 6 Specifications......................................................... 4 10 Layout................................................................... 21 6.1 AbsoluteMaximumRatings......................................4 10.1 LayoutGuidelines.................................................21 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................21 6.3 RecommendedOperatingConditions.......................4 11 DeviceandDocumentationSupport................. 22 6.4 ThermalInformation..................................................5 11.1 DocumentationSupport........................................22 6.5 ElectricalCharacteristics...........................................5 11.2 RelatedLinks........................................................22 6.6 TypicalCharacteristics..............................................8 11.3 CommunityResources..........................................22 7 DetailedDescription............................................ 12 11.4 Trademarks...........................................................22 7.1 Overview.................................................................12 11.5 ElectrostaticDischargeCaution............................22 7.2 FunctionalBlockDiagram.......................................12 11.6 Glossary................................................................22 7.3 FeatureDescription.................................................12 12 Mechanical,Packaging,andOrderable Information........................................................... 22 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(November2008)toRevisionC Page • AddedDeviceInformationtable,RevisionHistorysection,PinConfigurationandFunctionssection,Specifications section,DetailedDescriptionsection,ApplicationandImplementationsection,PowerSupplyRecommendations section,Layoutsection,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderable Informationsection................................................................................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 5 Pin Configuration and Functions DPackage 8-PinSOIC DDAPackage TopView 8-PinSOPowerPAD TopView VDD 1 8 LO VDD 1 8 LO HB 2 7 VSS HB 2 7 VSS PAD HO 3 6 LI HO 3 6 LI HS 4 5 HI HS 4 5 HI DRMPackage 8-PinVSON TopView VDD 1 8 LO HB 2 7 VSS PAD HO 3 6 LI HS 4 5 HI PinFunctions PIN I/O DESCRIPTION NAME NO. High-sidebootstrapsupply.Thebootstrapdiodeison-chipbuttheexternalbootstrapcapacitorisrequired. HB 2 I Connectpositivesideofthebootstrapcapacitortothispin.TypicalrangeofHBbypasscapacitoris 0.022μFto0.1μF,thevalueisdependantonthegatechargeofthehigh-sideMOSFEThowever. HI 5 I High-sideinput. HO 3 O High-sideoutput.Connecttothegateofthehigh-sidepowerMOSFET. High-sidesourceconnection.Connecttosourceofhigh-sidepowerMOSFET.Connectnegativesideof HS 4 I bootstrapcapacitortothispin. LI 6 I Low-sideinput. LO 8 O Low-sideoutput.Connecttothegateofthelow-sidepowerMOSFET. Positivesupplytothelowergatedriver.DecouplethispintoVSS(GND).Typicaldecouplingcapacitor VDD 1 I rangeis0.22μFto1μF. VSS 7 O Negativesupplyterminalforthedevicewhichisgenerallygrounded. UsedontheDDAandDRMpackagesonly.ElectricallyreferencedtoVSS(GND)(1).Connecttoalarge PowerPAD PAD — thermalmasstraceorGNDplanetodramaticallyimprovethermalperformance. (1) VSSpinandtheexposedthermaldiepadareinternallyconnected. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperature,unlessnoted,allvoltagesarewithrespecttoV .(1) SS MIN MAX UNIT Supplyvoltage,V (2) –0.3 20 V DD InputvoltagesonLIandHI,V ,V –0.3 20 V LI HI DC –0.3 V +0.3 DD OutputvoltageonLO,V V LO Repetitivepulse<100ns(3) –2 V +0.3 DD DC V –0.3 V +0.3 HS HB OutputvoltageonHO,V V HO Repetitivepulse<100ns(3) V –2 V +0.3 HS HB DC –1 120 VoltageonHS,V V HS Repetitivepulse<100ns(3) –5 120 VoltageonHB,V –0.3 120 V HB VoltageonHB-HS –0.3 20 V (Dpackage)(4) 1.3 PowerdissipationatT =25°C (DDApackage)(4) 2.7 W A (DRMpackage)(4) 3.3 Leadtemperature(soldering,10s) 300 °C Operatingvirtualjunctiontemperature,T –40 150 °C J Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoV .Currentsarepositiveinto,negativeoutofthespecifiedterminal. ss (3) Valuesareverifiedbycharacterizationandarenotproductiontested. (4) ThisdatawastakenusingtheJEDECproposedhigh-KtestPCB.SeeThermalInformationfordetails. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Supplyvoltage 8 12 17 V DD –1 105 V VoltageonHS V HS repetitivepulse<100ns –5 110 V VoltageonHB V +8 115 V HB HS VoltageslewrateonHS 50 V/ns T Operatingjunctiontemperature –40 140 °C J 4 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 6.4 Thermal Information P =(150–T )/θ ,unlessotherwisenoted. DISS A JA UCC27200,UCC27201 THERMALMETRIC(1) D(SOIC) DDA(HSOP) DRM(VSON) UNIT 8PINS 8PINS 8PINS R Junction-to-ambientthermalresistance 106.5 40.5 36.2 °C/W θJA R Junction-to-case(top)thermalresistance 52.9 49 41.6 °C/W θJC(top) R Junction-to-boardthermalresistance 46.6 10.2 13.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 9.6 3.1 0.6 °C/W JT ψ Junction-to-boardcharacterizationparameter 46.1 9.7 13.4 °C/W JB R Junction-to-case(bottom)thermalresistance — 1.5 3.1 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange,V =V =12V,V =V =0V,NoloadonLOorHO,T =T =–40°Cto DD HB HS SS A J 140°C,(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENTS I VDDquiescentcurrent V =V =0 0.4 0.8 DD LI HI UCC27200 2.5 4 I VDDoperatingcurrent f=500kHz,C =0 DDO LOAD UCC27201 3.8 5.5 mA I Bootvoltagequiescentcurrent V =V =0V 0.4 0.8 HB LI HI I Bootvoltageoperatingcurrent f=500kHz,C =0 2.5 4 HBO LOAD I HBtoV quiescentcurrent V =V =110V 0.0005 1 uA HBS SS HS HB I HBtoV operatingcurrent f=500kHz,C =0 0.1 mA HBSO SS LOAD INPUT V Inputrisingthreshold 5.8 8 HIT V Inputfallingthreshold UCC27200 3 5.4 LIT V Inputvoltagehysteresis 0.4 V IHYS V Inputvoltagethreshold 1.7 2.5 HIT V Inputvoltagethreshold UCC27201 0.8 1.6 LIT V InputvoltageHysteresis 100 mV IHYS R Inputpulldownresistance 100 200 350 kΩ IN UNDERVOLTAGEPROTECTION(UVLO) VDDrisingthreshold 6.2 7.1 7.8 VDDthresholdhysteresis 0.5 V VHBrisingthreshold 5.8 6.7 7.2 VHBthresholdhysteresis 0.4 Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com Electrical Characteristics (continued) overoperatingfree-airtemperaturerange,V =V =12V,V =V =0V,NoloadonLOorHO,T =T =–40°Cto DD HB HS SS A J 140°C,(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT BOOTSTRAPDIODE V Low-currentforwardvoltage I –HB=100μA 0.65 0.85 F VDD V V High-currentforwardvoltage I –HB=100mA 0.85 1.1 FI VDD R Dynamicresistance,ΔVF/ΔI I –HB=100mAand80mA 0.6 1 Ω D VDD LOGATEDRIVER V Low-leveloutputvoltage I =100mA 0.18 0.4 LOL LO V High-leveloutputvoltage ILO=–100mA, TJ=–40to125°C 0.25 0.4 V LOH VLOH=VDD–VLO TJ=–40to140°C 0.25 0.42 Peakpullupcurrent V =0V 3 LO A Peakpulldowncurrent V =12V 3 LO HOGATEDRIVER V Low-leveloutputvoltage I =100mA 0.18 0.4 HOL HO V High-leveloutputvoltage IHO=–100mA, TJ=–40to125°C 0.25 0.4 V HOH VHOH=VHB–VHO TJ=–40to140°C 0.25 0.42 Peakpullupcurrent V =0V 3 HO A Peakpulldowncurrent V =12V 3 HO PROPAGATIONDELAYS T =–40to125°C 20 45 J T V fallingtoV falling C =0 DLFF LI LO LOAD T =–40to140°C 20 50 J T =–40to125°C 20 45 J T V fallingtoV falling C =0 DHFF HI HO LOAD T =–40to140°C 20 50 J ns T =–40to125°C 20 45 J T V risingtoV rising C =0 DLRR LI LO LOAD T =–40to140°C 20 50 J T =–40to125°C 20 45 J T V risingtoV rising C =0 DHRR HI HO LOAD T =–40to140°C 20 50 J DELAYMATCHING T LION,HIOFF 1 7 MON ns T LIOFF,HION 1 7 MOFF OUTPUTRISEANDFALLTIME t LO,HO C =1000pF 8 R LOAD ns t LO,HO C =1000pF 7 F LOAD t LO,HO(3Vto9V) C =0.1μF 0.35 0.6 R LOAD us t LO,HO(3Vto9V) C =0.1μF 0.3 0.6 F LOAD MISCELLANEOUS Minimuminputpulsewidththat 50 changestheoutput ns Bootstrapdiodeturn-offtime I =20mA,I =0.5A(1)(2) 20 F REV (1) TypicalvaluesforT =25°C A (2) I :Forwardcurrentappliedtobootstrapdiode,I :Reversecurrentappliedtobootstrapdiode. F REV 6 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 LI Input (HI, LI) HI TDLRR, TDHRR LO Output (HO, LO) TDLFF, TDHFF HO TMON TMOFF Figure1. TimingDiagrams Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 6.6 Typical Characteristics 10.0 10.0 VDD=12V VDD=12V 150oC NoLoadonOutputs NoLoadonOutputs 25oC A A m 150oC m 125oC - - Current 125oC Current Operating 1.0 Operating 1.0 -40oC IDDO- -40oC 25oC IDDO- 0.1 0.1 10 100 1000 10 100 1000 Frequency-kHz Frequency-kHz Figure2.UCC27200IDDOperatingCurrentvsFrequency Figure3.UCC27201IDDOperatingCurrentvsFrequency 10.0 1.0 HB=12V HB=12V NoLoadonOutputs NoLoadonOutputs mA 150oC mA urrent- 125oC Current- 0.1 150oC C g perating 1.0 Operatin -O 25oC O- 0.01 25oC O S B B H -40oC H I I 125oC -40oC 0.1 0.001 10 100 1000 10 100 1000 Frequency-kHz Frequency-kHz Figure4.BootVoltageOperatingCurrentvsFrequency Figure5.HBtoVSSOperatingCurrentvsFrequency 50 2.0 % T=25oC T=25oC - e g e/VVoltaDD 48 Rising Voltage-V 1.8 Rising oltag 46 hold 1.6 Falling V s hreshold 44 Falling nputThre 1.4 T I put LI- In 42 HI, 1.2 - LI HI, 40 1.0 8 10 12 14 16 18 20 8 10 12 14 16 18 20 VDD-SupplyVoltage-V VDD-SupplyVoltage-V Figure6.UCC27200InputThresholdvsSupplyVoltage Figure7.UCC27201InputThresholdvsSupplyVoltage 8 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 Typical Characteristics (continued) 50 2.0 % VDD=12V VDD=12V - e g olta 48 -V 1.8 V e VDD Rising oltag Rising oltage/ 46 holdV 1.6 hresholdV 44 Falling nputThres 1.4 Falling T I put LI- In 42 HI, 1.2 - LI HI, 40 1.0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TA-Temperature-oC TA-Temperature-oC Figure8.UCC27200InputThresholdvsTemperature Figure9.UCC27201InputThresholdvsTemperature 0.45 0.45 0.40 ILO=IHO=-100mA VDD=VHB=16V 0.40 ILO=IHO=100mA V 0.35 VDD=VHB=12V V 0.35 Voltage- 0.30 VDD=VHB=8V Voltage- 0.30 VDD=VHB=1V2DVD=VHB=16V OOutput 00..2250 OOutput 00..2250 VDD=VHB=8V LO/H 0.15 LO/H 0.15 VOH- 0.10 VDD=VHB=20V VOL- 0.10 0.05 0.05 VDD=VHB=20V 0.0 0.0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 T -Temperature-oC T -Temperature-oC A A Figure10.LOandHOHigh-LevelOutputVoltagevs Figure11.LOandHOLow-LevelOutputVoltagevs Temperature Temperature 7.8 0.8 7.6 0.7 7.4 0.6 VDDUVLOHysteresis VDDRisingThreshold 7.2 hreshold-V 676...608 ysteresis-V 00..45 T H 0.3 HBUVLOHysteresis 6.4 HBRisingThreshold 0.2 6.2 0.1 6.0 5.8 0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 T -Temperature-oC T -Temperature-oC A A Figure12.UndervoltageLockoutThresholdvsTemperature Figure13.UndervoltageLockoutThresholdHysteresisvs Temperature Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com Typical Characteristics (continued) 36 36 V =V =12V V =V =12V 34 DD HD 34 DD HB TDHFF 32 32 s 30 TDHRR ns 30 elay-n 2268 Delay- 2268 D n Propagation 222204 Propagatio 222204 TDTLDRLRFF 18 TDLFF 18 TDHFF 16 16 TDLRR TDHRR 14 14 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 T -Temperature-oC T -Temperature-oC A A Figure14.UCC27200PropagationDelaysvsTemperature Figure15.UCC27201PropagationDelaysvsTemperature 26 26 T=25oC T=25oC 24 24 ns ns - - nDelay 22 LIFalling nDelay 22 LIFalling opagatio 20 HIFalling LIRising opagatio LIRising Pr Pr 20 HIRising 18 HIRising HIFalling 16 18 8 10 12 14 16 18 20 8 10 12 14 16 18 20 V =V -SupplyVoltage-V V =V -SupplyVoltage-V DD HB DD HB Figure16.UCC27200PropagationDelayvsSupplyVoltage Figure17.UCC27201PropagationDelayvsSupplyVoltage 3.5 7 V =V =12V V =V =12V DD HB DD HB 3.0 6 5 nt-A 2.5 Pull-UpCurrent Pull-DownCurrent g-ns 4 Curre 2.0 Matchin 3 UCC27200TUMCOCF2F7201TMOFF Output 1.5 Delay 2 UCC27201TMON UCC27200TMON I,I-LOHO 1.0 0.5 1 0 0 -50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10 12 TA-Temperature-oC VLO,VHO-OutputVoltage-V Figure18.DelayMatchingvsTemperature Figure19.OutputCurrentvsOutputVoltage 10 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 Typical Characteristics (continued) 100.0 700 InputsLow 600 T=25oC 10.0 A m 500 - mA ent nt- 1.0 Curr 400 IHB urre ply deC 0.1 Sup 300 IDD o - Di I,IDDHB 200 0.01 100 0.001 0 0.5 0.6 0.7 0.8 0.9 0 4 8 12 16 20 DiodeVoltage-V V ,V -SupplyVoltage-V DD HB Figure20.DiodeCurrentvsDiodeVoltage Figure21.QuiescentCurrentvsSupplyVoltage Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 7 Detailed Description 7.1 Overview The UCC27200 and UCC27201 are high-side and low-side drivers. The high-side and low-side each have independent inputs which allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27200 and UCC27201. The UCC27200 is the CMOS compatible input version and the UCC27201 is the TTL or logic compatible version. The high-side driver is referenced to the switch node (HS) which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions containedaretheinputstages,UVLOprotection,levelshift,bootdiode,andoutputdriverstages. 7.2 Functional Block Diagram 2 HB UVLO Level 3 HO Shift 4 HS HI 5 VDD 1 UVLO 8 LO LI 6 7 VSS Copyright © 2016,Texas Instruments Incorporated 7.3 Feature Description 7.3.1 InputStages The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200 is 200‑kΩ nominal and input capacitance is approximately 2 pF. The 200 kΩ is a pulldown resistance to VSS (ground). The CMOS compatible input of the UCC27200 provides a rising threshold of 48% of VDD and falling thresholdof45%ofVDD.TheinputsoftheUCC27200areintendedtobedrivenfrom0toVDDlevels. The input stages of the UCC27201 incorporate an open drain configuration to provide the lower input thresholds. The input impedance is 200-kΩ nominal and input capacitance is approximately 4 pF. The 200 kΩ is a pulldown resistance to VSS (ground). The logic level compatible input provides a rising threshold of 1.7 V and a falling thresholdof1.6V. 7.3.2 UndervoltageLockout(UVLO) The bias supplies for the high-side and low-side drivers have undervoltage lockout (UVLO) protection. VDD as well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLOrisingthresholdis6.7Vwith0.4-Vhysteresis. 12 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 Feature Description (continued) 7.3.3 LevelShift The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellentdelaymatchingwiththelow-sidedriver. 7.3.4 BootDiode The boot diode necessary to generate the high-side bias is included in the UCC2720x family of drivers. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliableoperation. 7.3.5 OutputStages TheoutputstagesaretheinterfacetothepowerMOSFETsinthepowertrain.Highslewrate,lowresistanceand high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low- sideoutputstageisreferencedfromVDDtoVSSandthehigh-sideisreferencedfromVHBtoVHS. 7.4 Device Functional Modes The device operates in normal mode and UVLO mode. See Undervoltage Lockout (UVLO) for more information onUVLOoperationmode.Innormalmode,theoutputstageisdependentonthesatesoftheHIandLIpins. Table1.DeviceLogicTable HIPIN LIPIN HO(1) LO(2) L L L L L H L H H L H L H H H H (1) HOismeasuredwithrespecttotheHS. (2) LOismeasuredwithrespecttotheVSS. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information Toeffectfastswitchingofpowerdevicesandreduceassociatedswitchingpowerlosses,apowerfulgatedriveris employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN and PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power becausetheylacklevel-shiftingcapability.Gatedriverseffectivelycombineboththelevel-shiftingandbuffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gatechargepowerlossesfromthecontrollerintothedriver. 14 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 8.2 Typical Application + + + Copyright © 2016,Texas Instruments Incorporated Figure22. Open-LoopHalf-BridgeConverter Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 8.2.1 DesignRequirements Forthisdesignexample,usetheparameterslistedinTable2. Table2.UCC27201DesignRequirements DESIGNPARAMETER EXAMPLEVALUE SupplyVoltage,VDD 12V VoltageonHS,VHS 0Vto100V VoltageonHB,VHB 12Vto112V Output 4V,20A Frequency 200kHz 8.2.2 DetailedDesignProcedure 8.2.2.1 SwitchingtheMOSFETs Achieving optimum drive performance at high frequency efficiently requires special attention to layout and minimizing parasitic inductances. Take care at the driver die and package level as well as the PCB layout to reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance elements and current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its CGS capacitance. L bond wire L trace L pin 1 VDD I SOURCE Cvdd Rsource L trace Driver L bond wire L pin Rg Output 8 Stage LO I sink Rsink Cgs L bond wire L pin L trace L trace 7 Vss Figure23. MOSFETDrivePathsandCircuitParasitics The I current charges the C gate capacitor and the I current discharges it. The rise and fall time of SOURCE GS SINK the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time. Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the actualswitchingprocessandlimitationsduetoparasiticinductances. 16 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 12 12 11 11 10 9 10 8 9 7 8 6 A 5 7 LOFalling,Vor 1234 oltage,V 456 V 0 O 1 L 3 2 2 3 1 4 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 t,ns 2 VVoollttaaggee 3 CCuurrrreenntt 2 1 0 1 2 3 4 5 LOCurrent,A Figure24.TurnoffVoltageandCurrentvsTime Figure25.TurnoffVoltageandCurrentSwitchingDiagram Turning off the MOSFET must be achieved as fast as possible to minimize switching losses. For this reason the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is specified as 0.18 V at 100-mA DC current implying 1.8-Ω R . With 12-V drive voltage, no parasitic inductance and a DS(on) linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately 3.3 A as shown in Figure 19. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The internal parasitic inductance of the 8-pin SOIC package is estimated to be 2 nH including bond wires and leads. The8-pinVSONpackagereducestheinternalparasiticinductancesbymorethan50%. Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and falltimeof7nsisconservativelyrated. Figure26.V andV RiseTime,1-nFLoad,5ns/Div Figure27.V andV FallTime,1-nFLoad,5-ns/Div LO HO LO HO Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 8.2.2.2 DynamicSwitchingoftheMOSFETs The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold voltage. Using the turnoff case as the example, when the gate to source threshold voltage is reached the drain voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turnoff plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be removed (Miller charge) makes good driver performance necessary for efficient switching. An open-loop half bridge power converter was used to evaluate performance in actual applications. The schematic of the half- bridgeconverterisshowninFigure22.TheturnoffwaveformsoftheUCC27200drivingtwoMOSFETsinparallel isshowninFigure28andFigure29. Figure28.V FallTimeinHalf-BridgeConverter Figure29.V FallTimeinHalf-BridgeConverter LO HO 8.2.2.2.1 DelayMatchingandNarrowPulseWidths The total delays encountered in the PWM, driver and power stage must be considered for a number of reasons, primarily delay in current limit response. Also to be considered are differences in delays between the drivers which can lead to various concerns depending on the topology. The sync-buck topology switching requires careful selection of dead time between the high-side and low-side switches to avoid cross conduction and excessive body diode conduction. Bridge topologies can be affected by a resulting V/s imbalance on the transformerifthereisimbalanceinthehighandlow-sidepulsewidthsinasteadystatecondition. Narrow pulse width performance is an important consideration when transient and short circuit conditions are encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very narrowpulsesmaybeencounteredinsoftstart,largeloadtransients,andshort-circuitconditions. The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and narrow pulse width performance. The delay matching waveforms are shown in Figure 30 and Figure 31. The UCC2720xdrivernarrowpulseperformanceisshowninFigure32andFigure33. 18 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 Figure30.V andV RisingEdgeDelayMatching Figure31.V andV FallingEdgeDelayMatching LO HO LO HO Figure32.20-nsInputPulseDelayMatching Figure33.10-nsInputPulseDelayMatching 8.2.2.3 BootDiodePerformance The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high-side bias internally. The characteristics of this diode are important to achieve efficient, reliable operation. The DC characteristics to consider are V and dynamic resistance. A low V and high dynamic resistance results in a F F high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V V and dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic F characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified with no conditions can be misleading. Diode recovery times at no forward current (I ) can be noticeably less than F with forward current applied. The UCC2720x boot diode recovery is specified at 20 ns at I = 20 mA, F I =0.5A.At0-mAI thereverserecoverytimeis15ns. REV F Anotherlessobviousconsiderationishowthestoredchargeofthediodeisaffectedbyappliedvoltage.Onevery switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often lessthanacomparableSchottkydiode. Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 8.2.3 ApplicationCurves Figure34.V FallTimeinHalf-BridgeConverter Figure35.V FallTimeinHalf-BridgeConverter LO HO 9 Power Supply Recommendations The bias supply voltage range for which the device is rated to operate is from 8 V to 17 V. The lower end of this range is governed by the internal UVLO protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolutemaximumvoltageratingoftheVDDpinofthedevice(whichisastressrating).Keepinga3-Vmarginto allow for transient voltage spikes, the maximum voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that, while operating at or near the 8-V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF) threshold which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system start-up,thedevicedoesnotbeginoperationuntiltheVDDpinvoltagehasexceededabovetheV(ON)threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, recognizing that the charge for source current pulses delivered by the HO pin is also supplied through the same VDD pin is important. As a result, every time a current is sourced out of the HO pin a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI recommends using a capacitor in the range of 0.22 uF to 4.7 uF between VDD and GND. In a similar manner, the current pulses delivered by the LO pin are sourced from the HB pin. Therefore, TI recommends a 0.022-uF to 0.1-uF localdecouplingcapacitorbetweentheHBandHSpins. 20 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 www.ti.com SLUS746C–DECEMBER2006–REVISEDAPRIL2016 10 Layout 10.1 Layout Guidelines Toimprovetheswitchingcharacteristicsandefficiencyofadesign,thefollowinglayoutrulesmustbefollowed. • PlacethedriverascloseaspossibletotheMOSFETs. • PlacetheV andV (bootstrap)capacitorsascloseaspossibletothedriver. DD HB • Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFETbutmustnotbeinthehighcurrentpathoftheMOSFET(s)drainorsourcecurrent. • UsesimilarrulesfortheHSnodeasforGNDforthehigh-sidedriver. • Use wide traces for LO and HO closely following the associated GND or HS traces. 60-mil to 100-mil width is preferablewherepossible. • Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For GND the number of vias must be a consideration of the thermal pad requirements as well as parasitic inductance. • Avoid L and H (driver input) going close to the HS node or any other high dV/dT traces that can induce I I significantnoiseintotherelativelyhighimpedanceleads. • Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can evenleadtodecreasedreliabilityofthewholesystem. 10.2 Layout Example Figure36. ExampleComponentPlacement Copyright©2006–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UCC27200 UCC27201

UCC27200,UCC27201 SLUS746C–DECEMBER2006–REVISEDAPRIL2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • QFN/SONPCBAttachment,SLUA271 • PowerPADThermallyEnhancedPackage,SLMA002 • PowePADMadeEasy,SLMA004 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UCC27200 Clickhere Clickhere Clickhere Clickhere Clickhere UCC27201 Clickhere Clickhere Clickhere Clickhere Clickhere 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks PowerPAD,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 22 SubmitDocumentationFeedback Copyright©2006–2016,TexasInstrumentsIncorporated ProductFolderLinks:UCC27200 UCC27201

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCC27200D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27200 & no Sb/Br) UCC27200DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200 & no Sb/Br) UCC27200DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27200 & no Sb/Br) UCC27200DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27200 & no Sb/Br) UCC27200DRMR ACTIVE VSON DRM 8 3000 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 140 27200 & no Sb/Br) UCC27200DRMT ACTIVE VSON DRM 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 140 27200 & no Sb/Br) UCC27201D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27201 & no Sb/Br) UCC27201DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201 & no Sb/Br) UCC27201DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201 & no Sb/Br) UCC27201DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 140 27201 & no Sb/Br) UCC27201DRMR ACTIVE VSON DRM 8 3000 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201 & no Sb/Br) UCC27201DRMT ACTIVE VSON DRM 8 250 Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 140 27201 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC27200 : •Automotive: UCC27200-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCC27200DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Power PAD UCC27200DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27200DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27200DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Power PAD UCC27201DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27201DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCC27200DDAR SOPowerPAD DDA 8 2500 364.0 364.0 27.0 UCC27200DR SOIC D 8 2500 340.5 338.1 20.6 UCC27200DRMR VSON DRM 8 3000 367.0 367.0 35.0 UCC27200DRMT VSON DRM 8 250 210.0 185.0 35.0 UCC27201DDAR SOPowerPAD DDA 8 2500 364.0 364.0 27.0 UCC27201DR SOIC D 8 2500 340.5 338.1 20.6 UCC27201DRMR VSON DRM 8 3000 367.0 367.0 35.0 UCC27201DRMT VSON DRM 8 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4202561/G

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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