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PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC2906DW NRND SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 70 UC2906DW & no Sb/Br) UC2906DWG4 NRND SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 70 UC2906DW & no Sb/Br) UC2906DWTR NRND SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 70 UC2906DW & no Sb/Br) UC2906N NRND PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 70 UC2906N & no Sb/Br) UC2906NG4 NRND PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 70 UC2906N & no Sb/Br) UC2906Q NRND PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 70 UC2906Q & no Sb/Br) UC3906DW NRND SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW & no Sb/Br) UC3906DWG4 NRND SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW & no Sb/Br) UC3906DWTR NRND SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW & no Sb/Br) UC3906DWTRG4 NRND SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW & no Sb/Br) UC3906N NRND PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -20 to 70 UC3906N & no Sb/Br) UC3906NG4 NRND PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -20 to 70 UC3906N & no Sb/Br) UC3906Q NRND PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR -20 to 70 UC3906Q & no Sb/Br) UC3906QG3 NRND PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR -20 to 70 UC3906Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2014 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UC2906DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 UC3906DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2014 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UC2906DWTR SOIC DW 16 2000 367.0 367.0 38.0 UC3906DWTR SOIC DW 16 2000 367.0 367.0 38.0 PackMaterials-Page2

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4215152/B 04/2017 PACKAGE OUTLINE FN0020A PLCC - 4.57 mm max height SCALE 1.300 PLASTIC CHIP CARRIER .180 MAX B .350-.356 [4.57] [8.89-9.04] .020 MIN NOTE 3 [0.51] A (.008) 3 1 20 [0.2] 4 18 PIN 1 ID .350-.356 (OPTIONAL) .283-.339 [8.89-9.04] [7.19-8.61] NOTE 3 8 14 9 13 .090-.120 TYP [2.29-3.04] 20X .026-.032 [0.66-0.81] C SEATING PLANE 20X .013-.021 [0.33-0.53] .004 [0.1] C 16X .050 .007 [0.18] C A B [1.27] .385-.395 [9.78-10.03] TYP 4215152/B 04/2017 NOTES: 1. All linear dimensions are in inches. Any dimensions in brackets are in millimeters. Any dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Dimension does not include mold protrusion. Maximum allowable mold protrusion .01 in [0.25 mm] per side. 4. Reference JEDEC registration MS-018. www.ti.com

4215152/B 04/2017 EXAMPLE BOARD LAYOUT FN0020A PLCC - 4.57 mm max height PLASTIC CHIP CARRIER SYMM (R.002 ) TYP 20X (.096 ) 3 1 20 [0.05] [2.45] 20X (.025 ) [0.64] 4 18 SYMM (.327) [8.3] 16X (.050 ) [1.27] 14 8 9 13 (.327) [8.3] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X .002 MIN .002 MAX EXPOSED METAL EXPOSED METAL [0.05] [0.05] ALL AROUND ALL AROUND METAL SOLDER MASK SOLDER MASK METAL UNDER OPENING OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4215152/B 04/2017 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN FFNN00002200AA PPLLCCCC -- 44..5577 mmmm mmaaxx hheeiigghhtt PPLLAASSTTIICC CCHHIIPP CCAARRRRIIEERR SYMM (R.002 ) TYP 20X (.096 ) 3 1 20 [0.05] [2.45] 20X (.025 ) [0.64] 4 18 SYMM (.327) [8.3] 16X (.050 ) [1.27] 14 8 9 13 (.327) [8.3] SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4215152/B 04/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height SMALL OUTLINE INTEGRATED CIRCUIT Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4040000-2/H

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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