UC3842B, UC3843B, UC2842B, UC2843B High Performance Current Mode Controllers The UC3842B, UC3843B series are high performance fixed frequency current mode controllers. They are specifically designed for http://onsemi.com Off−Line and DC−DC converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error PDIP−8 N SUFFIX amplifier, current sensing comparator, and a high current totem pole CASE 626 output ideally suited for driving a power MOSFET. 8 Also included are protective features consisting of input and 1 reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, programmable output deadtime, and a latch for single pulse metering. SOIC−14 D SUFFIX These devices are available in an 8−pin dual−in−line and surface 14 CASE 751A mount (SOIC−8) plastic package as well as the 14−pin plastic surface 1 mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage. The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off), SOIC−8 8 D1 SUFFIX ideally suited for off−line converters. The UCX843B is tailored for CASE 751 lower voltage applications having UVLO thresholds of 8.5 V (on) and 1 7.6 V (off). Features • Trimmed Oscillator for Precise Frequency Control PIN CONNECTIONS • Oscillator Frequency Guaranteed at 250 kHz • Current Mode Operation to 500 kHz Compensation 1 8 Vref • Voltage Feedback 2 7 VCC Automatic Feed Forward Compensation • Current Sense 3 6 Output • Latching PWM for Cycle−By−Cycle Current Limiting RT/CT 4 5 GND Internally Trimmed Reference with Undervoltage Lockout (Top View) • High Current Totem Pole Output • Undervoltage Lockout with Hysteresis Compensation 1 14 Vref • Low Startup and Operating Current NC 2 13 NC • This is a Pb−Free and Halide−Free Device Voltage Feedback 3 12 VCC NC 4 11 VC VCC 7(12) Current Sense 5 10 Output Vref 5.0V VCC NC 6 9 GND Undervoltage 8(14) R Reference Lockout RT/CT 7 8 Power Ground (Top View) R UndeVrvreofltage VC Lockout 7(11) RT/CT Output ORDERING INFORMATION Oscillator See detailed ordering and shipping information in the package 4(7) Latching 6(10) dimensions section on page 17 of this data sheet. Voltage PWM Power Feedback + Ground Input - 5(8) DEVICE MARKING INFORMATION 2(3) Error Current See general marking information in the device marking Output Amplifier Sense section on page 19 of this data sheet. Compensation 3(5)Input 1(1) GND 5(9) Pin numbers in parenthesis are for the D suffix SOIC−14 package. Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: September, 2013 − Rev. 17 UC3842B/D

UC3842B, UC3843B, UC2842B, UC2843B MAXIMUM RATINGS Rating Symbol Value Unit Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, VC 30 V Total Power Supply and Zener Current (ICC + IZ) 30 mA Output Current, Source or Sink IO 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 (cid:2)J Current Sense, Voltage Feedback, Vref and Rt/Ct Inputs Vin −0.3 to +5.5 V Compensation Vcomp −0.3 to +7.2 V Output Vo −0.3 to VCC or V VC +0.3 Error Amp Output Sink Current IO 10 mA Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SOIC−14 Case 751A Maximum Power Dissipation @ TA = 25°C PD 862 mW Thermal Resistance, Junction−to−Air R(cid:3)JA 145 °C/W D1 Suffix, Plastic Package, SOIC−8 Case 751 Maximum Power Dissipation @ TA = 25°C PD 702 mW Thermal Resistance, Junction−to−Air R(cid:3)JA 178 °C/W N Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 25°C PD 1.25 W Thermal Resistance, Junction−to−Air R(cid:3)JA 100 °C/W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature TA °C UC3842B, UC3843B 0 to 70 UC2842B, UC2843B −25 to +85 UC2843D −40 to +85 UC3842BV, UC3843BV −40 to +105 Storage Temperature Range Tstg −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard JESD22-A114B Machine Model Method 200 V per JEDEC Standard JESD22-A115-A 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78 http://onsemi.com 2

UC3842B, UC3843B, UC2842B, UC2843B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.) UC284XB, UC2843D UC384XB, XBV Characteristics Symbol Min Typ Max Min Typ Max Unit REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV Temperature Stability TS − 0.2 − − 0.2 − mV/°C Total Output Variation over Line, Load, and Temperature Vref V UC284XB 4.9 − 5.1 4.82 − 5.18 UC2843D 4.82 − 5.18 Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − (cid:2)V Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV Output Short Circuit Current ISC −30 −85 −180 −30 −85 −180 mA OSCILLATOR SECTION Frequency fOSC kHz TJ = 25°C 49 52 55 49 52 55 TA = Tlow to Thigh 48 − 56 48 − 56 TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) 225 250 275 225 250 275 Frequency Change with Voltage (VCC = 12 V to 25 V) (cid:4)fOSC/(cid:4)V − 0.2 1.0 − 0.2 1.0 % Frequency Change with Temperature, TA = Tlow to Thigh (cid:4)fOSC/(cid:4)T − 1.0 − − 0.5 − % Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V Discharge Current (VOSC = 2.0 V) Idischg mA TJ = 25°C, TA = Tlow to Thigh 7.8 8.3 8.8 7.8 8.3 8.8 UC284XB, UC384XB 7.5 − 8.8 7.6 − 8.8 UC2843D, UC384XBV − − − 7.2 − 8.8 ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) UC284XB VFB 2.45 2.5 2.55 2.42 2.5 2.58 V UC2843D 2.42 2.5 2.58 Input Bias Current (VFB = 5.0 V) IIB − −0.1 −1.0 − −0.1 −2.0 (cid:2)A Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB Output Current mA Sink (VO = 1.1 V, VFB = 2.7 V) ISink 2.0 12 − 2.0 12 − Source (VO = 5.0 V, VFB = 2.3 V) ISource −0.5 −1.0 − −0.5 −1.0 − Output Voltage Swing V High State (RL = 15 k to ground, VFB = 2.3 V) VOH 5.0 6.2 − 5.0 6.2 − Low State (RL = 15 k to Vref, VFB = 2.7 V) VOL UC284XB, UC384XB − 0.8 1.1 − 0.8 1.1 UC2843D, UC384XBV − − − − 0.8 1.2 3. Adjust VCC above the Startup threshold before setting to 15 V. 4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV, UC2843D Thigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B, UC2843D; +105°C for UC3842BV, UC3843BV http://onsemi.com 3

UC3842B, UC3843B, UC2842B, UC2843B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.) UC284XB, UC2843D UC384XB, XBV Characteristics Symbol Min Typ Max Min Typ Max Unit CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 5 and 6) AV V/V UC2843D, UC284XB, UC384XB 2.85 3.0 3.15 2.85 3.0 3.15 UC384XBV − − − 2.85 3.0 3.25 Maximum Current Sense Input Threshold (Note 5) Vth V UC2843D, UC284XB, UC384XB 0.9 1.0 1.1 0.9 1.0 1.1 UC384XBV − − − 0.85 1.0 1.1 Power Supply Rejection Ratio (VCC = 12 V to 25 V, Note 5) PSRR − 70 − − 70 − dB Input Bias Current IIB − −2.0 −10 − −2.0 −10 (cid:2)A Propagation Delay (Current Sense Input to Output) tPLH(In/Out) − 150 300 − 150 300 ns OUTPUT SECTION Output Voltage V Low State (ISink = 20 mA) VOL − 0.1 0.4 − 0.1 0.4 (ISink = 200 mA) UC284XB, UC384XB − 1.6 2.2 − 1.6 2.2 UC384XBV, UC2843D − − − − 1.6 2.3 High State (ISource = 20 mA) UC284XB, UC384XB VOH 13 13.5 − 13 13.5 − − − − 12.9 13.5 − UC384XBV, UC2843D 12 13.4 − 12 13.4 − (ISource = 200 mA) Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns UNDERVOLTAGE LOCKOUT SECTION Startup Threshold (VCC) Vth V UCX842B, BV 15 16 17 14.5 16 17.5 UCX843B, BV, D 7.8 8.4 9.0 7.8 8.4 9.0 Minimum Operating Voltage After Turn−On (VCC) VCC(min) V UCX842B, BV 9.0 10 11 8.5 10 11.5 UCX843B, BV, D 7.0 7.6 8.2 7.0 7.6 8.2 PWM SECTION Duty Cycle % Maximum UC284XB, UC384XB, UC2843D DC(max) 94 96 − 94 96 − Maximum UC384XBV − − − 93 96 − Minimum DC(min) − − 0 − − 0 TOTAL DEVICE Power Supply Current ICC + IC mA Startup (VCC = 6.5 V for UCX843B, UC2843D − 0.3 0.5 − 0.3 0.5 Startup VCC 14 V for UCX842B, BV) (Note 7) − 12 17 − 12 17 Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V 5. This parameter is measured at the latch trip point with VFB = 0 V. 6. Comparator gain is defined as: AV (cid:4)(cid:4)VV O Cuutprruetn Ct oSmenpseen sInaptiuotn 7. Adjust VCC above the Startup threshold before setting to 15 V. 8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for UC3842B, UC3843B; −25°C for UC2842B, UC2843B; −40°C for UC3842BV, UC3843BV, UC2843D Thigh = +70°C for UC3842B, UC3843B; +85°C for UC2842B, UC2843B, UC2843D; +105°C for UC3842BV, UC3843BV http://onsemi.com 4

UC3842B, UC3843B, UC2842B, UC2843B 80 100 50 E 1. CT = 10 nF 4 ΩR (k) 20 EADTIM 50 234... CCCTTT === 521...000 nnnFFF 2 3 TO T D 20 5. CT = 500 pF MING RESIS 58..00 ENT OUTPU 51.00 67.. CCTT == 210000 ppFF 1 5 6 7 , TIT ERC R 2.0 VTAC C= =2 51°5C V % DT, P 2.0 VTAC C= =2 51°5C V 0.8 1.0 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M fOSC, OSCILLATOR FREQUENCY (kHz) fOSC, OSCILLATOR FREQUENCY (kHz) Figure 2. Timing Resistor Figure 3. Output Deadtime versus Oscillator Frequency versus Oscillator Frequency 9.0 %) 100 ENT (mA) 8.5 VVCOCS C= =1 52 .V0 V Y CYCLE ( 90 R T R U 80 U D C T RGE 8.0 UTPU 70 Idischg = 8.54 mA A O CH M S U 60 , DIg7.5 AXIM VCCT C= =3 .135 n VF Idisch , Mmax 50 TA = 25°C 7.0 D 40 -(cid:2)55 -(cid:2)25 0 25 50 75 100 125 0.8 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 TA, AMBIENT TEMPERATURE (°C) RT, TIMING RESISTOR (k(cid:5)) Figure 4. Oscillator Discharge Current Figure 5. Maximum Output Duty Cycle versus Temperature versus Timing Resistor 2.55 V VCC = 15 V 3.0 V VCC = 15 V AV = -1.0 AV = -1.0 TA = 25°C TA = 25°C 2.50 V mV/DIV 2.5 V mV/DIV 20 20 2.45 V 2.0 V 0.5 (cid:2)s/DIV 1.0 (cid:2)s/DIV Figure 6. Error Amp Small Signal Figure 7. Error Amp Large Signal Transient Response Transient Response http://onsemi.com 5

UC3842B, UC3843B, UC2842B, UC2843B 100 0 V) 1.2 , OPEN LOOP VOLTAGE GAIN (dB)L 246800000 Gain RTVVACOL C === = 212 501.0°05P C VKVh atos e4.0 V 369110002500φ, EXCESS PHASE (DEGREES) RRENT SENSE INPUT THRESHOLD ( 00001.....24680 VCC = 1T5A V =T 1A2 =5 °2C5°C TA = -55°C O U V C A-(cid:2)20 180 , h 0 10 100 1.0 k 10 k 100 k 1.0 M 10 M Vt 0 2.0 4.0 6.0 8.0 f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (V) Figure 8. Error Amp Open Loop Gain and Figure 9. Current Sense Input Threshold Phase versus Frequency versus Error Amp Output Voltage GE (mV) 0 ÄVÄCC =Ä 15 VÄ RENT (mA) 110 ÄÄVRCL C≤ ÄÄ =0 .115 (cid:5) ÄÄV N-(cid:2)4.0 R A U H C RENCE VOLTAGE C---(cid:2)811.620 ÄTA =Ä 125Ä°C Ä ÄÄTA =ÄÄ -55ÄÄ°C E SHORT CIRCUIT 7900 E C F ÄÄÄÄ N E E , RVref-(cid:2)20 ÄTÄA = 2Ä5°CÄ REFER Δ -(cid:2)240 20 40 60 80 100 120 , SC 50-(cid:2)55 -(cid:2)25 0 25 50 75 100 125 I Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C) Figure 10. Reference Voltage Change Figure 11. Reference Short Circuit Current versus Source Current versus Temperature V) V) DI DI V/ V/ E (2.0 m VTIOAC =C= 1=2. 501° 5mC VA to 20 mA E (2.0 m VTAC C= =2 51°2C V to 25 G G N N A A H H C C E E G G A A T T L L O O V V T T U U P P T T U U O O , O , O V V Δ 2.0 ms/DIV Δ 2.0 ms/DIV Figure 12. Reference Load Regulation Figure 13. Reference Line Regulation http://onsemi.com 6

UC3842B, UC3843B, UC2842B, UC2843B ÄÄÄÄÄÄÄÄÄÄ 0 E (V) ÄVÄÄCC ÄÄÄÄÄS(LooÄuardc eto ÄS GatruoruÄantido)nÄÄ8Ä0 (cid:2)VsC PÄCu =ls 1eÄ5d VLoaÄd OLTAG -1.0 ÄTAÄ = 25Ä°C Ä ÄÄ120Ä Hz RÄate Ä 90% CVCL C= =1 .105 n VF TION V-(cid:2)2.0 ÄÄÄÄTA = -ÄÄ(cid:2)55°ÄÄC TA = 25°C A R U 3.0 ÄÄÄ T TPUT SA 2.0 ÄTA =Ä -(cid:2)55ÄÄ°C ÄÄÄ ÄÄTA =ÄÄ 25°ÄÄC U V, Osat 1.0 ÄS(ÄLionak dS Ätaot uVrCaÄtCio)n ÄGNDÄ 10% 0 0 200 400 600 800 IO, OUTPUT LOAD CURRENT (mA) 50 ns/DIV Figure 14. Output Saturation Voltage Figure 15. Output Waveform versus Load Current E G 25 A T L O , OUTPUT VVO VCTACL C== =21 553° 0pC FV V/DIV URRENT (mA) 1250 20 Y C ÄÄÄÄ PPLY CURRENT 0 mA/DIV , SUPPLICC150 UCX843B UCX842B ÄÄÄRVITCÄÄÄSAFTTe B n=== s = e213ÄÄÄ 50=0.3° V0k Cn VFÄÄÄ , SUC 10 00 10 20 30 40 IC 100 ns/DIV VCC, SUPPLY VOLTAGE (V) Figure 16. Output Cross Conduction Figure 17. Supply Current versus Supply Voltage PIN FUNCTION DESCRIPTION 8−Pin 14−Pin Function Description 1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation. 2 3 Voltage This is the inverting input of the Error Amplifier. It is normally connected to the switching power Feedback supply output through a resistor divider. 3 5 Current A voltage proportional to inductor current is connected to this input. The PWM uses this Sense information to terminate the output switch conduction. 4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. 5 GND This pin is the combined control circuitry and power ground. 6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. 7 12 VCC This pin is the positive supply of the control IC. 8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. 8 Power This pin is a separate power ground return that is connected back to the power source. It is used Ground to reduce the effects of switching transient noise on the control circuitry. 11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 9 GND This pin is the control circuitry ground return and is connected back to the power source ground. 2,4,6,1 NC No connection. These pins are not internally connected. 3 http://onsemi.com 7

UC3842B, UC3843B, UC2842B, UC2843B OPERATING DESCRIPTION (cid:4) (cid:6) The UC3842B, UC3843B series are high performance, VRT(cid:2)CT(valley)(cid:5)Vref ln fixed frequency, current mode controllers. They are VRT(cid:2)CT(peak)(cid:5)Vref specifically designed for Off−Line and DC−to−DC Dmax(cid:3) (cid:4) (cid:6) converter applications offering the designer a cost−effective ln VRT(cid:2)CT(valley)(cid:5)Vref(cid:8) RTIdischg(cid:7)VRT(cid:2)CT(peak)(cid:5)Vref solution with minimal external components. A VRT(cid:2)CT(peak)(cid:5)Vref RTIdischg(cid:7)VRT(cid:2)CT(valley)(cid:5)Vref representative block diagram is shown in Figure 19. (eq. 4) Clearly, the maximum duty ratio is determined by the Oscillator timing resistor R . Therefore, R is chosen such as to T T The oscillator frequency is programmed by the values achieve a desired maximum duty ratio. Once RT has been chosen for the timing components RT and CT. It must also be selected, CT can now be chosen to obtain the desired noted that the value of R uniquely determines the T switching frequency as per Equation 5. maximum duty ratio of UC384xx. The oscillator configuration depicting the connection of the timing f(cid:3) (cid:4) 1 (cid:6) Fcoigmupreo n1e8n. tCs atop atchiet oRr TC/CT Tg eptisn c ohfa rtgheed c fornotmro ltlheer Visr esfh soowunrc ien, RTCTln VVRRTT(cid:2)(cid:2)CCTT((vpaellaeky))(cid:5)(cid:5)VVrreeff(cid:8)RRTTIIddiisscchhgg(cid:7)(cid:7)VVRRTT(cid:2)(cid:2)CCTT((vpaellaeky))(cid:5)(cid:5)VVrreeff through resistor R to its peak threshold V , (eq. 5) T RT/CT(peak) typically 2.8 V. Upon reaching this peak threshold volage, an Figure 2 shows the frequency and maximum duty ratio internal 8.3 mA current source, Idischg, is enabled and the variation versus RT for given values of CT. Care should be voltage across CT begins to decrease. Once the voltage taken to ensure that the absolute minimum value of RT across CT reaches its valley threshold, VRT/CT(valley), should not be less than 542 (cid:5). However, considering a 10% typically 1.2 V, Idischg turns off. This allows capacitor CT to tolerance for the timing resistor, the nearest available charge up again from V . This entire cycle repeats, and the standard resistor of 680 (cid:5) is the absolute minimum that can ref resulting waveform on the RT/CT pin has a sawtooth shape. be used to guarantee normal oscillator operation. If a timing Typical waveforms are shown in Figure 20. resistor smaller than this value is used, then the charging The oscillator thresholds are temperature compensated to current through the RT, CT path will exceed the pulldown within ±6% at 50 kHz. Considering the general industry (discharge) current and the oscillator will get permanently trend of operating switching controllers at higher locked/latched to an undefined state. frequencies, the UC384xx is guaranteed to operate within In many noise-sensitive applications it may be desirable ±10% at 250 kHz. These internal circuit refinements to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal to the minimize variations of oscillator frequency and maximum duty ratio. circuit shown in Figure 22. For reliable synchronization, the The charging and discharging times of the timing free-running oscillator frequency should be set about 10% capacitor C are calculated using Equations 1 and 2. These less than the clock frequency. A method for multi-unit T synchronization is shown in Figure 23. By tailoring the equations do not take into account the propagation delays of clock waveform, accurate Output duty ratio clamping can be the internal comparator. Hence, at higher frequencies, the achieved. calculated value of the oscillator frequency differs from the actual value. (cid:4) (cid:6) Vref V (cid:5)V tRT(cid:2)CT(chg)(cid:3)RTCTln VRRTT(cid:2)(cid:2)CCTT((vpaellaeky))(cid:5)Vrreeff (eq. 1) RT (cid:4) (cid:6) 2.8 V R I (cid:7)V (cid:5)V RT/CT t (cid:3)R C ln Tdischg RT(cid:2)CT(peak) ref RT(cid:2)CT(dischg) T T R I (cid:7)V (cid:5)V 1.2 V Tdischg RT(cid:2)CT(valley) ref Idischg (eq. 2) Enable CT The maximum duty ratio, D is given by Equation 3. max Dmax(cid:3)t tRT(cid:7)(cid:2)CTt(chg) (eq. 3) Figure 18. Oscillator Configuration RT(cid:2)CT(chg) RT(cid:2)CT(dischg) Substituting Equations 1 and 2 into Equation 3, and after algebraic simplification, we obtain http://onsemi.com 8

UC3842B, UC3843B, UC2842B, UC2843B Error Amplifier appears at the Output during any given oscillator cycle. The A fully compensated Error Amplifier with access to the inductor current is converted to a voltage by inserting the inverting input and output is provided. It features a typical ground−referenced sense resistor R in series with the S DC voltage gain of 90 dB, and a unity gain bandwidth of source of output switch Q1. This voltage is monitored by the 1.0 MHz with 57 degrees of phase margin (Figure 8). The Current Sense Input (Pin 3) and compared to a level derived non−inverting input is internally biased at 2.5 V and is not from the Error Amp Output. The peak inductor current under pinned out. The converter output voltage is typically divided normal operating conditions is controlled by the voltage at down and monitored by the inverting input. The maximum pin 1 where: input bias current is −2.0 (cid:2)A which can cause an output voltage error that is equal to the product of the input bias Ipk = V(Pin 1) − 1.4 V 3 R S current and the equivalent input divider source resistance. Abnormal operating conditions occur when the power The Error Amp Output (Pin 1) is provided for external supply output is overloaded or if output voltage sensing is loop compensation (Figure 33). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the connects to the non−inverting input of the Current Sense maximum peak switch current is: Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when pin 1 is at its lowest state (V ). 1.0 V OL I = pk(max) R This occurs when the power supply is operating and the load S is removed, or at the beginning of a soft−start interval When designing a high power switching regulator it (Figures 25, 26). The Error Amp minimum feedback becomes desirable to reduce the internal clamp voltage in resistance is limited by the amplifier’s source current order to keep the power dissipation of RS to a reasonable (0.5 mA) and the required output voltage (V ) to reach the level. A simple method to adjust this voltage is shown in OH comparator’s 1.0 V clamp level: Figure 24. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over 3.0 (1.0 V) + 1.4 V Rf(min) ≈ 0.5 mA = 8800 (cid:5) temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the I clamp pk(max) Current Sense Comparator and PWM Latch voltage. The UC3842B, UC3843B operate as a current mode A narrow spike on the leading edge of the current controller, whereby output switch conduction is initiated by waveform can usually be observed and may cause the power the oscillator and terminated when the peak inductor current supply to exhibit an instability when the output is lightly reaches the threshold level established by the Error loaded. This spike is due to the power transformer Amplifier Output/Compensation (Pin 1). Thus the error interwinding capacitance and output rectifier recovery time. signal controls the peak inductor current on a The addition of an RC filter on the Current Sense Input with cycle−by−cycle basis. The Current Sense Comparator PWM a time constant that approximates the spike duration will Latch configuration used ensures that only a single pulse usually eliminate the instability (refer to Figure 28). http://onsemi.com 9

UC3842B, UC3843B, UC2842B, UC2843B VCC Vin VCC 7(12) 36V Vref Reference Regulator 8(14) R Internal UVVCLCO +- T(Seexte) VC RT 2.5V Bias R + 7(11) 3.6V - Vref UVLO Output Q1 Oscillator CT 4(7) + 1.0mA 6(10) S Power Ground Voltage 2R Q Feedback R PWM 5(8) Input2(3) Error R 1.0V Latch Current Sense Input Amplifier Output/ Compensation1(1) CCurormenpta Sraetnosre 3(5) RS GND 5(9) Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. = Sink Only Positive True Logic Pin numbers in parenthesis are for the D suffix SOIC-14 package. Figure 19. Representative Block Diagram Capacitor CT Latch “Set" Input Output/ Compensation Current Sense Input Latch “Reset" Input Output Large RT/Small CT Small RT/Large CT Figure 20. Timing Diagram http://onsemi.com 10

UC3842B, UC3843B, UC2842B, UC2843B Undervoltage Lockout Design Considerations Two undervoltage lockout comparators have been Do not attempt to construct the converter on incorporated to guarantee that the IC is fully functional wire−wrap or plug−in prototype boards. High frequency before the output stage is enabled. The positive power circuit layout techniques are imperative to prevent supply terminal (V ) and the reference output (V ) are pulse−width jitter. This is usually caused by excessive noise CC ref each monitored by separate comparators. Each has built−in pick−up imposed on the Current Sense or Voltage Feedback hysteresis to prevent erratic output behavior as their inputs. Noise immunity can be improved by lowering circuit respective thresholds are crossed. The V comparator impedances at these points. The printed circuit layout should CC upper and lower thresholds are 16 V/10 V for the UCX842B, contain a ground plane with low−current signal and and 8.4 V/7.6 V for the UCX843B. The V comparator high−current switch and output grounds returning on ref upper and lower thresholds are 3.6 V/3.4 V. The large separate paths back to the input filter capacitor. Ceramic hysteresis and low startup current of the UCX842B makes bypass capacitors (0.1 (cid:2)F) connected directly to V , V , CC C it ideally suited in off−line converter applications where and V may be required depending upon circuit layout. ref efficient bootstrap startup techniques are required This provides a low impedance path for filtering the high (Figure 35). The UCX843B is intended for lower voltage frequency noise. All high current loops should be kept as DC−to−DC converter applications. A 36 V Zener is short as possible using heavy copper runs to minimize connected as a shunt regulator from V to ground. Its radiated EMI. The Error Amp compensation circuitry and CC purpose is to protect the IC from excessive voltage that can the converter output voltage divider should be located close occur during system startup. The minimum operating to the IC and as far as possible from the power switch and voltage (V ) for the UCX842B is 11 V and 8.2 V for the other noise−generating components. CC UCX843B. Current mode converters can exhibit subharmonic These devices contain a single totem pole output stage that oscillations when operating at a duty cycle greater than 50% was specifically designed for direct drive of power with continuous inductor current. This instability is MOSFETs. It is capable of up to ±1.0 A peak drive current independent of the regulator’s closed loop characteristics and has a typical rise and fall time of 50 ns with a 1.0 nF load. and is caused by the simultaneous operating conditions of Additional internal circuitry has been added to keep the fixed frequency and peak current detecting. Figure 21A Output in a sinking mode whenever an undervoltage lockout shows the phenomenon graphically. At t , switch 0 is active. This characteristic eliminates the need for an conduction begins, causing the inductor current to rise at a external pull−down resistor. slope of m . This slope is a function of the input voltage 1 The SOIC−14 surface mount package provides separate divided by the inductance. At t , the Current Sense Input 1 pins for V (output supply) and Power Ground. Proper reaches the threshold established by the control voltage. C implementation will significantly reduce the level of This causes the switch to turn off and the current to decay at switching transient noise imposed on the control circuitry. a slope of m , until the next oscillator cycle. The unstable 2 This becomes particularly useful when reducing the I condition can be shown if a perturbation is added to the pk(max) clamp level. The separate V supply input allows the control voltage, resulting in a small (cid:4)I (dashed line). With C designer added flexibility in tailoring the drive voltage a fixed oscillator period, the current decay time is reduced, independent of V . A Zener clamp is typically connected and the minimum current at switch turn−on (t ) is increased CC 2 to this input when driving power MOSFETs in systems by (cid:4)I + (cid:4)I m /m . The minimum current at the next cycle 2 1 where VCC is greater than 20 V. Figure 27 shows proper (t3) decreases to ((cid:4)I + (cid:4)I m2/m1) (m2/m1). This perturbation power and control ground connections in a current−sensing is multiplied by m /m on each succeeding cycle, alternately 2 1 power MOSFET application. increasing and decreasing the inductor current at switch turn−on. Several oscillator cycles may be required before Reference the inductor current reaches zero causing the process to The 5.0 V bandgap reference is trimmed to ±1.0% commence again. If m /m is greater than 1, the converter tolerance at T = 25°C on the UC284XB, and ±2.0% on the 2 1 J will be unstable. Figure 21B shows that by adding an UC384XB. Its primary purpose is to supply charging current artificial ramp that is synchronized with the PWM clock to to the oscillator timing capacitor. The reference has short− the control voltage, the (cid:4)I perturbation will decrease to zero circuit protection and is capable of providing in excess of on succeeding cycles. This compensating ramp (m ) must 3 20 mA for powering additional control system circuitry. have a slope equal to or slightly greater than m /2 for 2 stability. With m /2 slope compensation, the average 2 inductor current follows the control voltage, yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 34). http://onsemi.com 11

UC3842B, UC3843B, UC2842B, UC2843B (A) (cid:4)I Control Voltage m1 m2 Inductor Current (cid:4)l(cid:7)(cid:4)lm2 m1 (cid:4)l(cid:7)(cid:4)lm2(cid:2)(cid:2)(cid:2)m2 Vref m1 m1 Oscillator Period 8(14) R Bias t0 t1 t2 t3 RT R (B) External Osc Control Voltage m3 SInypnuct 0.01 CT 4(7) + 2R (cid:4)I m1 47 2(3) EA R m2 Inductor Current 1(1) Oscillator Period 5(9) The diode clamp is required if the Sync amplitude is large enough to cause the bottom t4 t5 t6 side of CT to go more than 300 mV below ground. Figure 21. Continuous Current Waveforms Figure 22. External Clock Synchronization VCC Vin 7(12) 5.0V Ref 8(14) R + 8(14) R Bias - RA Bias R 7(11) + 8 4 R - Q1 RB 5.0k Osc 6 3 Osc 4(7) + VClamp 6(10) R 4(7) R2 1.0 mA S 5 5.0k Q + Q 2 S 7 2R 2(3) EA 2RR R 5(8) 1.0V Comp/Latch C 5.0k MC1455 2(3) EA R 1(1) 3(5) RS 1 R1 5(9) 1(1) f(cid:2)(cid:3)(cid:2)(RA(cid:2)(cid:7)1.4(cid:2)42RB)C D(max)(cid:2)(cid:3)(cid:2)RA(cid:2)(cid:7)RB(cid:2)2RB TUoC AXd8d4itXioBnsal 5(9) VClamp ≈ (cid:4)RR211(cid:7).671(cid:6) + 0.33x10-3 (cid:4)R1R(cid:7)1R2R2(cid:6) IWpkh(emrea:x 0)(cid:2) ≤(cid:9) V(cid:2)CVlaCmRlpaS m≤ p1.0 V Figure 23. External Duty Cycle Clamp and Figure 24. Adjustable Reduction of Clamp Level Multi−Unit Synchronization http://onsemi.com 12

UC3842B, UC3843B, UC2842B, UC2843B VCC Vin 7(12) 5.0V Ref 8(14) R + - Bias 5.0V Ref R 7(11) 8(14) R -+ Bias Q1 Osc R + 4(7) + VClamp 6(10) - 1.0 mA S Q 4(7) +O1s.c0mA S R2 2(3) EA 2RR 1.0V ComRp/Latch 5(8) 2(3) Q 1(1) 3(5) RS 2R R C R1 MPSA63 5(9) EA R 1.0V 1.0M VClamp(cid:2)(cid:9)(cid:2)(cid:4) 1.67 (cid:6) Where: 0 ≤ VClamp ≤ 1.0 V 1(1) R2(cid:7)1 (cid:10)R1 (cid:11) C tSoft-Start ≈ 3600C in (cid:2)F 5(9) tSoftStart(cid:3)(cid:5)In 1(cid:5)(cid:2)3(cid:2)VVCClamp (cid:2)CR1R(cid:2)1(cid:7)(cid:2)R(cid:2)2R2 Ipk(max)(cid:2)(cid:9)(cid:2)VCRlaSmp Figure 25. Soft−Start Circuit Figure 26. Adjustable Buffered Reduction of Clamp Level with Soft−Start VCC Vin (12) VPin5 (cid:9) rRDSMI(pokn)rD(cid:7)S(oRnS) VCC Vin If: SENSEFET = MTP10N10M 7(12) RS = 200 5.0V Ref + Then:(cid:2)VPin(cid:2)5(cid:2)(cid:9)(cid:2)0.075(cid:2)Ipk - 5.0V Ref (11) D SENSEFET +- + - S + 7(11) G - K Q1 (10) M S 6(10) Q S R (8) Q 5(8) Comp/Latch R Power Ground: Comp/Latch 3(5) R (5) RS To Input Source 1/4 W Return C RS Control Circuitry Ground: To Pin (9) Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over-current conditions, a The addition of the RC filter will eliminate instability caused by the leading reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 24 and 26. edge spike on the current waveform. Figure 27. Current Sensing Power MOSFET Figure 28. Current Waveform Spike Suppression http://onsemi.com 13

UC3842B, UC3843B, UC2842B, UC2843B VCC Vin 7(12) IB Vin + 0 5.0V Ref + Base Charge - - Removal 7(11) + - C1 Rg Q1 6(10) Q1 6(10) S Q R 5(8) 5(8) Comp/Latch 3(5) RS 3(5) RS Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in The totem pole output can furnish negative base current for enhanced the gate-source circuit. transistor turn-off, with the addition of capacitor C1. Figure 29. MOSFET Parasitic Oscillations Figure 30. Bipolar Transistor Drive VCC Vin 8(14) R Bias 7(12) Isolation R Boundary 5.0V Ref Osc + 4(7) + - VGS Waveforms 1.0 mA 2R 7(11) + + + Q1 - 0 2(3) EA R 0 - - 6(10) 50% DC 25% DC 1(1) RS Q 5(8) Ipk(cid:3)V(Pin31(cid:2)R)(cid:5)S 1.4(cid:2)(cid:4)NNSp(cid:6) M1C01R 329N05 2N 5(9) Comp/Latch 3(5) R 3903 C RS NS NP The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Figure 31. Isolated MOSFET Drive Figure 32. Latched Shutdown http://onsemi.com 14

UC3842B, UC3843B, UC2842B, UC2843B From VO 2.5V + Ri 2(3) 1.0mA 2R EA R Rd Cf Rf 1(1) Rf ≥ 8.8 k 5(9) Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. From VO 2.5V + Rp Ri 2(3) 1.0mA 2R Cp Rd Cf Rf EA R 1(1) 5(9) Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current. Figure 33. Error Amplifier Compensation VCC Vin 7(12) 36V 5.0V Ref 8(14) R + - RT Bias R MPS3904 + 7(11) - From VO RSlope CT 4(7) + Osc -m 6(10) Ri 2(3) 1.0mA2R SQ R 5(8) Rd Cf Rf EA R 1.0V Comp/Latch 1(1) -3.0m m 3(5) RS 5(9) The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. Figure 34. Slope Compensation http://onsemi.com 15

UC3842B, UC3843B, UC2842B, UC2843B L1 MBR1635 4.7(cid:5) MDA + 250 4.7k 3300 T1 2200 + 1000 + 5.0V/4.0A 202 pF 56k 115 Vac 5.0V RTN MUR110 1N4935 1N4935 12V/0.3A + L2 + 7(12) + 68 + 1000 10 100 47 ±12V RTN 1000 10 5.0V Ref 1N4937 + + 0.01 8(14) R + -12V/0.3A MUR110 - L3 Bias 680pF 10k R 7(11) + - 22 2.7k 1N4937 Osc 4700pF 4(7) + 6(10) MTP 18k S 1N5819 4N50 L1- 15 (cid:2)H at 5.0 A, Coilcraft Z7156 2(3) Q L2, L3- 25 (cid:2)H at 5.0 A, Coilcraft Z7157 100 EA R 5(8) 4.7k pF 150k Comp/Latch 1.0k T1 -Primary: 45 Turns #26 AWG 1(1) 3(5) 0.5 Secondary ±12 V: 9 Turns #30 AWG 470pF (2 Strands) Bifiliar Wound 5(9) Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns Figure 35. 27 W Off−Line Flyback Regulator #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin: Ferroxcube EC35PCB1 Gap: ≈ 0.10" for a primary inductance of 1.0 mH Test Conditions Results Line Regulation: 5.0 V Vin = 95 to 130 Vac (cid:4) = 50 mV or ±0.5% ±12V (cid:4) = 24 mV or ±0.1% Load Regulation: 5.0 V Vin = 115 Vac, (cid:4) = 300 mV or ±3.0% Iout = 1.0 A to 4.0 A ±12V Vin = 115 Vac, (cid:4) = 60 mV or ±0.25% Iout = 100 mA to 300 mA Output Ripple: 5.0 V Vin = 115 Vac 40 mVpp ±12V 80 mVpp Efficiency Vin = 115 Vac 70% All outputs are at nominal load currents, unless otherwise noted http://onsemi.com 16

UC3842B, UC3843B, UC2842B, UC2843B ORDERING INFORMATION Device Operating Temperature Range Package Shipping† UC2842BDG SOIC−14 55 Units/Rail (Pb−Free) UC2842BD1G SOIC−8 98 Units/Rail (Pb−Free) TA = −25° to +85°C UC2842BD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC2842BNG PDIP−8 1000 Units/Rail (Pb−Free) UC3842BNG PDIP−8 1000 Units/Rail (Pb−Free) UC3842BDG SOIC−14 55 Units/Rail (Pb−Free) UC3842BDR2G SOIC−14 2500 Tape & Reel TA = 0° to +70°C (Pb−Free) UC3842BD1G SOIC−8 98 Units/Rail (Pb−Free) UC3842BD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC3842BVDR2G SOIC−14 2500 Tape & Reel (Pb−Free) UC3842BVD1G SOIC−8 98 Units/Rail TA = −40° to +105°C (Pb−Free) UC3842BVD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC2843BDG SOIC−14 55 Units/Rail (Pb−Free) UC2843BDR2G SOIC−14 2500 Tape & Reel TA = −25° to +85°C (Pb−Free) UC2843BD1G SOIC−8 98 Units/Rail (Pb−Free) UC2843BD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) TA = −25° to +85°C UC2843BNG PDIP−8 1000 Units/Rail (Pb−Free) UC2843DD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) TA = −40° to +85°C UC2843DDR2G SOIC−8 2500 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 17

UC3842B, UC3843B, UC2842B, UC2843B ORDERING INFORMATION Device Operating Temperature Range Package Shipping† UC3843BDG SOIC−14 55 Units/Rail (Pb−Free) UC3843BDR2G SOIC−14 2500 Tape & Reel (Pb−Free) UC3843BD1G SOIC−8 98 Units/Rail (Pb−Free) TA = 0° to +70°C UC3843BD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC3843BDR2G SOIC−14 2500 Tape & Reel (Pb−Free) UC3843BNG PDIP−8 1000 Units/Rail (Pb−Free) UC3843BVDG SOIC−14 55 Units/Rail (Pb−Free) UC3843BVDR2G SOIC−14 2500 Tape & Reel (Pb−Free) UC3843BVD1G SOIC−8 98 Units/Rail TA = −40° to +105°C (Pb−Free) UC3843BVD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC3843BVNG PDIP−8 1000 Units/Rail (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 18

UC3842B, UC3843B, UC2842B, UC2843B MARKING DIAGRAMS PDIP−8 N SUFFIX CASE 626 8 8 8 UC384xBN UC3843BVN UC284xBN AWL AWL AWL YYWWG YYWWG YYWWG 1 1 1 SOIC−14 D SUFFIX CASE 751A 14 14 14 14 UC384xBDG UC384xBVDG UC284xBDG UC2843DDG AWLYWW AWLYWW AWLYWW AWLYWW 1 1 1 1 SOIC−8 D1 SUFFIX CASE 751 8 8 8 8 384xB 384xB 284xB 2843D ALYW ALYWV ALYW ALYW (cid:2) (cid:2) (cid:2) (cid:2) 1 1 1 1 x = 2 or 3 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or (cid:2) = Pb−Free Package http://onsemi.com 19

UC3842B, UC3843B, UC2842B, UC2843B PACKAGE DIMENSIONS PDIP−8 N SUFFIX CASE 626−05 ISSUE N D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. E 2. CONTROLLING DIMENSION: INCHES. H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 8 5 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE E1 NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM 1 4 PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE NOTE 8 c LEADS UNCONSTRAINED. b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE END VIEW LEADS, WHERE THE LEADS EXIT THE BODY. TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). NOTE 5 INCHES MILLIMETERS A2 DIM MIN MAX MIN MAX e/2 A A −−−− 0.210 −−− 5.33 NOTE 3 A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 L b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 SEATING A1 PLANE D1 0.005 −−−− 0.13 −−− E 0.300 0.325 7.62 8.26 C M E1 0.240 0.280 6.10 7.11 D1 e 0.100 BSC 2.54 BSC e eB eB −−−− 0.430 −−− 10.92 L 0.115 0.150 2.92 3.81 8Xb END VIEW M −−−− 10° −−− 10° 0.010 M C A M B M NOTE 6 SIDE VIEW http://onsemi.com 20

UC3842B, UC3843B, UC2842B, UC2843B PACKAGE DIMENSIONS SOIC−8 D1 SUFFIX CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER A ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 8 5 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR 1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL −Y− 4 K IMNA EXXIMCUEMSS M OAFT ETRHIEA LD CDOIMNEDNITSIOIONN. AT 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES C NX 45(cid:3) DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 SEATING PLANE B 3.80 4.00 0.150 0.157 −Z− C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 0.10 (0.004) G 1.27 BSC 0.050 BSC H D M J H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 0.25 (0.010)M Z Y S X S M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:4) (cid:6) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 21

UC3842B, UC3843B, UC2842B, UC2843B PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE J −A− NOTES: 1.DIMENSIONING AND TOLERANCING PER 14 8 ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. −B− P7 PL 4.MPEARX ISMIUDME. MOLD PROTRUSION 0.15 (0.006) 0.25 (0.010) M B M 5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 1 7 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL G RX 45(cid:3) F CONDITION. C MILLIMETERS INCHES DIM MIN MAX MIN MAX A 8.55 8.75 0.337 0.344 −T− B 3.80 4.00 0.150 0.157 SPELAATNIENG D14 PL K M J CD 10..3355 10..7459 00..005144 00..006189 0.25 (0.010) M T B S A S F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 (cid:3) 7 (cid:3) 0 (cid:3) 7 (cid:3) P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 SOLDERING FOOTPRINT 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS SENSEFET is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com UC3842B/D 22