UC1832 UC2832/3 UC3832/3 Precision Low Dropout Linear Controllers FEATURES DESCRIPTION • Precision 1% Reference The UC2832 and UC3833 series of precision linear regulators include all the control functions required in the design of very low dropout linear regulators. • Over-Current Sense Threshold Additionally, they feature an innovative duty-ratio current limiting technique Accurate to 5% which provides peak load capability while limiting the average power dissipa- • Programmable Duty-Ratio tion of the external pass transistor during fault conditions. When the load cur- Over-Current Protection rent reaches an accurately programmed threshold, a gated-astable timer is • 4.5 V to 36 V Operation enabled, which switches the regulator’s pass device off and on at an externally programmable duty-ratio. During the on-time of the pass element, the output • 100mA Output Drive, Source, or current is limited to a value slightly higher than the trip threshold of the duty-ra- Sink tio timer. The constant-current-limit is programmable on the UCx832 to allow • Under-Voltage Lockout higher peak current during the on-time of the pass device. With duty-ratio con- trol, high initial load demands and short circuit protection may both be accom- Additional Features of the UC2832 modated without extra heat sinking or foldback current limiting. Additionally, if series: the timer pin is grounded, the duty-ratio timer is disabled, and the IC operates • Adjustable Current Limit to in constant-voltage/constant-current regulating mode. Current Sense Ratio These IC’s include a 2 Volt (– 1%) reference, error amplifier, UVLO, and a high • Separate +VIN terminal current driver that has both source and sink outputs, allowing the use of either NPN or PNP external pass transistors. Safe operation is assured by the inclu- • Programmable Driver Current sion of under-voltage lockout (UVLO) and thermal shutdown. Limit The UC3833 family includes the basic functions of this design in a low-cost, 8- • Access to VREF and E/A(+) pin mini-dip package, while the UC2832 series provides added versatility with • Logic-Level Disable Input the availability of 14 pins. Packaging options include plastic (N suffix), or ce- ramic (J suffix). Specified operating temperature ranges are: commercial (0°C to 70°C), order UC3832/3 (N or J); and industrial (–40°C to 85°C), order UC2832/3 (N or J). Surface mount packaging is also available. BLOCK DIAGRAMS UDG-92040 SLUS387A - JUNE 1994 - REVISED - MAY 2003

UC1832 UC2832/3 UC3832/3 ABSOLUTE MAXIMUM RATINGS Supply Voltage +VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Driver Output Current (Sink or Source) . . . . . . . . . . . . . 450mA Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the speci- Driver Sink to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . 40V fied terminals. TRC Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 3.2V Note 2: See Unitrode Integrated Circuits databook for Other Input Voltages. . . . . . . . . . . . . . . . . . . . . . . –0.3V to +VIN information regarding thermal specifications and limitations of Operating Junction Temperature (note 2) . . . –55°C to +150°C packages. Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300(cid:176) C CONNECTION DIAGRAMS UC2832 UC3833 DIL-14 (Top View) DIL-8 (Top View) J Or N Package J Or N Package SOIC-16 (Top View) SOIC-16 (Top View) DW Package DW Package LCC-20 & PLCC-20 PACKAGE PIN FUNCTION LCC-20 & PLCC-20 PACKAGE PIN FUNCTION L & Q Package FUNCTION PIN L & Q Package FUNCTION PIN (Top View) N/C 1 (Top View) +VIN & C/S(+) 1 +VIN 2 N/C 2 Comp/Shutdown 3 N/C 3 E/A(+) 4 N/C 4 +2V REF 5 Comp/Shutdown 5 N/C 6 Gnd 6 Gnd 7 N/C 7 Logic Disable 8 N/C 8 Limit 9 N/C 9 Source 10 Source 10 N/C 11 N/C 11 E/A(-) 12 E/A(-) 12 Sink 13 N/C 13 VADJ 14 N/C 14 N/C 15-17 Sink 15 Timer RC 18 Timer RC 16 Current Sense(-) 19 Current Sense(+) 17 Current Sense(+) 20 N/C 18-20 2

UC1832 UC2832/3 UC3832/3 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, specifications hold for TA = 0°C to 70°C for the UC3832/3, –40°C to 85°C for the UC2832/3, +VIN = 15V, Driver sink = +VIN, C/S(+) voltage = +VIN. TA=TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Supply Supply Current +VIN = 6 V 6.5 10 mA +VIN = 36 V 9.5 15 mA Logic Disable = 2 V (UCx832 only) 3.3 mA Reference Section Output Voltage (Note 3) TJ = 25(cid:176) C, IDRIVER = 10 mA 1.98 2.00 2.02 V over temperature, IDRIVER = 10 mA 1.96 2.00 2.04 V Load Regulation (UCx832 only) IO = 0 to 10 m -10 -5.0 mV Line Regulation +VIN = 4.5 V to 36 V, IDRIVER = 10 m 0.033 0.5 mV/V Under-Voltage Lockout Threshold 3.6 4.5 V Logic Disable Input (UCx832 only) Threshold Voltage 1.3 1.4 1.5 V Input Bias Current Logic Disable = 0 V -5.0 -1.0 m A Current Sense Section Comparator Offset 95 100 105 mV Over Temperature 93 100 107 mV Amplifier Offset (UCx833 only) 110 135 170 mV Amplifier Offset (UCx832 only) VADJ = Open 110 135 170 mV VADJ = 1 V 180 235 290 mV VADJ = 0 V 250 305 360 mV Input Bias Current VCM = +VIN 65 100 135 m A Input Offset Current (UCx832 only) VCM = +VIN -10 10 m A Amplifier CMRR (UCx832 only) VCM = 4.1 V to + VIN + 0.3 80 dB Transconductance ICOMP = – 100 m A 65 mS VADJ Input Current (UCx832 only) VADJ = 0V -10 -1 m A Timer Inactive Leakage Current C/S(+) = C/S(-) = +VIN; TRC pin = 2 V 0.25 1.0 m A Active Pullup Current C/S(+) = +VIN, C/S(-) = +VIN - 0.4V; TRC pin = 0 V -345 -270 -175 m A Duty Ratio (note 4) ontime/period, RT = 200k, CT = 0.27m F 4.8 % Period (notes 4,5) ontime + offtime, RT = 200k, CT = 0.27m F 36 ms Upper Trip Threshold (Vu) 1.8 V Lower Trip Threshold (Vl) 0.9 V Trip Threshold Ratio Vu/Vl 2.0 V/V Error Amplifier Input Offset Voltage (UCx832 only) VCM = VCOMP = 2 V -8.0 8.0 mV Input Bias Current VCM = VCOMP = 2 V -4.5 -1.1 m A Input Offset Current (UCx832 only) VCM = VCOMP = 2 V -1.5 1.5 m A AVOL VCOMP = 1 V to 13 V 50 70 dB CMRR (UCx832 only) VCM = 0V to +VIN - 3 V 60 80 dB PSRR (UCx832 only) VCM = 2 V, +VIN = 4.5 V to 36 90 dB Transconductance ICOMP = – 10 m A 4.3 mS VOH ICOMP = 0, Volts below +VIN .95 1.3 V VOL ICOMP = 0 .45 0.7 V IOH VCOMP = 2 V -700 -500 -100 m A 3

UC1832 UC2832/3 UC3832/3 ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, specifications hold for TA = 0°C to 70°C for the UC3832/3, –40°C to 85°C for the UC2832/3, +VIN = 15 V, Driver sink = +VIN, C/S(+) voltage = +VIN. TA=TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Error Amplifier (cont.) IOL VCOMP = 2 V, C/S(-) = +VIN 100 500 700 m A VCOMP = 2 V, C/S(-) = +VIN - 0.4 V 2 6 mA Driver Maximum Current Driver Limit & Source pins common; TJ = 25°C 200 300 400 mA Over Temperature 100 300 450 mA Limiting Voltage (UCx832 only) Driver Limit to Source voltage at current limit, ISOURCE = -10 mA; TJ = 25°C (Note 6) .72 V Internal Current Sense Resistance TJ = 25°C (Note 6) 2.4 W Pull-Up Current at Driver Sink Compensation/Shutdown = 0.4 V; Driver Sink = +VIN - 1V -800 -300 -100 m A Compensation/Shutdown = 0.4 V, +VIN = 36 V; Driver Sink = 35 V -1000 -300 -75 m A Pull-Down Current at Driver Source Compensation/Shutdown = 0.4 V; Driver Source = 1 V 150 300 700 m A Saturation Voltage Sink to Source Driver Source = 0 V; Driver Current = 100 mA 1.5 V Maximum Source Voltage Driver Sink = +VIN, Driver Current = 100 mA Volts below + VIN 3.0 V UVLO Sink Leakage +VIN = C/S(+) = C/S(-) = 2.5 V, Driver Sink = 15 V, Driver Source = 0 V, TA = 25°C 25 m A Maximum Reverse Source Voltage Compensation/Shutdown = 0 V; ISOURCE = 100 m A, +VIN = 3 V 1.6 V Thermal Shutdown 160 °C Note 3: On the UCx833 this voltage is defined as the regulating level at the error amplifier inverting input, with the error amplifier driving VSOURCE to 2 V. Note 4: These parameters are first-order supply-independent, however both may vary with supply for +VIN less than about 4 V. This supply variation will cause a slight change in the timer period and duty cycle, although a high off-time/on-time ratio will be main- tained. Note 5: With recommended RT value of 200k, TOFF » RT CT * ln(Vu/Vl) – 10%. Note 6: The internal current limiting voltage has a temperature dependence of approximately -2.0 mV/°C, or -2800 ppm/°C. The inter- nal 2.4 W sense resistor has a temperature dependance of approximately +1500 ppm/°C. APPLICATION AND OPERATION INFORMATION NPN Pass (Local 100mA Regulator) (UCx833) UDG-92041-1 4

UC1832 UC2832/3 UC3832/3 APPLICATION AND OPERATION INFORMATION (cont.) PNP Pass (Low Drop-Out Regulator) (UCx833) UDG-92042-1 NPN Pass (Medium Power, Low Drop-Out Regulator) (UCx832) UDG-92043-1 Estimating Maximum Load Capacitance For any power supply, the rate at which the total output Current Sense Amplifier Offset Voltage and K = capacitance can be charged depends on the maximum 100mA output current available and on the nature of the load. For » 1.35 for UCx833, and is variable from 1.35 to 3.05 a constant-current current-limited power supply, the out- with VADJ for the UCx832. put will come up if the load asks for less than the maxi- mum available short-circuit limit current. For a worst-case constant-current load of value just less than ITH, CMAX can be estimated from: To guarantee recovery of a duty-ratio current-limited power supply from a short-circuited load condition, there CMAX = ((K- 1)ITH) (TON), VOUT is a maximum total output capacitance which can be where VOUT is the nominal regulator output voltage. charged for a given unit ON time. The design value of ON time can be adjusted by changing the timing capacitor. For a resistive load of value RL, the value of CMAX can be Nominally, TON = 0.693 x 10k x CT. estimated from: Typically, the IC regulates output current to a maximum of CMAX = TON • 1 . IMAX = K x ITH, where ITH is the timer trip-point current, RL In [(1- K •V ITOHU T• RL) - 1] 5

UC1832 UC2832/3 UC3832/3 APPLICATION AND OPERATION INFORMATION (cont.) Current Sense Amplifier Offset Voltage vs VADJ UCx832/33 Timer Function UCx832/33 Current Sense Input Configuration Load current, timing capacitor voltage, and output voltage of the regulator under fault conditions. 6

UC1832 UC2832/3 UC3832/3 APPLICATION AND OPERATION INFORMATION (cont.) UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 7

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-9326501M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9326501M2A UC1832L/ 883B 5962-9326501MCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9326501MC A UC1832J/883B 5962-9326501V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9326501V2A UC1832L QMLV 5962-9326501VCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9326501VC A UC1832JQMLV UC1832J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 UC1832J UC1832J883B ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-9326501MC A UC1832J/883B UC1832L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9326501M2A UC1832L/ 883B UC2832DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2832DW & no Sb/Br) UC2833DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2833DW & no Sb/Br) UC2833DWG4 ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2833DW & no Sb/Br) UC2833DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2833DW & no Sb/Br) UC3832DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3832DW & no Sb/Br) UC3832DWG4 ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3832DW & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) UC3833DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3833DW & no Sb/Br) UC3833DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3833DW & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 OTHER QUALIFIED VERSIONS OF UC1832, UC1832-SP, UC2832, UC3832 : •Catalog: UC3832, UC1832 •Enhanced Product: UC2832-EP •Military: UC1832 •Space: UC1832-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UC2833DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 UC3833DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UC2833DWTR SOIC DW 16 2000 367.0 367.0 38.0 UC3833DWTR SOIC DW 16 2000 367.0 367.0 38.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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