UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 HIGH SPEED PWM CONTROLLER FEATURES DESCRIPTION • ComplementaryOutputs The UC1824 family of PWM control devices is • PracticalOperationSwitchingFrequenciesto optimized for high frequency switched mode power 1MHz supply applications. Particular care was given to minimizing propagation delays through the • 50-nsPropagationDelaytoOutput comparators and logic circuitry while maximizing • HighCurrentDualTotemPoleOutputs(1.5A bandwidth and slew rate of the error amplifier. This Peak) controller is designed for use in either current mode • WideBandwidthErrorAmplifier or voltage mode systems with the capability for input voltagefeed-forward. • FullyLatchedLogicWithDoublePulse Suppression Protection circuitry includes a current limit • Pulse-by-PulseCurrentLimiting comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft-start pin which doubles as • SoftStart/MaximumDutyCycleControl a maximum duty cycle clamp. The logic is fully • Under-VoltageLockoutwithHysteresis latched to provide jitter free operation and prohibit • LowStartUpCurrent(1.1mA) multiple pulses at an output. An under-voltage lockout section with 800 mV of hysteresis assures • TrimmedBandgapReference(5.1V– 1%) low start up current. During under-voltage lockout, theoutputsarehighimpedance. BLOCKDIAGRAM Clock 4 RT 5 OSC CT 6 PWMLatch(SetDom.) R 1.25V Ramp 7 + S E/AOut 3 WideBandwidth (SetDom.) Error NI 2 + VIN Amp INV 1 Inhibit 9mA 13 VC 11 Out SoftStart 8 CPILRIMTR 14 INVOUT 1V 12 PwrGnd Shutdown ILIM/SD 9 CPRTR 1.4V Output Inhibit VCC 15 InBteiarnsal 9V 4V Gnd 10 VUCVCLOGood GATE GREENF VREFGood 10 VREF5.1V Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1997–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 DESCRIPTION (CONTINUED) These devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, suchasthegateofapowerMOSFET.Theonstateisdesignedasahighlevel. ABSOLUTE MAXIMUM RATINGS(1)(2) VALUE UNIT Supplyvoltage(pins13,15) 30 V Outputcurrent,sourceorsink(pins11,14) DC 0.5 A Pulse(0.5ms) 2 Analoginputs (Pins1,2,7) –0.3TO7 V (Pin8,9) –0.3TO6 Clockoutputcurrent(pin4) –5 Erroramplifieroutputcurrent(pin3) 5 mA Softstartsinkcurrent(pin8) 20 Oscillatorchargingcurrent(pin5) –5 Powerdissipation 1 W Storagetemperaturerange –65to150 (cid:176) C Leadtemperature(soldering,10seconds) 300 (1) AllvoltagesarewithrespecttoGND(Pin10);allcurrentsarepositiveinto,negativeoutofpart;pinnumbersrefertoDIL-16package. (2) ConsultUnitrodeIntegratedCircuitDatabookforthermallimitationsandconsiderationsofpackage. SOIC-16 DW PACKAGE (TOPVIEW) DIL-16 J OR N PACKAGE (TOPVIEW) 2 SubmitDocumentationFeedback

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 PLCC-20ANDLCC-20 PACKAGEPINFUNCTION QAND LPACKAGES FUNCTION PIN (TOPVIEW) N/C 1 INV 2 NI 3 E/AOut 4 Clock 5 N/C 6 RT 7 CT 8 Ramp 9 SoftStart 10 N/C 11 ILIM/SD 12 Gnd 13 Out 14 PwrGnd 15 N/C 16 VC 17 INVOUT 18 VCC 19 VREF5.1V 20 SubmitDocumentationFeedback 3

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS Unlessotherwisestated,thesespecificationsapplyfor,R =3.65k,C =1nF,V =15V,–55(cid:176) C<T <125(cid:176) Cforthe T T CC A UC1824,–40(cid:176) C<T <85(cid:176) CfortheUC2824,and0(cid:176) C<T <70(cid:176) CfortheUC3824,T =T. A A A J UC1824 UC3824 PARAMETER TESTCONDITIONS UC2824 UNIT MIN TYP MAX MIN TYP MAX ReferenceSection Outputvoltage T =25(cid:176) C,I =1mA 5.05 5.10 5.15 5 5.10 5.20 V J O Lineregulation 10V<V <30V 2 20 2 20 CC mVmV Loadregulation 1mA<I <10mA 5 20 5 20 O Temperaturestability(1) T <T <T 0.2 0.4 0.2 0.4 mV/(cid:176) C MIN A MAX Totaloutputvariation(1) Line,Load,Temperature 5 5.20 4.95 5.25 V Outputnoisevoltage(1) 10Hz<f<10kHz 50 50 μV longtermstability(1) T =125(cid:176) C,1000hrs. 5 25 5 25 mV J Shortcircuitcurrent V =0V –15 –50 –100 –15 –50 –100 mA REF OscillatorSection Initialaccuracy(1) T =25(cid:176) C 360 400 440 360 400 440 kHz J Voltagestability(1) 10V<V <30V 0.2% 2% 0.2% 2% CC Temperaturestability(1) T <T <T 5% 5% MIN A MAX Totalvariation(1) Line,Temperature 340 460 340 460 kHz Clockouthigh 3.9 4.5 3.9 4.5 Clockoutlow 2.3 2.9 2.3 2.9 Ramppeak(1) 2.6 2.8 3 2.6 2.8 3 V Rampvalley(1) 0.7 1 1.25 0.7 1 1.25 Rampvalleytopeak(1) 1.6 1.8 2 1.6 1.8 2 ErrorAmplifierSection Inputoffsetvoltage 10 15 mV Inputbiascurrent 0.6 3 0.6 3 μA Inputoffsetcurrent 0.1 1 0.1 1 μA Openloopgain 1V<V <4V 60 95 60 95 O CMRR 1.5V<V <5.5V 75 95 75 95 dB CM PSRR 10V<V <30V 85 110 85 110 CC Outputsinkcurrent V =1V 1 2.5 1 2.5 PIN3 mA Outputsourcecurrent V =4V –0.5 –1.3 –0.5 –1.3 PIN3 Outputhighvoltage I =–0.5mA 4 4.7 5 4 4.7 5 PIN3 V Outputlowvoltage I =1mA 0 0.5 1 0 0.5 1 PIN3 Unitygainbandwidth(1) 3 5.5 3 5.5 MHz Slewrate(1) 6 12 6 12 V/μs PWMComparatorSection Pin7biascurrent V =0V –1 –5 –1 –5 μA PIN7 Dutycyclerange 0 80 0 85 % Pin3zerodcthreshold V =0V 1.1 1.25 1.1 1.25 V PIN7 Delaytooutput(1) 50 80 50 80 ns Soft-StartSection Chargecurrent V =0.5V 3 9 20 3 9 20 μA PIN8 Dischargecurrent V =1V 1 1 mA PIN8 CurrentLimit/ShutdownSection Pin9biascurrent 0<V <4V 15 10 μA PIN9 (1) Thisparameternot100%testedinproductionbutguaranteedbydesign. 4 SubmitDocumentationFeedback

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS (continued) Unlessotherwisestated,thesespecificationsapplyfor,R =3.65k,C =1nF,V =15V,–55(cid:176) C<T <125(cid:176) Cforthe T T CC A UC1824,–40(cid:176) C<T <85(cid:176) CfortheUC2824,and0(cid:176) C<T <70(cid:176) CfortheUC3824,T =T. A A A J UC1824 UC3824 PARAMETER TESTCONDITIONS UC2824 UNIT MIN TYP MAX MIN TYP MAX Currentlimitthreshold 0.9 1 1.1 0.9 1 1.1 V Shutdownthreshold 1.25 1.40 1.55 1.25 1.40 1.55 Delaytooutput 50 80 50 80 ns OutputSection I =20mA 0.25 0.40 0.25 0.40 OUT Outputlowlevel I =200mA 1.2 2.2 1.2 2.2 OUT V I =–20mA 13 13.5 13 13.5 OUT Outputhighlevel I =–200mA 12 13 12 13 OUT Collectorleakage V =30V 100 500 10 500 μA C Rise/falltime(2) CL=1nF 30 60 30 60 ns Under-VoltageLockoutSection Startthreshold 8.8 9.2 9.6 8.8 9.2 9.6 V UVLOhysteresis 0.4 0.8 1.2 0.4 0.8 1.2 SupplyCurrentSection Startupcurrent V =8V 1.1 2.5 1.1 2.5 CC mA ICC V ,V ,V =0V;V =1V 22 33 22 33 PIN1 PIN7 PIN9 PIN2 (2) Thisparameternot100%testedinproductionbutguaranteedbydesign. UC1824 Printed Circuit Board Layout Considerations High speed circuits demand careful attention to layout and component placement. To assure proper performanceoftheUC1824followtheserules: 1. Useagroundplane. 2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves thispurpose. 3. Bypass V , V , and V . Use 0.1-μF monolithic ceramic capacitors with low equivalent series CC C REF inductance.Allowlessthan1cmoftotalleadlengthforeachcapacitorbetween the bypassed pin and the groundplane. 4. Treatthetimingcapacitor,C ,likeabypasscapacitor. T SubmitDocumentationFeedback 5

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 Error Amplifier Circuit SimplifiedSchematic OpenLoopFrequencyResponse Unity Gain Slew Rate Synchronized Operation TwoUnitsinCloseProximity GeneralizedSynchronization 6 SubmitDocumentationFeedback

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 Oscillator Circuit Primary OutputDeadtime vs C (3k£R £100k) T T m Primary Output Deadtime vs Frequency TimingResistance vs Frequency 160 1.0 nF 140 ns) 120 ( D T 100 470 pF 80 10k 100k 1M FREQ (Hz) TypicalNon-OverlapTime(TNO)OverTemperature 80 70 60 50 40 TNO(ns) 30 20 10 0 -75 -50 -25 0 25 50 75 100 125 T(°C) Non-OverlapTime(TNO) SubmitDocumentationFeedback 7

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 Forward Technique for Off-Line Voltage Mode Application Constant Volt-Second Clamp Circuit Thecircuitshownherewillachieveaconstantvolt-sec- ond product clamp over varying input voltages. The rampgeneratorcomponents,RTandCRarechosenso that the ramp atPin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be com- pletelydischargedduringtheminimumdeadtime. Output Section SimplifiedSchematic Rise/FallTime(CL=1nF) Rise/Fall Time (CL=10 nF) SaturationCurves 8 SubmitDocumentationFeedback

UC1824 UC2824 UC3824 www.ti.com SLUS326A–MARCH1997–REVISEDJULY2007 Open-Loop Laboratory Test Fixture UDG-92036-2 This test fixture is useful for exercising many of the As with any widebandcircuit, careful groundingandby- UC1824’sfunctionsandmeasuringtheirspecifications. pass procedures should be followed. The use of a groundplaneishighlyrecommended. SubmitDocumentationFeedback 9

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC2824DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2824DW & no Sb/Br) UC2824N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2824N & no Sb/Br) UC3824DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3824DW & no Sb/Br) UC3824DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3824DW & no Sb/Br) UC3824N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3824N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UC3824DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UC3824DWTR SOIC DW 16 2000 367.0 367.0 38.0 PackMaterials-Page2

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