Product Order Technical Tools & Support & Folder Now Documents Software Community UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 UCx84x Current-Mode PWM Controllers 1 Features 1 • Optimizedforoff-lineandDC-to-DCconverters The UCx84x family offers a variety of package options, temperature range options, choice of • Lowstart-upcurrent(< 1mA) maximum duty cycle, and choice of turnon and turnoff • Automaticfeedforwardcompensation thresholds and hysteresis ranges. Devices with • Pulse-by-pulsecurrentlimiting higher turnon or turnoff hysteresis are ideal choices • Enhancedload-responsecharacteristics for off-line power supplies, while the devices with a narrower hysteresis range are suited for DC-DC • Undervoltagelockoutwithhysteresis applications. The UC184x devices are specified for • Double-pulsesuppression operation from –55°C to 125°C, the UC284x series is • High-currenttotem-poleoutput specified for operation from –40°C to 85°C, and the UC384x series is specified for operation from 0°C to • Internallytrimmedbandgapreference 70°C. • Upto500-kHzoperation • Erroramplifierwithlowoutputresistance DeviceInformation(1) PARTNUMBER PACKAGE(PIN) BODYSIZE(NOM) 2 Applications CDIP(8) 9.60mm×6.67mm • Switchingregulatorsofanypolarity UC184x LCCC(20) 8.89mm×8.89mm • Transformer-coupledDC-DCconverters CFP(8) 9.21mm×5.97mm SOIC(8) 4.90mm×3.91mm 3 Description UC284x SOIC(14) 8.65mm×3.91mm The UCx84x series of control integrated circuits PDIP(8) 9.81mm×6.35mm provide the features that are necessary to implement SOIC(8) 4.90mm×3.91mm off-line or DC-to-DC fixed-frequency current-mode SOIC(14) 8.65mm×3.91mm control schemes, with a minimum number of external UC384x components. The internally implemented circuits PDIP(8) 9.81mm×6.35mm include an undervoltage lockout (UVLO), featuring a CFP(8) 9.21mm×5.97mm start-up current of less than 1 mA, and a precision (1) For all available packages, see the orderable addendum at reference trimmed for accuracy at the error amplifier theendofthedatasheet. input. Other internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control, and a totem-pole output stage that is designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when itisintheoffstate. SimplifiedApplication VIN VCC OUTPUT VREF ISENSE UC2843 VFB RT/CT GROUND COMP Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes........................................20 2 Applications........................................................... 1 9 ApplicationandImplementation........................ 21 3 Description............................................................. 1 9.1 ApplicationInformation............................................21 4 RevisionHistory..................................................... 2 9.2 TypicalApplication..................................................21 5 DeviceComparisonTable..................................... 3 10 PowerSupplyRecommendations..................... 32 6 PinConfigurationandFunctions......................... 3 11 Layout................................................................... 33 11.1 LayoutGuidelines.................................................33 7 Specifications......................................................... 6 11.2 LayoutExample....................................................34 7.1 AbsoluteMaximumRatings......................................6 12 DeviceandDocumentationSupport................. 35 7.2 ESDRatings..............................................................6 7.3 RecommendedOperatingConditions.......................6 12.1 RelatedLinks........................................................35 7.4 ThermalInformation..................................................6 12.2 ReceivingNotificationofDocumentationUpdates35 7.5 ElectricalCharacteristics...........................................7 12.3 CommunityResources..........................................35 7.6 TypicalCharacteristics..............................................9 12.4 Trademarks...........................................................35 12.5 ElectrostaticDischargeCaution............................35 8 DetailedDescription............................................ 11 12.6 Glossary................................................................35 8.1 Overview.................................................................11 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagrams.....................................11 Information........................................................... 35 8.3 FeatureDescription.................................................12 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionE(January2017)toRevisionF Page • ChangedUVLOTableupdated ............................................................................................................................................. 8 ChangesfromRevisionD(August2016)toRevisionE Page • ChangedV equation.............................................................................................................................................. 23 REFLECTED • ChangedD equation. ..................................................................................................................................................... 24 MAX ChangesfromRevisionC(June2007)toRevisionD Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • ChangedvaluesintheThermalInformationtable ................................................................................................................ 6 2 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 5 Device Comparison Table UVLO TURNONAT16V TURNONAT8.4V TURNOFFAT10V TURNOFFAT7.6V TEMPERATURERANGE MAXDUTYCYCLE SUITABLEFOROFF-LINE SUITABLEFORDC-DC APPLICATIONS APPLICATIONS UC1842 UC1843 –55°Cto125°C UC2842 UC2843 –40°Cto85°C Upto100% UC3842 UC3843 0°Cto70°C UC1844 UC1845 –55°Cto125°C UC2844 UC2845 –40°Cto85°C Upto50% UC3844 UC3845 0°Cto70°C 6 Pin Configuration and Functions D,JG,andPPackages 8-PinSOIC,CDIP,andPDIP DandWPackages TopView 14-PinSOICandCFP TopView COMP 1 8 VREF COMP 1 14 VREF NC 2 13 NC VFB 2 7 VCC VFB 3 12 VCC ISENSE 3 6 OUTPUT NC 4 11 VC RT/CT 4 5 GROUND ISENSE 5 10 OUTPUT NC 6 9 GROUND RT/CT 7 8 PWRGND FKPackage 20-PinLCCC TopView MP EF C O C R C N C N V N 3 2 1 20 19 NC 4 18 VCC VFB 5 17 VC NC 6 16 NC ISENSE 7 15 OUTPUT NC 8 14 NC 9 10 11 12 13 C T C D D N C N N N T/ G U R R O W R P G Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com PinFunctions PIN SOIC, CDIP, SOIC, LCCC TYPE DESCRIPTION NAME CFP PDIP (20) (14) (8) Erroramplifiercompensationpin.Connectexternalcompensation componentstothispintomodifytheerroramplifieroutput.Theerror COMP 1 1 2 O amplifierisinternallycurrent-limitedsotheusercancommandzero dutycyclebyexternallyforcingCOMPtoGROUND. Analogground.FordevicepackageswithoutPWRGND,GROUND GROUND 5 9 13 G functionsasbothpowergroundandanalogground. Powerground.FordevicepackageswithoutPWRGND,GROUND PWRGND — 8 12 G functionsasbothpowergroundandanalogground Primary-sidecurrentsensepin.Connecttocurrentsensingresistor. ThePWMusesthissignaltoterminatetheOUTPUTswitch ISENSE 3 5 7 I conduction.Avoltagerampcanbeappliedtothispintorunthe devicewithavoltage-modecontrolconfiguration. 1,3,4,6, NC — 2,4,6,13 8,9,11, — Donotconnect 14,16,19 OUTPUTisthegatedrivefortheexternalMOSFET.OUTPUTisthe outputoftheon-chipdriverstageintendedtodirectlydrivea OUTPUT 6 10 15 O MOSFET.Peakcurrentsofupto1Aaresourcedandsunkbythis pin.OUTPUTisactivelyheldlowwhenVCCisbelowtheturnon threshold. Fixedfrequencyoscillatorsetpoint.Connecttimingresistor,R ,to RT VREFandtimingcapacitor,C ,toGROUNDfromthispintosetthe CT switchingfrequency.Forbestperformance,keepthetimingcapacitor leadtothedeviceGROUNDasshortanddirectaspossible.If possible,useseparategroundtracesforthetimingcapacitorandall otherfunctions. The frequency of the oscillator can be estimated with the following equations: RT/CT 4 7 10 I/O 1.72 f = OSC R ×C RT CT (1) wheref isinHertz,R isinOhmsandC is inFarads.Never OSC RT CT useatimingresistorlessthan5kΩ.ThefrequencyoftheOUTPUT gatedriveoftheUCx842andUCx843,f ,isequaltof atupto SW OSC 100%dutycycle;thefrequencyoftheUCx844andUCx845isequal tohalfofthef frequencyatupto50%dutycycle. OSC Biassupplyinputfortheoutputgatedrive.ForPWMcontrollersthat donothavethispin,thegatedriverisbiasedfromtheVCCpin.VC VC — 11 17 I musthaveabypasscapacitoratleast10timesgreaterthanthegate capacitanceofthemainswitchingFETusedinthedesign. Analogcontrollerbiasinputthatprovidespowertothedevice.Total VCCcurrentisthesumofthequiescentVCCcurrentandthe averageOUTPUTcurrent.Knowingtheswitchingfrequencyandthe MOSFETgatecharge,Q ,theaverageOUTPUTcurrentcanbe g calculatedfrom: VCC 7 12 18 I IOUTPUT =Qg×fSW (2) Abypasscapacitor,typically0.1µF,connecteddirectlytoGROUND with minimal trace length, is required on this pin. An additional bypasscapacitoratleast10timesgreaterthanthegatecapacitance of the main switching FET used in the design is also required on VCC. Invertinginputtotheinternalerroramplifier.VFBisusedtocontrol VFB 2 3 5 I thepowerconvertervoltage-feedbackloopforstability. 4 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 PinFunctions(continued) PIN SOIC, CDIP, SOIC, LCCC TYPE DESCRIPTION NAME CFP PDIP (20) (14) (8) 5-Vreferencevoltage.VREFisusedtoprovidechargingcurrentto theoscillatortimingcapacitorthroughthetimingresistor.Itis importantforreferencestabilitythatVREFisbypassedtoGROUND VREF 8 14 20 O withaceramiccapacitorconnectedasclosetothepinaspossible.A minimumvalueof0.1-µFceramicisrequired.AdditionalVREF bypassingisrequiredforexternalloadsonVREF. Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Lowimpedancesource 30 V V VCC I <30mA SelfLimiting VCC V andV Analoginputvoltage –0.3 6.3 V VFB ISENSE V InputVoltage,QandDPackageonly 30 V VC I Outputdrivecurrent ±1 A OUTPUT I Erroramplifieroutputsinkcurrent 10 mA COMP E Outputenergy(capacitiveload) 5 µJ OUTPUT T Junctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 7.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) ±3000 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101,allpins(2) ±3000 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT V andV (1) Supplyvoltage 12 28 V VCC VC V Inputvoltage 2.5 V VFB V Inputvoltage 1 V ISENSE I Supplycurrent,externallylimited 25 mA VCC I Averageoutputcurrent 200 mA OUTPUT I Referenceoutputcurrent –20 mA VREF f Oscillatorfrequency 100 500 kHz OSC UC184x –55 125 T Operatingfree-airtemperature UC284x –40 85 °C A UC384x 0 70 (1) TheserecommendedvoltagesforVCandPOWERGROUNDapplyonlytotheDpackage. 7.4 Thermal Information UCx84x THERMALMETRIC(1) D(SOIC) D(SOIC) P(PDIP) FK(LCCC) UNIT 8PINS 14PINS 8PINS 20PINS R Junction-to-ambientthermalresistance 104.8 78.2 53.7 — °C/W θJA R Junction-to-case(top)thermalresistance 47.3 37.1 46.7 36.2 °C/W θJC(top) R Junction-to-boardthermalresistance 45.9 32.6 31 35.4 °C/W θJB ψ Junction-to-topcharacterizationparameter 8.2 7.3 17.1 — °C/W JT ψ Junction-to-bottomcharacterizationparameter 45.2 32.4 30.9 — °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 Thermal Information (continued) UCx84x THERMALMETRIC(1) D(SOIC) D(SOIC) P(PDIP) FK(LCCC) UNIT 8PINS 14PINS 8PINS 20PINS R Junction-to-case(bottom)thermalresistance — — — 4.1 °C/W θJC(bottom) 7.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted)–55°C≤T ≤125°CfortheUC184x;–40°C≤T ≤85°C A A fortheUC284x,0°C≤T ≤70°CfortheUC384x,V =15V(1);0.1µFcapacitorfromVCCtoGROUND,0.1µFcapacitor A VCC fromVREFtoGROUND,R =10kΩ;C =3.3nF,T =T . RT CT J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT REFERENCESECTION UC184x and 4.95 5 5.05 VVREF Referencevoltage IVREF=1mA,TJ=25°C UC284x V UC384x 4.9 5 5.1 Lineregulation 12≤VCC≤25V 6 20 mV Loadregulation 1≤I ≤20mA 6 25 mV VREF Temperaturestability See (2) (3) 0.2 0.4 mV/°C UC184x and 4.9 5.1 Totaloutputvariation Line,load,temperature (2) UC284x V UC384x 4.82 5.18 Outputnoisevoltage 10Hz≤f ≤10kHz, (2)T =25°C 50 μV OSC J Longtermstability T =125°C,1000Hrs (2) 5 25 mV A Outputshortcircuit –30 –100 –180 mA OSCILLATORSECTION f Initialaccuracy T =25°C(4) 47 52 57 kHz OSC J Voltagestability 12≤VCC≤25V 0.2% 1% Temperaturestability T ≤T ≤T (2) 5% MIN A MAX V Amplitude Peak-to-peak (2) 1.7 V RT/CT ERRORAMPLIFIERSECTION UC184x and 2.45 2.5 2.55 VVFB Inputvoltage VCOMP=2.5V UC284x V UC384x 2.42 2.5 2.58 UC184x and –1 IVFB Inputbiascurrent UC284x µA UC384x –2 A 2≤V ≤4V 65 90 dB VOL COMP Unitygainbandwidth T =25°C (2) 0.7 1 MHz J PSRR Powersupplyrejectionratio 12≤VCC≤25V 60 70 dB I COMPsinkcurrent V =2.7V,V =1.1V 2 6 (snk) VFB COMP mA I COMPsourcecurrent V =2.3V,V =5V –0.5 –0.8 (src) VFB COMP (1) AdjustVCCabovethestartthresholdbeforesettingat15V (2) Specifiedbydesign.Notproductiontested. (3) Temperaturestability,sometimesreferredtoasaveragetemperaturecoefficient,isdescribedbytheequation: VREF FVREF Temp Stability = :max; :min; T FT J:max; J:min; VREF andVREF arethemaximumandminimumreferencevoltages min max measuredovertheappropriatetemperaturerange.Notethattheextremesinvoltagedonotnecessarilyoccurattheextremesin temperature. (4) OUTPUTswitchingfrequency,f ,equalstheoscillatorfrequency,f ,fortheUCx842andUCx843.OUTPUTswitchingfrequency, SW OSC f ,isonehalfoscillatorfrequency,f ,fortheUCx844andUCx845. SW OSC Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Electrical Characteristics (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted)–55°C≤T ≤125°CfortheUC184x;–40°C≤T ≤85°C A A fortheUC284x,0°C≤T ≤70°CfortheUC384x,V =15V(1);0.1µFcapacitorfromVCCtoGROUND,0.1µFcapacitor A VCC fromVREFtoGROUND,R =10kΩ;C =3.3nF,T =T . RT CT J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V COMP High-leveloutputvoltage V =2.3V,R =15-kΩCOMPtoGROUND 5 6 High VFB L V V COMP Low-leveloutputvoltage V =2.7V,R =15-kΩCOMPtoVREF 0.7 1.1 Low VFB L CURRENTSENSESECTION A Gain See (5) (6) 2.85 3 3.15 V/V CS V Maximuminputsignal V =5V (5) 0.9 1 1.1 V ISENSE COMP PSRR Powersupplyrejectionratio 12V≤V ≤25V (2) (5) 70 dB VCC I Inputbiascurrent –2 –10 µA ISENSE t Delaytooutput V steppedfrom0Vto2V (2) 150 300 ns DLY ISENSE OUTPUTSECTION I =20mA 0.1 0.4 SINK V Low Low-levelOUTPUTvoltage V OUT I =200mA 1.5 2.2 SINK I =20mA 13 13.5 SOURCE V High High-levelOUTPUTvoltage V OUT I =200mA 12 13.5 SOURCE t Risetime (2) C =1nF,T =25°C 50 150 ns RISE OUTPUT J t Falltime (2) C =1nF,T =25°C, 50 150 ns FALL OUTPUT J UNDERVOLTAGELOCKOUT(UVLO) UC1842/4andUC2842/4 15 16 17 VCC Enablethreshold UC3842/4 14.5 16 17.5 V ON UCx843/5 7.8 8.4 9 UC1842/4andUC2842/4 9 10 11 VCC UVLOoffthreshold UC3842/4 8.5 10 11.5 V OFF UCx843/5 7 7.6 8.2 PWM UCx842/3 95% 97% 100% D Maximumdutycycle UC1844/5andUC2844/5 46% 48% 50% MAX UC3844/5 47% 48% 50% D Minimumdutycycle 0% MIN TOTALSTANDBYCURRENT I Start-upcurrent 0.5 1 VCC mA I Operatingsupplycurrent V =V =0V 11 17 VCC VFB ISENSE VCCZenervoltage I =25mA 30 34 V VCC (5) ParametermeasuredattrippointoflatchwithVFB=0V. (6) Gaindefinedas:A=ΔV /ΔV ,0V≤V ≤0.8V. COMP ISENSE ISENSE 8 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 7.6 Typical Characteristics 9.2 1.1 9 d (V) 1 8.8 hol 0.9 es 0.8 I (mA)DISCHARGE 888...2468 nt Sense Input Thr 0000....4567 e 0.3 77..68 V, CurrTH 00..12 TTTAAA === 12(cid:16)52555qCqqCC 7.4 0 -75 -50 -25 0 25 50 75 100 125 150 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Temperature (C) D001 VO, Error Amp Output Voltage (V) D005 Figure1.OscillatorDischargeCurrent Figure2.CurrentSenseInputThresholdvs vsTemperatureforVCC=15VandV =2V ErrorAmplifierOutputVoltageforVCC=15V OSC 100 200 0 10 Gain Phase -1 9 Gain (dB) 24680000 051105000 ce Saturation Voltage (V) ------765432 SSSSooiinnuukkrr ccSSeeaa ttSSuuaarraattuuttiirrooaannttii ooaanntt -2aa55tt5 2-C 5C55 C C 345678 k Saturation Voltage (V) our -8 2 Sin 0 -50 S -9 1 -20 -100 -10 0 10 100 1000 10000 100000 1000000 1E+7 0 100 200 300 400 500 600 700 800 Freq (Hz) D003 IO, Output Load Current (mA) D005 Figure3.ErrorAmplifierOpen-LoopGainandPhasevs Figure4.OUTPUTSaturationVoltagevs Frequency,VCC=15V,R =100kΩ,andT =25°C LoadCurrentforVCC=15Vwith5-msInputPulses L A 180 0 Ta = 125 C Ta = 25 C 160 V) -10 Ta = -40 C m 140 a ( elt -20 D A) 120 e (mSC 100 Voltag -30 I e nc -40 80 e er ef R -50 60 40 -60 -75 -50 -25 0 25 50 75 100 125 150 0 20 40 60 80 100 120 140 160 Temperature (C) Source Current (mA) D006 D007 Figure5.VREFShort-CircuitCurrentvs Figure6.VREFVoltagevsSourceCurrent TemperatureforVCC=15V Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Typical Characteristics (continued) 5.2 4 Source, TA = 25°C 5.15 Sink, TA = 25°C Source, TA = –55°C 5.1 e (V) 3 Sink, TA = –55°C 5.05 g V (V)REF 4.955 ation Volta 2 ur at 4.9 S 1 4.85 4.8 0 -75 -50 -25 0 25 50 75 100 125 150 0.01 0.1 1 Temperature (C) D008 Output Current (A) Figure7.VREFVoltagevsTemperature Figure8.OutputSaturation 3300 10 s)P 5 (E M TI D A E D t 1 0.5 0.3 1 5 10 50 100 CCT (nF) D006 Figure9.DeadTimevsTimingCapacitance,C CT 100 (cid:159)) 50 N e ( 20 c sistan 10 CCT (nF)100 e g R 47 min 22 Ti 5 10 4.7 2 2.2 1 1 100 1000 10 k 100 k 1 M Frequency (Hz) Figure10. TimingResistance,R ,vsFrequency RT 10 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 8 Detailed Description 8.1 Overview The UCx84x series of control integrated circuits provide the features necessary to implement AC-DC or DC-to- DC fixed-frequency current-mode control schemes with a minimum number of external components. Protection circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits include a start-up current of less than 1 mA, a precision reference trimmed for accuracy at the error amplifier input, logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control, andatotem-poleoutputstagedesignedtosourceorsinkhigh-peakcurrent.Theoutputstage,suitablefordriving N-channelMOSFETs,islowwhenitisintheoff-state. Major differences between members of these series are the UVLO thresholds, acceptable ambient temperature range, and maximum duty-cycle. Typical UVLO thresholds of 16 V (ON) and 10 V (OFF) on the UCx842 and UCx844 devices make them ideally suited to off-line AC-DC applications. The corresponding typical thresholds for the UCx843 and UCx845 devices are 8.4 V (ON) and 7.6 V (OFF), making them ideal for use with regulated input voltages used in DC-DC applications. The UCx842 and UCx843 devices operate to duty cycles approaching 100%. The UCx844 and UCx845 obtain a duty-cycle range of 0% to 50% by the addition of an internaltoggleflip-flop,whichblankstheoutputoffeveryotherclockcycle. The UC184x-series devices are characterized for operation from –55°C to 125°C. UC284x-series devices are characterizedforoperationfrom−40°Cto85°C.TheUC384xdevices are characterized for operation from 0°C to 70°C. 8.2 Functional Block Diagrams VCC UVLO 34 V EN 5-V VREF Reference GROUND Internal Bias VC 2.5 V VREF Good Logic RT/CT Osc OUTPUT 2R S + PWRGND E/A PWM VFB R Latch R 1 V PWM COMP Comparator ISENSE UCx842 UCx843 Copyright © 2016, Texas Instruments Incorporated Figure11. UCx842andUCx843BlockDiagram,NoToggle Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Functional Block Diagrams (continued) VCC UVLO 34 V EN 5-V VREF Reference GROUND Internal Bias VC 2.5 V VREF Good Logic RT/CT Osc OUTPUT T 2R S + PWRGND E/A PWM VFB R Latch R 1 V PWM COMP Comparator ISENSE UCx844 UCx845 Copyright © 2016, Texas Instruments Incorporated Figure12. UCx844andUCx845BlockDiagram,Toggle 8.3 Feature Description 8.3.1 DetailedPinDescription 8.3.1.1 COMP The error amplifier in the UCx84x family is an open collector in parallel with a current source, with a unity-gain bandwidth of 1 MHz. The COMP terminal can both source and sink current. The error amplifier is internally current-limited,sothatonecancommandzerodutycyclebyexternallyforcingCOMPtoGROUND. 8.3.1.2 VFB VFBistheinvertinginput of the error amplifier. VFB is used to control the power converter voltage-feedback loop for stability. For best stability, keep VFB lead length as short as possible and VFB stray capacitance as small as possible. 8.3.1.3 ISENSE The UCx84x current sense input connects to the PWM comparator. Connect ISENSE to the MOSFET source current sense resistor. The PWM uses this signal to terminate the OUTPUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration or to add slope compensation. To prevent false triggering due to leading edge noises, an RC current sense filter may be required.Thegainofthecurrentsenseamplifieristypically3V/V. 12 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 Feature Description (continued) 8.3.1.4 RT/CT RT/CT is the oscillator timing pin. For fixed frequency operation, set the timing capacitor charging current by connecting a resistor from VREF to RT/CT. Set the frequency by connecting timing capacitor from RT/CT to GROUND.Forthebestperformance,keepthetimingcapacitorleadtoGROUND as short and direct as possible. Ifpossible,useseparategroundtracesforthetimingcapacitorandallotherfunctions. The UCx84x’s oscillator allows for operation to 500 kHz. The device uses an external resistor to set the charging current for the external capacitor, which determines the oscillator frequency. The recommended range of timing resistor values is between 5 kΩ and 100 kΩ; the recommended range of timing capacitor values is between 1 nF and100nF. 1.72 f = OSC R × C RT CT (3) Inthisequation,theswitchingfrequency,f isinHz,R isinΩ,andC isinFarads. SW RT CT 8.3.1.5 GROUND GROUND is the signal and power returning ground. TI recommends separating the signal return path and the highcurrentgatedriverpathsothatthesignalisnotaffectedbytheswitchingcurrent. 8.3.1.6 OUTPUT The high-current bipolar totem-pole output of the UCx84x devices sinks or sources up to 1-A peak of current. The OUTPUT pin can directly drive a MOSFET. The OUTPUT of the UCx842 and UCx843 devices switches at the same frequency as the oscillator and can operate near 100% duty cycle. In the UCx844 and UCx845 devices, the switching frequency of OUTPUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle in the UCx844 and UCx845 to < 50%. Schottky diodes may be necessary on the OUTPUT pin to prevent overshoot and undershoot due to high impedance to the supply rail and to ground, respectively. A bleeder resistor, placed between the gate and the source of the MOSFET, should be used to prevent activating the power switch with extraneous leakage currents during undervoltage lockout. An external clamp circuit may be necessary to prevent overvoltage stress on the MOSFET gate when VCC exceeds the gate voltagerating. 8.3.1.7 VCC VCC is the power input connection for this device. In normal operation, power VCC through a current-limiting resistor. Although quiescent VCC current is only 0.5 mA, the total supply current is higher, depending on the OUTPUT current. Total VCC current is the sum of quiescent VCC current and the average OUTPUT current. Knowing the operating frequency and the MOSFET gate charge (Q ), average OUTPUT current can be g calculatedfromEquation4. I = Q ×f OUTPUT g SW (4) The UCx84x has a VCC supply voltage clamp of 34 V typical, but the absolute maximum value for VCC from a low-impedance source is 30 V. For applications that have a higher input voltage than the recommended VCC voltage, place a resistor in series with VCC to increase the source impedance. The maximum value of this resistoriscalculatedwithEquation5. V FV IN:min; VCC:max; R = VCC:max; I +kQ ×f o VCC g SW (5) In Equation 5, V is the minimum voltage that is used to supply VCC, V is the maximum VCC clamp IN(min) VCC(max) voltage and I is the IC supply current without considering the gate driver current and Q is the external power VCC g MOSFETgatechargeandf istheswitchingfrequency. SW The turnon and turnoff thresholds for the UCx84x family are significantly different: 16 V and 10 V for the UCx842 and UCx844; 8.4 V and 7.6 V for the UCx843 and UCx855. To ensure against noise related problems, filter VCC withanelectrolyticandbypasswithaceramiccapacitortoground.KeepthecapacitorsclosetotheICpins. Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Feature Description (continued) 8.3.1.8 VREF VREF is the voltage reference for the error amplifier and also for many other internal circuits in the IC. The high- speed switching logic uses VREF as the logic power supply. The 5-V reference tolerance is ±2% for the UCx84x family. The output short-circuit current is 30 mA. For reference stability and to prevent noise problems with high- speed switching transients, bypass VREF to ground with a ceramic capacitor close to the IC package. A minimumof0.1-µFceramiccapacitorisrequired.AdditionalVREFbypassingisrequiredforexternalloadson the reference.Anelectrolyticcapacitormayalsobeusedinadditiontotheceramiccapacitor. When VCC is greater than 1 V and less than the UVLO threshold, a 5-kΩ resistor pulls VREF to ground. VREF can be used as a logic output indicating power-system status because when VCC is lower than the UVLO threshold,VREFisheldlow. 8.3.2 Pulse-by-PulseCurrentLimiting Pulse-by-pulse limiting is inherent in the current mode control scheme. An upper limit on the peak current can be established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and powersemiconductorelementswhileensuringreliablesupplyoperation. 8.3.3 Current-Sense An external series resistor, R , senses the current and converts this current into a voltage that becomes the CS input to the ISENSE pin. The ISENSE pin is the noninverting input to the PWM comparator. The ISENSE input is compared to a signal proportional to the error amplifier output voltage; the gain of the current sense amplifier is typically3V/V.ThepeakI currentisdeterminedbyEquation6: SENSE V ISENSE I = SENSE R CS (6) The typical value for V is 1 V. A small RC filter, R and C , may be required to suppress switch ISENSE CSF CSF transients caused by the reverse recovery of a secondary side diode or equivalent capacitive loading in addition to parasitic circuit impedances. The time constant of this filter should be considerably less than the switching periodoftheconverter. Error Amplifier 2 R COMP R 1 V I PWM SENSE Comparator R CSF ISENSE R C CS CSF GROUND Copyright © 2016, Texas Instruments Incorporated Figure13. Current-SenseCircuitSchematic 14 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 Feature Description (continued) 8.3.4 ErrorAmplifierWithLowOutputResistance The error amplifier output is an open collector in parallel with a current source. With a low output resistance, various impedance networks may be used on the compensation pin input for error amplifier feedback. The error amplifier output, COMP, is frequently used as a control port for secondary-side regulation by using an external secondary-side adjustable voltage regulator, such as a TL431, to send an error signal across the secondary-to- primary isolation boundary through an opto-isolator, in this configuration connect the COMP pin directly to the opto-isolator feedback. On the primary side, the inverting input to the UCx48x error amplifier, VFB, should be connected to GROUND. With VFB tied to GROUND, the error amplifier output, COMP, is forced to its high state and sources current, typically 0.8 mA. The opto-isolator must overcome the source current capability to control theCOMPpinbelowtheerroramplifieroutputhighlevel,VOH. For primary-side regulation, configure the inverting input to the error amplifier, VFB, with a resistor divider to provide a signal that is proportional to the converter output voltage being regulated. Add the voltage loop compensation components between VFB and COMP. The internal noninverting input to the error amplifier is trimmed to 2.5 V. For best stability, keep VFB lead length as short as possible and minimize the stray capacitanceonVFB. The internal resistor divider on COMP is maintained at an R:2R ratio, the specific values of these internal resistorsshouldnotbecriticalinanyapplication. 0.5 mA 2.5 V + 2 R Error Amplifier R 1 V s(cid:3) PWM ZI Comparator VFB ZF COMP ISENSE Erroramplifiercansourceorsinkupto0.5mA. Figure14. Error-AmplifierConfigurationSchematic 8.3.5 UndervoltageLockout The UCx84x devices feature undervoltage lockout protection circuits for controlled operation during power-up and power-down sequences. The UVLO circuit insures that VCC is adequate to make the UCx84x fully operationalbeforeenablingtheoutputstage. Undervoltage lockout thresholds for the UCx842, UCx843, UCx844, andUCx845devicesareoptimizedfor two groups of applications: off-line power supplies and DC-DC converters. The6-VhysteresisintheUCx842andUCx844devicespreventsVCC oscillations during power sequencing. This wider VCC to VCC range, make these devices ideally suited to off-line AC input applications. The UCx843 ON OFF and UCx845 controllers have a much narrower VCC to VCC hysteresis and may be used in DC to DC ON OFF applicationswheretheinputisconsideredregulated. Start-up current is less than 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as illustrated by Figure 17. During normal circuit operation, VCC is developed from auxiliary winding N with D A BIAS and C . At start-up, however, C must be charged to 16 V through R . With a start-up current of 1 mA, VCC VCC START R can be as large as 100 kΩ and still charge C when V = 90 V RMS (low line). Power dissipation in START VCC AC R wouldthenbelessthan350mWevenunderhighline(V =130VRMS)conditions. START AC Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Feature Description (continued) During UVLO the IC draws less than 1 mA of supply current. Once crossing the turnon threshold the IC supply current increases to a maximum of 17 mA, typically 11 mA, During undervoltage lockout, the output driver is biased to a high impedance state and sinks minor amounts of current. A bleeder resistor, placed between the gate and the source of the MOSFET should be used to prevent activating the power switch with extraneous leakagecurrentsduringundervoltagelockout. < 17 mA VCC 7 ON/OFF Command to rest of device I VCC UCx842 UCx843 UCx844 UCx845 < 1 mA V (V) 16 8.4 ON VOFF VON VOFF (V) 10 7.6 VVCC Copyright © 2016, Texas Instruments Incorporated Figure15.UVLOThreshold Figure16.UVLOONandOFFProfile N N P S R START D N BIAS A I (cid:149)(cid:3)1mA VCC V AC C IN VCC OUTPUT C VCC 0.1 PF GROUND R CS Figure17. ProvidingPowertoUCx84x 8.3.6 Oscillator The oscillator allows for up to 500-kHz switching frequency. The OUTPUT gate drive is the same frequency as the oscillator in the UCx842 and UCx843 devices and can operate near 100% duty cycle. In the UCx844 and UCx845 devices, the frequency of OUTPUT is one-half that of the oscillator due to an internal T flipflop that blankstheoutputoffeveryotherclockcycle,resultingina maximum duty cycle for these devices of < 50% of the switching frequency. An external resistor, R , connected from VREF to RT/CT sets the charging current for the RT timing capacitor, C , which is connected from RT/CT to GROUND. An R value greater than 5 kΩ is CT RT recommended on RT/CT to set the positive ramp time of the internal oscillator. Using a value of 5 kΩ or greater for R maintains a favorable ratio between the internal impedance and the external oscillator set resistor and RT resultsinminimalchangeinfrequencyovertemperature.Usingavalueoflessthe recommended minimum value mayresultinfrequencydriftovertemperature,parttolerances,orprocessvariations. 16 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 Feature Description (continued) The peak-to-peak amplitude of the oscillator waveform is 1.7 V in UCx84x devices. The UCx842 and UCx843 have a maximum duty cycle of approximately 100%, whereas the UCx844 and UCx845 are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most flyback and forward converters.ForoptimumICperformancethedead-timeshouldnot exceed 15% of the oscillator clock period. The dischargecurrent,typically6 mA at room temperature, sets the dead time, see Figure 9. During the discharge, or dead time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle D MAX to: D = 1F:t ×f ; MAX DEADTIME OSC (7) Equation 8 applies to UCx842 and UCx843 units because the OUTPUT switches at the same frequency as the oscillatorandthemaximumdutycyclecanbeashighas100%. f OSC D = 1 t × MAX Fl DEADTIME 2 p (8) Equation 8 applies to UCx844 and UCx845 units because the OUTPUT switches at half the frequency as the oscillatorandthemaximumdutycyclecanbeashighas50%. Whenthepowertransistorturnsoff,anoisespikeiscoupledtotheoscillatorRT/CTterminal.Athighduty cycles, the voltage at RT/CT is approaching its threshold level (approximately 2.7 V, established by the internal oscillator circuit) when this spike occurs. A spike of sufficient amplitude prematurely trips the oscillator. To minimize the noise spike, choose C as large as possible, remembering that dead time increases with C . It is CT CT recommended that C never be less than approximately 1000 pF. Often the noise which causes this problem is CT caused by the OUTPUT being pulled below ground at turnoff by external parasitics. This is particularly true when driving MOSFETs. A Schottky diode clamp from GROUND to OUTPUT prevents such output noise from feeding totheoscillator. VREF R RT RT/CT C CT GROUND Copyright © 2016, Texas Instruments Incorporated 1.72 f = OSC R × C ForR >5kΩ: RT CT RT Figure18. OscillatorSectionSchematic 8.3.7 Synchronization The simplest method to force synchronization uses the timing capacitor, C , in near standard configuration. CT Rather than bring C to ground directly, a small resistor is placed in series with C to ground. This resistor CT CT serves as the input for the sync pulse which raises the C voltage above the oscillator’s internal upper CT threshold. The PWM is allowed to run at the frequency set by R and C until the sync pulse appears. This RT CT scheme offers several advantages including having the local ramp available for slope compensation. The UC3842/3/4/5 oscillator must be set to a lower frequency than the sync pulse stream, typically 20% with a 0.5-V pulseappliedacrosstheresistor. Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Feature Description (continued) VREF R RT RT/CT C CT SYNC 24 O GROUND Figure19. SynchronizingtheOscillator 8.3.8 ShutdownTechnique The PWM controller (see Figure 20) can be shut down by two methods: either raise the voltage at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (see Figure 20). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling VCCbelowthelowerUVLOthreshold.Atthispoint,thereferenceturnsoff,allowingtheSCRtoreset. 1 kO VREF COMP SHUTDOWN 30 O ISENSE 500 O SHUTDOWN To Current Sense Resistor Figure20. ShutdownTechniques 8.3.9 SlopeCompensation A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 21). Note that capacitor C forms a CSF filterwithR tosuppresstheleading-edgeswitchspikes. CSF 18 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 Feature Description (continued) UCx842 UCx843 VREF 0.1 µF R RT RT/CT C CT R RAMP I R SENSE CSF ISENSE R C CS CSF Copyright © 2016, Texas Instruments Incorporated Figure21. SlopeCompensation 8.3.10 SoftStart Upon power up, it is desirable to gradually widen the PWM pulse width starting at zero duty cycle. The UCx84x devices do not have internal soft-start control, but this can be easily implemented externally with three components. An R/C network is used to provide the time constant to control the error amplifier output. A transistor is also used to isolate the components from the normal operation of either node. It also minimizes the loadingeffectsontheRT/CTtimeconstantbyamplificationthroughthetransistorsgain. VREF R SS COMP C SS Figure22. Soft-StartCircuitry Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Feature Description (continued) 8.3.11 VoltageMode Indutycyclecontrol(voltagemode),pulse width modulation is attained by comparing the error amplifier output to an artificial ramp. The oscillator timing capacitor C is used to generate a sawtooth waveform on both current or CT voltage mode ICs. To use the UCx84x in a voltage mode configuration, this sawtooth waveform will be input to the current sense input, ISENSE, for comparison to the error voltage at the PWM comparator. This sawtooth is used to determine pulse width instead of the actual primary current in this method. Loop compensation is similar tothatofvoltagemodecontrollerswithsubtledifferencesdue to the low output resistance voltage amplifier in the UCx84x as opposed to a transconductance (current) type amplifier used in traditional voltage mode controllers. Forfurtherreferenceontopologiesandcompensation,consultClosingtheFeedbackLoop(SLUP068). VREF 1N4148 2N2907 RT/CT 2N2222 2.7 k(cid:13)(cid:3) ISENSE 1 k(cid:13)(cid:3) C CT Figure23. CurrentModePWMUsedasaVoltageModePWM 8.4 Device Functional Modes 8.4.1 NormalOperation During normal operating mode, the IC can be used in peak current mode or voltage mode control. When the converter is operating in peak current mode, the controller regulates the converter's peak current and duty cycle. When the IC is used in voltage mode control, the controller regulates the power converter's duty cycle. The regulation of the system's peak current and duty cycle can be achieved with the use of the integrated error amplifierandexternalfeedbackcircuitry. 8.4.2 UVLOMode During the system start-up, VCC voltage starts to rise from 0 V. Before the VCC voltage reaches its corresponding turn on threshold, the IC is operating in UVLO mode. In this mode, the VREF pin voltage is not generated. When VCC is above 1 V and below the turnon threshold, the VREF pin is actively pulled low through a5-kΩresistor.Thisway,VREFcanbeusedasalogicsignaltoindicateUVLOmode.Ifthe bias voltage to VCC drops below the UVLO-off threshold, PWM switching stops and VREF returns to 0 V. The device can be restartedbyapplyingavoltagegreaterthantheUVLO-onthresholdtotheVCCpin. 20 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The UCx84x controllers are peak current mode pulse width modulators. These controllers have an onboard amplifierandcanbeusedinisolatedandnon-isolatedpowersupplydesign.Thereisanonboard totem pole gate driver capable of delivering 1 A of peak current. This is a high-speed PWM capable of operating at switching frequenciesupto500kHz. 9.1.1 Open-LoopTestFixture The following application is an open-loop laboratory test fixture. This circuit demonstrates the setup and use of theUCx84xdevicesandtheirinternalcircuitry. In the open-loop laboratory test fixture (see Figure 24), high peak currents associated with loads necessitate carefulgroundingtechniques.TimingandbypasscapacitorsshouldbeconnectedclosetotheGROUND terminal in a single-point ground. The transistor and 5-kΩ potentiometer sample the oscillator waveform and apply an adjustableramptotheISENSEterminal. VREF R1 4.7 N(cid:159) UCx842 100 N(cid:159)(cid:3) 1 COMP VREF 8 VCC 1 N(cid:159) 2 VFB VCC 7 E/A 1 N(cid:159)(cid:3) 5 N(cid:159) Adjust 0.1 PF 3 ISENSE OUTPUT 6 OUTPUT I SENSE 0.1 PF Adjust 4.7 N(cid:159) 4 RT/CT GROUND 5 C GROUND RTCT Copyright © 2016, Texas Instruments Incorporated Figure24. Open-LoopLaboratoryTestFixture 9.2 Typical Application A typical application for the UC2842 in an off-line flyback converter is shown in Figure 25. The UC2842 uses an inner current control loop that contains a small current sense resistor which senses the primary inductor current ramp. This current sense resistor transforms the inductor current waveform to a voltage signal that is input directly into the primary side PWM comparator. This inner loop determines the response to input voltage changes. An outer voltage control loop involves comparing a portion of the output voltage to a reference voltage Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Typical Application (continued) at the input of an error amplifier. When used in an off-line isolated application, the voltage feedback of the isolated output is accomplished using a secondary-side error amplifier and adjustable voltage reference, such as the TL431. The error signal crosses the primary to secondary isolation boundary using an opto-isolator whose collector is connected to the VREF pin and the emitter is connected to VFB. The outer voltage control loop determinestheresponsetoloadchanges. DCLAMP VtIoN 2=6 855 V VAACC ~ 1C0S NnUFB 5R0S NkU(cid:13)B(cid:3) DOUT – DBRIDGE + CSS ~ C18IN0 µF R10S0TA kR(cid:13)T(cid:3) DBIAS 2R2V C(cid:13)C(cid:3) NP NS 22C0O0 U TµF V142 OA UVT, NA RSS CVCC LP =1.5 mH 120 µF NP:NS = 10 NP:NA = 10 UC2842 RCOMPp CCOMPp 1 COMP VREF 8 10 k(cid:13)(cid:3) 10 nF 2 VFB VCC 7 RG RRT 3 ISENSE OUTPUT 6 10 (cid:13)(cid:3) 15.4 k(cid:13)(cid:3) QSW 4 RT/CT GROUND 5 CVCCbp CVREF RBLEEDER RCS CCT 0.1 µF 1 µF 10 k(cid:13)(cid:3) 0.75 (cid:13)(cid:3) RLED RTLbias C10R AnMFP 1000 pF 4R.2C SkF(cid:13)(cid:3) 1.3 k(cid:13)(cid:3) 1 k(cid:13)(cid:3) RRAMP 24.9 k(cid:13)(cid:3) OPTO- 10 V C10C0SF pF Not PoRpPulated RFBG COUPLER R9.F5B3U k(cid:13)(cid:3) 4.99 k(cid:13)(cid:3) RCOMPz CCOMPz 88.7 k(cid:13)(cid:3) 0.01 µF ROPTO 1 k(cid:13)(cid:3) TL431 RFBB 2.49 k(cid:13)(cid:3) Copyright © 2016, Texas Instruments Incorporated Figure25. TypicalApplicationDesignExampleSchematic 9.2.1 DesignRequirements Table 1 illustrates a typical set of performance requirements for an off-line flyback converter capable of providing 48 W at 12-V output voltage from a universal AC input. The design uses peak primary current control in a continuouscurrentmodePWMconverter. Table1.PerformanceRequirements PARAMETER TESTCONDITIONS MIN NOM MAX UNIT V InputVoltage 85 115/230 265 V IN RMS f LineFrequency 47 50/60 63 Hz LINE V OutputVoltage I ≤I ≤I 11.75 12 12.25 V OUT OUT(min) OUT OUT(max) OutputRipple V I ≤I ≤I 100 mVpp RIPPLE Voltage OUT(min) OUT OUT(max) I OutputCurrent 0 4 A OUT Switching f 100 kHz SW Frequency η Efficiency 85% 22 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 9.2.2 DetailedDesignProcedure This procedure outlines the steps to design an off-line universal input continuous current mode (CCM) flyback converterusingtheUC2842.SeeFigure25forcomponentnamesreferredtointhedesignprocedure. 9.2.2.1 InputBulkCapacitorandMinimumBulkVoltage Bulk capacitance may consist of one or more capacitors connected in parallel, often with some inductance between them to suppress differential-mode conducted noise. The value of the input capacitor sets the minimum bulk voltage; setting the bulk voltage lower by using minimal input capacitance results in higher peak primary currents leading to more stress on the MOSFET switch, the transformer, and the output capacitors. Setting the bulk voltage higher by using a larger input capacitor results in higher peak current from the input source and the capacitor itself will be physically larger. Compromising between size and component stresses determines the acceptableminimuminputvoltage.Thetotalrequiredvaluefortheprimary-sidebulkcapacitance,C ,is selected IN based upon the power level of the converter, P , the efficiency target, η, the minimum input voltage, V , OUT IN(min) andischosentomaintainanacceptableminimumbulkvoltagelevel,V ,usingEquation9. BULK(min) 1 VBULK(min) 2×P × 0.25+ ×arcsin IN F N F(cid:190)2×V GG C = IN(min) IN k2×V2 FV2 o×f IN(min) BULK(min) LINE(min) (9) In this equation, V is the RMS value of the minimum AC input voltage, 85 VRMS, whose minimum line IN(min) frequency is denoted as f , equal to 47 Hz. Based on the C equation, to achieve a minimum bulk voltage LINE(min) IN of75V,assuming85%converterefficiency,thebulkcapacitorshouldbe larger than 126 µF; 180 µF was chosen forthedesign,takingintoconsiderationcomponenttolerancesandefficiencyestimation. 9.2.2.2 TransformerTurnsRatioandMaximumDutyCycle Thetransformerdesignstartswithselectingasuitableswitchingfrequencyforthe given application. The UC2842 is capable of switching up to 500 kHz but considerations such as overall converter size, switching losses, core loss, system compatibility, and interference with communication frequency bands generally determine an optimumfrequencythat should be used. For this off-line converter, the switching frequency, f , is selected to be SW 110 kHz as a compromise to minimize the transformer size and the EMI filter size, and still have acceptable losses. The transformer primary to secondary turns ratio, N , can be selected based on the desired MOSFET voltage PS rating and the secondary diode voltage rating. Because the maximum input voltage is 265 VRMS, the peak bulk inputvoltagecanbecalculatedasshowninEquation10. V = (cid:190)2×V N 375 V BULK(max) IN(max) (10) To minimize the cost of the system, a readily available 650-V MOSFET is selected. Derating the maximum voltage stress on the drain to 80% of its rated value and allowing for a leakage inductance voltage spike of up to 30% of the maximum bulk input voltage, the reflected output voltage should be less than 130 V as shown in Equation11. (cid:11) (cid:12) V 0.8u V (cid:16)1.3uV 130.2V REFLECTED DS(rated) BULK(max) (11) Themaximumprimarytosecondarytransformerturnsratio,N ,fora12Voutputcanbeselectedas PS V REFLECTED N = = 10.85 PS V OUT (12) AturnsratioofN =10isusedinthedesignexample. PS The auxiliary winding is used to supply bias voltage to the UC2842. Maintaining the bias voltage above the VCC minimum operating voltage after turn on is required for stabile operation. The minimum VCC operating voltage for the UC2842 version of the controller is 10 V. The auxiliary winding is selected to support a 12-V bias voltage so that it is above the minimum operating level but still keeps the losses low in the IC. The primary to auxiliary turnsratio,N ,canbecalculatedfromEquation13: PA V OUT N = N × = 10 PA PS V BIAS (13) Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Theoutputdiodeexperiencesavoltagestressthatisequaltotheoutputvoltageplusthereflectedinputvoltage: V V = BULK:max; +V = 49.5 V DIODE N OUT PS (14) To allow for voltage spikes due to ringing, a Schottky diode with a rated blocking voltage of greater than 60 V is recommendedforthisdesign.Theforwardvoltagedrop,V ,ofthisdiodeisestimatedtobeequalto0.6V F To avoid high peak currents, the flyback converter in this design operates in continuous conduction mode. Once N has been determined, the maximum duty cycle, D , can be calculated using the transfer function for a PS MAX CCMflybackconverter: V +V 1 D OUT F = × MAX V lN p l1 D p BULK:min; PS F MAX (15) N u(cid:11)V (cid:14)V (cid:12) D PS OUT F 0.627 MAX V (cid:14)N u(cid:11)V (cid:14)V (cid:12) BULK(min) PS OUT F (16) Because the maximum duty cycle exceeds 50%, and the design is an off-line (AC-input) application, the UC2842 isbestsuitedforthisapplication. 9.2.2.3 TransformerInductanceandPeakCurrents For this design example, the transformer magnetizing inductance is selected based upon the CCM condition. An inductance value that allows the converter to stay in CCM over a wider operating range before transitioning into discontinuous current mode is used to minimize losses due to otherwise high currents and also to decrease the output ripple. The design of the transformer in this example sizes the inductance so the converter enters CCM operationatapproximately10%loadandminimumbulkvoltagetominimizeoutputripple. Theinductor,L foraCCMflybackcanbecalculatedusingEquation17. P V 2 × NPS ×VOUT 2 1 k BULK:min;o lV +N ×V p L = × BULK:min; PS OUT P 2 0.1×P ×f IN SW (17) In Equation 17, the input power, P , is estimated by dividing the maximum output power, P , by the target IN OUT efficiency, η, and f is the switching frequency; for the UC2842 the switching frequency is equal to the oscillator SW frequency and is set to 110 kHz. Therefore, the transformer inductance should be approximately 1.8 mH; a 1.5- mHinductanceischosenasthemagnetizinginductancevalueforthisdesign. Based on calculated inductor value and the switching frequency, the current stress of the MOSFET and output diodecanbecalculated. Thepeakcurrentintheprimary-sideMOSFETofaCCMflybackcanbecalculatedasshowninEquation18. N ×V PS OUT P V V +:N ×V ; I = IN + BULK(min)× BULK:min; PS OUT PKMOSFET N ×V 2×L f V × PS OUT m SW BULK:min; V +:N ×V ; n r BULK:min; PS OUT (18) The MOSFET peak current is 1.36 A. The RMS current of the MOSFET is calculated to be 0.97 A as shown in Equation19.Therefore,IRFB9N65Aisselectedtobeusedastheprimary-sideswitch. D 3 V 2 D 2 ×I ×V I = MAX × BULK(min) MAX PKMOSFET BULK(min) + D ×I 2 RMSMOSFET ¤ 3 l LP ×fSW p FF LP ×fSW G k MAX PKMOSFET o (19) TheoutputdiodepeakcurrentisequaltotheMOSFETpeakcurrentreflectedtothesecondaryside. I = N ×I = 13.634 A PKDIODE PS PKMOSFET (20) The diode average current is equal to the total output current, 4 A; combined with a required 60-V rating and 13.6-Apeakcurrentrequirement,a48CTQ060-1isselectedfortheoutputdiode. 24 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 9.2.2.4 OutputCapacitor The total output capacitance is selected based upon the output voltage ripple requirement. In this design, 0.1% voltage ripple is assumed. Based on the 0.1% ripple requirement, the capacitor value can be selected using Equation21. N ×V I × PS OUT OUT V +N ×V C R BULK:min; PS OUT = 1865 JF OUT 0.001×V ×f OUT SW (21) Todesignfordevicetolerances,a2200-µFcapacitorwasselected. 9.2.2.5 CurrentSensingNetwork The current sensing network consists of the primary-side current sensing resistor, R , filtering components R CS CSF and C , and optional R . Typically, the direct current sense signal contains a large amplitude leading edge CSF P spike associated with the turnon of the main power MOSFET, reverse recovery of the output rectifier, and other factors including charging and discharging of parasitic capacitances. Therefore, C and R form a low-pass CSF CSF filterthatprovidesimmunitytosuppresstheleadingedgespike.Forthisconverter,C ischosentobe100pF. CSF Without R , R sets the maximum peak current in the transformer primary based on the maximum amplitude of P CS the ISENSE pin, which is specified to be 1 V. To achieve 1.36-A primary side peak current, a 0.75-Ω resistor is chosenforR . CS The high current sense threshold of ISENSE helps to provide better noise immunity to the system but also results in higher losses in the current sense resistor. These current sense losses can be minimized by injecting an offset voltage into the current sense signal using R . R and R form a resistor divider network from the P P CSF current sense signal to the device’s reference voltage, VREF, which adds an offset to the current sense voltage. This technique still achieves current mode control with cycle-by-cycle over-current protection. To calculate requiredoffsetvalue(V ),useEquation22. OFFSET R V = CSF ×V OFFSET R +R REF CSF P (22) OnceR isadded,adjustthecurrentsenseresistor,R ,accordingly. P CS 9.2.2.6 GateDriveResistor R is the gate driver resistor for the power switch, Q . The selection of this resistor value must be done in G SW conjunction with EMI compliance testing and efficiency testing. Using a larger resistor value for R slows down G the turnon and turnoff of the MOSFET. A slower switching speed reduces EMI but also increases the switching loss.Atrade-offbetweenswitchinglossandEMIperformancemustbecarefullyperformed.Forthisdesign,a10- Ωresistorwaschosenforthegatedriveresistor. 9.2.2.7 VREFCapacitor A precision 5-V reference voltage performs several important functions. The reference voltage is divided down internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate output voltage regulation. Other duties of the reference voltage are to set internal bias currents and thresholds for functions such as the oscillator upper and lower thresholds. Therefore, the reference voltage must be bypassed with a ceramic capacitor (C ), a 1-µF, 16-V ceramic capacitor was selected for this converter. Placement of this capacitor on VREF thephysicalprinted-circuitboardlayoutmustbeascloseaspossibletotherespectiveVREFandGROUNDpins. 9.2.2.8 RT/CT The internal oscillator uses a timing capacitor (C ) and a timing resistor (R ) to program the oscillator CT RT frequency and maximum duty cycle. The operating frequency can be programmed based the curves in Application Curves, where the timing resistor can be found once the timing capacitor is selected. It is best for the timing capacitor to have a flat temperature coefficient, typical of most COG or NPO type capacitors. For this converter,15.4kΩand1000pFwereselectedforR andC tooperateat110-kHzswitching. RT CT Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com 9.2.2.9 Start-UpCircuit At start-up, the IC gets its power directly from the high-voltage bulk, through a high-voltage resistor R . The START selection of the start-up resistor is the trade-off between power loss and start-up time. The current flowing throughR attheminimuminput voltage must be higher than the VCC current under UVLO conditions (1 mA START at its maximum value). A resistance of 100-kΩ was chosen for R , providing 1 mA of start-up current at low- START line conditions. The start-up resistor is physically comprised of two 50-kΩ resistors in series to meet the high voltagerequirementsandpowerratingathigh-line. AfterVCCischargedupabovetheUVLO-onthreshold,theUC2842startstoconsumefulloperatingcurrent.The VCC capacitor is required to provide enough energy to prevent its voltage from dropping below the UVLO-off threshold during start-up, before the output is able to reach its regulated level. A large bulk capacitance would hold more energy but would result in slower start-up time. In this design, a 120-µF capacitor is chosen to provide enoughenergyandmaintainastart-uptimeofapproximately2seconds. 9.2.2.10 VoltageFeedbackCompensation Feedback compensation, also called closed-loop control, can reduce or eliminate steady state error, reduce the sensitivity of the system to parametric changes, change the gain or phase of a system over some desired frequency range, reduce the effects of small signal load disturbances and noise on system performance, and create a stable system from an unstable system. A system is stable if its response to a perturbation is that the perturbation eventually dies out. A peak current mode flyback uses an outer voltage feedback loop to stabilize the converter. To adequately compensate the voltage loop, the open-loop parameters of the power stage must bedetermined. 9.2.2.10.1 PowerStagePolesandZeroes The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance, L , is greater than the P inductance for DCM/CCM boundary mode operation, called the critical inductance, or L , then the converter Pcrit operatesinCCM: L > L ,then CCM P Pcrit (23) R ×:N ;2 V 2 L = OUT PS × IN Pcrit 2×f lV +V ×N p SW IN OUT PS (24) For the entire input voltage range, the selected inductor has value larger than the critical inductor. Therefore, the converteroperatesinCCMandthecompensationlooprequiresdesignbasedonCCMflybackequations. The current-to-voltage conversion is done externally with the ground-referenced current sense resistor, R , and CS the internal resistor divider of 2R/R which sets up the internal current sense gain, A = 3. Note that the exact CS value of these internal resistors is not critical but the IC provides tight control of the resistor divider ratio, so regardlessoftheactualresistorvaluevariationstheirrelativevaluetoeachotherismaintained. The DC open-loop gain, G , of the fixed-frequency voltage control loop of a peak current mode control CCM O flyback converter shown in Equation 25 is approximated by first using the output load, R , the primary to OUT secondaryturnsratio,N ,themaximumdutycycle,D,calculatedinEquation25. PS R ×N 1 G = OUT PS × O R ×A :1FD;2 CS CS +:2×M;+1 R L (25) In Equation 25, D is calculated with Equation 26, τ is calculated with Equation 27, and M is calculated with L Equation28. N ×V D = PS OUT V +:N ×V ; BULKmin PS OUT (26) 2×L ×f P SW R = L R ×:N ;2 OUT PS (27) V ×N OUT PS M = V BULKmin (28) 26 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 For this design, a converter with an output voltage V of 12 V, and 48 W relates to an output load, R , equal OUT OUT to3 Ωatfullload.Witha maximum duty cycle calculated to be 0.627, a current sense resistance, R , of 0.75 Ω, CS andaprimarytosecondaryturns-ratio,N ,of10,theopen-loopgaincalculatesto3.082,or9.776dB. PS A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half planezero,ω ,tothepowerstage,andthefrequencyofthiszero,f ,arecalculatedwithEquation30. ESRz ESRz 1 X = ESRz R ×C ESR OUT (29) 1 f = ESRz 2×N×R ×C ESR OUT (30) Thef zeroforanoutputcapacitanceof2200µFandatotalESRof43mΩislocatedat1.682kHz. ESRz CCM flyback converters have a zero in the right-half plane, RHP, in their transfer function. A RHP zero has the same 20 dB/decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds a 90° phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location, f , of the RHP zero, ω , is a function of the output load, the duty cycle, the primary inductance, L , and the RHPz RHPz P primarytosecondarysideturnsratio,N . PS R ×:1FD;2 ×:N ;2 X = OUT PS RHPz L ×D P (31) R ×:1FD;2 ×:N ;2 OUT PS f = RHPz 2×N×L ×D P (32) The right-half plane zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest right-half plane zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DCinput,theRHPzerofrequency,f ,isequalto7.07kHzatmaximumdutycycle,fullload. RHPz The power stage has one dominate pole, ω , which is in the region of interest, located at a lower frequency, f , P1 P1 which is related to the duty cycle, D, the output load, and the output capacitance, calculated with Equation 34. There is also a double pole placed at half the switching frequency of the converter, f calculated with P2 Equation36.Forthisexample,polef islocatedat40.37Hzandf isat55kHz. P1 P2 :1FD;3 +1+D R X = L P1 R ×C OUT OUT (33) :1FD;3 +1+D R f = L P1 2×N×R ×C OUT OUT (34) X = N×f P2 SW (35) f SW f = P2 2 (36) 9.2.2.10.2 SlopeCompensation Slope compensation is the large signal sub-harmonic instability that can occur with duty cycles that may extend beyond 50% where the rising primary side inductor current slope may not match the falling secondary side current slope. The sub-harmonic oscillation would result in an increase in the output voltage ripple and may even limitthepowerhandlingcapabilityoftheconverter. The target of slope compensation is to achieve an ideal quality coefficient, Q , to be equal to 1 at half of the P switchingfrequency.TheQ iscalculatedwithEquation37. P 1 Q = P N×>M ×:1FD;F0.5? C (37) In Equation 37, D is the primary side switch duty cycle and M is the slope compensation factor, which is defined C withEquation38. Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com S e M = +1 C S n (38) In Equation 38, S is the compensation ramp slope and the S is the inductor rising slope. The optimal goal of e n the slope compensation is to achieve Q equal to 1; upon rearranging Equation 38 the ideal value of slope P compensationfactorisdetermined: 1 +0.5 N M = ideal 1FD (39) For this design to have adequate slope compensation, M must be 2.193 when D reaches it maximum value of C 0.627. Theinductorrisingslope,S ,attheISENSEpiniscalculatedwithEquation40. n V ×R V INmin CS S = = 0.038 n L Js P (40) Thecompensationslope,S ,iscalculatedwithEquation41. e mV S = :M F1;×S = 44.74 e C n Js (41) The compensation slope is added into the system through R and R . The C is an AC-coupling RAMP CSF RAMP capacitor that allows the voltage ramp of the oscillator to be used without adding an offset to the current sense; select a value to approximate high frequency short circuit, such as 10 nF as a starting point and make adjustments if required. The R and R resistors form a voltage divider from the oscillator charge slope and RAMP CSF this proportional ramp is injected into the ISENSE pin to add slope compensation. Choose the value of R to RAMP bemuch larger than the R resistor so that it does not load down the internal oscillator and result in a frequency RT shift. The oscillator charge slope is calculated using the peak-to-peak voltage of the RT/CT sawtooth waveform, V ,equalto1.7V,andtheminimumon-time,asshowninEquation43. OSCpp D t = ONmin f SW (42) V 1.7 V mV S = OSCpp = = 298 OSC t 5.7 Js Js ONmin (43) To achieve a 44.74-mV/µs compensation slope, R resistor is calculated with Equation 44. In this design, CSF R isselectedas24.9kΩ,a4.2-kΩ resistorwasselectedforR . RAMP CSF R RAMP R = CSF S OSC F1 S e (44) 9.2.2.10.3 Open-LoopGain Once the power stage poles and zeros are calculated and the slope compensation is determined, the power stage open-loop gain and phase of the CCM flyback converter can be plotted as a function of frequency. The powerstagetransferfunctioncanbecharacterizedwithEquation45. s:f; s:f; 1+ × 1 l X p l FX p 1 H :s; = G × ESRz RHPz × OPEN 0 s:f; s:f; s:f;2 1+ 1+ + X X ×Q :X ;2 P1 P2 P P2 (45) Thebodefortheopen-loopgainandphasecanbeplottedbyusingEquation46. Gain :s; = 20×log:(cid:1)H :s;(cid:1); OPEN OPEN (46) (seeFigure26andFigure27). 28 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 10 0 5 -45 0 Gain (dB) -1-50 qPhase () -90 -15 -135 -20 -25 -180 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 frequency (Hz) frequency (Hz) D001 D002 Figure26.ConverterOpen-LoopBodePlot-Gain Figure27.ConverterOpen-LoopBodePlot-Phase 9.2.2.10.4 CompensationLoop The design of the compensation loop involves selecting the appropriate components so that the required gain, poles, and zeros can be designed to result in a stabile system over the entire operating range. There are three distinct portions of the loop: the TL431, the opto-coupler, and the error amplifier. Each of these stages is combinedwiththepowerstagetoresultinastablerobustsystem. For good transient response, the bandwidth of the finalized design should be as large as possible. The bandwidth of a CCM flyback, f , is limited to ¼ of the RHP zero frequency, or approximately 1.77 kHz using BW Equation47. f RHPz f = BW 4 (47) The gain of the open-loop power stage at f can be calculated using Equation 46 or can be observed on the BW Bodeplot(Figure26)andisequalto–19.55dBandthephaseatf isequalto–58°. BW The secondary side portion of the compensation loop begins with establishing the regulated steady state output voltage.Tosettheregulatedoutputvoltage, a TL431 adjustable precision shunt regulator is ideally suited for use on the secondary side of isolated converters due to its accurate voltage reference and internal op amp. The resistors used in the divider from the output terminals of the converter to the TL431 REF pin are selected based upon the desired power consumption. Because the REF input current for the TL431 is only 2 µA, selecting the resistors for a divider current, I , of 1 mA results in minimal error. The top divider resistor, R , is FB_REF FBU calculatedusingEquation48: V FREF R = OUT TL431 FBU I FB_REF (48) The TL431 reference voltage, REF , has a typical value of 2.495 V. A 9.53-kΩ resistor is chosen for R . To TL431 FBU settheoutputvoltageto12V,2.49kΩisusedforR . FBB REF TL431 R = ×R FBB V FREF FBU OUT TL431 (49) For good phase margin, a compensator zero, f , is needed and should be placed at 1/10th the desired COMPz bandwidth: f BW f = COMPz 10 (50) X = 2×N×f COMPz COMPz (51) With this converter, f should be set at approximately 177 Hz. A series resistor, R , and capacitor, COMPz COMPz C ,placedacrosstheTL431 cathode to REF sets the compensator zero location. Setting C to 0.01 µF, COMPz COMPz R iscalculatedusingEquation52: COMPz Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com 1 R = COMPz X ×C COMPz COMPz (52) Usingastandardvalueof88.7kΩforR anda0.01 µFforC resultsinazeroplacedat179Hz. Z Z Referring to Figure 25, R provides cathode current to the TL431 from the regulated voltage provided from TLbias the Zener diode, D . For robust performance, 10 mA is provided to bias the TL431 by way of the 10-V Zener REG and1-kΩ resistorisusedforR . TLbias ThegainoftheTL431portionofthecompensationloopcanbewrittenas: 1 1 G :s; = R + × TL431 l COMPz s(f)×C p R ZCOMPz FBU (53) A compensation pole is needed at the frequency of right half plane zero or the ESR zero, whichever is lowest. Based previous the analysis, the right half plane zero, f , is located at 7.07 kHz and the ESR zero, f , is at RHPz ESRz 1.68 kHz; therefore, for this design, the compensation pole must be put at 1.68 kHz. The opto-coupler contains a parasitic pole that is difficult to characterize over frequency so the opto-coupler is set up with a pulldown resistor, R equalto1kΩ,whichmovesthe parasitic opto-coupler pole further out and beyond the range of interest for OPTO thisdesign. The required compensation pole can be added to the primary side error amplifier using R and C . COMPp COMPp ChoosingR as10kΩ,therequiredvalueofC isdeterminedusingEquation54. COMPp COMPp 1 C = = 9.46 nF COMPp 2×N×f ×R ESRz COMPp (54) A10-nFcapacitorisusedforC settingthecompensationpoleat1.59kHz. COMPp Adding a DC gain to the primary side error amplifier may be required to obtain the required bandwidth and helps to adjust the loop gain as needed. Using a 4.99 kΩ for R sets the DC gain on the error amplifier to 2. At this FBG point the gain transfer function of the error amplifier stage, G (s), of the compensation loop can be EA characterized: R 1 G s = COMPp × EA: ; l R p F1+s f ×C ×R G FBG : ; COMPp COMPp (55) Using an opto-coupler whose current transfer ratio (CTR) is typically at 100% in the frequency range of interest sothatCTR=1,thetransferfunctionoftheopto-couplerstage,G (s),isequalto: OPTO CTR×R G (s) = OPTO OPTO R LED (56) The bias resistor, R , to the internal diode of the opto-coupler, and the pulldown resistor on the opto emitter, LED R ,setsthegainacrosstheisolationboundary.R hasalreadybeensetto1kΩ but the value of R has OPTO OPTO LED notyetbeendetermined. The total closed-loop gain, G (s), is the combination of the open-loop power stage, H (s), the opto gain, TOTAL o G (s),theerroramplifiergain,G (s),andthegainoftheTL431stage,G (s): OPTO EA TL431 G :s; = (cid:1)H :s;(cid:1)×(cid:1)G :s;(cid:1)×(cid:1)G :s;(cid:1)×(cid:1)G :s;(cid:1) TOTAL OPEN OPTO EA TL431 (57) The required value for R can be selected to achieve the desired crossover frequency, f . By setting the total LED BW loop gain equal to 1 at the desired crossover frequency and rearranging Equation 57, the optimal value for R LED canbedetermined,asshowninEquation58. R Q (cid:1)H :s;(cid:1)×(cid:1)CTR×C (cid:1)×(cid:1)G :s;(cid:1)×(cid:1)G :s;(cid:1) LED OPEN OPTO EA TL431 (58) A1.3-kΩresistorsuitstherequirementforR . LED Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation59. 30 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 CTR×R R 1 OPTO COMPp G s = H s × × × CLOSED : ; OPEN: ; R R F1+ s×C ×R G LED FBG COMPp COMPp l p l p 1 k o R + × COMPz @s×CCOMPz A R FBU n r (59) The final closed-loop bode plots are show in Figure 28 and Figure 29. The converter achieves a crossover frequencyofapproximately1.8kHzandhasaphasemarginofapproximately67o. TI recommends checking the loop stability across all the corner cases including component tolerances to ensure systemstability. 80 0 60 -45 40 ain (dB) 20 qgrees () -90 G e D 0 -135 -20 -40 -180 1 10 100 1000 10000 100000 1 10 100 1000 10000 100000 frequency (Hz) frequency (Hz) D003 DD000014 Figure28.ConverterClosed-LoopBodePlot–Gain Figure29.ConverterClosed-LoopBodePlot–Phase 9.2.3 ApplicationCurves Figure30.PrimarySideMOSFETDraintoSourceVoltage Figure31.PrimarySideMOSFETDraintoSourceVoltage at240-VACInput(100V/div) at120-VACInput(100V/div) Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com Figure32.OutputVoltageDuring0.9-Ato2.7-ALoad Figure33.OutputVoltageRippleatFullLoad(100mV/div) Transient(CH1:OutputVoltageACCoupled,200mV/div; CH4:OutputCurrent,1A/div) Figure34.OutputVoltageBehavioratFullLoadStart-Up(5V/div) 10 Power Supply Recommendations It is important to bypass the ICs supply (VCC) and reference voltage (VREF) pins with a 0.1-µF to 1-µF ceramic capacitortoground.Thecapacitors must be placed as close to the actual pin connections as possible for optimal noise filtering. A second, larger filter capacitor may also be required in offline applications to hold the supply voltage(VCC)abovetheUVLOturnoffthresholdduringstart-up. To prevent false triggering due to leading edge noises, an RC current sense filter may be required on ISENSE. KeepthetimeconstantoftheRCfilterwellbelowtheminimumon-timepulsewidth. Schottky diodes may be necessary on the OUTPUT pin to prevent overshoot and undershoot due to the high impedance to the supply rail and to ground, respectively. A bleeder resistor, placed between the gate and the source of the MOSFET should be used to prevent activating the power switch with extraneous leakage currents duringundervoltagelockout. To prevent noise problems with high-speed switching transients, bypass VREF to ground with a ceramic capacitor close to the IC package. A minimum of 0.1-µF ceramic capacitor is required. Additional VREF bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition totheceramiccapacitor. 32 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 11 Layout 11.1 Layout Guidelines 11.1.1 FeedbackTraces Try to run the feedback trace as far from the inductor and noisy power traces as possible. Be as direct as possible with the feedback trace and somewhat thick. These two sometimes involve a trade-off, but keeping it away from EMI and other noise sources is the more critical of the two. If possible, run the feedback trace on the sideofthePCBoppositeoftheinductorwithagroundplaneseparatingthetwo. 11.1.2 BypassCapacitors When using a low value ceramic bypass capacitor, it should be located as close to the VCC pin of the device as possible.Thiseliminatesasmuchtraceinductanceeffectsaspossibleandgivestheinternaldevicerailacleaner voltage supply. Using surface mount capacitors also reduces lead length and lessens the chance of noise couplingintotheeffectiveantennacreatedbythrough-holecomponents. 11.1.3 CompensationComponents For best stability, external compensation components should be placed close to the IC. Keep VFB lead length as short as possible and VFB stray capacitance as small as possible. Surface mount components are recommended here as well for the same reasons discussed for the filter capacitors. These should not be located veryclosetotraceswithhighswitchingnoise. 11.1.4 TracesandGroundPlanes Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere. The inductor, output capacitors, and output diode should be as close to each other possible. This helps reduce the EMI radiated by the power traces due to the high switching currents through them. This also reduces lead inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should be connected close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of the PCB. This reduces noise as well by reducing ground loop errors as well as by absorbing more of the EMI radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used to separate the power plane (where the power traces and components are) and the signal plane (where the feedback and compensation and components are) for improved performance. On multi-layer boards the use of vias is required to connect traces and different planes. It is good practice to use one standard via per 200 mA of currentifthetraceneedstoconductasignificantamountofcurrentfromoneplanetotheother. Arrange the components so that the switching current loops curl in the same direction. Due to the way switching regulators operate, there are two power states. One state when the switch is on and one when the switch is off. Duringeachstatethereisacurrentloopmadeby the power components that are currently conducting. Place the power components so that during each of the two states the current loop is conducting in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces radiated EMI. Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 SLUS223F–APRIL1997–REVISEDAPRIL2020 www.ti.com 11.2 Layout Example MOSFET Heatsink Track To TO-220FP Bottom View <= %XON(cid:3)&DS(cid:3)¯ RCS1 S G 6 ½ RCS2 P Track To R Transformer => I W FBead in D d in g RSNUB ½ P R Track To CSNUB I Win <= Bulk Cap + d in g 4 22AWG Jumper T Wire R RCSF A N CCSF S F O CCT R M > GROUND RT/CT CRAMP E = R = RG OUTPUT ISENSE RRAMP n UCx84x o CVCCbp VCC VFB 2 CVCC i t c VREF COMP A e U ir CVREF CCOMPp Aux Cap X W D in er RRT RCOMPp din g ld RP RFBG CVCC1 1 o S ROPTO e v 22AWG Jumper a Wires E K W OPTO-ISOLATOR C A PCB Bottom-side View Copyright © 2016, Texas Instruments Incorporated Figure35. UCx84xLayoutExample 34 SubmitDocumentationFeedback Copyright©1997–2020,TexasInstrumentsIncorporated ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

UC1842,UC2842,UC3842,UC1843,UC2843,UC3843 UC1844,UC2844,UC3844,UC1845,UC2845,UC3845 www.ti.com SLUS223F–APRIL1997–REVISEDAPRIL2020 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table2.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY UC1842 Clickhere Clickhere Clickhere Clickhere Clickhere UC2842 Clickhere Clickhere Clickhere Clickhere Clickhere UC3842 Clickhere Clickhere Clickhere Clickhere Clickhere UC1843 Clickhere Clickhere Clickhere Clickhere Clickhere UC2843 Clickhere Clickhere Clickhere Clickhere Clickhere UC3843 Clickhere Clickhere Clickhere Clickhere Clickhere UC1844 Clickhere Clickhere Clickhere Clickhere Clickhere UC2844 Clickhere Clickhere Clickhere Clickhere Clickhere UC3844 Clickhere Clickhere Clickhere Clickhere Clickhere UC1845 Clickhere Clickhere Clickhere Clickhere Clickhere UC2845 Clickhere Clickhere Clickhere Clickhere Clickhere UC3845 Clickhere Clickhere Clickhere Clickhere Clickhere 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Community Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight fromtheexperts.Searchexistinganswersoraskyourownquestiontogetthequickdesignhelpyouneed. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do notnecessarilyreflectTI'sviews;seeTI'sTermsofUse. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,seetheleft-handnavigation. Copyright©1997–2020,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:UC1842 UC2842 UC3842 UC1843 UC2843 UC3843UC1844 UC2844 UC3844 UC1845 UC2845 UC3845

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8670401PA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670401PA UC1842 5962-8670401VPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670401VPA UC1842 5962-8670401XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670401XA UC1842L/ 883B 5962-8670402PA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670402PA UC1843 5962-8670402XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670402XA UC1843L/ 883B 5962-8670403PA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670403PA UC1844 5962-8670403VXA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670403VXA UC1844L QMLV 5962-8670403XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670403XA UC1844L/ 883B 5962-8670404DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type 5962-8670404DA UC1845W/883B 5962-8670404PA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670404PA UC1845 5962-8670404VPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type 8670404VPA UC1845 5962-8670404VXA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670404VXA UC1845L QMLV 5962-8670404XA ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670404XA Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC1845L/ 883B UC1842J ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 UC1842J UC1842J883B ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670401PA UC1842 UC1842L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670401XA UC1842L/ 883B UC1842W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 UC1842W UC1843J ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 UC1843J UC1843J883B ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670402PA UC1843 UC1843L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1843L UC1843L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670402XA UC1843L/ 883B UC1844J ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 UC1844J UC1844J883B ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670403PA UC1844 UC1844L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670403XA UC1844L/ 883B UC1845J ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 UC1845J UC1845J883B ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 8670404PA UC1845 UC1845L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1845L UC1845L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 8670404XA UC1845L/ 883B Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC1845W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 UC1845W UC1845W883B ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type 5962-8670404DA UC1845W/883B UC2842D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842D & no Sb/Br) UC2842D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842 & no Sb/Br) D8 UC2842D8G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842 & no Sb/Br) D8 UC2842D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842 & no Sb/Br) D8 UC2842DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2842D & no Sb/Br) UC2842N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2842N & no Sb/Br) UC2842NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2842N & no Sb/Br) UC2843D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843D & no Sb/Br) UC2843D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843 & no Sb/Br) D8 UC2843D8G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843 & no Sb/Br) D8 UC2843D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843 & no Sb/Br) D8 UC2843D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843 & no Sb/Br) D8 UC2843DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843D & no Sb/Br) UC2843DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2843D & no Sb/Br) UC2843N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2843N & no Sb/Br) UC2843NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2843N & no Sb/Br) Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC2844D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844D & no Sb/Br) UC2844D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844 & no Sb/Br) D8 UC2844D8G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844 & no Sb/Br) D8 UC2844D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844 & no Sb/Br) D8 UC2844DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844D & no Sb/Br) UC2844DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2844D & no Sb/Br) UC2844N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2844N & no Sb/Br) UC2844NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2844N & no Sb/Br) UC2845D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D & no Sb/Br) UC2845D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845 & no Sb/Br) D8 UC2845D8G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845 & no Sb/Br) D8 UC2845D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845 & no Sb/Br) D8 UC2845D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845 & no Sb/Br) D8 UC2845DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D & no Sb/Br) UC2845DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D & no Sb/Br) UC2845DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 UC2845D & no Sb/Br) UC2845N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2845N & no Sb/Br) UC2845NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2845N & no Sb/Br) Addendum-Page 4

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC3842D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842D & no Sb/Br) UC3842D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842 & no Sb/Br) D8 UC3842D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842 & no Sb/Br) D8 UC3842DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3842D & no Sb/Br) UC3842N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3842N & no Sb/Br) UC3842NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3842N & no Sb/Br) UC3843D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843D & no Sb/Br) UC3843D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843 & no Sb/Br) D8 UC3843D8G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843 & no Sb/Br) D8 UC3843D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843 & no Sb/Br) D8 UC3843D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843 & no Sb/Br) D8 UC3843DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843D & no Sb/Br) UC3843DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3843D & no Sb/Br) UC3843N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3843N & no Sb/Br) UC3843NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3843N & no Sb/Br) UC3844D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844D & no Sb/Br) UC3844D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844 & no Sb/Br) D8 UC3844D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844 & no Sb/Br) D8 Addendum-Page 5

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC3844D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844 & no Sb/Br) D8 UC3844DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844D & no Sb/Br) UC3844DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3844D & no Sb/Br) UC3844N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3844N & no Sb/Br) UC3844NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3844N & no Sb/Br) UC3845AJ ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type 0 to 70 UC3845AJ UC3845D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D & no Sb/Br) UC3845D8 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845 & no Sb/Br) D8 UC3845D8G4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845 & no Sb/Br) D8 UC3845D8TR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845 & no Sb/Br) D8 UC3845D8TRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845 & no Sb/Br) D8 UC3845DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D & no Sb/Br) UC3845DTR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D & no Sb/Br) UC3845DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UC3845D & no Sb/Br) UC3845N ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3845N & no Sb/Br) UC3845NG4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3845N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 6

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1842, UC1842-SP, UC1843, UC1844, UC1844-SP, UC1845, UC1845-SP, UC3842, UC3843, UC3844, UC3845, UC3845AM : •Catalog: UC3842, UC1842, UC3843, UC3844, UC1844, UC3845, UC1845, UC3842M, UC3845A •Enhanced Product: UC1845A-EP •Military: UC1842, UC1843, UC1844, UC1845, UC1845A •Space: UC1842-SP, UC1843-SP, UC1844-SP, UC1845-SP, UC1845A-SP NOTE: Qualified Version Definitions: Addendum-Page 7

PACKAGE OPTION ADDENDUM www.ti.com 28-Apr-2020 •Catalog - TI's standard catalog product •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 8

PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UC2842D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC2842DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC2843D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC2843DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC2844D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC2844DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC2845D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC2845DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC3842D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC3842DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC3843D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC3843DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC3844D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC3844DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 UC3845D8TR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC3845DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UC2842D8TR SOIC D 8 2500 340.5 338.1 20.6 UC2842DTR SOIC D 14 2500 333.2 345.9 28.6 UC2843D8TR SOIC D 8 2500 340.5 338.1 20.6 UC2843DTR SOIC D 14 2500 333.2 345.9 28.6 UC2844D8TR SOIC D 8 2500 340.5 338.1 20.6 UC2844DTR SOIC D 14 2500 333.2 345.9 28.6 UC2845D8TR SOIC D 8 2500 340.5 338.1 20.6 UC2845DTR SOIC D 14 2500 333.2 345.9 28.6 UC3842D8TR SOIC D 8 2500 340.5 338.1 20.6 UC3842DTR SOIC D 14 2500 333.2 345.9 28.6 UC3843D8TR SOIC D 8 2500 340.5 338.1 20.6 UC3843DTR SOIC D 14 2500 333.2 345.9 28.6 UC3844D8TR SOIC D 8 2500 340.5 338.1 20.6 UC3844DTR SOIC D 14 2500 333.2 345.9 28.6 UC3845D8TR SOIC D 8 2500 340.5 338.1 20.6 UC3845DTR SOIC D 14 2500 333.2 345.9 28.6 PackMaterials-Page2

None

None

None

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated