UC2842B/3B/4B/5B UC3842B/3B/4B/5B ® HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER . .TRIMMED OSCILLATOR FOR PRECISE FRE- QUENCY CONTROL .OSCILLATOR FREQUENCY GUARANTEED .AT 250kHz CURRENT MODE OPERATION TO 500kHz .AUTOMATIC FEED FORWARD COMPENSA- TION Minidip SO8 .LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING .INTERNALLY TRIMMED REFERENCE WITH .UNDERVOLTAGE LOCKOUT comparator which also provides current limit control, HIGH CURRENT TOTEM POLE OUTPUT and a totem pole output stage designed to source .UNDERVOLTAGE LOCKOUT WITH HYSTER- or sink high peak current. The output stage, suitable ESIS for driving N-Channel MOSFETs, is low in the off- LOW START-UP AND OPERATING CURRENT state. Differences between members of this family are the DESCRIPTION under-voltage lockout thresholds and maximum duty The UC384xB family of control ICs provides the nec- cycle ranges. The UC3842B and UC3844B have essary features to implement off-line or DC to DC UVLO thresholds of 16V (on) and 10V (off), ideally fixed frequency current mode control schemes with suited off-line applications The corresponding thresh- a minimal external parts count. Internally imple- olds for the UC3843B and UC3845B are 8.5 V and 7.9 mented circuits include a trimmed oscillator for pre- V. The UC3842B and UC3843B can operate to duty cise DUTY CYCLE CONTROL under voltage lock- cycles approaching 100%. A range of the zero to < out featuring start-up current less than 0.5mA, a pre- 50 % is obtained by the UC3844B and UC3845B by cision reference trimmed for accuracy at the error the addition of an internal toggle flip flop which blanks amp input, logic to insure latched operation, a PWM the output off every other clock cycle. BLOCK DIAGRAM (toggle flip flop used only in UC3844B and UC3845B) 7 Vi 5 34V UVLO S/R 5V 8 VREF GROUND REF 5V 50mA INTERNAL 2.50V BIAS VREF GOOD LOGIC 6 OUTPUT 4 RT/CT OSC T ERROR AMP. + 2R S 2 VFB - R PWM R 1V LATCH 1 COMP CURRENT SENSE 3 UC3842B CURRENT COMPARATOR SENSE D95IN331 March 1999 1/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V Supply Voltage (low impedance source) 30 V i Vi Supply Voltage (Ii < 30mA) Self Limiting IO Output Current – 1 A EO Output Energy (capacitive load) 5 m J Analog Inputs (pins 2, 3) – 0.3 to 5.5 V Error Amplifier Output Sink Current 10 mA Ptot Power Dissipation at Tamb £ 25 (cid:176) C (Minidip) 1.25 W Ptot Power Dissipation at Tamb £ 25 (cid:176) C (SO8) 800 mW Tstg Storage Temperature Range – 65 to 150 (cid:176) C T Junction Operating Temperature – 40 to 150 °C J TL Lead Temperature (soldering 10s) 300 (cid:176) C * All voltages are with respect to pin 5, all currents are positive into the specified terminal. PIN CONNECTION (top view) Minidip/SO8 COMP 1 8 V REF V 2 7 Vi FB I 3 6 OUTPUT SENSE R /C 4 5 GROUND T T D95IN332 PIN FUNCTIONS No Function Description 1 COMP This pin is the Error Amplifier output and is made available for loop compensation. 2 V This is the inverting input of the Error Amplifier. It is normally connected to the switching FB power supply output through a resistor divider. 3 I A voltage proportional to inductor current is connected to this input. The PWM uses this SENSE information to terminate the output switch conduction. 4 R /C The oscillator frequency and maximum Output duty cycle are programmed by connecting T T resistor R to Vref and cpacitor C to ground. Operation to 500kHz is possible. T T 5 GROUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. 7 V This pin is the positive supply of the control IC. CC 8 V This is the reference output. It provides charging current for capacitor C through resistor R . ref T T ORDERING NUMBERS SO8 Minidip UC2842BD1; UC3842BD1 UC2842BN; UC3842BN UC2843BD1; UC3843BD1 UC2843BN; UC3843BN UC2844BD1; UC3844BD1 UC2844BN; UC3844BN UC2845BD1; UC3845BD1 UC2845BN; UC3845BN 2/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B THERMAL DATA Symbol Description Minidip SO8 Unit Rth j-amb Thermal Resistance Junction-ambient. max. 100 150 (cid:176) C/W ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for -25 < T < 85(cid:176) C for UC284XB; 0 < T < 70(cid:176) C for UC384XB; V = 15V (note 5); R = 10K; C = 3.3nF) amb amb i T T UC284XB UC384XB Symbol Parameter Test Conditions Unit Min. Typ. Max. Min. Typ. Max. REFERENCE SECTION VREF Output Voltage Tj = 25(cid:176) C Io = 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V D VREF Line Regulation 12V £ Vi £ 25V 2 20 2 20 mV D VREF Load Regulation 1 £ Io £ 20mA 3 25 3 25 mV D V /D T Temperature Stability (Note 2) 0.2 0.2 mV/(cid:176) C REF Total Output Variation Line, Load, Temperature 4.9 5.1 4.82 5.18 V eN Output Noise Voltage 10Hz £ f £ 10KHz Tj = 25(cid:176) C 50 50 m V (note 2) Long Term Stability T = 125(cid:176) C, 1000Hrs 5 25 5 25 mV amb (note 2) ISC Output Short Circuit -30 -100 -180 -30 -100 -180 mA OSCILLATOR SECTION fOSC Frequency Tj = 25(cid:176) C 49 52 55 49 52 55 KHz TA = Tlow to Thigh 48 – 56 48 – 56 KHz T = 25°C (R = 6.2k, C = 1nF) 225 250 275 225 250 275 KHz J T T D fOSC/D V Frequency Change with Volt. VCC = 12V to 25V – 0.2 1 – 0.2 1 % D fOSC/D T Frequency Change with Temp. TA = Tlow to Thigh – 1 – – 0.5 – % V Oscillator Voltage Swing (peak to peak) – 1.6 – – 1.6 – V OSC I Discharge Current (V =2V) T = 25°C 7.8 8.3 8.8 7.8 8.3 8.8 mA dischg OSC J T = T to T 7.5 – 8.8 7.6 – 8.8 mA A low high ERROR AMP SECTION V2 Input Voltage VPIN1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V Ib Input Bias Current VFB = 5V -0.1 -1 -0.1 -2 m A AVOL 2V £ Vo £ 4V 65 90 65 90 dB BW Unity Gain Bandwidth T = 25°C 0.7 1 0.7 1 MHz J PSRR Power Supply Rejec. Ratio 12V £ V £ 25V 60 70 60 70 dB i Io Output Sink Current VPIN2 = 2.7V VPIN1 = 1.1V 2 12 2 12 mA Io Output Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -1 -0.5 -1 mA VOUT High VPIN2 = 2.3V; 5 6.2 5 6.2 V R = 15KW to Ground L VOUT Low VPIN2 = 2.7V; 0.8 1.1 0.8 1.1 V R = 15KW to Pin 8 L CURRENT SENSE SECTION GV Gain (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V V3 Maximum Input Signal VPIN1 = 5V (note 3) 0.9 1 1.1 0.9 1 1.1 V SVR Supply Voltage Rejection 12 £ V £ 25V (note 3) 70 70 dB i Ib Input Bias Current -2 -10 -2 -10 m A Delay to Output 150 300 150 300 ns 3/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B ELECTRICAL CHARACTERISTICS (continued) UC284XB UC384XB Symbol Parameter Test Conditions Unit Min. Typ. Max. Min. Typ. Max. OUTPUT SECTION V Output Low Level I = 20mA 0.1 0.4 0.1 0.4 V OL SINK I = 200mA 1.6 2.2 1.6 2.2 V SINK V Output High Level I = 20mA 13 13.5 13 13.5 V OH SOURCE I = 200mA 12 13.5 12 13.5 V SOURCE V UVLO Saturation VCC = 6V; I = 1mA 0.1 1.1 0.1 1.1 V OLS SINK tr Rise Time Tj = 25(cid:176) C CL = 1nF (2) 50 150 50 150 ns tf Fall Time Tj = 25(cid:176) C CL = 1nF (2) 50 150 50 150 ns UNDER-VOLTAGE LOCKOUT SECTION Start Threshold X842B/4B 15 16 17 14.5 16 17.5 V X843B/5B 7.8 8.4 9.0 7.8 8.4 9.0 V Min Operating Voltage X842B/4B 9 10 11 8.5 10 11.5 V After Turn-on X843B/5B 7.0 7.6 8.2 7.0 7.6 8.2 V PWM SECTION Maximum Duty Cycle X842B/3B 94 96 100 94 96 100 % X844B/5B 47 48 50 47 48 50 % Minimum Duty Cycle 0 0 % TOTAL STANDBY CURRENT Ist Start-up Current Vi = 6.5V for UCX843B/45B 0.3 0.5 0.3 0.5 mA Vi = 14V for UCX842B/44B 0.3 0.5 0.3 0.5 mA Ii Operating Supply Current VPIN2 = VPIN3 = 0V 12 17 12 17 mA V Zener Voltage I = 25mA 30 36 30 36 V iz i Notes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : A = DD VVPPIINN13 ; 0 £ VPIN3 £ 0.8 V 5. Adjust Vi above the start threshold before setting at 15 V. 4/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 1: Open Loop Test Circuit. V REF 4.7KW R T 2N2222 A V i V REF 0.1m F 100KW COMP 8 1 7 V V ERROR AMP. FB i 2 ADJUST 1KW 0.1m F 1W I UC2842B 1KW 4.7KW ISENSE SENSE 3 OUTPUT ADJUST 5KW 6 OUTPUT R /C T T 4 GROUND 5 C T D95IN343 GROUND High peak currents associated with capacitive loads to pin 5 in a single point ground. The transistor and necessitate careful grounding techniques. Timing 5 KW potentiometer are used to sample the oscillator and bypass capacitors should be connected close waveform and apply an adjustable ramp to pin 3. Figure 2: Timing Resistor vs. Oscillator Fre- Figure 3: Output Dead-Time vs. Oscillator Fre- quency quency RT D95IN333 D95IN334 (KW ) % 2500 CT=5nF CTC=TC1=nT2F=0500p0FpF CT=100pF 235000 CT=1nF CT=5nF CT=2nF 10 CT=10nF 10 CT=500pF 5 CT=200pF 5 CT=2nF CT=10nF 3 CT=100pF 2 Vi=15V 2 TA=25˚C Vi=15V 1 TA=25˚C 0.8 1 10K 20K 30K 50K 100K 200K 300K 500K fOSC(KHz) 10K 20K 30K 50K 100K 200K 300K 500K fOSC(KHz) 5/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 4: Oscillator Discharge Current vs. Tem- Figure 5: Maximum Output Duty Cycle vs. Tim- perature. ing Resistor. Idischg D95IN335 Dmax D95IN336 (mA) (%) Vi=15V 90 VOSC=2V 8.5 Idischg=7.5mA 80 Idischg=8.8mA 8.0 70 60 Vi=15V 7.5 CT=3.3nF 50 TA=25˚C 7.0 40 0.8 1 2 3 5 RT(KW ) -55 -25 0 25 50 75 100 TA(˚C) Figure 6: Error Amp Open-Loop Gain and Figure 7: Current Sense Input Threshold vs. Er- Phase vs. Frequency. ror Amp Output Voltage. (dB) D95IN337 f Vth D95IN338 Vi=15V (V) Vi=15V VO=2V to 4V 80 30 1.0 RL=100K Gain TA=25˚C TA=25˚C 60 60 0.8 TA=125˚C 40 90 0.6 Phase 20 120 0.4 TA=-40˚C 0 150 0.2 -20 180 0.0 10 100 1K 10K 100K 1M f(Hz) 0 2 4 6 VO(V) Figure 8: Reference Voltage Change vs. Figure 9: Reference Short Circuit Current vs. Source Current. Temperature. 60 D95IN339 ISC D95IN340 (mA) Vi=15V Vi=15V 50 100 RL£ 0.1W 40 TA=-40˚C 90 TA=125˚C 30 80 C ˚ 20 25 70 = A T 10 60 0 50 0 20 40 60 80 100 Iref(mA) -55 -25 0 25 50 75 100 TA(˚C) 6/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 10: Output Saturation Voltagevs. Load Figure 11: Supply Current vs. Supply Voltage. Current. Vsat D95IN341 Ii D95IN342 (V) Source Saturation (mA) Vi (Load to Ground) -1 TA=25˚C TA=-40˚C 20 -2 Vi=15V 80m s Pulsed Load 120Hz Rate 15 3 2 TA=-40˚C 10 843/45 842/44 RCVFTTB===1300.3VKnF TA=25˚C CX CX ISense=0V 5 U U TA=25˚C 1 Sink Saturation GND (Load to Vi) 0 0 0 200 400 600 IO(mA) 0 10 20 30 Vi(V) Figure 12: Output Waveform. Figure 13: Output Cross Conduction V =30V V =15V i i C = 15pF C = 1.0nF L 90% L T = 25°C T = 25°C A A VO 20V/DIV I CC 10% 100mA/DIV 50ns/DIV 100ns/DIV Figure 14: Oscillator and Output Waveforms. V i 7 CT 8 5V REG OUTPUT PWM 6 R OUTPUT LARGE R /SMALL C T T T CLOCK 4 OSCILLATOR CT I D C OUTPUT T 5 SMALL R /LARGE C T T GND D95IN344 7/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 15 : Error Amp Configuration. 2.5V 1mA + V 2 FB Z - i COMP 1 Z f D95IN345 Figure 16 : Under Voltage Lockout. 7 ON/OFF COMMAND Vi TO REST OF IC ICC <17mA UC3842B UC3843B UC3844B UC3845B V 16V 8.4V ON <0.5mA V CC V V V 10V 7.6V OFF ON OFF D95IN346 During UVLO, the Output is low Figure 17 : Current Sense Circuit . ERROR AMPL. 2R I S 1 R 1V COMP CURRENT SENSE R 3 COMPARATOR CURRENT R C SENSE S 5 GND D95IN347 Peak current (i ) is determined by the formula s 1.0 V I » S max RS A small RC filter may be required to suppress switch transients. 8/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 18 : Slope Compensation Techniques. V V REG REG 8 8 R R T T R /C R /C T T T T I 4 I 4 S UC3842B S UC3842B R C C SLOPE T T R SLOPE R1 ISENSE R1 ISENSE 3 3 5 5 R R S S GND GND D95IN348 Figure 19 : Isolated MOSFET Drive and Current Transformer Sensing. V V CC in 7 + ISOLATION 5.0Vref BOUNDARY - V Waveforms GS Q1 + + + 6 0 0 - - - 50% DC 25% DC S Q V -1.4 (N ) (pin 1) S R I = pk 3R N S P - + COMP/LATCH 3 R R N N C S S P D95IN349 9/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 20 : Latched Shutdown. 4 OSC 8 R BIAS R + 1mA + 2R - 2 EA R 1 5 2N 3905 2N 3903 D95IN350 SCR must be selected for a holding current of less than 0.5mA at T . A(min) The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K. Figure 21: Error Amplifier Compensation + From V 2.5V O 1mA Ri + 2R - 2 EA R R C R d f f 1 5 Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. + From V 2.5V O 1mA RP + 2R R i - 2 EA R C R C R P d f f 1 5 D95IN351 Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. 10/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 22: External Clock Synchronization. V REF 8 R BIAS R R T 4 OSC + C T EXTERNAL SYNC INPUT 0.01m F + 2R - 2 EA 47W R 1 5 D95IN352 The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of C to go more than 300mV below ground T Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization. V 8 REF R R A BIAS 8 4 R 5K R B 6 + 3 4 5 R OSC - + 5K Q 7 + + 2R 2 S 2 - - EA C 5K R 1 NE555 1 5 TO ADDITIONAL UCX84XAs 1.44 R B f = Dmax = D95IN353 (R + 2R )C R + 2R A B A B 11/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Figure 24: Soft-Start Circuit 8 5V ref R + BIAS - R 4 OSC + 1mA S + 2R Q 2 + - R 1MW EA - R 1V 1 C 5 D95IN354 Figure 25: Soft-Start and Error Amplifier Output Duty Cycle Clamp. V V CC in 7 + 8 5V ref - R + BIAS - 7 R 4 6 OSC Q1 + 1mA V S Clamp + 2R Q 5 2 - - R R2 EA R 1V + 1 Comp/Latch 5 R C R1 BC109 S R V VCLAMP = · R +1 R where 0 <VCLAMP <1V Ipk(max) = CRLAMP D95IN355 1 2 S 12/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A 1.75 0.069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45(cid:176) (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 SO8 M 0.6 0.024 S 8(cid:176) (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 13/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D 10.92 0.430 E 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 3.81 0.125 0.150 Minidip Z 1.52 0.060 14/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi- croelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 15/15