UC3844B, UC3845B, UC2844B, UC2845B High Performance Current Mode Controllers The UC3844B, UC3845B series are high performance fixed frequency current mode controllers. They are specifically designed for Off−Line and dc−dc converter applications offering the designer a cost−effective solution with minimal external components. These integrated circuits http://onsemi.com feature an oscillator, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. PDIP−8 Also included are protective features consisting of input and N SUFFIX reference undervoltage lockouts each with hysteresis, cycle−by−cycle CASE 626 current limiting, a latch for single pulse metering, and a flip−flop 8 which blanks the output off every other oscillator cycle, allowing 1 output deadtimes to be programmed from 50% to 70%. These devices are available in an 8−pin dual−in−line and surface SOIC−14 mount (SOIC−8) plastic package as well as the 14−pin plastic surface D SUFFIX 14 mount (SOIC−14). The SOIC−14 package has separate power and CASE 751A ground pins for the totem pole output stage. 1 The UCX844B has UVLO thresholds of 16V (on) and 10V (off), ideally suited for off−line converters. The UCX845B is tailored for lower voltage SOIC−8 applications having UVLO thresholds of 8.5V (on) and 7.6V (off). 8 D1 SUFFIX Features CASE 751 • 1 Trimmed Oscillator for Precise Frequency Control • Oscillator Frequency Guaranteed at 250 kHz • Current Mode Operation to 500 kHz Output Switching Frequency • PIN CONNECTIONS Output Deadtime Adjustable from 50% to 70% • • Automatic Feed Forward Compensation Compensation 1 8 Vref Latching PWM for Cycle−By−Cycle Current Limiting Voltage Feedback 2 7 VCC • Internally Trimmed Reference with Undervoltage Lockout Current Sense 3 6 Output • High Current Totem Pole Output RT/CT 4 5 GN • D Undervoltage Lockout with Hysteresis (Top View) • Low Startup and Operating Current • These Devices are Pb−Free and are RoHS Compliant Compensation 1 14 Vref • NC 2 13 NC NCV Prefix for Automotive and Other Applications Requiring Voltage Feedback 3 12 VCC Unique Site and Control Change Requirements; AEC−Q100 NC 4 11 VC Qualified and PPAP Capable Current Sense 5 10 Output VCC 7(12) NC 6 9 GND RT/CT 7 8 Power Ground Vref 5.0V UndeVrCvoCltage (Top View) 8(14) R Reference Lockout R UndeVrvreofltage VC ORDERING INFORMATION Lockout 7(11) See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. RT/CT Output Oscillator 4(7) Latching 6(10) DEVICE MARKING INFORMATION PWM Power Voltage Ground See general marking information in the device marking Feedback section on page 16 of this data sheet. Input 5(8) 2(3) Error Current Output/ Amplifier Sense Input Compensation 1(1) 3(5) GND 5(9) Pin numbers in parenthesis are for the D suffix SOIC-14 package. Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: August, 2013 − Rev. 11 UC3844B/D

UC3844B, UC3845B, UC2844B, UC2845B MAXIMUM RATINGS Rating Symbol Value Unit Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) (Note 1) VCC, VC 36 V Total Power Supply and Zener Current (ICC + IZ) 30 mA Output Current, Source or Sink (Note 2) IO 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 (cid:2)J Current Sense and Voltage Feedback Inputs Vin −0.3 to +5.5 V Error Amp Output Sink Current IO 10 mA Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SOIC−14 Case 751A Maximum Power Dissipation @ TA = 25°C PD 862 mW Thermal Resistance, Junction−to−Air R(cid:3)JA 145 °C/W D1 Suffix, Plastic Package, SOIC−8 Case 751 Maximum Power Dissipation @ TA = 25°C PD 702 mW Thermal Resistance, Junction−to−Air R(cid:3)JA 178 °C/W N Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 25°C PD 1.25 W Thermal Resistance, Junction−to−Air R(cid:3)JA 100 °C/W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature UC3844B, UC3845B TA 0 to +70 °C UC2844B, UC2845B −25 to +85 UC3844BV, UC3845BV −40 to +105 Storage Temperature Range Tstg −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The voltage is clamped by a zener diode (see page 9 Under Voltage Lockout section). Therefore this voltage may be exceeded as long as the total power supply and zener current is not exceeded. 2. Maximum package power dissipation limits must be observed. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard JESD22-A114B, Machine Model Method 200 V per JEDEC Standard JESD22-A115-A 4. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78 ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 5], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 6], unless otherwise noted.) UC284xB UC384xB, xBV, NCV384xBV Characteristic Symbol Min Typ Max Min Typ Max Unit REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV Temperature Stability TS − 0.2 − − 0.2 − mV/°C Total Output Variation over Line, Load, & Temperature Vref 4.9 − 5.1 4.82 − 5.18 V Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − (cid:2)V Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV Output Short Circuit Current ISC −30 −85 −180 −30 −85 −180 mA OSCILLATOR SECTION Frequency TJ = 25°C fOSC 49 52 55 49 52 55 kHz TA = Tlow to Thigh 48 − 56 48 − 56 TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) 225 250 275 225 250 275 Frequency Change with Voltage (VCC = 12 V to 25 V) (cid:4)fOSC/(cid:4)V − 0.2 1.0 − 0.2 1.0 % Frequency Change w/ Temperature (TA = Tlow to Thigh) (cid:4)fOSC/(cid:4)T − 1.0 − − 0.5 − % Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V 5. Adjust VCC above the Startup threshold before setting to 15 V. 6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow= 0°C for UC3844B, UC3845B Thigh= +70°C for UC3844B, UC3845B = −25°C for UC2844B, UC2845B = +85°C for UC2844B, UC2845B = −40°C for UC384xBV, NCV384xBV =+105°C for UC3844BV, UC3845BV = +125°C for NCV384xBV http://onsemi.com 2

UC3844B, UC3845B, UC2844B, UC2845B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.) UC284xB UC384xB, xBV, NCV384xBV Characteristic Symbol Min Typ Max Min Typ Max Unit OSCILLATOR SECTION Discharge Current (VOSC = 2.0 V) TJ = 25°C Idischg 7.8 8.3 8.8 7.8 8.3 8.8 mA TA = Tlow to Thigh (UC284XB, UC384XB) 7.5 − 8.8 7.6 − 8.8 (UC384XBV) − − − 7.2 − 8.8 ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V Input Bias Current (VFB = 5.0 V) IIB − −0.1 −1.0 − −0.1 −2.0 (cid:2)A Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB Output Current − Sink (VO = 1.1 V, VFB = 2.7 V) ISink 2.0 12 − 2.0 12 − mA Output Current − Source (VO = 5.0 V, VFB = 2.3 V) ISource −0.5 −1.0 − −0.5 −1.0 − Output Voltage Swing V High State (RL = 15 k to ground, VFB = 2.3 V) VOH 5.0 6.2 − 5.0 6.2 − Low State (RL = 15 k to Vref, VFB = 2.7 V) VOL (UC284XB, UC384XB) − 0.8 1.1 − 0.8 1.1 (UC384XBV) − − − − 0.8 1.2 CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 9 & 10) AV V/V (UC284XB, UC384XB) 2.85 3.0 3.15 2.85 3.0 3.15 (UC384XBV) − − − 2.85 3.0 3.25 Maximum Current Sense Input Threshold (Note 9) Vth V (UC284XB, UC384XB) 0.9 1.0 1.1 0.9 1.0 1.1 (UC384XBV) − − − 0.85 1.0 1.1 Power Supply Rejection Ratio (VCC = 12 V to 25 V) (Note 9) PSRR − 70 − − 70 − dB Input Bias Current IIB − −2.0 −10 − −2.0 −10 (cid:2)A Propagation Delay (Current Sense Input to Output) tPLH(In/Out) − 150 300 − 150 300 ns OUTPUT SECTION Output Voltage V Low State (ISink = 20 mA) VOL − 0.1 0.4 − 0.1 0.4 (ISink = 200 mA, UC284XB, UC384XB) − 1.6 2.2 − 1.6 2.2 (ISink = 200 mA, UC384XBV) − − − − 1.6 2.3 High State (ISource = 20 mA, UC284XB, UC384XB) VOH 13 13.5 − 13 13.5 − (ISource = 20 mA, UC384XBV) − − − 12.9 − − (ISource = 200 mA) 12 13.4 − 12 13.4 − Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns UNDERVOLTAGE LOCKOUT SECTION Startup Threshold UCX844B, BV Vth 15 16 17 14.5 16 17.5 V UCX845B, BV 7.8 8.4 9.0 7.8 8.4 9.0 Minimum Operating Voltage After Turn−On UCX844B, BV VCC(min) 9.0 10 11 8.5 10 11.5 V UCX845B, BV 7.0 7.6 8.2 7.0 7.6 8.2 7. Adjust VCC above the Startup threshold before setting to 15 V. 8. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow= 0°C for UC3844B, UC3845B Thigh= +70°C for UC3844B, UC3845B = −25°C for UC2844B, UC2845B = +85°C for UC2844B, UC2845B = −40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV = +125°C for NCV384xBV 9. This parameter is measured at the latch trip point with VFB = 0 V. 10.Comparator gain is defined as: AV = (cid:4)(cid:4)VV OCuutrpreunt/tC Soemnpseen Isnaptuiotn http://onsemi.com 3

UC3844B, UC3845B, UC2844B, UC2845B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 11], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 12], unless otherwise noted.) UC284xB UC384xB, xBV, NCV384xBV Characteristic Symbol Min Typ Max Min Typ Max Unit PWM SECTION Duty Cycle % Maximum (UC284XB, UC384XB) DC(max) 47 48 50 47 48 50 Maximum (UC384XBV) − − − 46 48 50 Minimum DC(min) − − 0 − − 0 TOTAL DEVICE Power Supply Current ICC mA Startup (VCC = 6.5 V for UCX845B, − 0.3 0.5 − 0.3 0.5 Startup (VCC = 14 V for UCX844B, BV) Operating (Note 11) − 12 17 − 12 17 Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V 11.Adjust VCC above the Startup threshold before setting to 15 V. 12.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow= 0°C for UC3844B, UC3845B Thigh= +70°C for UC3844B, UC3845B = −25°C for UC2844B, UC2845B = +85°C for UC2844B, UC2845B = −40°C for UC384xBV, NCV384xBV = +105°C for UC3844BV, UC3845BV =+125°C for NCV384xBV ÄÄÄÄÄ 80 75 ΩR (k) 2500 VTAC C= =2 51°5C V DEADTIME 70ÄÄÄ1234....(cid:2)(cid:2)(cid:2)(cid:2)ÄÄÄCCCCTTTT ==== ÄÄÄ5211...0000 nnnnFÄÄÄFFF ÄÄÄ 2 34 RESISTO 8.0 OUTPUT 65ÄÄ567...(cid:2)(cid:2)(cid:2)ÄÄCCCTTT === ÄÄ521000000 pppÄÄFFF ÄÄ 1 NG 5.0 NT 60 MI CE 7 TI R R, T2.0 T, PE 55 5 NOTE: Output switches at D 1/2 the oscillator frequency % 6 0.8 50 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M fOSC, OSCILLATOR FREQUENCY (kHz) fOSC, OSCILLATOR FREQUENCY (kHz) ForR (cid:2)5Kf(cid:3) 1.72 T R C T T Figure 2. Timing Resistor Figure 3. Output Deadtime versus Oscillator Frequency versus Oscillator Frequency VCC = 15 V VCC = 15 V 2.55 V ATAV == 2-51°.0C 3.0 V ATAV == 2-51°.0C 2.5 V mV/DIV 2.5 V mV/DIV 20 00 2 2.45 V 2.0 V 0.5 (cid:2)s/DIV 1.0 (cid:2)s/DIV Figure 4. Error Amp Small Signal Figure 5. Error Amp Large Signal Transient Response Transient Response http://onsemi.com 4

UC3844B, UC3845B, UC2844B, UC2845B 100 0 V) 1.2 B) D ( N LOOP VOLTAGE GAIN (d 24680000 Gain VVRTACOL C === = 212 501.0°05 C VkV toP 4h.a0s Ve 136920000SS PHASE (DEGREES)SENSE INPUT THRESHOL 0001....4680 VCC = T1AT5 A =V =1 2255°°CC , OPEVOL 0 150φ, EXCECURRENT 0.2 TA = -(cid:3)55°C A-(cid:3)20 180 , h 0 10 100 1.0 k 10 k 100 k 1.0 M 10 M Vt 0 2.0 4.0 6.0 8.0 f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (VO) Figure 6. Error Amp Open Loop Gain and Figure 7. Current Sense Input Threshold Phase versus Frequency versus Error Amp Output Voltage A) NGE (mV)-(cid:3)4.00 VCC = 15 V RRENT (m110 ÄÄVRCLÄÄ C≤ =0 .11ÄÄ5 (cid:5) V ÄÄ A U H C TAGE C-(cid:3)8.0 RCUIT 90 RENCE VOL --(cid:3)(cid:3)1162 TA = 125°C TA = -(cid:4)55°C E SHORT CI 70 E C F N E E R -(cid:3)20 R , Vref TA = 25°C REFE Δ -(cid:3)24 , 50 0 20 40 60 80 100 120 SC -(cid:3)55 -(cid:3)25 0 25 50 75 100 125 I Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C) Figure 8. Reference Voltage Change Figure 9. Reference Short Circuit Current versus Source Current versus Temperature V) V) DI DI E (2.0 mV/ VTIOAC =C= 1=2. 501° 5mC VA to 20 mA E (2.0 mV/ VTAC C= =2 51°2C V to 25 V G G N N A A H H C C E E G G A A T T L L O O V V T T U U P P T T U U O O , O , O V V Δ Δ 2.0 ms/DIV 2.0 ms/DIV Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation http://onsemi.com 5

UC3844B, UC3845B, UC2844B, UC2845B 0 VOLTAGE (V)--(cid:3)12..00 ÄVCÄC ÄÄTA =ÄÄ 25°CÄÄÄÄÄS(LoÄÄÄouarcde t ÄÄÄoS aGtruorÄÄÄuantiodn)ÄÄÄÄV8102ÄÄC 0C(cid:2) Hs= z PÄÄ1 Ru5l asVteeÄÄd LoaÄÄd 9%0 VTCACL C== =21 5.10°5 Cn VF N TA = -(cid:3)55°C O ÄÄÄÄ TI A TUR 3.0 ÄÄÄÄ TPUT SA 2.0 ÄTAÄ = -(cid:3)Ä55°CÄÄÄÄÄÄÄÄTÄÄA = 25ÄÄ°C ÄÄ U 10 V, Osat 1.00 ÄS(ÄLinoka Sd Äatotu VraCtÄiCo)n ÄÄGÄND Ä % 0 200 400 600 800 50 ns/DIV I(cid:3)O, OUTPUT LOAD CURRENT (mA) Figure 12. Output Saturation Voltage Figure 13. Output Waveform versus Load Current E G TA 25 OL VCC = 30 V OUTPUT V CTAL == 2155° pCF 0 V/DIV ENT (mA) 20 , O 2 RR 15 V CU Y L ÄÄÄÄ UPPLY CURRENT 100 mA/DIV , SUPPICC1500 UCX845B UCX844B ÄÄÄÄÄÄRCVTISAFTTe B n=== s =ÄÄÄ e213 50=0.3° V0k Cn ÄÄÄVF , SC 0 10 20 30 40 IC 100 ns/DIV VCC, SUPPLY VOLTAGE (V) Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage PIN FUNCTION DESCRIPTION Pin 8−Pin 14−Pin Function Description 1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation. 2 3 Voltage This is the inverting input of the Error Amplifier. It is normally connected to the switching power Feedback supply output through a resistor divider. 3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. 4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible. 5 GND This pin is the combined control circuitry and power ground. 6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. The output switches at one−half the oscillator frequency. 7 12 VCC This pin is the positive supply of the control IC. 8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. 8 Power This pin is a separate power ground return that is connected back to the power source. It is used Ground to reduce the effects of switching transient noise on the control circuitry. 11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 9 GND This pin is the control circuitry ground return and is connected back to the powersource ground. 2,4,6,13 NC No connection. These pins are not internally connected. http://onsemi.com 6

UC3844B, UC3845B, UC2844B, UC2845B OPERATING DESCRIPTION The UC3844B, UC3845B series are high performance, Comparator. This guarantees that no drive pulses appear at fixed frequency, current mode controllers. They are the Output (Pin 6) when Pin 1 is at its lowest state (V ). OL specifically designed for Off−Line and DC−DC converter This occurs when the power supply is operating and the load applications offering the designer a cost−effective solution is removed, or at the beginning of a soft−start interval with minimal external components. A representative block (Figures 21, 22). The Error Amp minimum feedback diagram is shown in Figure 16. resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (V ) to reach the OH Oscillator comparator’s 1.0 V clamp level: The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT Rf(min) ≈ 3.0 (1.0 V) + 1.4 V = 8800 (cid:5) 0.5 mA is charged from the 5.0 V reference through resistor R to T approximately 2.8 V and discharged to 1.2 V by an internal Current Sense Comparator and PWM Latch current sink. During the discharge of C , the oscillator T The UC3844B, UC3845B operate as a current mode generates an internal blanking pulse that holds the center controller, whereby output switch conduction is initiated by input of the NOR gate high. This causes the Output to be in the oscillator and terminated when the peak inductor current a low state, thus producing a controlled amount of output reaches the threshold level established by the Error deadtime. An internal flip−flop has been incorporated in the Amplifier Output/Compensation (Pin 1). Thus the error UCX844/5B which blanks the output off every other clock signal controls the peak inductor current on a cycle by holding one of the inputs of the NOR gate high. This cycle−by−cycle basis. The Current Sense Comparator PWM in combination with the C discharge period yields output T Latch configuration used ensures that only a single pulse deadtimes programmable from 50% to 70%. Figure 2 shows appears at the Output during any given oscillator cycle. The R versus Oscillator Frequency and Figure 3, Output T inductor current is converted to a voltage by inserting the Deadtime versus Frequency, both for given values of C . T ground−referenced sense resistor R in series with the S Note that many values of R and C will give the same T T source of output switch Q1. This voltage is monitored by the oscillator frequency but only one combination will yield a Current Sense Input (Pin 3) and compared to a level derived specific output deadtime at a given frequency. The oscillator from the Error Amp Output. The peak inductor current under thresholds are temperature compensated to within ±6% normal operating conditions is controlled by the voltage at at 50 kHz. Also, because of industry trends moving the Pin 1 where: UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within ±10% at 250 kHz. I = V(Pin 1) − 1.4 V pk In many noise−sensitive applications it may be desirable 3 RS to frequency−lock the converter to an external system clock. Abnormal operating conditions occur when the power This can be accomplished by applying a clock signal to the supply output is overloaded or if output voltage sensing is circuit shown in Figure 18. For reliable locking, the lost. Under these conditions, the Current Sense Comparator free−running oscillator frequency should be set about 10% threshold will be internally clamped to 1.0 V. Therefore the less than the clock frequency. A method for multi−unit maximum peak switch current is: synchronization is shown in Figure 19. By tailoring the 1.0 V clock waveform, accurate Output duty cycle clamping can Ipk(max) = R be achieved to realize output deadtimes of greater than 70%. S When designing a high power switching regulator it Error Amplifier becomes desirable to reduce the internal clamp voltage in order A fully compensated Error Amplifier with access to the to keep the power dissipation of R to a reasonable level. A S inverting input and output is provided. It features a typical simple method to adjust this voltage is shown in Figure 20. The dc voltage gain of 90 dB, and a unity gain bandwidth of two external diodes are used to compensate the internal diodes, 1.0 MHz with 57 degrees of phase margin (Figure 6). The yielding a constant clamp voltage over temperature. Erratic non−inverting input is internally biased at 2.5 V and is not operation due to noise pickup can result if there is an excessive pinned out. The converter output voltage is typically divided reduction of the I clamp voltage. pk(max) down and monitored by the inverting input. The maximum A narrow spike on the leading edge of the current input bias current is −2.0 (cid:2)A which can cause an output waveform can usually be observed and may cause the power voltage error that is equal to the product of the input bias supply to exhibit an instability when the output is lightly current and the equivalent input divider source resistance. loaded. This spike is due to the power transformer The Error Amp Output (Pin 1) is provided for external interwinding capacitance and output rectifier recovery time. loop compensation (Figure 29). The output voltage is offset The addition of an RC filter on the Current Sense Input with by two diode drops (≈1.4 V) and divided by three before it a time constant that approximates the spike duration will connects to the inverting input of the Current Sense usually eliminate the instability (refer to Figure 24). http://onsemi.com 7

UC3844B, UC3845B, UC2844B, UC2845B VCC Vin VCC 7(12) 36V Vref Reference Regulator 8(14) R Internal UVVCLCO +- T(Seexte) VC RT 2.5V Bias R + 7(11) 3.6V - Vref UVLO Output Q1 Oscillator CT 4(7) + 1.0mA T 6(10) S Power Ground Voltage 2R Q Feedback R PWM 5(8) Input2(3) Error R 1.0V Latch Current Sense Input Amplifier Output/ Compensation1(1) CCurormenpta Sraetnosre 3(5) RS GND 5(9) Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. = Sink Only Positive True Logic Pin numbers in parenthesis are for the D suffix SOIC-14 package. Figure 16. Representative Block Diagram Capacitor CT Latch “Set" Input Output/ Compensation Current Sense Input Latch “Reset" Input Output Large RT/Small CT Small RT/Large CT Figure 17. Timing Diagram http://onsemi.com 8

UC3844B, UC3845B, UC2844B, UC2845B Undervoltage Lockout designer added flexibility in tailoring the drive voltage Two undervoltage lockout comparators have been independent of V . A Zener clamp is typically connected CC incorporated to guarantee that the IC is fully functional to this input when driving power MOSFETs in systems before the output stage is enabled. The positive power where V is greater than 20 V. Figure 23 shows proper CC supply terminal (VCC) and the reference output (Vref) are power and control ground connections in a current−sensing each monitored by separate comparators. Each has built−in power MOSFET application. hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The V comparator Reference CC upper and lower thresholds are 16 V/10 V for the UCX844B, The 5.0 V bandgap reference is trimmed to ±1.0% and 8.4 V/7.6 V for the UCX845B. The Vref comparator tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the upper and lower thresholds are 3.6 V/3.4 V. The large UC384XB. Its primary purpose is to supply charging current hysteresis and low startup current of the UCX844B makes to the oscillator timing capacitor. The reference has it ideally suited in off−line converter applications where short−circuit protection and is capable of providing in efficient bootstrap startup techniques are required excess of 20 mA for powering additional control system circuitry. (Figure 30). The UCX845B is intended for lower voltage dc−dc converter applications. A 36 V Zener is connected as Design Considerations a shunt regulator from V to ground. Its purpose is to CC Do not attempt to construct the converter on protect the IC from excessive voltage that can occur during wire−wrap or plug−in prototype boards. High frequency system startup. The minimum operating voltage for the circuit layout techniques are imperative to prevent UCX844B is 11 V and 8.2 V for the UCX845B. pulse−width jitter. This is usually caused by excessive noise pick−up imposed on the Current Sense or Voltage Feedback Output inputs. Noise immunity can be improved by lowering circuit These devices contain a single totem pole output stage that impedances at these points. The printed circuit layout should was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current contain a ground plane with low−current signal and high−current switch and output grounds returning on and has a typical rise and fall time of 50 ns with a 1.0 nF load. separate paths back to the input filter capacitor. Ceramic Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout bypass capacitors (0.1 (cid:2)F) connected directly to VCC, VC, is active. This characteristic eliminates the need for an and Vref may be required depending upon circuit layout. external pulldown resistor. This provides a low impedance path for filtering the high The SOIC−14 surface mount package provides separate frequency noise. All high current loops should be kept as pins for V (output supply) and Power Ground. Proper short as possible using heavy copper runs to minimize C implementation will significantly reduce the level of radiated EMI. The Error Amp compensation circuitry and switching transient noise imposed on the control circuitry. the converter output voltage divider should be located close This becomes particularly useful when reducing the I to the IC and as far as possible from the power switch and pk(max) clamp level. The separate V supply input allows the other noise−generating components. C Vref 8(14) R 8(14) R Bias RA Bias RT R 8 4 R RB 5.0k 6 3 Osc Osc 0.01 CT 4(7) + 5 5.0k RQ 7 4(7) + 2R 2 S 2R ExStyenrncal 47 2(3) EA R C 5.0k MC1455 2(3) EA R Input 1 1(1) 1(1) 5(9) To Additional 5(9) UCX84XBs Tthhee b doitotodme cslaidme po fis C rTe qtou igreod m ifo trhee t hSaynn c3 0a0m mpliVtu bdeel oisw l agrrgoeu nedn.ough to cause f(cid:3)(cid:4)(cid:3)(RA(cid:3)(cid:5)1.4(cid:3)42RB)C D(max)(cid:3)(cid:4)(cid:3)RA(cid:3)(cid:5)RA(cid:3)2RB Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and Multi−Unit Synchronization http://onsemi.com 9

UC3844B, UC3845B, UC2844B, UC2845B VCC Vin 7(12) 5.0V Ref 5.0V Ref 8(14) R 8(14) R + Bias Bias - R + R + 7(11) - - Osc Osc Q1 4(7) + T 4(7) + VClamp T 6(10) 1.0mA S R2 1.0 mA S Q 2(3) 2R R Q 2(3) EA 2RR 1.0V ComRp/Latch 5(8) 1.0M EA R 1.0V 1(1) 1(1) 3(5) RS C R1 5(9) tSoft-Start ≈ 3600C in (cid:2)F 5(9) (cid:7) (cid:8) VClamp ≈ (cid:7)RR211.(cid:5)671(cid:8)+ 0.33x10-3 R1R(cid:5)1R2R2 WIphk(emrea:x 0)(cid:3) ≤(cid:6) V(cid:3)CVlaCmpla ≤m p1.0 V RS Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit VCC Vin VCC Vin 7(12) (12) VPin(cid:3)5(cid:3)(cid:6)(cid:3)rRDSM(cid:3)(Iopnk(cid:3))r(cid:3)D(cid:5)S((cid:3)oRnS) If: SENSEFET = MTP10N10M RS = 200 5.0V Ref 5.0V Ref Then:(cid:3)VPin(cid:3)5(cid:3)(cid:6)(cid:3)0.075(cid:3)Ipk 8(14) R + + Bias - - D SENSEFET R + 7(11) + (11) - - S Q1 G Osc K 4(7) + 1.0 mA VClamp ST 6(10) ST (10) M Q Q R2 2(3) EA 2RR 1.0V ComRp/Latch 5(8) RComp/Latch (8) Power Ground: 3(5) (5) RS To Input Source 1(1) RS 1/4 W Return R1 MPSA63 5(9) Control Circuitry Ground: To Pin (9) 1.67 VClamp ≈ (cid:7)RR21(cid:5)1(cid:8) Where: 0 ≤ VClamp ≤ 1.0 V Vofi ratu SalElyN lSosEsFleEsTs(cid:2) cu prroewnet rs eswnsiticnhg. cFaonr bpero apcehr ioepveedra wtioitnh dthueri nimg polevemre-cnutarrtieonnt (cid:10) (cid:11) conditions, a reduction of the Ipk(max) clamp level must be implemented. tSoftStart(cid:4)(cid:9)In 1(cid:9)(cid:3)3VCVlCamp (cid:3)CR1R1(cid:5)(cid:3)R2R2 Ipk(max)(cid:3)(cid:6)(cid:3)VCRlaSmp Refer to Figures 20 and 22. Figure 22. Adjustable Buffered Reduction of Figure 23. Current Sensing Power MOSFET Clamp Level with Soft−Start http://onsemi.com 10

UC3844B, UC3845B, UC2844B, UC2845B VCC Vin 7(12) 5.0V Ref + - + 7(11) The addition of the RC filter will eliminate - instability caused by the leading edge spike Q1 on the current waveform. T 6(10) S 5(8) Q R Comp/Latch 3(5) R C RS Figure 24. Current Waveform Spike Suppression VCC Vin IB 7(12) + Vin 0 Base Charge 5.0V Ref - Removal + - C1 + 7(11) - Rg Q1 Q1 6(10) T 6(10) S Q 5(8) R 5(8) Comp/Latch 3(5) RS 3(5) RS Series gate resistor Rg will damp any high frequency The totem pole output can furnish negative base current parasitic oscillations caused by the MOSFET input for enhanced transistor turn-off, with the addition of capacitance and any series wiring inductance in the capacitor C1. gate-source circuit. Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive http://onsemi.com 11

UC3844B, UC3845B, UC2844B, UC2845B VCC Vin 7(12) Isolation Boundary 5.0V Ref + - VGS Waveforms + 7(11) + + Q1 - 0 0 - - T 6(10) 50% DC 25% DC S 5(8) (cid:7) (cid:8) Q V(Pin(cid:3)1) - 1.4 NS ComRp/Latch 3(5) R Ipk = 3 RS Np C RS NS NP Figure 27. Isolated MOSFET Drive 8(14) R Bias R Osc 4(7) + 1.0 mA 2R 2(3) R EA 1(1) MCR 2N 101 3905 5(9) 2N 3903 The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Figure 28. Latched Shutdown From VO 2.5V From VO 2.5V + + Ri 2(3) 1.0mA 2R Rp Ri 2(3) 1.0mA 2R R R Rd Cf Rf EA Cp Rd Cf Rf EA 1(1) 1(1) Rf ≥ 8.8k 5(9) 5(9) Error Amp compensation circuit for stabilizing any current mode topology except Error Amp compensation circuit for stabilizing current mode boost for boost and flyback converters operating with continuous inductor current. and flyback topologies operating with continuous inductor current. Figure 29. Error Amplifier Compensation http://onsemi.com 12

UC3844B, UC3845B, UC2844B, UC2845B L1 MBR1635 4.7(cid:5) MDA + 250 4.7k 3300 T1 + + 5.0V/4.0A 2200 1000 202 pF 56k 115 Vac 5.0V RTN MUR110 1N4935 1N4935 12V/0.3A + L2 + 7(12) + 68 + 1000 10 100 47 ±12V RTN 5.0V Ref 1000 10 0.01 8(14) + 1N4937 + + R - -12V/0.3A MUR110 33k Bias L3 R 7(11) + - 680pF2.7k 1N4937 22 Osc 1.0nF 4(7) + T 6(10) MTP 1N5819 4N50 18k S 2(3) Q R 5(8) 100 EA 4.7k pF 150k Comp/Latch 1.0k 3(5) 1(1) 0.5 470pF 5(9) T1 -Primary: 45 Turns #26 AWG L1- 15 (cid:2)H at 5.0 A, Coilcraft Z7156 Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound L2, L3- 25 (cid:2)H at 5.0 A, Coilcraft Z7157 Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin: Ferroxcube EC35PCB1 Gap: ≈ 0.10" for a primary inductance of 1.0 mH Figure 30. 7 W Off−Line Flyback Regulator Test Conditions Results Line Regulation: 5.0 V Vin = 95 Vac to 130 Vac (cid:4) = 50 mV or ±0.5% ±12V (cid:4) = 24 mV or ±0.1% Load Regulation: 5.0 V Vin = 115 Vac, Iout = 1.0 A to 4.0 A (cid:4) = 300 mV or ±3.0% ±12V Vin = 115 Vac, Iout = 100 mA to 300 mA (cid:4) = 60 mV or ±0.25% Output Ripple: 5.0 V Vin = 115 Vac 40 mVpp ±12V 80 mVpp Efficiency Vin = 115 Vac 70% All outputs are at nominal load currents unless otherwise noted. http://onsemi.com 13

UC3844B, UC3845B, UC2844B, UC2845B Output Load Regulation Vin = 15V (Open Loop Configuration) UC3845B 7(12) + IO (mA) VO (V) 47 0 29.9 34V Reference 2 28.8 Regulator 9 28.3 10k8(14) 2.5V R Internal UVVCLCO +- 7(11) 1N5819 18 27.4 Bias 36 24.4 R 3.6V -+ Vref 15 10 UVLO 6(10) 1N5819 Osc VO ≈ 2 (Vin) 1.0nF 4(7) + T + + 0.5mA2R S 5(8) CPionn 2n efocrt to R2 47 2(3) Q closed loop Error R 1.0V R PLaWtcMh 3(5) operation. Amplifier Current Sense 1(1) R1 Comparator (cid:7) (cid:8) 5(9) VO = 2.5 RR21(cid:5)1 The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown. Figure 31. Step−Up Charge Pump Converter Vin = 15V Output Load Regulation UC3845B 7(12) + IO (mA) VO (V) 47 34V 0 −14.4 Reference 2 −13.2 Regulator 10k8(14) 2.5V R Internal UVVCLCO +- 7(11) 198 −−1112..75 Bias 32 −10.6 R 3.6V -+ Vref 15 10 UVLO 6(10) 1N5819 Osc VO ≈ -Vin 1.0nF 4(7) + T 1N5819 + 0.5mA S 5(8) 47 2R 2(3) Q R PWM Error R 1.0V Latch 3(5) Amplifier Current Sense 1(1) Comparator 5(9) The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. Figure 32. Voltage−Inverting Charge Pump Converter http://onsemi.com 14

UC3844B, UC3845B, UC2844B, UC2845B ORDERING INFORMATION Device Operating Temperature Range Package Shipping† UC384xBDG SOIC−14 55 Units/Rail (Pb−Free) UC384xBDR2G SOIC−14 2500 Tape & Reel (Pb−Free) UC384xBD1G SOIC−8 98 Units/Rail TA = 0° to +70°C (Pb−Free) UC384xBD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC384xBNG PDIP−8 50 Units/Rail (Pb−Free) UC284xBDG SOIC−14 55 Units/Rail (Pb−Free) UC284xBDR2G SOIC−14 2500 Tape & Reel (Pb−Free) UC284xBD1G SOIC−8 98 Units/Rail TA = −25° to +85°C (Pb−Free) UC284xBD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC284xBNG PDIP−8 50 Units/Rail (Pb−Free) UC384xBVDG SOIC−14 55 Units/Rail (Pb−Free) UC384xBVDR2G SOIC−14 2500 Tape & Reel (Pb−Free) UC384xBVD1G SOIC−8 98 Units/Rail TA = −40° to +105°C (Pb−Free) UC384xBVD1R2G SOIC−8 2500 Tape & Reel (Pb−Free) UC384xBVNG PDIP−8 50 Units/Rail (Pb−Free) NCV3845BVD1R2G* SOIC−8 2500 Tape & Reel TA = −40° to +125°C (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. x indicates either a 4 or 5 to define specific device part numbers. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 15

UC3844B, UC3845B, UC2844B, UC2845B MARKING DIAGRAMS PDIP−8 N SUFFIX CASE 626 8 8 8 UC384xBN UC384xBVN UC284xBN AWL AWL AWL YYWWG YYWWG YYWWG 1 1 1 SOIC−14 D SUFFIX CASE 751A 14 14 14 UC384xBDG UC384xBVDG UC284xBDG AWLYWW AWLYWW AWLYWW 1 1 1 SOIC−8 D1 SUFFIX CASE 751 8 8 8 384xB 384xB 284xB ALYW ALYWV ALYW (cid:3) (cid:3) (cid:3) 1 1 1 x = 4 or 5 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or (cid:3) = Pb−Free Package http://onsemi.com 16

UC3844B, UC3845B, UC2844B, UC2845B PACKAGE DIMENSIONS PDIP−8 N SUFFIX CASE 626−05 ISSUE N D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. E 2. CONTROLLING DIMENSION: INCHES. H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 8 5 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE E1 NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM 1 4 PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE NOTE 8 c LEADS UNCONSTRAINED. b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE END VIEW LEADS, WHERE THE LEADS EXIT THE BODY. TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). NOTE 5 INCHES MILLIMETERS A2 DIM MIN MAX MIN MAX e/2 A A −−−− 0.210 −−− 5.33 NOTE 3 A1 0.015 −−−− 0.38 −−− A2 0.115 0.195 2.92 4.95 L b 0.014 0.022 0.35 0.56 b2 0.060 TYP 1.52 TYP C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 SEATING A1 PLANE D1 0.005 −−−− 0.13 −−− E 0.300 0.325 7.62 8.26 C M E1 0.240 0.280 6.10 7.11 D1 e 0.100 BSC 2.54 BSC e eB eB −−−− 0.430 −−− 10.92 L 0.115 0.150 2.92 3.81 8Xb END VIEW M −−−− 10° −−− 10° 0.010 M C A M B M NOTE 6 SIDE VIEW http://onsemi.com 17

UC3844B, UC3845B, UC2844B, UC2845B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: −X− 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. A 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 8 5 PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL 1 IN EXCESS OF THE D DIMENSION AT −Y− 4 K 6. M75A1X−I0M1U TMH RMUA T7E51R−IA0L6 CAROEN DOIBTSIOONL.ETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES DIM MIN MAX MIN MAX C NX 45(cid:4) A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 SEATING PLANE C 1.35 1.75 0.053 0.069 −Z− D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC 0.10 (0.004) H 0.10 0.25 0.004 0.010 H D M J J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:4) 8 (cid:4) 0 (cid:4) 8 (cid:4) N 0.25 0.50 0.010 0.020 0.25 (0.010)M Z Y S X S S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:7) (cid:8) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 18

UC3844B, UC3845B, UC2844B, UC2845B PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1.DIMENSIONING AND TOLERANCING PER −A− ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 14 8 3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P7 PL 5.DDIAMMEBNASRIO PNR DO TDROUESSIO NNO. TA LINLCOLWUADBELE 0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL 1 7 CONDITION. G MILLIMETERS INCHES RX 45(cid:4) F DIM MIN MAX MIN MAX C A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 −T− D 0.35 0.49 0.014 0.019 SEATING D14 PL K M J GF 0.14.027 BS1C.25 0.001.0650 B0.S0C49 PLANE J 0.19 0.25 0.008 0.009 0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009 M 0 (cid:4) 7 (cid:4) 0 (cid:4) 7 (cid:4) P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 SOLDERING FOOTPRINT 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS SENSEFET is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com UC3844B/D 19