UC3842A, UC3843A, UC2842A, UC2843A High Performance Current Mode Controllers The UC3842A, UC3843A series of high performance fixed frequency current mode controllers are specifically designed for http://onsemi.com off−line and DC−to−DC converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle PDIP−8 control, a temperature compensated reference, high gain error N SUFFIX amplifier, current sensing comparator, and a high current totem pole CASE 626 8 output ideally suited for driving a power MOSFET. 1 Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle−by−cycle current limiting, programmable output deadtime, and a latch for single SOIC−14 D SUFFIX pulse metering. 14 CASE 751A These devices are available in an 8−pin dual−in−line plastic package 1 as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14 package has separate power and ground pins for the totem pole output stage. SOIC−8 The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), 8 D1 SUFFIX ideally suited for off−line converters. The UCX843A is tailored for 1 CASE 751 lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). Features PIN CONNECTIONS • Trimmed Oscillator Discharge Current for Precise Duty Cycle Compensation 1 8 Vref Control • Current Mode Operation to 500 kHz Voltage Feedback 2 7 VCC • Current Sense 3 6 Output Automatic Feed Forward Compensation • Latching PWM for Cycle−By−Cycle Current Limiting RT/CT 4 5 GND • Internally Trimmed Reference with Undervoltage Lockout (Top View) • High Current Totem Pole Output • Undervoltage Lockout with Hysteresis Compensation 1 14 Vref • Low Startup and Operating Current NC 2 13 NC • Direct Interface with ON Semiconductor SENSEFET™ Products Voltage Feedback 3 12 VCC • Pb−Free Packages are Available NC 4 11 VC Current Sense 5 10 Output NC 6 9 GND RT/CT 7 8 Power Ground (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 16 of this data sheet. © Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: November, 2005 − Rev. 8 UC3842A/D

UC3842A, UC3843A, UC2842A, UC2843A VCC 7(12) Vref 5.0V VCC Undervoltage Reference 8(14) R Lockout R UndeVrvreofltage VC Lockout 7(11) RTCT Output Oscillator 4(7) Latching 6(10) Voltage PWM Power Feedback + Ground Input − 5(8) 2(3) Error Current Output Amplifier Sense Compensation 3(5)Input 1(1) GND 5(9) Pin numbers in parenthesis are for the D suffix SOIC−14 package. Figure 1. Simplified Block Diagram MAXIMUM RATINGS Rating Symbol Value Unit Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, VC 30 V Total Power Supply and Zener Current (ICC + IZ) 30 mA Output Current, Source or Sink (Note 1) IO 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 (cid:2)J Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V Error Amp Output Sink Current IO 10 mA Power Dissipation and Thermal Characteristics D Suffix, Plastic Package Maximum Power Dissipation @ TA = 25°C PD 862 mW Thermal Resistance, Junction−to−Air R(cid:3)JA 145 °C/W N Suffix, Plastic Package Maximum Power Dissipation @ TA = 25°C PD 1.25 W Thermal Resistance, Junction−to−Air R(cid:3)JA 100 °C/W Operating Junction Temperature TJ + 150 °C Operating Ambient Temperature TA °C UC3842A, UC3843A 0 to + 70 UC2842A, UC2843A − 25 to + 85 Storage Temperature Range Tstg − 65 to + 150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum Package power dissipation limits must be observed. http://onsemi.com 2

UC3842A, UC3843A, UC2842A, UC2843A ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3], unless otherwise noted.) UC284XA UC384XA Characteristics Symbol Min Typ Max Min Typ Max Unit REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV Temperature Stability TS − 0.2 − − 0.2 − mV/°C Total Output Variation over Line, Load, Temperature Vref 4.9 − 5.1 4.82 − 5.18 V Output Noise Voltage (f = 10 Hz to 10 kHz, Vn − 50 − − 50 − (cid:2)V TJ = 25°C) Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV Output Short Circuit Current ISC − 30 − 85 − 180 − 30 − 85 − 180 mA OSCILLATOR SECTION Frequency fosc kHz TJ = 25°C 47 52 57 47 52 57 TA = Tlow to Thigh 46 − 60 46 − 60 Frequency Change with Voltage (VCC = 12 V to 25 V) (cid:4)fosc/(cid:4)V − 0.2 1.0 − 0.2 1.0 % Frequency Change with Temperature (cid:4)fosc/(cid:4)T − 5.0 − − 5.0 − % TA = Tlow to Thigh Oscillator Voltage Swing (Peak−to−Peak) Vosc − 1.6 − − 1.6 − V Discharge Current (Vosc = 2.0 V) Idischg mA TJ = 25°C 7.5 8.4 9.3 7.5 8.4 9.3 TA = Tlow to Thigh 7.2 − 9.5 7.2 − 9.5 ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V Input Bias Current (VFB = 2.7 V) IIB − −0.1 −1.0 − −0.1 −2.0 (cid:2)A Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB Output Current mA Sink (VO = 1.1 V, VFB = 2.7 V) ISink 2.0 12 − 2.0 12 − Source (VO = 5.0 V, VFB = 2.3 V) ISource −0.5 −1.0 − −0.5 −1.0 − Output Voltage Swing V High State (RL = 15 k to ground, VFB = 2.3 V) VOH 5.0 6.2 − 5.0 6.2 − Low State (RL = 15 k to Vref, VFB = 2.7 V) VOL − 0.8 1.1 − 0.8 1.1 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow= 0°C for UC3842A, UC3843A Thigh= +70°C for UC3842A, UC3843A −25°C for UC2842A, UC2843A +85°C for UC2842A, UC2843A http://onsemi.com 3

UC3842A, UC3843A, UC2842A, UC2843A ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 4], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 5], unless otherwise noted.) UC284XA UC384XA Characteristics Symbol Min Typ Max Min Typ Max Unit CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 6 & 7) AV 2.85 3.0 3.15 2.85 3.0 3.15 V/V Maximum Current Sense Input Threshold (Note 6) Vth 0.9 1.0 1.1 0.9 1.0 1.1 V Power Supply Rejection Ratio PSRR dB VCC = 12 to 25 V (Note 6) − 70 − − 70 − Input Bias Current IIB − −2.0 −10 − −2.0 −10 (cid:2)A Propagation Delay (Current Sense Input to Output) tPLH(in/out) − 150 300 − 150 300 ns OUTPUT SECTION Output Voltage V Low State (ISink = 20 mA) VOL − 0.1 0.4 − 0.1 0.4 Low State (ISink = 200 mA) − 1.6 2.2 − 1.6 2.2 High State (ISink = 20 mA) VOH 13 13.5 − 13 13.5 − High State (ISink = 200 mA) 12 13.4 − 12 13.4 − Output Voltage with UVLO Activated VOL(UVLO) V VCC = 6.0 V, ISink = 1.0 mA − 0.1 1.1 − 0.1 1.1 Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns UNDERVOLTAGE LOCKOUT SECTION Startup Threshold Vth V UCX842A 15 16 17 14.5 16 17.5 UCX843A 7.8 8.4 9.0 7.8 8.4 9.0 Minimum Operating Voltage After Turn−On VCC(min) V UCX842A 9.0 10 11 8.5 10 11.5 UCX843A 7.0 7.6 8.2 7.0 7.6 8.2 PWM SECTION Duty Cycle % Maximum DCmax 94 96 − 94 96 − Minimum DCmin − − 0 − − 0 TOTAL DEVICE Power Supply Current (Note 4) ICC mA Startup: (VCC = 6.5 V for UCX843A, − 0.5 1.0 − 0.5 1.0 (VCC = 14 V for UCX842A) Operating − 12 17 − 12 17 Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V 4. Adjust VCC above the Startup threshold before setting to 15 V. 5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow= 0°C for UC3842A, UC3843A Thigh= +70°C for UC3842A, UC3843A −25°C for UC2842A, UC2843A +85°C for UC2842A, UC2843A 6. This parameter is measured at the latch trip point with VFB = 0 V. (cid:4)V Output Compensation 7. Comparator gain is defined as: AV (cid:4)V Current Sense Input http://onsemi.com 4

UC3842A, UC3843A, UC2842A, UC2843A 80 100 E 50 DTIM50 VTAC C= =2 51°5C V Ω) EA R (k 20 T D20 O U T P S T ESI 8.0 OU10 R T NG 5.0 CEN5.0 MI R R, TIT2.0 VTAC C= =2 51°5C V % DT, PE2.0 0.8 1.0 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M fOSC, OSCILLATOR FREQUENCY (Hz) fOSC, OSCILLATOR FREQUENCY (Hz) Figure 2. Timing Resistor versus Figure 3. Output Deadtime versus Oscillator Frequency Oscillator Frequency 9.0 %)100 ENT (mA) 8.5 VVCOCS C= =1 52 .V0 V Y CYCLE ( 90 VCTACT C== =23 5.13°5 Cn VF URR DUT 80 Idischg = 7.2 mA C T RGE 8.0 UTPU 70 A O CH M S U 60 DI M , dischg7.5 , MAXIax50 Idischg = 9.5 mA I m 7.0 D 40 −55 −25 0 25 50 75 100 125 800 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k TA, AMBIENT TEMPERATURE (°C) RT, TIMING RESISTOR ((cid:5)) Figure 4. Oscillator Discharge Current Figure 5. Maximum Output Duty Cycle versus Temperature versus Timing Resistor VCC = 15 V VCC = 15 V 2.55 V AV = −1.0 3.0 V AV = −1.0 TA = 25°C TA = 25°C 2.5 V mV/DIV 2.5 V mV/DIV 20 00 2 2.45 V 2.0 V 0.5 (cid:2)s/DIV 0.1 (cid:2)s/DIV Figure 6. Error Amp Small Signal Figure 7. Error Amp Large Signal Transient Response Transient Response http://onsemi.com 5

UC3842A, UC3843A, UC2842A, UC2843A , OPEN LOOP VOLTAGE GAIN (dB)L102468000000 Gain VVRTACOL C === = 212 501.0°05P C VKhV atos e4.0 V 0369110002500φ, EXCESS PHASE (DEGREES) RRENT SENSE INPUT THRESHOLD (V000011......246802 VCC = 1T5A V=T 1A2 =5 °2C5°C TA = −55°C O U V C A−(cid:2)20 180 , h 0 10 100 1.0 k 10 k 100 k 1.0 M 10 M Vt 0 2.0 4.0 6.0 8.0 f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (V) Figure 8. Error Amp Open Loop Gain and Figure 9. Current Sense Input Threshold Phase versus Frequency versus Error Amp Output Voltage A) mV) 0 T (m110 GE ( VCC = 15 V REN GE CHAN−−48..00 CUIT CUR 90 VRCL C≤ = 0 .115 (cid:5) V E VOLTA−12 ORT CIR C H N S FERE−16 TA = 125°C TA = 55°C NCE 70 E E , Ref−20 TA = 25°C EFER Vr R Δ −24 , C50 0 20 40 60 80 100 120 IS −55 −25 0 25 50 75 100 125 Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C) Figure 10. Reference Voltage Change Figure 11. Reference Short Circuit Current versus Source Current versus Temperature V) V) DI DI E (2.0 mV/ VITOAC =C= 1=2. 501° 5mC VA to 20 mA E (2.0 mV/ VTAC C= =2 51°2C V to 25 V G G N N A A H H C C E E G G A A OLT OLT V V T T U U P P T T U U O O , , O O V V Δ 2.0 ms/DIV Δ 2.0 ms/DIV Figure 12. Reference Load Regulation Figure 13. Reference Line Regulation http://onsemi.com 6

UC3842A, UC3843A, UC2842A, UC2843A V) 0 GE ( VCC S(Loouarcde t oS aGturorautniodn) 80 (cid:2)VsC PCu =ls 1e5d VLoad VCC = 15 V VOLTA−−21..00 TA = 25°C 120 Hz Rate 90% CTAL == 215.0° CnF ON TA = −55°C TI A R U T A 3.0 S UT TA = −55°C UTP 2.0 TA = 25°C 10% O , 1.0 Sink Saturation Vsat (Load to VCC) GND 0 0 200 400 600 800 50 ns/DIV IO, OUTPUT LOAD CURRENT (mA) Figure 14. Output Saturation Voltage Figure 15. Output Waveform versus Load Current E G A T 25 L VO VCC = 30 V PUT CTAL == 2155° pCF DIV mA)20 OUT 0 V/ NT ( , VO 2 URRE15 C ENT PPLY 10 RT = 10 k RR V SU A A CT = 3.3 nF PPLY CU 00 mA/DI , ICC 5 UCX843 UCX842 V TISAFe B=n =s2e 50 =° VC0 V U 1 S 0 , CC 100 ns/DIV 0 10 20 30 40 I VCC , SUPPLY VOLTAGE Figure 16. Output Cross Conduction Figure 17. Supply Current versus Supply Voltage http://onsemi.com 7

UC3842A, UC3843A, UC2842A, UC2843A VCC Vin VCC 7(12) 36V Vref Reference + 8(14) R Internal Regulator UVVCLCO − + − 2.5V Bias + VC RT R 3.6V + − Vref 7(11) − UVLO Output Q1 Oscillator 4(7) T Q 6(10) CT + 1.0mA S Power Ground + Q Voltage Feedback − 2R +− R PWM 5(8) Input 2(3) Latch Error R 1.0V Current Sense Input Output Amplifier Compensation Current Sense 3(5) 1(1) Comparator RS GND 5(9) + Sink Only = − Positive True Logic Pin numbers in parenthesis are for the D suffix SOIC−14 package. Figure 18. Representative Block Diagram Capacitor CT Latch ‘‘Set’’ Input Output/ Compensation Current Sense Input Latch ‘‘Reset’’ Input Output Large RT/Small CT Small RT/Large CT Figure 19. Timing Diagram http://onsemi.com 8

UC3842A, UC3843A, UC2842A, UC2843A OPERATING DESCRIPTION The UC3842A, UC3843A series are high performance, is removed, or at the beginning of a soft−start interval fixed frequency, current mode controllers. They are (Figures 24, 25). The Error Amp minimum feedback specifically designed for Off−Line and DC−to−DC resistance is limited by the amplifier’s source current converter applications offering the designer a cost effective (0.5 mA) and the required output voltage (V ) to reach the OH solution with minimal external components. A comparator’s 1.0 V clamp level: representative block diagram is shown in Figure 18. 3.0 (1.0 V) + 1.4 V R ≈ = 8800 (cid:5) f(min) 0.5 mA Oscillator The oscillator frequency is programmed by the values Current Sense Comparator and PWM Latch selected for the timing components R and C . Capacitor C T T T The UC3842A, UC3843A operate as a current mode is charged from the 5.0 V reference through resistor R to T controller, whereby output switch conduction is initiated by approximately 2.8 V and discharged to 1.2 V by an internal the oscillator and terminated when the peak inductor current current sink. During the discharge of C , the oscillator T reaches the threshold level established by the Error generates and internal blanking pulse that holds the center Amplifier Output/Compensation (Pin 1). Thus the error input of the NOR gate high. This causes the Output to be in signal controls the peak inductor current on a a low state, thus producing a controlled amount of output cycle−by−cycle basis. The current Sense Comparator PWM deadtime. Figure 2 shows R versus Oscillator Frequency T Latch configuration used ensures that only a single pulse and Figure 3, Output Deadtime versus Frequency, both for appears at the Output during any given oscillator cycle. The given values of C . Note that many values of R and C will T T T inductor current is converted to a voltage by inserting the give the same oscillator frequency but only one combination ground referenced sense resistor R in series with the source S will yield a specific output deadtime at a given frequency. of output switch Q1. This voltage is monitored by the The oscillator thresholds are temperature compensated, and Current Sense Input (Pin 3) and compared a level derived the discharge current is trimmed and guaranteed to within from the Error Amp Output. The peak inductor current under ±10% at T = 25°C. These internal circuit refinements J normal operating conditions is controlled by the voltage at minimize variations of oscillator frequency and maximum pin 1 where: output duty cycle. The results are shown in Figures 4 and 5. In many noise sensitive applications it may be desirable to I = V(Pin 1) − 1.4 V pk 3 R frequency−lock the converter to an external system clock. S This can be accomplished by applying a clock signal to the Abnormal operating conditions occur when the power circuit shown in Figure 21. For reliable locking, the supply output is overloaded or if output voltage sensing is free−running oscillator frequency should be set about 10% lost. Under these conditions, the Current Sense Comparator less than the clock frequency. A method for multi unit threshold will be internally clamped to 1.0 V. Therefore the synchronization is shown in Figure 22. By tailoring the maximum peak switch current is: clock waveform, accurate Output duty cycle clamping can 1.0 V I = be achieved. pk(max) R S When designing a high power switching regulator it Error Amplifier becomes desirable to reduce the internal clamp voltage in A fully compensated Error Amplifier with access to the order to keep the power dissipation of R to a reasonable inverting input and output is provided. It features a typical S level. A simple method to adjust this voltage is shown in dc voltage gain of 90 dB, and a unity gain bandwidth of Figure 23. The two external diodes are used to compensate 1.0 MHz with 57 degrees of phase margin (Figure 8). The the internal diodes yielding a constant clamp voltage over noninverting input is internally biased at 2.5 V and is not temperature. Erratic operation due to noise pickup can result pinned out. The converter output voltage is typically divided if there is an excessive reduction of the I clamp down and monitored by the inverting input. The maximum pk(max) voltage. input bias current is −2.0 (cid:2)A which can cause an output A narrow spike on the leading edge of the current voltage error that is equal to the product of the input bias waveform can usually be observed and may cause the power current and the equivalent input divider source resistance. supply to exhibit an instability when the output is lightly The Error Amp Output (Pin 1) is provide for external loop loaded. This spike is due to the power transformer compensation (Figure 31). The output voltage is offset by interwinding capacitance and output rectifier recovery time. two diode drops (≈ 1.4 V) and divided by three before it The addition of an RC filter on the Current Sense Input with connects to the inverting input of the Current Sense a time constant that approximates the spike duration will Comparator. This guarantees that no drive pulses appear at usually eliminate the instability; refer to Figure 27. the Output (Pin 6) when Pin 1 is at its lowest state (V ). OL This occurs when the power supply is operating and the load http://onsemi.com 9

UC3842A, UC3843A, UC2842A, UC2843A PIN FUNCTION DESCRIPTION Pin 8−Pin 14−Pin Function Description 1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation. 2 3 Voltage This is the inverting input of the Error Amplifier. It is normally connected to the switching pow- Feedback er supply output through a resistor divider. 3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this infor- mation to terminate the output switch conduction. 4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. 5 − GND This pin is the combined control circuitry and power ground (8−pin package only). 6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. 7 12 VCC This pin is the positive supply of the control IC. 8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. − 8 Power Ground This pin is a separate power ground return (14−pin package only) that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. − 11 VC The Output high state (VOH) is set by the voltage applied to this pin (14−pin package only). With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. − 9 GND This pin is the control circuitry ground return (14−pin package only) and is connected back to the power source ground. − 2,4,6,13 NC No connection (14−pin package only). These pins are not internally connected. Undervoltage Lockout and has a typical rise and fall time of 50 ns with a 1.0 nF load. Two undervoltage lockout comparators have been Additional internal circuitry has been added to keep the incorporated to guarantee that the IC is fully functional Output in a sinking mode whenever an undervoltage lockout before the output stage is enabled. The positive power is active. This characteristic eliminates the need for an supply terminal (VCC) and the reference output (Vref) are external pull−down resistor. each monitored by separate comparators. Each has built−in The SOIC−14 surface mount package provides separate hysteresis to prevent erratic output behavior as their pins for V (output supply) and Power Ground. Proper C respective thresholds are crossed. The VCC comparator implementation will significantly reduce the level of upper and lower thresholds are 16 V/10 V for the UCX842A, switching transient noise imposed on the control circuitry. and 8.4 V/7.6 V for the UCX843A. The Vref comparator This becomes particularly useful when reducing the Ipk(max) upper and lower thresholds are 3.6V/3.4 V. The large clamp level. The separate V supply input allows the C hysteresis and low startup current of the UCX842A makes designer added flexibility in tailoring the drive voltage it ideally suited in off−line converter applications where independent of V . A zener clamp is typically connected CC efficient bootstrap startup techniques are required to this input when driving power MOSFETs in systems (Figure 34). The UCX843A is intended for lower voltage dc where V is greater than 20 V. Figure 26 shows proper CC to dc converter applications. A 36 V zener is connected as power and control ground connections in a current sensing a shunt regulator form VCC to ground. Its purpose is to power MOSFET application. protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the Reference UCX842A is 11 V and 8.2 V for the UCX843A. The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at T = 25°C on the UC284XA, and± 2.0% on the J Output UC384XA. Its primary purpose is to supply charging current These devices contain a single totem pole output stage that to the oscillator timing capacitor. The reference has short was specifically designed for direct drive of power circuit protection and is capable of providing in excess of MOSFETs. It is capable of up to±1.0 A peak drive current 20 mA for powering additional control system circuitry. http://onsemi.com 10

UC3842A, UC3843A, UC2842A, UC2843A DESIGN CONSIDERATIONS Do not attempt to construct the converter on (t3) decreases to ((cid:4)I + (cid:4)I m2/m1) (m2/m1). This perturbation wire−wrap or plug−in prototype boards. High Frequency is multiplied by m .m on each succeeding cycle, alternately 2 1 circuit layout techniques are imperative to prevent pulse increasing and decreasing the inductor current at switch width jitter. This is usually caused by excessive noise turn−on. Several oscillator cycles may be required before pick−up imposed on the Current Sense or Voltage Feedback the inductor current reaches zero causing the process to inputs. Noise immunity can be improved by lowering circuit commence again. If m /m is greater than 1, the converter 2 1 impedances at these points. The printed circuit layout should will be unstable. Figure 20B shows that by adding an contain a ground plane with low−current signal and artificial ramp that is synchronized with the PWM clock to high−current switch and output grounds returning on the control voltage, the (cid:4)I perturbation will decrease to zero separate paths back to the input filter capacitor. Ceramic on succeeding cycles. This compensation ramp (m ) must 3 bypass capacitors (0.1 (cid:2)F) connected directly to V , V , have a slope equal to or slightly greater than m /2 for CC C 2 and V may be required depending upon circuit layout. stability. With m /2 slope compensation, the average ref 2 This provides a low impedance path for filtering the high inductor current follows the control voltage yielding true frequency noise. All high current loops should be kept as current mode operation. The compensating ramp can be short as possible using heavy copper runs to minimize derived from the oscillator and added to either the Voltage radiated EMI. The Error Amp compensation circuitry and Feedback or Current Sense inputs (Figure 33). the converter output voltage divider should be located close to the IC and as far as possible from the power switch and (A) (cid:4)I other noise generating components. Control Voltage Current mode converters can exhibit subharmonic m2 oscillations when operating at a duty cycle greater than 50% m1 winidthep ecnodnetnint uoofu tsh ei nredguucltaotro rsc ucrlroesnetd. −Tlohoips cihnasrtaacbtielirtiyst iciss ICnduurrcetnotr Os(cid:4)ciIl l+at o(cid:4)r IPermmio21d (cid:4) I + (cid:4)Imm21 mm21 and is caused by the simultaneous operating conditions of t0 t1 t2 t3 fixed frequency and peak current detecting. Figure 20A shows the phenomenon graphically. At t , switch 0 (B) conduction begins, causing the inductor current to rise at a Control Voltage m3 slope of m . This slope is a function of the input voltage 1 divided by the inductance. At t , the Current Sense Input 1 (cid:4)I reaches the threshold established by the control voltage. m1 This causes the switch to turn off and the current to decay at m2 Inductor Current a slope of m until the next oscillator cycle. The unstable 2 Oscillator Period condition can be shown if a perturbation is added to the control voltage, resulting in a small (cid:4)I (dashed line). With t4 t5 t6 a fixed oscillator period, the current decay time is reduced, Figure 20. Continuous Current Waveforms and the minimum current at switch turn−on (t ) is increased 2 by (cid:4)I + (cid:4)I m2/m1. The minimum current at the next cycle http://onsemi.com 11

UC3842A, UC3843A, UC2842A, UC2843A Vref 8(14) R RT R Bias RA 8 4 8(14) R Bias R RB Osc 6 5.0k ESInxyptnuectrnal 0.01 C4T7 42((73)) +− EA+ 2R 52 5.0k +−+− RSQ 73 4(7) +− +Osc R C 5.0k MC1455 2(3) EA 2R R 1(1) 1 1(1) 5(9) To 5(9) Tcahues dei othdee bcolatmtomp i ss irdeeq oufir CedT itfo t hgeo Smyonrce a tmhapnli t3u0d0e misV la brgeelo ewn goruoguhn dto. f = (RA 1+. 424RB)C Dmax = RA R+ B2RB AUdCdXit8io4nXaAl’s Figure 21. External Clock Synchronization Figure 22. External Duty Cycle Clamp and Multi Unit Synchronization VCC Vin 7(12) + 5.0Vref − + 8(14) R Bias + − R + − 7(11) 5.0Vref − Q1 8(14) R Osc 4(7) + VClamp 6(10) R Bias + +− 1.0mA S R22(3) +− EA 2RR −+ CoRmpQ/Latch 5(8) 4(7) +Osc − 1.0V 3(5) 1.0mA S R11(1) 5(9) RS 2(3) +− EA 2R −+ RQ 1.0M R 1.0V VClamp = RR211.67+ 1 + 0.33 x 10 − 3 RR11 + R R22 Ipk(mWaxh)e =re: 0 ≤V CVRlCaSlmampp ≤ 1.0 V C 1(t1S)oft−Start (cid:2) 3600C in (cid:2)F 5(9) Figure 23. Adjustable Reduction of Clamp Level Figure 24. Soft−Start Circuit 7(12) VCC Vin (12) VCC Vin VPin 5 = RrSD M Ip(okn )r +D SR(oSn) If: SENSEFET = MTP10N10M 8(14) R 5.0Vref +− + 5.0V+ref +− +− D SENSEFETThen: VpiRn S5 == 200.0075 Ipk R Bias + +− − + − (11) 7(11) − S − Q1 4(7) +Osc VClamp 6(10) S (10) G M K 2(3) +− EA 1.0mA2RR −+ ComRSpQ/Latch 5(8) −+ ComRpQ/Latch (8) TPoo Iwnpeur tG Sroouurncde R2 1.0V 3(5) (5) RS Return 1(1) RS Control CIrcuitry 1/4 W C MPSA63 5(9) Ground: R1 To Pin (9) 1.67 VClamp = R2 + 1 Ipk(max) = VCRlaSmp Where: 0 ≤ VClamp ≤ 1.0 V Virtually lossless current sensing can be achieved with the implementation of a R1 tSoftstart = − In 1 − 3VVClCamp C RR11 + R R22 SreEdNucStEioFnE oTf thpeo wIpek(rm sawx) itcclahm. Fp oler vperl ompuesr t obpee irmaptiolenm deunrteindg. Roevfeerr ctou rFriegnutr ecso n2d3 itaionnds 2, 5a. Figure 25. Adjustable Buffered Reduction of Figure 26. Current Sensing Power MOSFET Clamp Level with Soft−Start http://onsemi.com 12

UC3842A, UC3843A, UC2842A, UC2843A VCC Vin 7(12) VCC Vin 7(12) + 5.0Vref +− + 5.0Vref − + + − +− − − + + 7(11) − 7(11) Q1 − Rg Q1 6(10) 6(10) S −+ RSQ 5(8) −+ RQ 5(8) Comp/Latch R Comp/Latch 3(5) 3(5) C RS RS Series gate resistor Rg will damp any high frequency parasitic oscillations The addition of the RC filter will eliminate instability caused by the leading caused by the MOSFET input capacitance and any series wiring inductance edge spike on the current waveform. in the gate−source circuit. Figure 27. Current Waveform Spike Suppression Figure 28. MOSFET Parasitic Oscillations IB Vin + VCC Vin 7(12) 0 Base Charge − RemovalC1 5.0Vref +− + BIsooulnadtioanry Q1 + +− − 7(11) Q1 +ÉÉVGS Wav+efoÉrms 6(1) − 0 É 0 ÉÉÉ − − 6(1) 50% DC 25% DC 5(8) −+ ComRSpQ/Latch 5(8) R Ipk = ÉV(pin 31 )R −S 1.4 NNPS 3(5) RS 3(5) C RS NS Np The totem−pole output can furnish negative base current for enhanced transistor turn−off, with the addition of capacitor C1. Figure 29. Bipolar Transistor Drive Figure 30. Isolated MOSFET Drive From VO 2.5V + Ri 2(3) 1.0mA + 8(14) R Bias Rd CI Rf − EA 2RR R 1(1) Osc 5(9) 4(7) + 1.0mA Error Amp compensation circuit for stabilizing any current−mode topology except + − for boost and flyback converters operating with continuous inductor current. 2(3) EA 2R R From VO 1(1) 2.5V + MCR 2N 5(9) Rp Ri 2(3) + 1.0mA 101 3905 − 329N03 Cp Rd CI Rf EA 2RR 1(1) 5(9) The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA(min). Error Amp compensation circuit for stabilizing current−mode boost and flyback The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. topologies operating with continuous inductor current. Figure 31. Latched Shutdown Figure 32. Error Amplifier Compensation http://onsemi.com 13

UC3842A, UC3843A, UC2842A, UC2843A VCC Vin 7(12) 8(14) + 5.0Vref − R + RT Bias − MPS3904 + R + − 7(11) RSlope 4(7) − Osc From VO CT + −m 6(10) Ri 2(3) +− EA 1.0mA 2R +− RS Q 5(8) Rd Cf Rf R 1.0V Comp/Latch m 3(5) 1(1) RS −3.0 m 5(9) The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. Figure 33. Slope Compensation L1 4.7(cid:5) M2D02A + 250 4.7k 3300pF T1 MBR1635+ + 5.0V/4.0A 115Va 56k 2200 1000 c 5.0V RTN MUR110 1N4935 1N4935 + L2 + 12V/0.3A 1000 10 7(12) + + 68 47 ±12V RTN 100 8(14) 1000 10 5.0Vref +− + + + −12V/0.3A 0.01 1N4937 MUR110 Bias 680pF L3 + + − 10k 7(11) 2.7k 1N4937 4(7) 22(cid:5) Osc 4700pF + 6(10) MTP 18k 4N50 L1 − 15 (cid:2)H at 5.0 A, Coilcraft Z7156. 4.7k 100pF 2150k(3) +− EA +− ComSRp/LQatch 35((58)) 1.0k TT11 −− SPL2eri,cm oLa3nr dy−a: 2r4y55 ± (cid:2)T uH1r2 na sVt :1# 9. 02 T 6Au A,r nCWso G#ilc 3ra0f tA ZW7G15 7. 1(1) 470pF 0.5(cid:5) (cid:3)T1 − (2 strands) Bifiliar Wound T1 − Secondary 5.0 V: 4 Turns (six strands) 5(9) (cid:3)T1 − #26 Hexfiliar Wound T1 − Secondary Feedback: 10 Turns #30 AWG (cid:3)T1 − (2 strands) Bifiliar Wound Figure 34. 27 Watt Off−Line Flyback Regulator T1 − Core: Ferroxcube EC35−3C8 T1 − Bobbin: Ferroxcube EC35PCB1 T1 − Gap≈ 0.01" for a primary inductance of 1.0 mH Test Conditions Results Line Regulation: 5.0 V Vin = 95 Vac to 130 Vac (cid:4) = 50 mV or± 0.5% ± 12 V (cid:4) = 24 mV or± 0.1% Load Regulation: 5.0 V Vin = 115 Vac, Iout = 1.0 A to 4.0 A (cid:4) = 300 mV or± 3.0% ± 12 V Vin = 115 Vac, Iout = 100 mA to 300 mA (cid:4) = 60 mV or± 0.25% Output Ripple: 5.0 V Vin = 115 Vac 40 mVpp ± 12 V 80 mVpp Efficiency Vin = 115 Vac 70% All outputs are at nominal load currents, unless otherwise noted. http://onsemi.com 14

UC3842A, UC3843A, UC2842A, UC2843A ORDERING INFORMATION Device Operating Temperature Range Package Shipping† UC3842AN PDIP−8 UC3842ANG PDIP−8 (Pb−Free) 50 Units / Rail UC3842AN2 PDIP−8 UC3842AN2G PDIP−8 (Pb−Free) UC3842AD SOIC−14 55 Units / Rail UC3842ADG SOIC−14 55 Units / Rail (Pb−Free) UC3842ADR2 SOIC−14 2500 / Tape & Reel UC3842ADR2G SOIC−14 2500 / Tape & Reel (Pb−Free) UC3843AN PDIP−8 UC3843ANG PDIP−8 (Pb−Free) 50 Units / Rail UC3843AN2 PDIP−8 UC3843AN2G TA = 0° to +70°C PDIP−8 (Pb−Free) UC3843AD SOIC−14 55 Units / Rail UC3843ADG SOIC−14 55 Units / Rail (Pb−Free) UC3843ADR2 SOIC−14 2500 / Tape & Reel UC3843ADR2G SOIC−14 2500 / Tape & Reel (Pb−Free) UC3843AD1 SOIC−8 98 Units / Rail UC3843AD1G SOIC−8 98 Units / Rail (Pb−Free) UC3843AD1R2 SOIC−8 UC3843AD1R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel UC3843AD2R2 SOIC−14 UC3843AD2R2G SOIC−14 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 15

UC3842A, UC3843A, UC2842A, UC2843A ORDERING INFORMATION Device Operating Temperature Range Package Shipping† UC2842AN PDIP−8 50 Units / Rail UC2842ANG PDIP−8 50 Units / Rail (Pb−Free) UC2842AD SOIC−14 55 Units / Rail UC2842ADG SOIC−14 55 Units / Rail (Pb−Free) UC2842ADR2 SOIC−14 2500 / Tape & Reel UC2842ADR2G SOIC−14 2500 / Tape & Reel (Pb−Free) UC2843AN PDIP−8 50 Units / Rail UC2843ANG PDIP−8 50 Units / Rail (Pb−Free) TA = −25° to +85°C UC2843AD SOIC−14 55 Units / Rail UC2843ADG SOIC−14 55 Units / Rail (Pb−Free) UC2843ADR2 SOIC−14 2500 / Tape & Reel UC2843ADR2G SOIC−14 2500 / Tape & Reel (Pb−Free) UC2843AD1 SOIC−8 98 Units / Rail UC2843AD1G SOIC−8 98 Units / Rail (Pb−Free) UC2843AD1R2 SOIC−8 2500 / Tape & Reel UC2843AD1R2G SOIC−8 2500 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS PDIP−8 SOIC−14 SOIC−8 N SUFFIX D SUFFIX D1 SUFFIX CASE 626 CASE 751A CASE 751 8 14 8 UCx84xAN UCx84xADG x843 AWL ALYW AWLYWW (cid:2) YYWWG 1 1 1 x = 2 or 3 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or (cid:2) = Pb−Free Package http://onsemi.com 16

UC3842A, UC3843A, UC2842A, UC2843A PACKAGE DIMENSIONS PDIP−8 N SUFFIX CASE 626−05 ISSUE L NOTES: 1.DIMENSION L TO CENTER OF LEAD WHEN 8 5 FORMED PARALLEL. 2.PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). −B− 3.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 1 4 MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.40 10.16 0.370 0.400 F B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 NOTE 2 −A− D 0.38 0.51 0.015 0.020 L F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 C K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC J M −−− 10 (cid:3) −−− 10(cid:3) −T− N 0.76 1.01 0.030 0.040 SEATING N PLANE M D K H G 0.13 (0.005)M T A M B M SOIC−14 D SUFFIX CASE 751A−03 ISSUE G −A− NOTES: 1.DIMENSIONING AND TOLERANCING PER 14 8 ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. −B− P7 PL 4.MPEARX ISMIDUEM. MOLD PROTRUSION 0.15 (0.006) 0.25 (0.010)M B M 5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 1 7 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL G RX 45(cid:3) F CONDITION. C MILLIMETERS INCHES DIM MIN MAX MIN MAX A 8.55 8.75 0.337 0.344 −T− B 3.80 4.00 0.150 0.157 SPELAATNIENG D14 PL K M J CD 10..3355 10..7459 00..005144 00..006189 0.25 (0.010)M T B S A S F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 (cid:3) 7 (cid:3) 0 (cid:3) 7 (cid:3) P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 http://onsemi.com 17

UC3842A, UC3843A, UC2842A, UC2843A PACKAGE DIMENSIONS SOIC−8 D1 SUFFIX CASE 751−07 ISSUE AG −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER A ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE 8 5 MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. B S 0.25 (0.010)M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR 1 PROTRUSION. ALLOWABLE DAMBAR 4 PROTRUSION SHALL BE 0.127 (0.005) TOTAL −Y− K IMNA EXXIMCUESMS M OAFT ETRHIEA LD CDOIMNEDNITSIIOONN. AT 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. G MILLIMETERS INCHES C NX 45(cid:3) DIM MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 SEATING PLANE B 3.80 4.00 0.150 0.157 −Z− C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 0.10 (0.004) G 1.27 BSC 0.050 BSC H D M J H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 (cid:3) 8 (cid:3) 0 (cid:3) 8 (cid:3) 0.25 (0.010)M Z Y S X S N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 4.0 0.275 0.155 0.6 1.270 0.024 0.050 (cid:2) (cid:3) mm SCALE 6:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SENSEFET is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: http://onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Order Literature: http://www.onsemi.com/litorder Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 For additional information, please contact your Email: orderlit@onsemi.com Phone: 81−3−5773−3850 local Sales Representative. http://onsemi.com UC3842A/D 18