UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 ECONOMY HIGH-SPEED PWM CONTROLLER FEATURES DESCRIPTION D PeakCurrentMode,AverageCurrentMode, TheUC28023andUC28025arefixed-frequency orVoltageMode(withFeed-Forward)Control PWM controllers optimized for high-frequency Methods switched-mode power supply applications. The D PracticalOperationUpto1MHz UC28023isasingleoutputPWMforsingle-ended D 50-nsPropagationDelaytoOutput topologies while the UC28025 offers dual alternating outputs for double-ended and full D ±1.5-APeakTotemPoleOutputs bridgetopologies. D 9-Vto30-VNominalOperationalVoltage Range Targetedforcosteffectivesolutionswithminimal external components, UC2802x include an D WideBandwidthErrorAmplifier oscillator,atemperaturecompensatedreference, D FullyLatchedLogicwithDoublePulse a wide band width error amplifier, a high-speed Suppression current-sense comparator and high-current D Pulse-by-PulseCurrentLimiting active-high totem-pole outputs to directly drive D ProgrammableMaximumDutyCycleControl externalMOSFETs. D Under--VoltageLockoutwithHysteresis Protection circuitry includes a current limit D Trimmed5.1-VReferencewithUVLO comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft-start pin D SameFunctionalityasUC3823andUC3825 whichwilldoubleasamaximumdutycycleclamp. The logic is fully latched to provide jitter free APPLICATIONS operation and prohibit multiple pulses at an D Off-LineandDC/DCPowerSupplies output. An undervoltage lockout section with D ConvertersUsingVoltageMode,Peak 800mV of hysteresis assures low start-up current.Duringundervoltagelockout,theoutputs CurrentMode,orAverageCurrentMode arehighimpedance.Particularcarewasgivento ControlMethods minimizing propagation delays through the D Single-EndedorTwo-SwitchTopology comparatorsandlogiccircuitrywhilemaximizing Designs bandwidthandslewrateoftheerroramplifier. Devicesareavailableintheindustrialtemperature range of --40°C to 105°C. Package offerings are 16-pin SOICW (DW), or 16-pin PDIP (N) packages. ORDERING INFORMATION OOUUTTPPUUTT EEXXTTEERRNNAALLCCUURRRREENNTT PACKAGEDDEVICES TTA=TTJ CONFIGURATION LIMITREFERENCE PDIP-16(N) SOICW--16(DW) Single Yes UC28023N UC28023DW --4400°°CCttoo110055°°CC DualAlternating No UC28025N UC28025DW (1) TheDWpackagearealsoavailabletapedandreeled.AddanRsuffixtothedevicetype(i.e.,UC28023DWR(2,000devicesperreel). PRODUCTION DATA information is current as of publication date. Copyright©2005--2010,TexasInstrumentsIncorporated ProductsconformtospecificationsperthetermsofTexasInstruments standardwarranty.Productionprocessingdoesnotnecessarilyinclude testingofallparameters. www.ti.com 1

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerangeunlessotherwisenoted(1) UC28023 UC28025 RATING UNIT Inputvoltagerange, VC,VCC VC,VCC 30 V Outputcurrent,IOUT(DC) OUT OUTA,OUTB ±0.5 A Peakoutputcurrent,pulsed0.5msIOUT(pulsed) OUT OUTA,OUTB ±2.0 A Capacitiveload,CLOAD 200 pF INV,NI,RAMP INV,NI,RAM --0.3Vto7V Analoginputs SS,ILIM/SD SS,ILIM/SD VREF+0.3V, V --0.3V Outputcurrent,IREF VREF VREF 10 Outputcurrent,ICLOCK CLOCK CLOCK --5 Soft-startsinkcurrent,ISINK_SS SS SS 5 mmAA Outputcurrent,IOUT(EA) EAOUT EAOUT 20 Oscillatorchargingcurrent,IOSC_CHG RT RT --5 PowerDissipationatTA=25°C (allpackages) 1 W Operatingjunctiontemperaturerange,TJ --55to150 Storagetemperature,Tstg --65to150 °CC Leadtemperature1,6mm(1/16inch)fromcasefor10seconds,Tsol 300 (1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly, andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”is notimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.Allvoltagesarewithrespectto GND.Allcurrentsarepositiveintoandnegativeoutofthespecifiedterminal. 2 www.ti.com

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 UC28023 UC28023 NPACKAGE DWPACKAGE (TOPVIEW) (TOPVIEW) INV 1 16 VREF INV 1 16 VREF NI 2 15 VCC NI 2 15 VCC EAOUT 3 14 OUT EAOUT 3 14 OUT CLOCK 4 13 VC CLOCK 4 13 VC RT 5 12 PGND RT 5 12 PGND CT 6 11 ILIMREF CT 6 11 ILIMREF RAMP 7 10 GND RAMP 7 10 GND SS 8 9 ILIM/SD SS 8 9 ILIM/SD UC28025 UC28025 DWPACKAGE NPACKAGE (TOPVIEW) (TOPVIEW) INV 1 16 VREF INV 1 16 VREF NI 2 15 VCC NI 2 15 VCC EAOUT 3 14 OUTB EAOUT 3 14 OUTB CLOCK 4 13 VC CLOCK 4 13 VC RT 5 12 PGND RT 5 12 PGND CT 6 11 OUTA CT 6 11 OUTA RAMP 7 10 GND SS 8 9 ILIM/SD RAMP 7 10 GND SS 8 9 ILIM/SD www.ti.com 3

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 ELECTRICAL CHARACTERISTICS TA=--40°Cto105°C,TJ=TA,RT=3.65kΩ,CT=1nF,VCC=15V(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT REFERENCE VREF Referencevoltage TJ=25°C, IREF=1mA 5.05 5.10 5.15 V Lineregulationvoltage 10V≤VCC≤30V 2 15 mmVV Loadregulationvoltage 1mA≤IREF≤10mA 5 15 Temperaturestability(1) T(min)<TA<T(max) 0.2 0.4 mV/°C Totaloutputvoltagevariation(1) Line,load,temperature 4.95 5.25 V Outputnoisevoltage(1) 10Hz<f<10kHz 50 μV Longtermstabilityvoltage(1) TJ=125°C, 1000hours 5 25 mV ISS Shortcircuitcurrent VREF=0V --20 --50 --100 mA OSCILLATOR fOSC Initialaccuracy(1) TJ=25°C 360 400 440 kHz Voltagestability(1) 10V≤VCC≤30V 0.2% 2.0% Temperaturestability(1) T(min)<TA<T(max) 5% Totalvoltagevariation(1) Line,temperature 340 460 kHz VCLOCK_H High-levelclockoutputvoltage 3.9 4.5 VCLOCK_L Low-levelclockoutputvoltage 2.3 2.9 VRAMP(p) Ramppeakvoltage(1) 2.6 2.8 3.0 VV VRAMP(v) Rampvalleyvoltage(1) 0.70 1.00 1.25 VRAMP(v-p) Rampvally-to-peakvoltage(1) 1.6 1.8 2.0 ERRORAMPLIFIER VIN Inputoffsetvoltage 15 mV IBIAS Inputbiascurrent 0.6 3.0 μAA IIN Inputoffsetcurrent 0.1 1.0 AVOL Openloopgain 1V≤VOUT≤4V 60 95 CMRR Commonmoderejectionratio 1.5V≤VCM≤5.5V 75 95 ddBB PSRR Powersupplyrejectionratio 10V≤VCC≤30V 85 110 IOUT(sink) Outputsinkcurrent V(EAOUT)= 1V 1.0 2.5 mmAA IOUT(src) Outputsourcecurrent V(EAOUT)= 4V --0.5 --1.3 VOH High-leveloutputvoltage I(EAOUT)= --0.5mA 4.0 4.7 5.0 VV VOL Low-leveloutputvoltage I(EAOUT)= 1mA 0 0.5 1.0 Unitygainbandwidth(1) 3.0 5.5 MHz Slewrate(1) 6 12 V/μs PWMCOMPARATOR IBIAS RAMPbiascurrent VRAMP= 0V --1 --5 μA UC28023 80% 90% MMaaxxiimmuummdduuttyyccyyccllee UC28025 (2) 40% 45% UC28023 0% MMiinniimmuummdduuttyyccyyccllee UC28025 0% EAOUTzeroDCthreshold VRAMP= 0V 1.10 1.25 1.40 V tDELAY Delaytooutputtime(1) 50 100 ns (1) Ensuredbydesign.Notproductiontested. (2) Testedas80%minimumfortheoscillatorwhichistheequivalentof40%forUC28025. 4 www.ti.com

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 ELECTRICAL CHARACTERISTICS TA=--40°Cto105°C,TJ=TA,RT=3.65kΩ,CT=1nF,VCC=15V(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SOFT-START ICHG Chargecurrent VSS= 0.5V 3 9 20 μA IDISCHG Dischargecurrent VSS= 1.0V 1.0 7.5 mA CURRENTLIMIT/SHUTDOWN ILIMIT Currentlimitbiascurrent 0V<V(ILIM/SD)<4V ±10 μA ILIMIT Offsetvoltage UC28023 15 mV ILIMREF Commonmoderange(1) UC28023 1.00 1.25 Currentlimitthresholdvoltage UC28025 0.9 1.0 1.1 VV Shutdownthresholdvoltage 1.25 1.40 1.55 tDELAY Delaytooutputtime(1) 50 80 ns OUTPUT IOUT= 20mA 0.25 0.40 VVOL LLooww-lleevveelloouuttppuuttvvoollttaaggee IOUT= 200mA 1.2 2.2 VV IOUT= --20mA 13.0 13.5 VVOH HHiigghh-lleevveelloouuttppuuttvvoollttaaggee IOUT= --200mA 12 13 Collectorleakage VC= 30V 100 500 μA Risetime/Falltime(1) CLOAD= 1nF 30 60 ns UNDERVOLTAGELOCKOUT(UVLO) Startthresholdvoltage 8.8 9.2 9.6 VV Hysteresis 0.4 0.8 1.2 SUPPLYCURRENT Start-upcurrent VCC= 8V 1.1 2.0 mmAA ICC Operatingcurrent VINV= VRAMP= VILIM= 0V VINV= 1V 25 35 (1) Ensuredbydesign.Notproductiontested. THERMAL RESISTANCE PACKAGE θJA(°C/W) θJC(°C/W) N(2) 90(2) 45 DW(2) 50--100(2) 27 (2)SpecifiedθJA(junction-to-ambient)isfordevicesmountiedto5-square-inchFR4PCboardwithoneouncecopper wherenoted.Whenresistancerangeisgiven,lowervaluesarefor5-square-inchaluminumPCboard.TestPWBis0.062 inchesthickandtypicallyuses0.635mmtracewidthforpowerpackagesand1.3mmtracewidthsfornon-power packageswitha100x100milprobelandareaattheendofeachtrace. www.ti.com 5

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 FUNCTIONAL BLOCK DIAGRAM CLOCK 4 UC28025 RT 5 13 VC ToggleF/F OSCILLATOR CT 6 11 OUTA PWM 1.25V Latch T RAMP 7 + R 14 OUTB EAOUT 3 SD WideBandwidth 12 PGND ErrorAmplifier NI 2 + VIN 9μA INV 1 UC28023 Inhibit 13 VC 14 OUT SS 8 12 PGND 1V (UC28025Only) ILIM Comparator ILIMREF 11 (UC28023 Only) 1V Shutdown ILIM/SD 9 Comparator InternalBias 1.4V 16 VREF VCC 15 VCCGood REFGEN VREFGood 9V 4V GND 10 UVLO OutputInhibit UDG--03048 6 www.ti.com

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 TERMINAL FUNCTIONS TERMINAL NNAAMMEE II//OO DDEESSCCRRIIPPTTIIOONN UC28023 UC28025 CLOCK 4 4 O Outputoftheinternaloscillator Timingcapacitorconnectionpinforoscillatorfrequencyprogramming.Thetimingcapacitorshould CT 6 6 I beconnectedtothedevicegroundusingminimaltracelength. EAOUT 3 3 O Outputoftheerroramplifierforcompensation GND 10 10 -- Analoggroundreturnpin. ILIM/SD 9 9 I Inputtothecurrentlimitcomparatorandtheshutdowncomparator. ILIMREF 11 -- I Pintosetthecurrentlimitthresholdexternally. INV 1 1 I Invertinginputtotheerroramplifier NI 2 2 I Non-invertinginputtotheerroramplifier OUT 14 -- O Highcurrenttotempoleoutputoftheon-chipdrivestage. OUTA -- 11 O HighcurrenttotempoleoutputAoftheon-chipdrivestage. OUTB -- 14 O HighcurrenttotempoleoutputBoftheon-chipdrivestage. PGND 12 12 -- Groundreturnpinfortheoutputdriverstage Non-invertinginputtothePWMcomparatorwith1.25-Vinternalinputoffset.Involtagemode RAMP 7 7 I operationthisservesastheinputvoltagefeed-forwardfunctionbyusingtheCTramp.Inpeak currentmodeoperation,thisservesastheslopecompensationinput. RT 5 5 I Timingresistorconnectionpinforoscillatorfrequencyprogramming SS 8 8 I Soft-startinputpin. Powersupplypinfortheoutputstage.Thispinshouldbebypassedwitha0.1-μFmonolithic VC 13 13 -- ceramiclowESLcapacitorwithminimaltracelengths. Powersupplypinforthedevice.Thispinshouldbebypassedwitha0.1-μFmonolithicceramic VCC 15 15 -- lowESLcapacitorwithminimaltracelengths 5.1--Vreference.Forstability,thereferenceshouldbebypassedwitha0.1-μFmonolithicceramic VREF 16 16 O lowESLcapacitorandminimaltracelengthtothegroundplane. www.ti.com 7

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION + VIN VOUT5V 42Vto56V 12V 1Ato10A -- + 4.7μF 0.8μH 15V 15 13 VCC VC 0.1μF 16 VREF OUTB 14 6μF 1kΩ 1N5820 -- 1Ω 5:1 2 NI OUTA 11 10 4.3kΩ kΩ UC28025 4.7μF 1kΩ 1 INV ILIM/SD 9 1nF 22pF 3.3kΩ 3 EAOUT RAMP 7 8.2kΩ 1kΩ 10nF 4 CLOCK CT 6 120pF CT 470pF 5 RT PGND 12 GND SS 1.5kΩ 10 8 0.1μF UDG--03047 Figure1.TypicalApplication:1.5MHz,48-Vto5-VDC/DCPush-PullConverterUsingUC28025 8 www.ti.com

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION PCB LAYOUT CONSIDERATIONS High speed circuits demand careful attention to layout and component placement. To assure proper performanceoftheUC2802xfollowtheserules: 1. Useagroundplane. 2. DamporclampparasiticinductivekickenergyfromthegateofdrivenMOSFETs.Donotallowtheoutput pinstoringbelowground.Aseriesgateresistororashunt1-ASchottkydiodeattheoutputpinservesthis purpose. 3. Bypass VCC, VC, and VREF. Use 0.1-μF monolithic ceramic capacitors with low equivalent series inductance.Allowlessthan1-cmoftotalleadlengthforeachcapacitorbetweenthebypassedpinandthe groundplane. 4. Treatthetimingcapacitor,C ,asabypasscapacitor. T ERROR AMPLIFIER Figure 2 shows a simplified schematic of the UC2802x error amplifier and Figures 3 and 4 show its characteristics. 5.1V 16 VREF 3 EAOUT INV 1 200Ω NI 2 UDG--03049 Figure2.SimplifiedErrorAmplifierSchematic www.ti.com 9

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION GAINANDPHASE VOLTAGE vs vs FREQUENCY TIME 100 5 80 VIN VOUT V -- 60 GAIN age 4 olt V B40 ut d p -- ut 3 n O ai20 A G E/ -- -- AV 0 0 out A 2 E PHASE S V --20 --90 ° -- e s a --40 --180 Ph 1 100 1k 10k 100k 1M 10M 100M 0 0.2 0.4 0.6 0.8 1.0 fOSC--Frequency--Hz tdelay--DelayTime--μs Figure3.OpenLoopFrequencyResponse Figure4.UnityGainSlewRate CONTROL METHODS UC2802x UC2802x CT CT CT 6 OSCILLATOR ISENSE 6 OSCILLATOR RAMP 1.25V RAMP 1.25V 7 7 * * CT From RSENSE From ErrorAmplifier ErrorAmplifier UDG--03050 *Asmallfiltermayberequiredtosupressswitchnoise. UDG--03050 Figure5.VoltageModeControl Figure6.PeakCurrentModeControl 10 www.ti.com

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION OSCILLATOR DEADTIME vs TIMINGCAPACITANCE 10.0 IR RT UC2802x 3kΩ≤RT≤100kΩ 5 4.70 3V IC=IR CT 2.20 s μ 6 -- e m 1.00 Ti d 5.1V ea 0.47 D -- D T CLOCK 0.22 4 Blanking 0.10 TD 400μA 0.047 0.47 1.0 2.2 4.7 10.0 22.0 47 100 UDG--03052 CT--TimingCapacitance--nF Figure7.OscillatorCircuit Figure8. TIMINGRESISTANCE DEADTIME vs vs FREQUENCY FREQUENCY 100k 160 4.7nF 2.2nF Ω -- 140 e c 1nF n s a n sist e-- CT=1nF e 470pF m gR 10k Ti 120 n d mi ea Ti D R--T 100nF T--D CT=470pF 47nF 100 22nF 10nF 1k 80 100 1k 10k 100k 1M 10k 100k 1M fOSC--Frequency--Hz fOSC--Frequency--Hz Figure9.OscillatorCircuit Figure10. www.ti.com 11

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION SYNCHRONIZATION Figure11showsageneralizedsynchronization.Figure12showsasynchronozedoperationoftwounitsinclose proximity. UC2802x UC2802x (Master) (Slave) VREF 16 RT 10μF 1.15Ω 5 RT 2N222 CLOCK 4 43Ω 0.1μF RT RT 5 24Ω CT 43Ω 0.1μF CT 6 CT CT 6 Toother 43Ω 0.1μF slaves 24Ω Local Local 470Ω Ramp Ramp UDG--03050 Figure11.GeneralizedSynchronization UC2802x UC2802x (Master) (Slave) CLOCK 4 4 CLOCK 16 VREF RT RT 5 5 RT Local CT 6 6 CT Ramp CT UDG--03050 Figure12.SynchronizationofTwoUnitsInClose Proximity 12 www.ti.com

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION FEEDFORWARD CIRCUIT VIN UC2802x RFF 7 RAMP CFF 4 CLOCK 6 CT 5 RT UDG--03050 Figure13.FeedforwardTechniqueforOff-LineVoltage-ModeApplications CONSTANT VOLT-SECOND CLAMP CIRCUIT ThecircuitfortheUC28023showninFigure14describesachievementaconstantvolt-secondproductclamp overvaryinginputvoltages.Therampgeneratorcomponents,R andC arechosensothattherampatPin T R 9(ILIM/SD)crossesthe1-Vthresholdatthesametimethedesiredmaximumvolt-secondproductisreached. The delay through the functional inverter block must be such that the ramp capacitor can be completely dischargedduringtheminimumdeadtime. UC28023 VIN OUT RT 14 ILIM/SD 9 CR UDG--03050 Figure14.AchievingConstantVolt-SecondProductClampwiththeUC28023 www.ti.com 13

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 ThecircuitfortheUC28025showninFigure15describesachievementaconstantvolt-secondproductclamp overvaryinginputvoltages.Therampgeneratorcomponents,R andC arechosensothattherampatPin T R 9(ILIM/SD)crossesthe1-Vthresholdatthesametimethedesiredmaximumvolt-secondproductisreached. The delay through the functional inverter block must be such that the ramp capacitor can be completely dischargedduringtheminimumdeadtime. UC28025 VIN OUTB RT 14 ILIM/SD 9 OUTA 11 CR UDG--03050 Figure15.AchievingConstantVolt-SecondProductClampwiththeUC28025 14 www.ti.com

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION OUTPUTS UC28023hasoneoutputandUC28025hasdualalternatingoutputs. SATURATIONVOLTAGE vs UC2802x OUTPUTCURRENT 3 15 VCC 13 VC V -- e 2 g a olt Source V n o OUTx rati u Sat 1 -- T A S V 12 PWRGND Sink 10 GND 0 0 0.25 0.50 0.75 1.00 1.25 1.50 IOUT--Output Current--A Figure16.SimplifiedSchematic Figure17. RISE/FALLTIME RISE/FALLTIME vs vs OUTPUTVOLTAGEANDLOADCURRENT OUTPUTVOLTAGEANDLOADCURRENT A A 0.2 -- 0.2 -- CLOAD=1nF nt CLOAD=10nF nt e e urr urr C C 0 d 0 d a a o o L L -- -- D D 15 --0.2 A 15 --0.2 A V LO V LO -- I -- I e e g g olta 10 olta 10 V V ut ut p p ut ut O 5 O 5 -- -- T T U U O O V V 0 0 0 40 80 120 160 200 0 100 200 300 400 500 tRISE(tFALL)--Time--ns tRISE(tFALL)--Time--ns Figure18. Figure19. www.ti.com 15

UC28023 UC28025 SLUS557F--MARCH2003--REVISEDAUGUST2010 APPLICATION INFORMATION Open Loop Laboratory Test Fixture The following test fixture is useful for exercising many of the UC28025’s functions and measuring their specifications.Aswithanywidebandcircuit,carefulgroundandby-passproceduresshouldbefollowed.The useofagroundplaneishighlyrecommended. UC28025 15V 0.1μF 4 CLOCK VCC 15 RT 3.65kΩ 15V 5 RT OSCILLATOR VC 13 10uF CT 1.0nF 0.1μF 10μF 6 CT 200Ω OUTA 11 7 RAMP 3 EAOUT OUTB14 27kΩ 50Ω 68kΩ 1N5820 ERROR 1N5820 4.7kΩ 10kΩ AMPLIFIER 2 NI PGND 12 22kΩ 1 INV 27kΩ GND 10 4.7kΩ 8 SS 0.1μF 10μF 10kΩ VREF 16 9 ILIM/SD 3.3kΩ UDG--03051 Figure20.LaboratoryTestFixture References 1. 1.5-MHzCurrentModeICControlled50--WattPowerSupply,TexasInstrumentsApplicationNoteLiterature No.SLUA053. 2. The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, Texas Instruments ApplicationNoteLiteratureNo.SLUA125. Revision History Rev E to Rev F 1. UpdatedTypicalApplicationDiagram,Figure1,page8. 16 www.ti.com

PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UC28023DW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW & no Sb/Br) UC28023DWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW & no Sb/Br) UC28023DWR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW & no Sb/Br) UC28023DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28023DW & no Sb/Br) UC28023N OBSOLETE PDIP N 16 TBD Call TI Call TI -40 to 105 UC28023N UC28025DW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW & no Sb/Br) UC28025DWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW & no Sb/Br) UC28025DWR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW & no Sb/Br) UC28025DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 UC28025DW & no Sb/Br) UC28025N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 105 UC28025N & no Sb/Br) UC28025NG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 105 UC28025N & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2016 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

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