TSU101, TSU102, TSU104 Nanopower, rail-to-rail input and output, 5 V CMOS operational amplifiers Datasheet - production data Benefits • 42 years of typical equivalent lifetime (for TSU101) if supplied by a 220 mAh coin type Lithium battery • Tolerance to power supply transient drops • Accurate signal conditioning of high impedance sensors • Application performances guaranteed over industrial temperature range • Fast desaturation Applications • Ultra long life battery-powered applications • Power metering • UV and photo sensors • Electrochemical and gas sensors • Pyroelectric passive infrared (PIR) detection • Battery current sensing • Medical instrumentation Features • RFID readers • Submicro ampere current consumption: Description 580 nA typ per channel at 25 °C at V = 1.8 V The TSU101, TSU102, and TSU104 operational CC • Low supply voltage: 1.5 V - 5.5 V amplifiers offer an ultra low-power consumption • Unity gain stable of 580 nA typical and 750 nA maximum per • Rail-to-rail input and output channel when supplied by 1.8 V. Combined with • Gain bandwidth product: 8 kHz typ a supply voltage range of 1.5 V to 5.5 V, these features allow the TSU10x series to be efficiently • Low input bias current: 5 pA max at 25 °C supplied by a coin type Lithium battery or a • High tolerance to ESD: 2 kV HBM regulated voltage in low-power applications. • Industrial temperature range: -40 °C to 85 °C The 8 kHz gain bandwidth of these devices make them ideal for sensor signal conditioning, battery supplied, and portable applications. September 2015 DocID024317 Rev 3 1/33 This is information on a product in full production. www.st.com

Contents TSU101, TSU102, TSU104 Contents 1 Package pin connections ................................................................ 3 2 Absolute maximum ratings and operating conditions ................. 4 3 Electrical characteristics ................................................................ 5 4 Application information ................................................................ 17 4.1 Operating voltages .......................................................................... 17 4.2 Rail-to-rail input ............................................................................... 17 4.3 Input offset voltage drift over temperature ....................................... 17 4.4 Long term input offset voltage drift .................................................. 18 4.5 Schematic optimization aiming for nanopower ................................ 19 4.6 PCB layout considerations .............................................................. 20 4.7 Using the TSU10x series with sensors ............................................ 20 4.8 Fast desaturation ............................................................................ 22 4.9 Using the TSU10x series in comparator mode ................................ 22 4.10 ESD structure of TSU10x series ..................................................... 22 5 Package information ..................................................................... 23 5.1 SC70-5 (or SOT323-5) package information ................................... 24 5.2 SOT23-5 package information ........................................................ 25 5.3 DFN8 2x2 package information ....................................................... 26 5.4 MiniSO8 package information ......................................................... 27 5.5 QFN16 3x3 package information ..................................................... 28 5.6 TSSOP14 package information ....................................................... 30 6 Ordering information ..................................................................... 31 7 Revision history ............................................................................ 32 2/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Package pin connections 1 Package pin connections Figure 1: Pin connections for each package (top view) DocID024317 Rev 3 3/33

Absolute maximum ratings and operating TSU101, TSU102, TSU104 conditions 2 Absolute maximum ratings and operating conditions Table 1: Absolute maximum ratings (AMR) Symbol Parameter Value Unit VCC Supply voltage (1) 6 Vid Differential input voltage (2) ±VCC V Vin Input voltage (3) (VCC-) - 0.2 to (VCC+) + 0.2 Iin Input current (4) 10 mA Tstg Storage temperature -65 to 150 °C Tj Maximum junction temperature 150 SC70-5 205 SOT23-5 250 Thermal resistance junction to DFN8 2x2 117 Rthja ambient (5)(6) MiniSO8 190 °C/W QFN16 3x3 45 TSSOP14 100 HBM: human body model (7) 2000 MM: machine model (8) 200 ESD All other packages V 1000 CDM: charged device model (9) except SC70-5 SC70-5 900 Latch-up immunity (10) 200 mA Notes: (1)All voltage values, except the differential voltage are with respect to the network ground terminal. (2)The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. (3)((VCC+) - Vin) must not exceed 6 V, (Vin - VCC-) must not exceed 6 V. (4)The input current must be limited by a resistor in series with the inputs. (5)Rth are typical values. (6)Short-circuits can cause excessive heating and destructive dissipation. (7)Related to ESDA/JEDEC JS-001 Apr. 2010 (8)Related to JEDEC JESD22-A115C Nov.2010 (9)Related to JEDEC JESD22-C101-E Dec. 2009 (10)Related to JEDEC JESD78C Sept. 2010 Table 2: Operating conditions Symbol Parameter Value Unit VCC Supply voltage 1.5 to 5.5 V Vicm Common mode input voltage range (VCC-) - 0.1 to (VCC+) + 0.1 Toper Operating free air temperature range -40 to 85 °C 4/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Electrical characteristics 3 Electrical characteristics Table 3: Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance -3 0.1 3 Vio Input offset voltage mV -40 °C < T< 85 °C -3.4 3.4 ΔVio/ΔT Input offset voltage drift -40 °C < T< 85 °C 5 μV/°C ΔVio Lvoolntagg-tee rdmri fitn put offset T = 25 °C (1) 0.18 √mµoVn/ th 1 5 Iio Input offset current (2) -40 °C < T< 85 °C 30 pA 1 5 Iib Input bias current (2) -40 °C < T< 85 °C 30 Vicm = 0 to 0.6 V, Vout = VCC/2 65 85 Common mode rejection -40 °C < T< 85 °C 65 CMR ratio 20 log (ΔVicm/ΔVio) Vicm = 0 to 1.8 V, Vout = VCC/2 55 74 -40 °C < T< 85 °C 55 dB Vout = 0.3 V to ((VCC+) - 0.3 V), 95 115 Avd Large signal voltage gain RL = 100 kΩ -40 °C < T< 85 °C 95 High level output voltage, RL = 100 kΩ 40 VOH (drop from VCC+) -40 °C < T< 85 °C 40 mV RL = 100 kΩ 40 VOL Low level output voltage -40 °C < T< 85 °C 40 Vout = VCC , VID = -200 mV 4 5 Output sink current -40 °C < T< 85 °C 4 Iout mA Vout = 0 V, VID = 200 mV 4 5 Output source current -40 °C < T< 85 °C 4 Supply current, No load, Vout = VCC/2 580 750 ICC (per channel) -40 °C < T< 85 °C 800 nA AC performance GBP Gain bandwidth product 8 kHz Fu Unity gain frequency 8 RL = 1 MΩ, CL = 60 pF ϕm Phase margin 60 Degrees Gm Gain margin 10 dB RL = 1 MΩ, CL = 60 pF SR Slew rate (10 % to 90 %) 3 V/ms Vout = 0.3 V to ((VCC+) - 0.3 V) Equivalent input noise f = 100 Hz 265 en voltage f = 1 kHz 265 nV/√Hz DocID024317 Rev 3 5/33

Electrical characteristics TSU101, TSU102, TSU104 Symbol Parameter Conditions Min. Typ. Max. Unit Low-frequency peak-to- ∫en peak input noise Bandwidth: f = 0.1 to 10 Hz 9 µVpp Equivalent input noise f = 100 Hz 0.64 in current f = 1 kHz 4.4 fA/√Hz 100 mV from rail in comparator, trec Overload recovery time RL = 100 kΩ, VID = ±VCC, 30 µs -40 °C < T< 85 °C Notes: (1) Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. (2)Guaranteed by design. 6/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Electrical characteristics Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance -3 0.1 3 Vio Input offset voltage mV -40 °C < T< 85 °C -3.4 3.4 ΔVio/ΔT Input offset voltage drift -40 °C < T< 85 °C 5 μV/°C ΔVio Lvoolntagg-tee rdmri fitn put offset T = 25 °C (1) 0.36 √mµoVn/ th 1 5 Iio Input offset current (2) -40 °C < T< 85 °C 30 pA 1 5 Iib Input bias current (2) -40 °C < T< 85 °C 30 Vicm = 0 to 2.1 V, Vout = VCC/2 70 92 Common mode rejection -40 °C < T< 85 °C 70 CMR ratio 20 log (ΔVicm/ΔVio) Vicm = 0 to 3.3 V, Vout = VCC/2 60 77 -40 °C < T< 85 °C 60 dB Vout = 0.3 V to ((VCC+) - 0.3 V), 105 120 Avd Large signal voltage gain RL= 100 kΩ -40 °C < T< 85 °C 105 High level output voltage RL = 100 kΩ 40 VOH (drop from VCC+) -40 °C < T< 85 °C 40 mV RL = 100 kΩ 40 VOL Low level output voltage -40 °C < T< 85 °C 40 Vout = VCC , VID = -200 mV 6 9 Output sink current -40 °C < T< 85 °C 6 Iout mA Vout = 0 V, VID = 200 mV 8 11 Output source current -40 °C < T< 85 °C 8 Supply current, No load, Vout = VCC/2 600 800 ICC (per channel) -40 °C < T< 85 °C 850 nA AC performance GBP Gain bandwidth product 8 kHz Fu Unity gain frequency 8 RL = 1 MΩ, CL = 60 pF ϕm Phase margin 60 Degrees Gm Gain margin 11 dB SR Slew rate (10 % to 90 %) RL = 1 MΩ, CL = 60 pF, 3 V/ms Vout = 0.3 V to ((VCC+) - 0.3 V) Equivalent input noise f = 100 Hz 260 en voltage f = 1 kHz 255 nV/√Hz Low-frequency peak-to- ∫en peak input noise Bandwidth: f = 0.1 to 10 Hz 8.6 µVpp DocID024317 Rev 3 7/33

Electrical characteristics TSU101, TSU102, TSU104 Symbol Parameter Conditions Min. Typ. Max. Unit Equivalent input noise f = 100 Hz 0.55 in current f = 1 kHz 3.8 fA/√Hz 100 mV from rail in comparator, trec Overload recovery time RL = 100 kΩ, VID = ±VCC, 30 µs -40 °C < T< 85 °C Notes: (1) Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. (2)Guaranteed by design. 8/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Electrical characteristics Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance -3 0.1 3 Vio Input offset voltage mV -40 °C < T< 85 °C -3.4 3.4 ΔVio/ΔT Input offset voltage drift -40 °C < T< 85 °C 5 μV/°C ΔVio Lvoolntagg-tee rdmri fitn put offset T = 25 °C (1) 1.1 √mµoVn/ th 1 5 Iio Input offset current (2) -40 °C < T< 85 °C 30 pA 1 5 Iib Input bias current (2) -40 °C < T< 85 °C 30 Vicm = 0 to 3.8 V, Vout = VCC/2 70 90 Common mode rejection -40 °C < T< 85 °C 70 CMR ratio 20 log (ΔVicm/ΔVio) Vicm = 0 to 5 V, Vout = VCC/2 65 82 -40 °C < T< 85 °C 65 Supply voltage rejection VCC = 1.5 to 5.5 V, Vicm = 0 V 70 90 dB SVR ratio -40 °C < T< 85 °C 70 Vout = 0.3 V to ((Vcc+) - 0.3 V), 110 130 Avd Large signal voltage gain RL= 100 kΩ -40 °C < T< 85 °C 110 High level output voltage, RL = 100 kΩ 40 VOH (drop from VCC+) -40 °C < T< 85 °C 40 mV RL = 100 kΩ 40 VOL Low level output voltage -40 °C < T< 85 °C 40 Vout = VCC , VID = -200 mV 6 9 Output sink current -40 °C < T< 85 °C 6 Iout mA Vout = 0 V, VID = 200 mV 8 11 Output source current -40 °C < T< 85 °C 8 Supply current, No load, Vout = VCC/2 650 850 nA ICC (per channel) -40 °C < T< 85 °C 950 AC performance GBP Gain bandwidth product 9 kHz Fu Unity gain frequency 8.6 RL = 1 MΩ, CL = 60 pF ϕm Phase margin 60 Degrees Gm Gain margin 12 dB SR Slew rate (10 % to 90 %) RL = 1 MΩ, CL = 60 pF, 3 V/ms Vout = 0.3 V to ((VCC+) - 0.3 V) Equivalent input noise f = 100 Hz 240 en voltage f = 1 kHz 225 nV√Hz DocID024317 Rev 3 9/33

Electrical characteristics TSU101, TSU102, TSU104 Symbol Parameter Conditions Min. Typ. Max. Unit Low-frequency ∫en Bandwidth: f = 0.1 to 10 Hz 8.1 µVpp peak-to-peak input noise Equivalent input noise f = 100 Hz 0.18 in current f = 1 kHz 3.5 fA√Hz 100 mV from rail in comparator, trec Overload recovery time RL = 100 kΩ, VID = ±VCC, 30 µs -40 °C < T< 85 °C Vin = -10 dBm, f = 400 MHz 73 Electromagnetic Vin = -10 dBm, f = 900 MHz 88 EMIRR interference rejection dB ratio (3) Vin = -10 dBm, f = 1.8 GHz 80 Vin = -10 dBm, f = 2.4 GHz 80 Notes: (1) Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. (2)Guaranteed by design. (3)Based on evaluations performed only in conductive mode. 10/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Electrical characteristics Figure 2: Supply current vs. supply voltage Figure 3: Supply current vs. input common mode voltage Figure 4: Supply current in saturation mode Figure 5: Input offset voltage distribution 11..00 0.9 Temperature 00..88 85°C/65°C/45°C/25°C/-5°C/-40°C 0.7 A) 00..66 µ c ( 0.5 c I 00..44 0.3 Vcc=3.3V 00..22 Followerconfiguration 0.1 00..00 00252550507575100100125125150150175175 100100125125150150175175200200225225250250275275300300 333333333333333333 Inputvoltage(mV) Figure 6: Input offset voltage vs common mode voltage Figure 7: Input offset voltage vs temperature at 3.3 V supply voltage DocID024317 Rev 3 11/33

Electrical characteristics TSU101, TSU102, TSU104 Figure 8: Input offset voltage temperature coefficient Figure 9: Input bias current vs. temperature at distribution mid VICM Figure 10: Input bias current vs. temperature at Figure 11: Input bias current vs. temperature at low VICM high VICM Figure 12: Output characteristics at 1.8 V supply voltage Figure 13: Output characteristics at 3.3 V supply voltage 12/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Electrical characteristics Figure 14: Output characteristics at 5 V supply voltage Figure 15: Output voltage vs. input voltage close to the rails 33330000 33227755 33225500 Temperature 33222255 85°C/65°C/45°C/25°C/-5°C/-40°C 33220000 mV)3333111155770055 e(33112255 ag33110000 volt 117755 ut 115500 Outp 111100220055 Vcc=3.3V 7755 Followerconfiguration 5500 2255 00 0055005500550055 005500550055005500 2255771010121215151717 101012121515171720202222252527273030 333333333333333333 Inputvoltage(mV) Figure 16: Output saturation with a sine wave on input Figure 17: Desaturation time Figure 18: Phase reversal free Figure 19: Slew rate vs. supply voltage DocID024317 Rev 3 13/33

Electrical characteristics TSU101, TSU102, TSU104 Figure 20: Output swing vs. input signal frequency Figure 21: Triangulation of a sine wave Figure 22: Large signal response at 3.3 V supply Figure 23: Small signal response at 3.3 V supply voltage voltage Figure 24: Overshoot vs. capacitive load at 3.3 V supply Figure 25: Phase margin vs. capacitive load at 3.3 V voltage supply voltage 14/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Electrical characteristics Figure 26: Bode diagram for different feedback values Figure 27: Bode diagram at 1.8 V supply voltage Figure 28: Bode diagram at 3.3 V supply voltage Figure 29: Bode diagram at 5 V supply voltage Figure 30: Gain bandwidth product vs. input common Figure 31: In-series resistor (Riso) vs. capacitive load mode voltage DocID024317 Rev 3 15/33

Electrical characteristics TSU101, TSU102, TSU104 Figure 32: Noise at 1.8 V supply voltage in follower Figure 33: Noise at 3.3 V supply voltage in follower configuration configuration Figure 34: Noise at 5 V supply voltage in follower Figure 35: Noise amplitude on 0.1 to 10 Hz frequency configuration range Figure 36: Channel separation on TSU102 Figure 37: Channel separation on TSU104 16/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Application information 4 Application information 4.1 Operating voltages The TSU101, TSU102, and TSU104 series of amplifiers can operate from 1.5 V to 5.5 V. Their parameters are fully specified at 1.8 V, 3.3 V, and 5 V supply voltages and are very stable in the full V range. Additionally, main specifications are guaranteed on the CC industrial temperature range from -40 to 85 ° C. 4.2 Rail-to-rail input The TSU101, TSU102, and TSU104 series is built with two complementary PMOS and NMOS input differential pairs. Thus, these devices have a rail-to-rail input, and the input common mode range is extended from (V ) - 0.1 V to (V ) + 0.1 V. CC- CC+ The devices have been designed to prevent phase reversal behavior. 4.3 Input offset voltage drift over temperature The maximum input voltage drift over the temperature variation is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effects of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 ∆Vio = maxVio(T)–Vio(25°C) ∆T T–25°C with T = -40 °C and 85 °C. The datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a C (process capability index) greater than 2. pk DocID024317 Rev 3 17/33

Application information TSU101, TSU102, TSU104 4.4 Long term input offset voltage drift To evaluate product reliability, two types of stress acceleration are used: • Voltage acceleration, by changing the applied voltage • Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 β.(V –V ) A = e S U FV Where: A is the voltage acceleration factor FV b is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) V is the stress voltage used for the accelerated test S V is the voltage used for the application U The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 E-----a- . 1 – 1 k T T A = e U S FT Where: A is the temperature acceleration factor FT E is the activation energy of the technology based on the failure rate a k is the Boltzmann constant (8.6173 x 10-5 eVk-1) T is the temperature of the die when V is used (°K) U U T is the temperature of the die under temperature stress (°K) S The final acceleration factor, A , is the multiplication of the voltage acceleration factor and F the temperature acceleration factor (Equation 4). Equation 4 A = A × A F FT FV A is calculated using the temperature and voltage defined in the mission profile of the F product. The A value can then be used in Equation 5 to calculate the number of months of F use equivalent to 1000 hours of reliable stress duration. Equation 5 Months = A ×1000h×12months/(24h×365.25days) F 18/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Application information To evaluate the op-amp reliability, a follower stress condition is used where V is defined CC as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The V drift (in µV) of the product after 1000 h of stress is tracked with parameters at io different measurement conditions (see Equation 6). Equation 6 V = maxV withV = V /2 CC op icm CC The long term drift parameter (ΔV ), estimating the reliability performance of the product, is io obtained using the ratio of the V (input offset voltage value) drift over the square root of io the calculated number of months (Equation 7). Equation 7 V drift io ∆V = io (months) where V drift is the measured drift value in the specified test conditions after 1000 h stress io duration. 4.5 Schematic optimization aiming for nanopower To benefit from the full performance of the TSU10 series, the impedances must be maximized so that current consumption is not lost where it is not required. For example, an aluminum electrolytic capacitance can have significantly high leakage. This leakage may be greater than the current consumption of the op-amp. For this reason, ceramic type capacitors are preferred. For the same reason, big resistor values should be used in the feedback loop. However, there are three main limitations to be considered when choosing a resistor. 1. When the TSU10x series is used with a sensor: the resistance connected between the sensor and the input must remain much higher than the impedance of the sensor itself. 2. Noise generated: a 100 kΩ resistor generates 40 nV/√Hz, a bigger resistor value generates even more noise. 3. Leakage on the PCB: leakage can be generated by moisture. This can be improved by using a specific coating process on the PCB. DocID024317 Rev 3 19/33

Application information TSU101, TSU102, TSU104 4.6 PCB layout considerations For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins. Minimizing the leakage from sensitive high impedance nodes on the inputs of the TSU10x series can be performed with a guarding technique. The technique consists of surrounding high impedance tracks by a low impedance track (the ring). The ring is at the same electrical potential as the high impedance node. Therefore, even if some parasitic impedance exists between the tracks, no leakage current can flow through them as they are at the same potential (see Figure 38: "Guarding on the PCB"). Figure 38: Guarding on the PCB 4.7 Using the TSU10x series with sensors The TSU10x series has MOS inputs, thus input bias currents can be guaranteed down to 5 pA maximum at ambient temperature. This is an important parameter when the operational amplifier is used in combination with high impedance sensors. The TSU101, TSU102, and TSU104 series is perfectly suited for trans-impedance configuration as shown in Figure 39: "Trans-impedance amplifier schematic". This configuration allows a current to be converted into a voltage value with a gain set by the user. It is an ideal choice for portable electrochemical gas sensing or photo/UV sensing applications. The TSU10x series, using trans-impedance configuration, is able to provide a voltage value based on the physical parameter sensed by the sensor. 20/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Application information Electrochemical gas sensors The output current of electrochemical gas sensors is generally in the range of tens of nA to hundreds of µA. As the input bias current of the TSU101, TSU102, and TSU104 is very low (see Figure 9, Figure 10, and Figure 11) compared to these current values, the TSU10x series is well adapted for use with the electrochemical sensors of two or three electrodes. Figure 40: "Potentiostat schematic using the TSU101 (or TSU102)" shows a potentiostat (electronic hardware required to control a three-electrode cell) schematic using the TSU101, TSU102, and TSU104. In such a configuration, the devices minimize leakage in the reference electrode compared to the current being measured on the working electrode. Figure 39: Trans-impedance amplifier schematic Figure 40: Potentiostat schematic using the TSU101 (or TSU102) DocID024317 Rev 3 21/33

Application information TSU101, TSU102, TSU104 4.8 Fast desaturation When the TSU101, TSU102, and TSU104 operational amplifiers go into saturation mode, they take a short period of time to recover, typically thirty microseconds. When recovering after saturation, the TSU10x series does not exhibit any voltage peaks that could generate issues (such as false alarms) in the application (see Figure 17). This is because the internal gain of the amplifier decreases smoothly when the output signal gets close to the V or V supply rails (see Figure 15 and Figure 16). CC+ CC- Thus, to maintain signal integrity, the user should take care that the output signal stays at 100 mV from the supply rails. With a trans-impedance schematic, a voltage reference can be used to keep the signal away from the supply rails. 4.9 Using the TSU10x series in comparator mode The TSU10x series can be used as a comparator. In this case, the output stage of the device always operates in saturation mode. In addition, Figure 4 shows the current consumption is not bigger and even decreases smoothly close to the rails. The TSU101, TSU102, and TSU104 are obviously operational amplifiers and are therefore optimized to be used in linear mode. We recommend to use the TS88 series of nanopower comparators if the primary function is to perform a signal comparison only. 4.10 ESD structure of TSU10x series The TSU101, TSU102, and TSU104 are protected against electrostatic discharge (ESD) with dedicated diodes (see Figure 41: "ESD structure"). These diodes must be considered at application level especially when signals applied on the input pins go beyond the power supply rails (V or V ). CC+ CC- Figure 41: ESD structure Current through the diodes must be limited to a maximum of 10 mA as stated in Table 1: "Absolute maximum ratings (AMR)". A serial resistor or a Schottky diode can be used on the inputs to improve protection but the 10 mA limit of input current must be strictly observed. 22/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Package information 5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID024317 Rev 3 23/33

Package information TSU101, TSU102, TSU104 5.1 SC70-5 (or SOT323-5) package information Figure 42: SC70-5 (or SOT323-5) package outline SIDE VIEW DIMENSIONS IN MM GAUGE PLANE COPLANAR LEADS SEATING PLANE TOP VIEW Table 6: SC70-5 (or SOT323-5) mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.80 1.10 0.315 0.043 A1 0.10 0.004 A2 0.80 0.90 1.00 0.315 0.035 0.039 b 0.15 0.30 0.006 0.012 c 0.10 0.22 0.004 0.009 D 1.80 2.00 2.20 0.071 0.079 0.087 E 1.80 2.10 2.40 0.071 0.083 0.094 E1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65 0.025 e1 1.30 0.051 L 0.26 0.36 0.46 0.010 0.014 0.018 < 0° 8° 0° 8° 24/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Package information 5.2 SOT23-5 package information Figure 43: SOT23-5 package outline Table 7: SOT23-5 mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.90 1.20 1.45 0.035 0.047 0.057 A1 0.15 0.006 A2 0.90 1.05 1.30 0.035 0.041 0.051 B 0.35 0.40 0.50 0.014 0.016 0.020 C 0.09 0.15 0.20 0.004 0.006 0.008 D 2.80 2.90 3.00 0.110 0.114 0.118 D1 1.90 0.075 e 0.95 0.037 E 2.60 2.80 3.00 0.102 0.110 0.118 F 1.50 1.60 1.75 0.059 0.063 0.069 L 0.10 0.35 0.60 0.004 0.014 0.024 K 0 degrees 10 degrees 0 degrees 10 degrees DocID024317 Rev 3 25/33

Package information TSU101, TSU102, TSU104 5.3 DFN8 2x2 package information Figure 44: DFN8 2x2 package outline Table 8: DFN8 2x2 mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 2.00 0.079 E 2.00 0.079 e 0.50 0.020 L 0.045 0.55 0.65 0.018 0.022 0.026 N 8 26/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Package information 5.4 MiniSO8 package information Figure 45: MiniSO8 package outline Table 9: MiniSO8 mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.1 0.043 A1 0 0.15 0 0.006 A2 0.75 0.85 0.95 0.030 0.033 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 e 0.65 0.026 L 0.40 0.60 0.80 0.016 0.024 0.031 L1 0.95 0.037 L2 0.25 0.010 k 0° 8° 0° 8° ccc 0.10 0.004 DocID024317 Rev 3 27/33

Package information TSU101, TSU102, TSU104 5.5 QFN16 3x3 package information Figure 46: QFN16 3x3 mm package outline The exposed pad is not internally connected and can be set to ground. 28/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Package information Table 10: QFN16 3x3 mm mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0 0.05 0 0.002 A3 0.20 0.008 b 0.18 0.30 0.007 0.012 D 2.90 3.00 3.10 0.114 0.118 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.00 3.10 0.114 0.118 0.122 E2 1.50 1.80 0.059 0.071 e 0.50 0.020 L 0.30 0.50 0.012 0.020 Figure 47: QFN16 3x3 mm recommended footprint DocID024317 Rev 3 29/33

Package information TSU101, TSU102, TSU104 5.6 TSSOP14 package information Figure 48: TSSOP14 package outline Table 11: TSSOP14 mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.20 0.047 A1 0.05 0.15 0.002 0.004 0.006 A2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.90 5.00 5.10 0.193 0.197 0.201 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.169 0.173 0.176 e 0.65 0.0256 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 0.039 k 0° 8° 0° 8° aaa 0.10 0.004 30/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 Ordering information 6 Ordering information Table 12: Order codes Order code Temperature range Package Packing Marking TSU101ICT SC70-5 K22 TSU101ILT SΟΤ23-5 K160 TSU101RICT SC70-5 K24 TSU101RILT SΟΤ23-5 K169 -40 °C to 85 °C Tape and reel TSU102IQ2T DFN8 2x2 K24 TSU102IST MiniSO8 K160 TSU104IQ4T QFN16 3x3 K160 TSU104IPT TSSOP14 TSU104I DocID024317 Rev 3 31/33

Revision history TSU101, TSU102, TSU104 7 Revision history Table 13: Document revision history Date Revision Changes 16-Apr-2013 1 Initial release Added the TSU102 and TSU104 devices and updated the datasheet accordingly. Added the silhouettes, pin connections, and package 02-Jul-2013 2 information for DFN8 2x2, MiniSO8, QFN16 3x3, and TSSOP14. Added Figure 36 and Figure 37 Updated title of Figure 31 04-Sep-2015 3 Replaced QFN16 3x3 package information (outline, mechanical data, and footprint). 32/33 DocID024317 Rev 3

TSU101, TSU102, TSU104 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID024317 Rev 3 33/33

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: S TMicroelectronics: TSU101ICT TSU101ILT TSU101RICT TSU101RILT TSU102IQ2T TSU102IST TSU104IPT TSU104IQ4T